diff --git a/bsp/board/bl602_iot/bl602_config.h b/bsp/board/bl602_iot/bl602_config.h new file mode 100644 index 00000000..e73ab663 --- /dev/null +++ b/bsp/board/bl602_iot/bl602_config.h @@ -0,0 +1,30 @@ +/** + * @file bl602_config.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef __BL702_CONFIG_H__ +#define __BL702_CONFIG_H__ + +#include "peripheral_config.h" +#include "clock_config.h" + +#endif \ No newline at end of file diff --git a/bsp/board/bl602_iot/board.c b/bsp/board/bl602_iot/board.c new file mode 100644 index 00000000..5998f217 --- /dev/null +++ b/bsp/board/bl602_iot/board.c @@ -0,0 +1,226 @@ +/** + * @file board.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "hal_gpio.h" +#include "hal_clock.h" +#include "bl602_glb.h" +#include "pinmux_config.h" + +struct pin_mux_cfg +{ + uint8_t pin; + uint16_t func; +}; + +static const struct pin_mux_cfg af_pin_table[] = +{ + { + .pin = GPIO_PIN_0, + .func = CONFIG_GPIO0_FUNC + }, + { + .pin = GPIO_PIN_1, + .func = CONFIG_GPIO1_FUNC + }, + { + .pin = GPIO_PIN_2, + .func = CONFIG_GPIO2_FUNC + }, + { + .pin = GPIO_PIN_3, + .func = CONFIG_GPIO3_FUNC + }, + { + .pin = GPIO_PIN_4, + .func = CONFIG_GPIO4_FUNC + }, + { + .pin = GPIO_PIN_5, + .func = CONFIG_GPIO5_FUNC + }, + { + .pin = GPIO_PIN_6, + .func = CONFIG_GPIO6_FUNC + }, + { + .pin = GPIO_PIN_7, + .func = CONFIG_GPIO7_FUNC + }, + { + .pin = GPIO_PIN_8, + .func = CONFIG_GPIO8_FUNC + }, + { + .pin = GPIO_PIN_9, + .func = CONFIG_GPIO9_FUNC + }, + { + .pin = GPIO_PIN_10, + .func = CONFIG_GPIO10_FUNC + }, + { + .pin = GPIO_PIN_11, + .func = CONFIG_GPIO11_FUNC + }, + { + .pin = GPIO_PIN_12, + .func = CONFIG_GPIO12_FUNC + }, + { + .pin = GPIO_PIN_13, + .func = CONFIG_GPIO13_FUNC + }, + { + .pin = GPIO_PIN_14, + .func = CONFIG_GPIO14_FUNC + }, + { + .pin = GPIO_PIN_15, + .func = CONFIG_GPIO15_FUNC + }, + { + .pin = GPIO_PIN_16, + .func = CONFIG_GPIO16_FUNC + }, + { + .pin = GPIO_PIN_17, + .func = CONFIG_GPIO17_FUNC + }, + { + .pin = GPIO_PIN_18, + .func = CONFIG_GPIO18_FUNC + }, + { + .pin = GPIO_PIN_19, + .func = CONFIG_GPIO19_FUNC + }, + { + .pin = GPIO_PIN_20, + .func = CONFIG_GPIO20_FUNC + }, + { + .pin = GPIO_PIN_21, + .func = CONFIG_GPIO21_FUNC + }, + { + .pin = GPIO_PIN_22, + .func = CONFIG_GPIO22_FUNC + }, + { + .pin = GPIO_PIN_23, + .func = CONFIG_GPIO23_FUNC + }, + { + .pin = GPIO_PIN_24, + .func = CONFIG_GPIO24_FUNC + }, + { + .pin = GPIO_PIN_25, + .func = CONFIG_GPIO25_FUNC + }, + { + .pin = GPIO_PIN_26, + .func = CONFIG_GPIO26_FUNC + }, + { + .pin = GPIO_PIN_27, + .func = CONFIG_GPIO27_FUNC + }, + { + .pin = GPIO_PIN_28, + .func = CONFIG_GPIO28_FUNC + }, +}; + +static void board_pin_mux_init(void) +{ + GLB_GPIO_Cfg_Type gpio_cfg; + + gpio_cfg.drive = 0; + gpio_cfg.smtCtrl = 1; + + for (int i = 0; i < sizeof(af_pin_table)/sizeof(af_pin_table[0]); i++) + { + gpio_cfg.gpioMode = GPIO_MODE_AF; + gpio_cfg.pullType = GPIO_PULL_UP; + gpio_cfg.gpioPin = af_pin_table[i].pin; + gpio_cfg.gpioFun = af_pin_table[i].func; + + if(af_pin_table[i].func == GPIO_FUN_UNUSED) + { + continue; + } + else if(af_pin_table[i].func == GPIO_FUN_PWM) + { + gpio_cfg.pullType = GPIO_PULL_DOWN; + } + // else if((af_pin_table[i].func == GPIO_FUN_DAC)|| (af_pin_table[i].func == GPIO_FUN_DAC)) + // { + // gpio_cfg.gpioFun = GPIO_FUN_ANALOG; + // gpio_cfg.gpioMode = GPIO_MODE_ANALOG; + // } + else if((af_pin_table[i].func & 0x70) == 0x70) + { + gpio_cfg.gpioFun = GPIO_FUN_UART; + uint8_t sig = af_pin_table[i].func & 0x07; + GLB_UART_Fun_Sel((gpio_cfg.gpioPin % 8), sig); + } + GLB_GPIO_Init(&gpio_cfg); + } + +} + +static void board_clock_init(void) +{ + system_clock_init(); + peripheral_clock_init(); +} + +void bl_show_info(void) +{ + MSG(" ____ __ __ _ _ _ \r\n"); + MSG(" | _ \\ / _|/ _| | | | | | | \r\n"); + MSG(" | |_) | ___ _ _| |_| |_ __ _| | ___ | | __ _| |__ \r\n"); + MSG(" | _ < / _ \\| | | | _| _/ _` | |/ _ \\| |/ _` | '_ \\ \r\n"); + MSG(" | |_) | (_) | |_| | | | || (_| | | (_) | | (_| | |_) |\r\n"); + MSG(" |____/ \\___/ \\__,_|_| |_| \\__,_|_|\\___/|_|\\__,_|_.__/ \r\n"); + MSG("\r\n"); + MSG("Build:%s,%s\r\n",__TIME__,__DATE__); + MSG("Copyright (c) 2021 Bouffalolab team\r\n"); + +#if 0 + MSG("root clock:%dM\r\n",system_clock_get(SYSTEM_CLOCK_ROOT_CLOCK)/1000000); + MSG("fclk clock:%dM\r\n",system_clock_get(SYSTEM_CLOCK_FCLK)/1000000); + MSG("bclk clock:%dM\r\n",system_clock_get(SYSTEM_CLOCK_BCLK)/1000000); + + MSG("uart clock:%dM\r\n",peripheral_clock_get(PERIPHERAL_CLOCK_UART)/1000000); + MSG("spi clock:%dM\r\n",peripheral_clock_get(PERIPHERAL_CLOCK_SPI)/1000000); + MSG("i2c clock:%dM\r\n",peripheral_clock_get(PERIPHERAL_CLOCK_I2C)/1000000); +#endif +} + +void board_init(void) +{ + board_clock_init(); + board_pin_mux_init(); +} diff --git a/bsp/board/bl602_iot/clock_config.h b/bsp/board/bl602_iot/clock_config.h new file mode 100644 index 00000000..cb8bd1ff --- /dev/null +++ b/bsp/board/bl602_iot/clock_config.h @@ -0,0 +1,55 @@ +/** + * @file clock_config.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef _CLOCK_CONFIG_H +#define _CLOCK_CONFIG_H + +#define BSP_ROOT_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_160M + +#if defined(BSP_ROOT_CLOCK_SOURCE) +#define BSP_HCLK_DIV 0 +#define BSP_BCLK_DIV 1 +#endif + +#if defined(BSP_USING_UART0)||defined(BSP_USING_UART1) +#define BSP_UART_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_160M +#define BSP_UART_CLOCK_DIV 0 +#endif +#if defined(BSP_USING_I2C0) +#define BSP_I2C_CLOCK_SOURCE ROOT_CLOCK_SOURCE_BCLK +#define BSP_I2C_CLOCK_DIV 0 +#endif +#if defined(BSP_USING_SPI0) +#define BSP_SPI_CLOCK_SOURCE ROOT_CLOCK_SOURCE_BCLK +#define BSP_SPI_CLOCK_DIV 0 +#endif +#if defined(BSP_USING_ADC0) +#define BSP_ADC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_XCLK +#define BSP_ADC_CLOCK_DIV 0 +#endif +#if defined(BSP_USING_DAC0) +#define BSP_DAC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL +#define BSP_DAC_CLOCK_DIV 1 +#endif + +#endif \ No newline at end of file diff --git a/bsp/board/bl602_iot/peripheral_config.h b/bsp/board/bl602_iot/peripheral_config.h new file mode 100644 index 00000000..6b371120 --- /dev/null +++ b/bsp/board/bl602_iot/peripheral_config.h @@ -0,0 +1,309 @@ +/** + * @file peripheral_config.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef _PERIPHERAL_CONFIG_H_ +#define _PERIPHERAL_CONFIG_H_ + +/* PERIPHERAL USING LIST */ +#define BSP_USING_UART0 +/* ----------------------*/ + +/* PERIPHERAL With DMA LIST */ + +#define BSP_USING_DMA0_CH0 +#define BSP_USING_DMA0_CH1 +#define BSP_USING_DMA0_CH2 +#define BSP_USING_DMA0_CH3 +#define BSP_USING_DMA0_CH4 +#define BSP_USING_DMA0_CH2 +#define BSP_USING_DMA0_CH6 + +/* PERIPHERAL CONFIG */ +#if defined(BSP_USING_ADC0) +#ifndef ADC0_CONFIG +#define ADC0_CONFIG \ +{ \ + .clk_div = ADC_CLOCK_DIV_32,\ + .vref = ADC_VREF_3P2V,\ + .continuous_conv_mode = DISABLE,\ + .differential_mode = DISABLE,\ + .data_width = ADC_DATA_WIDTH_16B_WITH_256_AVERAGE,\ + .fifo_threshold = ADC_FIFO_THRESHOLD_1BYTE,\ + .gain = ADC_GAIN_1\ +} +#endif +#endif + +#if defined(BSP_USING_DAC0) +#ifndef DAC_CONFIG +#define DAC_CONFIG \ +{ \ + .clk = DAC_CLK_500KHZ,\ + .pin.dac0 = GLB_GPIO_PIN_11,\ + .pin.pin_num = 1,\ +} +#endif +#endif + +#if defined(BSP_USING_UART0) +#ifndef UART0_CONFIG +#define UART0_CONFIG \ +{ \ + .id = 0, \ + .baudrate = 2000000,\ + .databits = UART_DATA_LEN_8, \ + .stopbits = UART_STOP_ONE, \ + .parity = UART_PAR_NONE, \ + .fifo_threshold = 1, \ +} +#endif +#endif + +#if defined(BSP_USING_UART1) +#ifndef UART1_CONFIG +#define UART1_CONFIG \ +{ \ + .id = 1, \ + .baudrate = 2000000,\ + .databits = UART_DATA_LEN_8, \ + .stopbits = UART_STOP_ONE, \ + .parity = UART_PAR_NONE, \ + .fifo_threshold = 64, \ +} +#endif +#endif + +#if defined(BSP_USING_SPI0) +#ifndef SPI0_CONFIG +#define SPI0_CONFIG \ +{ \ + .id = 0, \ + .clk = 18000000,\ + .mode = SPI_MASTER_MODE, \ + .direction = SPI_MSB_BYTE0_DIRECTION_FIRST, \ + .clk_polaraity = SPI_POLARITY_LOW, \ + .clk_phase = SPI_PHASE_1EDGE, \ + .datasize = SPI_DATASIZE_8BIT, \ + .fifo_threshold = 1, \ +} +#endif +#endif + +#if defined(BSP_USING_PWM_CH2) +#ifndef PWM_CH2_CONFIG +#define PWM_CH2_CONFIG \ +{ \ + .ch = 2, \ + .frequency = 1000000, \ + .dutycycle = 0, \ + .it_pulse_count = 0,\ +} +#endif +#endif + +#if defined(BSP_USING_I2S0) +#ifndef I2S0_CONFIG +#define I2S0_CONFIG \ +{ \ + .id = 0, \ + .iis_mode = I2S_MODE_MASTER,\ + .interface_mode = I2S_MODE_LEFT, \ + .sampl_freq_hz = 16*1000, \ + .channel_num = I2S_FS_CHANNELS_NUM_MONO, \ + .frame_size = I2S_FRAME_LEN_16, \ + .data_size = I2S_DATA_LEN_16, \ + .fifo_threshold = 8, \ +} +#endif +#endif + +#if defined(BSP_USING_DMA0_CH0) +#ifndef DMA0_CH0_CONFIG +#define DMA0_CH0_CONFIG \ +{ \ + .id = 0, \ + .ch = 0,\ + .direction = DMA_MEMORY_TO_MEMORY,\ + .transfer_mode = DMA_LLI_ONCE_MODE, \ + .src_req = DMA_REQUEST_NONE, \ + .dst_req = DMA_REQUEST_NONE, \ + .src_width = DMA_TRANSFER_WIDTH_32BIT , \ + .dst_width = DMA_TRANSFER_WIDTH_32BIT , \ +} +#endif +#endif + +#if defined(BSP_USING_DMA0_CH1) +#ifndef DMA0_CH1_CONFIG +#define DMA0_CH1_CONFIG \ +{ \ + .id = 0, \ + .ch = 1,\ + .direction = DMA_MEMORY_TO_MEMORY, \ + .transfer_mode = DMA_LLI_ONCE_MODE, \ + .src_req = DMA_REQUEST_NONE, \ + .dst_req = DMA_REQUEST_NONE, \ + .src_width = DMA_TRANSFER_WIDTH_16BIT , \ + .dst_width = DMA_TRANSFER_WIDTH_16BIT , \ +} +#endif +#endif + +#if defined(BSP_USING_DMA0_CH2) +#ifndef DMA0_CH2_CONFIG +#define DMA0_CH2_CONFIG \ +{ \ + .id = 0, \ + .ch = 2,\ + .direction = DMA_MEMORY_TO_PERIPH, \ + .transfer_mode = DMA_LLI_ONCE_MODE, \ + .src_req = DMA_REQUEST_NONE, \ + .dst_req = DMA_REQUEST_UART1_TX, \ + .src_width = DMA_TRANSFER_WIDTH_8BIT , \ + .dst_width = DMA_TRANSFER_WIDTH_8BIT , \ +} +#endif +#endif + + +#if defined(BSP_USING_DMA0_CH3) +#ifndef DMA0_CH3_CONFIG +#define DMA0_CH3_CONFIG \ +{ \ + .id = 0, \ + .ch = 3,\ + .direction = DMA_MEMORY_TO_PERIPH, \ + .transfer_mode = DMA_LLI_ONCE_MODE, \ + .src_req = DMA_REQUEST_NONE, \ + .dst_req = DMA_REQUEST_SPI0_TX, \ + .src_width = DMA_TRANSFER_WIDTH_8BIT , \ + .dst_width = DMA_TRANSFER_WIDTH_8BIT , \ +} +#endif +#endif + +#if defined(BSP_USING_DMA0_CH4) +#ifndef DMA0_CH4_CONFIG +#define DMA0_CH4_CONFIG \ +{ \ + .id = 0, \ + .ch = 4,\ + .direction = DMA_PERIPH_TO_MEMORY, \ + .transfer_mode = DMA_LLI_ONCE_MODE, \ + .src_req = DMA_REQUEST_SPI0_RX, \ + .dst_req = DMA_REQUEST_NONE, \ + .src_width = DMA_TRANSFER_WIDTH_8BIT , \ + .dst_width = DMA_TRANSFER_WIDTH_8BIT , \ +} +#endif +#endif + + +#if defined(BSP_USING_DMA0_CH5) +#ifndef DMA0_CH5_CONFIG +#define DMA0_CH5_CONFIG \ +{ \ + .id = 0, \ + .ch = 5,\ + .direction = DMA_MEMORY_TO_PERIPH, \ + .transfer_mode = DMA_LLI_CYCLE_MODE, \ + .src_req = DMA_REQUEST_NONE, \ + .dst_req = DMA_REQUEST_I2S_TX, \ + .src_width = DMA_TRANSFER_WIDTH_16BIT , \ + .dst_width = DMA_TRANSFER_WIDTH_16BIT , \ +} +#endif +#endif + +#if defined(BSP_USING_DMA0_CH6) +#ifndef DMA0_CH6_CONFIG +#define DMA0_CH6_CONFIG \ +{ \ + .id = 0, \ + .ch = 6,\ + .direction = DMA_MEMORY_TO_PERIPH, \ + .transfer_mode = DMA_LLI_CYCLE_MODE, \ + .src_req = DMA_REQUEST_NONE, \ + .dst_req = DMA_REQUEST_I2S_TX, \ + .src_width = DMA_TRANSFER_WIDTH_16BIT , \ + .dst_width = DMA_TRANSFER_WIDTH_16BIT , \ +} +#endif +#endif + + +#if defined(BSP_USING_DMA0_CH7) +#ifndef DMA0_CH7_CONFIG +#define DMA0_CH7_CONFIG \ +{ \ + .id = 0, \ + .ch = 0,\ + .direction = DMA_MEMORY_TO_MEMORY,\ + .transfer_mode = DMA_LLI_ONCE_MODE, \ + .src_req = DMA_REQUEST_NONE, \ + .dst_req = DMA_REQUEST_NONE, \ + .src_width = DMA_TRANSFER_WIDTH_32BIT , \ + .dst_width = DMA_TRANSFER_WIDTH_32BIT , \ +} +#endif +#endif + + + +#if defined(BSP_USING_I2C0) +#ifndef I2C0_CONFIG +#define I2C0_CONFIG \ +{ \ + .id = 0, \ + .mode = I2C_HW_MODE,\ + .phase = 15, \ +} +#endif +#endif + + +#if defined (BSP_USING_TIMER_CH0) +#ifndef TIMER_CH0_CONFIG +#define TIMER_CH0_CONFIG \ +{ \ + .id = 0, \ + .ch = 0, \ + .cnt_mode = TIMER_CNT_PRELOAD, \ + .pl_trig_src = TIMER_PL_TRIG_COMP0, \ +} +#endif +#endif + +#if defined (BSP_USING_TIMER_CH1) +#ifndef TIMER_CH1_CONFIG +#define TIMER_CH1_CONFIG \ +{ \ + .id = 0, \ + .ch = 1, \ + .cnt_mode = TIMER_CNT_PRELOAD, \ + .pl_trig_src = TIMER_PL_TRIG_COMP0, \ +} +#endif +#endif + +#endif diff --git a/bsp/board/bl602_iot/pinmux_config.h b/bsp/board/bl602_iot/pinmux_config.h new file mode 100644 index 00000000..4aa32d67 --- /dev/null +++ b/bsp/board/bl602_iot/pinmux_config.h @@ -0,0 +1,144 @@ +/** + * @file pinmux_config.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef _PINMUX_CONFIG_H +#define _PINMUX_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// GPIO0 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio0 function +#define CONFIG_GPIO0_FUNC GPIO_FUN_UNUSED + +// GPIO1 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_CTS//GPIO_FUN_UART1_CTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio1 function +#define CONFIG_GPIO1_FUNC GPIO_FUN_UNUSED + +// GPIO2 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_TX//GPIO_FUN_UART1_TX//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio2 function +#define CONFIG_GPIO2_FUNC GPIO_FUN_UNUSED + +// GPIO3 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RX//GPIO_FUN_UART1_RX//GPIO_FUN_QDEC] +// config gpio3 function +#define CONFIG_GPIO3_FUNC GPIO_FUN_UNUSED + +// GPIO4 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio4 function +#define CONFIG_GPIO4_FUNC GPIO_FUN_UNUSED + +// GPIO5 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_CTS//GPIO_FUN_UART1_CTS//GPIO_FUN_QDEC] +// config gpio5 function +#define CONFIG_GPIO5_FUNC GPIO_FUN_UNUSED + +// GPIO6 <2> [GPIO_FUN_UNUSED//GPIO_FUN_CLK_OUT//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_TX//GPIO_FUN_UART1_TX//GPIO_FUN_QDEC] +// config gpio6 function +#define CONFIG_GPIO6_FUNC GPIO_FUN_UNUSED + +// GPIO7 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_USB//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RX//GPIO_FUN_UART1_RX//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio7 function +#define CONFIG_GPIO7_FUNC GPIO_FUN_UART0_RX + +// GPIO8 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_USB//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio8 function +#define CONFIG_GPIO8_FUNC GPIO_FUN_UNUSED + +// GPIO9 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio9 function +#define CONFIG_GPIO9_FUNC GPIO_FUN_UNUSED + +// GPIO10 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio10 function +#define CONFIG_GPIO10_FUNC GPIO_FUN_UNUSED + +// GPIO11 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio11 function +#define CONFIG_GPIO11_FUNC GPIO_FUN_UNUSED + +// GPIO12 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio12 function +#define CONFIG_GPIO12_FUNC GPIO_FUN_UNUSED + +// GPIO13 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio13 function +#define CONFIG_GPIO13_FUNC GPIO_FUN_UNUSED + +// GPIO14 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio14 function +#define CONFIG_GPIO14_FUNC GPIO_FUN_UNUSED + +// GPIO15 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio15 function +#define CONFIG_GPIO15_FUNC GPIO_FUN_UNUSED + +// GPIO16 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio16 function +#define CONFIG_GPIO16_FUNC GPIO_FUN_UART0_TX + +// GPIO17 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio17 function +#define CONFIG_GPIO17_FUNC GPIO_FUN_UNUSED + +// GPIO18 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio18 function +#define CONFIG_GPIO18_FUNC GPIO_FUN_UNUSED + +// GPIO19 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio19 function +#define CONFIG_GPIO19_FUNC GPIO_FUN_UNUSED + +// GPIO20 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio20 function +#define CONFIG_GPIO20_FUNC GPIO_FUN_UNUSED + +// GPIO21 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio21 function +#define CONFIG_GPIO21_FUNC GPIO_FUN_UNUSED + +// GPIO22 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio22 function +#define CONFIG_GPIO22_FUNC GPIO_FUN_UNUSED + +// GPIO23 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC] +// config gpio23 function +#define CONFIG_GPIO23_FUNC GPIO_FUN_UNUSED + +// GPIO24 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio24 function +#define CONFIG_GPIO24_FUNC GPIO_FUN_UNUSED + +// GPIO25 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio25 function +#define CONFIG_GPIO25_FUNC GPIO_FUN_UNUSED + +// GPIO26 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio26 function +#define CONFIG_GPIO26_FUNC GPIO_FUN_UNUSED + +// GPIO27 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio27 function +#define CONFIG_GPIO27_FUNC GPIO_FUN_UNUSED + +// GPIO28 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC] +// config gpio28 function +#define CONFIG_GPIO28_FUNC GPIO_FUN_UNUSED + +#endif diff --git a/drivers/bl602_driver/CMakeLists.txt b/drivers/bl602_driver/CMakeLists.txt new file mode 100644 index 00000000..4bbf6e5c --- /dev/null +++ b/drivers/bl602_driver/CMakeLists.txt @@ -0,0 +1,61 @@ +################# Add global include ################# +list(APPEND ADD_INCLUDE +"${CMAKE_CURRENT_SOURCE_DIR}" +"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/inc" +"${CMAKE_CURRENT_SOURCE_DIR}/hal_drv/inc" +"${CMAKE_CURRENT_SOURCE_DIR}/startup" +"${CMAKE_CURRENT_SOURCE_DIR}/risc-v/Core/Include" +"${CMAKE_CURRENT_SOURCE_DIR}/regs" +) +####################################################### + +################# Add private include ################# +list(APPEND ADD_PRIVATE_INCLUDE +"${CMAKE_CURRENT_SOURCE_DIR}/hal_drv/default_config" +) +####################################################### + +############## Add current dir source files ########### +file(GLOB_RECURSE sources +"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/*.c" +"${CMAKE_CURRENT_SOURCE_DIR}/hal_drv/src/*.c" +"${CMAKE_CURRENT_SOURCE_DIR}/startup/interrupt.c" +"${CMAKE_CURRENT_SOURCE_DIR}/startup/system_bl602.c" +"${CMAKE_CURRENT_SOURCE_DIR}/startup/GCC/entry.S" +"${CMAKE_CURRENT_SOURCE_DIR}/startup/GCC/start_load.c" +) +list(APPEND ADD_SRCS ${sources}) +# aux_source_directory(src ADD_SRCS) +list(REMOVE_ITEM ADD_SRCS "${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/bl602_mfg_efuse.c" +"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/bl602_mfg_media.c" +"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/bl602_mfg_flash.c" +"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/bl602_romdriver.c") +####################################################### + +########### Add required/dependent components ######### +list(APPEND ADD_REQUIREMENTS common) +####################################################### + +############ Add static libs ########################## +# if(CONFIG_COMPONENT1_INCLUDE_STATIC_LIB) +# list(APPEND ADD_STATIC_LIB "lib/libtest.a") +# endif() +####################################################### + +############ Add dynamic libs ######################### +# list(APPEND ADD_DYNAMIC_LIB "lib/arch/v831/libmaix_nn.so" +# "lib/arch/v831/libmaix_cam.so" +# ) +####################################################### + +############ Add global compile option ################ +#add components denpend on this component +list(APPEND ADD_DEFINITIONS -DARCH_RISCV) +####################################################### + +############ Add private compile option ################ +#add compile option for this component that won't affect other modules +# list(APPEND ADD_DEFINITIONS_PRIVATE -DAAAAA=1) +####################################################### + +generate_library() diff --git a/drivers/bl602_driver/bl602_flash.ld b/drivers/bl602_driver/bl602_flash.ld new file mode 100644 index 00000000..1f5919d3 --- /dev/null +++ b/drivers/bl602_driver/bl602_flash.ld @@ -0,0 +1,222 @@ +/**************************************************************************************** +* @file map.txt +* +* @brief This file is the map file (gnuarm or armgcc). +* +* Copyright (C) BouffaloLab 2018 +* +**************************************************************************************** +*/ + +/* configure the CPU type */ +OUTPUT_ARCH( "riscv" ) +/* link with the standard c library */ +INPUT(-lc) +/* link with the standard GCC library */ +INPUT(-lgcc) +/* configure the entry point */ +ENTRY(_enter) + +StackSize = 0x0400; /* 1KB */ +HeapSize = 0x1000; /* 4KB */ + +MEMORY +{ + xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 1024K + itcm_memory (rx) : ORIGIN = 0x22010000, LENGTH = 16K + dtcm_memory (rx) : ORIGIN = 0x42014000, LENGTH = 48K + ram_memory (!rx) : ORIGIN = 0x42020000, LENGTH = 176K +} + +SECTIONS +{ + PROVIDE(__metal_chicken_bit = 0); + + .text : + { + . = ALIGN(4); + __text_code_start__ = .; + + KEEP (*(.text.metal.init.enter)) + KEEP (*(SORT_NONE(.init))) + + /* section information for finsh shell */ + . = ALIGN(4); + _shell_command_start = .; + KEEP(*(shellCommand)) + _shell_command_end = .; + + *(.text) + *(.text.*) + + /*put .rodata**/ + *(EXCLUDE_FILE( *bl602_glb.o \ + *bl602_pds.o \ + *bl602_common.o \ + *bl602_sf_cfg.o \ + *bl602_sf_ctrl.o \ + *bl602_sflash.o \ + *bl602_xip_sflash.o \ + *bl602_ef_ctrl.o) .rodata*) + *(.rodata) + *(.rodata.*) + + *(.srodata) + *(.srodata.*) + + . = ALIGN(4); + __text_code_end__ = .; + + } > xip_memory + + . = ALIGN(4); + __itcm_load_addr = .; + + .itcm_region : AT (__itcm_load_addr) + { + . = ALIGN(4); + __tcm_code_start__ = .; + + *(.tcm_code) + *(.tcm_const) + *(.sclock_rlt_code) + *(.sclock_rlt_const) + + *bl602_glb.o*(.rodata*) + *bl602_pds.o*(.rodata*) + *bl602_common.o*(.rodata*) + *bl602_sf_cfg.o*(.rodata*) + *bl602_sf_ctrl.o*(.rodata*) + *bl602_sflash.o*(.rodata*) + *bl602_xip_sflash.o*(.rodata*) + *bl602_ef_ctrl.o*(.rodata*) + + . = ALIGN(4); + __tcm_code_end__ = .; + } > itcm_memory + + __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); + + .dtcm_region : AT (__dtcm_load_addr) + { + . = ALIGN(4); + __tcm_data_start__ = .; + + *(.tcm_data) + + . = ALIGN(4); + __tcm_data_end__ = .; + } > dtcm_memory + + + /* .heap_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of heap sections, and assign + * values to heap symbols later */ + .heap_dummy (NOLOAD): + { + . = ALIGN(0x4); + . = . + HeapSize; + . = ALIGN(0x4); + } > dtcm_memory + + _HeapBase = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory) - StackSize - HeapSize; + _HeapSize = HeapSize; + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(_HeapBase >= __tcm_data_end__, "region RAM overflowed with stack") + + /*************************************************************************/ + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + . = ALIGN(0x4); + . = . + StackSize; + . = ALIGN(0x4); + } > dtcm_memory + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); + PROVIDE( __freertos_irq_stack_top = __StackTop); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") + /*************************************************************************/ + + __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); + + .system_ram_data_region : AT (__system_ram_load_addr) + { + . = ALIGN(4); + __system_ram_data_start__ = .; + + *(.system_ram) + + . = ALIGN(4); + __system_ram_data_end__ = .; + } > ram_memory + + __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); + + /* Data section */ + RAM_DATA : AT (__ram_load_addr) + { + . = ALIGN(4); + __ram_data_start__ = .; + + PROVIDE( __global_pointer$ = . + 0x800 ); + + *(.data) + *(.data.*) + *(.sdata) + *(.sdata.*) + *(.sdata2) + *(.sdata2.*) + + . = ALIGN(4); + __ram_data_end__ = .; + } > ram_memory + + .bss (NOLOAD) : + { + . = ALIGN(4); + __bss_start__ = .; + + *(.bss*) + *(.sbss*) + *(COMMON) + + . = ALIGN(4); + __bss_end__ = .; + } > ram_memory + + .noinit_data (NOLOAD) : + { + . = ALIGN(4); + __noinit_data_start__ = .; + + *(.noinit_data*) + + . = ALIGN(4); + __noinit_data_end__ = .; + } > ram_memory + + .heap (NOLOAD): + { + . = ALIGN(4); + __HeapBase = .; + + /*__end__ = .;*/ + /*end = __end__;*/ + KEEP(*(.heap*)) + + . = ALIGN(4); + __HeapLimit = .; + } > ram_memory + __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); + +} + diff --git a/drivers/bl602_driver/cpu_flags.cmake b/drivers/bl602_driver/cpu_flags.cmake new file mode 100644 index 00000000..590844c7 --- /dev/null +++ b/drivers/bl602_driver/cpu_flags.cmake @@ -0,0 +1,14 @@ +SET(CPU_ARCH "RISCV") +SET(MCPU "e24") +if(${SUPPORT_FLOAT} STREQUAL "y") +SET(MARCH "rv32imafc") +SET(MABI "ilp32f") +else() +SET(MARCH "rv32imac") +SET(MABI "ilp32") +endif() + +list(APPEND GLOBAL_C_FLAGS -march=${MARCH} -mabi=${MABI}) +list(APPEND GLOBAL_LD_FLAGS -march=${MARCH} -mabi=${MABI}) + +SET(LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/bl602_flash.ld) \ No newline at end of file diff --git a/drivers/bl602_driver/hal_drv/default_config/adc_config.h b/drivers/bl602_driver/hal_drv/default_config/adc_config.h new file mode 100644 index 00000000..92e1d278 --- /dev/null +++ b/drivers/bl602_driver/hal_drv/default_config/adc_config.h @@ -0,0 +1,5 @@ +#ifndef _ADC_CONFIG_H +#define _ADC_CONFIG_H + + +#endif \ No newline at end of file diff --git a/drivers/bl602_driver/hal_drv/default_config/spi_config.h b/drivers/bl602_driver/hal_drv/default_config/spi_config.h new file mode 100644 index 00000000..99f133dc --- /dev/null +++ b/drivers/bl602_driver/hal_drv/default_config/spi_config.h @@ -0,0 +1,6 @@ +#ifndef _SPI_CONFIG_H +#define _SPI_CONFIG_H + +#define SPI_DEGLITCH_ENABLE (0) +#define SPI_CONTINUE_TRANSFER_ENABLE (1) +#endif \ No newline at end of file diff --git a/drivers/bl602_driver/hal_drv/default_config/uart_config.h b/drivers/bl602_driver/hal_drv/default_config/uart_config.h new file mode 100644 index 00000000..f83fc91e --- /dev/null +++ b/drivers/bl602_driver/hal_drv/default_config/uart_config.h @@ -0,0 +1,12 @@ +#ifndef _UART_CONFIG_H +#define _UART_CONFIG_H + +#define UART_CLOCK_SOURCE_160M_ENABLE (1) +#define UART_CTS_FLOWCONTROL_ENABLE (0) +#define UART_RTS_FLOWCONTROL_ENABLE (0) +#define UART_RX_DEGLITCH_ENABLE (0) +#define UART_MSB_FIRST_ENABLE (0) + +#define UART_FIFO_MAX_LEN 128 +#define UART_DEFAULT_RTO_TIMEOUT 255 +#endif \ No newline at end of file diff --git a/drivers/bl602_driver/hal_drv/inc/hal_clock.h b/drivers/bl602_driver/hal_drv/inc/hal_clock.h new file mode 100644 index 00000000..71625637 --- /dev/null +++ b/drivers/bl602_driver/hal_drv/inc/hal_clock.h @@ -0,0 +1,83 @@ +/** + * @file hal_clock.h + * @brief + * + * Copyright 2019-2030 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_CLOCK__H__ +#define __HAL_CLOCK__H__ + +#include "drv_device.h" +#include "bl602_config.h" + +#define EXTERNAL_XTAL_NONE 0 +#define EXTERNAL_XTAL_24M 1 +#define EXTERNAL_XTAL_32M 2 +#define EXTERNAL_XTAL_38P4M 3 +#define EXTERNAL_XTAL_40M 4 +#define EXTERNAL_XTAL_26M 5 +#define INTERAL_XTAL_RC32M 6 + +#define ROOT_CLOCK_SOURCE_RC_32K 0 +#define ROOT_CLOCK_SOURCE_XTAL_32K 1 +#define ROOT_CLOCK_SOURCE_RC_32M 2 + +#define ROOT_CLOCK_SOURCE_XTAL_32M 3 +#define ROOT_CLOCK_SOURCE_PLL_48M 4 +#define ROOT_CLOCK_SOURCE_PLL_120M 5 +#define ROOT_CLOCK_SOURCE_PLL_160M 6 +#define ROOT_CLOCK_SOURCE_PLL_192M 7 + +#define ROOT_CLOCK_SOURCE_XCLK ROOT_CLOCK_SOURCE_XTAL_32M +#define ROOT_CLOCK_SOURCE_FCLK 8 +#define ROOT_CLOCK_SOURCE_HCLK 8 +#define ROOT_CLOCK_SOURCE_BCLK 9 + +#define ROOT_CLOCK_SOURCE_AUPLL 9 + +#define OUTPUT_REF_CLOCK_SOURCE_NONE 0 +#define OUTPUT_REF_CLOCK_SOURCE_I2S 1 + +#if (BSP_ROOT_CLOCK_SOURCE > 2) && (BSP_ROOT_CLOCK_SOURCE < 8) +#define CLOCK_XTAL EXTERNAL_XTAL_40M +#else +#define CLOCK_XTAL INTERAL_XTAL_RC32M +#endif + +enum system_clock_type +{ + SYSTEM_CLOCK_ROOT_CLOCK = 0, + SYSTEM_CLOCK_FCLK, + SYSTEM_CLOCK_BCLK, + SYSTEM_CLOCK_XCLK, +}; +enum peripheral_clock_type +{ + PERIPHERAL_CLOCK_UART = 0, + PERIPHERAL_CLOCK_SPI, + PERIPHERAL_CLOCK_I2C, + PERIPHERAL_CLOCK_ADC, + PERIPHERAL_CLOCK_DAC, +}; + +void system_clock_init(void); +void peripheral_clock_init(void); +uint32_t system_clock_get(enum system_clock_type type); +uint32_t peripheral_clock_get(enum peripheral_clock_type type); +#endif \ No newline at end of file diff --git a/drivers/bl602_driver/hal_drv/inc/hal_dma.h b/drivers/bl602_driver/hal_drv/inc/hal_dma.h new file mode 100644 index 00000000..3d90d2d1 --- /dev/null +++ b/drivers/bl602_driver/hal_drv/inc/hal_dma.h @@ -0,0 +1,193 @@ +/** + * @file hal_dma.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_DMA__H__ +#define __HAL_DMA__H__ + +#include "drv_device.h" +#include "bl602_config.h" + +#define DMA_CHANNEL_GET_STATUS 0x10 +#define DMA_CHANNEL_START 0x11 +#define DMA_CHANNEL_STOP 0x12 +#define DMA_CHANNEL_UPDATE 0x13 + +enum dma_index_type +{ +#ifdef BSP_USING_DMA0_CH0 + DMA0_CH0_INDEX, +#endif +#ifdef BSP_USING_DMA0_CH1 + DMA0_CH1_INDEX, +#endif +#ifdef BSP_USING_DMA0_CH2 + DMA0_CH2_INDEX, +#endif +#ifdef BSP_USING_DMA0_CH3 + DMA0_CH3_INDEX, +#endif +#ifdef BSP_USING_DMA0_CH4 + DMA0_CH4_INDEX, +#endif +#ifdef BSP_USING_DMA0_CH5 + DMA0_CH5_INDEX, +#endif +#ifdef BSP_USING_DMA0_CH6 + DMA0_CH6_INDEX, +#endif +#ifdef BSP_USING_DMA0_CH7 + DMA0_CH7_INDEX, +#endif + DMA_MAX_INDEX +}; + +#define dma_channel_start(dev) device_control(dev,DMA_CHANNEL_START,NULL) +#define dma_channel_stop(dev) device_control(dev,DMA_CHANNEL_STOP,NULL) +#define dma_channel_update(dev,list) device_control(dev,DMA_CHANNEL_UPDATE,list) +#define dma_channel_check_busy(dev) device_control(dev,DMA_CHANNEL_GET_STATUS,NULL) + +#define DMA_ADDR_UART0_TDR (0x4000A000+0x88) +#define DMA_ADDR_UART0_RDR (0x4000A000+0x8C) +#define DMA_ADDR_UART1_TDR (0x4000A100+0x88) +#define DMA_ADDR_UART1_RDR (0x4000A100+0x8C) +#define DMA_ADDR_I2C_TDR (0x4000A300+0x88) +#define DMA_ADDR_I2C_RDR (0x4000A300+0x8C) +#define DMA_ADDR_SPI_TDR (0x4000A200+0x88) +#define DMA_ADDR_SPI_RDR (0x4000A200+0x8C) +#define DMA_ADDR_I2S_TDR (0x4000AA00+0x88) +#define DMA_ADDR_I2S_RDR (0x4000AA00+0x8C) +#define DMA_ADDR_ADC0_DR (0x40002000+0x04) +#define DMA_ADDR_ADC1_DR (0x40002000+0x04) +#define DMA_ADDR_DAC_TDR (0x40002048) + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @brief DMA peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE 1 /*!< Peripheral increment mode enable */ +#define DMA_PINC_DISABLE 0 /*!< Peripheral increment mode disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @brief DMA memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE 1 /*!< Memory increment mode enable */ +#define DMA_MINC_DISABLE 0 /*!< Memory increment mode disable */ + +#define DMA_REQUEST_NONE 0x00000000 /*!< DMA request peripheral:None */ +#define DMA_REQUEST_UART0_RX 0x00000000 /*!< DMA request peripheral:UART0 RX */ +#define DMA_REQUEST_UART0_TX 0x00000001 /*!< DMA request peripheral:UART0 TX */ +#define DMA_REQUEST_UART1_RX 0x00000002 /*!< DMA request peripheral:UART1 RX */ +#define DMA_REQUEST_UART1_TX 0x00000003 /*!< DMA request peripheral:UART1 TX */ +#define DMA_REQUEST_I2C0_RX 0x00000006 /*!< DMA request peripheral:I2C RX */ +#define DMA_REQUEST_I2C0_TX 0x00000007 /*!< DMA request peripheral:I2C TX */ +#define DMA_REQUEST_SPI0_RX 0x0000000A /*!< DMA request peripheral:SPI RX */ +#define DMA_REQUEST_SPI0_TX 0x0000000B /*!< DMA request peripheral:SPI TX */ +#define DMA_REQUEST_I2S_RX 0x00000014 /*!< DMA request peripheral:I2S RX */ +#define DMA_REQUEST_I2S_TX 0x00000015 /*!< DMA request peripheral:I2S TX */ +#define DMA_REQUEST_ADC0 0x00000016 /*!< DMA request peripheral:GPADC0 */ +#define DMA_REQUEST_DAC0 0x00000017 /*!< DMA request peripheral:GPADC1 */ + +#define DMA_BURST_1BYTE 0 +#define DMA_BURST_4BYTE 1 +#define DMA_BURST_8BYTE 2 +#define DMA_BURST_16BYTE 3 + +#define DMA_TRANSFER_WIDTH_8BIT 0 +#define DMA_TRANSFER_WIDTH_16BIT 1 +#define DMA_TRANSFER_WIDTH_32BIT 2 + +#define DMA_LLI_ONCE_MODE 0 +#define DMA_LLI_CYCLE_MODE 1 + +/** + * @brief DMA transfer direction type definition + */ +typedef enum { + DMA_MEMORY_TO_MEMORY = 0, /*!< DMA transfer tyep:memory to memory */ + DMA_MEMORY_TO_PERIPH, /*!< DMA transfer tyep:memory to peripheral */ + DMA_PERIPH_TO_MEMORY, /*!< DMA transfer tyep:peripheral to memory */ + DMA_PERIPH_TO_PERIPH, /*!< DMA transfer tyep:peripheral to peripheral */ +}dma_transfer_dir_type; + +typedef union +{ + struct + { + uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ + uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ + uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ + uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ + uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ + uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ + uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ + uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ + uint32_t fix_cnt : 2; /* [24:23], r/w, 0x0 */ + uint32_t SLargerD : 1; /* [ 25], r/w, 0x0 */ + uint32_t SI : 1; /* [ 26], r/w, 0x1 */ + uint32_t DI : 1; /* [ 27], r/w, 0x1 */ + uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ + uint32_t I : 1; /* [ 31], r/w, 0x0 */ + } bits; + uint32_t WORD; +} dma_control_data_t; + +typedef struct +{ + uint32_t src_addr; + uint32_t dst_addr; + uint32_t nextlli; + dma_control_data_t cfg; +} dma_lli_ctrl_t; + +typedef struct +{ + uint8_t direction; + uint32_t src_req; + uint32_t dst_req; +} dma_ctrl_param_t; + +typedef struct dma_device +{ + struct device parent; + uint8_t id; + uint8_t ch; + uint8_t direction; + uint8_t transfer_mode; + uint32_t src_req; + uint32_t dst_req; + uint8_t src_burst_size; + uint8_t dst_burst_size; + uint8_t src_width; + uint8_t dst_width; + dma_lli_ctrl_t *lli_cfg; +} dma_device_t; + +#define DMA_DEV(dev) ((dma_device_t*)dev) + +int dma_register(enum dma_index_type, const char *name, uint16_t flag); +int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size); +int dma_allocate_register(const char *name, uint16_t flag); +#endif diff --git a/drivers/bl602_driver/hal_drv/inc/hal_gpio.h b/drivers/bl602_driver/hal_drv/inc/hal_gpio.h new file mode 100644 index 00000000..dc36fac5 --- /dev/null +++ b/drivers/bl602_driver/hal_drv/inc/hal_gpio.h @@ -0,0 +1,113 @@ +/** + * ***************************************************************************** + * @file hal_gpio.h + * @version 0.1 + * @date 2021-03-01 + * @brief + * ***************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ***************************************************************************** + */ +#ifndef __HAL_GPIO__H__ +#define __HAL_GPIO__H__ + +#include "drv_device.h" + +typedef enum +{ + GPIO_PIN_0 = 0, + GPIO_PIN_1, + GPIO_PIN_2, + GPIO_PIN_3, + GPIO_PIN_4, + GPIO_PIN_5, + GPIO_PIN_6, + GPIO_PIN_7, + GPIO_PIN_8, + GPIO_PIN_9, + GPIO_PIN_10, + GPIO_PIN_11, + GPIO_PIN_12, + GPIO_PIN_13, + GPIO_PIN_14, + GPIO_PIN_15, + GPIO_PIN_16, + GPIO_PIN_17, + GPIO_PIN_18, + GPIO_PIN_19, + GPIO_PIN_20, + GPIO_PIN_21, + GPIO_PIN_22, + GPIO_PIN_23, + GPIO_PIN_24, + GPIO_PIN_25, + GPIO_PIN_26, + GPIO_PIN_27, + GPIO_PIN_28, + GPIO_PIN_29, + GPIO_PIN_30, + GPIO_PIN_31, + GPIO_PIN_32, + GPIO_PIN_33, + GPIO_PIN_34, + GPIO_PIN_35, + GPIO_PIN_36, + GPIO_PIN_37, + GPIO_PIN_MAX, +}gpio_pin_type; + + +#define GPIO_OUTPUT_MODE 0 +#define GPIO_OUTPUT_PP_MODE 1 +#define GPIO_OUTPUT_PD_MODE 2 +#define GPIO_INPUT_MODE 3 +#define GPIO_INPUT_PP_MODE 4 +#define GPIO_INPUT_PD_MODE 5 +#define GPIO_ASYNC_RISING_TRIGER_INT_MODE 6 +#define GPIO_ASYNC_FALLING_TRIGER_INT_MODE 7 +#define GPIO_ASYNC_HIGH_LEVEL_INT_MODE 8 +#define GPIO_ASYNC_LOW_LEVEL_INT_MODE 9 +#define GPIO_SYNC_RISING_TRIGER_INT_MODE 10 +#define GPIO_SYNC_FALLING_TRIGER_INT_MODE 11 +#define GPIO_SYNC_HIGH_LEVEL_INT_MODE 12 +#define GPIO_SYNC_LOW_LEVEL_INT_MODE 13 + +typedef struct gpio_device +{ + struct device parent; +} gpio_device_t; + +void gpio_register(const char *name, uint16_t flag); + +void gpio_set_mode(uint32_t pin, uint32_t mode); +void gpio_write(uint32_t pin, uint32_t value); +void gpio_toggle(uint32_t pin); +int gpio_read(uint32_t pin); +void gpio_attach_irq(uint32_t pin, void (*cbFun)(void)); +void gpio_irq_enable(uint32_t pin,uint8_t enabled); +#endif \ No newline at end of file diff --git a/drivers/bl602_driver/hal_drv/inc/hal_mtimer.h b/drivers/bl602_driver/hal_drv/inc/hal_mtimer.h new file mode 100644 index 00000000..e547994c --- /dev/null +++ b/drivers/bl602_driver/hal_drv/inc/hal_mtimer.h @@ -0,0 +1,12 @@ +#ifndef __HAL_MTIMER__H__ +#define __HAL_MTIMER__H__ + +#include "stdint.h" + +void mtimer_set_alarm_time(uint64_t ticks, void (*interruptfun)(void)); +uint32_t mtimer_get_clk_src_div(void); +uint64_t mtimer_get_time_ms(); +uint64_t mtimer_get_time_us(); +void mtimer_delay_ms(uint32_t time); +void mtimer_delay_us(uint32_t time); +#endif \ No newline at end of file diff --git a/drivers/bl602_driver/hal_drv/inc/hal_uart.h b/drivers/bl602_driver/hal_drv/inc/hal_uart.h new file mode 100644 index 00000000..1924f9ae --- /dev/null +++ b/drivers/bl602_driver/hal_drv/inc/hal_uart.h @@ -0,0 +1,159 @@ +/** + * ***************************************************************************** + * @file hal_uart.h + * @version 0.1 + * @date 2021-03-01 + * @brief + * ***************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ***************************************************************************** + */ +#ifndef __HAL_UART__H__ +#define __HAL_UART__H__ + +#include "drv_device.h" +#include "bl602_config.h" + +#define DEVICE_CTRL_UART_GET_TX_FIFO 0x10 +#define DEVICE_CTRL_UART_GET_RX_FIFO 0x11 +#define DEVICE_CTRL_UART_ATTACH_TX_DMA 0x12 +#define DEVICE_CTRL_UART_ATTACH_RX_DMA 0x13 + +enum uart_index_type +{ +#ifdef BSP_USING_UART0 + UART0_INDEX, +#endif +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif +#ifdef BSP_USING_UART4 + UART4_INDEX, +#endif + UART_MAX_INDEX +}; + +/*! + * @brief UART data length settings + * + * This enumeration defines the UART data lengths. + */ +typedef enum +{ + UART_DATA_LEN_5 = 0, /*!< Data length is 5 bits */ + UART_DATA_LEN_6 = 1, /*!< Data length is 6 bits */ + UART_DATA_LEN_7 = 2, /*!< Data length is 7 bits */ + UART_DATA_LEN_8 = 3 /*!< Data length is 8 bits */ +} uart_databits_t; + +/*! + * @brief UART stop bit settings + * + * This enumeration defines the UART stop bits. + */ +typedef enum +{ + UART_STOP_ONE = 0, /*!< One stop bit */ + UART_STOP_ONE_D_FIVE = 0, /*!< 1.5 stop bit */ + UART_STOP_TWO = 1 /*!< Two stop bits */ +} uart_stopbits_t; + +/*! + * @brief UART parity type settings + * + * This enumeration defines the UART parity types. + */ +typedef enum +{ + UART_PAR_NONE = 0, /*!< No parity */ + UART_PAR_ODD = 1, /*!< Parity bit is odd */ + UART_PAR_EVEN = 2, /*!< Parity bit is even */ +} uart_parity_t; + +enum uart_event_type +{ + UART_EVENT_TX_END, + UART_EVENT_TX_FIFO, + UART_EVENT_RX_END, + UART_EVENT_RX_FIFO, + UART_EVENT_RTO, + UART_EVENT_UNKNOWN +}; + +typedef struct +{ + uint8_t tx; + uint8_t rx; + uint8_t cts; + uint8_t rts; +} uart_pin_t; + +enum uart_it_type +{ + UART_TX_END_IT = 1 << 0, + UART_RX_END_IT = 1 << 1, + UART_TX_FIFO_IT = 1 << 2, + UART_RX_FIFO_IT = 1 << 3, + UART_RTO_IT = 1 << 4, + UART_PCE_IT = 1 << 5, + UART_TX_FER_IT = 1 << 6, + UART_RX_FER_IT = 1 << 7, + UART_ALL_IT = 1 << 8 +}; + +typedef struct +{ + uint32_t baudrate; + uart_databits_t databits; + uart_stopbits_t stopbits; + uart_parity_t parity; +}uart_param_cfg_t; + +typedef struct uart_device +{ + struct device parent; + uint8_t id; + uint32_t baudrate; + uart_databits_t databits; + uart_stopbits_t stopbits; + uart_parity_t parity; + uint8_t fifo_threshold; + uart_pin_t pin; + void* tx_dma; + void* rx_dma; +} uart_device_t; + +int uart_register(enum uart_index_type index, const char *name, uint16_t flag); + +#endif \ No newline at end of file diff --git a/drivers/bl602_driver/hal_drv/src/hal_clock.c b/drivers/bl602_driver/hal_drv/src/hal_clock.c new file mode 100644 index 00000000..1152b5d0 --- /dev/null +++ b/drivers/bl602_driver/hal_drv/src/hal_clock.c @@ -0,0 +1,122 @@ +#include "bl602_glb.h" +#include "hal_clock.h" + +static uint32_t mtimer_get_clk_src_div(void) +{ + return ((SystemCoreClockGet()/(GLB_Get_BCLK_Div() + 1))/1000/1000-1); +} + +void system_clock_init(void) +{ + /*select root clock*/ + GLB_Set_System_CLK(CLOCK_XTAL,BSP_ROOT_CLOCK_SOURCE-2); + /*set fclk/hclk and bclk clock*/ + GLB_Set_System_CLK_Div(BSP_HCLK_DIV,BSP_BCLK_DIV); + GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div()); +} +void peripheral_clock_init(void) +{ +#if defined(BSP_USING_UART0)||defined(BSP_USING_UART1) +#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_160M + GLB_Set_UART_CLK(ENABLE,HBN_UART_CLK_160M,BSP_UART_CLOCK_DIV); +#elif BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK + GLB_Set_UART_CLK(ENABLE,HBN_UART_CLK_FCLK,BSP_UART_CLOCK_DIV); +#endif +#endif + +#if defined(BSP_USING_I2C0) + GLB_Set_I2C_CLK(ENABLE,BSP_I2C_CLOCK_DIV); +#endif + +#if defined(BSP_USING_SPI0) + GLB_Set_SPI_CLK(ENABLE,BSP_SPI_CLOCK_DIV); +#endif + +#if defined(BSP_USING_PWM) +#if BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_RC_32K + +#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK + +#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK + +#endif +#endif + +#if defined(BSP_USING_IR) + GLB_Set_IR_CLK(ENABLE,0,BSP_IR_CLOCK_DIV); +#endif + +#if defined(BSP_USING_ADC0) +#if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL + GLB_Set_ADC_CLK(ENABLE,GLB_ADC_CLK_AUDIO_PLL,BSP_ADC_CLOCK_DIV); +#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK + GLB_Set_ADC_CLK(ENABLE,GLB_ADC_CLK_XCLK,BSP_ADC_CLOCK_DIV); +#endif + +#endif + +#if defined(BSP_USING_DAC0) +#if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL + GLB_Set_DAC_CLK(ENABLE,GLB_ADC_CLK_AUDIO_PLL,BSP_DAC_CLOCK_DIV); +#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK + GLB_Set_DAC_CLK(ENABLE,GLB_ADC_CLK_XCLK,BSP_DAC_CLOCK_DIV); +#endif +#endif + +} +uint32_t system_clock_get(enum system_clock_type type) +{ + switch (type) + { + case SYSTEM_CLOCK_ROOT_CLOCK: + return SystemCoreClockGet(); + case SYSTEM_CLOCK_FCLK: + return (SystemCoreClockGet()/(GLB_Get_HCLK_Div()+1)); + case SYSTEM_CLOCK_BCLK: + return (SystemCoreClockGet()/((GLB_Get_HCLK_Div()+1)*(GLB_Get_BCLK_Div()+1))); + case SYSTEM_CLOCK_XCLK: + return 32000000; + default: + break; + } + return 0; +} +uint32_t peripheral_clock_get(enum peripheral_clock_type type) +{ + uint32_t tmpVal; + uint32_t div; + switch (type) + { + case PERIPHERAL_CLOCK_UART: + #if defined(BSP_USING_UART0)||defined(BSP_USING_UART1) + #if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_160M + return 160000000; + #elif BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK + return system_clock_get(SYSTEM_CLOCK_FCLK)/(GLB_Get_HCLK_Div()+1)); + #endif + #endif + case PERIPHERAL_CLOCK_SPI: +#if defined(BSP_USING_SPI0) +#if BSP_SPI_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK + tmpVal=BL_RD_REG(GLB_BASE,GLB_CLK_CFG3); + div = BL_GET_REG_BITS_VAL(tmpVal,GLB_SPI_CLK_DIV); + return system_clock_get(SYSTEM_CLOCK_BCLK)/(div+1); +#endif +#endif + case PERIPHERAL_CLOCK_I2C: +#if defined(BSP_USING_I2C0) +#if BSP_I2C_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK + tmpVal=BL_RD_REG(GLB_BASE,GLB_CLK_CFG3); + div = BL_GET_REG_BITS_VAL(tmpVal,GLB_I2C_CLK_DIV); + return system_clock_get(SYSTEM_CLOCK_BCLK)/(div+1); +#endif +#endif + case PERIPHERAL_CLOCK_ADC: + return 32000000; + default: + break; + } + (void)(tmpVal); + (void)(div); + return 0; +} \ No newline at end of file diff --git a/drivers/bl602_driver/hal_drv/src/hal_dma.c b/drivers/bl602_driver/hal_drv/src/hal_dma.c new file mode 100644 index 00000000..3eb9e73c --- /dev/null +++ b/drivers/bl602_driver/hal_drv/src/hal_dma.c @@ -0,0 +1,477 @@ +/** + * @file hal_dma.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_dma.h" +#include "drv_mmheap.h" +#include "bl602_dma.h" + +dma_control_data_t dma_ctrl_cfg; + +void DMA0_IRQ(void); + +dma_device_t dmax_device[DMA_MAX_INDEX] = +{ +#ifdef BSP_USING_DMA0_CH0 + DMA0_CH0_CONFIG, +#endif +#ifdef BSP_USING_DMA0_CH1 + DMA0_CH1_CONFIG, +#endif +#ifdef BSP_USING_DMA0_CH2 + DMA0_CH2_CONFIG, +#endif +#ifdef BSP_USING_DMA0_CH3 + DMA0_CH3_CONFIG, +#endif +#ifdef BSP_USING_DMA0_CH4 + DMA0_CH4_CONFIG, +#endif +#ifdef BSP_USING_DMA0_CH5 + DMA0_CH5_CONFIG, +#endif +#ifdef BSP_USING_DMA0_CH6 + DMA0_CH6_CONFIG, +#endif +#ifdef BSP_USING_DMA0_CH7 + DMA0_CH7_CONFIG, +#endif +}; +/** + * @brief + * + * @param dev + * @param oflag + * @return int + */ +int dma_open(struct device *dev, uint16_t oflag) +{ + dma_device_t *dma_device = (dma_device_t *)dev; + + DMA_LLI_Cfg_Type lliCfg = {0}; + + /* Disable all interrupt */ + DMA_IntMask(dma_device->ch, DMA_INT_ALL, MASK); + /* Enable uart interrupt*/ + NVIC_DisableIRQ(DMA_ALL_IRQn); + + DMA_Disable(); + + DMA_Channel_Disable(dma_device->ch); + + lliCfg.dir = dma_device->direction; + lliCfg.srcPeriph = dma_device->src_req; + lliCfg.dstPeriph = dma_device->dst_req; + + DMA_LLI_Init(dma_device->ch, &lliCfg); + + dma_ctrl_cfg.bits.fix_cnt = 0; + dma_ctrl_cfg.bits.dst_min_mode = 0; + dma_ctrl_cfg.bits.dst_add_mode = 0; + + DMA_Enable(); + + Interrupt_Handler_Register(DMA_ALL_IRQn, DMA0_IRQ); + + return 0; +} +/** + * @brief + * + * @param dev + * @param cmd + * @param args + * @return int + */ +int dma_control(struct device *dev, int cmd, void *args) +{ + dma_device_t *dma_device = (dma_device_t *)dev; + + switch (cmd) + { + case DEVICE_CTRL_SET_INT /* constant-expression */: + /* Dma interrupt configuration */ + DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, UNMASK); + DMA_IntMask(dma_device->ch, DMA_INT_ERR, UNMASK); + + /* Enable uart interrupt*/ + NVIC_EnableIRQ(DMA_ALL_IRQn); + break; + case DEVICE_CTRL_CLR_INT /* constant-expression */: + /* Dma interrupt configuration */ + DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, MASK); + DMA_IntMask(dma_device->ch, DMA_INT_ERR, MASK); + + /* Enable uart interrupt*/ + NVIC_DisableIRQ(DMA_ALL_IRQn); + break; + case DEVICE_CTRL_GET_INT /* constant-expression */: + /* code */ + break; + case DEVICE_CTRL_CONFIG /* constant-expression */: + { + dma_ctrl_param_t *cfg = (dma_ctrl_param_t *)args; + DMA_LLI_Cfg_Type lliCfg = {0}; + + lliCfg.dir = cfg->direction; + lliCfg.srcPeriph = cfg->src_req; + lliCfg.dstPeriph = cfg->dst_req; + + DMA_LLI_Init(dma_device->ch, &lliCfg); + + break; + } + case DMA_CHANNEL_UPDATE: + DMA_LLI_Update(dma_device->ch, (uint32_t)args); + break; + case DMA_CHANNEL_GET_STATUS /* constant-expression */: + return DMA_Channel_Is_Busy(dma_device->ch); + case DMA_CHANNEL_START /* constant-expression */: + DMA_Channel_Enable(dma_device->ch); + break; + case DMA_CHANNEL_STOP /* constant-expression */: + DMA_Channel_Disable(dma_device->ch); + break; + default: + break; + } + + return 0; +} +/** + * @brief + * + * @param dev + * @return int + */ +int dma_close(struct device *dev) +{ + DMA_Disable(); + return 0; +} + +int dma_register(enum dma_index_type index, const char *name, uint16_t flag) +{ + struct device *dev; + + if (DMA_MAX_INDEX == 0) + return -DEVICE_EINVAL; + + dev = &(dmax_device[index].parent); + + dev->open = dma_open; + dev->close = dma_close; + dev->control = dma_control; + // dev->write = dma_write; + // dev->read = dma_read; + + dev->status = DEVICE_UNREGISTER; + dev->type = DEVICE_CLASS_DMA; + dev->handle = NULL; + + return device_register(dev, name, flag); +} + +static BL_Err_Type dma_scan_unregister_device(uint8_t * allocate_index){ + struct device *dev; + dlist_t *node; + uint8_t dma_index=0; + uint32_t dma_handle[DMA_MAX_INDEX]; + + for(dma_index = 0;dma_indextype == DEVICE_CLASS_DMA){ + dma_handle[(((uint32_t)dev - (uint32_t)dmax_device) / sizeof(dma_device_t)) % DMA_MAX_INDEX] = SET; + } + } + + for(dma_index = 0;dma_indexopen = dma_open; + dev->close = dma_close; + dev->control = dma_control; + // dev->write = dma_write; + // dev->read = dma_read; + + dev->status = DEVICE_UNREGISTER; + dev->type = DEVICE_CLASS_DMA; + dev->handle = NULL; + + return device_register(dev, name, flag); +} + +/** + * @brief + * + * @param dev + * @param src_addr + * @param dst_addr + * @param transfer_size + * @return int + */ +int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size) +{ + uint32_t malloc_count; + uint32_t remain_len; + uint32_t actual_transfer_len = 0; + uint32_t actual_transfer_offset = 0; + + dma_device_t *dma_device = (dma_device_t *)dev; + + DMA_Channel_Disable(dma_device->ch); + + if (dma_device->direction == DMA_MEMORY_TO_MEMORY) + { + dma_ctrl_cfg.bits.SI = 1; + dma_ctrl_cfg.bits.DI = 1; + } + else if (dma_device->direction == DMA_MEMORY_TO_PERIPH) + { + dma_ctrl_cfg.bits.SI = 1; + dma_ctrl_cfg.bits.DI = 0; + } + else if (dma_device->direction == DMA_PERIPH_TO_MEMORY) + { + dma_ctrl_cfg.bits.SI = 0; + dma_ctrl_cfg.bits.DI = 1; + } + else if (dma_device->direction == DMA_PERIPH_TO_PERIPH) + { + dma_ctrl_cfg.bits.SI = 0; + dma_ctrl_cfg.bits.DI = 0; + } + + dma_ctrl_cfg.bits.SBSize = dma_device->src_burst_size; + dma_ctrl_cfg.bits.DBSize = dma_device->dst_burst_size; + dma_ctrl_cfg.bits.SWidth = dma_device->src_width; + dma_ctrl_cfg.bits.DWidth = dma_device->dst_width; + + if (dma_device->src_width == DMA_TRANSFER_WIDTH_8BIT) + { + actual_transfer_offset = 4095; + actual_transfer_len = transfer_size; + } + else if (dma_device->src_width == DMA_TRANSFER_WIDTH_16BIT) + { + if (transfer_size % 2) + return -1; + + actual_transfer_offset = (4095 * 2); + actual_transfer_len = transfer_size/2; + } + else if (dma_device->src_width == DMA_TRANSFER_WIDTH_32BIT) + { + if (transfer_size % 4) + return -1; + + actual_transfer_offset = (4095 * 4); + actual_transfer_len = transfer_size/4; + } + + malloc_count = actual_transfer_len / 4095; + remain_len = actual_transfer_len % 4095; + + if (remain_len) + { + malloc_count++; + } + + if(dma_device->lli_cfg) + { + mmheap_free(dma_device->lli_cfg); + dma_device->lli_cfg = (dma_lli_ctrl_t *)mmheap_alloc(sizeof(dma_lli_ctrl_t) * malloc_count); + } + else + { + dma_device->lli_cfg = (dma_lli_ctrl_t *)mmheap_alloc(sizeof(dma_lli_ctrl_t) * malloc_count); + } + + if (dma_device->lli_cfg) + { + /*transfer_size will be 4095 or 4095*2 or 4095*4 in different transfer width*/ + if ((!remain_len) && (malloc_count == 1)) + { + dma_device->lli_cfg[0].src_addr = src_addr; + dma_device->lli_cfg[0].dst_addr = dst_addr; + dma_device->lli_cfg[0].nextlli = 0; + dma_ctrl_cfg.bits.TransferSize = remain_len; + dma_ctrl_cfg.bits.I = 1; + memcpy(&dma_device->lli_cfg[0].cfg, &dma_ctrl_cfg, sizeof(dma_control_data_t)); + } + /*transfer_size will be 4095*n or 4095*2*n or 4095*4*n,(n>1) in different transfer width*/ + else if ((!remain_len) && (malloc_count > 1)) + { + for (uint32_t i = 0; i < malloc_count; i++) + { + dma_device->lli_cfg[i].src_addr = src_addr; + dma_device->lli_cfg[i].dst_addr = dst_addr; + dma_device->lli_cfg[i].nextlli = 0; + + dma_ctrl_cfg.bits.TransferSize = 4095; + dma_ctrl_cfg.bits.I = 0; + if (dma_ctrl_cfg.bits.SI) + src_addr += actual_transfer_offset; + if (dma_ctrl_cfg.bits.DI) + dst_addr += actual_transfer_offset; + + if (i == malloc_count - 1) + { + dma_ctrl_cfg.bits.I = 1; + + if (dma_device->transfer_mode == DMA_LLI_CYCLE_MODE) + dma_device->lli_cfg[i].nextlli = (uint32_t)&dma_device->lli_cfg[0]; + } + if (i) + { + dma_device->lli_cfg[i - 1].nextlli = (uint32_t)&dma_device->lli_cfg[i]; + } + memcpy(&dma_device->lli_cfg[i].cfg, &dma_ctrl_cfg, sizeof(dma_control_data_t)); + } + } + else + { + for (uint32_t i = 0; i < malloc_count; i++) + { + dma_device->lli_cfg[i].src_addr = src_addr; + dma_device->lli_cfg[i].dst_addr = dst_addr; + dma_device->lli_cfg[i].nextlli = 0; + + dma_ctrl_cfg.bits.TransferSize = 4095; + dma_ctrl_cfg.bits.I = 0; + if (dma_ctrl_cfg.bits.SI) + src_addr += actual_transfer_offset; + if (dma_ctrl_cfg.bits.DI) + dst_addr += actual_transfer_offset; + + if (i == malloc_count - 1) + { + dma_ctrl_cfg.bits.TransferSize = remain_len; + dma_ctrl_cfg.bits.I = 1; + + if (dma_device->transfer_mode == DMA_LLI_CYCLE_MODE) + dma_device->lli_cfg[i].nextlli = (uint32_t)&dma_device->lli_cfg[0]; + + } + if (i) + { + dma_device->lli_cfg[i - 1].nextlli = (uint32_t)&dma_device->lli_cfg[i]; + } + memcpy(&dma_device->lli_cfg[i].cfg, &dma_ctrl_cfg, sizeof(dma_control_data_t)); + } + } + DMA_LLI_Update(dma_device->ch, (uint32_t)dma_device->lli_cfg); + } + else + { + return -2; + } + + return 0; +} +/** + * @brief + * + * @param handle + */ +void dma_isr(dma_device_t *handle) +{ + uint32_t tmpVal; + uint32_t intClr; + + /* Get DMA register */ + if (handle->id == 0) + { + uint32_t DMAChs = DMA_BASE; + for (uint8_t i = 0; i < DMA_CH_MAX; i++) + { + tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS); + if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << handle[i].ch)) != 0) + { + /* Clear interrupt */ + tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR); + intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR); + intClr |= (1 << handle[i].ch); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr); + BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal); + + if (handle[i].parent.callback) + handle[i].parent.callback(&handle[i].parent, NULL, 0, DMA_INT_TCOMPLETED); + } + } + + for (uint8_t i = 0; i < DMA_CH_MAX; i++) + { + tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS); + if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << handle[i].ch)) != 0) + { + /*Clear interrupt */ + tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR); + intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR); + intClr |= (1 << handle[i].ch); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr); + BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal); + + if (handle[i].parent.callback) + handle[i].parent.callback(&handle->parent, NULL, 0, DMA_INT_ERR); + } + } + } + else + { + } +} +/** + * @brief + * + */ +void DMA0_IRQ(void) +{ + dma_isr(&dmax_device[0]); +} diff --git a/drivers/bl602_driver/hal_drv/src/hal_gpio.c b/drivers/bl602_driver/hal_drv/src/hal_gpio.c new file mode 100644 index 00000000..e75f7bdf --- /dev/null +++ b/drivers/bl602_driver/hal_drv/src/hal_gpio.c @@ -0,0 +1,218 @@ +/** + * ***************************************************************************** + * @file hal_gpio.c + * @version 0.1 + * @date 2021-03-01 + * @brief + * ***************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ***************************************************************************** + */ +#include "bl602_glb.h" +#include "bl602_gpio.h" +#include "hal_gpio.h" + +gpio_device_t gpio_device; +/** + * @brief + * + * @param pin + * @param mode + */ +void gpio_set_mode(uint32_t pin, uint32_t mode) +{ + GLB_GPIO_Cfg_Type gpio_cfg; + + gpio_cfg.gpioFun = GPIO_FUN_GPIO; + gpio_cfg.gpioPin = pin; + gpio_cfg.drive = 0; + gpio_cfg.smtCtrl = 1; + switch (mode) + { + case GPIO_OUTPUT_MODE: + gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; + gpio_cfg.pullType = GPIO_PULL_NONE; + break; + case GPIO_OUTPUT_PP_MODE: + gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; + gpio_cfg.pullType = GPIO_PULL_UP; + break; + case GPIO_OUTPUT_PD_MODE: + gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; + gpio_cfg.pullType = GPIO_PULL_DOWN; + break; + case GPIO_INPUT_MODE: + gpio_cfg.gpioMode = GPIO_MODE_INPUT; + gpio_cfg.pullType = GPIO_PULL_NONE; + break; + case GPIO_INPUT_PP_MODE: + gpio_cfg.gpioMode = GPIO_MODE_INPUT; + gpio_cfg.pullType = GPIO_PULL_UP; + break; + case GPIO_INPUT_PD_MODE: + gpio_cfg.gpioMode = GPIO_MODE_INPUT; + gpio_cfg.pullType = GPIO_PULL_DOWN; + break; + default: + NVIC_DisableIRQ(GPIO_INT0_IRQn); + GLB_GPIO_IntMask(pin, MASK); + + gpio_cfg.gpioMode = GPIO_MODE_INPUT; + + GLB_GPIO_INT0_IRQHandler_Install(); + if (mode == GPIO_ASYNC_RISING_TRIGER_INT_MODE) + { + gpio_cfg.pullType = GPIO_PULL_DOWN; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_POS_PULSE); + } + + else if (mode == GPIO_ASYNC_FALLING_TRIGER_INT_MODE) + { + gpio_cfg.pullType = GPIO_PULL_UP; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_NEG_PULSE); + } + + else if (mode == GPIO_ASYNC_HIGH_LEVEL_INT_MODE) + { + gpio_cfg.pullType = GPIO_PULL_DOWN; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_POS_LEVEL); + } + + else if (mode == GPIO_ASYNC_LOW_LEVEL_INT_MODE) + { + gpio_cfg.pullType = GPIO_PULL_UP; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_NEG_LEVEL); + } + + else if (mode == GPIO_SYNC_RISING_TRIGER_INT_MODE) + { + gpio_cfg.pullType = GPIO_PULL_DOWN; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_POS_PULSE); + } + + else if (mode == GPIO_SYNC_FALLING_TRIGER_INT_MODE) + { + gpio_cfg.pullType = GPIO_PULL_UP; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_NEG_PULSE); + } + + else if (mode == GPIO_SYNC_HIGH_LEVEL_INT_MODE) + { + gpio_cfg.pullType = GPIO_PULL_DOWN; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_POS_LEVEL); + } + + else if (mode == GPIO_SYNC_LOW_LEVEL_INT_MODE) + { + gpio_cfg.pullType = GPIO_PULL_UP; + GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_NEG_LEVEL); + } + + else + return; + NVIC_EnableIRQ(GPIO_INT0_IRQn); + break; + + } + GLB_GPIO_Init(&gpio_cfg); +} +/** + * @brief + * + * @param pin + * @param value + */ +void gpio_write(uint32_t pin, uint32_t value) +{ + GLB_GPIO_Write(pin, value); +} +/** + * @brief + * + * @param pin + */ +void gpio_toggle(uint32_t pin) +{ + +} +/** + * @brief + * + * @param pin + * @return int + */ +int gpio_read(uint32_t pin) +{ + return GLB_GPIO_Read(pin); +} +/** + * @brief + * + * @param pin + * @param cbFun + */ +void gpio_attach_irq(uint32_t pin, void (*cbFun)(void)) +{ + GLB_GPIO_INT0_Callback_Install(pin, cbFun); +} +/** + * @brief + * + * @param pin + * @param enabled + */ +void gpio_irq_enable(uint32_t pin, uint8_t enabled) +{ + if (enabled) + { + GLB_GPIO_IntMask(pin, UNMASK); + } + else + { + GLB_GPIO_IntMask(pin, MASK); + } + +} + +void pin_register(const char *name, uint16_t flag) +{ + struct device *dev; + dev = &(gpio_device.parent); + + dev->open = NULL; + dev->close = NULL; + dev->control = NULL; + dev->write = NULL; + dev->read = NULL; + + dev->status = DEVICE_UNREGISTER; + dev->type = DEVICE_CLASS_GPIO; + dev->handle = NULL; + + device_register(dev, name, flag); +} \ No newline at end of file diff --git a/drivers/bl602_driver/hal_drv/src/hal_mtimer.c b/drivers/bl602_driver/hal_drv/src/hal_mtimer.c new file mode 100644 index 00000000..6cd6f981 --- /dev/null +++ b/drivers/bl602_driver/hal_drv/src/hal_mtimer.c @@ -0,0 +1,147 @@ +/** + * @file hal_mtimer.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_mtimer.h" +#include "bl602_glb.h" + +static void (*systick_callback)(void); +static uint64_t next_compare_tick = 0; +static uint64_t current_set_ticks = 0; + +static void Systick_Handler(void) +{ + *(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIMECMP) = next_compare_tick; + systick_callback(); + next_compare_tick += current_set_ticks; +} + +/** + * @brief + * + * @param time + * @param interruptFun + */ +void mtimer_set_alarm_time(uint64_t ticks, void (*interruptfun)(void)) +{ + NVIC_DisableIRQ(MTIME_IRQn); + + uint32_t ulCurrentTimeHigh, ulCurrentTimeLow; + volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( CLIC_CTRL_ADDR + CLIC_MTIME + 4 ); + volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( CLIC_CTRL_ADDR + CLIC_MTIME ); + volatile uint32_t ulHartId = 0; + + current_set_ticks = ticks; + systick_callback = interruptfun; + + __asm volatile( "csrr %0, mhartid" : "=r"( ulHartId ) ); + do + { + ulCurrentTimeHigh = *pulTimeHigh; + ulCurrentTimeLow = *pulTimeLow; + } while( ulCurrentTimeHigh != *pulTimeHigh ); + + next_compare_tick = ( uint64_t ) ulCurrentTimeHigh; + next_compare_tick <<= 32ULL; + next_compare_tick |= ( uint64_t ) ulCurrentTimeLow; + next_compare_tick += ( uint64_t ) current_set_ticks; + + *(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIMECMP) = next_compare_tick; + + /* Prepare the time to use after the next tick interrupt. */ + next_compare_tick += ( uint64_t ) current_set_ticks; + + Interrupt_Handler_Register(MTIME_IRQn, Systick_Handler); + NVIC_EnableIRQ(MTIME_IRQn); +} + +/** + * @brief + * + * @return uint64_t + */ +uint64_t mtimer_get_time_ms() +{ + return mtimer_get_time_us()/1000; +} +/** + * @brief + * + * @return uint64_t + */ +uint64_t mtimer_get_time_us() +{ + + uint32_t tmpValLow, tmpValHigh, tmpValHigh1; + + do + { + tmpValLow = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME); + tmpValHigh = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME + 4); + tmpValHigh1 = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME + 4); + } while (tmpValHigh != tmpValHigh1); + + return (((uint64_t)tmpValHigh << 32) + tmpValLow); + +} +/** + * @brief + * + * @param time + */ +void mtimer_delay_ms(uint32_t time) +{ + uint64_t cnt = 0; + uint32_t clock = SystemCoreClockGet(); + uint64_t startTime = mtimer_get_time_ms(); + + while (mtimer_get_time_ms() - startTime < time) + { + cnt++; + /* assume BFLB_BSP_Get_Time_Ms take 32 cycles*/ + if (cnt > (time * (clock >> (10 + 5))) * 2) + { + break; + } + } +} +/** + * @brief + * + * @param time + */ +void mtimer_delay_us(uint32_t time) +{ + uint64_t cnt = 0; + uint32_t clock = SystemCoreClockGet(); + uint64_t startTime = mtimer_get_time_us(); + + while (mtimer_get_time_us() - startTime < time) + { + cnt++; + /* assume BFLB_BSP_Get_Time_Ms take 32 cycles*/ + if (cnt > (time * (clock >> (10 + 5))) * 2) + { + break; + } + } +} + diff --git a/drivers/bl602_driver/hal_drv/src/hal_uart.c b/drivers/bl602_driver/hal_drv/src/hal_uart.c new file mode 100644 index 00000000..50d0466a --- /dev/null +++ b/drivers/bl602_driver/hal_drv/src/hal_uart.c @@ -0,0 +1,418 @@ +/** + * ***************************************************************************** + * @file hal_uart.c + * @version 0.1 + * @date 2021-03-01 + * @brief + * ***************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ***************************************************************************** + */ +#include "hal_uart.h" +#include "hal_dma.h" +#include "hal_gpio.h" +#include "hal_clock.h" +#include "bl602_uart.h" +#include "bl602_glb.h" +#include "uart_config.h" + +#ifdef BSP_USING_UART0 +void UART0_IRQ(void); +#endif +#ifdef BSP_USING_UART1 +void UART1_IRQ(void); +#endif + +uart_device_t uartx_device[UART_MAX_INDEX] = +{ +#ifdef BSP_USING_UART0 + UART0_CONFIG, +#endif +#ifdef BSP_USING_UART1 + UART1_CONFIG, +#endif +}; +/** + * @brief + * + * @param dev + * @param oflag + * @return int + */ +int uart_open(struct device *dev, uint16_t oflag) +{ + uart_device_t *uart_device = (uart_device_t *)dev; + UART_FifoCfg_Type fifoCfg = {0}; + UART_CFG_Type uart_cfg = {0}; + + /* disable all interrupt */ + UART_IntMask(uart_device->id, UART_INT_ALL, MASK); + /* disable uart before config */ + UART_Disable(uart_device->id, UART_TXRX); + + uint32_t uart_clk = peripheral_clock_get(PERIPHERAL_CLOCK_UART); + + uart_cfg.baudRate = uart_device->baudrate; + uart_cfg.dataBits = uart_device->databits; + uart_cfg.stopBits = uart_device->stopbits; + uart_cfg.parity = uart_device->parity; + uart_cfg.uartClk = uart_clk; + uart_cfg.ctsFlowControl = UART_CTS_FLOWCONTROL_ENABLE; + uart_cfg.rtsSoftwareControl = UART_RTS_FLOWCONTROL_ENABLE; + uart_cfg.byteBitInverse = UART_MSB_FIRST_ENABLE; + + /* uart init with default configuration */ + UART_Init(uart_device->id, &uart_cfg); + + /* Enable tx free run mode */ + UART_TxFreeRun(uart_device->id, ENABLE); + + /* Set rx time-out value */ + UART_SetRxTimeoutValue(uart_device->id, UART_DEFAULT_RTO_TIMEOUT); + + fifoCfg.txFifoDmaThreshold = uart_device->fifo_threshold; + fifoCfg.txFifoDmaEnable = DISABLE; + fifoCfg.rxFifoDmaThreshold = uart_device->fifo_threshold; + fifoCfg.rxFifoDmaEnable = DISABLE; + + if (oflag & DEVICE_OFLAG_STREAM_TX) + { + } + if ((oflag & DEVICE_OFLAG_INT_TX) || (oflag & DEVICE_OFLAG_INT_RX)) + { +#ifdef BSP_USING_UART0 + if (uart_device->id == UART0_ID) + Interrupt_Handler_Register(UART0_IRQn, UART0_IRQ); +#endif +#ifdef BSP_USING_UART1 + if (uart_device->id == UART1_ID) + Interrupt_Handler_Register(UART1_IRQn, UART1_IRQ); +#endif + } + if (oflag & DEVICE_OFLAG_DMA_TX) + { + fifoCfg.txFifoDmaEnable = ENABLE; + } + if (oflag & DEVICE_OFLAG_DMA_RX) + { + fifoCfg.rxFifoDmaEnable = ENABLE; + } + + UART_FifoConfig(uart_device->id, &fifoCfg); + /* enable uart */ + UART_Enable(uart_device->id, UART_TXRX); + return 0; +} +/** + * @brief + * + * @param dev + * @return int + */ +int uart_close(struct device *dev) +{ + uart_device_t *uart_device = (uart_device_t *)dev; + + UART_Disable(uart_device->id, UART_TXRX); + return 0; +} +/** + * @brief + * + * @param dev + * @param cmd + * @param args + * @return int + */ +int uart_control(struct device *dev, int cmd, void *args) +{ + uart_device_t *uart_device = (uart_device_t *)dev; + + switch (cmd) + { + case DEVICE_CTRL_SET_INT /* constant-expression */: + { + uint32_t offset = __builtin_ctz((uint32_t)args); + while ((0 <= offset) && (offset < 9)) + { + if ((uint32_t)args & (1 << offset)) + { + UART_IntMask(uart_device->id, offset, UNMASK); + } + offset++; + } + if (uart_device->id == UART0_ID) + NVIC_EnableIRQ(UART0_IRQn); + else if (uart_device->id == UART1_ID) + NVIC_EnableIRQ(UART1_IRQn); + + break; + } + case DEVICE_CTRL_CLR_INT /* constant-expression */: + { + uint32_t offset = __builtin_ctz((uint32_t)args); + while ((0 <= offset) && (offset < 9)) + { + if ((uint32_t)args & (1 << offset)) + { + UART_IntMask(uart_device->id, offset, MASK); + } + offset++; + } + if (uart_device->id == UART0_ID) + NVIC_DisableIRQ(UART0_IRQn); + else if (uart_device->id == UART1_ID) + NVIC_DisableIRQ(UART1_IRQn); + + break; + } + case DEVICE_CTRL_GET_INT /* constant-expression */: + /* code */ + break; + case DEVICE_CTRL_CONFIG /* constant-expression */: + { + uart_param_cfg_t* cfg = (uart_param_cfg_t *)args; + UART_CFG_Type uart_cfg = {0}; + + /* Disable uart before config */ + UART_Disable(uart_device->id, UART_TXRX); + + uart_cfg.uartClk = 160*1000*1000; + uart_cfg.baudRate = cfg->baudrate; + uart_cfg.stopBits = cfg->stopbits; + uart_cfg.parity = cfg->parity; + uart_cfg.dataBits = cfg->databits; + uart_cfg.ctsFlowControl = UART_CTS_FLOWCONTROL_ENABLE; + uart_cfg.rtsSoftwareControl = UART_RTS_FLOWCONTROL_ENABLE; + uart_cfg.byteBitInverse = UART_MSB_FIRST_ENABLE; + UART_Init(uart_device->id, &uart_cfg); +#ifdef BSP_USING_UART0 + if (uart_device->id == UART0_ID) + Interrupt_Handler_Register(UART0_IRQn, UART0_IRQ); +#endif +#ifdef BSP_USING_UART1 + if (uart_device->id == UART1_ID) + Interrupt_Handler_Register(UART1_IRQn, UART1_IRQ); +#endif + /* Enable uart */ + UART_Enable(uart_device->id, UART_TXRX); + break; + } + case DEVICE_CTRL_GET_CONFIG /* constant-expression */: + break; + case DEVICE_CTRL_ATTACH_TX_DMA /* constant-expression */: + uart_device->tx_dma = (struct device *)args; + break; + case DEVICE_CTRL_ATTACH_RX_DMA /* constant-expression */: + uart_device->rx_dma = (struct device *)args; + break; + case DEVICE_CTRL_UART_GET_TX_FIFO /* constant-expression */: + return UART_GetTxFifoCount(uart_device->id); + case DEVICE_CTRL_UART_GET_RX_FIFO /* constant-expression */: + return UART_GetRxFifoCount(uart_device->id); + default: + break; + } + + return 0; +} +/** + * @brief + * + * @param dev + * @param pos + * @param buffer + * @param size + * @return int + */ +int uart_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) +{ + uart_device_t *uart_device = (uart_device_t *)dev; + if (dev->oflag & DEVICE_OFLAG_DMA_TX) + { + struct device *dma_ch = (struct device *)uart_device->tx_dma; + if (!dma_ch) + return -1; + + if(uart_device->id == 0) + { + dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_UART0_TDR, size); + dma_channel_start(dma_ch); + } + else if(uart_device->id == 1) + { + dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_UART1_TDR, size); + dma_channel_start(dma_ch); + } + return 0; + } + return UART_SendData(uart_device->id, (uint8_t *)buffer, size); +} +/** + * @brief + * + * @param dev + * @param pos + * @param buffer + * @param size + * @return int + */ +int uart_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) +{ + uart_device_t *uart_device = (uart_device_t *)dev; + if (dev->oflag & DEVICE_OFLAG_DMA_RX) + { + struct device *dma_ch = (struct device *)uart_device->rx_dma; + if (!dma_ch) + return -1; + } + return UART_ReceiveData(uart_device->id, (uint8_t *)buffer, size); +} +/** + * @brief + * + * @param index + * @param name + * @param flag + * @return int + */ +int uart_register(enum uart_index_type index, const char *name, uint16_t flag) +{ + struct device *dev; + + if(UART_MAX_INDEX == 0) + return -DEVICE_EINVAL; + + dev = &(uartx_device[index].parent); + + dev->open = uart_open; + dev->close = uart_close; + dev->control = uart_control; + dev->write = uart_write; + dev->read = uart_read; + + dev->status = DEVICE_UNREGISTER; + dev->type = DEVICE_CLASS_UART; + dev->handle = NULL; + + return device_register(dev, name, flag); +} +/** + * @brief + * + * @param handle + */ +void uart_isr(uart_device_t *handle) +{ + uint32_t tmpVal = 0; + uint32_t maskVal = 0; + uint32_t UARTx = (UART0_BASE + handle->id * 0x100); + + tmpVal = BL_RD_REG(UARTx, UART_INT_STS); + maskVal = BL_RD_REG(UARTx, UART_INT_MASK); + + if (!handle->parent.callback) + return; + + /* Length of uart tx data transfer arrived interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_END_MASK)) + { + BL_WR_REG(UARTx, UART_INT_CLEAR, 0x1); + handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_TX_END); + } + + /* Length of uart rx data transfer arrived interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_END_MASK)) + { + BL_WR_REG(UARTx, UART_INT_CLEAR, 0x2); + handle->parent.callback(&handle->parent,NULL, 0, UART_EVENT_RX_END); + } + + /* Tx fifo ready interrupt,auto-cleared when data is pushed */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FIFO_MASK)) + { + handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_TX_FIFO); + } + + /* Rx fifo ready interrupt,auto-cleared when data is popped */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FIFO_MASK)) + { + uint8_t buffer[UART_FIFO_MAX_LEN]; + UART_ReceiveData(handle->id, buffer, handle->fifo_threshold); + handle->parent.callback(&handle->parent, &buffer[0], handle->fifo_threshold, UART_EVENT_RX_FIFO); + } + + /* Rx time-out interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK)) + { + uint8_t buffer[UART_FIFO_MAX_LEN]; + uint8_t len = UART_ReceiveData(handle->id, buffer, handle->fifo_threshold); + handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RTO); + BL_WR_REG(UARTx, UART_INT_CLEAR, 0x10); + } + + /* Rx parity check error interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_PCE_MASK)) + { + BL_WR_REG(UARTx, UART_INT_CLEAR, 0x20); + handle->parent.callback(&handle->parent, NULL, 0, UART_PCE_IT); + } + + /* Tx fifo overflow/underflow error interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FER_MASK)) + { + handle->parent.callback(&handle->parent, NULL, 0, UART_TX_FER_IT); + } + + /* Rx fifo overflow/underflow error interrupt */ + if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FER_MASK)) + { + handle->parent.callback(&handle->parent, NULL, 0, UART_RX_FER_IT); + } +} + +#ifdef BSP_USING_UART0 +/** + * @brief + * + */ +void UART0_IRQ(void) +{ + uart_isr(&uartx_device[UART0_INDEX]); +} +#endif +#ifdef BSP_USING_UART1 +/** + * @brief + * + */ +void UART1_IRQ(void) +{ + uart_isr(&uartx_device[UART1_INDEX]); +} +#endif \ No newline at end of file diff --git a/drivers/bl602_driver/regs/aon_reg.h b/drivers/bl602_driver/regs/aon_reg.h new file mode 100644 index 00000000..70682460 --- /dev/null +++ b/drivers/bl602_driver/regs/aon_reg.h @@ -0,0 +1,1535 @@ +/** + ****************************************************************************** + * @file aon_reg.h + * @version V1.2 + * @date 2020-04-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __AON_REG_H__ +#define __AON_REG_H__ + +#include "bl602.h" + +/* 0x800 : aon */ +#define AON_OFFSET (0x800) +#define AON_RESV AON_RESV +#define AON_RESV_POS (0U) +#define AON_RESV_LEN (8U) +#define AON_RESV_MSK (((1U< +#include +/* ARM CPU include files */ +#ifdef ARCH_ARM +#ifdef CPU_AP_CM4 + #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#endif +#ifdef CPU_NP_CM0 + #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ +#endif +#endif +/* RISCV CPU include files */ +#ifdef ARCH_RISCV +#ifdef __GNUC__ + #include "cmsis_compatible_gcc.h" + #include "clic.h" + #include "riscv_encoding.h" +#endif +#endif + +/** + * @} + */ + + + + + + + +#endif diff --git a/drivers/bl602_driver/regs/cci_reg.h b/drivers/bl602_driver/regs/cci_reg.h new file mode 100644 index 00000000..57388ec5 --- /dev/null +++ b/drivers/bl602_driver/regs/cci_reg.h @@ -0,0 +1,190 @@ +/** + ****************************************************************************** + * @file cci_reg.h + * @version V1.2 + * @date 2019-11-12 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __CCI_REG_H__ +#define __CCI_REG_H__ + +#include "bl602.h" + +/* 0x0 : cci_cfg */ +#define CCI_CFG_OFFSET (0x0) +#define CCI_EN CCI_EN +#define CCI_EN_POS (0U) +#define CCI_EN_LEN (1U) +#define CCI_EN_MSK (((1U<
© COPYRIGHT(c) 2019 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __CKS_REG_H__ +#define __CKS_REG_H__ + +#include "bl602.h" + +/* 0x0 : cks_config */ +#define CKS_CONFIG_OFFSET (0x0) +#define CKS_CR_CKS_CLR CKS_CR_CKS_CLR +#define CKS_CR_CKS_CLR_POS (0U) +#define CKS_CR_CKS_CLR_LEN (1U) +#define CKS_CR_CKS_CLR_MSK (((1U<
© COPYRIGHT(c) 2019 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __DMA_REG_H__ +#define __DMA_REG_H__ + +#include "bl602.h" + +/* 0x0 : DMA_IntStatus */ +#define DMA_INTSTATUS_OFFSET (0x0) +#define DMA_INTSTATUS DMA_INTSTATUS +#define DMA_INTSTATUS_POS (0U) +#define DMA_INTSTATUS_LEN (8U) +#define DMA_INTSTATUS_MSK (((1U<
© COPYRIGHT(c) 2019 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __EF_CTRL_REG_H__ +#define __EF_CTRL_REG_H__ + +#include "bl602.h" + +/* 0x800 : ef_if_ctrl_0 */ +#define EF_CTRL_EF_IF_CTRL_0_OFFSET (0x800) +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS (0U) +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN (1U) +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_MSK (((1U<
© COPYRIGHT(c) 2019 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __EF_DATA_0_REG_H__ +#define __EF_DATA_0_REG_H__ + +#include "bl602.h" + +/* 0x0 : ef_cfg_0 */ +#define EF_DATA_0_EF_CFG_0_OFFSET (0x0) +#define EF_DATA_0_EF_SF_AES_MODE EF_DATA_0_EF_SF_AES_MODE +#define EF_DATA_0_EF_SF_AES_MODE_POS (0U) +#define EF_DATA_0_EF_SF_AES_MODE_LEN (2U) +#define EF_DATA_0_EF_SF_AES_MODE_MSK (((1U<
© COPYRIGHT(c) 2019 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __EF_DATA_1_REG_H__ +#define __EF_DATA_1_REG_H__ + +#include "bl602.h" + +/* 0x80 : reg_key_slot_6_w0 */ +#define EF_DATA_1_REG_KEY_SLOT_6_W0_OFFSET (0x80) +#define EF_DATA_1_REG_KEY_SLOT_6_W0 EF_DATA_1_REG_KEY_SLOT_6_W0 +#define EF_DATA_1_REG_KEY_SLOT_6_W0_POS (0U) +#define EF_DATA_1_REG_KEY_SLOT_6_W0_LEN (32U) +#define EF_DATA_1_REG_KEY_SLOT_6_W0_MSK (((1U<
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __GLB_REG_H__ +#define __GLB_REG_H__ + +#include "bl602.h" + +/* 0x0 : clk_cfg0 */ +#define GLB_CLK_CFG0_OFFSET (0x0) +#define GLB_REG_PLL_EN GLB_REG_PLL_EN +#define GLB_REG_PLL_EN_POS (0U) +#define GLB_REG_PLL_EN_LEN (1U) +#define GLB_REG_PLL_EN_MSK (((1U<
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __GPIP_REG_H__ +#define __GPIP_REG_H__ + +#include "bl602.h" + +/* 0x0 : gpadc_config */ +#define GPIP_GPADC_CONFIG_OFFSET (0x0) +#define GPIP_GPADC_DMA_EN GPIP_GPADC_DMA_EN +#define GPIP_GPADC_DMA_EN_POS (0U) +#define GPIP_GPADC_DMA_EN_LEN (1U) +#define GPIP_GPADC_DMA_EN_MSK (((1U<
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HBN_REG_H__ +#define __HBN_REG_H__ + +#include "bl602.h" + +/* 0x0 : HBN_CTL */ +#define HBN_CTL_OFFSET (0x0) +#define HBN_RTC_CTL HBN_RTC_CTL +#define HBN_RTC_CTL_POS (0U) +#define HBN_RTC_CTL_LEN (7U) +#define HBN_RTC_CTL_MSK (((1U<
© COPYRIGHT(c) 2019 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __I2C_REG_H__ +#define __I2C_REG_H__ + +#include "bl602.h" + +/* 0x0 : i2c_config */ +#define I2C_CONFIG_OFFSET (0x0) +#define I2C_CR_I2C_M_EN I2C_CR_I2C_M_EN +#define I2C_CR_I2C_M_EN_POS (0U) +#define I2C_CR_I2C_M_EN_LEN (1U) +#define I2C_CR_I2C_M_EN_MSK (((1U<
© COPYRIGHT(c) 2019 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __IR_REG_H__ +#define __IR_REG_H__ + +#include "bl602.h" + +/* 0x0 : irtx_config */ +#define IRTX_CONFIG_OFFSET (0x0) +#define IR_CR_IRTX_EN IR_CR_IRTX_EN +#define IR_CR_IRTX_EN_POS (0U) +#define IR_CR_IRTX_EN_LEN (1U) +#define IR_CR_IRTX_EN_MSK (((1U<
© COPYRIGHT(c) 2019 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __L1C_REG_H__ +#define __L1C_REG_H__ + +#include "bl602.h" + +/* 0x0 : l1c_config */ +#define L1C_CONFIG_OFFSET (0x0) +#define L1C_CACHEABLE L1C_CACHEABLE +#define L1C_CACHEABLE_POS (0U) +#define L1C_CACHEABLE_LEN (1U) +#define L1C_CACHEABLE_MSK (((1U<
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __PDS_REG_H__ +#define __PDS_REG_H__ + +#include "bl602.h" + +/* 0x0 : PDS_CTL */ +#define PDS_CTL_OFFSET (0x0) +#define PDS_START_PS PDS_START_PS +#define PDS_START_PS_POS (0U) +#define PDS_START_PS_LEN (1U) +#define PDS_START_PS_MSK (((1U<
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __PWM_REG_H__ +#define __PWM_REG_H__ + +#include "bl602.h" + +/* 0x0 : pwm_int_config */ +#define PWM_INT_CONFIG_OFFSET (0x0) +#define PWM_INTERRUPT_STS PWM_INTERRUPT_STS +#define PWM_INTERRUPT_STS_POS (0U) +#define PWM_INTERRUPT_STS_LEN (6U) +#define PWM_INTERRUPT_STS_MSK (((1U<
© COPYRIGHT(c) 2018 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __RF_FPGA_REG_H__ +#define __RF_FPGA_REG_H__ + +#include "bl602.h" + +/* 0x600 : rf_fpga_ctrl_0 */ +#define RF_FPGA_CTRL_0_OFFSET (0x600) +#define RF_FPGA_RF_FSM_ST_CCI_4S RF_FPGA_RF_FSM_ST_CCI_4S +#define RF_FPGA_RF_FSM_ST_CCI_4S_POS (0U) +#define RF_FPGA_RF_FSM_ST_CCI_4S_LEN (5U) +#define RF_FPGA_RF_FSM_ST_CCI_4S_MSK (((1U<
© COPYRIGHT(c) 2019 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __RF_REG_H__ +#define __RF_REG_H__ + +#include "bl602.h" + +/* 0x0 : Silicon revision */ +#define RF_REV_OFFSET (0x0) +#define RF_ID RF_ID +#define RF_ID_POS (0U) +#define RF_ID_LEN (8U) +#define RF_ID_MSK (((1U<
© COPYRIGHT(c) 2019 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __SEC_DBG_REG_H__ +#define __SEC_DBG_REG_H__ + +#include "bl602.h" + +/* 0x0 : sd_chip_id_low */ +#define SEC_DBG_SD_CHIP_ID_LOW_OFFSET (0x0) +#define SEC_DBG_SD_CHIP_ID_LOW SEC_DBG_SD_CHIP_ID_LOW +#define SEC_DBG_SD_CHIP_ID_LOW_POS (0U) +#define SEC_DBG_SD_CHIP_ID_LOW_LEN (32U) +#define SEC_DBG_SD_CHIP_ID_LOW_MSK (((1U<
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __SEC_ENG_REG_H__ +#define __SEC_ENG_REG_H__ + +#include "bl602.h" + +/* 0x0 : se_sha_0_ctrl */ +#define SEC_ENG_SE_SHA_0_CTRL_OFFSET (0x0) +#define SEC_ENG_SE_SHA_0_BUSY SEC_ENG_SE_SHA_0_BUSY +#define SEC_ENG_SE_SHA_0_BUSY_POS (0U) +#define SEC_ENG_SE_SHA_0_BUSY_LEN (1U) +#define SEC_ENG_SE_SHA_0_BUSY_MSK (((1U<
© COPYRIGHT(c) 2019 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __SF_CTRL_REG_H__ +#define __SF_CTRL_REG_H__ + +#include "bl602.h" + +/* 0x0 : sf_ctrl_0 */ +#define SF_CTRL_0_OFFSET (0x0) +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL SF_CTRL_SF_CLK_SF_RX_INV_SEL +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS (2U) +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN (1U) +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_MSK (((1U< + + bouffalolab + bouffalolab + 602 + WiFi BT + high-performance, 32-bit RV32IMAFC core + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + 602 + little + + + + glb + glb. + 0x40000000 + glb + 32 + read-write + + 0 + 0x1000 + registers + + + + clk_cfg0 + clk_cfg0. + 0x0 + + + glb_id + 28 + 31 + + + chip_rdy + 27 + 27 + + + fclk_sw_state + 24 + 26 + + + reg_bclk_div + 16 + 23 + + + reg_hclk_div + 8 + 15 + + + hbn_root_clk_sel + 6 + 7 + + + reg_pll_sel + 4 + 5 + + + reg_bclk_en + 3 + 3 + + + reg_hclk_en + 2 + 2 + + + reg_fclk_en + 1 + 1 + + + reg_pll_en + 0 + 0 + + + + + clk_cfg1 + clk_cfg1. + 0x4 + + + ble_en + 24 + 24 + + + ble_clk_sel + 16 + 21 + + + wifi_mac_wt_div + 4 + 7 + + + wifi_mac_core_div + 0 + 3 + + + + + clk_cfg2 + clk_cfg2. + 0x8 + + + dma_clk_en + 24 + 31 + + + ir_clk_en + 23 + 23 + + + ir_clk_div + 16 + 21 + + + sf_clk_sel2 + 14 + 15 + + + sf_clk_sel + 12 + 13 + + + sf_clk_en + 11 + 11 + + + sf_clk_div + 8 + 10 + + + hbn_uart_clk_sel + 7 + 7 + + + uart_clk_en + 4 + 4 + + + uart_clk_div + 0 + 2 + + + + + clk_cfg3 + clk_cfg3. + 0xC + + + i2c_clk_en + 24 + 24 + + + i2c_clk_div + 16 + 23 + + + spi_clk_en + 8 + 8 + + + spi_clk_div + 0 + 4 + + + + + swrst_cfg0 + swrst_cfg0. + 0x10 + + + swrst_s30 + 8 + 8 + + + swrst_s20 + 4 + 4 + + + swrst_s01 + 1 + 1 + + + swrst_s00 + 0 + 0 + + + + + swrst_cfg1 + swrst_cfg1. + 0x14 + + + swrst_s1a7 + 23 + 23 + + + swrst_s1a6 + 22 + 22 + + + swrst_s1a5 + 21 + 21 + + + swrst_s1a4 + 20 + 20 + + + swrst_s1a3 + 19 + 19 + + + swrst_s1a2 + 18 + 18 + + + swrst_s1a1 + 17 + 17 + + + swrst_s1a0 + 16 + 16 + + + swrst_s1f + 15 + 15 + + + swrst_s1e + 14 + 14 + + + swrst_s1d + 13 + 13 + + + swrst_s1c + 12 + 12 + + + swrst_s1b + 11 + 11 + + + swrst_s1a + 10 + 10 + + + swrst_s19 + 9 + 9 + + + swrst_s18 + 8 + 8 + + + swrst_s17 + 7 + 7 + + + swrst_s16 + 6 + 6 + + + swrst_s15 + 5 + 5 + + + swrst_s14 + 4 + 4 + + + swrst_s13 + 3 + 3 + + + swrst_s12 + 2 + 2 + + + swrst_s11 + 1 + 1 + + + swrst_s10 + 0 + 0 + + + + + swrst_cfg2 + swrst_cfg2. + 0x18 + + + pka_clk_sel + 24 + 24 + + + reg_ctrl_reset_dummy + 4 + 7 + + + reg_ctrl_sys_reset + 2 + 2 + + + reg_ctrl_cpu_reset + 1 + 1 + + + reg_ctrl_pwron_rst + 0 + 0 + + + + + swrst_cfg3 + swrst_cfg3. + 0x1C + + + + cgen_cfg0 + cgen_cfg0. + 0x20 + + + cgen_m + 0 + 7 + + + + + cgen_cfg1 + cgen_cfg1. + 0x24 + + + cgen_s1a + 16 + 23 + + + cgen_s1 + 0 + 15 + + + + + cgen_cfg2 + cgen_cfg2. + 0x28 + + + cgen_s3 + 4 + 4 + + + cgen_s2 + 0 + 0 + + + + + cgen_cfg3 + cgen_cfg3. + 0x2C + + + + MBIST_CTL + MBIST_CTL. + 0x30 + + + reg_mbist_rst_n + 31 + 31 + + + wifi_mbist_mode + 4 + 4 + + + ocram_mbist_mode + 3 + 3 + + + tag_mbist_mode + 2 + 2 + + + hsram_mbist_mode + 1 + 1 + + + irom_mbist_mode + 0 + 0 + + + + + MBIST_STAT + MBIST_STAT. + 0x34 + + + wifi_mbist_fail + 20 + 20 + + + ocram_mbist_fail + 19 + 19 + + + tag_mbist_fail + 18 + 18 + + + hsram_mbist_fail + 17 + 17 + + + irom_mbist_fail + 16 + 16 + + + wifi_mbist_done + 4 + 4 + + + ocram_mbist_done + 3 + 3 + + + tag_mbist_done + 2 + 2 + + + hsram_mbist_done + 1 + 1 + + + irom_mbist_done + 0 + 0 + + + + + bmx_cfg1 + bmx_cfg1. + 0x50 + + + hbn_apb_cfg + 24 + 31 + + + pds_apb_cfg + 16 + 23 + + + hsel_option + 12 + 15 + + + bmx_gating_dis + 10 + 10 + + + bmx_busy_option_dis + 9 + 9 + + + bmx_err_en + 8 + 8 + + + bmx_arb_mode + 4 + 5 + + + bmx_timeout_en + 0 + 3 + + + + + bmx_cfg2 + bmx_cfg2. + 0x54 + + + bmx_dbg_sel + 28 + 31 + + + bmx_err_tz + 5 + 5 + + + bmx_err_dec + 4 + 4 + + + bmx_err_addr_dis + 0 + 0 + + + + + bmx_err_addr + bmx_err_addr. + 0x58 + + + bmx_err_addr + 0 + 31 + + + + + bmx_dbg_out + bmx_dbg_out. + 0x5C + + + bmx_dbg_out + 0 + 31 + + + + + rsv0 + rsv0. + 0x60 + + + rsvd_31_0 + 0 + 31 + + + + + rsv1 + rsv1. + 0x64 + + + rsvd_31_0 + 0 + 31 + + + + + rsv2 + rsv2. + 0x68 + + + rsvd_31_0 + 0 + 31 + + + + + rsv3 + rsv3. + 0x6C + + + rsvd_31_0 + 0 + 31 + + + + + sram_ret + sram_ret. + 0x70 + + + reg_sram_ret + 0 + 31 + + + + + sram_slp + sram_slp. + 0x74 + + + reg_sram_slp + 0 + 31 + + + + + sram_parm + sram_parm. + 0x78 + + + reg_sram_parm + 0 + 31 + + + + + seam_misc + seam_misc. + 0x7C + + + em_sel + 0 + 3 + + + + + glb_parm + glb_parm. + 0x80 + + + uart_swap_set + 24 + 26 + + + p7_jtag_use_io_2_5 + 23 + 23 + + + p6_sdio_use_io_0_5 + 22 + 22 + + + p5_dac_test_with_jtag + 21 + 21 + + + p4_adc_test_with_jtag + 20 + 20 + + + p3_cci_use_io_2_5 + 19 + 19 + + + p2_dac_test_with_cci + 18 + 18 + + + p1_adc_test_with_cci + 17 + 17 + + + reg_cci_use_sdio_pin + 16 + 16 + + + reg_cci_use_jtag_pin + 15 + 15 + + + reg_spi_0_swap + 13 + 13 + + + reg_spi_0_master_mode + 12 + 12 + + + sel_embedded_sflash + 9 + 9 + + + swap_sflash_io_3_io_0 + 8 + 8 + + + jtag_swap_set + 2 + 7 + + + reg_ext_rst_smt + 1 + 1 + + + reg_bd_en + 0 + 0 + + + + + CPU_CLK_CFG + CPU_CLK_CFG. + 0x90 + + + debug_ndreset_gate + 20 + 20 + + + cpu_rtc_sel + 19 + 19 + + + cpu_rtc_en + 18 + 18 + + + cpu_rtc_div + 0 + 16 + + + + + GPADC_32M_SRC_CTRL + GPADC_32M_SRC_CTRL. + 0xA4 + + + gpadc_32m_div_en + 8 + 8 + + + gpadc_32m_clk_sel + 7 + 7 + + + gpadc_32m_clk_div + 0 + 5 + + + + + DIG32K_WAKEUP_CTRL + DIG32K_WAKEUP_CTRL. + 0xA8 + + + reg_en_platform_wakeup + 31 + 31 + + + dig_clk_src_sel + 28 + 28 + + + dig_512k_comp + 25 + 25 + + + dig_512k_en + 24 + 24 + + + dig_512k_div + 16 + 22 + + + dig_32k_comp + 13 + 13 + + + dig_32k_en + 12 + 12 + + + dig_32k_div + 0 + 10 + + + + + WIFI_BT_COEX_CTRL + WIFI_BT_COEX_CTRL. + 0xAC + + + en_gpio_bt_coex + 12 + 12 + + + coex_bt_bw + 11 + 11 + + + coex_bt_pti + 7 + 10 + + + coex_bt_channel + 0 + 6 + + + + + UART_SIG_SEL_0 + UART_SIG_SEL_0. + 0xC0 + + + uart_sig_7_sel + 28 + 31 + + + uart_sig_6_sel + 24 + 27 + + + uart_sig_5_sel + 20 + 23 + + + uart_sig_4_sel + 16 + 19 + + + uart_sig_3_sel + 12 + 15 + + + uart_sig_2_sel + 8 + 11 + + + uart_sig_1_sel + 4 + 7 + + + uart_sig_0_sel + 0 + 3 + + + + + DBG_SEL_LL + DBG_SEL_LL. + 0xD0 + + + reg_dbg_ll_ctrl + 0 + 31 + + + + + DBG_SEL_LH + DBG_SEL_LH. + 0xD4 + + + reg_dbg_lh_ctrl + 0 + 31 + + + + + DBG_SEL_HL + DBG_SEL_HL. + 0xD8 + + + reg_dbg_hl_ctrl + 0 + 31 + + + + + DBG_SEL_HH + DBG_SEL_HH. + 0xDC + + + reg_dbg_hh_ctrl + 0 + 31 + + + + + debug + debug. + 0xE0 + + + debug_i + 1 + 31 + + + debug_oe + 0 + 0 + + + + + GPIO_CFGCTL0 + GPIO_CFGCTL0. + 0x100 + + + real_gpio_1_func_sel + 28 + 31 + + + reg_gpio_1_func_sel + 24 + 27 + + + reg_gpio_1_pd + 21 + 21 + + + reg_gpio_1_pu + 20 + 20 + + + reg_gpio_1_drv + 18 + 19 + + + reg_gpio_1_smt + 17 + 17 + + + reg_gpio_1_ie + 16 + 16 + + + real_gpio_0_func_sel + 12 + 15 + + + reg_gpio_0_func_sel + 8 + 11 + + + reg_gpio_0_pd + 5 + 5 + + + reg_gpio_0_pu + 4 + 4 + + + reg_gpio_0_drv + 2 + 3 + + + reg_gpio_0_smt + 1 + 1 + + + reg_gpio_0_ie + 0 + 0 + + + + + GPIO_CFGCTL1 + GPIO_CFGCTL1. + 0x104 + + + real_gpio_3_func_sel + 28 + 31 + + + reg_gpio_3_func_sel + 24 + 27 + + + reg_gpio_3_pd + 21 + 21 + + + reg_gpio_3_pu + 20 + 20 + + + reg_gpio_3_drv + 18 + 19 + + + reg_gpio_3_smt + 17 + 17 + + + reg_gpio_3_ie + 16 + 16 + + + real_gpio_2_func_sel + 12 + 15 + + + reg_gpio_2_func_sel + 8 + 11 + + + reg_gpio_2_pd + 5 + 5 + + + reg_gpio_2_pu + 4 + 4 + + + reg_gpio_2_drv + 2 + 3 + + + reg_gpio_2_smt + 1 + 1 + + + reg_gpio_2_ie + 0 + 0 + + + + + GPIO_CFGCTL2 + GPIO_CFGCTL2. + 0x108 + + + real_gpio_5_func_sel + 28 + 31 + + + reg_gpio_5_func_sel + 24 + 27 + + + reg_gpio_5_pd + 21 + 21 + + + reg_gpio_5_pu + 20 + 20 + + + reg_gpio_5_drv + 18 + 19 + + + reg_gpio_5_smt + 17 + 17 + + + reg_gpio_5_ie + 16 + 16 + + + real_gpio_4_func_sel + 12 + 15 + + + reg_gpio_4_func_sel + 8 + 11 + + + reg_gpio_4_pd + 5 + 5 + + + reg_gpio_4_pu + 4 + 4 + + + reg_gpio_4_drv + 2 + 3 + + + reg_gpio_4_smt + 1 + 1 + + + reg_gpio_4_ie + 0 + 0 + + + + + GPIO_CFGCTL3 + GPIO_CFGCTL3. + 0x10C + + + reg_gpio_7_func_sel + 24 + 27 + + + reg_gpio_7_pd + 21 + 21 + + + reg_gpio_7_pu + 20 + 20 + + + reg_gpio_7_drv + 18 + 19 + + + reg_gpio_7_smt + 17 + 17 + + + reg_gpio_7_ie + 16 + 16 + + + reg_gpio_6_func_sel + 8 + 11 + + + reg_gpio_6_pd + 5 + 5 + + + reg_gpio_6_pu + 4 + 4 + + + reg_gpio_6_drv + 2 + 3 + + + reg_gpio_6_smt + 1 + 1 + + + reg_gpio_6_ie + 0 + 0 + + + + + GPIO_CFGCTL4 + GPIO_CFGCTL4. + 0x110 + + + reg_gpio_9_func_sel + 24 + 27 + + + reg_gpio_9_pd + 21 + 21 + + + reg_gpio_9_pu + 20 + 20 + + + reg_gpio_9_drv + 18 + 19 + + + reg_gpio_9_smt + 17 + 17 + + + reg_gpio_9_ie + 16 + 16 + + + reg_gpio_8_func_sel + 8 + 11 + + + reg_gpio_8_pd + 5 + 5 + + + reg_gpio_8_pu + 4 + 4 + + + reg_gpio_8_drv + 2 + 3 + + + reg_gpio_8_smt + 1 + 1 + + + reg_gpio_8_ie + 0 + 0 + + + + + GPIO_CFGCTL5 + GPIO_CFGCTL5. + 0x114 + + + reg_gpio_11_func_sel + 24 + 27 + + + reg_gpio_11_pd + 21 + 21 + + + reg_gpio_11_pu + 20 + 20 + + + reg_gpio_11_drv + 18 + 19 + + + reg_gpio_11_smt + 17 + 17 + + + reg_gpio_11_ie + 16 + 16 + + + reg_gpio_10_func_sel + 8 + 11 + + + reg_gpio_10_pd + 5 + 5 + + + reg_gpio_10_pu + 4 + 4 + + + reg_gpio_10_drv + 2 + 3 + + + reg_gpio_10_smt + 1 + 1 + + + reg_gpio_10_ie + 0 + 0 + + + + + GPIO_CFGCTL6 + GPIO_CFGCTL6. + 0x118 + + + reg_gpio_13_func_sel + 24 + 27 + + + reg_gpio_13_pd + 21 + 21 + + + reg_gpio_13_pu + 20 + 20 + + + reg_gpio_13_drv + 18 + 19 + + + reg_gpio_13_smt + 17 + 17 + + + reg_gpio_13_ie + 16 + 16 + + + reg_gpio_12_func_sel + 8 + 11 + + + reg_gpio_12_pd + 5 + 5 + + + reg_gpio_12_pu + 4 + 4 + + + reg_gpio_12_drv + 2 + 3 + + + reg_gpio_12_smt + 1 + 1 + + + reg_gpio_12_ie + 0 + 0 + + + + + GPIO_CFGCTL7 + GPIO_CFGCTL7. + 0x11C + + + reg_gpio_15_func_sel + 24 + 27 + + + reg_gpio_15_pd + 21 + 21 + + + reg_gpio_15_pu + 20 + 20 + + + reg_gpio_15_drv + 18 + 19 + + + reg_gpio_15_smt + 17 + 17 + + + reg_gpio_15_ie + 16 + 16 + + + reg_gpio_14_func_sel + 8 + 11 + + + reg_gpio_14_pd + 5 + 5 + + + reg_gpio_14_pu + 4 + 4 + + + reg_gpio_14_drv + 2 + 3 + + + reg_gpio_14_smt + 1 + 1 + + + reg_gpio_14_ie + 0 + 0 + + + + + GPIO_CFGCTL8 + GPIO_CFGCTL8. + 0x120 + + + reg_gpio_17_func_sel + 24 + 27 + + + reg_gpio_17_pd + 21 + 21 + + + reg_gpio_17_pu + 20 + 20 + + + reg_gpio_17_drv + 18 + 19 + + + reg_gpio_17_smt + 17 + 17 + + + reg_gpio_17_ie + 16 + 16 + + + reg_gpio_16_func_sel + 8 + 11 + + + reg_gpio_16_pd + 5 + 5 + + + reg_gpio_16_pu + 4 + 4 + + + reg_gpio_16_drv + 2 + 3 + + + reg_gpio_16_smt + 1 + 1 + + + reg_gpio_16_ie + 0 + 0 + + + + + GPIO_CFGCTL9 + GPIO_CFGCTL9. + 0x124 + + + reg_gpio_19_func_sel + 24 + 27 + + + reg_gpio_19_pd + 21 + 21 + + + reg_gpio_19_pu + 20 + 20 + + + reg_gpio_19_drv + 18 + 19 + + + reg_gpio_19_smt + 17 + 17 + + + reg_gpio_19_ie + 16 + 16 + + + reg_gpio_18_func_sel + 8 + 11 + + + reg_gpio_18_pd + 5 + 5 + + + reg_gpio_18_pu + 4 + 4 + + + reg_gpio_18_drv + 2 + 3 + + + reg_gpio_18_smt + 1 + 1 + + + reg_gpio_18_ie + 0 + 0 + + + + + GPIO_CFGCTL10 + GPIO_CFGCTL10. + 0x128 + + + reg_gpio_21_func_sel + 24 + 27 + + + reg_gpio_21_pd + 21 + 21 + + + reg_gpio_21_pu + 20 + 20 + + + reg_gpio_21_drv + 18 + 19 + + + reg_gpio_21_smt + 17 + 17 + + + reg_gpio_21_ie + 16 + 16 + + + reg_gpio_20_func_sel + 8 + 11 + + + reg_gpio_20_pd + 5 + 5 + + + reg_gpio_20_pu + 4 + 4 + + + reg_gpio_20_drv + 2 + 3 + + + reg_gpio_20_smt + 1 + 1 + + + reg_gpio_20_ie + 0 + 0 + + + + + GPIO_CFGCTL11 + GPIO_CFGCTL11. + 0x12C + + + reg_gpio_23_pd + 21 + 21 + + + reg_gpio_23_pu + 20 + 20 + + + reg_gpio_23_drv + 18 + 19 + + + reg_gpio_23_smt + 17 + 17 + + + reg_gpio_23_ie + 16 + 16 + + + reg_gpio_22_func_sel + 8 + 11 + + + reg_gpio_22_pd + 5 + 5 + + + reg_gpio_22_pu + 4 + 4 + + + reg_gpio_22_drv + 2 + 3 + + + reg_gpio_22_smt + 1 + 1 + + + reg_gpio_22_ie + 0 + 0 + + + + + GPIO_CFGCTL12 + GPIO_CFGCTL12. + 0x130 + + + reg_gpio_25_pd + 21 + 21 + + + reg_gpio_25_pu + 20 + 20 + + + reg_gpio_25_drv + 18 + 19 + + + reg_gpio_25_smt + 17 + 17 + + + reg_gpio_25_ie + 16 + 16 + + + reg_gpio_24_pd + 5 + 5 + + + reg_gpio_24_pu + 4 + 4 + + + reg_gpio_24_drv + 2 + 3 + + + reg_gpio_24_smt + 1 + 1 + + + reg_gpio_24_ie + 0 + 0 + + + + + GPIO_CFGCTL13 + GPIO_CFGCTL13. + 0x134 + + + reg_gpio_27_pd + 21 + 21 + + + reg_gpio_27_pu + 20 + 20 + + + reg_gpio_27_drv + 18 + 19 + + + reg_gpio_27_smt + 17 + 17 + + + reg_gpio_27_ie + 16 + 16 + + + reg_gpio_26_pd + 5 + 5 + + + reg_gpio_26_pu + 4 + 4 + + + reg_gpio_26_drv + 2 + 3 + + + reg_gpio_26_smt + 1 + 1 + + + reg_gpio_26_ie + 0 + 0 + + + + + GPIO_CFGCTL14 + GPIO_CFGCTL14. + 0x138 + + + reg_gpio_28_pd + 5 + 5 + + + reg_gpio_28_pu + 4 + 4 + + + reg_gpio_28_drv + 2 + 3 + + + reg_gpio_28_smt + 1 + 1 + + + reg_gpio_28_ie + 0 + 0 + + + + + GPIO_CFGCTL30 + GPIO_CFGCTL30. + 0x180 + + + reg_gpio_22_i + 22 + 22 + + + reg_gpio_21_i + 21 + 21 + + + reg_gpio_20_i + 20 + 20 + + + reg_gpio_19_i + 19 + 19 + + + reg_gpio_18_i + 18 + 18 + + + reg_gpio_17_i + 17 + 17 + + + reg_gpio_16_i + 16 + 16 + + + reg_gpio_15_i + 15 + 15 + + + reg_gpio_14_i + 14 + 14 + + + reg_gpio_13_i + 13 + 13 + + + reg_gpio_12_i + 12 + 12 + + + reg_gpio_11_i + 11 + 11 + + + reg_gpio_10_i + 10 + 10 + + + reg_gpio_9_i + 9 + 9 + + + reg_gpio_8_i + 8 + 8 + + + reg_gpio_7_i + 7 + 7 + + + reg_gpio_6_i + 6 + 6 + + + reg_gpio_5_i + 5 + 5 + + + reg_gpio_4_i + 4 + 4 + + + reg_gpio_3_i + 3 + 3 + + + reg_gpio_2_i + 2 + 2 + + + reg_gpio_1_i + 1 + 1 + + + reg_gpio_0_i + 0 + 0 + + + + + GPIO_CFGCTL31 + GPIO_CFGCTL31. + 0x184 + + + + GPIO_CFGCTL32 + GPIO_CFGCTL32. + 0x188 + + + reg_gpio_22_o + 22 + 22 + + + reg_gpio_21_o + 21 + 21 + + + reg_gpio_20_o + 20 + 20 + + + reg_gpio_19_o + 19 + 19 + + + reg_gpio_18_o + 18 + 18 + + + reg_gpio_17_o + 17 + 17 + + + reg_gpio_16_o + 16 + 16 + + + reg_gpio_15_o + 15 + 15 + + + reg_gpio_14_o + 14 + 14 + + + reg_gpio_13_o + 13 + 13 + + + reg_gpio_12_o + 12 + 12 + + + reg_gpio_11_o + 11 + 11 + + + reg_gpio_10_o + 10 + 10 + + + reg_gpio_9_o + 9 + 9 + + + reg_gpio_8_o + 8 + 8 + + + reg_gpio_7_o + 7 + 7 + + + reg_gpio_6_o + 6 + 6 + + + reg_gpio_5_o + 5 + 5 + + + reg_gpio_4_o + 4 + 4 + + + reg_gpio_3_o + 3 + 3 + + + reg_gpio_2_o + 2 + 2 + + + reg_gpio_1_o + 1 + 1 + + + reg_gpio_0_o + 0 + 0 + + + + + GPIO_CFGCTL33 + GPIO_CFGCTL33. + 0x18C + + + + GPIO_CFGCTL34 + GPIO_CFGCTL34. + 0x190 + + + reg_gpio_22_oe + 22 + 22 + + + reg_gpio_21_oe + 21 + 21 + + + reg_gpio_20_oe + 20 + 20 + + + reg_gpio_19_oe + 19 + 19 + + + reg_gpio_18_oe + 18 + 18 + + + reg_gpio_17_oe + 17 + 17 + + + reg_gpio_16_oe + 16 + 16 + + + reg_gpio_15_oe + 15 + 15 + + + reg_gpio_14_oe + 14 + 14 + + + reg_gpio_13_oe + 13 + 13 + + + reg_gpio_12_oe + 12 + 12 + + + reg_gpio_11_oe + 11 + 11 + + + reg_gpio_10_oe + 10 + 10 + + + reg_gpio_9_oe + 9 + 9 + + + reg_gpio_8_oe + 8 + 8 + + + reg_gpio_7_oe + 7 + 7 + + + reg_gpio_6_oe + 6 + 6 + + + reg_gpio_5_oe + 5 + 5 + + + reg_gpio_4_oe + 4 + 4 + + + reg_gpio_3_oe + 3 + 3 + + + reg_gpio_2_oe + 2 + 2 + + + reg_gpio_1_oe + 1 + 1 + + + reg_gpio_0_oe + 0 + 0 + + + + + GPIO_CFGCTL35 + GPIO_CFGCTL35. + 0x194 + + + + GPIO_INT_MASK1 + GPIO_INT_MASK1. + 0x1A0 + + + reg_gpio_int_mask1 + 0 + 31 + + + + + GPIO_INT_STAT1 + GPIO_INT_STAT1. + 0x1A8 + + + gpio_int_stat1 + 0 + 31 + + + + + GPIO_INT_CLR1 + GPIO_INT_CLR1. + 0x1B0 + + + reg_gpio_int_clr1 + 0 + 31 + + + + + GPIO_INT_MODE_SET1 + GPIO_INT_MODE_SET1. + 0x1C0 + + + reg_gpio_int_mode_set1 + 0 + 31 + + + + + GPIO_INT_MODE_SET2 + GPIO_INT_MODE_SET2. + 0x1C4 + + + reg_gpio_int_mode_set2 + 0 + 31 + + + + + GPIO_INT_MODE_SET3 + GPIO_INT_MODE_SET3. + 0x1C8 + + + reg_gpio_int_mode_set3 + 0 + 31 + + + + + led_driver + led_driver. + 0x224 + + + pu_leddrv + 31 + 31 + + + ir_rx_gpio_sel + 8 + 9 + + + leddrv_ibias + 4 + 7 + + + led_din_polarity_sel + 2 + 2 + + + led_din_sel + 1 + 1 + + + led_din_reg + 0 + 0 + + + + + gpdac_ctrl + gpdac_ctrl. + 0x308 + + + gpdac_reserved + 24 + 31 + + + gpdac_test_sel + 9 + 11 + + + gpdac_ref_sel + 8 + 8 + + + gpdac_test_en + 7 + 7 + + + gpdacb_rstn_ana + 1 + 1 + + + gpdaca_rstn_ana + 0 + 0 + + + + + gpdac_actrl + gpdac_actrl. + 0x30C + + + gpdac_a_outmux + 20 + 22 + + + gpdac_a_rng + 18 + 19 + + + gpdac_ioa_en + 1 + 1 + + + gpdac_a_en + 0 + 0 + + + + + gpdac_bctrl + gpdac_bctrl. + 0x310 + + + gpdac_b_outmux + 20 + 22 + + + gpdac_b_rng + 18 + 19 + + + gpdac_iob_en + 1 + 1 + + + gpdac_b_en + 0 + 0 + + + + + gpdac_data + gpdac_data. + 0x314 + + + gpdac_a_data + 16 + 25 + + + gpdac_b_data + 0 + 9 + + + + + tzc_glb_ctrl_0 + tzc_glb_ctrl_0. + 0xF00 + + + tzc_glb_clk_lock + 31 + 31 + + + tzc_glb_mbist_lock + 30 + 30 + + + tzc_glb_dbg_lock + 29 + 29 + + + tzc_glb_bmx_lock + 28 + 28 + + + tzc_glb_l2c_lock + 27 + 27 + + + tzc_glb_sram_lock + 26 + 26 + + + tzc_glb_misc_lock + 25 + 25 + + + tzc_glb_ctrl_ungated_ap_lock + 15 + 15 + + + tzc_glb_ctrl_sys_reset_lock + 14 + 14 + + + tzc_glb_ctrl_cpu_reset_lock + 13 + 13 + + + tzc_glb_ctrl_pwron_rst_lock + 12 + 12 + + + tzc_glb_swrst_s30_lock + 8 + 8 + + + tzc_glb_swrst_s01_lock + 1 + 1 + + + tzc_glb_swrst_s00_lock + 0 + 0 + + + + + tzc_glb_ctrl_1 + tzc_glb_ctrl_1. + 0xF04 + + + tzc_glb_swrst_s1f_lock + 31 + 31 + + + tzc_glb_swrst_s1e_lock + 30 + 30 + + + tzc_glb_swrst_s1d_lock + 29 + 29 + + + tzc_glb_swrst_s1c_lock + 28 + 28 + + + tzc_glb_swrst_s1b_lock + 27 + 27 + + + tzc_glb_swrst_s1a_lock + 26 + 26 + + + tzc_glb_swrst_s19_lock + 25 + 25 + + + tzc_glb_swrst_s18_lock + 24 + 24 + + + tzc_glb_swrst_s17_lock + 23 + 23 + + + tzc_glb_swrst_s16_lock + 22 + 22 + + + tzc_glb_swrst_s15_lock + 21 + 21 + + + tzc_glb_swrst_s14_lock + 20 + 20 + + + tzc_glb_swrst_s13_lock + 19 + 19 + + + tzc_glb_swrst_s12_lock + 18 + 18 + + + tzc_glb_swrst_s11_lock + 17 + 17 + + + tzc_glb_swrst_s10_lock + 16 + 16 + + + tzc_glb_swrst_s2f_lock + 15 + 15 + + + tzc_glb_swrst_s2e_lock + 14 + 14 + + + tzc_glb_swrst_s2d_lock + 13 + 13 + + + tzc_glb_swrst_s2c_lock + 12 + 12 + + + tzc_glb_swrst_s2b_lock + 11 + 11 + + + tzc_glb_swrst_s2a_lock + 10 + 10 + + + tzc_glb_swrst_s29_lock + 9 + 9 + + + tzc_glb_swrst_s28_lock + 8 + 8 + + + tzc_glb_swrst_s27_lock + 7 + 7 + + + tzc_glb_swrst_s26_lock + 6 + 6 + + + tzc_glb_swrst_s25_lock + 5 + 5 + + + tzc_glb_swrst_s24_lock + 4 + 4 + + + tzc_glb_swrst_s23_lock + 3 + 3 + + + tzc_glb_swrst_s22_lock + 2 + 2 + + + tzc_glb_swrst_s21_lock + 1 + 1 + + + tzc_glb_swrst_s20_lock + 0 + 0 + + + + + tzc_glb_ctrl_2 + tzc_glb_ctrl_2. + 0xF08 + + + tzc_glb_gpio_28_lock + 28 + 28 + + + tzc_glb_gpio_27_lock + 27 + 27 + + + tzc_glb_gpio_26_lock + 26 + 26 + + + tzc_glb_gpio_25_lock + 25 + 25 + + + tzc_glb_gpio_24_lock + 24 + 24 + + + tzc_glb_gpio_23_lock + 23 + 23 + + + tzc_glb_gpio_22_lock + 22 + 22 + + + tzc_glb_gpio_21_lock + 21 + 21 + + + tzc_glb_gpio_20_lock + 20 + 20 + + + tzc_glb_gpio_19_lock + 19 + 19 + + + tzc_glb_gpio_18_lock + 18 + 18 + + + tzc_glb_gpio_17_lock + 17 + 17 + + + tzc_glb_gpio_16_lock + 16 + 16 + + + tzc_glb_gpio_15_lock + 15 + 15 + + + tzc_glb_gpio_14_lock + 14 + 14 + + + tzc_glb_gpio_13_lock + 13 + 13 + + + tzc_glb_gpio_12_lock + 12 + 12 + + + tzc_glb_gpio_11_lock + 11 + 11 + + + tzc_glb_gpio_10_lock + 10 + 10 + + + tzc_glb_gpio_9_lock + 9 + 9 + + + tzc_glb_gpio_8_lock + 8 + 8 + + + tzc_glb_gpio_7_lock + 7 + 7 + + + tzc_glb_gpio_6_lock + 6 + 6 + + + tzc_glb_gpio_5_lock + 5 + 5 + + + tzc_glb_gpio_4_lock + 4 + 4 + + + tzc_glb_gpio_3_lock + 3 + 3 + + + tzc_glb_gpio_2_lock + 2 + 2 + + + tzc_glb_gpio_1_lock + 1 + 1 + + + tzc_glb_gpio_0_lock + 0 + 0 + + + + + tzc_glb_ctrl_3 + tzc_glb_ctrl_3. + 0xF0C + + + + + + rf + rf. + 0x40001000 + rf + 32 + read-write + + 0 + 0x1000 + registers + + + + rf_rev + Silicon revision + 0x0 + + + hw_rev + 16 + 23 + + + fw_rev + 8 + 15 + + + rf_id + 0 + 7 + + + + + rf_fsm_ctrl_hw + Digital Control + 0x4 + + + rf_rc_state_value + 28 + 30 + + + rf_fsm_st_int_set + 24 + 24 + + + rf_fsm_st_int_clr + 20 + 20 + + + rf_fsm_st_int + 16 + 16 + + + rf_fsm_st_int_sel + 12 + 14 + + + rf_rc_state_dbg_en + 11 + 11 + + + rf_rc_state_dbg + 8 + 10 + + + rf_fsm_state + 4 + 6 + + + rf_fsm_t2r_cal_mode + 2 + 3 + + + rf_fsm_ctrl_en + 1 + 1 + + + + + rf_fsm_ctrl_sw + rfsm status reg + 0x8 + + + lo_unlocked + 20 + 20 + + + inc_cal_timeout + 16 + 16 + + + full_cal_en + 12 + 12 + + + rf_fsm_sw_st_vld + 8 + 8 + + + rf_fsm_sw_st + 0 + 4 + + + + + rfctrl_hw_en + Control logic switch + 0xC + + + adda_ctrl_hw + 12 + 12 + + + rbb_pkdet_out_rstn_ctrl_hw + 11 + 11 + + + rbb_pkdet_en_ctrl_hw + 10 + 10 + + + sdm_ctrl_hw + 9 + 9 + + + inc_fcal_ctrl_en_hw + 8 + 8 + + + inc_acal_ctrl_en_hw + 7 + 7 + + + lo_ctrl_hw + 6 + 6 + + + trxcal_ctrl_hw + 5 + 5 + + + rbb_bw_ctrl_hw + 4 + 4 + + + lna_ctrl_hw + 3 + 3 + + + tx_gain_ctrl_hw + 2 + 2 + + + rx_gain_ctrl_hw + 1 + 1 + + + pu_ctrl_hw + 0 + 0 + + + + + temp_comp + temp_comp. + 0x10 + + + temp_comp_en + 16 + 16 + + + const_fcal + 8 + 15 + + + const_acal + 0 + 7 + + + + + rfcal_status + rfcal_status. + 0x14 + + + dpd_status + 30 + 31 + + + tenscal_status + 28 + 29 + + + pwdet_cal_status + 26 + 27 + + + riqcal_status_resv + 24 + 25 + + + tiqcal_status_resv + 22 + 23 + + + lo_leakcal_status + 20 + 21 + + + rccal_status + 18 + 19 + + + tos_status + 16 + 17 + + + ros_status + 14 + 15 + + + clkpll_cal_status + 12 + 13 + + + inc_acal_status + 10 + 11 + + + inc_fcal_status + 8 + 9 + + + acal_status + 6 + 7 + + + fcal_status + 4 + 5 + + + adc_oscal_status + 2 + 3 + + + rcal_status + 0 + 1 + + + + + rfcal_status2 + rfcal_status2. + 0x18 + + + dl_rfcal_table_status + 0 + 1 + + + + + rfcal_ctrlen + Calibration mode register + 0x1C + + + dpd_en + 17 + 17 + + + tsencal_en + 16 + 16 + + + pwdet_cal_en + 15 + 15 + + + riqcal_en + 14 + 14 + + + tiqcal_en + 13 + 13 + + + lo_leakcal_en + 12 + 12 + + + rccal_en + 11 + 11 + + + toscal_en + 10 + 10 + + + roscal_en + 9 + 9 + + + clkpll_cal_en + 8 + 8 + + + roscal_inc_en + 7 + 7 + + + acal_inc_en + 6 + 6 + + + fcal_inc_en + 5 + 5 + + + acal_en + 4 + 4 + + + fcal_en + 3 + 3 + + + dl_rfcal_table_en + 2 + 2 + + + adc_oscal_en + 1 + 1 + + + rcal_en_resv + 0 + 0 + + + + + rfcal_stateen + rf calibration state enabl in full cal list + 0x20 + + + rfcal_level + 30 + 31 + + + dpd_sten + 16 + 16 + + + tsencal_sten + 15 + 15 + + + pwdet_cal_sten + 14 + 14 + + + riqcal_sten + 13 + 13 + + + tiqcal_sten + 12 + 12 + + + lo_leakcal_sten + 11 + 11 + + + rccal_sten + 10 + 10 + + + toscal_sten_resv + 9 + 9 + + + roscal_sten + 8 + 8 + + + clkpll_cal_sten + 7 + 7 + + + inc_acal_sten + 6 + 6 + + + inc_fcal_sten + 5 + 5 + + + acal_sten + 4 + 4 + + + fcal_sten + 3 + 3 + + + dl_rfcal_table_sten + 2 + 2 + + + adc_oscal_sten + 1 + 1 + + + rcal_sten_resv + 0 + 0 + + + + + saradc_resv + SARADC Control Registers + 0x24 + + + + rf_base_ctrl1 + ZRF Control register 0 + 0x28 + + + mbg_trim + 27 + 28 + + + pud_pa_dly + 14 + 15 + + + pud_iref_dly + 12 + 13 + + + pud_vco_dly + 10 + 11 + + + ppu_lead + 8 + 9 + + + lo_sdm_rst_dly + 2 + 3 + + + aupll_sdm_rst_dly + 0 + 1 + + + + + rf_base_ctrl2 + ZRF Control register 0 + 0x2C + + + + pucr1 + pucr1. + 0x30 + + + pu_tosdac + 31 + 31 + + + pu_pwrmx + 30 + 30 + + + pu_rosdac + 29 + 29 + + + pu_pkdet + 28 + 28 + + + trsw_en + 26 + 26 + + + pu_txbuf + 25 + 25 + + + pu_rxbuf + 24 + 24 + + + pu_osmx + 23 + 23 + + + pu_pfd + 22 + 22 + + + pu_fbdv + 21 + 21 + + + pu_vco + 20 + 20 + + + pu_dac + 19 + 19 + + + pu_tbb + 18 + 18 + + + pu_tmx + 17 + 17 + + + pu_pa + 16 + 16 + + + pu_op_atest + 15 + 15 + + + pu_adc + 14 + 14 + + + adc_clk_en + 13 + 13 + + + pu_adda_ldo + 12 + 12 + + + pu_rbb + 11 + 11 + + + pu_rmx + 10 + 10 + + + pu_rmxgm + 9 + 9 + + + pu_lna + 8 + 8 + + + pu_sfreg + 0 + 0 + + + + + pucr1_hw + read only from hardware logic + 0x34 + + + pu_tosdac_hw + 31 + 31 + + + pu_rosdac_hw + 29 + 29 + + + pu_pkdet_hw + 28 + 28 + + + trsw_en_hw + 26 + 26 + + + pu_txbuf_hw + 25 + 25 + + + pu_rxbuf_hw + 24 + 24 + + + pu_osmx_hw + 23 + 23 + + + pu_pfd_hw + 22 + 22 + + + pu_fbdv_hw + 21 + 21 + + + pu_vco_hw + 20 + 20 + + + pu_dac_hw + 19 + 19 + + + pu_tbb_hw + 18 + 18 + + + pu_tmx_hw + 17 + 17 + + + pu_pa_hw + 16 + 16 + + + pu_adc_hw + 14 + 14 + + + adc_clk_en_hw + 13 + 13 + + + pu_adda_ldo_hw + 12 + 12 + + + pu_rbb_hw + 11 + 11 + + + pu_rmx_hw + 10 + 10 + + + pu_rmxgm_hw + 9 + 9 + + + pu_lna_hw + 8 + 8 + + + pu_sfreg_hw + 0 + 0 + + + + + pucr2 + pucr2. + 0x38 + + + + pucr2_hw + pucr2_hw. + 0x3C + + + + ppu_ctrl_hw + ppu_ctrl_hw. + 0x40 + + + ppu_txbuf_hw + 25 + 25 + + + ppu_rxbuf_hw + 24 + 24 + + + ppu_osmx_hw + 23 + 23 + + + ppu_pfd_hw + 22 + 22 + + + ppu_fbdv_hw + 21 + 21 + + + ppu_vco_hw + 20 + 20 + + + ppu_rbb_hw + 11 + 11 + + + ppu_rmxgm_hw + 9 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+ + ten_clkpll + 8 + 8 + + + dc_tp_clkpll_en + 4 + 4 + + + dc_tp_en + 3 + 3 + + + tmux + 0 + 2 + + + + + ten_dig + digital test register + 0x54 + + + rf_dtest_en + 23 + 23 + + + dtest_pull_down + 9 + 9 + + + dten_lo_fref + 8 + 8 + + + dten_lo_fsdm + 6 + 6 + + + dten_clkpll_fin + 5 + 5 + + + dten_clkpll_fref + 4 + 4 + + + dten_clkpll_fsdm + 3 + 3 + + + dten_clkpll_clk32m + 2 + 2 + + + dten_clkpll_clk96m + 1 + 1 + + + dten_clkpll_postdiv_clk + 0 + 0 + + + + + ten_ac + ac test register + 0x58 + + + atest_in_en_i + 23 + 23 + + + atest_in_en_q + 22 + 22 + + + atest_out_en_i + 21 + 21 + + + atest_out_en_q + 20 + 20 + + + atest_gain_r5 + 16 + 18 + + + atest_gain_r6 + 14 + 15 + + + atest_gain_r7 + 12 + 13 + + + atest_gain_r8 + 10 + 11 + + + atest_gain_r9 + 8 + 9 + + + atest_in_en + 6 + 6 + + + atest_in_trx_sw + 5 + 5 + + + atest_dac_en + 4 + 4 + + + atest_op_cc + 0 + 3 + + + + + pmip_mv2aon + pmip_mv2aon. + 0x5C + + + + cip + RX normal bias mode registers + 0x60 + + + vg13_sel + 2 + 3 + + + vg11_sel + 0 + 1 + + + + + pa1 + pa1. + 0x64 + + + pa_att_gc + 28 + 31 + + + pa_pwrmx_bm + 24 + 26 + + + pa_pwrmx_dac_pn_switch + 22 + 22 + + + pa_pwrmx_osdac + 18 + 21 + + + pa_lz_bias_en + 17 + 17 + + + pa_ib_fix + 16 + 16 + + + pa_half_on + 15 + 15 + + + pa_vbcas + 12 + 14 + + + pa_vbcore + 8 + 11 + + + pa_iet + 4 + 7 + + + pa_etb_en + 3 + 3 + + + pa_iaq + 0 + 2 + + + + + pa2 + RX normal bias mode registers + 0x68 + + + pa_ib_fix_hw + 17 + 17 + + + pa_half_on_hw + 16 + 16 + + + pa_vbcas_hw + 12 + 14 + + + pa_vbcore_hw + 8 + 11 + + + pa_iet_hw + 4 + 7 + + + pa_etb_en_hw + 3 + 3 + + + + + tmx + tmx. + 0x6C + + + tx_tsense_en + 16 + 16 + + + tmx_bm_cas_bulk + 12 + 14 + + + tmx_bm_cas + 8 + 10 + + + tmx_bm_sw + 4 + 6 + + + tmx_cs + 0 + 2 + + + + + tbb + tbb. + 0x70 + + + tbb_tosdac_i + 24 + 29 + + + tbb_tosdac_q + 16 + 21 + + + tbb_atest_out_en + 15 + 15 + + + tbb_iq_bias_short + 14 + 14 + + + tbb_cflt + 12 + 13 + + + tbb_vcm + 8 + 9 + + + tbb_bm_cg + 4 + 5 + + + tbb_bm_sf + 0 + 1 + + + + + lna + lna. + 0x74 + + + lna_lg_gsel + 24 + 26 + + + lna_cap_lg + 20 + 21 + + + lna_rfb_match + 16 + 18 + + + lna_load_csw_hw + 12 + 15 + + + lna_load_csw + 8 + 11 + + + lna_bm_hw + 4 + 7 + + + lna_bm + 0 + 3 + + + + + rmxgm + rmxgm. + 0x78 + + + rmxgm_10m_mode_en + 8 + 8 + + + rmxgm_bm + 4 + 6 + + + rmx_bm + 0 + 2 + + + + + rbb1 + rbb1. + 0x7C + + + rosdac_range + 31 + 31 + + + rosdac_i_hw + 24 + 29 + + + rosdac_q_hw + 16 + 21 + + + rosdac_i + 8 + 13 + + + rosdac_q + 0 + 5 + + + + + rbb2 + rbb2. + 0x80 + + + rbb_cap1_fc_i + 24 + 29 + + + rbb_cap1_fc_q + 16 + 21 + + + rbb_cap2_fc_i + 8 + 13 + + + rbb_cap2_fc_q + 0 + 5 + + + + + rbb3 + rbb3. + 0x84 + + + pwr_det_en + 31 + 31 + + + rxiqcal_en + 28 + 28 + + + rbb_bw + 24 + 25 + + + rbb_tia_iqbias_short + 21 + 21 + + + rbb_bq_iqbias_short + 20 + 20 + + + rbb_vcm + 16 + 17 + + + rbb_bm_op + 12 + 14 + + + rbb_deq + 8 + 9 + + + rbb_bt_fif_tune + 5 + 6 + + + rbb_bt_mode + 4 + 4 + + + rbb_bt_mode_hw + 0 + 0 + + + + + rbb4 + rbb4. + 0x88 + + + pkdet_out_latch + 24 + 24 + + + pkdet_out_raw + 20 + 20 + + + rbb_pkdet_en_hw + 16 + 16 + + + rbb_pkdet_out_rstn_hw + 12 + 12 + + + rbb_pkdet_en + 8 + 8 + + + rbb_pkdet_out_rstn + 4 + 4 + + + rbb_pkdet_vth + 0 + 3 + + + + + adda1 + adda1. + 0x8C + + + adda_ldo_dvdd_sel_hw + 24 + 26 + + + adda_ldo_dvdd_sel + 20 + 22 + + + adda_ldo_byps + 16 + 16 + + + dac_clk_sync_inv + 13 + 13 + + + dac_rccalsel + 12 + 12 + + + dac_clk_sel + 8 + 9 + + + dac_bias_sel + 4 + 5 + + + dac_dvdd_sel + 0 + 1 + + + + + adda2 + adda2. + 0x90 + + + adc_clk_div_sel + 28 + 28 + + + adc_clk_inv + 24 + 24 + + + adc_clk_sync_inv + 20 + 20 + + + adc_gt_rm + 16 + 16 + + + adc_sar_ascal_en + 12 + 12 + + + adc_dvdd_sel + 8 + 9 + + + adc_dly_ctl + 4 + 5 + + + adc_vref_sel + 0 + 1 + + + + + vco1 + vco1. + 0xA0 + + + lo_vco_idac_cw_hw + 24 + 28 + + + lo_vco_idac_cw + 16 + 20 + + + lo_vco_freq_cw_hw + 8 + 15 + + + lo_vco_freq_cw + 0 + 7 + + + + + vco2 + vco2. + 0xA4 + + + acal_inc_en_hw + 16 + 16 + + + acal_vco_ud + 12 + 12 + + + acal_vref_cw + 8 + 10 + + + lo_vco_short_idac_filter + 6 + 6 + + + lo_vco_short_vbias_filter + 5 + 5 + + + lo_vco_idac_boot + 4 + 4 + + + lo_vco_vbias_cw + 0 + 1 + + + + + vco3 + vco3. + 0xA8 + + + fcal_cnt_op + 16 + 31 + + + fcal_div + 0 + 15 + + + + + vco4 + vco4. + 0xAC + + + fcal_inc_vctrl_ud + 24 + 25 + + + fcal_cnt_rdy + 20 + 20 + + + fcal_inc_large_range + 16 + 16 + + + fcal_inc_en_hw + 8 + 8 + + + fcal_cnt_start + 4 + 4 + + + + + pfdcp + pfdcp. + 0xB0 + + + lo_pfd_rst_csd_hw + 29 + 29 + + + lo_pfd_rst_csd + 28 + 28 + + + lo_pfd_rvdd_boost + 24 + 24 + + + lo_cp_hiz + 20 + 20 + + + lo_cp_opamp_en + 16 + 16 + + + lo_cp_ota_en + 12 + 12 + + + lo_cp_startup_en + 8 + 8 + + + lo_cp_sel_hw + 4 + 4 + + + lo_cp_sel + 0 + 0 + + + + + lo + lo. + 0xB4 + + + lo_slipped_up + 24 + 24 + + + lo_slipped_dn + 20 + 20 + + + lo_lf_r4_short + 18 + 18 + + + lo_lf_r4 + 16 + 17 + + + lo_lf_cz + 14 + 15 + + + lo_lf_rz + 12 + 13 + + + lo_lf_cz_hw + 8 + 9 + + + lo_lf_r4_hw + 4 + 5 + + + lo_lf_rz_hw + 0 + 1 + + + + + fbdv + fbdv. + 0xB8 + + + lo_fbdv_rst_hw + 20 + 20 + + + lo_fbdv_rst + 16 + 16 + + + lo_fbdv_sel_fb_clk + 12 + 13 + + + lo_fbdv_sel_sample_clk + 8 + 9 + + + lo_fbdv_halfstep_en + 4 + 4 + + + lo_fbdv_halfstep_en_hw + 0 + 0 + + + + + lodist + lodist. + 0xBC + + + lo_lodist_rxbuf_stre + 28 + 28 + + + lo_lodist_txbuf_stre + 24 + 24 + + + lo_osmx_cap + 20 + 23 + + + lo_osmx_capbank_bias + 16 + 17 + + + lo_osmx_vbuf_stre + 12 + 12 + + + lo_osmx_fix_cap + 8 + 8 + + + lo_osmx_en_xgm + 4 + 4 + + + lo_osmx_xgm_boost + 0 + 0 + + + + + sdm1 + sdm1. + 0xC0 + + + lo_sdm_flag + 20 + 20 + + + lo_sdm_rstb_hw + 17 + 17 + + + lo_sdm_rstb + 16 + 16 + + + lo_sdm_bypass + 12 + 12 + + + lo_sdm_dither_sel + 8 + 9 + + + lo_sdm_bypass_hw + 4 + 4 + + + lo_sdm_dither_sel_hw + 0 + 1 + + + + + sdm2 + sdm2. + 0xC4 + + + lo_sdmin + 0 + 29 + + + + + sdm3 + sdm3. + 0xC8 + + + lo_sdmin_hw + 0 + 29 + + + + + rf_resv_reg_0 + rf_resv_reg_0. + 0xEC + + + rf_reserved0 + 0 + 31 + + + + + rf_resv_reg_1 + rf_resv_reg_1. + 0xF0 + + + rf_reserved1 + 0 + 31 + + + + + rf_resv_reg_2 + rf_resv_reg_2. + 0xF4 + + + rf_reserved2 + 0 + 31 + + + + + rrf_gain_index1 + rrf_gain_index1. + 0xF8 + + + gain_ctrl5_gc_lna + 27 + 29 + + + gain_ctrl5_gc_rmxgm + 25 + 26 + + + gain_ctrl4_gc_lna + 22 + 24 + + + gain_ctrl4_gc_rmxgm + 20 + 21 + + + gain_ctrl3_gc_lna + 17 + 19 + + + gain_ctrl3_gc_rmxgm + 15 + 16 + + + gain_ctrl2_gc_lna + 12 + 14 + + + gain_ctrl2_gc_rmxgm + 10 + 11 + + + gain_ctrl1_gc_lna + 7 + 9 + + + gain_ctrl1_gc_rmxgm + 5 + 6 + + + gain_ctrl0_gc_lna + 2 + 4 + + + gain_ctrl0_gc_rmxgm + 0 + 1 + + + + + rrf_gain_index2 + rrf_gain_index2. + 0xFC + + + gain_ctrl6_gc_lna + 12 + 14 + + + gain_ctrl6_gc_rmxgm + 10 + 11 + + + gain_ctrl7_gc_lna + 7 + 9 + + + gain_ctrl7_gc_rmxgm + 5 + 6 + + + gain_ctrl8_gc_lna + 2 + 4 + + + gain_ctrl8_gc_rmxgm + 0 + 1 + + + + + lna_ctrl_hw_mux + lna_ctrl_hw_mux. + 0x100 + + + lna_load_csw_lg + 12 + 15 + + + lna_load_csw_hg + 8 + 11 + + + lna_bm_lg + 4 + 7 + + + lna_bm_hg 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gain_ctrl2_gc_tbb_boost + 14 + 15 + + + gain_ctrl2_dac_bias_sel + 12 + 13 + + + gain_ctrl2_gc_tmx + 8 + 10 + + + gain_ctrl2_gc_tbb + 0 + 4 + + + + + tbb_gain_index3 + tbb_gain_index3. + 0x120 + + + gain_ctrl5_gc_tbb_boost + 30 + 31 + + + gain_ctrl5_dac_bias_sel + 28 + 29 + + + gain_ctrl5_gc_tmx + 24 + 26 + + + gain_ctrl5_gc_tbb + 16 + 20 + + + gain_ctrl4_gc_tbb_boost + 14 + 15 + + + gain_ctrl4_dac_bias_sel + 12 + 13 + + + gain_ctrl4_gc_tmx + 8 + 10 + + + gain_ctrl4_gc_tbb + 0 + 4 + + + + + tbb_gain_index4 + tbb_gain_index4. + 0x124 + + + gain_ctrl7_gc_tbb_boost + 30 + 31 + + + gain_ctrl7_dac_bias_sel + 28 + 29 + + + gain_ctrl7_gc_tmx + 24 + 26 + + + gain_ctrl7_gc_tbb + 16 + 20 + + + gain_ctrl6_gc_tbb_boost + 14 + 15 + + + gain_ctrl6_dac_bias_sel + 12 + 13 + + + gain_ctrl6_gc_tmx + 8 + 10 + + + gain_ctrl6_gc_tbb + 0 + 4 + + + + + pa_reg_ctrl_hw1 + pa_reg_ctrl_hw1. + 0x128 + + + pa_vbcas_11n + 20 + 22 + + + pa_vbcore_11n + 16 + 19 + + + pa_iet_11n + 12 + 15 + + + + + pa_reg_ctrl_hw2 + pa_reg_ctrl_hw2. + 0x12C + + + pa_vbcas_11b + 20 + 22 + + + pa_vbcore_11b + 16 + 19 + + + pa_iet_11b + 12 + 15 + + + pa_vbcas_11g + 8 + 10 + + + pa_vbcore_11g + 4 + 7 + + + pa_iet_11g + 0 + 3 + + + + + pa_reg_wifi_ctrl_hw + pa_reg_wifi_ctrl_hw. + 0x130 + + + pa_ib_fix_wifi + 16 + 16 + + + pa_etb_en_wifi + 8 + 8 + + + pa_half_on_wifi + 0 + 0 + + + + + adda_reg_ctrl_hw + adda_reg_ctrl_hw. + 0x134 + + + adda_ldo_dvdd_sel_tx + 4 + 6 + + + adda_ldo_dvdd_sel_rx + 0 + 2 + + + + + lo_reg_ctrl_hw1 + lo_reg_ctrl_hw1. + 0x138 + + + lo_lf_r4_tx + 24 + 25 + + + lo_lf_r4_rx + 20 + 21 + + + lo_lf_rz_tx + 16 + 17 + + + lo_lf_rz_rx + 12 + 13 + + + lo_lf_cz_tx + 8 + 9 + + + lo_lf_cz_rx + 4 + 5 + + + lo_cp_sel_tx + 3 + 3 + + + lo_cp_sel_rx + 2 + 2 + + + lo_fbdv_halfstep_en_tx + 1 + 1 + + + lo_fbdv_halfstep_en_rx + 0 + 0 + + + + + lo_cal_ctrl_hw1 + lo_cal_ctrl_hw1. + 0x13C + + + lo_vco_freq_cw_2408 + 24 + 31 + + + lo_vco_idac_cw_2408 + 16 + 20 + + + lo_vco_freq_cw_2404 + 8 + 15 + + + lo_vco_idac_cw_2404 + 0 + 4 + + + + + lo_cal_ctrl_hw2 + lo_cal_ctrl_hw2. + 0x140 + + + lo_vco_freq_cw_2416 + 24 + 31 + + + lo_vco_idac_cw_2416 + 16 + 20 + + + lo_vco_freq_cw_2412 + 8 + 15 + + + lo_vco_idac_cw_2412 + 0 + 4 + + + + + lo_cal_ctrl_hw3 + lo_cal_ctrl_hw3. + 0x144 + + + lo_vco_freq_cw_2424 + 24 + 31 + + + lo_vco_idac_cw_2424 + 16 + 20 + + + lo_vco_freq_cw_2420 + 8 + 15 + + + lo_vco_idac_cw_2420 + 0 + 4 + + + + + lo_cal_ctrl_hw4 + lo_cal_ctrl_hw4. + 0x148 + + + lo_vco_freq_cw_2432 + 24 + 31 + + + lo_vco_idac_cw_2432 + 16 + 20 + + + lo_vco_freq_cw_2428 + 8 + 15 + + + lo_vco_idac_cw_2428 + 0 + 4 + + + + + lo_cal_ctrl_hw5 + lo_cal_ctrl_hw5. + 0x14C + + + lo_vco_freq_cw_2440 + 24 + 31 + + + lo_vco_idac_cw_2440 + 16 + 20 + + + lo_vco_freq_cw_2436 + 8 + 15 + + + lo_vco_idac_cw_2436 + 0 + 4 + + + + + lo_cal_ctrl_hw6 + lo_cal_ctrl_hw6. + 0x150 + + + lo_vco_freq_cw_2448 + 24 + 31 + + + lo_vco_idac_cw_2448 + 16 + 20 + + + lo_vco_freq_cw_2444 + 8 + 15 + + + lo_vco_idac_cw_2444 + 0 + 4 + + + + + lo_cal_ctrl_hw7 + lo_cal_ctrl_hw7. + 0x154 + + + lo_vco_freq_cw_2456 + 24 + 31 + + + lo_vco_idac_cw_2456 + 16 + 20 + + + lo_vco_freq_cw_2452 + 8 + 15 + + + lo_vco_idac_cw_2452 + 0 + 4 + + + + + lo_cal_ctrl_hw8 + lo_cal_ctrl_hw8. + 0x158 + + + lo_vco_freq_cw_2464 + 24 + 31 + + + lo_vco_idac_cw_2464 + 16 + 20 + + + lo_vco_freq_cw_2460 + 8 + 15 + + + lo_vco_idac_cw_2460 + 0 + 4 + + + + + lo_cal_ctrl_hw9 + lo_cal_ctrl_hw9. + 0x15C + + + lo_vco_freq_cw_2472 + 24 + 31 + + + lo_vco_idac_cw_2472 + 16 + 20 + + + lo_vco_freq_cw_2468 + 8 + 15 + + + lo_vco_idac_cw_2468 + 0 + 4 + + + + + lo_cal_ctrl_hw10 + lo_cal_ctrl_hw10. + 0x160 + + + lo_vco_freq_cw_2480 + 24 + 31 + + + lo_vco_idac_cw_2480 + 16 + 20 + + + lo_vco_freq_cw_2476 + 8 + 15 + + + lo_vco_idac_cw_2476 + 0 + 4 + + + + + lo_cal_ctrl_hw11 + lo_cal_ctrl_hw11. + 0x164 + + + lo_vco_freq_cw_2484 + 8 + 15 + + + lo_vco_idac_cw_2484 + 0 + 4 + + + + + rosdac_ctrl_hw1 + rosdac_ctrl_hw1. + 0x168 + + + rosdac_q_gc1 + 24 + 29 + + + rosdac_i_gc1 + 16 + 21 + + + rosdac_q_gc0 + 8 + 13 + + + rosdac_i_gc0 + 0 + 5 + + + + + rosdac_ctrl_hw2 + rosdac_ctrl_hw2. + 0x16C + + + rosdac_q_gc3 + 24 + 29 + + + rosdac_i_gc3 + 16 + 21 + + + rosdac_q_gc2 + 8 + 13 + + + rosdac_i_gc2 + 0 + 5 + + + + + rxiq_ctrl_hw1 + rxiq_ctrl_hw1. + 0x170 + + + rx_iq_gain_comp_gc0 + 16 + 26 + + + rx_iq_phase_comp_gc0 + 0 + 9 + + + + + rxiq_ctrl_hw2 + rxiq_ctrl_hw2. + 0x174 + + + rx_iq_gain_comp_gc1 + 16 + 26 + + + rx_iq_phase_comp_gc1 + 0 + 9 + + + + + rxiq_ctrl_hw3 + rxiq_ctrl_hw3. + 0x178 + + + rx_iq_gain_comp_gc2 + 16 + 26 + + + rx_iq_phase_comp_gc2 + 0 + 9 + + + + + rxiq_ctrl_hw4 + rxiq_ctrl_hw4. + 0x17C + + + rx_iq_gain_comp_gc3 + 16 + 26 + + + rx_iq_phase_comp_gc3 + 0 + 9 + + + + + tosdac_ctrl_hw1 + tosdac_ctrl_hw1. + 0x180 + + + tbb_tosdac_q_gc1 + 24 + 29 + + + tbb_tosdac_i_gc1 + 16 + 21 + + + tbb_tosdac_q_gc0 + 8 + 13 + + + tbb_tosdac_i_gc0 + 0 + 5 + + + + + tosdac_ctrl_hw2 + tosdac_ctrl_hw2. + 0x184 + + + tbb_tosdac_q_gc3 + 24 + 29 + + + tbb_tosdac_i_gc3 + 16 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16 + 26 + + + tx_iq_phase_comp_gc4 + 0 + 9 + + + + + tx_iq_gain_hw5 + tx_iq_gain_hw5. + 0x1A4 + + + tx_iq_gain_comp_gc5 + 16 + 26 + + + tx_iq_phase_comp_gc5 + 0 + 9 + + + + + tx_iq_gain_hw6 + tx_iq_gain_hw6. + 0x1A8 + + + tx_iq_gain_comp_gc6 + 16 + 26 + + + tx_iq_phase_comp_gc6 + 0 + 9 + + + + + tx_iq_gain_hw7 + tx_iq_gain_hw7. + 0x1AC + + + tx_iq_gain_comp_gc7 + 16 + 26 + + + tx_iq_phase_comp_gc7 + 0 + 9 + + + + + lo_sdm_ctrl_hw1 + lo_sdm_ctrl_hw1. + 0x1B0 + + + lo_sdm_dither_sel_wlan_2484 + 26 + 27 + + + lo_sdm_dither_sel_wlan_2472 + 24 + 25 + + + lo_sdm_dither_sel_wlan_2467 + 22 + 23 + + + lo_sdm_dither_sel_wlan_2462 + 20 + 21 + + + lo_sdm_dither_sel_wlan_2457 + 18 + 19 + + + lo_sdm_dither_sel_wlan_2452 + 16 + 17 + + + lo_sdm_dither_sel_wlan_2447 + 14 + 15 + + + lo_sdm_dither_sel_wlan_2442 + 12 + 13 + + + lo_sdm_dither_sel_wlan_2437 + 10 + 11 + + + lo_sdm_dither_sel_wlan_2432 + 8 + 9 + + + lo_sdm_dither_sel_wlan_2427 + 6 + 7 + + + lo_sdm_dither_sel_wlan_2422 + 4 + 5 + + + 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lo_sdm_ctrl_hw5. + 0x1C0 + + + lo_sdm_bypass_mode + 12 + 17 + + + lo_center_freq_mhz + 0 + 11 + + + + + lo_sdm_ctrl_hw6 + lo_sdm_ctrl_hw6. + 0x1C4 + + + lo_sdmin_center + 0 + 28 + + + + + lo_sdm_ctrl_hw7 + lo_sdm_ctrl_hw7. + 0x1C8 + + + lo_sdmin_1m + 0 + 19 + + + + + lo_sdm_ctrl_hw8 + lo_sdm_ctrl_hw8. + 0x1CC + + + lo_sdmin_if + 0 + 19 + + + + + rbb_bw_ctrl_hw + rbb_bw_ctrl_hw. + 0x1D0 + + + rbb_bt_mode_ble + 0 + 0 + + + + + singen_ctrl0 + singen_ctrl0. + 0x20C + + + singen_en + 31 + 31 + + + singen_clkdiv_n + 29 + 30 + + + singen_unsign_en + 28 + 28 + + + singen_inc_step0 + 16 + 25 + + + singen_inc_step1 + 0 + 9 + + + + + singen_ctrl1 + singen_ctrl1. + 0x210 + + + singen_mode_i + 28 + 31 + + + singen_clkdiv_i + 16 + 25 + + + singen_mode_q + 12 + 15 + + + singen_clkdiv_q + 0 + 9 + + + + + singen_ctrl2 + singen_ctrl2. + 0x214 + + + singen_start_addr0_i + 22 + 31 + + + singen_start_addr1_i + 12 + 21 + + + singen_gain_i + 0 + 10 + + + + + singen_ctrl3 + singen_ctrl3. + 0x218 + + + singen_start_addr0_q + 22 + 31 + + + singen_start_addr1_q + 12 + 21 + + + singen_gain_q + 0 + 10 + + + + + singen_ctrl4 + singen_ctrl4. + 0x21C + + + singen_fix_en_i + 28 + 28 + + + singen_fix_i + 16 + 27 + + + singen_fix_en_q + 12 + 12 + + + singen_fix_q + 0 + 11 + + + + + rfif_dfe_ctrl0 + rfif_dfe_ctrl0. + 0x220 + + + test_sel + 28 + 31 + + + bbmode_4s_en + 27 + 27 + + + bbmode_4s + 26 + 26 + + + wifimode_4s_en + 25 + 25 + + + wifimode_4s + 23 + 24 + + + rf_ch_ind_ble_4s_en + 22 + 22 + + + rf_ch_ind_ble_4s + 15 + 21 + + + pad_dac_clkout_inv_en + 14 + 14 + + + pad_adc_clkout_inv_en + 13 + 13 + + + tx_test_sel + 11 + 12 + + + rx_test_sel + 9 + 10 + + + tx_dfe_en_4s_en + 8 + 8 + + + tx_dfe_en_4s + 7 + 7 + + + rx_dfe_en_4s_en + 6 + 6 + + + rx_dfe_en_4s + 5 + 5 + + + rfckg_dac_afifo_inv + 4 + 4 + + + rfckg_adc_clkout_sel + 3 + 3 + + + rfckg_adc_afifo_inv + 2 + 2 + + + rfckg_txclk_4s_on + 1 + 1 + + + rfckg_rxclk_4s_on + 0 + 0 + + + + + rfif_test_read + rfif_test_read. + 0x224 + + + test_read + 0 + 31 + + + + + rfif_dig_ctrl + rfif_dig_ctrl. + 0x228 + + + rfif_ppud_manaual_en + 30 + 30 + + + rfif_ppud_cnt1 + 25 + 29 + + + rfif_ppud_cnt2 + 16 + 24 + + + rfif_int_lo_unlocked_mask + 3 + 3 + + + rfckg_rxclk_div2_mode + 2 + 2 + + + test_gc_from_pad_en + 1 + 1 + + + test_from_pad_en + 0 + 0 + + + + + rf_data_temp_0 + rf_data_temp_0. + 0x22C + + + rf_data_temp_0 + 0 + 31 + + + + + rf_data_temp_1 + rf_data_temp_1. + 0x230 + + + rf_data_temp_1 + 0 + 31 + + + + + rf_data_temp_2 + rf_data_temp_2. + 0x234 + + + rf_data_temp_2 + 0 + 31 + + + + + rf_data_temp_3 + rf_data_temp_3. + 0x238 + + + rf_data_temp_3 + 0 + 31 + + + + + rf_sram_ctrl0 + rf_sram_ctrl0. + 0x23C + + + rf_sram_ext_clr + 19 + 19 + + + rf_sram_swap + 18 + 18 + + + rf_sram_link_mode + 16 + 17 + + + rf_sram_link_dly + 0 + 15 + + + + + rf_sram_ctrl1 + rf_sram_ctrl1. + 0x240 + + + rf_sram_adc_done_cnt + 16 + 31 + + + rf_sram_adc_sts_clr + 3 + 3 + + + rf_sram_adc_loop_en + 2 + 2 + + + rf_sram_adc_en + 1 + 1 + + + rf_sram_adc_done + 0 + 0 + + + + + rf_sram_ctrl2 + rf_sram_ctrl2. + 0x244 + + + rf_sram_adc_addr_start + 16 + 31 + + + rf_sram_adc_addr_end + 0 + 15 + + + + + rf_sram_ctrl3 + rf_sram_ctrl3. + 0x248 + + + rf_sram_adc_sts + 0 + 31 + + + + + rf_sram_ctrl4 + rf_sram_ctrl4. + 0x24C + + + rf_sram_dac_done_cnt + 16 + 31 + + + rf_sram_dac_sts_clr + 3 + 3 + + + rf_sram_dac_loop_en + 2 + 2 + + + rf_sram_dac_en + 1 + 1 + + + rf_sram_dac_done + 0 + 0 + + + + + rf_sram_ctrl5 + rf_sram_ctrl5. + 0x250 + + + rf_sram_dac_addr_start + 16 + 31 + + + rf_sram_dac_addr_end + 0 + 15 + + + + + rf_sram_ctrl6 + rf_sram_ctrl6. + 0x254 + + + rf_sram_dac_sts + 0 + 31 + + + + + rf_ical_ctrl0 + rf_ical_ctrl0. + 0x258 + + + rf_ical_f_ud_inv_en + 31 + 31 + + + rf_ical_a_ud_inv_en + 30 + 30 + + + rf_ical_f_cnt_n + 20 + 29 + + + rf_ical_a_cnt_n + 10 + 19 + + + rf_ical_r_cnt_n + 0 + 9 + + + + + rf_ical_ctrl1 + rf_ical_ctrl1. + 0x25C + + + rf_ical_r_os_i + 20 + 29 + + + rf_ical_r_os_q + 10 + 19 + + + rf_ical_r_avg_n + 0 + 4 + + + + + rf_ical_ctrl2 + rf_ical_ctrl2. + 0x260 + + + rf_ical_period_n + 0 + 15 + + + + + rf_fsm_ctrl0 + rf_fsm_ctrl0. + 0x264 + + + rf_ch_ind_wifi + 0 + 11 + + + + + rf_fsm_ctrl1 + rf_fsm_ctrl1. + 0x268 + + + rf_fsm_pu_pa_dly_n + 20 + 29 + + + rf_fsm_lo_rdy_sbclr + 19 + 19 + + + rf_fsm_lo_rdy_4s_1 + 18 + 18 + + + rf_fsm_lo_rdy_rst + 17 + 17 + + + rf_fsm_lo_rdy + 16 + 16 + + + rf_fsm_lo_time + 0 + 15 + + + + + rf_fsm_ctrl2 + rf_fsm_ctrl2. + 0x26C + + + rf_fsm_dfe_rx_dly_n + 20 + 29 + + + rf_fsm_dfe_tx_dly_n + 10 + 19 + + + rf_trx_ble_4s_en + 6 + 6 + + + rf_trx_sw_ble_4s + 5 + 5 + + + rf_trx_en_ble_4s + 4 + 4 + + + rf_fsm_st_dbg_en + 3 + 3 + + + rf_fsm_st_dbg + 0 + 2 + + + + + rf_pkdet_ctrl0 + rf_pkdet_ctrl0. + 0x270 + + + pkdet_out_mode + 5 + 5 + + + pkdet_out_cnt_en + 4 + 4 + + + pkdet_out_cnt_sts + 0 + 3 + + + + + dfe_ctrl_0 + dfe_ctrl_0. + 0x600 + + + tx_dvga_gain_ctrl_hw + 31 + 31 + + + tx_dvga_gain_qdb + 24 + 30 + + + tx_iqc_gain_en + 23 + 23 + + + tx_iqc_gain + 12 + 22 + + + tx_iqc_phase_en + 10 + 10 + + + tx_iqc_phase + 0 + 9 + + + + + dfe_ctrl_1 + dfe_ctrl_1. + 0x604 + + + tx_dac_iq_swap + 31 + 31 + + + tx_dac_dat_format + 30 + 30 + + + tx_dac_os_q + 16 + 27 + + + tx_dac_os_i + 0 + 11 + + + + + dfe_ctrl_2 + dfe_ctrl_2. + 0x608 + + + rx_adc_iq_swap + 31 + 31 + + + rx_adc_dat_format + 30 + 30 + + + rx_adc_low_pow_en + 29 + 29 + + + rx_adc_dce_flt_en + 28 + 28 + + + rx_adc_os_q + 16 + 25 + + + rx_adc_os_i + 0 + 9 + + + + + dfe_ctrl_3 + dfe_ctrl_3. + 0x60C + + + rx_adc_4s_q_en + 26 + 26 + + + rx_adc_4s_q_val + 16 + 25 + + + rx_adc_4s_i_en + 10 + 10 + + + rx_adc_4s_i_val + 0 + 9 + + + + + dfe_ctrl_4 + dfe_ctrl_4. + 0x610 + + + rx_pf_i_en + 31 + 31 + + + rx_pf_q_en + 30 + 30 + + + rx_pf_th1 + 16 + 25 + + + rx_pf_th2 + 0 + 9 + + + + + dfe_ctrl_5 + dfe_ctrl_5. + 0x614 + + + rx_iqc_gain_en + 23 + 23 + + + rx_iqc_gain + 12 + 22 + + + rx_iqc_phase_en + 10 + 10 + + + rx_iqc_phase + 0 + 9 + + + + + dfe_ctrl_6 + dfe_ctrl_6. + 0x618 + + + rx_pm_in_sel + 30 + 31 + + + rx_pm_en + 29 + 29 + + + rx_pm_done + 28 + 28 + + + rx_pm_freqshift_en + 20 + 20 + + + rx_pm_freqshift_cw + 0 + 19 + + + + + dfe_ctrl_7 + dfe_ctrl_7. + 0x61C + + + rx_pm_acc_len + 16 + 31 + + + rx_pm_start_ofs + 0 + 15 + + + + + dfe_ctrl_8 + dfe_ctrl_8. + 0x620 + + + rx_pm_iqacc_i + 0 + 24 + + + + + dfe_ctrl_9 + dfe_ctrl_9. + 0x624 + + + rx_pm_iqacc_q + 0 + 24 + + + + + dfe_ctrl_10 + dfe_ctrl_10. + 0x628 + + + dfe_dac_raw_q + 16 + 26 + + + dfe_dac_raw_i + 0 + 10 + + + + + dfe_ctrl_11 + dfe_ctrl_11. + 0x62C + + + dfe_adc_raw_q + 16 + 25 + + + dfe_adc_raw_i + 0 + 9 + + + + + dfe_ctrl_12 + dfe_ctrl_12. + 0x630 + + + tx_dvga_gain_qdb_gc3 + 24 + 30 + + + tx_dvga_gain_qdb_gc2 + 16 + 22 + + + tx_dvga_gain_qdb_gc1 + 8 + 14 + + + tx_dvga_gain_qdb_gc0 + 0 + 6 + + + + + dfe_ctrl_13 + dfe_ctrl_13. + 0x634 + + + tx_dvga_gain_qdb_gc7 + 24 + 30 + + + tx_dvga_gain_qdb_gc6 + 16 + 22 + + + tx_dvga_gain_qdb_gc5 + 8 + 14 + + + tx_dvga_gain_qdb_gc4 + 0 + 6 + + + + + dfe_ctrl_14 + dfe_ctrl_14. + 0x638 + + + tx_dvga_gain_qdb_gc11 + 24 + 30 + + + tx_dvga_gain_qdb_gc10 + 16 + 22 + + + tx_dvga_gain_qdb_gc9 + 8 + 14 + + + tx_dvga_gain_qdb_gc8 + 0 + 6 + + + + + dfe_ctrl_15 + dfe_ctrl_15. + 0x63C + + + tx_dvga_gain_qdb_gc15 + 24 + 30 + + + tx_dvga_gain_qdb_gc14 + 16 + 22 + + + tx_dvga_gain_qdb_gc13 + 8 + 14 + + + tx_dvga_gain_qdb_gc12 + 0 + 6 + + + + + dfe_ctrl_16 + dfe_ctrl_16. + 0x640 + + + rf_tbb_ind_gc7 + 28 + 30 + + + rf_tbb_ind_gc6 + 24 + 26 + + + rf_tbb_ind_gc5 + 20 + 22 + + + rf_tbb_ind_gc4 + 16 + 18 + + + rf_tbb_ind_gc3 + 12 + 14 + + + rf_tbb_ind_gc2 + 8 + 10 + + + rf_tbb_ind_gc1 + 4 + 6 + + + rf_tbb_ind_gc0 + 0 + 2 + + + + + dfe_ctrl_17 + dfe_ctrl_17. + 0x644 + + + rf_tbb_ind_gc15 + 28 + 30 + + + rf_tbb_ind_gc14 + 24 + 26 + + + rf_tbb_ind_gc13 + 20 + 22 + + + rf_tbb_ind_gc12 + 16 + 18 + + + rf_tbb_ind_gc11 + 12 + 14 + + + rf_tbb_ind_gc10 + 8 + 10 + + + rf_tbb_ind_gc9 + 4 + 6 + + + rf_tbb_ind_gc8 + 0 + 2 + + + + + dfe_ctrl_18 + dfe_ctrl_18. + 0x648 + + + tx_dvga_gain_qdb_ble_gc2 + 16 + 22 + + + tx_dvga_gain_qdb_ble_gc1 + 8 + 14 + + + tx_dvga_gain_qdb_ble_gc0 + 0 + 6 + + + + + + + gpip + gpip. + 0x40002000 + gpip + 32 + read-write + + 0 + 0x1000 + registers + + + + gpadc_config + gpadc_config. + 0x0 + + + rsvd_31_24 + 24 + 31 + + + gpadc_fifo_thl + 22 + 23 + + + gpadc_fifo_data_count + 16 + 21 + + + gpadc_fifo_underrun_mask + 14 + 14 + + + gpadc_fifo_overrun_mask + 13 + 13 + + + gpadc_rdy_mask + 12 + 12 + + + gpadc_fifo_underrun_clr + 10 + 10 + + + gpadc_fifo_overrun_clr + 9 + 9 + + + gpadc_rdy_clr + 8 + 8 + + + gpadc_fifo_underrun + 6 + 6 + + + gpadc_fifo_overrun + 5 + 5 + + + gpadc_rdy + 4 + 4 + + + gpadc_fifo_full + 3 + 3 + + + gpadc_fifo_ne + 2 + 2 + + + gpadc_fifo_clr + 1 + 1 + + + gpadc_dma_en + 0 + 0 + + + + + gpadc_dma_rdata + gpadc_dma_rdata. + 0x4 + + + rsvd_31_26 + 26 + 31 + + + gpadc_dma_rdata + 0 + 25 + + + + + gpdac_config + gpdac_config. + 0x40 + + + rsvd_31_24 + 24 + 31 + + + gpdac_ch_b_sel + 20 + 23 + + + gpdac_ch_a_sel + 16 + 19 + + + gpdac_mode + 8 + 10 + + + dsm_mode + 4 + 5 + + + gpdac_en2 + 1 + 1 + + + gpdac_en + 0 + 0 + + + + + gpdac_dma_config + gpdac_dma_config. + 0x44 + + + gpdac_dma_format + 4 + 5 + + + gpdac_dma_tx_en + 0 + 0 + + + + + gpdac_dma_wdata + gpdac_dma_wdata. + 0x48 + + + gpdac_dma_wdata + 0 + 31 + + + + + gpdac_tx_fifo_status + gpdac_tx_fifo_status. + 0x4C + + + TxFifoWrPtr + 8 + 9 + + + TxFifoRdPtr + 4 + 6 + + + tx_cs + 2 + 3 + + + tx_fifo_full + 1 + 1 + + + tx_fifo_empty + 0 + 0 + + + + + + + sec_dbg + sec_dbg. + 0x40003000 + sec_dbg + 32 + read-write + + 0 + 0x1000 + registers + + + + sd_chip_id_low + sd_chip_id_low. + 0x0 + + + sd_chip_id_low + 0 + 31 + + + + + sd_chip_id_high + sd_chip_id_high. + 0x4 + + + sd_chip_id_high + 0 + 31 + + + + + sd_wifi_mac_low + sd_wifi_mac_low. + 0x8 + + + sd_wifi_mac_low + 0 + 31 + + + + + sd_wifi_mac_high + sd_wifi_mac_high. + 0xC + + + sd_wifi_mac_high + 0 + 31 + + + + + sd_dbg_pwd_low + sd_dbg_pwd_low. + 0x10 + + + sd_dbg_pwd_low + 0 + 31 + + + + + sd_dbg_pwd_high + sd_dbg_pwd_high. + 0x14 + + + sd_dbg_pwd_high + 0 + 31 + + + + + sd_status + sd_status. + 0x18 + + + sd_dbg_ena + 28 + 31 + + + sd_dbg_mode + 24 + 27 + + + sd_dbg_pwd_cnt + 4 + 23 + + + sd_dbg_cci_clk_sel + 3 + 3 + + + sd_dbg_cci_read_en + 2 + 2 + + + sd_dbg_pwd_trig + 1 + 1 + + + sd_dbg_pwd_busy + 0 + 0 + + + + + sd_dbg_reserved + sd_dbg_reserved. + 0x1C + + + sd_dbg_reserved + 0 + 31 + + + + + + + sec_eng + sec_eng. + 0x40004000 + sec_eng + 32 + read-write + + 0 + 0x1000 + registers + + + + se_sha_0_ctrl + se_sha_0_ctrl. + 0x0 + + + se_sha_0_msg_len + 16 + 31 + + + se_sha_0_link_mode + 15 + 15 + + + se_sha_0_int_mask + 11 + 11 + + + se_sha_0_int_set_1t + 10 + 10 + + + se_sha_0_int_clr_1t + 9 + 9 + + + se_sha_0_int + 8 + 8 + + + se_sha_0_hash_sel + 6 + 6 + + + se_sha_0_en + 5 + 5 + + + se_sha_0_mode + 2 + 4 + + + se_sha_0_trig_1t + 1 + 1 + + + se_sha_0_busy + 0 + 0 + + + + + se_sha_0_msa + se_sha_0_msa. + 0x4 + + + se_sha_0_msa + 0 + 31 + + + + + se_sha_0_status + se_sha_0_status. + 0x8 + + + se_sha_0_status + 0 + 31 + + + + + se_sha_0_endian + se_sha_0_endian. + 0xC + + + se_sha_0_dout_endian + 0 + 0 + + + + + se_sha_0_hash_l_0 + se_sha_0_hash_l_0. + 0x10 + + + se_sha_0_hash_l_0 + 0 + 31 + + + + + se_sha_0_hash_l_1 + se_sha_0_hash_l_1. + 0x14 + + + se_sha_0_hash_l_1 + 0 + 31 + + + + + se_sha_0_hash_l_2 + se_sha_0_hash_l_2. + 0x18 + + + se_sha_0_hash_l_2 + 0 + 31 + + + + + se_sha_0_hash_l_3 + se_sha_0_hash_l_3. + 0x1C + + + se_sha_0_hash_l_3 + 0 + 31 + + + + + se_sha_0_hash_l_4 + se_sha_0_hash_l_4. + 0x20 + + + se_sha_0_hash_l_4 + 0 + 31 + + + + + se_sha_0_hash_l_5 + se_sha_0_hash_l_5. + 0x24 + + + se_sha_0_hash_l_5 + 0 + 31 + + + + + se_sha_0_hash_l_6 + se_sha_0_hash_l_6. + 0x28 + + + se_sha_0_hash_l_6 + 0 + 31 + + + + + se_sha_0_hash_l_7 + se_sha_0_hash_l_7. + 0x2C + + + se_sha_0_hash_l_7 + 0 + 31 + + + + + se_sha_0_hash_h_0 + se_sha_0_hash_h_0. + 0x30 + + + se_sha_0_hash_h_0 + 0 + 31 + + + + + se_sha_0_hash_h_1 + se_sha_0_hash_h_1. + 0x34 + + + se_sha_0_hash_h_1 + 0 + 31 + + + + + se_sha_0_hash_h_2 + se_sha_0_hash_h_2. + 0x38 + + + se_sha_0_hash_h_2 + 0 + 31 + + + + + se_sha_0_hash_h_3 + se_sha_0_hash_h_3. + 0x3C + + + se_sha_0_hash_h_3 + 0 + 31 + + + + + se_sha_0_hash_h_4 + se_sha_0_hash_h_4. + 0x40 + + + se_sha_0_hash_h_4 + 0 + 31 + + + + + se_sha_0_hash_h_5 + se_sha_0_hash_h_5. + 0x44 + + + se_sha_0_hash_h_5 + 0 + 31 + + + + + se_sha_0_hash_h_6 + se_sha_0_hash_h_6. + 0x48 + + + se_sha_0_hash_h_6 + 0 + 31 + + + + + se_sha_0_hash_h_7 + se_sha_0_hash_h_7. + 0x4C + + + se_sha_0_hash_h_7 + 0 + 31 + + + + + se_sha_0_link + se_sha_0_link. + 0x50 + + + se_sha_0_lca + 0 + 31 + + + + + se_sha_0_ctrl_prot + se_sha_0_ctrl_prot. + 0xFC + + + se_sha_id1_en + 2 + 2 + + + se_sha_id0_en + 1 + 1 + + + se_sha_prot_en + 0 + 0 + + + + + se_aes_0_ctrl + se_aes_0_ctrl. + 0x100 + + + se_aes_0_msg_len + 16 + 31 + + + se_aes_0_link_mode + 15 + 15 + + + se_aes_0_iv_sel + 14 + 14 + + + se_aes_0_block_mode + 12 + 13 + + + se_aes_0_int_mask + 11 + 11 + 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se_aes_0_key_1 + 0 + 31 + + + + + se_aes_0_key_2 + se_aes_0_key_2. + 0x128 + + + se_aes_0_key_2 + 0 + 31 + + + + + se_aes_0_key_3 + se_aes_0_key_3. + 0x12C + + + se_aes_0_key_3 + 0 + 31 + + + + + se_aes_0_key_4 + se_aes_0_key_4. + 0x130 + + + se_aes_0_key_4 + 0 + 31 + + + + + se_aes_0_key_5 + se_aes_0_key_5. + 0x134 + + + se_aes_0_key_5 + 0 + 31 + + + + + se_aes_0_key_6 + se_aes_0_key_6. + 0x138 + + + se_aes_0_key_6 + 0 + 31 + + + + + se_aes_0_key_7 + se_aes_0_key_7. + 0x13C + + + se_aes_0_key_7 + 0 + 31 + + + + + se_aes_0_key_sel_0 + se_aes_0_key_sel_0. + 0x140 + + + se_aes_0_key_sel_0 + 0 + 1 + + + + + se_aes_0_key_sel_1 + se_aes_0_key_sel_1. + 0x144 + + + se_aes_0_key_sel_1 + 0 + 1 + + + + + se_aes_0_endian + se_aes_0_endian. + 0x148 + + + se_aes_0_ctr_len + 30 + 31 + + + se_aes_0_iv_endian + 3 + 3 + + + se_aes_0_key_endian + 2 + 2 + + + se_aes_0_din_endian + 1 + 1 + + + se_aes_0_dout_endian + 0 + 0 + + + + + se_aes_0_sboot + se_aes_0_sboot. + 0x14C + + + se_aes_0_sboot_key_sel + 0 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ef_key_slot_5_w0. + 0x6C + + + ef_key_slot_5_w0 + 0 + 31 + + + + + ef_key_slot_5_w1 + ef_key_slot_5_w1. + 0x70 + + + ef_key_slot_5_w1 + 0 + 31 + + + + + ef_key_slot_5_w2 + ef_key_slot_5_w2. + 0x74 + + + ef_key_slot_5_w2 + 0 + 31 + + + + + ef_key_slot_5_w3 + ef_key_slot_5_w3. + 0x78 + + + ef_key_slot_5_w3 + 0 + 31 + + + + + ef_data_0_lock + ef_data_0_lock. + 0x7C + + + rd_lock_key_slot_5 + 31 + 31 + + + rd_lock_key_slot_4 + 30 + 30 + + + rd_lock_key_slot_3 + 29 + 29 + + + rd_lock_key_slot_2 + 28 + 28 + + + rd_lock_key_slot_1 + 27 + 27 + + + rd_lock_key_slot_0 + 26 + 26 + + + rd_lock_dbg_pwd + 25 + 25 + + + wr_lock_key_slot_5_h + 24 + 24 + + + wr_lock_key_slot_4_h + 23 + 23 + + + wr_lock_key_slot_3 + 22 + 22 + + + wr_lock_key_slot_2 + 21 + 21 + + + wr_lock_key_slot_1 + 20 + 20 + + + wr_lock_key_slot_0 + 19 + 19 + + + wr_lock_wifi_mac + 18 + 18 + + + wr_lock_sw_usage_0 + 17 + 17 + + + wr_lock_dbg_pwd + 16 + 16 + + + wr_lock_boot_mode + 15 + 15 + + + wr_lock_key_slot_5_l + 14 + 14 + + + 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reg_key_slot_8_w1. + 0xA4 + + + reg_key_slot_8_w1 + 0 + 31 + + + + + reg_key_slot_8_w2 + reg_key_slot_8_w2. + 0xA8 + + + reg_key_slot_8_w2 + 0 + 31 + + + + + reg_key_slot_8_w3 + reg_key_slot_8_w3. + 0xAC + + + reg_key_slot_8_w3 + 0 + 31 + + + + + reg_key_slot_9_w0 + reg_key_slot_9_w0. + 0xB0 + + + reg_key_slot_9_w0 + 0 + 31 + + + + + reg_key_slot_9_w1 + reg_key_slot_9_w1. + 0xB4 + + + reg_key_slot_9_w1 + 0 + 31 + + + + + reg_key_slot_9_w2 + reg_key_slot_9_w2. + 0xB8 + + + reg_key_slot_9_w2 + 0 + 31 + + + + + reg_key_slot_9_w3 + reg_key_slot_9_w3. + 0xBC + + + reg_key_slot_9_w3 + 0 + 31 + + + + + reg_key_slot_10_w0 + reg_key_slot_10_w0. + 0xC0 + + + + reg_key_slot_10_w1 + reg_key_slot_10_w1. + 0xC4 + + + + reg_key_slot_10_w2 + reg_key_slot_10_w2. + 0xC8 + + + + reg_key_slot_10_w3 + reg_key_slot_10_w3. + 0xCC + + + + reg_key_slot_11_w0 + reg_key_slot_11_w0. + 0xD0 + + + + reg_key_slot_11_w1 + reg_key_slot_11_w1. + 0xD4 + + + + reg_key_slot_11_w2 + reg_key_slot_11_w2. + 0xD8 + + + + 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3 + + + cci_read_flag + 1 + 1 + + + cci_write_flag + 0 + 0 + + + + + + + l1c + l1c. + 0x40009000 + l1c + 32 + read-write + + 0 + 0x1000 + registers + + + + l1c_config + l1c_config. + 0x0 + + + wrap_dis + 26 + 26 + + + early_resp_dis + 25 + 25 + + + l1c_bmx_busy_option_dis + 24 + 24 + + + l1c_bmx_timeout_en + 20 + 23 + + + l1c_bmx_arb_mode + 16 + 17 + + + l1c_bmx_err_en + 15 + 15 + + + l1c_bypass + 14 + 14 + + + irom_2t_access + 12 + 12 + + + l1c_way_dis + 8 + 11 + + + l1c_invalid_done + 3 + 3 + + + l1c_invalid_en + 2 + 2 + + + l1c_cnt_en + 1 + 1 + + + l1c_cacheable + 0 + 0 + + + + + hit_cnt_lsb + hit_cnt_lsb. + 0x4 + + + hit_cnt_lsb + 0 + 31 + + + + + hit_cnt_msb + hit_cnt_msb. + 0x8 + + + hit_cnt_msb + 0 + 31 + + + + + miss_cnt + miss_cnt. + 0xC + + + miss_cnt + 0 + 31 + + + + + l1c_range + l1c_range. + 0x10 + + + + l1c_bmx_err_addr_en + l1c_bmx_err_addr_en. + 0x200 + + + l1c_hsel_option + 16 + 19 + + + l1c_bmx_err_tz + 5 + 5 + + + l1c_bmx_err_dec + 4 + 4 + + + l1c_bmx_err_addr_dis + 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+ 19 + + + gpadc_dwa_en + 18 + 18 + + + gpadc_byp_micboost + 16 + 16 + + + gpadc_micpga_en + 15 + 15 + + + gpadc_micbias_en + 14 + 14 + + + gpadc_neg_gnd + 13 + 13 + + + gpadc_pos_sel + 8 + 12 + + + gpadc_neg_sel + 3 + 7 + + + gpadc_soft_rst + 2 + 2 + + + gpadc_conv_start + 1 + 1 + + + gpadc_global_en + 0 + 0 + + + + + gpadc_reg_config1 + gpadc_reg_config1. + 0x910 + + + gpadc_v18_sel + 29 + 30 + + + gpadc_v11_sel + 27 + 28 + + + gpadc_dither_en + 26 + 26 + + + gpadc_scan_en + 25 + 25 + + + gpadc_scan_length + 21 + 24 + + + gpadc_clk_div_ratio + 18 + 20 + + + gpadc_clk_ana_inv + 17 + 17 + + + gpadc_res_sel + 2 + 4 + + + gpadc_cont_conv_en + 1 + 1 + + + gpadc_cal_os_en + 0 + 0 + + + + + gpadc_reg_config2 + gpadc_reg_config2. + 0x914 + + + gpadc_tsvbe_low + 31 + 31 + + + gpadc_dly_sel + 28 + 30 + + + gpadc_pga1_gain + 25 + 27 + + + gpadc_pga2_gain + 22 + 24 + + + gpadc_test_sel + 19 + 21 + + + gpadc_test_en + 18 + 18 + + + gpadc_bias_sel + 17 + 17 + + + gpadc_chop_mode + 15 + 16 + + + gpadc_pga_vcmi_en + 14 + 14 + + + gpadc_pga_en + 13 + 13 + + + gpadc_pga_os_cal + 9 + 12 + + + gpadc_pga_vcm + 7 + 8 + + + gpadc_ts_en + 6 + 6 + + + gpadc_tsext_sel + 5 + 5 + + + gpadc_vbat_en + 4 + 4 + + + gpadc_vref_sel + 3 + 3 + + + gpadc_diff_mode + 2 + 2 + + + + + gpadc_reg_scn_pos1 + adc converation sequence 1 + 0x918 + + + gpadc_scan_pos_5 + 25 + 29 + + + gpadc_scan_pos_4 + 20 + 24 + + + gpadc_scan_pos_3 + 15 + 19 + + + gpadc_scan_pos_2 + 10 + 14 + + + gpadc_scan_pos_1 + 5 + 9 + + + gpadc_scan_pos_0 + 0 + 4 + + + + + gpadc_reg_scn_pos2 + adc converation sequence 2 + 0x91C + + + gpadc_scan_pos_11 + 25 + 29 + + + gpadc_scan_pos_10 + 20 + 24 + + + gpadc_scan_pos_9 + 15 + 19 + + + gpadc_scan_pos_8 + 10 + 14 + + + gpadc_scan_pos_7 + 5 + 9 + + + gpadc_scan_pos_6 + 0 + 4 + + + + + gpadc_reg_scn_neg1 + adc converation sequence 3 + 0x920 + + + gpadc_scan_neg_5 + 25 + 29 + + + gpadc_scan_neg_4 + 20 + 24 + + + gpadc_scan_neg_3 + 15 + 19 + + + gpadc_scan_neg_2 + 10 + 14 + + + gpadc_scan_neg_1 + 5 + 9 + + + gpadc_scan_neg_0 + 0 + 4 + + + + + gpadc_reg_scn_neg2 + adc converation sequence 4 + 0x924 + + + gpadc_scan_neg_11 + 25 + 29 + + + gpadc_scan_neg_10 + 20 + 24 + + + gpadc_scan_neg_9 + 15 + 19 + + + gpadc_scan_neg_8 + 10 + 14 + + + gpadc_scan_neg_7 + 5 + 9 + + + gpadc_scan_neg_6 + 0 + 4 + + + + + gpadc_reg_status + gpadc_reg_status. + 0x928 + + + gpadc_reserved + 16 + 31 + + + gpadc_data_rdy + 0 + 0 + + + + + gpadc_reg_isr + gpadc_reg_isr. + 0x92C + + + gpadc_pos_satur_mask + 9 + 9 + + + gpadc_neg_satur_mask + 8 + 8 + + + gpadc_pos_satur_clr + 5 + 5 + + + gpadc_neg_satur_clr + 4 + 4 + + + gpadc_pos_satur + 1 + 1 + + + gpadc_neg_satur + 0 + 0 + + + + + gpadc_reg_result + gpadc_reg_result. + 0x930 + + + gpadc_data_out + 0 + 25 + + + + + gpadc_reg_raw_result + gpadc_reg_raw_result. + 0x934 + + + gpadc_raw_data + 0 + 11 + + + + + gpadc_reg_define + gpadc_reg_define. + 0x938 + + + gpadc_os_cal_data + 0 + 15 + + + + + hbncore_resv0 + hbncore_resv0. + 0x93C + + + hbncore_resv0_data + 0 + 31 + + + + + hbncore_resv1 + hbncore_resv1. + 0x940 + + + hbncore_resv1_data + 0 + 31 + + + + + + + diff --git a/drivers/bl602_driver/regs/spi_reg.h b/drivers/bl602_driver/regs/spi_reg.h new file mode 100644 index 00000000..06171988 --- /dev/null +++ b/drivers/bl602_driver/regs/spi_reg.h @@ -0,0 +1,513 @@ +/** + ****************************************************************************** + * @file spi_reg.h + * @version V1.2 + * @date 2019-10-21 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __SPI_REG_H__ +#define __SPI_REG_H__ + +#include "bl602.h" + +/* 0x0 : spi_config */ +#define SPI_CONFIG_OFFSET (0x0) +#define SPI_CR_SPI_M_EN SPI_CR_SPI_M_EN +#define SPI_CR_SPI_M_EN_POS (0U) +#define SPI_CR_SPI_M_EN_LEN (1U) +#define SPI_CR_SPI_M_EN_MSK (((1U<
© COPYRIGHT(c) 2019 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __TIMER_REG_H__ +#define __TIMER_REG_H__ + +#include "bl602.h" + +/* 0x0 : TCCR */ +#define TIMER_TCCR_OFFSET (0x0) +#define TIMER_CS_1 TIMER_CS_1 +#define TIMER_CS_1_POS (2U) +#define TIMER_CS_1_LEN (2U) +#define TIMER_CS_1_MSK (((1U<
© COPYRIGHT(c) 2019 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __TZC_NSEC_REG_H__ +#define __TZC_NSEC_REG_H__ + +#include "bl602.h" + +/* 0x40 : tzc_rom_ctrl */ +#define TZC_NSEC_TZC_ROM_CTRL_OFFSET (0x40) +#define TZC_NSEC_TZC_ROM0_R0_ID0_EN TZC_NSEC_TZC_ROM0_R0_ID0_EN +#define TZC_NSEC_TZC_ROM0_R0_ID0_EN_POS (0U) +#define TZC_NSEC_TZC_ROM0_R0_ID0_EN_LEN (1U) +#define TZC_NSEC_TZC_ROM0_R0_ID0_EN_MSK (((1U<
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __TZC_SEC_REG_H__ +#define __TZC_SEC_REG_H__ + +#include "bl602.h" + +/* 0x40 : tzc_rom_ctrl */ +#define TZC_SEC_TZC_ROM_CTRL_OFFSET (0x40) +#define TZC_SEC_TZC_ROM0_R0_ID0_EN TZC_SEC_TZC_ROM0_R0_ID0_EN +#define TZC_SEC_TZC_ROM0_R0_ID0_EN_POS (0U) +#define TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN (1U) +#define TZC_SEC_TZC_ROM0_R0_ID0_EN_MSK (((1U<
© COPYRIGHT(c) 2019 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __UART_REG_H__ +#define __UART_REG_H__ + +#include "bl602.h" + +/* 0x0 : utx_config */ +#define UART_UTX_CONFIG_OFFSET (0x0) +#define UART_CR_UTX_EN UART_CR_UTX_EN +#define UART_CR_UTX_EN_POS (0U) +#define UART_CR_UTX_EN_LEN (1U) +#define UART_CR_UTX_EN_MSK (((1U<> 24); + res &= 0xFF0000FF; /* only for sure */ + res |= ((value >> 8) & 0x0000FF00) | ((value << 8) & 0x00FF0000); + + return res; +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + return __builtin_bswap16(value); +} + +extern void clic_enable_interrupt (uint32_t source); +extern void clic_disable_interrupt ( uint32_t source); +extern void clic_set_pending(uint32_t source); +extern void clic_clear_pending(uint32_t source); + +#define NVIC_EnableIRQ clic_enable_interrupt + +#define NVIC_DisableIRQ clic_disable_interrupt + +#define NVIC_ClearPendingIRQ clic_clear_pending + +//#define __set_MSP(val) __ASM volatile ("lw sp,0(%0)":: "r"(val)) +#define __set_MSP(msp) __ASM volatile ("add sp, x0, %0":: "r"(msp)) + +#endif /* __CMSIS_COMPATIBLE_GCC_H */ diff --git a/drivers/bl602_driver/risc-v/Core/Include/riscv_bits.h b/drivers/bl602_driver/risc-v/Core/Include/riscv_bits.h new file mode 100644 index 00000000..bfe656fe --- /dev/null +++ b/drivers/bl602_driver/risc-v/Core/Include/riscv_bits.h @@ -0,0 +1,36 @@ +// See LICENSE for license details. +#ifndef _RISCV_BITS_H +#define _RISCV_BITS_H + +#define likely(x) __builtin_expect((x), 1) +#define unlikely(x) __builtin_expect((x), 0) + +#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b)) +#define ROUNDDOWN(a, b) ((a)/(b)*(b)) + +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) + +#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) +#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) + +#define STR(x) XSTR(x) +#define XSTR(x) #x + +#if __riscv_xlen == 64 +# define SLL32 sllw +# define STORE sd +# define LOAD ld +# define LWU lwu +# define LOG_REGBYTES 3 +#else +# define SLL32 sll +# define STORE sw +# define LOAD lw +# define LWU lw +# define LOG_REGBYTES 2 +#endif +#define REGBYTES (1 << LOG_REGBYTES) + +#endif diff --git a/drivers/bl602_driver/risc-v/Core/Include/riscv_const.h b/drivers/bl602_driver/risc-v/Core/Include/riscv_const.h new file mode 100644 index 00000000..d5dec8ac --- /dev/null +++ b/drivers/bl602_driver/risc-v/Core/Include/riscv_const.h @@ -0,0 +1,18 @@ +// See LICENSE for license details. +/* Derived from */ + +#ifndef _RISCV_CONST_H +#define _RISCV_CONST_H + +#ifdef __ASSEMBLER__ +#define _AC(X,Y) X +#define _AT(T,X) X +#else +#define _AC(X,Y) (X##Y) +#define _AT(T,X) ((T)(X)) +#endif /* !__ASSEMBLER__*/ + +#define _BITUL(x) (_AC(1,UL) << (x)) +#define _BITULL(x) (_AC(1,ULL) << (x)) + +#endif /* _NUCLEI_CONST_H */ diff --git a/drivers/bl602_driver/risc-v/Core/Include/riscv_encoding.h b/drivers/bl602_driver/risc-v/Core/Include/riscv_encoding.h new file mode 100644 index 00000000..65fdbb16 --- /dev/null +++ b/drivers/bl602_driver/risc-v/Core/Include/riscv_encoding.h @@ -0,0 +1,1370 @@ +// See LICENSE for license details. + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_PUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_VM 0x1F000000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS64_SD 0x8000000000000000 + + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_PUM 0x00040000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define MIE_SSIE MIP_SSIP +#define MIE_HSIE MIP_HSIP +#define MIE_MSIE MIP_MSIP +#define MIE_STIE MIP_STIP +#define MIE_HTIE MIP_HTIP +#define MIE_MTIE MIP_MTIP +#define MIE_SEIE MIP_SEIP +#define MIE_HEIE MIP_HEIP +#define MIE_MEIE MIP_MEIP + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define VM_MBARE 0 +#define VM_MBB 1 +#define VM_MBBID 2 +#define VM_SV32 8 +#define VM_SV39 9 +#define VM_SV48 10 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define DEFAULT_NMIVEC 0x00001004 +#define DEFAULT_MTVEC 0x00001010 +#define CONFIG_STRING_ADDR 0x0000100C +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#ifdef __riscv64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define asm __asm + +#define read_fpu(reg) ({ unsigned long __tmp; \ + asm volatile ("fmv.x.w %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_fpu(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("fmv.w.x " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("fmv.w.x " #reg ", %0" :: "r"(val)); }) + + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ + else \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + + + + + + +#endif + +#endif + +#endif + +#endif +/* Automatically generated by parse-opcodes */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_HRET 0x20200073 +#define MASK_HRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VM 0x10400073 +#define MASK_SFENCE_VM 0xfff07fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_S 0xe0000053 +#define MASK_FMV_X_S 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_S_X 0xf0000053 +#define MASK_FMV_S_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_SBADADDR 0x143 +#define CSR_SIP 0x144 +#define CSR_SPTBR 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MBADADDR 0x343 +#define CSR_MIP 0x344 +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MUCOUNTEREN 0x320 +#define CSR_MSCOUNTEREN 0x321 +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f + + +#define CSR_MTVT 0x307 +#define CSR_MNXTI 0x345 + +#define CSR_MCOUNTINHIBIT 0x320 + +#define CSR_MNVEC 0x7C3 + +#define CSR_MTVT2 0x7EC +#define CSR_JALMNXTI 0x7ED +#define CSR_PUSHMCAUSE 0x7EE +#define CSR_PUSHMEPC 0x7EF +#define CSR_PUSHMSUBM 0x7EB + +#define CSR_WFE 0x810 +#define CSR_SLEEPVALUE 0x811 +#define CSR_TXEVT 0x812 + +#define CSR_MMISC_CTL 0x7d0 +#define CSR_MSUBM 0x7c4 + + +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FAULT_FETCH 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_FAULT_LOAD 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_FAULT_STORE 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, +MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, +MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, +MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, +MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(sbadaddr, CSR_SBADADDR) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(sptbr, CSR_SPTBR) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mbadaddr, CSR_MBADADDR) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) +DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +#endif + diff --git a/drivers/bl602_driver/startup/GCC/entry.S b/drivers/bl602_driver/startup/GCC/entry.S new file mode 100644 index 00000000..dccee584 --- /dev/null +++ b/drivers/bl602_driver/startup/GCC/entry.S @@ -0,0 +1,131 @@ +/* Copyright 2018 SiFive, Inc */ +/* SPDX-License-Identifier: Apache-2.0 */ +#include "riscv_encoding.h" + +/* This code executes before _start, which is contained inside the C library. + * In embedded systems we want to ensure that _enter, which contains the first + * code to be executed, can be loaded at a specific address. To enable this + * feature we provide the '.text.metal.init.enter' section, which is + * defined to have the first address being where execution should start. */ +.section .text.metal.init.enter +.global _enter +_enter: + .cfi_startproc + + /* Inform the debugger that there is nowhere to backtrace past _enter. */ + .cfi_undefined ra + + /* The absolute first thing that must happen is configuring the global + * pointer register, which must be done with relaxation disabled because + * it's not valid to obtain the address of any symbol without GP + * configured. The C environment might go ahead and do this again, but + * that's safe as it's a fixed register. */ +.option push +.option norelax + la gp, __global_pointer$ +.option pop + + /* Disable global interrupt */ + /*clear_csr(mstatus, MSTATUS_MIE);*/ + csrci mstatus,8 + + /* Set up a simple trap vector to catch anything that goes wrong early in + * the boot process. */ + la t0, Trap_Handler_Stub + /* enable CLIC Vectored mode */ + ori t0,t0,3 + csrw mtvec, t0 + /* enable chicken bit if core is bullet series*/ + la t0, __metal_chicken_bit + beqz t0, 1f + csrwi 0x7C1, 0 +1: + + /* There may be pre-initialization routines inside the MBI code that run in + * C, so here we set up a C environment. First we set up a stack pointer, + * which is left as a weak reference in order to allow initialization + * routines that do not need a stack to be set up to transparently be + * called. */ + .weak __StackTop + la sp, __StackTop + + /* Intial the mtvt, MUST BE 64 bytes aligned*/ + .weak __Vectors + la t0, __Vectors + csrw mtvt, t0 + +#if __riscv_float_abi_single + /* deal with FP */ + /* Is F extension present? */ + csrr t0, misa + andi t0, t0, (1 << ('F' - 'A')) + beqz t0, 1f + /* If so, enable it */ + li t0, MSTATUS_FS + csrs mstatus, t0 + fssr x0 +1: +#endif + + /* Check for an initialization routine and call it if one exists, otherwise + * just skip over the call entirely. Note that __metal_initialize isn't + * actually a full C function, as it doesn't end up with the .bss or .data + * segments having been initialized. This is done to avoid putting a + * burden on systems that can be initialized without having a C environment + * set up. */ + call SystemInit + + /* start load code to itcm like. */ + call start_load + + /* At this point we can enter the C runtime's startup file. The arguments + * to this function are designed to match those provided to the SEE, just + * so we don't have to write another ABI. */ + csrr a0, mhartid + li a1, 0 + li a2, 0 + call main + + /* If we've made it back here then there's probably something wrong. We + * allow the METAL to register a handler here. */ + .weak __metal_after_main + la ra, __metal_after_main + beqz ra, 1f + jalr ra +1: + + /* If that handler returns then there's not a whole lot we can do. Just + * try to make some noise. */ + la t0, 1f + csrw mtvec, t0 +1: + lw t1, 0(x0) + j 1b + + .cfi_endproc + +/* For sanity's sake we set up an early trap vector that just does nothing. If + * you end up here then there's a bug in the early boot code somewhere. */ +.weak Trap_Handler_Stub +.section .text.metal.init.trapvec +.align 2 +Trap_Handler_Stub: + .cfi_startproc + csrr t0, mcause + csrr t1, mepc + csrr t2, mtval + j Trap_Handler_Stub + .cfi_endproc + +/* The GCC port might not emit a __register_frame_info symbol, which eventually + * results in a weak undefined reference that eventually causes crash when it + * is dereference early in boot. We really shouldn't need to put this here, + * but to deal with what I think is probably a bug in the linker script I'm + * going to leave this in for now. At least it's fairly cheap :) */ +.weak __register_frame_info +.global __register_frame_info +.section .text.metal.init.__register_frame_info +__register_frame_info: + .cfi_startproc + ret + .cfi_endproc diff --git a/drivers/bl602_driver/startup/GCC/start_load.c b/drivers/bl602_driver/startup/GCC/start_load.c new file mode 100644 index 00000000..0f226274 --- /dev/null +++ b/drivers/bl602_driver/startup/GCC/start_load.c @@ -0,0 +1,85 @@ +#include +#include "bl602.h" + +#define __STARTUP_CLEAR_BSS 1 + +/*---------------------------------------------------------------------------- + Linker generated Symbols + *----------------------------------------------------------------------------*/ +extern uint32_t __itcm_load_addr; +extern uint32_t __dtcm_load_addr; +extern uint32_t __system_ram_load_addr; +extern uint32_t __ram_load_addr; + +extern uint32_t __text_code_start__; +extern uint32_t __text_code_end__; +extern uint32_t __tcm_code_start__; +extern uint32_t __tcm_code_end__; +extern uint32_t __tcm_data_start__; +extern uint32_t __tcm_data_end__; +extern uint32_t __system_ram_data_start__; +extern uint32_t __system_ram_data_end__; +extern uint32_t __ram_data_start__; +extern uint32_t __ram_data_end__; +extern uint32_t __bss_start__; +extern uint32_t __bss_end__; +extern uint32_t __noinit_data_start__; +extern uint32_t __noinit_data_end__; + +extern uint32_t __StackTop; +extern uint32_t __StackLimit; + + +//extern uint32_t __copy_table_start__; +//extern uint32_t __copy_table_end__; +//extern uint32_t __zero_table_start__; +//extern uint32_t __zero_table_end__; + + +void start_load(void) { + uint32_t *pSrc, *pDest; + uint32_t *pTable __attribute__((unused)); + + /* Copy ITCM code */ + pSrc = &__itcm_load_addr; + pDest = &__tcm_code_start__; + for ( ; pDest < &__tcm_code_end__ ; ) { + *pDest++ = *pSrc++; + } + + /* Copy DTCM code */ + pSrc = &__dtcm_load_addr; + pDest = &__tcm_data_start__; + for( ; pDest < &__tcm_data_end__; ){ + *pDest++ = *pSrc++; + } + + /* BF Add system RAM data copy */ + pSrc = &__system_ram_load_addr; + pDest = &__system_ram_data_start__; + for ( ; pDest < &__system_ram_data_end__ ; ) { + *pDest++ = *pSrc++; + } + + /* BF Add OCARAM data copy */ + pSrc = &__ram_load_addr; + pDest = &__ram_data_start__; + for ( ; pDest < &__ram_data_end__ ; ) { + *pDest++ = *pSrc++; + } + +#ifdef __STARTUP_CLEAR_BSS + /* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + pDest = &__bss_start__; + for ( ; pDest < &__bss_end__ ; ) { + *pDest++ = 0ul; + } +#endif +} diff --git a/drivers/bl602_driver/startup/interrupt.c b/drivers/bl602_driver/startup/interrupt.c new file mode 100644 index 00000000..0b19b13b --- /dev/null +++ b/drivers/bl602_driver/startup/interrupt.c @@ -0,0 +1,181 @@ +#include + +#include "../risc-v/Core/Include/clic.h" +#include "../risc-v/Core/Include/cmsis_compatible_gcc.h" + +typedef void( *pFunc )( void ); +extern void Trap_Handler(void); +extern void Interrupt_Handler(void); +void Interrupt_Handler_Stub(void); + +void clic_msip_handler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void clic_mtimer_handler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void clic_mext_handler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void clic_csoft_handler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void BMX_ERR_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void BMX_TO_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void L1C_BMX_ERR_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void L1C_BMX_TO_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void SEC_BMX_ERR_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void RF_TOP_INT0_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void RF_TOP_INT1_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void SDIO_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void DMA_BMX_ERR_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void SEC_GMAC_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void SEC_CDET_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void SEC_PKA_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void SEC_TRNG_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void SEC_AES_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void SEC_SHA_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void DMA_ALL_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void IRTX_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void IRRX_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void SF_CTRL_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void GPADC_DMA_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void EFUSE_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void SPI_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void UART0_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void UART1_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void I2C_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void PWM_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void TIMER_CH0_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void TIMER_CH1_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void TIMER_WDT_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void GPIO_INT0_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void PDS_WAKEUP_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void HBN_OUT0_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void HBN_OUT1_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void BOR_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void WIFI_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void BZ_PHY_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void BLE_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void MAC_TXRX_TIMER_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void MAC_TXRX_MISC_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void MAC_RX_TRG_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void MAC_TX_TRG_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void MAC_GEN_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void MAC_PORT_TRG_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); +void WIFI_IPC_PUBLIC_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub"))); + +const pFunc __Vectors[] __attribute__ ((section(".init"),aligned(64))) = { + 0, /* */ + 0, /* */ + 0, /* */ + clic_msip_handler_Wrapper, /* */ + 0, /* */ + 0, /* */ + 0, /* */ + clic_mtimer_handler_Wrapper, /* */ + (pFunc)0x00000004, /* */ + (pFunc)0x00001007, /* */ + (pFunc)0x00010002, /* */ + clic_mext_handler_Wrapper, /* */ + clic_csoft_handler_Wrapper, /* */ + (pFunc)2000000, /* */ + 0, /* */ + 0, /* */ + BMX_ERR_IRQHandler_Wrapper, /* 16 + 0 */ + BMX_TO_IRQHandler_Wrapper, /* 16 + 1 */ + L1C_BMX_ERR_IRQHandler_Wrapper, /* 16 + 2 */ + L1C_BMX_TO_IRQHandler_Wrapper, /* 16 + 3 */ + SEC_BMX_ERR_IRQHandler_Wrapper, /* 16 + 4 */ + RF_TOP_INT0_IRQHandler_Wrapper, /* 16 + 5 */ + RF_TOP_INT1_IRQHandler_Wrapper, /* 16 + 6 */ + SDIO_IRQHandler_Wrapper, /* 16 + 7 */ + DMA_BMX_ERR_IRQHandler_Wrapper, /* 16 + 8 */ + SEC_GMAC_IRQHandler_Wrapper, /* 16 + 9 */ + SEC_CDET_IRQHandler_Wrapper, /* 16 + 10 */ + SEC_PKA_IRQHandler_Wrapper, /* 16 + 11 */ + SEC_TRNG_IRQHandler_Wrapper, /* 16 + 12 */ + SEC_AES_IRQHandler_Wrapper, /* 16 + 13 */ + SEC_SHA_IRQHandler_Wrapper, /* 16 + 14 */ + DMA_ALL_IRQHandler_Wrapper, /* 16 + 15 */ + 0, /* 16 + 16 */ + 0, /* 16 + 17 */ + 0, /* 16 + 18 */ + IRTX_IRQHandler_Wrapper, /* 16 + 19 */ + IRRX_IRQHandler_Wrapper, /* 16 + 20 */ + 0, /* 16 + 21 */ + 0, /* 16 + 22 */ + SF_CTRL_IRQHandler_Wrapper, /* 16 + 23 */ + 0, /* 16 + 24 */ + GPADC_DMA_IRQHandler_Wrapper, /* 16 + 25 */ + EFUSE_IRQHandler_Wrapper, /* 16 + 26 */ + SPI_IRQHandler_Wrapper, /* 16 + 27 */ + 0, /* 16 + 28 */ + UART0_IRQHandler_Wrapper, /* 16 + 29 */ + UART1_IRQHandler_Wrapper, /* 16 + 30 */ + 0, /* 16 + 31 */ + I2C_IRQHandler_Wrapper, /* 16 + 32 */ + 0, /* 16 + 33 */ + PWM_IRQHandler_Wrapper, /* 16 + 34 */ + 0, /* 16 + 35 */ + TIMER_CH0_IRQHandler_Wrapper, /* 16 + 36 */ + TIMER_CH1_IRQHandler_Wrapper, /* 16 + 37 */ + TIMER_WDT_IRQHandler_Wrapper, /* 16 + 38 */ + 0, /* 16 + 39 */ + 0, /* 16 + 40 */ + 0, /* 16 + 41 */ + 0, /* 16 + 42 */ + 0, /* 16 + 43 */ + GPIO_INT0_IRQHandler_Wrapper, /* 16 + 44 */ + 0, /* 16 + 45 */ + 0, /* 16 + 46 */ + 0, /* 16 + 47 */ + 0, /* 16 + 48 */ + 0, /* 16 + 49 */ + PDS_WAKEUP_IRQHandler_Wrapper, /* 16 + 50 */ + HBN_OUT0_IRQHandler_Wrapper, /* 16 + 51 */ + HBN_OUT1_IRQHandler_Wrapper, /* 16 + 52 */ + BOR_IRQHandler_Wrapper, /* 16 + 53 */ + WIFI_IRQHandler_Wrapper, /* 16 + 54 */ + BZ_PHY_IRQHandler_Wrapper, /* 16 + 55 */ + BLE_IRQHandler_Wrapper, /* 16 + 56 */ + MAC_TXRX_TIMER_IRQHandler_Wrapper, /* 16 + 57 */ + MAC_TXRX_MISC_IRQHandler_Wrapper, /* 16 + 58 */ + MAC_RX_TRG_IRQHandler_Wrapper, /* 16 + 59 */ + MAC_TX_TRG_IRQHandler_Wrapper, /* 16 + 60 */ + MAC_GEN_IRQHandler_Wrapper, /* 16 + 61 */ + MAC_PORT_TRG_IRQHandler_Wrapper, /* 16 + 62 */ + WIFI_IPC_PUBLIC_IRQHandler_Wrapper, /* 16 + 63 */ +}; + +void __IRQ_ALIGN64 Trap_Handler_Stub(void){ + Trap_Handler(); +} + +void __IRQ Interrupt_Handler_Stub(void){ + Interrupt_Handler(); +} + +void clic_enable_interrupt (uint32_t source) { + *(volatile uint8_t*)(CLIC_HART0_ADDR+CLIC_INTIE+source) = 1; +} + +void clic_disable_interrupt ( uint32_t source){ + *(volatile uint8_t*)(CLIC_HART0_ADDR+CLIC_INTIE+source) = 0; +} + +void clic_set_pending(uint32_t source){ + *(volatile uint8_t*)(CLIC_HART0_ADDR+CLIC_INTIP+source) = 1; +} + +void clic_clear_pending(uint32_t source){ + *(volatile uint8_t*)(CLIC_HART0_ADDR+CLIC_INTIP+source) = 0; +} + +void clic_set_intcfg (uint32_t source, uint32_t intcfg){ + *(volatile uint8_t*)(CLIC_HART0_ADDR+CLIC_INTCFG+source) = intcfg; +} + +uint8_t clic_get_intcfg ( uint32_t source){ + return *(volatile uint8_t*)(CLIC_HART0_ADDR+CLIC_INTCFG+source); +} + +void clic_set_cliccfg ( uint32_t cfg){ + *(volatile uint8_t*)(CLIC_HART0_ADDR+CLIC_CFG) = cfg; +} + +uint8_t clic_get_cliccfg (void){ + return *(volatile uint8_t*)(CLIC_HART0_ADDR+CLIC_CFG); +} diff --git a/drivers/bl602_driver/startup/system_bl602.c b/drivers/bl602_driver/startup/system_bl602.c new file mode 100644 index 00000000..b77efc7b --- /dev/null +++ b/drivers/bl602_driver/startup/system_bl602.c @@ -0,0 +1,135 @@ +#include "bl602.h" +#include "bl602_glb.h" +#include "bl602_hbn.h" +#include "system_bl602.h" + +#ifdef BOOTROM +#include "bflb_bootrom.h" +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define SYSTEM_CLOCK ( 32000000UL ) + +/*---------------------------------------------------------------------------- + Vector Table + *----------------------------------------------------------------------------*/ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ + +void system_bor_init(void) +{ + HBN_BOR_CFG_Type borCfg = {1/* pu_bor */, 0/* irq_bor_en */, 1/* bor_vth */, 1/* bor_sel */}; + HBN_Set_BOR_Cfg(&borCfg); +} + +void SystemInit (void) +{ + uint32_t *p; + uint32_t i=0; + uint32_t tmpVal=0; + +#ifdef BOOTROM + extern void GLB_Power_On_LDO18_IO(void); + extern void WDT_Disable(void); + extern void HBN_Clear_RTC_INT(void); + + BMX_Cfg_Type bmxCfg={ + .timeoutEn=0, + .errEn=DISABLE, + .arbMod=BMX_ARB_FIX + }; + L1C_BMX_Cfg_Type l1cBmxCfg={ + .timeoutEn=0, + .errEn=DISABLE, + .arbMod=L1C_BMX_ARB_FIX, + }; + + /* NP boot log Flag */ + p= (uint32_t *)(BFLB_BOOTROM_NP_BOOT_LOG_ADDR); + *p=0x5A5AA5A5; + /*diable BMX error incase Sbooten=0xf,while user send vector(core) reset and CPU read deadbeef, + if not disable this bit, CPU will also get hardfault at the same time*/ + //GLB->bmx_cfg1.BF.bmx_err_en=0; + //GLB->bmx_cfg1.BF.bmx_timeout_en=0; + //GLB->bmx_cfg2.BF.bmx_err_addr_dis=1; + GLB_BMX_Init(&bmxCfg); + GLB_BMX_Addr_Monitor_Disable(); + //L1C->l1c_config.BF.l1c_bmx_err_en=0; + //L1C->l1c_config.BF.l1c_bmx_timeout_en=0; + //L1C->l1c_bmx_err_addr_en.BF.l1c_bmx_err_addr_dis=1; + L1C_BMX_Init(&l1cBmxCfg); + L1C_BMX_Addr_Monitor_Disable(); + //L1C->l1c_config.BF.l1c_way_dis=0xf; + L1C_Set_Way_Disable(0x0f); + /* Disable Watchdog */ + WDT_Disable(); + /* Clear RTC */ + HBN_Clear_RTC_INT(); + /* Make OCRAM Idle from retention or sleep */ + GLB_Set_OCRAM_Idle(); + /* Disable embedded flash power up*/ + HBN_Set_Embedded_Flash_Pullup(DISABLE); +#endif + + /* disable hardware_pullup_pull_down (reg_en_hw_pu_pd = 0) */ + tmpVal=BL_RD_REG(HBN_BASE,HBN_IRQ_MODE); + tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_REG_EN_HW_PU_PD); + BL_WR_REG(HBN_BASE,HBN_IRQ_MODE,tmpVal); + + /* GLB_Set_EM_Sel(GLB_EM_0KB); */ + tmpVal=BL_RD_REG(GLB_BASE,GLB_SEAM_MISC); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_EM_SEL,GLB_EM_0KB); + BL_WR_REG(GLB_BASE,GLB_SEAM_MISC,tmpVal); + + /* Fix 26M xtal clkpll_sdmin */ + tmpVal=BL_RD_REG(PDS_BASE,PDS_CLKPLL_SDM); + if(0x49D39D==BL_GET_REG_BITS_VAL(tmpVal,PDS_CLKPLL_SDMIN)){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,PDS_CLKPLL_SDMIN,0x49D89E); + BL_WR_REG(PDS_BASE,PDS_CLKPLL_SDM,tmpVal); + } + + /* Restore default setting*/ + /* GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); */ + tmpVal=BL_RD_REG(GLB_BASE,GLB_PARM); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_UART_SWAP_SET,UART_SIG_SWAP_NONE); + BL_WR_REG(GLB_BASE,GLB_PARM,tmpVal); + /* GLB_JTAG_Sig_Swap_Set(JTAG_SIG_SWAP_NONE); */ + tmpVal=BL_RD_REG(GLB_BASE,GLB_PARM); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_JTAG_SWAP_SET,JTAG_SIG_SWAP_NONE); + BL_WR_REG(GLB_BASE,GLB_PARM,tmpVal); + + /* CLear all interrupt */ + p=(uint32_t *)(CLIC_HART0_ADDR+CLIC_INTIE); + for(i=0;i<(IRQn_LAST+3)/4;i++){ + p[i]=0; + } + p=(uint32_t *)(CLIC_HART0_ADDR+CLIC_INTIP); + for(i=0;i<(IRQn_LAST+3)/4;i++){ + p[i]=0; + } + + /* global IRQ enable */ + __enable_irq(); + + /* init bor for all platform */ + system_bor_init(); + +#ifdef BOOTROM + /*Power up soc 11 power domain,TODO: This should be optional */ + //AON_Power_On_SOC_11(); + /* Record LDO18 pu flag before power up. This maybe not neccessary but copy from 606*/ + //BL_WR_WORD(BFLB_BOOTROM_AP_BOOT_LOG_ADDR,GLB->ldo18io.BF.pu_ldo18io); + /* Power up flash power*/ + //GLB_Power_On_LDO18_IO(); +#endif + +} +void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ +} diff --git a/drivers/bl602_driver/startup/system_bl602.h b/drivers/bl602_driver/startup/system_bl602.h new file mode 100644 index 00000000..20b2eade --- /dev/null +++ b/drivers/bl602_driver/startup/system_bl602.h @@ -0,0 +1,16 @@ +#ifndef __SYSTEM_BL602_H__ +#define __SYSTEM_BL602_H__ + +/** + * @brief PLL Clock type definition + */ + +extern uint32_t SystemCoreClock; + +extern void SystemCoreClockUpdate (void); +extern void SystemInit (void); +extern void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +extern void Systick_Stop(void); +extern void Systick_Start(void); + +#endif diff --git a/drivers/bl602_driver/std_drv/inc/bl602_acomp.h b/drivers/bl602_driver/std_drv/inc/bl602_acomp.h new file mode 100644 index 00000000..1bcbe62c --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_acomp.h @@ -0,0 +1,212 @@ +/** + ****************************************************************************** + * @file bl602_acomp.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_ACOMP_H__ +#define __BL602_ACOMP_H__ + +#include "aon_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup ACOMP + * @{ + */ + +/** @defgroup ACOMP_Public_Types + * @{ + */ + +/** + * @brief Analog compare id type definition + */ +typedef enum { + AON_ACOMP0_ID, /*!< Analog compare 0 */ + AON_ACOMP1_ID, /*!< Analog compare 1 */ +}AON_ACOMP_ID_Type; + +/** + * @brief Analog compare level type definition + */ +typedef enum { + AON_ACOMP_LEVEL_FACTOR_0P25, /*!< Analog compare level scaling factor 0.25 */ + AON_ACOMP_LEVEL_FACTOR_0P5, /*!< Analog compare level scaling factor 0.5 */ + AON_ACOMP_LEVEL_FACTOR_0P75, /*!< Analog compare level scaling factor 0.75 */ + AON_ACOMP_LEVEL_FACTOR_1, /*!< Analog compare level scaling factor 1 */ +}AON_ACOMP_Level_Factor_Type; + +/** + * @brief Analog compare channel type definition + */ +typedef enum { + AON_ACOMP_CHAN_ADC0, /*!< Analog compare channel,ADC input channel 0 */ + AON_ACOMP_CHAN_ADC1, /*!< Analog compare channel,ADC input channel 1 */ + AON_ACOMP_CHAN_ADC2, /*!< Analog compare channel,ADC input channel 2 */ + AON_ACOMP_CHAN_ADC3, /*!< Analog compare channel,ADC input channel 3 */ + AON_ACOMP_CHAN_ADC4, /*!< Analog compare channel,ADC input channel 4 */ + AON_ACOMP_CHAN_ADC5, /*!< Analog compare channel,ADC input channel 5 */ + AON_ACOMP_CHAN_ADC6, /*!< Analog compare channel,ADC input channel 6 */ + AON_ACOMP_CHAN_ADC7, /*!< Analog compare channel,ADC input channel 7 */ + AON_ACOMP_CHAN_DACA, /*!< Analog compare channel,DAC output channel A */ + AON_ACOMP_CHAN_DACB, /*!< Analog compare channel,DAC output channel B */ + AON_ACOMP_CHAN_VREF_1P2V, /*!< Analog compare channel,1.2V ref voltage */ + AON_ACOMP_CHAN_0P375VBAT_NOT_IMP, /*!< Analog compare channel,6/16Vbat */ + AON_ACOMP_CHAN_0P25VBAT, /*!< Analog compare channel,4/16Vbat */ + AON_ACOMP_CHAN_0P1875VBAT, /*!< Analog compare channel,3/16Vbat */ + AON_ACOMP_CHAN_0P3125VBAT, /*!< Analog compare channel,5/16Vbat */ + AON_ACOMP_CHAN_VSS, /*!< Analog compare channel,vss */ +}AON_ACOMP_Chan_Type; + +/** + * @brief Analog compare bias current control type definition + */ +typedef enum { + AON_ACOMP_BIAS_POWER_MODE1, /*!< Analog compare power mode 1,slow response mode */ + AON_ACOMP_BIAS_POWER_MODE2, /*!< Analog compare power mode 2,medium response mode */ + AON_ACOMP_BIAS_POWER_MODE3, /*!< Analog compare power mode 3,fast response mode */ + AON_ACOMP_BIAS_POWER_NONE, /*!< Analog compare power mode none */ +}AON_ACOMP_Bias_Prog_Type; + +/** + * @brief Analog compare hysteresis voltage type definition + */ +typedef enum { + AON_ACOMP_HYSTERESIS_VOLT_NONE, /*!< Analog compare hysteresis voltage none */ + AON_ACOMP_HYSTERESIS_VOLT_10MV, /*!< Analog compare hysteresis voltage 10mv */ + AON_ACOMP_HYSTERESIS_VOLT_20MV, /*!< Analog compare hysteresis voltage 20mv */ + AON_ACOMP_HYSTERESIS_VOLT_30MV, /*!< Analog compare hysteresis voltage 30mv */ + AON_ACOMP_HYSTERESIS_VOLT_40MV, /*!< Analog compare hysteresis voltage 40mv */ + AON_ACOMP_HYSTERESIS_VOLT_50MV, /*!< Analog compare hysteresis voltage 50mv */ + AON_ACOMP_HYSTERESIS_VOLT_60MV, /*!< Analog compare hysteresis voltage 60mv */ + AON_ACOMP_HYSTERESIS_VOLT_70MV, /*!< Analog compare hysteresis voltage 70mv */ +}AON_ACOMP_Hysteresis_Volt_Type; + +/** + * @brief AON ACOMP configuration type definition + */ +typedef struct { + BL_Fun_Type muxEn; /*!< ACOMP mux enable */ + uint8_t posChanSel; /*!< ACOMP positive channel select */ + uint8_t negChanSel; /*!< ACOMP negtive channel select */ + AON_ACOMP_Level_Factor_Type levelFactor; /*!< ACOMP level select factor */ + AON_ACOMP_Bias_Prog_Type biasProg; /*!< ACOMP bias current control */ + AON_ACOMP_Hysteresis_Volt_Type hysteresisPosVolt; /*!< ACOMP hysteresis voltage for positive */ + AON_ACOMP_Hysteresis_Volt_Type hysteresisNegVolt; /*!< ACOMP hysteresis voltage for negtive */ +}AON_ACOMP_CFG_Type; + +/*@} end of group ACOMP_Public_Types */ + +/** @defgroup ACOMP_Public_Constants + * @{ + */ + +/** @defgroup AON_ACOMP_ID_TYPE + * @{ + */ +#define IS_AON_ACOMP_ID_TYPE(type) (((type) == AON_ACOMP0_ID) || \ + ((type) == AON_ACOMP1_ID)) + +/** @defgroup AON_ACOMP_LEVEL_FACTOR_TYPE + * @{ + */ +#define IS_AON_ACOMP_LEVEL_FACTOR_TYPE(type) (((type) == AON_ACOMP_LEVEL_FACTOR_0P25) || \ + ((type) == AON_ACOMP_LEVEL_FACTOR_0P5) || \ + ((type) == AON_ACOMP_LEVEL_FACTOR_0P75) || \ + ((type) == AON_ACOMP_LEVEL_FACTOR_1)) + +/** @defgroup AON_ACOMP_CHAN_TYPE + * @{ + */ +#define IS_AON_ACOMP_CHAN_TYPE(type) (((type) == AON_ACOMP_CHAN_ADC0) || \ + ((type) == AON_ACOMP_CHAN_ADC1) || \ + ((type) == AON_ACOMP_CHAN_ADC2) || \ + ((type) == AON_ACOMP_CHAN_ADC3) || \ + ((type) == AON_ACOMP_CHAN_ADC4) || \ + ((type) == AON_ACOMP_CHAN_ADC5) || \ + ((type) == AON_ACOMP_CHAN_ADC6) || \ + ((type) == AON_ACOMP_CHAN_ADC7) || \ + ((type) == AON_ACOMP_CHAN_DACA) || \ + ((type) == AON_ACOMP_CHAN_DACB) || \ + ((type) == AON_ACOMP_CHAN_VREF_1P2V) || \ + ((type) == AON_ACOMP_CHAN_0P375VBAT_NOT_IMP) || \ + ((type) == AON_ACOMP_CHAN_0P25VBAT) || \ + ((type) == AON_ACOMP_CHAN_0P1875VBAT) || \ + ((type) == AON_ACOMP_CHAN_0P3125VBAT) || \ + ((type) == AON_ACOMP_CHAN_VSS)) + +/** @defgroup AON_ACOMP_BIAS_PROG_TYPE + * @{ + */ +#define IS_AON_ACOMP_BIAS_PROG_TYPE(type) (((type) == AON_ACOMP_BIAS_POWER_MODE1) || \ + ((type) == AON_ACOMP_BIAS_POWER_MODE2) || \ + ((type) == AON_ACOMP_BIAS_POWER_MODE3) || \ + ((type) == AON_ACOMP_BIAS_POWER_NONE)) + +/** @defgroup AON_ACOMP_HYSTERESIS_VOLT_TYPE + * @{ + */ +#define IS_AON_ACOMP_HYSTERESIS_VOLT_TYPE(type) (((type) == AON_ACOMP_HYSTERESIS_VOLT_NONE) || \ + ((type) == AON_ACOMP_HYSTERESIS_VOLT_10MV) || \ + ((type) == AON_ACOMP_HYSTERESIS_VOLT_20MV) || \ + ((type) == AON_ACOMP_HYSTERESIS_VOLT_30MV) || \ + ((type) == AON_ACOMP_HYSTERESIS_VOLT_40MV) || \ + ((type) == AON_ACOMP_HYSTERESIS_VOLT_50MV) || \ + ((type) == AON_ACOMP_HYSTERESIS_VOLT_60MV) || \ + ((type) == AON_ACOMP_HYSTERESIS_VOLT_70MV)) + +/*@} end of group ACOMP_Public_Constants */ + +/** @defgroup ACOMP_Public_Macros + * @{ + */ + +/*@} end of group ACOMP_Public_Macros */ + +/** @defgroup ACOMP_Public_Functions + * @{ + */ +void AON_ACOMP_Init(AON_ACOMP_ID_Type acompNo,AON_ACOMP_CFG_Type *cfg); +void AON_ACOMP_Enable(AON_ACOMP_ID_Type acompNo); +BL_Sts_Type AON_ACOMP_Get_Result(AON_ACOMP_ID_Type acompNo); + +/*@} end of group ACOMP_Public_Functions */ + +/*@} end of group ACOMP */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_ACOMP_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_adc.h b/drivers/bl602_driver/std_drv/inc/bl602_adc.h new file mode 100644 index 00000000..a7038650 --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_adc.h @@ -0,0 +1,541 @@ +/** + ****************************************************************************** + * @file bl602_adc.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_ADC_H__ +#define __BL602_ADC_H__ + +#include "aon_reg.h" +#include "gpip_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/** @defgroup ADC_Public_Types + * @{ + */ + +/** + * @brief ADC channel type definition + */ +typedef enum { + ADC_CHAN0, /*!< GPIO 0, ADC channel 0 */ + ADC_CHAN1, /*!< GPIO 1, ADC channel 1 */ + ADC_CHAN2, /*!< GPIO 2, ADC channel 2 */ + ADC_CHAN3, /*!< GPIO 3, ADC channel 3 */ + ADC_CHAN4, /*!< GPIO 4, ADC channel 4 */ + ADC_CHAN5, /*!< GPIO 5, ADC channel 5 */ + ADC_CHAN6, /*!< GPIO 6, ADC channel 6 */ + ADC_CHAN7, /*!< GPIO 7, ADC channel 7 */ + ADC_CHAN8, /*!< GPIO 8, ADC channel 8 */ + ADC_CHAN9, /*!< GPIO 9, ADC channel 9 */ + ADC_CHAN10, /*!< GPIO 10, ADC channel 10 */ + ADC_CHAN11, /*!< GPIO 11, ADC channel 11 */ + ADC_CHAN_DAC_OUTA, /*!< DACA, ADC channel 12 */ + ADC_CHAN_DAC_OUTB, /*!< DACB, ADC channel 13 */ + ADC_CHAN_TSEN_P, /*!< TSenp, ADC channel 14 */ + ADC_CHAN_TSEN_N, /*!< TSenn, ADC channel 15 */ + ADC_CHAN_VREF, /*!< Vref, ADC channel 16 */ + ADC_CHAN_DCTEST, /*!< DCTest, ADC channel 17 */ + ADC_CHAN_VABT_HALF, /*!< VBAT/2, ADC channel 18 */ + ADC_CHAN_SENP3, /*!< SenVP3, ADC channel 19 */ + ADC_CHAN_SENP2, /*!< SenVP2, ADC channel 20 */ + ADC_CHAN_SENP1, /*!< SenVP1, ADC channel 21 */ + ADC_CHAN_SENP0, /*!< SenVP0, ADC channel 22 */ + ADC_CHAN_GND, /*!< GND, ADC channel 23 */ +}ADC_Chan_Type; + +/** + * @brief ADC V18 selection type definition + */ +typedef enum { + ADC_V18_SEL_1P62V, /*!< V18 select 1.62V */ + ADC_V18_SEL_1P72V, /*!< V18 select 1.72V */ + ADC_V18_SEL_1P82V, /*!< V18 select 1.82V */ + ADC_V18_SEL_1P92V, /*!< V18 select 1.92V */ +}ADC_V18_SEL_Type; + +/** + * @brief ADC V11 selection type definition + */ +typedef enum { + ADC_V11_SEL_1P0V, /*!< V11 select 1.0V */ + ADC_V11_SEL_1P1V, /*!< V11 select 1.1V */ + ADC_V11_SEL_1P18V, /*!< V11 select 1.18V */ + ADC_V11_SEL_1P26V, /*!< V11 select 1.26V */ +}ADC_V11_SEL_Type; + +/** + * @brief ADC clock type definition + */ +typedef enum { + ADC_CLK_DIV_1, /*!< ADC clock:on 32M clock is 32M */ + ADC_CLK_DIV_4, /*!< ADC clock:on 32M clock is 8M */ + ADC_CLK_DIV_8, /*!< ADC clock:on 32M clock is 4M */ + ADC_CLK_DIV_12, /*!< ADC clock:on 32M clock is 2.666M */ + ADC_CLK_DIV_16, /*!< ADC clock:on 32M clock is 2M */ + ADC_CLK_DIV_20, /*!< ADC clock:on 32M clock is 1.6M */ + ADC_CLK_DIV_24, /*!< ADC clock:on 32M clock is 1.333M */ + ADC_CLK_DIV_32, /*!< ADC clock:on 32M clock is 1M */ +}ADC_CLK_Type; + +/** + * @brief ADC conversion speed type definition + */ +typedef enum { + ADC_DELAY_SEL_0, /*!< Select delay 0 */ + ADC_DELAY_SEL_1, /*!< Select delay 1 */ + ADC_DELAY_SEL_2, /*!< Select delay 2 */ + ADC_DELAY_SEL_3, /*!< Select delay 3 */ + ADC_DELAY_SEL_4, /*!< Select delay 4, not recommend */ + ADC_DELAY_SEL_5, /*!< Select delay 5, not recommend */ + ADC_DELAY_SEL_6, /*!< Select delay 6, not recommend */ + ADC_DELAY_SEL_7, /*!< Select delay 7, not recommend */ +}ADC_DELAY_SEL_Type; + +/** + * @brief ADC PGA gain type definition + */ +typedef enum { + ADC_PGA_GAIN_NONE, /*!< No PGA gain */ + ADC_PGA_GAIN_1, /*!< PGA gain 1 */ + ADC_PGA_GAIN_2, /*!< PGA gain 2 */ + ADC_PGA_GAIN_4, /*!< PGA gain 4 */ + ADC_PGA_GAIN_8, /*!< PGA gain 8 */ + ADC_PGA_GAIN_16, /*!< PGA gain 16 */ + ADC_PGA_GAIN_32, /*!< PGA gain 32 */ +}ADC_PGA_GAIN_Type; + +/** + * @brief ADC analog portion low power mode selection type definition + */ +typedef enum { + ADC_BIAS_SEL_MAIN_BANDGAP, /*!< ADC current from main bandgap */ + ADC_BIAS_SEL_AON_BANDGAP, /*!< ADC current from aon bandgap for HBN mode */ +}ADC_BIAS_SEL_Type; + +/** + * @brief ADC chop mode type definition + */ +typedef enum { + ADC_CHOP_MOD_ALL_OFF, /*!< all off */ + ADC_CHOP_MOD_AZ_ON, /*!< Vref AZ on */ + ADC_CHOP_MOD_AZ_PGA_ON, /*!< Vref AZ and PGA chop on */ + ADC_CHOP_MOD_AZ_PGA_RPC_ON, /*!< Vref AZ and PGA chop+RPC on */ +}ADC_CHOP_MOD_Type; + +/** + * @brief ADC audio PGA output common mode control type definition + */ +typedef enum { + ADC_PGA_VCM_1V, /*!< ADC VCM=1V */ + ADC_PGA_VCM_1P2V, /*!< ADC VCM=1.2V */ + ADC_PGA_VCM_1P4V, /*!< ADC VCM=1.4V */ + ADC_PGA_VCM_1P6V, /*!< ADC VCM=1.6V */ +}ADC_PGA_VCM_Type; + +/** + * @brief ADC tsen diode mode type definition + */ +typedef enum { + ADC_TSEN_MOD_INTERNAL_DIODE, /*!< Internal diode mode */ + ADC_TSEN_MOD_EXTERNAL_DIODE, /*!< External diode mode */ +}ADC_TSEN_MOD_Type; + +/** + * @brief ADC voltage reference type definition + */ +typedef enum { + ADC_VREF_3P2V, /*!< ADC select 3.2V as reference voltage */ + ADC_VREF_2V, /*!< ADC select 2V as reference voltage */ +}ADC_VREF_Type; + +/** + * @brief ADC signal input type definition + */ +typedef enum { + ADC_INPUT_SINGLE_END, /*!< ADC signal is single end */ + ADC_INPUT_DIFF, /*!< ADC signal is differential */ +}ADC_SIG_INPUT_Type; + +/** + * @brief ADC data width type definition + */ +typedef enum { + ADC_DATA_WIDTH_12, /*!< ADC 12 bits */ + ADC_DATA_WIDTH_14_WITH_16_AVERAGE, /*!< ADC 14 bits,and the value is average of 16 converts */ + ADC_DATA_WIDTH_16_WITH_64_AVERAGE, /*!< ADC 16 bits,and the value is average of 64 converts */ + ADC_DATA_WIDTH_16_WITH_128_AVERAGE, /*!< ADC 16 bits,and the value is average of 128 converts */ + ADC_DATA_WIDTH_16_WITH_256_AVERAGE, /*!< ADC 16 bits,and the value is average of 256 converts */ +}ADC_Data_Width_Type; + +/** + * @brief ADC micboost 32db type definition + */ +typedef enum { + ADC_MICBOOST_DB_16DB, /*!< MIC boost 16db */ + ADC_MICBOOST_DB_32DB, /*!< MIC boost 32db */ +}ADC_MICBOOST_DB_Type; + +/** + * @brief ADC pga2 gain type definition + */ +typedef enum { + ADC_PGA2_GAIN_0DB, /*!< MIC pga2 gain 0db */ + ADC_PGA2_GAIN_6DB, /*!< MIC pga2 gain 6db */ + ADC_PGA2_GAIN_N6DB, /*!< MIC pga2 gain -6db */ + ADC_PGA2_GAIN_12DB, /*!< MIC pga2 gain 12db */ +}ADC_PGA2_GAIN_Type; + +/** + * @brief ADC mic mode type definition + */ +typedef enum { + ADC_MIC_MODE_SINGLE, /*!< MIC single mode */ + ADC_MIC_MODE_DIFF, /*!< MIC diff mode */ +}ADC_MIC_MODE_Type; + +/** + * @brief ADC mic type definition + */ +typedef struct { + ADC_MICBOOST_DB_Type micboostDb; /*!< MIC boost db */ + ADC_PGA2_GAIN_Type micPga2Gain; /*!< MIC pga2 gain */ + ADC_MIC_MODE_Type mic1Mode; /*!< MIC1 single or diff */ + ADC_MIC_MODE_Type mic2Mode; /*!< MIC2 single or diff */ + BL_Fun_Type dwaEn; /*!< Improve dynamic performance */ + BL_Fun_Type micboostBypassEn; /*!< MIC boost amp bypass enable or disable */ + BL_Fun_Type micPgaEn; /*!< MIC pga enable or disable */ + BL_Fun_Type micBiasEn; /*!< MIC bias enable or disable */ +}ADC_MIC_Type; + +/** + * @brief ADC configuration type definition + */ +typedef struct { + ADC_V18_SEL_Type v18Sel; /*!< ADC 1.8V select */ + ADC_V11_SEL_Type v11Sel; /*!< ADC 1.1V select */ + ADC_CLK_Type clkDiv; /*!< Clock divider */ + ADC_PGA_GAIN_Type gain1; /*!< PGA gain 1 */ + ADC_PGA_GAIN_Type gain2; /*!< PGA gain 2 */ + ADC_CHOP_MOD_Type chopMode; /*!< ADC chop mode select */ + ADC_BIAS_SEL_Type biasSel; /*!< ADC current form main bandgap or aon bandgap */ + ADC_PGA_VCM_Type vcm; /*!< ADC VCM value */ + ADC_VREF_Type vref; /*!< ADC voltage reference */ + ADC_SIG_INPUT_Type inputMode; /*!< ADC input signal type */ + ADC_Data_Width_Type resWidth; /*!< ADC resolution and oversample rate */ + BL_Fun_Type offsetCalibEn; /*!< Offset calibration enable */ + int16_t offsetCalibVal; /*!< Offset calibration value */ +}ADC_CFG_Type; + +/** + * @brief ADC configuration type definition + */ +typedef struct { + int8_t posChan; /*!< Positive channel */ + int8_t negChan; /*!< Negative channel */ + uint16_t value; /*!< ADC value */ + float volt; /*!< ADC voltage result */ +}ADC_Result_Type; + +/** + * @brief ADC FIFO threshold type definition + */ +typedef enum { + ADC_FIFO_THRESHOLD_1, /*!< ADC FIFO threshold is 1 */ + ADC_FIFO_THRESHOLD_4, /*!< ADC FIFO threshold is 4 */ + ADC_FIFO_THRESHOLD_8, /*!< ADC FIFO threshold is 8 */ + ADC_FIFO_THRESHOLD_16, /*!< ADC FIFO threshold is 16 */ +}ADC_FIFO_Threshold_Type; + +/** + * @brief ADC interrupt type definition + */ +typedef enum { + ADC_INT_POS_SATURATION, /*!< ADC positive channel saturation */ + ADC_INT_NEG_SATURATION, /*!< ADC negative channel saturation */ + ADC_INT_FIFO_UNDERRUN, /*!< ADC FIFO underrun interrupt */ + ADC_INT_FIFO_OVERRUN, /*!< ADC FIFO overrun interrupt */ + ADC_INT_ADC_READY, /*!< ADC data ready interrupt */ + ADC_INT_ALL, /*!< ADC all the interrupt */ +}ADC_INT_Type; + +/** + * @brief ADC FIFO configuration structure type definition + */ +typedef struct { + ADC_FIFO_Threshold_Type fifoThreshold; /*!< ADC FIFO threshold */ + BL_Fun_Type dmaEn; /*!< ADC DMA enable */ +}ADC_FIFO_Cfg_Type; + +/** + * @brief ADC REG GAIN CAL + */ +typedef struct { + BL_Fun_Type adcGainCoeffEnable; /*!< ADC_Gain_Coeff enable */ + uint16_t adcgainCoeffVal; /*!< ADC_Gain_Coeff value */ + float coe; /*!< ADC_Gain_Coeff result */ +}ADC_Gain_Coeff_Type; + +/*@} end of group ADC_Public_Types */ + +/** @defgroup ADC_Public_Constants + * @{ + */ + +/** @defgroup ADC_CHAN_TYPE + * @{ + */ +#define IS_ADC_CHAN_TYPE(type) (((type) == ADC_CHAN0) || \ + ((type) == ADC_CHAN1) || \ + ((type) == ADC_CHAN2) || \ + ((type) == ADC_CHAN3) || \ + ((type) == ADC_CHAN4) || \ + ((type) == ADC_CHAN5) || \ + ((type) == ADC_CHAN6) || \ + ((type) == ADC_CHAN7) || \ + ((type) == ADC_CHAN8) || \ + ((type) == ADC_CHAN9) || \ + ((type) == ADC_CHAN10) || \ + ((type) == ADC_CHAN11) || \ + ((type) == ADC_CHAN_DAC_OUTA) || \ + ((type) == ADC_CHAN_DAC_OUTB) || \ + ((type) == ADC_CHAN_TSEN_P) || \ + ((type) == ADC_CHAN_TSEN_N) || \ + ((type) == ADC_CHAN_VREF) || \ + ((type) == ADC_CHAN_DCTEST) || \ + ((type) == ADC_CHAN_VABT_HALF) || \ + ((type) == ADC_CHAN_SENP3) || \ + ((type) == ADC_CHAN_SENP2) || \ + ((type) == ADC_CHAN_SENP1) || \ + ((type) == ADC_CHAN_SENP0) || \ + ((type) == ADC_CHAN_GND)) + +/** @defgroup ADC_V18_SEL_TYPE + * @{ + */ +#define IS_ADC_V18_SEL_TYPE(type) (((type) == ADC_V18_SEL_1P62V) || \ + ((type) == ADC_V18_SEL_1P72V) || \ + ((type) == ADC_V18_SEL_1P82V) || \ + ((type) == ADC_V18_SEL_1P92V)) + +/** @defgroup ADC_V11_SEL_TYPE + * @{ + */ +#define IS_ADC_V11_SEL_TYPE(type) (((type) == ADC_V11_SEL_1P0V) || \ + ((type) == ADC_V11_SEL_1P1V) || \ + ((type) == ADC_V11_SEL_1P18V) || \ + ((type) == ADC_V11_SEL_1P26V)) + +/** @defgroup ADC_CLK_TYPE + * @{ + */ +#define IS_ADC_CLK_TYPE(type) (((type) == ADC_CLK_DIV_1) || \ + ((type) == ADC_CLK_DIV_4) || \ + ((type) == ADC_CLK_DIV_8) || \ + ((type) == ADC_CLK_DIV_12) || \ + ((type) == ADC_CLK_DIV_16) || \ + ((type) == ADC_CLK_DIV_20) || \ + ((type) == ADC_CLK_DIV_24) || \ + ((type) == ADC_CLK_DIV_32)) + +/** @defgroup ADC_DELAY_SEL_TYPE + * @{ + */ +#define IS_ADC_DELAY_SEL_TYPE(type) (((type) == ADC_DELAY_SEL_0) || \ + ((type) == ADC_DELAY_SEL_1) || \ + ((type) == ADC_DELAY_SEL_2) || \ + ((type) == ADC_DELAY_SEL_3) || \ + ((type) == ADC_DELAY_SEL_4) || \ + ((type) == ADC_DELAY_SEL_5) || \ + ((type) == ADC_DELAY_SEL_6) || \ + ((type) == ADC_DELAY_SEL_7)) + +/** @defgroup ADC_PGA_GAIN_TYPE + * @{ + */ +#define IS_ADC_PGA_GAIN_TYPE(type) (((type) == ADC_PGA_GAIN_NONE) || \ + ((type) == ADC_PGA_GAIN_1) || \ + ((type) == ADC_PGA_GAIN_2) || \ + ((type) == ADC_PGA_GAIN_4) || \ + ((type) == ADC_PGA_GAIN_8) || \ + ((type) == ADC_PGA_GAIN_16) || \ + ((type) == ADC_PGA_GAIN_32)) + +/** @defgroup ADC_BIAS_SEL_TYPE + * @{ + */ +#define IS_ADC_BIAS_SEL_TYPE(type) (((type) == ADC_BIAS_SEL_MAIN_BANDGAP) || \ + ((type) == ADC_BIAS_SEL_AON_BANDGAP)) + +/** @defgroup ADC_CHOP_MOD_TYPE + * @{ + */ +#define IS_ADC_CHOP_MOD_TYPE(type) (((type) == ADC_CHOP_MOD_ALL_OFF) || \ + ((type) == ADC_CHOP_MOD_AZ_ON) || \ + ((type) == ADC_CHOP_MOD_AZ_PGA_ON) || \ + ((type) == ADC_CHOP_MOD_AZ_PGA_RPC_ON)) + +/** @defgroup ADC_PGA_VCM_TYPE + * @{ + */ +#define IS_ADC_PGA_VCM_TYPE(type) (((type) == ADC_PGA_VCM_1V) || \ + ((type) == ADC_PGA_VCM_1P2V) || \ + ((type) == ADC_PGA_VCM_1P4V) || \ + ((type) == ADC_PGA_VCM_1P6V)) + +/** @defgroup ADC_TSEN_MOD_TYPE + * @{ + */ +#define IS_ADC_TSEN_MOD_TYPE(type) (((type) == ADC_TSEN_MOD_INTERNAL_DIODE) || \ + ((type) == ADC_TSEN_MOD_EXTERNAL_DIODE)) + +/** @defgroup ADC_VREF_TYPE + * @{ + */ +#define IS_ADC_VREF_TYPE(type) (((type) == ADC_VREF_3P2V) || \ + ((type) == ADC_VREF_2V)) + +/** @defgroup ADC_SIG_INPUT_TYPE + * @{ + */ +#define IS_ADC_SIG_INPUT_TYPE(type) (((type) == ADC_INPUT_SINGLE_END) || \ + ((type) == ADC_INPUT_DIFF)) + +/** @defgroup ADC_DATA_WIDTH_TYPE + * @{ + */ +#define IS_ADC_DATA_WIDTH_TYPE(type) (((type) == ADC_DATA_WIDTH_12) || \ + ((type) == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) || \ + ((type) == ADC_DATA_WIDTH_16_WITH_64_AVERAGE) || \ + ((type) == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) || \ + ((type) == ADC_DATA_WIDTH_16_WITH_256_AVERAGE)) + +/** @defgroup ADC_MICBOOST_DB_TYPE + * @{ + */ +#define IS_ADC_MICBOOST_DB_TYPE(type) (((type) == ADC_MICBOOST_DB_16DB) || \ + ((type) == ADC_MICBOOST_DB_32DB)) + +/** @defgroup ADC_PGA2_GAIN_TYPE + * @{ + */ +#define IS_ADC_PGA2_GAIN_TYPE(type) (((type) == ADC_PGA2_GAIN_0DB) || \ + ((type) == ADC_PGA2_GAIN_6DB) || \ + ((type) == ADC_PGA2_GAIN_N6DB) || \ + ((type) == ADC_PGA2_GAIN_12DB)) + +/** @defgroup ADC_MIC_MODE_TYPE + * @{ + */ +#define IS_ADC_MIC_MODE_TYPE(type) (((type) == ADC_MIC_MODE_SINGLE) || \ + ((type) == ADC_MIC_MODE_DIFF)) + +/** @defgroup ADC_FIFO_THRESHOLD_TYPE + * @{ + */ +#define IS_ADC_FIFO_THRESHOLD_TYPE(type) (((type) == ADC_FIFO_THRESHOLD_1) || \ + ((type) == ADC_FIFO_THRESHOLD_4) || \ + ((type) == ADC_FIFO_THRESHOLD_8) || \ + ((type) == ADC_FIFO_THRESHOLD_16)) + +/** @defgroup ADC_INT_TYPE + * @{ + */ +#define IS_ADC_INT_TYPE(type) (((type) == ADC_INT_POS_SATURATION) || \ + ((type) == ADC_INT_NEG_SATURATION) || \ + ((type) == ADC_INT_FIFO_UNDERRUN) || \ + ((type) == ADC_INT_FIFO_OVERRUN) || \ + ((type) == ADC_INT_ADC_READY) || \ + ((type) == ADC_INT_ALL)) + +/*@} end of group ADC_Public_Constants */ + +/** @defgroup ADC_Public_Macros + * @{ + */ + +/*@} end of group ADC_Public_Macros */ + +/** @defgroup ADC_Public_Functions + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +void GPADC_DMA_IRQHandler(void); +#endif +void ADC_Vbat_Enable(void); +void ADC_Vbat_Disable(void); +void ADC_Reset(void); +void ADC_Enable(void); +void ADC_Disable(void); +void ADC_Init(ADC_CFG_Type* cfg); +void ADC_Channel_Config(ADC_Chan_Type posCh,ADC_Chan_Type negCh,BL_Fun_Type contEn); +void ADC_Scan_Channel_Config(ADC_Chan_Type posChList[],ADC_Chan_Type negChList[],uint8_t scanLength,BL_Fun_Type contEn); +void ADC_Start(void); +void ADC_Stop(void); +void ADC_FIFO_Cfg(ADC_FIFO_Cfg_Type *fifoCfg); +uint8_t ADC_Get_FIFO_Count(void); +BL_Sts_Type ADC_FIFO_Is_Empty(void); +BL_Sts_Type ADC_FIFO_Is_Full(void); +uint32_t ADC_Read_FIFO(void); +void ADC_Parse_Result(uint32_t *orgVal,uint32_t len,ADC_Result_Type *result); +void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask); +void ADC_IntClr(ADC_INT_Type intType); +BL_Sts_Type ADC_GetIntStatus(ADC_INT_Type intType); +void ADC_Int_Callback_Install(ADC_INT_Type intType,intCallback_Type* cbFun); +void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask); +void ADC_SET_TSVBE_LOW(void); +void ADC_SET_TSVBE_HIGH(void); +void ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod); +BL_Err_Type ADC_Mic_Init(ADC_MIC_Type * adc_mic_config); +void ADC_MIC_Bias_Disable(void); +void ADC_MIC_Bias_Enable(void); +BL_Err_Type ADC_Trim_TSEN(uint16_t * tsen_offset); +BL_Err_Type ADC_Gain_Trim(void); +uint32_t ADC_Cal_Reg_Coeff_Value(uint32_t raw_reg); +float TSEN_Get_Temp(uint32_t tsen_offset); + +/*@} end of group ADC_Public_Functions */ + +/*@} end of group ADC */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_ADC_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_aon.h b/drivers/bl602_driver/std_drv/inc/bl602_aon.h new file mode 100644 index 00000000..34629df2 --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_aon.h @@ -0,0 +1,108 @@ +/** + ****************************************************************************** + * @file bl602_aon.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_AON_H__ +#define __BL602_AON_H__ + +#include "aon_reg.h" +#include "glb_reg.h" +#include "hbn_reg.h" +#include "pds_reg.h" +#include "bl602_ef_ctrl.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup AON + * @{ + */ + +/** @defgroup AON_Public_Types + * @{ + */ + +/*@} end of group AON_Public_Types */ + +/** @defgroup AON_Public_Constants + * @{ + */ + +/*@} end of group AON_Public_Constants */ + +/** @defgroup AON_Public_Macros + * @{ + */ + +/*@} end of group AON_Public_Macros */ + +/** @defgroup AON_Public_Functions + * @{ + */ +/*----------*/ +BL_Err_Type AON_Power_On_MBG(void); +BL_Err_Type AON_Power_Off_MBG(void); +/*----------*/ +BL_Err_Type AON_Power_On_XTAL(void); +BL_Err_Type AON_Set_Xtal_CapCode(uint8_t capIn,uint8_t capOut); +uint8_t AON_Get_Xtal_CapCode(void); +BL_Err_Type AON_Power_Off_XTAL(void); +/*----------*/ +BL_Err_Type AON_Power_On_BG(void); +BL_Err_Type AON_Power_Off_BG(void); +/*----------*/ +BL_Err_Type AON_Power_On_LDO11_SOC(void); +BL_Err_Type AON_Power_Off_LDO11_SOC(void); +/*----------*/ +BL_Err_Type AON_Power_On_LDO15_RF(void); +BL_Err_Type AON_Power_Off_LDO15_RF(void); +/*----------*/ +BL_Err_Type AON_Power_On_SFReg(void); +BL_Err_Type AON_Power_Off_SFReg(void); +/*----------*/ +BL_Err_Type AON_LowPower_Enter_PDS0(void); +BL_Err_Type AON_LowPower_Exit_PDS0(void); +/*----------*/ +BL_Err_Type AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay); +/*----------*/; + +/*@} end of group AON_Public_Functions */ + +/*@} end of group AON */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_AON_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_common.h b/drivers/bl602_driver/std_drv/inc/bl602_common.h new file mode 100644 index 00000000..d2de1761 --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_common.h @@ -0,0 +1,60 @@ +#ifndef __BL602_COMMON_H__ +#define __BL602_COMMON_H__ + +#include "bl602.h" +#include "bflb_platform.h" + +/** @addtogroup BL606_Peripheral_Driver + * @{ + */ + +/** @addtogroup COMMON + * @{ + */ + +/** @defgroup COMMON_Public_Types + * @{ + */ + +/*@} end of group COMMON_Public_Types */ + +/** @defgroup COMMON_Public_Constants + * @{ + */ + +/** @defgroup DRIVER_INT_PERIPH + * @{ + */ +#define IS_INT_PERIPH(INT_PERIPH) ((INT_PERIPH) < IRQn_LAST) + +/*@} end of group DRIVER_INT_PERIPH */ + +/** @defgroup DRIVER_INT_MASK + * @{ + */ +#define IS_BL_MASK_TYPE(type) (((type) == MASK) || ((type) == UNMASK)) + +/*@} end of group COMMON_Public_Constants */ + +/** @defgroup COMMON_Public_Macros + * @{ + */ + +/*@} end of group DRIVER_Public_Macro */ + +/** @defgroup DRIVER_Public_FunctionDeclaration + * @brief DRIVER functions declaration + * @{ + */ + +#define ARCH_Delay_US BL602_Delay_US +#define ARCH_Delay_MS BL602_Delay_MS + +void Interrupt_Handler_Register(IRQn_Type irq,pFunc interruptFun); +void ASM_Delay_Us(uint32_t core,uint32_t cnt); +void BL602_Delay_US(uint32_t cnt); +void BL602_Delay_MS(uint32_t cnt); + +#endif /* __BL602_COMMON_H__ */ + + diff --git a/drivers/bl602_driver/std_drv/inc/bl602_dac.h b/drivers/bl602_driver/std_drv/inc/bl602_dac.h new file mode 100644 index 00000000..a45e80b4 --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_dac.h @@ -0,0 +1,286 @@ +/** + ****************************************************************************** + * @file bl602_dac.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_DAC_H__ +#define __BL602_DAC_H__ + +#include "aon_reg.h" +#include "glb_reg.h" +#include "gpip_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/** @defgroup DAC_Public_Types + * @{ + */ + +/** + * @brief DAC reference voltage definition + */ +typedef enum { + GLB_DAC_REF_SEL_INTERNAL, /*!< DAC reference select internal */ + GLB_DAC_REF_SEL_EXTERNAL, /*!< DAC reference select external */ +}GLB_DAC_Ref_Sel_Type; + +/** + * @brief DAC reference voltage definition + */ +typedef enum { + GLB_DAC_Output_Volt_0P2_1, /*!< DAC output voltage is 0.2-1V */ + GLB_DAC_Output_Volt_0P225_1P425, /*!< DAC output voltage is 0.225-1.425V */ + GLB_DAC_Output_Volt_RESEVED, /*!< DAC output voltage is 0.225-1.425V */ + GLB_DAC_Output_Volt_0P2_1P8, /*!< DAC output voltage is 0.2-1.8V */ +}GLB_DAC_Output_Volt_Range_Type; + +/** + * @brief DAC channel type definition + */ +typedef enum { + GLB_DAC_CHAN0, /*!< DAC channel 0 */ + GLB_DAC_CHAN1, /*!< DAC channel 1 */ + GLB_DAC_CHAN2, /*!< DAC channel 2 */ + GLB_DAC_CHAN3, /*!< DAC channel 3 */ + GLB_DAC_CHAN4, /*!< DAC channel 4 */ + GLB_DAC_CHAN5, /*!< DAC channel 5 */ + GLB_DAC_CHAN6, /*!< DAC channel 6 */ + GLB_DAC_CHAN7, /*!< DAC channel 7 */ + GLB_DAC_CHAN_ALL, /*!< DAC channel all */ +}GLB_DAC_Chan_Type; + +/** + * @brief DAC channel configuration structure type definition + */ +typedef struct { + BL_Fun_Type chanEn; /*!< Enable this channel or not */ + BL_Fun_Type outputEn; /*!< Output this channel result to PAD */ + GLB_DAC_Chan_Type outMux; /*!< DAC output mux,NOT implement yet,DAC use fixed GPIO9 and GPIO10 */ + GLB_DAC_Output_Volt_Range_Type outRange; /*!< DAC output voltage range */ +}GLB_DAC_Chan_Cfg_Type; + +/** + * @brief DAC configuration structure type definition + */ +typedef struct { + GLB_DAC_Ref_Sel_Type refSel; /*!< DAC reference voltage select */ + BL_Fun_Type resetChanA; /*!< Reset DAC channel A */ + BL_Fun_Type resetChanB; /*!< Reset DAC channel B */ +}GLB_DAC_Cfg_Type; + +/** + * @brief DAC channel B source selection type definition + */ +typedef enum { + GPIP_DAC_ChanB_SRC_REG, /*!< select Reg as source of DAC channel B */ + GPIP_DAC_ChanB_SRC_DMA, /*!< select DMA as source of DAC channel B */ + GPIP_DAC_ChanB_SRC_DMA_WITH_FILTER, /*!< select DMA with Filter as source of DAC channel B */ + GPIP_DAC_ChanB_SRC_SIN_GEN, /*!< select Sin Gen as source of DAC channel B */ + GPIP_DAC_ChanB_SRC_A, /*!< select channel A as source of DAC channel B */ + GPIP_DAC_ChanB_SRC_INVERSE_A, /*!< select inverse of channel A as source of DAC channel B */ +}GPIP_DAC_ChanB_SRC_Type; + +/** + * @brief DAC channel A source selection type definition + */ +typedef enum { + GPIP_DAC_ChanA_SRC_REG, /*!< select Reg as source of DAC channel A */ + GPIP_DAC_ChanA_SRC_DMA, /*!< select DMA as source of DAC channel A */ + GPIP_DAC_ChanA_SRC_DMA_WITH_FILTER, /*!< select DMA with Filter as source of DAC channel A */ + GPIP_DAC_ChanA_SRC_SIN_GEN, /*!< select Sin Gen as source of DAC channel A */ +}GPIP_DAC_ChanA_SRC_Type; + +/** + * @brief DAC mode selection type definition + */ +typedef enum { + GPIP_DAC_MOD_32K, /*!< select 32K as DAC mode */ + GPIP_DAC_MOD_16K, /*!< select 16K as DAC mode */ + GPIP_DAC_MOD_RESERVE, /*!< reserved */ + GPIP_DAC_MOD_8K, /*!< select 8K as DAC mode */ + GPIP_DAC_MOD_512K, /*!< select 512 as DAC mode Only For DMA Mode */ +}GPIP_DAC_MOD_Type; + +/** + * @brief DAC DMA TX format selection type definition + */ +typedef enum { + GPIP_DAC_DMA_FORMAT_0, /*!< {A0},{A1},{A2},... */ + GPIP_DAC_DMA_FORMAT_1, /*!< {B0,A0},{B1,A1},{B2,A2},... */ + GPIP_DAC_DMA_FORMAT_2, /*!< {A1,A0},{A3,A2},{A5,A4},... */ +}GPIP_DAC_DMA_TX_FORMAT_Type; + +/** + * @brief AON and GPIP DAC configuration structure type definition + */ +typedef struct { + GLB_DAC_Ref_Sel_Type refSel; /*!< DAC reference voltage select */ + BL_Fun_Type resetChanA; /*!< Reset DAC channel A */ + BL_Fun_Type resetChanB; /*!< Reset DAC channel B */ + GPIP_DAC_MOD_Type mod; /*!< DAC mode selection */ + BL_Fun_Type dmaEn; /*!< DAC DMA transfer enable */ + GPIP_DAC_DMA_TX_FORMAT_Type dmaFmt; /*!< DAC DMA TX format selection */ +}GLB_GPIP_DAC_Cfg_Type; + +/** + * @brief AON and GPIP DAC channel A configuration structure type definition + */ +typedef struct { + BL_Fun_Type chanCovtEn; /*!< Enable this channel conversion or not */ + BL_Fun_Type outputEn; /*!< Output this channel result to PAD */ + BL_Fun_Type chanEn; /*!< Enable this channel or not */ + GPIP_DAC_ChanA_SRC_Type src; /*!< DAC channel A source */ +}GLB_GPIP_DAC_ChanA_Cfg_Type; + +/** + * @brief AON and GPIP DAC channel B configuration structure type definition + */ +typedef struct { + BL_Fun_Type chanCovtEn; /*!< Enable this channel conversion or not */ + BL_Fun_Type outputEn; /*!< Output this channel result to PAD */ + BL_Fun_Type chanEn; /*!< Enable this channel or not */ + GPIP_DAC_ChanB_SRC_Type src; /*!< DAC channel B source */ +}GLB_GPIP_DAC_ChanB_Cfg_Type; + +/*@} end of group DAC_Public_Types */ + +/** @defgroup DAC_Public_Constants + * @{ + */ + +/** @defgroup GLB_DAC_REF_SEL_TYPE + * @{ + */ +#define IS_GLB_DAC_REF_SEL_TYPE(type) (((type) == GLB_DAC_REF_SEL_INTERNAL) || \ + ((type) == GLB_DAC_REF_SEL_EXTERNAL)) + +/** @defgroup GLB_DAC_OUTPUT_VOLT_RANGE_TYPE + * @{ + */ +#define IS_GLB_DAC_OUTPUT_VOLT_RANGE_TYPE(type) (((type) == GLB_DAC_Output_Volt_0P2_1) || \ + ((type) == GLB_DAC_Output_Volt_0P225_1P425) || \ + ((type) == GLB_DAC_Output_Volt_RESEVED) || \ + ((type) == GLB_DAC_Output_Volt_0P2_1P8)) + +/** @defgroup GLB_DAC_CHAN_TYPE + * @{ + */ +#define IS_GLB_DAC_CHAN_TYPE(type) (((type) == GLB_DAC_CHAN0) || \ + ((type) == GLB_DAC_CHAN1) || \ + ((type) == GLB_DAC_CHAN2) || \ + ((type) == GLB_DAC_CHAN3) || \ + ((type) == GLB_DAC_CHAN4) || \ + ((type) == GLB_DAC_CHAN5) || \ + ((type) == GLB_DAC_CHAN6) || \ + ((type) == GLB_DAC_CHAN7) || \ + ((type) == GLB_DAC_CHAN_ALL)) + +/** @defgroup GPIP_DAC_CHANB_SRC_TYPE + * @{ + */ +#define IS_GPIP_DAC_CHANB_SRC_TYPE(type) (((type) == GPIP_DAC_ChanB_SRC_REG) || \ + ((type) == GPIP_DAC_ChanB_SRC_DMA) || \ + ((type) == GPIP_DAC_ChanB_SRC_DMA_WITH_FILTER) || \ + ((type) == GPIP_DAC_ChanB_SRC_SIN_GEN) || \ + ((type) == GPIP_DAC_ChanB_SRC_A) || \ + ((type) == GPIP_DAC_ChanB_SRC_INVERSE_A)) + +/** @defgroup GPIP_DAC_CHANA_SRC_TYPE + * @{ + */ +#define IS_GPIP_DAC_CHANA_SRC_TYPE(type) (((type) == GPIP_DAC_ChanA_SRC_REG) || \ + ((type) == GPIP_DAC_ChanA_SRC_DMA) || \ + ((type) == GPIP_DAC_ChanA_SRC_DMA_WITH_FILTER) || \ + ((type) == GPIP_DAC_ChanA_SRC_SIN_GEN)) + +/** @defgroup GPIP_DAC_MOD_TYPE + * @{ + */ +#define IS_GPIP_DAC_MOD_TYPE(type) (((type) == GPIP_DAC_MOD_32K) || \ + ((type) == GPIP_DAC_MOD_16K) || \ + ((type) == GPIP_DAC_MOD_RESERVE) || \ + ((type) == GPIP_DAC_MOD_8K) || \ + ((type) == GPIP_DAC_MOD_512K)) + +/** @defgroup GPIP_DAC_DMA_TX_FORMAT_TYPE + * @{ + */ +#define IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(type) (((type) == GPIP_DAC_DMA_FORMAT_0) || \ + ((type) == GPIP_DAC_DMA_FORMAT_1) || \ + ((type) == GPIP_DAC_DMA_FORMAT_2)) + +/*@} end of group DAC_Public_Constants */ + +/** @defgroup DAC_Public_Macros + * @{ + */ + +/*@} end of group DAC_Public_Macros */ + +/** @defgroup DAC_Public_Functions + * @{ + */ +void GLB_DAC_Init(GLB_DAC_Cfg_Type *cfg); +void GLB_DAC_Set_ChanA_Config(GLB_DAC_Chan_Cfg_Type *cfg); +void GLB_DAC_Set_ChanB_Config(GLB_DAC_Chan_Cfg_Type *cfg); +void GPIP_Set_DAC_ChanB_SRC_SEL(GPIP_DAC_ChanB_SRC_Type src); +void GPIP_Set_DAC_ChanA_SRC_SEL(GPIP_DAC_ChanA_SRC_Type src); +void GPIP_Set_DAC_Mod_SEL(GPIP_DAC_MOD_Type mod); +void GPIP_DAC_ChanB_Enable(void); +void GPIP_DAC_ChanB_Disable(void); +void GPIP_DAC_ChanA_Enable(void); +void GPIP_DAC_ChanA_Disable(void); +void GPIP_Set_DAC_DMA_TX_FORMAT_SEL(GPIP_DAC_DMA_TX_FORMAT_Type fmt); +void GPIP_Set_DAC_DMA_TX_Enable(void); +void GPIP_Set_DAC_DMA_TX_Disable(void); +void GPIP_DAC_DMA_WriteData(uint32_t data); +BL_Err_Type GLB_GPIP_DAC_Init(GLB_GPIP_DAC_Cfg_Type* cfg); +void GLB_GPIP_DAC_Set_ChanA_Config(GLB_GPIP_DAC_ChanA_Cfg_Type *cfg); +void GLB_GPIP_DAC_Set_ChanB_Config(GLB_GPIP_DAC_ChanB_Cfg_Type *cfg); +void GLB_DAC_Set_ChanA_Value(uint16_t val); +void GLB_DAC_Set_ChanB_Value(uint16_t val); + +/*@} end of group DAC_Public_Functions */ + +/*@} end of group DAC */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_DAC_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_dma.h b/drivers/bl602_driver/std_drv/inc/bl602_dma.h new file mode 100644 index 00000000..a57dca78 --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_dma.h @@ -0,0 +1,342 @@ +/** + ****************************************************************************** + * @file bl602_dma.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_DMA_H__ +#define __BL602_DMA_H__ + +#include "dma_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/** @defgroup DMA_Public_Types + * @{ + */ + +/** + * @brief DMA endian type definition + */ +typedef enum { + DMA_LITTLE_ENDIAN = 0, /*!< DMA use little endian */ + DMA_BIG_ENDIAN, /*!< DMA use big endian */ +}DMA_Endian_Type; + +/** + * @brief DMA synchronization logic type definition + */ +typedef enum { + DMA_SYNC_LOGIC_ENABLE = 0, /*!< DMA synchronization logic enable */ + DMA_SYNC_LOGIC_DISABLE, /*!< DMA synchronization logic disable */ +}DMA_Sync_Logic_Type; + +/** + * @brief DMA transfer width type definition + */ +typedef enum { + DMA_TRNS_WIDTH_8BITS = 0, /*!< DMA transfer width:8 bits */ + DMA_TRNS_WIDTH_16BITS, /*!< DMA transfer width:16 bits */ + DMA_TRNS_WIDTH_32BITS, /*!< DMA transfer width:32 bits */ +}DMA_Trans_Width_Type; + +/** + * @brief DMA transfer direction type definition + */ +typedef enum { + DMA_TRNS_M2M = 0, /*!< DMA transfer tyep:memory to memory */ + DMA_TRNS_M2P, /*!< DMA transfer tyep:memory to peripheral */ + DMA_TRNS_P2M, /*!< DMA transfer tyep:peripheral to memory */ + DMA_TRNS_P2P, /*!< DMA transfer tyep:peripheral to peripheral */ +}DMA_Trans_Dir_Type; + +/** + * @brief DMA burst size type definition + */ +typedef enum { + DMA_BURST_SIZE_1 = 0, /*!< DMA transfer width:8 bits */ + DMA_BURST_SIZE_4, /*!< DMA transfer width:16 bits */ + DMA_BURST_SIZE_8, /*!< DMA transfer width:32 bits */ + DMA_BURST_SIZE_16, /*!< DMA transfer width:64 bits */ +}DMA_Burst_Size_Type; + +/** + * @brief DMA destination peripheral type definition + */ +typedef enum { + DMA_REQ_UART0_RX = 0, /*!< DMA request peripheral:UART0 RX */ + DMA_REQ_UART0_TX, /*!< DMA request peripheral:UART0 TX */ + DMA_REQ_UART1_RX, /*!< DMA request peripheral:UART1 RX */ + DMA_REQ_UART1_TX, /*!< DMA request peripheral:UART1 TX */ + DMA_REQ_I2C_RX = 6, /*!< DMA request peripheral:I2C RX */ + DMA_REQ_I2C_TX, /*!< DMA request peripheral:I2C TX */ + DMA_REQ_SPI_RX = 10, /*!< DMA request peripheral:SPI RX */ + DMA_REQ_SPI_TX, /*!< DMA request peripheral:SPI TX */ + DMA_REQ_GPADC0 = 22, /*!< DMA request peripheral:GPADC0 */ + DMA_REQ_GPADC1, /*!< DMA request peripheral:GPADC1 */ + DMA_REQ_NONE = 0, /*!< DMA request peripheral:None */ +}DMA_Periph_Req_Type; + +/** + * @brief DMA channel type definition + */ +typedef enum { + DMA_CH0 = 0, /*!< DMA channel 0 */ + DMA_CH1, /*!< DMA channel 1 */ + DMA_CH2, /*!< DMA channel 2 */ + DMA_CH3, /*!< DMA channel 3 */ + DMA_CH_MAX, /*!< */ +}DMA_Chan_Type; + +/** + * @brief DMA interrupt type definition + */ +typedef enum { + DMA_INT_TCOMPLETED = 0, /*!< DMA completed interrupt */ + DMA_INT_ERR, /*!< DMA error interrupt */ + DMA_INT_ALL, /*!< All the interrupt */ +}DMA_INT_Type; + +/** + * @brief DMA LLI Structure PING-PONG + */ +typedef enum { + PING_INDEX = 0, /*!< PING INDEX */ + PONG_INDEX, /*!< PONG INDEX */ +}DMA_LLI_PP_Index_Type; + +/** + * @brief DMA Configuration Structure type definition + */ +typedef struct { + DMA_Endian_Type endian; /*!< DMA endian type */ + DMA_Sync_Logic_Type syncLogic; /*!< DMA synchronization logic */ +}DMA_Cfg_Type; + +/** + * @brief DMA channel Configuration Structure type definition + */ +typedef struct { + uint32_t srcDmaAddr; /*!< Source address of DMA transfer */ + uint32_t destDmaAddr; /*!< Destination address of DMA transfer */ + uint32_t transfLength; /*!< Transfer length, 0~4095, this is burst count */ + DMA_Trans_Dir_Type dir; /*!< Transfer dir control. 0: Memory to Memory, 1: Memory to peripheral, 2: Peripheral to memory */ + DMA_Chan_Type ch; /*!< Channel select 0-4 */ + DMA_Trans_Width_Type srcTransfWidth; /*!< Transfer width. 0: 8 bits, 1: 16 bits, 2: 32 bits */ + DMA_Trans_Width_Type dstTransfWidth; /*!< Transfer width. 0: 8 bits, 1: 16 bits, 2: 32 bits */ + DMA_Burst_Size_Type srcBurstSzie; /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width. + 0: 1 item, 1: 4 items, 2: 8 items, 3: 16 items */ + DMA_Burst_Size_Type dstBurstSzie; /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width. + 0: 1 item, 1: 4 items, 2: 8 items, 3: 16 items */ + uint8_t srcAddrInc; /*!< Source address increment. 0: No change, 1: Increment */ + uint8_t destAddrInc; /*!< Destination address increment. 0: No change, 1: Increment */ + DMA_Periph_Req_Type srcPeriph; /*!< Source peripheral select */ + DMA_Periph_Req_Type dstPeriph; /*!< Destination peripheral select */ +}DMA_Channel_Cfg_Type; + +/** + * @brief DMA LLI control structure type definition + */ +typedef struct { + uint32_t srcDmaAddr; /*!< Source address of DMA transfer */ + uint32_t destDmaAddr; /*!< Destination address of DMA transfer */ + uint32_t nextLLI; /*!< Next LLI address */ + struct DMA_Control_Reg dmaCtrl; /*!< DMA transaction control */ +}DMA_LLI_Ctrl_Type; + +/** + * @brief DMA LLI configuration structure type definition + */ +typedef struct { + DMA_Trans_Dir_Type dir; /*!< Transfer dir control. 0: Memory to Memory, 1: Memory to peripheral, 2: Peripheral to memory */ + DMA_Periph_Req_Type srcPeriph; /*!< Source peripheral select */ + DMA_Periph_Req_Type dstPeriph; /*!< Destination peripheral select */ +}DMA_LLI_Cfg_Type; + +/** + * @brief DMA LLI Ping-Pong Buf definition + */ +typedef struct { + uint8_t idleIndex; /*!< Index Idle lliListHeader */ + uint8_t dmaChan; /*!< DMA LLI Channel used */ + DMA_LLI_Ctrl_Type *lliListHeader[2]; /*!< Ping-Pong BUf List Header */ + void (* onTransCompleted)(DMA_LLI_Ctrl_Type *); /*!< Completed Transmit One List Callback Function */ +}DMA_LLI_PP_Buf; + +/** + * @brief DMA LLI Ping-Pong Structure definition + */ +typedef struct { + uint8_t trans_index; /*!< Ping or Pong Trigger TC */ + uint8_t dmaChan; /*!< DMA LLI Channel used */ + struct DMA_Control_Reg dmaCtrlRegVal; /*!< DMA Basic Pararmeter */ + DMA_LLI_Cfg_Type *DMA_LLI_Cfg; /*!< LLI Config parameter */ + uint32_t operatePeriphAddr; /*!< Operate Peripheral register address */ + uint32_t chache_buf_addr[2]; /*!< Ping-Pong structure chache */ + BL_Fun_Type is_single_mode; /*!< is Ping-pong running forever or single mode ,if is single mode ping-pong will run only once + after one start */ +}DMA_LLI_PP_Struct; + +/*@} end of group DMA_Public_Types */ + +/** @defgroup DMA_Public_Constants + * @{ + */ + +/** @defgroup DMA_ENDIAN_TYPE + * @{ + */ +#define IS_DMA_ENDIAN_TYPE(type) (((type) == DMA_LITTLE_ENDIAN ) || \ + ((type) == DMA_BIG_ENDIAN)) + +/** @defgroup DMA_SYNC_LOGIC_TYPE + * @{ + */ +#define IS_DMA_SYNC_LOGIC_TYPE(type) (((type) == DMA_SYNC_LOGIC_ENABLE ) || \ + ((type) == DMA_SYNC_LOGIC_DISABLE)) + +/** @defgroup DMA_TRANS_WIDTH_TYPE + * @{ + */ +#define IS_DMA_TRANS_WIDTH_TYPE(type) (((type) == DMA_TRNS_WIDTH_8BITS ) || \ + ((type) == DMA_TRNS_WIDTH_16BITS) || \ + ((type) == DMA_TRNS_WIDTH_32BITS)) + +/** @defgroup DMA_TRANS_DIR_TYPE + * @{ + */ +#define IS_DMA_TRANS_DIR_TYPE(type) (((type) == DMA_TRNS_M2M ) || \ + ((type) == DMA_TRNS_M2P) || \ + ((type) == DMA_TRNS_P2M) || \ + ((type) == DMA_TRNS_P2P)) + +/** @defgroup DMA_BURST_SIZE_TYPE + * @{ + */ +#define IS_DMA_BURST_SIZE_TYPE(type) (((type) == DMA_BURST_SIZE_1 ) || \ + ((type) == DMA_BURST_SIZE_4) || \ + ((type) == DMA_BURST_SIZE_8) || \ + ((type) == DMA_BURST_SIZE_16)) + +/** @defgroup DMA_PERIPH_REQ_TYPE + * @{ + */ +#define IS_DMA_PERIPH_REQ_TYPE(type) (((type) == DMA_REQ_UART0_RX ) || \ + ((type) == DMA_REQ_UART0_TX) || \ + ((type) == DMA_REQ_UART1_RX) || \ + ((type) == DMA_REQ_UART1_TX) || \ + ((type) == DMA_REQ_I2C_RX ) || \ + ((type) == DMA_REQ_I2C_TX) || \ + ((type) == DMA_REQ_SPI_RX ) || \ + ((type) == DMA_REQ_SPI_TX) || \ + ((type) == DMA_REQ_GPADC0 ) || \ + ((type) == DMA_REQ_GPADC1) || \ + ((type) == DMA_REQ_NONE )) + +/** @defgroup DMA_CHAN_TYPE + * @{ + */ +#define IS_DMA_CHAN_TYPE(type) (((type) == DMA_CH0 ) || \ + ((type) == DMA_CH1) || \ + ((type) == DMA_CH2) || \ + ((type) == DMA_CH3) || \ + ((type) == DMA_CH_MAX)) + +/** @defgroup DMA_INT_TYPE + * @{ + */ +#define IS_DMA_INT_TYPE(type) (((type) == DMA_INT_TCOMPLETED ) || \ + ((type) == DMA_INT_ERR) || \ + ((type) == DMA_INT_ALL)) + +/** @defgroup DMA_LLI_PP_INDEX_TYPE + * @{ + */ +#define IS_DMA_LLI_PP_INDEX_TYPE(type) (((type) == PING_INDEX ) || \ + ((type) == PONG_INDEX)) + +/*@} end of group DMA_Public_Constants */ + +/** @defgroup DMA_Public_Macros + * @{ + */ +#define DMA_PINC_ENABLE 1 +#define DMA_PINC_DISABLE 0 +#define DMA_MINC_ENABLE 1 +#define DMA_MINC_DISABLE 0 + +/*@} end of group DMA_Public_Macros */ + +/** @defgroup DMA_Public_Functions + * @{ + */ + +/** + * @brief DMA Functions + */ +void DMA_Enable(void); +void DMA_Disable(void); +void DMA_Channel_Init(DMA_Channel_Cfg_Type *chCfg); +void DMA_Channel_Update_SrcMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len); +void DMA_Channel_Update_DstMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len); +uint32_t DMA_Channel_TranferSize(uint8_t ch); +BL_Sts_Type DMA_Channel_Is_Busy(uint8_t ch); +void DMA_Channel_Enable(uint8_t ch); +void DMA_Channel_Disable(uint8_t ch); +void DMA_LLI_Init(uint8_t ch,DMA_LLI_Cfg_Type *lliCfg); +void DMA_LLI_Update(uint8_t ch, uint32_t LLI); +void DMA_IntMask(uint8_t ch,DMA_INT_Type intType, BL_Mask_Type intMask); +BL_Err_Type DMA_LLI_PpStruct_Init(DMA_LLI_PP_Struct *dmaPpStruct); +DMA_LLI_Ctrl_Type * DMA_LLI_PpBuf_Remove_Completed_List(DMA_LLI_PP_Buf *dmaPpBuf); +void DMA_LLI_PpBuf_Append(DMA_LLI_PP_Buf *dmaPpBuf, DMA_LLI_Ctrl_Type *dmaLliList); +void DMA_LLI_PpBuf_Destroy(DMA_LLI_PP_Buf *dmaPpBuf); +void DMA_Int_Callback_Install(DMA_Chan_Type dmaChan,DMA_INT_Type intType,intCallback_Type * cbFun); +void DMA_LLI_PpBuf_Start_New_Transmit(DMA_LLI_PP_Buf *dmaPpBuf); +void DMA_LLI_PpStruct_Start(DMA_LLI_PP_Struct *dmaPpStruct); +void DMA_LLI_PpStruct_Stop(DMA_LLI_PP_Struct *dmaPpStruct); +BL_Err_Type DMA_LLI_PpStruct_Set_Transfer_Len(DMA_LLI_PP_Struct *dmaPpStruct, + uint16_t Ping_Transfer_len,uint16_t Pong_Transfer_len); + +/*@} end of group DMA_Public_Functions */ + +/*@} end of group DMA */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_DMA_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_ef_ctrl.h b/drivers/bl602_driver/std_drv/inc/bl602_ef_ctrl.h new file mode 100644 index 00000000..997e9299 --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_ef_ctrl.h @@ -0,0 +1,324 @@ +/** + ****************************************************************************** + * @file bl602_ef_ctrl.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_EF_CTRL_H__ +#define __BL602_EF_CTRL_H__ + +#include "ef_ctrl_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup EF_CTRL + * @{ + */ + +/** @defgroup EF_CTRL_Public_Types + * @{ + */ + +/** + * @brief Efuse Ctrl key slot type definition + */ +typedef enum { + EF_CTRL_KEY_SLOT0, /*!< key slot 0 */ + EF_CTRL_KEY_SLOT1, /*!< key slot 1 */ + EF_CTRL_KEY_SLOT2, /*!< key slot 2 */ + EF_CTRL_KEY_SLOT3, /*!< key slot 3 */ + EF_CTRL_KEY_SLOT4, /*!< key slot 4 */ + EF_CTRL_KEY_SLOT5, /*!< key slot 5 */ + EF_CTRL_KEY_MAX, /*!< */ +}EF_Ctrl_Key_Type; + +/** + * @brief Efuse Ctrl sign type definition + */ +typedef enum { + EF_CTRL_SIGN_NONE, /*!< no sign */ + EF_CTRL_SIGN_RSA, /*!< use RSA to sign */ + EF_CTRL_SIGN_ECC, /*!< use ECC to sign */ +}EF_Ctrl_Sign_Type; + +/** + * @brief Efuse Ctrl flash AES type definition + */ +typedef enum { + EF_CTRL_SF_AES_NONE, /*!< No AES */ + EF_CTRL_SF_AES_128, /*!< AES 128 */ + EF_CTRL_SF_AES_192, /*!< AES 192 */ + EF_CTRL_SF_AES_256, /*!< AES 256 */ +}EF_Ctrl_SF_AES_Type; + +/** + * @brief Efuse Ctrl Dbg type definition + */ +typedef enum { + EF_CTRL_DBG_OPEN = 0, /*!< Open debug */ + EF_CTRL_DBG_PASSWORD, /*!< Open debug with password */ + EF_CTRL_DBG_CLOSE=4, /*!< Close debug */ +}EF_Ctrl_Dbg_Mode_Type; + +/** + * @brief Efuse Ctrl clock type definition + */ +typedef enum { + EF_CTRL_EF_CLK, /*!< Select efuse clock */ + EF_CTRL_SAHB_CLK, /*!< Select SAHB clock */ +}EF_Ctrl_CLK_Type; + +/** + * @brief Efuse Ctrl clock type definition + */ +typedef enum { + EF_CTRL_PARA_DFT , /*!< Select default cyc parameter */ + EF_CTRL_PARA_MANUAL, /*!< Select manual cyc parameter */ +}EF_Ctrl_CYC_PARA_Type; + +/** + * @brief Efuse Ctrl clock type definition + */ +typedef enum { + EF_CTRL_OP_MODE_AUTO , /*!< Select efuse program auto mode */ + EF_CTRL_OP_MODE_MANUAL, /*!< Select efuse program manual mode */ +}EF_Ctrl_OP_MODE_Type; + +/** + * @brief Efuse Ctrl secure configuration structure type definition + */ +typedef struct { + EF_Ctrl_Dbg_Mode_Type ef_dbg_mode; /*!< Efuse debug mode */ + uint8_t ef_dbg_jtag_0_dis; /*!< Jtag debug disable config value */ + uint8_t ef_sboot_en; /*!< Secure boot enable config value */ + uint8_t ef_no_hd_boot_en; /*!< No header boot enable */ +}EF_Ctrl_Sec_Param_Type; + +/** + * @brief Efuse analog RC32M trim type definition + */ +typedef struct { + uint32_t trimRc32mCodeFrExt : 8; /*!< Efuse analog trim:trim_rc32m_code_fr_ext */ + uint32_t trimRc32mCodeFrExtParity : 1; /*!< Efuse analog trim:trim_rc32m_ext_code_en_parity */ + uint32_t trimRc32mExtCodeEn : 1; /*!< Efuse analog trim:trim_rc32m_ext_code_en */ + uint32_t reserved : 22; /*!< Efuse analog trim:reserved */ +}Efuse_Ana_RC32M_Trim_Type; + +/** + * @brief Efuse analog RC32K trim type definition + */ +typedef struct { + uint32_t trimRc32kCodeFrExt : 10; /*!< Efuse analog trim:trim_rc32k_code_fr_ext */ + uint32_t trimRc32kCodeFrExtParity : 1; /*!< Efuse analog trim:trim_rc32k_code_fr_ext_parity */ + uint32_t trimRc32kExtCodeEn : 1; /*!< Efuse analog trim:trim_rc32k_ext_code_en */ + uint32_t reserved : 20; /*!< Efuse analog trim:reserved */ +}Efuse_Ana_RC32K_Trim_Type; + +/** + * @brief Efuse analog TSEN trim type definition + */ +typedef struct { + uint32_t tsenRefcodeCorner : 12; /*!< TSEN refcode */ + uint32_t tsenRefcodeCornerParity : 1; /*!< TSEN refcode parity */ + uint32_t tsenRefcodeCornerEn : 1; /*!< TSEN refcode enable */ + uint32_t tsenRefcodeCornerVersion : 1; /*!< TSEN refcode version */ + uint32_t reserved : 17; /*!< TSEN analog trim:reserved */ +}Efuse_TSEN_Refcode_Corner_Type; + +/** + * @brief Efuse analog ADC Gain trim type definition + */ +typedef struct { + uint32_t adcGainCoeff : 12; /*!< ADC gain coeff */ + uint32_t adcGainCoeffParity : 1; /*!< ADC gain coeff parity */ + uint32_t adcGainCoeffEn : 1; /*!< ADC gain coeff enable */ + uint32_t reserved : 18; /*!< ADC gain coeff:reserved */ +}Efuse_ADC_Gain_Coeff_Type; + +/** + * @brief Efuse analog device info type definition + */ +typedef struct { + uint32_t rsvd : 22; /*!< Reserved */ + uint32_t customerID : 2; /*!< Efuse customer ID information */ + uint32_t rsvd_info : 3; /*!< Efuse device info extension: 1:BL602C, 2:BL602L, 3:BL602E */ + uint32_t memoryInfo : 2; /*!< Efuse memory info 0:no memory, 1:1MB flash, 2:2MB flash */ + uint32_t coreInfo : 1; /*!< Efuse reserved */ + uint32_t mcuInfo : 1; /*!< Efuse mcu info 0:wifi, 1:mcu */ + uint32_t pinInfo : 1; /*!< Efuse pin info 0:QFN32, 1:QFN40 */ +}Efuse_Device_Info_Type; + +/** + * @brief Efuse Capcode type definition + */ +typedef struct { + uint32_t capCode : 6; /*!< Cap code value */ + uint32_t parity : 1; /*!< Parity of capcode */ + uint32_t en : 1; /*!< Enable status */ + uint32_t rsvd : 24; /*!< Reserved */ +}Efuse_Capcode_Info_Type; + +/*@} end of group EF_CTRL_Public_Types */ + +/** @defgroup EF_CTRL_Public_Constants + * @{ + */ + +/** @defgroup EF_CTRL_KEY_TYPE + * @{ + */ +#define IS_EF_CTRL_KEY_TYPE(type) (((type) == EF_CTRL_KEY_SLOT0) || \ + ((type) == EF_CTRL_KEY_SLOT1) || \ + ((type) == EF_CTRL_KEY_SLOT2) || \ + ((type) == EF_CTRL_KEY_SLOT3) || \ + ((type) == EF_CTRL_KEY_SLOT4) || \ + ((type) == EF_CTRL_KEY_SLOT5) || \ + ((type) == EF_CTRL_KEY_MAX)) + +/** @defgroup EF_CTRL_SIGN_TYPE + * @{ + */ +#define IS_EF_CTRL_SIGN_TYPE(type) (((type) == EF_CTRL_SIGN_NONE) || \ + ((type) == EF_CTRL_SIGN_RSA) || \ + ((type) == EF_CTRL_SIGN_ECC)) + +/** @defgroup EF_CTRL_SF_AES_TYPE + * @{ + */ +#define IS_EF_CTRL_SF_AES_TYPE(type) (((type) == EF_CTRL_SF_AES_NONE) || \ + ((type) == EF_CTRL_SF_AES_128) || \ + ((type) == EF_CTRL_SF_AES_192) || \ + ((type) == EF_CTRL_SF_AES_256)) + +/** @defgroup EF_CTRL_DBG_MODE_TYPE + * @{ + */ +#define IS_EF_CTRL_DBG_MODE_TYPE(type) (((type) == EF_CTRL_DBG_OPEN ) || \ + ((type) == EF_CTRL_DBG_PASSWORD) || \ + ((type) == EF_CTRL_DBG_CLOSE)) + +/** @defgroup EF_CTRL_CLK_TYPE + * @{ + */ +#define IS_EF_CTRL_CLK_TYPE(type) (((type) == EF_CTRL_EF_CLK) || \ + ((type) == EF_CTRL_SAHB_CLK)) + +/** @defgroup EF_CTRL_CYC_PARA_TYPE + * @{ + */ +#define IS_EF_CTRL_CYC_PARA_TYPE(type) (((type) == EF_CTRL_PARA_DFT ) || \ + ((type) == EF_CTRL_PARA_MANUAL)) + +/** @defgroup EF_CTRL_OP_MODE_TYPE + * @{ + */ +#define IS_EF_CTRL_OP_MODE_TYPE(type) (((type) == EF_CTRL_OP_MODE_AUTO ) || \ + ((type) == EF_CTRL_OP_MODE_MANUAL)) + +/*@} end of group EF_CTRL_Public_Constants */ + +/** @defgroup EF_CTRL_Public_Macros + * @{ + */ +#define EF_CTRL_EFUSE_R0_SIZE 128 + +/*@} end of group EF_CTRL_Public_Macros */ + +/** @defgroup EF_CTRL_Public_Functions + * @{ + */ +void EF_Ctrl_Load_Efuse_R0(void); +void EF_Ctrl_Program_Efuse_0(void); +BL_Sts_Type EF_Ctrl_Busy(void); +BL_Sts_Type EF_Ctrl_AutoLoad_Done(void); +void EF_Ctrl_Write_Dbg_Pwd(uint32_t passWdLow, uint32_t passWdHigh,uint8_t program); +void EF_Ctrl_Read_Dbg_Pwd(uint32_t *passWdLow, uint32_t *passWdHigh); +void EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program); +void EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program); +void EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg,uint8_t program); +void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg); +void EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1],uint8_t program); +void EF_Ctrl_Read_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1]); +void EF_Ctrl_Read_CPU_Cfg(uint8_t *apDisabled,uint8_t *npDisabled,uint8_t *npCpuType); +uint8_t EF_Ctrl_Get_Trim_Enable(void); +uint8_t EF_Ctrl_Get_Trim_Parity(uint32_t val,uint8_t len); +void EF_Ctrl_Write_Ana_Trim(uint32_t index, uint32_t trim,uint8_t program); +void EF_Ctrl_Read_Ana_Trim( uint32_t index, uint32_t *trim); +void EF_Ctrl_Read_RC32M_Trim( Efuse_Ana_RC32M_Trim_Type *trim); +void EF_Ctrl_Read_RC32K_Trim( Efuse_Ana_RC32K_Trim_Type *trim); +void EF_Ctrl_Read_TSEN_Trim( Efuse_TSEN_Refcode_Corner_Type *trim); +void EF_Ctrl_Read_ADC_Gain_Trim( Efuse_ADC_Gain_Coeff_Type *trim); +void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage,uint8_t program); +void EF_Ctrl_Read_Sw_Usage( uint32_t index, uint32_t *usage); +void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program); +void EF_Ctrl_Write_MAC_Address(uint8_t mac[6],uint8_t program); +BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[6]); +BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]); +void EF_Ctrl_Writelock_MAC_Address(uint8_t program); +BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t id[8]); +void EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo); +void EF_Ctrl_Write_AES_Key(uint8_t index,uint32_t *keyData,uint32_t len,uint8_t program); +void EF_Ctrl_Read_AES_Key(uint8_t index,uint32_t *keyData,uint32_t len); +void EF_Ctrl_Writelock_AES_Key(uint8_t index,uint8_t program); +void EF_Ctrl_Readlock_AES_Key(uint8_t index,uint8_t program); +void EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len); +void EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len); +void EF_Ctrl_Program_Direct(uint32_t index, uint32_t *data, uint32_t len); +void EF_Ctrl_Read_Direct(uint32_t index, uint32_t *data, uint32_t len); +void EF_Ctrl_Clear(uint32_t index, uint32_t len); +void EF_Ctrl_Crc_Enable(void); +BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void); +void EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue); +BL_Err_Type EF_Ctrl_Crc_Result(void); +void EF_Ctrl_Sw_AHB_Clk_0(void); +uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot,uint8_t reload); +BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot,uint8_t mac[6],uint8_t program); +BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot,uint8_t mac[6],uint8_t reload); +uint8_t EF_Ctrl_Is_CapCode_Slot_Empty(uint8_t slot,uint8_t reload); +BL_Err_Type EF_Ctrl_Write_CapCode_Opt(uint8_t slot,uint8_t code,uint8_t program); +BL_Err_Type EF_Ctrl_Read_CapCode_Opt(uint8_t slot,uint8_t *code,uint8_t reload); +uint8_t EF_Ctrl_Is_PowerOffset_Slot_Empty(uint8_t slot,uint8_t reload); +BL_Err_Type EF_Ctrl_Write_PowerOffset_Opt(uint8_t slot,int8_t pwrOffset[3],uint8_t program); +BL_Err_Type EF_Ctrl_Read_PowerOffset_Opt(uint8_t slot,int8_t pwrOffset[3],uint8_t reload); +void EF_Ctrl_Write_R0(uint32_t index, uint32_t *data, uint32_t len); +void EF_Ctrl_Read_R0(uint32_t index, uint32_t *data, uint32_t len); + +/*@} end of group EF_CTRL_Public_Functions */ + +/*@} end of group EF_CTRL */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_EF_CTRL_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_glb.h b/drivers/bl602_driver/std_drv/inc/bl602_glb.h new file mode 100644 index 00000000..e15a5f70 --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_glb.h @@ -0,0 +1,665 @@ +/** + ****************************************************************************** + * @file bl602_glb.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_GLB_H__ +#define __BL602_GLB_H__ + +#include "glb_reg.h" +#include "pds_reg.h" +#include "bl602_gpio.h" +#include "bl602_l1c.h" +#include "bl602_hbn.h" +#include "bl602_sf_ctrl.h" +#include "bl602_sf_cfg.h" +#include "bl602_aon.h" +#include "bl602_ef_ctrl.h" +#include "bl602_pds.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup GLB + * @{ + */ + +/** @defgroup GLB_Public_Types + * @{ + */ + +/** + * @brief GLB root clock type definition + */ +typedef enum { + GLB_ROOT_CLK_RC32M, /*!< root clock select RC32M */ + GLB_ROOT_CLK_XTAL, /*!< root clock select XTAL */ + GLB_ROOT_CLK_PLL, /*!< root clock select PLL others */ +}GLB_ROOT_CLK_Type; + +/** + * @brief GLB system clock type definition + */ +typedef enum { + GLB_SYS_CLK_RC32M, /*!< use RC32M as system clock frequency */ + GLB_SYS_CLK_XTAL, /*!< use XTAL as system clock */ + GLB_SYS_CLK_PLL48M, /*!< use PLL output 48M as system clock */ + GLB_SYS_CLK_PLL120M, /*!< use PLL output 120M as system clock */ + GLB_SYS_CLK_PLL160M, /*!< use PLL output 160M as system clock */ + GLB_SYS_CLK_PLL192M, /*!< use PLL output 192M as system clock */ +}GLB_SYS_CLK_Type; + +/** + * @brief GLB DMA clock ID type definition + */ +typedef enum { + GLB_DMA_CLK_DMA0_CH0, /*!< DMA clock ID:channel 0 */ + GLB_DMA_CLK_DMA0_CH1, /*!< DMA clock ID:channel 1 */ + GLB_DMA_CLK_DMA0_CH2, /*!< DMA clock ID:channel 2 */ + GLB_DMA_CLK_DMA0_CH3, /*!< DMA clock ID:channel 3 */ +}GLB_DMA_CLK_ID_Type; + +/** + * @brief GLB clock source type definition + */ +typedef enum { + GLB_IR_CLK_SRC_XCLK, /*!< IR clock source select XCLK */ +}GLB_IR_CLK_SRC_Type; + +/** + * @brief GLB flash clock type definition + */ +typedef enum { + GLB_SFLASH_CLK_120M, /*!< Select 120M as flash clock */ + GLB_SFLASH_CLK_XTAL, /*!< Select XTAL as flash clock */ + GLB_SFLASH_CLK_48M, /*!< Select 48M as flash clock */ + GLB_SFLASH_CLK_80M, /*!< Select 80M as flash clock */ + GLB_SFLASH_CLK_BCLK, /*!< Select BCLK as flash clock */ + GLB_SFLASH_CLK_96M, /*!< Select 96M as flash clock */ +}GLB_SFLASH_CLK_Type; + +/** + * @brief GLB SPI pad action type definition + */ +typedef enum { + GLB_SPI_PAD_ACT_AS_SLAVE, /*!< SPI pad act as slave */ + GLB_SPI_PAD_ACT_AS_MASTER, /*!< SPI pad act as master */ +}GLB_SPI_PAD_ACT_AS_Type; + +/** + * @brief GLB PKA clock type definition + */ +typedef enum { + GLB_PKA_CLK_HCLK, /*!< Select HCLK as PKA clock */ + GLB_PKA_CLK_PLL120M, /*!< Select PLL 120M as PKA clock */ +}GLB_PKA_CLK_Type; + +/** + * @brief BMX arb mode type definition + */ +typedef enum { + BMX_ARB_FIX, /*!< 0->fix */ + BMX_ARB_ROUND_ROBIN, /*!< 2->round-robin */ + BMX_ARB_RANDOM, /*!< 3->random */ +}BMX_ARB_Type; + +/** + * @brief BMX configuration structure type definition + */ +typedef struct { + uint8_t timeoutEn; /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */ + BL_Fun_Type errEn; /*!< Bus error response enable */ + BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */ +}BMX_Cfg_Type; + +/** + * @brief BMX bus err type definition + */ +typedef enum { + BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */ + BMX_BUS_ERR_ADDR_DECODE, /*!< Bus addr decode error */ +}BMX_BUS_ERR_Type; + +/** + * @brief BMX bus err interrupt type definition + */ +typedef enum { + BMX_ERR_INT_ERR, /*!< BMX bus err interrupt */ + BMX_ERR_INT_ALL, /*!< BMX bus err interrupt max num */ +}BMX_ERR_INT_Type; + +/** + * @brief BMX time out interrupt type definition + */ +typedef enum { + BMX_TO_INT_TIMEOUT, /*!< BMX timeout interrupt */ + BMX_TO_INT_ALL, /*!< BMX timeout interrupt max num */ +}BMX_TO_INT_Type; + +/** + * @brief GLB EM type definition + */ +typedef enum { + GLB_EM_0KB=0x0, /*!< 0x0 --> 0KB */ + GLB_EM_8KB=0x3, /*!< 0x3 --> 8KB */ + GLB_EM_16KB=0xF, /*!< 0xF --> 16KB */ +}GLB_EM_Type; + +/** + * @brief GLB RTC clock type definition + */ +typedef enum { + GLB_MTIMER_CLK_BCLK, /*!< BUS clock */ + GLB_MTIMER_CLK_32K, /*!< 32KHz */ +}GLB_MTIMER_CLK_Type; + +/** + * @brief GLB ADC clock type definition + */ +typedef enum { + GLB_ADC_CLK_96M, /*!< use 96M as ADC clock */ + GLB_ADC_CLK_XCLK, /*!< use XCLK as ADC clock */ +}GLB_ADC_CLK_Type; + +/** + * @brief GLB DAC clock type definition + */ +typedef enum { + GLB_DAC_CLK_32M, /*!< use 32M as DAC clock */ + GLB_DAC_CLK_XCLK, /*!< use XCLK as DAC clock */ +}GLB_DAC_CLK_Type; + +/** + * @brief GLB DIG clock source select type definition + */ +typedef enum { + GLB_DIG_CLK_PLL_32M, /*!< select PLL 32M as DIG clock source */ + GLB_DIG_CLK_XCLK, /*!< select XCLK as DIG clock source */ +}GLB_DIG_CLK_Type; + +/** + * @brief GLB 512K clock out select type definition + */ +typedef enum { + GLB_512K_CLK_OUT_512K, /*!< select 512K clock out */ + GLB_512K_CLK_OUT_256K, /*!< select 256K clock out */ + GLB_512K_CLK_OUT_128K, /*!< select 128K clock out */ +}GLB_512K_CLK_OUT_Type; + +/** + * @brief GLB BT bandwidth type definition + */ +typedef enum { + GLB_BT_BANDWIDTH_1M, /*!< BT bandwidth 1MHz */ + GLB_BT_BANDWIDTH_2M, /*!< BT bandwidth 2MHz */ +}GLB_BT_BANDWIDTH_Type; + +/** + * @brief GLB UART signal type definition + */ +typedef enum { + GLB_UART_SIG_0, /*!< UART signal 0 */ + GLB_UART_SIG_1, /*!< UART signal 1 */ + GLB_UART_SIG_2, /*!< UART signal 2 */ + GLB_UART_SIG_3, /*!< UART signal 3 */ + GLB_UART_SIG_4, /*!< UART signal 4 */ + GLB_UART_SIG_5, /*!< UART signal 5 */ + GLB_UART_SIG_6, /*!< UART signal 6 */ + GLB_UART_SIG_7, /*!< UART signal 7 */ +}GLB_UART_SIG_Type; + +/** + * @brief GLB UART signal function type definition + */ +typedef enum { + GLB_UART_SIG_FUN_UART0_RTS, /*!< UART funtion: UART 0 RTS */ + GLB_UART_SIG_FUN_UART0_CTS, /*!< UART funtion: UART 0 CTS */ + GLB_UART_SIG_FUN_UART0_TXD, /*!< UART funtion: UART 0 TXD */ + GLB_UART_SIG_FUN_UART0_RXD, /*!< UART funtion: UART 0 RXD */ + GLB_UART_SIG_FUN_UART1_RTS, /*!< UART funtion: UART 1 RTS */ + GLB_UART_SIG_FUN_UART1_CTS, /*!< UART funtion: UART 1 CTS */ + GLB_UART_SIG_FUN_UART1_TXD, /*!< UART funtion: UART 1 TXD */ + GLB_UART_SIG_FUN_UART1_RXD, /*!< UART funtion: UART 1 RXD */ +}GLB_UART_SIG_FUN_Type; + +/** + * @brief GLB GPIO real mode type definition + */ +typedef enum { + GLB_GPIO_REAL_MODE_REG, /*!< GPIO real function is reg_gpio_x_func_sel */ + GLB_GPIO_REAL_MODE_SDIO=0x1, /*!< GPIO real function is SDIO */ + GLB_GPIO_REAL_MODE_RF=0xC, /*!< GPIO real function is RF */ + GLB_GPIO_REAL_MODE_JTAG=0xE, /*!< GPIO real function is JTAG */ + GLB_GPIO_REAL_MODE_CCI=0xF, /*!< GPIO real function is CCI */ +}GLB_GPIO_REAL_MODE_Type; + +/** + * @brief GLB GPIO interrupt trigger mode type definition + */ +typedef enum { + GLB_GPIO_INT_TRIG_NEG_PULSE, /*!< GPIO negedge pulse trigger interrupt */ + GLB_GPIO_INT_TRIG_POS_PULSE, /*!< GPIO posedge pulse trigger interrupt */ + GLB_GPIO_INT_TRIG_NEG_LEVEL, /*!< GPIO negedge level trigger interrupt (32k 3T) */ + GLB_GPIO_INT_TRIG_POS_LEVEL, /*!< GPIO posedge level trigger interrupt (32k 3T) */ +}GLB_GPIO_INT_TRIG_Type; + +/** + * @brief GLB GPIO interrupt control mode type definition + */ +typedef enum { + GLB_GPIO_INT_CONTROL_SYNC, /*!< GPIO interrupt sync mode */ + GLB_GPIO_INT_CONTROL_ASYNC, /*!< GPIO interrupt async mode */ +}GLB_GPIO_INT_CONTROL_Type; + +/** + * @brief PLL XTAL type definition + */ +typedef enum { + GLB_PLL_XTAL_NONE, /*!< XTAL is none */ + GLB_PLL_XTAL_24M, /*!< XTAL is 24M */ + GLB_PLL_XTAL_32M, /*!< XTAL is 32M */ + GLB_PLL_XTAL_38P4M, /*!< XTAL is 38.4M */ + GLB_PLL_XTAL_40M, /*!< XTAL is 40M */ + GLB_PLL_XTAL_26M, /*!< XTAL is 26M */ + GLB_PLL_XTAL_RC32M, /*!< XTAL is RC32M */ +}GLB_PLL_XTAL_Type; + +/** + * @brief PLL output clock type definition + */ +typedef enum { + GLB_PLL_CLK_480M, /*!< PLL output clock:480M */ + GLB_PLL_CLK_240M, /*!< PLL output clock:240M */ + GLB_PLL_CLK_192M, /*!< PLL output clock:192M */ + GLB_PLL_CLK_160M, /*!< PLL output clock:160M */ + GLB_PLL_CLK_120M, /*!< PLL output clock:120M */ + GLB_PLL_CLK_96M, /*!< PLL output clock:96M */ + GLB_PLL_CLK_80M, /*!< PLL output clock:80M */ + GLB_PLL_CLK_48M, /*!< PLL output clock:48M */ + GLB_PLL_CLK_32M, /*!< PLL output clock:32M */ +}GLB_PLL_CLK_Type; + +/** + * @brief PLL configuration structure type definition + */ +typedef struct { + uint8_t clkpllIcp1u; /*!< int mode:0, frac mode:1 */ + uint8_t clkpllIcp5u; /*!< int mode:2, frac mode:0 */ + uint8_t clkpllIntFracSw; /*!< 0:int mode, 1:frac mode */ + uint8_t clkpllC3; /*!< int:3, frac:2 */ + uint8_t clkpllCz; /*!< int:1, frac:2 */ + uint8_t clkpllRz; /*!< int:1, frac:5 */ + uint8_t clkpllR4; /*!< int:2, frac:2 */ + uint8_t clkpllR4Short; /*!< int:1, frac:0 */ + uint8_t clkpllRefdivRatio; /*!< ref divider ratio */ + uint8_t clkpllPostdiv; /*!< >=8 and should be even number */ + uint32_t clkpllSdmin; /*!< sdmin */ + uint8_t clkpllSelFbClk; /*!< 0:mod1, 1:mod2, 2:mod3 */ + uint8_t clkpllSelSampleClk; /*!< 0:[16,63)mod3, 1:[32:127)mod4, 2:[64,255)mod5 */ +}GLB_PLL_Cfg_Type; + +/*@} end of group GLB_Public_Types */ + +/** @defgroup GLB_Public_Constants + * @{ + */ + +/** @defgroup GLB_ROOT_CLK_TYPE + * @{ + */ +#define IS_GLB_ROOT_CLK_TYPE(type) (((type) == GLB_ROOT_CLK_RC32M) || \ + ((type) == GLB_ROOT_CLK_XTAL) || \ + ((type) == GLB_ROOT_CLK_PLL)) + +/** @defgroup GLB_SYS_CLK_TYPE + * @{ + */ +#define IS_GLB_SYS_CLK_TYPE(type) (((type) == GLB_SYS_CLK_RC32M) || \ + ((type) == GLB_SYS_CLK_XTAL) || \ + ((type) == GLB_SYS_CLK_PLL48M) || \ + ((type) == GLB_SYS_CLK_PLL120M) || \ + ((type) == GLB_SYS_CLK_PLL160M) || \ + ((type) == GLB_SYS_CLK_PLL192M)) + +/** @defgroup GLB_DMA_CLK_ID_TYPE + * @{ + */ +#define IS_GLB_DMA_CLK_ID_TYPE(type) (((type) == GLB_DMA_CLK_DMA0_CH0) || \ + ((type) == GLB_DMA_CLK_DMA0_CH1) || \ + ((type) == GLB_DMA_CLK_DMA0_CH2) || \ + ((type) == GLB_DMA_CLK_DMA0_CH3)) + +/** @defgroup GLB_IR_CLK_SRC_TYPE + * @{ + */ +#define IS_GLB_IR_CLK_SRC_TYPE(type) (((type) == GLB_IR_CLK_SRC_XCLK)) + +/** @defgroup GLB_SFLASH_CLK_TYPE + * @{ + */ +#define IS_GLB_SFLASH_CLK_TYPE(type) (((type) == GLB_SFLASH_CLK_120M) || \ + ((type) == GLB_SFLASH_CLK_XTAL) || \ + ((type) == GLB_SFLASH_CLK_48M) || \ + ((type) == GLB_SFLASH_CLK_80M) || \ + ((type) == GLB_SFLASH_CLK_BCLK) || \ + ((type) == GLB_SFLASH_CLK_96M)) + +/** @defgroup GLB_SPI_PAD_ACT_AS_TYPE + * @{ + */ +#define IS_GLB_SPI_PAD_ACT_AS_TYPE(type) (((type) == GLB_SPI_PAD_ACT_AS_SLAVE) || \ + ((type) == GLB_SPI_PAD_ACT_AS_MASTER)) + +/** @defgroup GLB_PKA_CLK_TYPE + * @{ + */ +#define IS_GLB_PKA_CLK_TYPE(type) (((type) == GLB_PKA_CLK_HCLK) || \ + ((type) == GLB_PKA_CLK_PLL120M)) + +/** @defgroup BMX_ARB_TYPE + * @{ + */ +#define IS_BMX_ARB_TYPE(type) (((type) == BMX_ARB_FIX) || \ + ((type) == BMX_ARB_ROUND_ROBIN) || \ + ((type) == BMX_ARB_RANDOM)) + +/** @defgroup BMX_BUS_ERR_TYPE + * @{ + */ +#define IS_BMX_BUS_ERR_TYPE(type) (((type) == BMX_BUS_ERR_TRUSTZONE_DECODE) || \ + ((type) == BMX_BUS_ERR_ADDR_DECODE)) + +/** @defgroup BMX_ERR_INT_TYPE + * @{ + */ +#define IS_BMX_ERR_INT_TYPE(type) (((type) == BMX_ERR_INT_ERR) || \ + ((type) == BMX_ERR_INT_ALL)) + +/** @defgroup BMX_TO_INT_TYPE + * @{ + */ +#define IS_BMX_TO_INT_TYPE(type) (((type) == BMX_TO_INT_TIMEOUT) || \ + ((type) == BMX_TO_INT_ALL)) + +/** @defgroup GLB_EM_TYPE + * @{ + */ +#define IS_GLB_EM_TYPE(type) (((type) == GLB_EM_0KB) || \ + ((type) == GLB_EM_8KB) || \ + ((type) == GLB_EM_16KB)) + +/** @defgroup GLB_MTIMER_CLK_TYPE + * @{ + */ +#define IS_GLB_MTIMER_CLK_TYPE(type) (((type) == GLB_MTIMER_CLK_BCLK) || \ + ((type) == GLB_MTIMER_CLK_32K)) + +/** @defgroup GLB_ADC_CLK_TYPE + * @{ + */ +#define IS_GLB_ADC_CLK_TYPE(type) (((type) == GLB_ADC_CLK_96M) || \ + ((type) == GLB_ADC_CLK_XCLK)) + +/** @defgroup GLB_DAC_CLK_TYPE + * @{ + */ +#define IS_GLB_DAC_CLK_TYPE(type) (((type) == GLB_DAC_CLK_32M) || \ + ((type) == GLB_DAC_CLK_XCLK)) + +/** @defgroup GLB_DIG_CLK_TYPE + * @{ + */ +#define IS_GLB_DIG_CLK_TYPE(type) (((type) == GLB_DIG_CLK_PLL_32M) || \ + ((type) == GLB_DIG_CLK_XCLK)) + +/** @defgroup GLB_512K_CLK_OUT_TYPE + * @{ + */ +#define IS_GLB_512K_CLK_OUT_TYPE(type) (((type) == GLB_512K_CLK_OUT_512K) || \ + ((type) == GLB_512K_CLK_OUT_256K) || \ + ((type) == GLB_512K_CLK_OUT_128K)) + +/** @defgroup GLB_BT_BANDWIDTH_TYPE + * @{ + */ +#define IS_GLB_BT_BANDWIDTH_TYPE(type) (((type) == GLB_BT_BANDWIDTH_1M) || \ + ((type) == GLB_BT_BANDWIDTH_2M)) + +/** @defgroup GLB_UART_SIG_TYPE + * @{ + */ +#define IS_GLB_UART_SIG_TYPE(type) (((type) == GLB_UART_SIG_0) || \ + ((type) == GLB_UART_SIG_1) || \ + ((type) == GLB_UART_SIG_2) || \ + ((type) == GLB_UART_SIG_3) || \ + ((type) == GLB_UART_SIG_4) || \ + ((type) == GLB_UART_SIG_5) || \ + ((type) == GLB_UART_SIG_6) || \ + ((type) == GLB_UART_SIG_7)) + +/** @defgroup GLB_UART_SIG_FUN_TYPE + * @{ + */ +#define IS_GLB_UART_SIG_FUN_TYPE(type) (((type) == GLB_UART_SIG_FUN_UART0_RTS) || \ + ((type) == GLB_UART_SIG_FUN_UART0_CTS) || \ + ((type) == GLB_UART_SIG_FUN_UART0_TXD) || \ + ((type) == GLB_UART_SIG_FUN_UART0_RXD) || \ + ((type) == GLB_UART_SIG_FUN_UART1_RTS) || \ + ((type) == GLB_UART_SIG_FUN_UART1_CTS) || \ + ((type) == GLB_UART_SIG_FUN_UART1_TXD) || \ + ((type) == GLB_UART_SIG_FUN_UART1_RXD)) + +/** @defgroup GLB_GPIO_REAL_MODE_TYPE + * @{ + */ +#define IS_GLB_GPIO_REAL_MODE_TYPE(type) (((type) == GLB_GPIO_REAL_MODE_REG) || \ + ((type) == GLB_GPIO_REAL_MODE_SDIO) || \ + ((type) == GLB_GPIO_REAL_MODE_RF) || \ + ((type) == GLB_GPIO_REAL_MODE_JTAG) || \ + ((type) == GLB_GPIO_REAL_MODE_CCI)) + +/** @defgroup GLB_GPIO_INT_TRIG_TYPE + * @{ + */ +#define IS_GLB_GPIO_INT_TRIG_TYPE(type) (((type) == GLB_GPIO_INT_TRIG_NEG_PULSE) || \ + ((type) == GLB_GPIO_INT_TRIG_POS_PULSE) || \ + ((type) == GLB_GPIO_INT_TRIG_NEG_LEVEL) || \ + ((type) == GLB_GPIO_INT_TRIG_POS_LEVEL)) + +/** @defgroup GLB_GPIO_INT_CONTROL_TYPE + * @{ + */ +#define IS_GLB_GPIO_INT_CONTROL_TYPE(type) (((type) == GLB_GPIO_INT_CONTROL_SYNC) || \ + ((type) == GLB_GPIO_INT_CONTROL_ASYNC)) + +/** @defgroup GLB_PLL_XTAL_TYPE + * @{ + */ +#define IS_GLB_PLL_XTAL_TYPE(type) (((type) == GLB_PLL_XTAL_NONE) || \ + ((type) == GLB_PLL_XTAL_24M) || \ + ((type) == GLB_PLL_XTAL_32M) || \ + ((type) == GLB_PLL_XTAL_38P4M) || \ + ((type) == GLB_PLL_XTAL_40M) || \ + ((type) == GLB_PLL_XTAL_26M) || \ + ((type) == GLB_PLL_XTAL_RC32M)) + +/** @defgroup GLB_PLL_CLK_TYPE + * @{ + */ +#define IS_GLB_PLL_CLK_TYPE(type) (((type) == GLB_PLL_CLK_480M) || \ + ((type) == GLB_PLL_CLK_240M) || \ + ((type) == GLB_PLL_CLK_192M) || \ + ((type) == GLB_PLL_CLK_160M) || \ + ((type) == GLB_PLL_CLK_120M) || \ + ((type) == GLB_PLL_CLK_96M) || \ + ((type) == GLB_PLL_CLK_80M) || \ + ((type) == GLB_PLL_CLK_48M) || \ + ((type) == GLB_PLL_CLK_32M)) + +/*@} end of group GLB_Public_Constants */ + +/** @defgroup GLB_Public_Macros + * @{ + */ +#define UART_SIG_SWAP_GPIO0_GPIO7 0x01 /* GPIO0-7 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */ +#define UART_SIG_SWAP_GPIO8_GPIO15 0x02 /* GPIO8-15 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */ +#define UART_SIG_SWAP_GPIO16_GPIO22 0x04 /* GPIO16-22 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */ +#define UART_SIG_SWAP_NONE 0x00 /* GPIO0-22 uart_sig[0:7] <- uart_sig[4:7], uart_sig[0:3] */ +#define JTAG_SIG_SWAP_GPIO0_GPIO3 0x01 /* GPIO0-3 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO4_GPIO7 0x02 /* GPIO4-7 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO8_GPIO11 0x04 /* GPIO8-11 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO12_GPIO15 0x08 /* GPIO12-15 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO16_GPIO19 0x10 /* GPIO16-19 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO20_GPIO22 0x20 /* GPIO20-22 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_NONE 0x00 /* GPIO0-22 E21_TMS/E21_TDI/E21_TCK/E21_TDO <- E21_TCK/E21_TDO/E21_TMS/E21_TDI */ + +/*@} end of group GLB_Public_Macros */ + +/** @defgroup GLB_Public_Functions + * @{ + */ +/*----------*/ +#ifndef BFLB_USE_HAL_DRIVER +void BMX_ERR_IRQHandler(void); +void BMX_TO_IRQHandler(void); +void GPIO_INT0_IRQHandler(void); +#endif +/*----------*/ +GLB_ROOT_CLK_Type GLB_Get_Root_CLK_Sel(void); +BL_Err_Type GLB_Set_System_CLK_Div(uint8_t hclkDiv,uint8_t bclkDiv); +uint8_t GLB_Get_BCLK_Div(void); +uint8_t GLB_Get_HCLK_Div(void); +BL_Err_Type Update_SystemCoreClockWith_XTAL(GLB_PLL_XTAL_Type xtalType); +BL_Err_Type GLB_Set_System_CLK(GLB_PLL_XTAL_Type xtalType,GLB_SYS_CLK_Type clkFreq); +BL_Err_Type System_Core_Clock_Update_From_RC32M(void); +/*----------*/ +BL_Err_Type GLB_Set_BLE_CLK(uint8_t enable); +BL_Err_Type GLB_Set_WiFi_Core_CLK(uint8_t clkDiv); +BL_Err_Type GLB_Set_WiFi_Encrypt_CLK(uint8_t clkDiv); +BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable,GLB_DMA_CLK_ID_Type clk); +BL_Err_Type GLB_Set_IR_CLK(uint8_t enable,GLB_IR_CLK_SRC_Type clkSel,uint8_t div); +BL_Err_Type GLB_Set_SF_CLK(uint8_t enable,GLB_SFLASH_CLK_Type clkSel,uint8_t div); +BL_Err_Type GLB_Set_UART_CLK(uint8_t enable,HBN_UART_CLK_Type clkSel,uint8_t div); +BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable,uint8_t div); +BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable,uint8_t div); +/*----------*/ +BL_Err_Type GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel); +BL_Err_Type GLB_SW_System_Reset(void); +BL_Err_Type GLB_SW_CPU_Reset(void); +BL_Err_Type GLB_SW_POR_Reset(void); +BL_Err_Type GLB_AHB_Slave1_Reset(BL_AHB_Slave1_Type slave1); +BL_Err_Type GLB_AHB_Slave1_Clock_Gate(uint8_t enable,BL_AHB_Slave1_Type slave1); +/*----------*/ +BL_Err_Type GLB_BMX_Init(BMX_Cfg_Type *BmxCfg); +BL_Err_Type GLB_BMX_Addr_Monitor_Enable(void); +BL_Err_Type GLB_BMX_Addr_Monitor_Disable(void); +BL_Err_Type GLB_BMX_BusErrResponse_Enable(void); +BL_Err_Type GLB_BMX_BusErrResponse_Disable(void); +BL_Sts_Type GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType); +uint32_t GLB_BMX_Get_Err_Addr(void); +BL_Err_Type BMX_ERR_INT_Callback_Install(BMX_ERR_INT_Type intType,intCallback_Type* cbFun); +BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType,intCallback_Type* cbFun); +/*----------*/ +BL_Err_Type GLB_Set_OCRAM_Idle(void); +BL_Err_Type GLB_Set_SRAM_RET(uint32_t value); +uint32_t GLB_Get_SRAM_RET(void); +BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value); +uint32_t GLB_Get_SRAM_SLP(void); +BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value); +uint32_t GLB_Get_SRAM_PARM(void); +/*----------*/ +BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType); +/*----------*/ +BL_Err_Type GLB_UART_Sig_Swap_Set(uint8_t swapSel); +BL_Err_Type GLB_JTAG_Sig_Swap_Set(uint8_t swapSel); +BL_Err_Type GLB_Swap_SPI_0_MOSI_With_MISO(BL_Fun_Type newState); +BL_Err_Type GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod); +BL_Err_Type GLB_Select_Internal_Flash(void); +BL_Err_Type GLB_Select_External_Flash(void); +BL_Err_Type GLB_Deswap_Flash_Pin(void); +BL_Err_Type GLB_Swap_Flash_Pin(void); +/*----------*/ +BL_Err_Type GLB_Set_MTimer_CLK(uint8_t enable,GLB_MTIMER_CLK_Type clkSel,uint32_t div); +/*----------*/ +BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable,GLB_ADC_CLK_Type clkSel,uint8_t div); +BL_Err_Type GLB_Set_DAC_CLK(uint8_t enable,GLB_DAC_CLK_Type clkSel,uint8_t div); +/*----------*/ +BL_Err_Type GLB_Platform_Wakeup_Enable(void); +BL_Err_Type GLB_Platform_Wakeup_Disable(void); +/*----------*/ +BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel); +BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable,uint8_t compensation,uint8_t div); +BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable,uint8_t compensation,uint8_t div); +/*----------*/ +BL_Err_Type GLB_Set_BT_Coex_Signal(uint8_t enable,GLB_BT_BANDWIDTH_Type bandWidth, + uint8_t pti,uint8_t channel); +/*----------*/ +BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig,GLB_UART_SIG_FUN_Type fun); +/*----------*/ +BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio); +BL_Err_Type GLB_IR_LED_Driver_Enable(void); +BL_Err_Type GLB_IR_LED_Driver_Disable(void); +BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias); +/*----------*/ +BL_Err_Type GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg); +BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun,GLB_GPIO_Type *pinList,uint8_t cnt); +BL_Err_Type GLB_GPIO_INPUT_Enable(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_Set_PullUp(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_Set_PullDown(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin); +uint8_t GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin); +GLB_GPIO_REAL_MODE_Type GLB_GPIO_Get_Real_Fun(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin,uint32_t val); +uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin,BL_Mask_Type intMask); +BL_Err_Type GLB_GPIO_IntClear(GLB_GPIO_Type gpioPin,BL_Sts_Type intClear); +BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_Set_GPIO_IntMod(GLB_GPIO_Type gpioPin,GLB_GPIO_INT_CONTROL_Type intCtlMod, + GLB_GPIO_INT_TRIG_Type intTrgMod); +GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_IntCtlMod(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void); +BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin,intCallback_Type* cbFun); + +/*@} end of group GLB_Public_Functions */ + +/*@} end of group GLB */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_GLB_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_gpio.h b/drivers/bl602_driver/std_drv/inc/bl602_gpio.h new file mode 100644 index 00000000..badf80a5 --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_gpio.h @@ -0,0 +1,447 @@ +/** + + ****************************************************************************** + + * @file bl602_gpio.h + + * @version V1.2 + + * @date 2019-12-14 + + * @brief This file is the description of.IP register + + ****************************************************************************** + + * @attention + + * + + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ + * + + * Redistribution and use in source and binary forms, with or without modification, + + * are permitted provided that the following conditions are met: + + * 1. Redistributions of source code must retain the above copyright notice, + + * this list of conditions and the following disclaimer. + + * 2. Redistributions in binary form must reproduce the above copyright notice, + + * this list of conditions and the following disclaimer in the documentation + + * and/or other materials provided with the distribution. + + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + + * may be used to endorse or promote products derived from this software + + * without specific prior written permission. + + * + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + * + + ****************************************************************************** + + */ + +#ifndef __BL602_GPIO_H__ +#define __BL602_GPIO_H__ + + +typedef enum +{ + GLB_GPIO_PIN_0 = 0, + GLB_GPIO_PIN_1, + GLB_GPIO_PIN_2, + GLB_GPIO_PIN_3, + GLB_GPIO_PIN_4, + GLB_GPIO_PIN_5, + GLB_GPIO_PIN_6, + GLB_GPIO_PIN_7, + GLB_GPIO_PIN_8, + GLB_GPIO_PIN_9, + GLB_GPIO_PIN_10, + GLB_GPIO_PIN_11, + GLB_GPIO_PIN_12, + GLB_GPIO_PIN_13, + GLB_GPIO_PIN_14, + GLB_GPIO_PIN_15, + GLB_GPIO_PIN_16, + GLB_GPIO_PIN_17, + GLB_GPIO_PIN_18, + GLB_GPIO_PIN_19, + GLB_GPIO_PIN_20, + GLB_GPIO_PIN_21, + GLB_GPIO_PIN_22, + GLB_GPIO_PIN_MAX, +}GLB_GPIO_Type; + +#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */ +#define GPIO_MODE_AF ((uint32_t)0x00000002U) /*!< Alternate function */ +#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog function */ +#define GPIO_PULL_UP ((uint32_t)0x00000000U) /*!< GPIO pull up */ +#define GPIO_PULL_DOWN ((uint32_t)0x00000001U) /*!< GPIO pull down */ +#define GPIO_PULL_NONE ((uint32_t)0x00000002U) /*!< GPIO no pull up or down */ + +typedef enum +{ + GPIO_FUN_SDIO = 1, + GPIO_FUN_FLASH = 2, + GPIO_FUN_SPI = 4, + GPIO_FUN_I2C = 6, + GPIO_FUN_UART = 7, + GPIO_FUN_PWM = 8, + GPIO_FUN_EXT_PA = 9, + GPIO_FUN_ANALOG = 10, + GPIO_FUN_SWGPIO = 11, + GPIO_FUN_GPIO = 11, + GPIO_FUN_JTAG = 14, + GPIO_FUN_UART0_RTS = 0x70 , + GPIO_FUN_UART0_CTS = 0x71 , + GPIO_FUN_UART0_TX = 0x72 , + GPIO_FUN_UART0_RX = 0x73 , + GPIO_FUN_UART1_RTS = 0x74 , + GPIO_FUN_UART1_CTS = 0x75 , + GPIO_FUN_UART1_TX = 0x76 , + GPIO_FUN_UART1_RX = 0x77 , + GPIO_FUN_GPIO_OUTPUT = 0x80, + GPIO_FUN_GPIO_INPUT = 0x81, + GPIO_FUN_UNUSED = 255, +}GLB_GPIO_FUNC_Type; + +typedef struct +{ + uint8_t gpioPin; + uint8_t gpioFun; + uint8_t gpioMode; + uint8_t pullType; + uint8_t drive; + uint8_t smtCtrl; +}GLB_GPIO_Cfg_Type; + +/* GPIO0 function definition */ +#define GPIO0_FUN_SDIO_CLK 1 +#define GPIO0_FUN_SF_D1 2 +#define GPIO0_FUN_UNUSED3 3 +#define GPIO0_FUN_SPI_MISO_SPI_MOSI 4 +#define GPIO0_FUN_UNUSED5 5 +#define GPIO0_FUN_I2C_SCL 6 +#define GPIO0_FUN_UART_SIG0 7 +#define GPIO0_FUN_PWM_CH0 8 +#define GPIO0_FUN_FEM_GPIO_0 9 +#define GPIO0_FUN_ATEST_IN 10 +#define GPIO0_FUN_SWGPIO_0 11 +#define GPIO0_FUN_E21_TMS 14 +/* GPIO1 function definition */ +#define GPIO1_FUN_SDIO_CMD 1 +#define GPIO1_FUN_SF_D2 2 +#define GPIO1_FUN_UNUSED3 3 +#define GPIO1_FUN_SPI_MOSI_SPI_MISO 4 +#define GPIO1_FUN_UNUSED5 5 +#define GPIO1_FUN_I2C_SDA 6 +#define GPIO1_FUN_UART_SIG1 7 +#define GPIO1_FUN_PWM_CH1 8 +#define GPIO1_FUN_FEM_GPIO_1 9 +#define GPIO1_FUN_ATEST_IP 10 +#define GPIO1_FUN_SWGPIO_1 11 +#define GPIO1_FUN_E21_TDI 14 +/* GPIO2 function definition */ +#define GPIO2_FUN_SDIO_DAT0 1 +#define GPIO2_FUN_SF_D3 2 +#define GPIO2_FUN_UNUSED3 3 +#define GPIO2_FUN_SPI_SS 4 +#define GPIO2_FUN_UNUSED5 5 +#define GPIO2_FUN_I2C_SCL 6 +#define GPIO2_FUN_UART_SIG2 7 +#define GPIO2_FUN_PWM_CH2 8 +#define GPIO2_FUN_FEM_GPIO_2 9 +#define GPIO2_FUN_ATEST_QN 10 +#define GPIO2_FUN_SWGPIO_2 11 +#define GPIO2_FUN_E21_TCK 14 +/* GPIO3 function definition */ +#define GPIO3_FUN_SDIO_DAT1 1 +#define GPIO3_FUN_UNUSED2 2 +#define GPIO3_FUN_UNUSED3 3 +#define GPIO3_FUN_SPI_SCLK 4 +#define GPIO3_FUN_UNUSED5 5 +#define GPIO3_FUN_I2C_SDA 6 +#define GPIO3_FUN_UART_SIG3 7 +#define GPIO3_FUN_PWM_CH3 8 +#define GPIO3_FUN_FEM_GPIO_3 9 +#define GPIO3_FUN_ATEST_QP 10 +#define GPIO3_FUN_SWGPIO_3 11 +#define GPIO3_FUN_E21_TDO 14 +/* GPIO4 function definition */ +#define GPIO4_FUN_SDIO_DAT2 1 +#define GPIO4_FUN_UNUSED2 2 +#define GPIO4_FUN_UNUSED3 3 +#define GPIO4_FUN_SPI_MISO_SPI_MOSI 4 +#define GPIO4_FUN_UNUSED5 5 +#define GPIO4_FUN_I2C_SCL 6 +#define GPIO4_FUN_UART_SIG4 7 +#define GPIO4_FUN_PWM_CH4 8 +#define GPIO4_FUN_FEM_GPIO_0 9 +#define GPIO4_FUN_GPIP_CH1 10 +#define GPIO4_FUN_SWGPIO_4 11 +#define GPIO4_FUN_E21_TMS 14 +/* GPIO5 function definition */ +#define GPIO5_FUN_SDIO_DAT3 1 +#define GPIO5_FUN_UNUSED2 2 +#define GPIO5_FUN_UNUSED3 3 +#define GPIO5_FUN_SPI_MOSI_SPI_MISO 4 +#define GPIO5_FUN_UNUSED5 5 +#define GPIO5_FUN_I2C_SDA 6 +#define GPIO5_FUN_UART_SIG5 7 +#define GPIO5_FUN_PWM_CH0 8 +#define GPIO5_FUN_FEM_GPIO_1 9 +#define GPIO5_FUN_GPIP_CH4 10 +#define GPIO5_FUN_SWGPIO_5 11 +#define GPIO5_FUN_E21_TDI 14 +/* GPIO6 function definition */ +#define GPIO6_FUN_UNUSED1 1 +#define GPIO6_FUN_UNUSED2 2 +#define GPIO6_FUN_UNUSED3 3 +#define GPIO6_FUN_SPI_SS 4 +#define GPIO6_FUN_UNUSED5 5 +#define GPIO6_FUN_I2C_SCL 6 +#define GPIO6_FUN_UART_SIG6 7 +#define GPIO6_FUN_PWM_CH1 8 +#define GPIO6_FUN_FEM_GPIO_2 9 +#define GPIO6_FUN_GPIP_CH5 10 +#define GPIO6_FUN_SWGPIO_6 11 +#define GPIO6_FUN_E21_TCK 14 +/* GPIO7 function definition */ +#define GPIO7_FUN_UNUSED1 1 +#define GPIO7_FUN_UNUSED2 2 +#define GPIO7_FUN_UNUSED3 3 +#define GPIO7_FUN_SPI_SCLK 4 +#define GPIO7_FUN_UNUSED5 5 +#define GPIO7_FUN_I2C_SDA 6 +#define GPIO7_FUN_UART_SIG7 7 +#define GPIO7_FUN_PWM_CH2 8 +#define GPIO7_FUN_FEM_GPIO_3 9 +#define GPIO7_FUN_UNUSED10 10 +#define GPIO7_FUN_SWGPIO_7 11 +#define GPIO7_FUN_E21_TDO 14 +/* GPIO8 function definition */ +#define GPIO8_FUN_UNUSED1 1 +#define GPIO8_FUN_UNUSED2 2 +#define GPIO8_FUN_UNUSED3 3 +#define GPIO8_FUN_SPI_MISO_SPI_MOSI 4 +#define GPIO8_FUN_UNUSED5 5 +#define GPIO8_FUN_I2C_SCL 6 +#define GPIO8_FUN_UART_SIG0 7 +#define GPIO8_FUN_PWM_CH3 8 +#define GPIO8_FUN_FEM_GPIO_0 9 +#define GPIO8_FUN_UNUSED10 10 +#define GPIO8_FUN_SWGPIO_8 11 +#define GPIO8_FUN_E21_TMS 14 +/* GPIO9 function definition */ +#define GPIO9_FUN_UNUSED1 1 +#define GPIO9_FUN_UNUSED2 2 +#define GPIO9_FUN_UNUSED3 3 +#define GPIO9_FUN_SPI_MOSI_SPI_MISO 4 +#define GPIO9_FUN_UNUSED5 5 +#define GPIO9_FUN_I2C_SDA 6 +#define GPIO9_FUN_UART_SIG1 7 +#define GPIO9_FUN_PWM_CH4 8 +#define GPIO9_FUN_FEM_GPIO_1 9 +#define GPIO9_FUN_GPIP_CH6_GPIP_CH7 10 +#define GPIO9_FUN_SWGPIO_9 11 +#define GPIO9_FUN_E21_TDI 14 +/* GPIO10 function definition */ +#define GPIO10_FUN_UNUSED1 1 +#define GPIO10_FUN_UNUSED2 2 +#define GPIO10_FUN_UNUSED3 3 +#define GPIO10_FUN_SPI_SS 4 +#define GPIO10_FUN_UNUSED5 5 +#define GPIO10_FUN_I2C_SCL 6 +#define GPIO10_FUN_UART_SIG2 7 +#define GPIO10_FUN_PWM_CH0 8 +#define GPIO10_FUN_FEM_GPIO_2 9 +#define GPIO10_FUN_MICBIAS_GPIP_CH8_GPIP_CH9 10 +#define GPIO10_FUN_SWGPIO_10 11 +#define GPIO10_FUN_E21_TCK 14 +/* GPIO11 function definition */ +#define GPIO11_FUN_UNUSED1 1 +#define GPIO11_FUN_UNUSED2 2 +#define GPIO11_FUN_UNUSED3 3 +#define GPIO11_FUN_SPI_SCLK 4 +#define GPIO11_FUN_UNUSED5 5 +#define GPIO11_FUN_I2C_SDA 6 +#define GPIO11_FUN_UART_SIG3 7 +#define GPIO11_FUN_PWM_CH1 8 +#define GPIO11_FUN_FEM_GPIO_3 9 +#define GPIO11_FUN_IRLED_OUT_GPIP_CH10 10 +#define GPIO11_FUN_SWGPIO_11 11 +#define GPIO11_FUN_E21_TDO 14 +/* GPIO12 function definition */ +#define GPIO12_FUN_UNUSED1 1 +#define GPIO12_FUN_UNUSED2 2 +#define GPIO12_FUN_UNUSED3 3 +#define GPIO12_FUN_SPI_MISO_SPI_MOSI 4 +#define GPIO12_FUN_UNUSED5 5 +#define GPIO12_FUN_I2C_SCL 6 +#define GPIO12_FUN_UART_SIG4 7 +#define GPIO12_FUN_PWM_CH2 8 +#define GPIO12_FUN_FEM_GPIO_0 9 +#define GPIO12_FUN_GPIP_CH0_GPADC_VREF_EXT 10 +#define GPIO12_FUN_SWGPIO_12 11 +#define GPIO12_FUN_E21_TMS 14 +/* GPIO13 function definition */ +#define GPIO13_FUN_UNUSED1 1 +#define GPIO13_FUN_UNUSED2 2 +#define GPIO13_FUN_UNUSED3 3 +#define GPIO13_FUN_SPI_MOSI_SPI_MISO 4 +#define GPIO13_FUN_UNUSED5 5 +#define GPIO13_FUN_I2C_SDA 6 +#define GPIO13_FUN_UART_SIG5 7 +#define GPIO13_FUN_PWM_CH3 8 +#define GPIO13_FUN_FEM_GPIO_1 9 +#define GPIO13_FUN_GPIP_CH3 10 +#define GPIO13_FUN_SWGPIO_13 11 +#define GPIO13_FUN_E21_TDI 14 +/* GPIO14 function definition */ +#define GPIO14_FUN_UNUSED1 1 +#define GPIO14_FUN_UNUSED2 2 +#define GPIO14_FUN_UNUSED3 3 +#define GPIO14_FUN_SPI_SS 4 +#define GPIO14_FUN_UNUSED5 5 +#define GPIO14_FUN_I2C_SCL 6 +#define GPIO14_FUN_UART_SIG6 7 +#define GPIO14_FUN_PWM_CH4 8 +#define GPIO14_FUN_FEM_GPIO_2 9 +#define GPIO14_FUN_GPIP_CH2 10 +#define GPIO14_FUN_SWGPIO_14 11 +#define GPIO14_FUN_E21_TCK 14 +/* GPIO15 function definition */ +#define GPIO15_FUN_UNUSED1 1 +#define GPIO15_FUN_UNUSED2 2 +#define GPIO15_FUN_UNUSED3 3 +#define GPIO15_FUN_SPI_SCLK 4 +#define GPIO15_FUN_UNUSED5 5 +#define GPIO15_FUN_I2C_SDA 6 +#define GPIO15_FUN_UART_SIG7 7 +#define GPIO15_FUN_PWM_CH0 8 +#define GPIO15_FUN_FEM_GPIO_3 9 +#define GPIO15_FUN_PSW_IRRCV_OUT_GPIP_CH11 10 +#define GPIO15_FUN_SWGPIO_15 11 +#define GPIO15_FUN_E21_TDO 14 +/* GPIO16 function definition */ +#define GPIO16_FUN_UNUSED1 1 +#define GPIO16_FUN_UNUSED2 2 +#define GPIO16_FUN_UNUSED3 3 +#define GPIO16_FUN_SPI_MISO_SPI_MOSI 4 +#define GPIO16_FUN_UNUSED5 5 +#define GPIO16_FUN_I2C_SCL 6 +#define GPIO16_FUN_UART_SIG0 7 +#define GPIO16_FUN_PWM_CH1 8 +#define GPIO16_FUN_FEM_GPIO_0 9 +#define GPIO16_FUN_UNUSED10 10 +#define GPIO16_FUN_SWGPIO_16 11 +#define GPIO16_FUN_E21_TMS 14 +/* GPIO17 function definition */ +#define GPIO17_FUN_UNUSED1 1 +#define GPIO17_FUN_SF_D3 2 +#define GPIO17_FUN_UNUSED3 3 +#define GPIO17_FUN_SPI_MOSI_SPI_MISO 4 +#define GPIO17_FUN_UNUSED5 5 +#define GPIO17_FUN_I2C_SDA 6 +#define GPIO17_FUN_UART_SIG1 7 +#define GPIO17_FUN_PWM_CH2 8 +#define GPIO17_FUN_FEM_GPIO_1 9 +#define GPIO17_FUN_PMIP_DC_TP_OUT 10 +#define GPIO17_FUN_SWGPIO_17 11 +#define GPIO17_FUN_E21_TDI 14 +/* GPIO18 function definition */ +#define GPIO18_FUN_UNUSED1 1 +#define GPIO18_FUN_SF_D2 2 +#define GPIO18_FUN_UNUSED3 3 +#define GPIO18_FUN_SPI_SS 4 +#define GPIO18_FUN_UNUSED5 5 +#define GPIO18_FUN_I2C_SCL 6 +#define GPIO18_FUN_UART_SIG2 7 +#define GPIO18_FUN_PWM_CH3 8 +#define GPIO18_FUN_FEM_GPIO_2 9 +#define GPIO18_FUN_UNUSED10 10 +#define GPIO18_FUN_SWGPIO_18 11 +#define GPIO18_FUN_E21_TCK 14 +/* GPIO19 function definition */ +#define GPIO19_FUN_UNUSED1 1 +#define GPIO19_FUN_SF_D1 2 +#define GPIO19_FUN_UNUSED3 3 +#define GPIO19_FUN_SPI_SCLK 4 +#define GPIO19_FUN_UNUSED5 5 +#define GPIO19_FUN_I2C_SDA 6 +#define GPIO19_FUN_UART_SIG3 7 +#define GPIO19_FUN_PWM_CH4 8 +#define GPIO19_FUN_FEM_GPIO_3 9 +#define GPIO19_FUN_UNUSED10 10 +#define GPIO19_FUN_SWGPIO_19 11 +#define GPIO19_FUN_E21_TDO 14 +/* GPIO20 function definition */ +#define GPIO20_FUN_UNUSED1 1 +#define GPIO20_FUN_SF_D0 2 +#define GPIO20_FUN_UNUSED3 3 +#define GPIO20_FUN_SPI_MISO_SPI_MOSI 4 +#define GPIO20_FUN_UNUSED5 5 +#define GPIO20_FUN_I2C_SCL 6 +#define GPIO20_FUN_UART_SIG4 7 +#define GPIO20_FUN_PWM_CH0 8 +#define GPIO20_FUN_FEM_GPIO_0 9 +#define GPIO20_FUN_UNUSED10 10 +#define GPIO20_FUN_SWGPIO_20 11 +#define GPIO20_FUN_E21_TMS 14 +/* GPIO21 function definition */ +#define GPIO21_FUN_UNUSED1 1 +#define GPIO21_FUN_SF_CS 2 +#define GPIO21_FUN_UNUSED3 3 +#define GPIO21_FUN_SPI_MOSI_SPI_MISO 4 +#define GPIO21_FUN_UNUSED5 5 +#define GPIO21_FUN_I2C_SDA 6 +#define GPIO21_FUN_UART_SIG5 7 +#define GPIO21_FUN_PWM_CH1 8 +#define GPIO21_FUN_FEM_GPIO_1 9 +#define GPIO21_FUN_UNUSED10 10 +#define GPIO21_FUN_SWGPIO_21 11 +#define GPIO21_FUN_E21_TDI 14 +/* GPIO22 function definition */ +#define GPIO22_FUN_UNUSED1 1 +#define GPIO22_FUN_SF_CLK_OUT 2 +#define GPIO22_FUN_UNUSED3 3 +#define GPIO22_FUN_SPI_SS 4 +#define GPIO22_FUN_UNUSED5 5 +#define GPIO22_FUN_I2C_SCL 6 +#define GPIO22_FUN_UART_SIG6 7 +#define GPIO22_FUN_PWM_CH2 8 +#define GPIO22_FUN_FEM_GPIO_2 9 +#define GPIO22_FUN_UNUSED10 10 +#define GPIO22_FUN_SWGPIO_22 11 +#define GPIO22_FUN_E21_TCK 14 + +#endif /*__BL602_GPIO_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_hbn.h b/drivers/bl602_driver/std_drv/inc/bl602_hbn.h new file mode 100644 index 00000000..ca9b8041 --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_hbn.h @@ -0,0 +1,495 @@ +/** + ****************************************************************************** + * @file bl602_hbn.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_HBN_H__ +#define __BL602_HBN_H__ + +#include "hbn_reg.h" +#include "bl602_aon.h" +#include "bl602_sflash.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup HBN + * @{ + */ + +/** @defgroup HBN_Public_Types + * @{ + */ + +/** + * @brief HBN PIR interrupt configuration type definition + */ +typedef struct { + BL_Fun_Type lowIntEn; /*!< Low will trigger interrupt */ + BL_Fun_Type highIntEn; /*!< High will trigger interrupt */ +}HBN_PIR_INT_CFG_Type; + +/** + * @brief HBN PIR low pass filter type definition + */ +typedef enum { + HBN_PIR_LPF_DIV1, /*!< HBN PIR lpf div 1 */ + HBN_PIR_LPF_DIV2, /*!< HBN PIR lpf div 2 */ +}HBN_PIR_LPF_Type; + +/** + * @brief HBN PIR high pass filter type definition + */ +typedef enum { + HBN_PIR_HPF_METHOD0, /*!< HBN PIR hpf calc method 0, 1-z^-1 */ + HBN_PIR_HPF_METHOD1, /*!< HBN PIR hpf calc method 1, 1-z^-2 */ + HBN_PIR_HPF_METHOD2, /*!< HBN PIR hpf calc method 2, 1-z^-3 */ +}HBN_PIR_HPF_Type; + +/** + * @brief HBN BOR threshold type definition + */ +typedef enum { + HBN_BOR_THRES_2P0V, /*!< BOR threshold 2.0V */ + HBN_BOR_THRES_2P4V, /*!< BOR threshold 2.4V */ +}HBN_BOR_THRES_Type; + +/** + * @brief HBN BOR mode type definition + */ +typedef enum { + HBN_BOR_MODE_POR_INDEPENDENT, /*!< POR is independent of BOR */ + HBN_BOR_MODE_POR_RELEVANT, /*!< POR is relevant to BOR */ +}HBN_BOR_MODE_Type; + +/** + * @brief HBN 32K clock type definition + */ +typedef enum { + HBN_32K_RC=0, /*!< HBN use rc 32k */ + HBN_32K_XTAL, /*!< HBN use xtal 32k */ + HBN_32K_DIG=3, /*!< HBN use dig 32k */ +}HBN_32K_CLK_Type; + +/** + * @brief HBN xclk clock type definition + */ +typedef enum { + HBN_XCLK_CLK_RC32M, /*!< use RC32M as xclk clock */ + HBN_XCLK_CLK_XTAL, /*!< use XTAL as xclk clock */ +}HBN_XCLK_CLK_Type; + +/** + * @brief HBN root clock type definition + */ +typedef enum { + HBN_ROOT_CLK_RC32M, /*!< use RC32M as root clock */ + HBN_ROOT_CLK_XTAL, /*!< use XTAL as root clock */ + HBN_ROOT_CLK_PLL, /*!< use PLL as root clock */ +}HBN_ROOT_CLK_Type; + +/** + * @brief HBN UART clock type definition + */ +typedef enum { + HBN_UART_CLK_FCLK=0, /*!< Select FCLK as UART clock */ + HBN_UART_CLK_160M, /*!< Select 160M as UART clock */ +}HBN_UART_CLK_Type; + +/** + * @brief HBN RTC interrupt delay type definition + */ +typedef enum { + HBN_RTC_INT_DELAY_32T=0, /*!< HBN RTC interrupt delay 32T */ + HBN_RTC_INT_DELAY_0T=1, /*!< HBN RTC interrupt delay 0T */ +}HBN_RTC_INT_Delay_Type; + +/** + * @brief HBN interrupt type definition + */ +typedef enum { + HBN_INT_GPIO7=0, /*!< HBN interrupt type: GPIO7 */ + HBN_INT_GPIO8=1, /*!< HBN interrupt type: GPIO8 */ + HBN_INT_RTC=16, /*!< HBN interrupt type: RTC */ + HBN_INT_PIR=17, /*!< HBN interrupt type: PIR */ + HBN_INT_BOR=18, /*!< HBN interrupt type: BOR */ + HBN_INT_ACOMP0=20, /*!< HBN interrupt type: ACOMP0 */ + HBN_INT_ACOMP1=22, /*!< HBN interrupt type: ACOMP1 */ +}HBN_INT_Type; + +/** + * @brief HBN acomp interrupt type definition + */ +typedef enum { + HBN_ACOMP_INT_EDGE_POSEDGE=0, /*!< HBN acomp interrupt edge posedge */ + HBN_ACOMP_INT_EDGE_NEGEDGE=1, /*!< HBN acomp interrupt edge negedge */ +}HBN_ACOMP_INT_EDGE_Type; + +/** + * @brief HBN GPIO interrupt trigger type definition + */ +typedef enum { + HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE, /*!< HBN GPIO INT trigger type: sync falling edge trigger */ + HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE, /*!< HBN GPIO INT trigger type: sync rising edge trigger */ + HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL, /*!< HBN GPIO INT trigger type: sync low level trigger */ + HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL, /*!< HBN GPIO INT trigger type: sync high level trigger */ + HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE, /*!< HBN GPIO INT trigger type: async falling edge trigger */ + HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE, /*!< HBN GPIO INT trigger type: async rising edge trigger */ + HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL, /*!< HBN GPIO INT trigger type: async low level trigger */ + HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL, /*!< HBN GPIO INT trigger type: async high level trigger */ +}HBN_GPIO_INT_Trigger_Type; + +/** + * @brief HBN OUT0 interrupt type definition + */ +typedef enum { + HBN_OUT0_INT_GPIO7=0, /*!< HBN out 0 interrupt type: GPIO7 */ + HBN_OUT0_INT_GPIO8, /*!< HBN out 0 interrupt type: GPIO8 */ + HBN_OUT0_INT_RTC, /*!< HBN out 0 interrupt type: RTC */ +}HBN_OUT0_INT_Type; + +/** + * @brief HBN OUT0 interrupt type definition + */ +typedef enum { + HBN_OUT1_INT_PIR, /*!< HBN out 1 interrupt type: PIR */ + HBN_OUT1_INT_BOR, /*!< HBN out 1 interrupt type: BOR */ + HBN_OUT1_INT_ACOMP0, /*!< HBN out 1 interrupt type: ACOMP0 */ + HBN_OUT1_INT_ACOMP1, /*!< HBN out 1 interrupt type: ACOMP1 */ +}HBN_OUT1_INT_Type; + +/** + * @brief HBN LDO level type definition + */ +typedef enum { + HBN_LDO_LEVEL_0P60V=0, /*!< HBN LDO voltage 0.60V */ + HBN_LDO_LEVEL_0P65V=1, /*!< HBN LDO voltage 0.65V */ + HBN_LDO_LEVEL_0P70V=2, /*!< HBN LDO voltage 0.70V */ + HBN_LDO_LEVEL_0P75V=3, /*!< HBN LDO voltage 0.75V */ + HBN_LDO_LEVEL_0P80V=4, /*!< HBN LDO voltage 0.80V */ + HBN_LDO_LEVEL_0P85V=5, /*!< HBN LDO voltage 0.85V */ + HBN_LDO_LEVEL_0P90V=6, /*!< HBN LDO voltage 0.90V */ + HBN_LDO_LEVEL_0P95V=7, /*!< HBN LDO voltage 0.95V */ + HBN_LDO_LEVEL_1P00V=8, /*!< HBN LDO voltage 1.00V */ + HBN_LDO_LEVEL_1P05V=9, /*!< HBN LDO voltage 1.05V */ + HBN_LDO_LEVEL_1P10V=10, /*!< HBN LDO voltage 1.10V */ + HBN_LDO_LEVEL_1P15V=11, /*!< HBN LDO voltage 1.15V */ + HBN_LDO_LEVEL_1P20V=12, /*!< HBN LDO voltage 1.20V */ + HBN_LDO_LEVEL_1P25V=13, /*!< HBN LDO voltage 1.25V */ + HBN_LDO_LEVEL_1P30V=14, /*!< HBN LDO voltage 1.30V */ + HBN_LDO_LEVEL_1P35V=15, /*!< HBN LDO voltage 1.35V */ +}HBN_LDO_LEVEL_Type; + +/** + * @brief HBN level type definition + */ +typedef enum { + HBN_LEVEL_0, /*!< HBN pd_core */ + HBN_LEVEL_1, /*!< HBN pd_aon_hbncore + pd_core */ + HBN_LEVEL_2, /*!< HBN pd_aon_hbnrtc + pd_aon_hbncore + pd_core */ + HBN_LEVEL_3, /*!< HBN pd_aon_hbnrtc + pd_aon_hbncore + pd_core */ +}HBN_LEVEL_Type; + +/** + * @brief HBN BOR configuration type definition + */ +typedef struct { + uint8_t enableBor; /*!< Enable BOR or not */ + uint8_t enableBorInt; /*!< Enable BOR interrupt or not */ + uint8_t borThreshold; /*!< BOR threshold */ + uint8_t enablePorInBor; /*!< Enable POR when BOR occure or not */ +}HBN_BOR_CFG_Type; + +/** + * @brief HBN APP configuration type definition + */ +typedef struct { + uint8_t useXtal32k; /*!< Whether use xtal 32K as 32K clock source,otherwise use rc32k */ + uint32_t sleepTime; /*!< HBN sleep time */ + uint8_t gpioWakeupSrc; /*!< GPIO Wakeup source */ + HBN_GPIO_INT_Trigger_Type gpioTrigType; /*!< GPIO Triger type */ + SPI_Flash_Cfg_Type *flashCfg; /*!< Flash config pointer, used when power down flash */ + HBN_LEVEL_Type hbnLevel; /*!< HBN level */ + HBN_LDO_LEVEL_Type ldoLevel; /*!< LDO level */ +}HBN_APP_CFG_Type; + +/*@} end of group HBN_Public_Types */ + +/** @defgroup HBN_Public_Constants + * @{ + */ + +/** @defgroup HBN_PIR_LPF_TYPE + * @{ + */ +#define IS_HBN_PIR_LPF_TYPE(type) (((type) == HBN_PIR_LPF_DIV1) || \ + ((type) == HBN_PIR_LPF_DIV2)) + +/** @defgroup HBN_PIR_HPF_TYPE + * @{ + */ +#define IS_HBN_PIR_HPF_TYPE(type) (((type) == HBN_PIR_HPF_METHOD0) || \ + ((type) == HBN_PIR_HPF_METHOD1) || \ + ((type) == HBN_PIR_HPF_METHOD2)) + +/** @defgroup HBN_BOR_THRES_TYPE + * @{ + */ +#define IS_HBN_BOR_THRES_TYPE(type) (((type) == HBN_BOR_THRES_2P0V) || \ + ((type) == HBN_BOR_THRES_2P4V)) + +/** @defgroup HBN_BOR_MODE_TYPE + * @{ + */ +#define IS_HBN_BOR_MODE_TYPE(type) (((type) == HBN_BOR_MODE_POR_INDEPENDENT) || \ + ((type) == HBN_BOR_MODE_POR_RELEVANT)) + +/** @defgroup HBN_32K_CLK_TYPE + * @{ + */ +#define IS_HBN_32K_CLK_TYPE(type) (((type) == HBN_32K_RC) || \ + ((type) == HBN_32K_XTAL) || \ + ((type) == HBN_32K_DIG)) + +/** @defgroup HBN_XCLK_CLK_TYPE + * @{ + */ +#define IS_HBN_XCLK_CLK_TYPE(type) (((type) == HBN_XCLK_CLK_RC32M) || \ + ((type) == HBN_XCLK_CLK_XTAL)) + +/** @defgroup HBN_ROOT_CLK_TYPE + * @{ + */ +#define IS_HBN_ROOT_CLK_TYPE(type) (((type) == HBN_ROOT_CLK_RC32M) || \ + ((type) == HBN_ROOT_CLK_XTAL) || \ + ((type) == HBN_ROOT_CLK_PLL)) + +/** @defgroup HBN_UART_CLK_TYPE + * @{ + */ +#define IS_HBN_UART_CLK_TYPE(type) (((type) == HBN_UART_CLK_FCLK) || \ + ((type) == HBN_UART_CLK_160M)) + +/** @defgroup HBN_RTC_INT_DELAY_TYPE + * @{ + */ +#define IS_HBN_RTC_INT_DELAY_TYPE(type) (((type) == HBN_RTC_INT_DELAY_32T) || \ + ((type) == HBN_RTC_INT_DELAY_0T)) + +/** @defgroup HBN_INT_TYPE + * @{ + */ +#define IS_HBN_INT_TYPE(type) (((type) == HBN_INT_GPIO7) || \ + ((type) == HBN_INT_GPIO8) || \ + ((type) == HBN_INT_RTC) || \ + ((type) == HBN_INT_PIR) || \ + ((type) == HBN_INT_BOR) || \ + ((type) == HBN_INT_ACOMP0) || \ + ((type) == HBN_INT_ACOMP1)) + +/** @defgroup HBN_ACOMP_INT_EDGE_TYPE + * @{ + */ +#define IS_HBN_ACOMP_INT_EDGE_TYPE(type) (((type) == HBN_ACOMP_INT_EDGE_POSEDGE) || \ + ((type) == HBN_ACOMP_INT_EDGE_NEGEDGE)) + +/** @defgroup HBN_GPIO_INT_TRIGGER_TYPE + * @{ + */ +#define IS_HBN_GPIO_INT_TRIGGER_TYPE(type) (((type) == HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) || \ + ((type) == HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) || \ + ((type) == HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) || \ + ((type) == HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) || \ + ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \ + ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) || \ + ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) || \ + ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL)) + +/** @defgroup HBN_OUT0_INT_TYPE + * @{ + */ +#define IS_HBN_OUT0_INT_TYPE(type) (((type) == HBN_OUT0_INT_GPIO7) || \ + ((type) == HBN_OUT0_INT_GPIO8) || \ + ((type) == HBN_OUT0_INT_RTC)) + +/** @defgroup HBN_OUT1_INT_TYPE + * @{ + */ +#define IS_HBN_OUT1_INT_TYPE(type) (((type) == HBN_OUT1_INT_PIR) || \ + ((type) == HBN_OUT1_INT_BOR) || \ + ((type) == HBN_OUT1_INT_ACOMP0) || \ + ((type) == HBN_OUT1_INT_ACOMP1)) + +/** @defgroup HBN_LDO_LEVEL_TYPE + * @{ + */ +#define IS_HBN_LDO_LEVEL_TYPE(type) (((type) == HBN_LDO_LEVEL_0P60V) || \ + ((type) == HBN_LDO_LEVEL_0P65V) || \ + ((type) == HBN_LDO_LEVEL_0P70V) || \ + ((type) == HBN_LDO_LEVEL_0P75V) || \ + ((type) == HBN_LDO_LEVEL_0P80V) || \ + ((type) == HBN_LDO_LEVEL_0P85V) || \ + ((type) == HBN_LDO_LEVEL_0P90V) || \ + ((type) == HBN_LDO_LEVEL_0P95V) || \ + ((type) == HBN_LDO_LEVEL_1P00V) || \ + ((type) == HBN_LDO_LEVEL_1P05V) || \ + ((type) == HBN_LDO_LEVEL_1P10V) || \ + ((type) == HBN_LDO_LEVEL_1P15V) || \ + ((type) == HBN_LDO_LEVEL_1P20V) || \ + ((type) == HBN_LDO_LEVEL_1P25V) || \ + ((type) == HBN_LDO_LEVEL_1P30V) || \ + ((type) == HBN_LDO_LEVEL_1P35V)) + +/** @defgroup HBN_LEVEL_TYPE + * @{ + */ +#define IS_HBN_LEVEL_TYPE(type) (((type) == HBN_LEVEL_0) || \ + ((type) == HBN_LEVEL_1) || \ + ((type) == HBN_LEVEL_2) || \ + ((type) == HBN_LEVEL_3)) + +/*@} end of group HBN_Public_Constants */ + +/** @defgroup HBN_Public_Macros + * @{ + */ +#define HBN_RAM_SIZE (4*1024) +#define HBN_RTC_COMP_BIT0_39 0x01 +#define HBN_RTC_COMP_BIT0_23 0x02 +#define HBN_RTC_COMP_BIT13_39 0x04 +#define HBN_STATUS_ENTER_FLAG 0x4e424845 +#define HBN_STATUS_WAKEUP_FLAG 0x4e424857 +#define HBN_WAKEUP_GPIO_NONE 0x00 +#define HBN_WAKEUP_GPIO_7 0x01 +#define HBN_WAKEUP_GPIO_8 0x02 +#define HBN_WAKEUP_GPIO_ALL 0x03 + +/*@} end of group HBN_Public_Macros */ + +/** @defgroup HBN_Public_Functions + * @{ + */ +/*----------*/ +#ifndef BFLB_USE_HAL_DRIVER +void HBN_OUT0_IRQHandler(void); +void HBN_OUT1_IRQHandler(void); +#endif +/*----------*/ +void HBN_Mode_Enter(HBN_APP_CFG_Type *cfg); +void HBN_Mode_Enter_Ext(HBN_APP_CFG_Type *cfg); +void HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg); +void HBN_Enable(uint8_t aGPIOIeCfg,HBN_LDO_LEVEL_Type ldoLevel,HBN_LEVEL_Type hbnLevel); +void HBN_Enable_Ext(uint8_t aGPIOIeCfg,HBN_LDO_LEVEL_Type ldoLevel,HBN_LEVEL_Type hbnLevel); +BL_Err_Type HBN_Reset(void); +BL_Err_Type HBN_App_Reset(uint8_t npXtalType,uint8_t bclkDiv,uint8_t apXtalType,uint8_t fclkDiv); +BL_Err_Type HBN_Disable(void); +/*----------*/ +BL_Err_Type HBN_PIR_Enable(void); +BL_Err_Type HBN_PIR_Disable(void); +BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type* pirIntCfg); +BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf); +BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf); +BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold); +uint16_t HBN_Get_PIR_Threshold(void); +BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval); +uint16_t HBN_Get_PIR_Interval(void); +/*----------*/ +BL_Sts_Type HBN_Get_BOR_OUT_State(void); +BL_Err_Type HBN_Set_BOR_Config(uint8_t enable,HBN_BOR_THRES_Type threshold,HBN_BOR_MODE_Type mode); +/*----------*/ +BL_Err_Type HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel); +BL_Err_Type HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel); +BL_Err_Type HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel); +BL_Err_Type HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel); +/*----------*/ +BL_Err_Type HBN_32K_Sel(HBN_32K_CLK_Type clkType); +BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel); +BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk); +BL_Err_Type HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk); +/*----------*/ +BL_Err_Type HBN_Set_HRAM_slp(void); +BL_Err_Type HBN_Set_HRAM_Ret(void); +/*----------*/ +uint32_t HBN_Get_Status_Flag(void); +BL_Err_Type HBN_Set_Status_Flag(uint32_t flag); +uint32_t HBN_Get_Wakeup_Addr(void); +BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr); +/*----------*/ +BL_Err_Type HBN_Clear_RTC_Counter(void); +BL_Err_Type HBN_Enable_RTC_Counter(void); +BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay,uint32_t compValLow,uint32_t compValHigh,uint8_t compMode); +BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow,uint32_t *valHigh); +BL_Err_Type HBN_Clear_RTC_IRQ(void); +/*----------*/ +BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType); +BL_Err_Type HBN_GPIO_INT_Disable(void); +BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType); +uint8_t HBN_Get_Pin_Wakeup_Mode(void); +BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType); +BL_Err_Type HBN_Hw_Pu_Pd_Cfg(uint8_t enable); +BL_Err_Type HBN_Aon_Pad_IeSmt_Cfg(uint8_t padCfg); +BL_Err_Type HBN_Pin_WakeUp_Mask(uint8_t maskVal); +/*----------*/ +BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge); +BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge); +BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge); +BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge); +/*----------*/ +BL_Err_Type HBN_Enable_BOR_IRQ(void); +BL_Err_Type HBN_Disable_BOR_IRQ(void); +/*----------*/ +BL_Err_Type HBN_Out0_IRQHandler_Install(void); +BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType,intCallback_Type* cbFun); +BL_Err_Type HBN_Out1_IRQHandler_Install(void); +BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType,intCallback_Type* cbFun); +/*----------*/ +BL_Err_Type HBN_GPIO7_Dbg_Pull_Cfg(BL_Fun_Type pupdEn,BL_Fun_Type iesmtEn, + BL_Fun_Type dlyEn,uint8_t dlySec); +/*----------*/ +BL_Err_Type HBN_Power_On_Xtal_32K(void); +BL_Err_Type HBN_Power_Off_Xtal_32K(void); +BL_Err_Type HBN_Power_On_RC32K(void); +BL_Err_Type HBN_Power_Off_RC32K(void); +BL_Err_Type HBN_Trim_RC32K(void); +BL_Err_Type HBN_Set_Embedded_Flash_Pullup(uint8_t enable); +BL_Err_Type HBN_Set_BOR_Cfg(HBN_BOR_CFG_Type *cfg); + +/*@} end of group HBN_Public_Functions */ + +/*@} end of group HBN */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_HBN_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_i2c.h b/drivers/bl602_driver/std_drv/inc/bl602_i2c.h new file mode 100644 index 00000000..949901e3 --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_i2c.h @@ -0,0 +1,193 @@ +/** + ****************************************************************************** + * @file bl602_i2c.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_I2C_H__ +#define __BL602_I2C_H__ + +#include "i2c_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @defgroup I2C_Public_Types + * @{ + */ + +/** + * @brief I2C No. type definition + */ +typedef enum { + I2C0_ID = 0, /*!< I2C0 define */ + I2C_ID_MAX, /*!< I2C max define */ +}I2C_ID_Type; + +/** + * @brief I2C read/write type definition + */ +typedef enum { + I2C_WRITE = 0, /*!< I2C write direction */ + I2C_READ, /*!< I2C read direction */ +}I2C_Direction_Type; + +/** + * @brief I2C interrupt type definition + */ +typedef enum { + I2C_TRANS_END_INT, /*!< I2C transfer end interrupt */ + I2C_TX_FIFO_READY_INT, /*!< I2C TX fifo ready interrupt */ + I2C_RX_FIFO_READY_INT, /*!< I2C RX fifo ready interrupt */ + I2C_NACK_RECV_INT, /*!< I2C nack received interrupt */ + I2C_ARB_LOST_INT, /*!< I2C arbitration lost interrupt */ + I2C_FIFO_ERR_INT, /*!< I2C TX/RX FIFO error interrupt */ + I2C_INT_ALL, /*!< I2C interrupt all type */ +}I2C_INT_Type; + +/** + * @brief I2S start condition phase structure type definition + */ +typedef struct { + uint8_t len0; /*!< Length of START condition phase 0 */ + uint8_t len1; /*!< Length of START condition phase 1 */ + uint8_t len2; /*!< Length of START condition phase 2 */ + uint8_t len3; /*!< Length of START condition phase 3 */ +}I2C_Start_Condition_Phase_Type; + +/** + * @brief I2S stop condition phase structure type definition + */ +typedef struct { + uint8_t len0; /*!< Length of STOP condition phase 0 */ + uint8_t len1; /*!< Length of STOP condition phase 1 */ + uint8_t len2; /*!< Length of STOP condition phase 2 */ + uint8_t len3; /*!< Length of STOP condition phase 3 */ +}I2C_Stop_Condition_Phase_Type; + +/** + * @brief I2S data phase structure type definition + */ +typedef struct { + uint8_t len0; /*!< Length of DATA phase 0 */ + uint8_t len1; /*!< Length of DATA phase 1 */ + uint8_t len2; /*!< Length of DATA phase 2 */ + uint8_t len3; /*!< Length of DATA phase 3 */ +}I2C_Data_Phase_Type; + +/** + * @brief I2S transfer structure type definition + */ +typedef struct { + uint8_t slaveAddr; /*!< I2C slave address */ + BL_Fun_Type stopEveryByte; /*!< I2C all data byte with stop bit */ + uint8_t subAddrSize; /*!< Specifies the size of I2C sub address section */ + uint32_t subAddr; /*!< I2C sub address */ + uint16_t dataSize; /*!< Specifies the size of I2C data section */ + uint8_t* data; /*!< Specifies the pointer of I2C R/W data */ +}I2C_Transfer_Cfg; + +/*@} end of group I2C_Public_Types */ + +/** @defgroup I2C_Public_Constants + * @{ + */ + +/** @defgroup I2C_ID_TYPE + * @{ + */ +#define IS_I2C_ID_TYPE(type) (((type) == I2C0_ID ) || \ + ((type) == I2C_ID_MAX)) + +/** @defgroup I2C_DIRECTION_TYPE + * @{ + */ +#define IS_I2C_DIRECTION_TYPE(type) (((type) == I2C_WRITE ) || \ + ((type) == I2C_READ)) + +/** @defgroup I2C_INT_TYPE + * @{ + */ +#define IS_I2C_INT_TYPE(type) (((type) == I2C_TRANS_END_INT) || \ + ((type) == I2C_TX_FIFO_READY_INT) || \ + ((type) == I2C_RX_FIFO_READY_INT) || \ + ((type) == I2C_NACK_RECV_INT) || \ + ((type) == I2C_ARB_LOST_INT) || \ + ((type) == I2C_FIFO_ERR_INT) || \ + ((type) == I2C_INT_ALL)) + +/*@} end of group I2C_Public_Constants */ + +/** @defgroup I2C_Public_Macros + * @{ + */ + +/*@} end of group I2C_Public_Macros */ + +/** @defgroup I2C_Public_Functions + * @{ + */ + +/** + * @brief I2C Functions + */ +#ifndef BFLB_USE_HAL_DRIVER +void I2C_IRQHandler(void); +void I2C_Int_Callback_Install(I2C_ID_Type i2cNo, I2C_INT_Type intType, intCallback_Type* cbFun); +#endif +void I2C_SendWord(I2C_ID_Type i2cNo, uint32_t data); +uint32_t I2C_RecieveWord(I2C_ID_Type i2cNo); +void I2C_Enable(I2C_ID_Type i2cNo); +void I2C_Disable(I2C_ID_Type i2cNo); +BL_Err_Type I2C_Reset(I2C_ID_Type i2cNo); +void I2C_SetPrd(I2C_ID_Type i2cNo, uint8_t phase); +void I2C_ClockSet(I2C_ID_Type i2cNo, uint32_t clk); +void I2C_SetSclSync(I2C_ID_Type i2cNo, uint8_t enable); +void I2C_Init(I2C_ID_Type i2cNo,I2C_Direction_Type direct,I2C_Transfer_Cfg *cfg); +BL_Sts_Type I2C_IsBusy(I2C_ID_Type i2cNo); +BL_Err_Type I2C_MasterSendBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg); +BL_Err_Type I2C_MasterReceiveBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg); +void I2C_IntMask(I2C_ID_Type i2cNo,I2C_INT_Type intType, BL_Mask_Type intMask); + +/*@} end of group I2C_Public_Functions */ + +/*@} end of group I2C */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_I2C_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_ir.h b/drivers/bl602_driver/std_drv/inc/bl602_ir.h new file mode 100644 index 00000000..4bcd616f --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_ir.h @@ -0,0 +1,253 @@ +/** + ****************************************************************************** + * @file bl602_ir.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_IR_H__ +#define __BL602_IR_H__ + +#include "ir_reg.h" +#include "bl602_common.h" +#include "bl602_hbn.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup IR + * @{ + */ + +/** @defgroup IR_Public_Types + * @{ + */ + +/** + * @brief IR direction type definition + */ +typedef enum { + IR_TX, /*!< IR TX direction */ + IR_RX, /*!< IR RX direction */ + IR_TXRX, /*!< IR TX and RX direction */ +}IR_Direction_Type; + +/** + * @brief IR word type definition + */ +typedef enum { + IR_WORD_0, /*!< IR data word 0 */ + IR_WORD_1, /*!< IR data word 1 */ +}IR_Word_Type; + +/** + * @brief IR RX mode type definition + */ +typedef enum { + IR_RX_NEC, /*!< IR RX NEC mode */ + IR_RX_RC5, /*!< IR RX RC5 mode */ + IR_RX_SWM, /*!< IR RX software pulse-width detection mode */ +}IR_RxMode_Type; + +/** + * @brief IR interrupt type definition + */ +typedef enum { + IR_INT_TX, /*!< IR TX transfer end interrupt */ + IR_INT_RX, /*!< IR RX transfer end interrupt */ + IR_INT_ALL, /*!< IR all interrupt */ +}IR_INT_Type; + +/** + * @brief IR fifo underflow or overflow type definition + */ +typedef enum { + IR_RX_FIFO_UNDERFLOW, /*!< Underflow flag of rx fifo */ + IR_RX_FIFO_OVERFLOW, /*!< Overflow flag of rx fifo */ +}IR_FifoStatus_Type; + +/** + * @brief IR TX configuration structure type definition + */ +typedef struct { + uint8_t dataBits; /*!< Bit count of data phase */ + BL_Fun_Type tailPulseInverse; /*!< Enable or disable signal of tail pulse inverse (don't care if SWM is enabled) */ + BL_Fun_Type tailPulse; /*!< Enable or disable signal of tail pulse (don't care if SWM is enabled) */ + BL_Fun_Type headPulseInverse; /*!< Enable or disable signal of head pulse inverse (don't care if SWM is enabled) */ + BL_Fun_Type headPulse; /*!< Enable or disable signal of head pulse (don't care if SWM is enabled) */ + BL_Fun_Type logic1PulseInverse; /*!< Enable or disable signal of logic 1 pulse inverse (don't care if SWM is enabled) */ + BL_Fun_Type logic0PulseInverse; /*!< Enable or disable signal of logic 0 pulse inverse (don't care if SWM is enabled) */ + BL_Fun_Type dataPulse; /*!< Enable or disable signal of data pulse (don't care if SWM is enabled) */ + BL_Fun_Type outputModulation; /*!< Enable or disable signal of output modulation */ + BL_Fun_Type outputInverse; /*!< Enable or disable signal of output inverse,0:output stays at low during idle state,1:stay at high */ +}IR_TxCfg_Type; + +/** + * @brief IR TX pulse width configuration structure type definition + */ +typedef struct { + uint8_t logic0PulseWidth_1; /*!< Pulse width of logic 0 pulse phase 1 (don't care if SWM is enabled) */ + uint8_t logic0PulseWidth_0; /*!< Pulse width of logic 0 pulse phase 0 (don't care if SWM is enabled) */ + uint8_t logic1PulseWidth_1; /*!< Pulse width of logic 1 pulse phase 1 (don't care if SWM is enabled) */ + uint8_t logic1PulseWidth_0; /*!< Pulse width of logic 1 pulse phase 0 (don't care if SWM is enabled) */ + uint8_t headPulseWidth_1; /*!< Pulse width of head pulse phase 1 (don't care if SWM is enabled) */ + uint8_t headPulseWidth_0; /*!< Pulse width of head pulse phase 0 (don't care if SWM is enabled) */ + uint8_t tailPulseWidth_1; /*!< Pulse width of tail pulse phase 1 (don't care if SWM is enabled) */ + uint8_t tailPulseWidth_0; /*!< Pulse width of tail pulse phase 0 (don't care if SWM is enabled) */ + uint8_t moduWidth_1; /*!< Modulation phase 1 width */ + uint8_t moduWidth_0; /*!< Modulation phase 0 width */ + uint16_t pulseWidthUnit; /*!< Pulse width unit */ +}IR_TxPulseWidthCfg_Type; + +/** + * @brief IR TX software mode pulse width(multiples of pulse width unit) configuration structure type definition + */ +typedef struct { + uint32_t swmData0; /*!< SWM pulse width data 0~7,multiples of pulse width unit,each pulse is represented by 4-bit */ + uint32_t swmData1; /*!< SWM pulse width data 8~15,multiples of pulse width unit,each pulse is represented by 4-bit */ + uint32_t swmData2; /*!< SWM pulse width data 16~23,multiples of pulse width unit,each pulse is represented by 4-bit */ + uint32_t swmData3; /*!< SWM pulse width data 24~31,multiples of pulse width unit,each pulse is represented by 4-bit */ + uint32_t swmData4; /*!< SWM pulse width data 32~39,multiples of pulse width unit,each pulse is represented by 4-bit */ + uint32_t swmData5; /*!< SWM pulse width data 40~47,multiples of pulse width unit,each pulse is represented by 4-bit */ + uint32_t swmData6; /*!< SWM pulse width data 48~55,multiples of pulse width unit,each pulse is represented by 4-bit */ + uint32_t swmData7; /*!< SWM pulse width data 56~63,multiples of pulse width unit,each pulse is represented by 4-bit */ +}IR_TxSWMPulseWidthCfg_Type; + +/** + * @brief IR RX configuration structure type definition + */ +typedef struct { + IR_RxMode_Type rxMode; /*!< Set ir rx mode */ + BL_Fun_Type inputInverse; /*!< Enable or disable signal of input inverse */ + uint16_t endThreshold; /*!< Pulse width threshold to trigger end condition */ + uint16_t dataThreshold; /*!< Pulse width threshold for logic 0/1 detection (don't care if SWM is enabled) */ + BL_Fun_Type rxDeglitch; /*!< Enable or disable signal of rx input de-glitch function */ + uint8_t DeglitchCnt; /*!< De-glitch function cycle count */ +}IR_RxCfg_Type; + +/*@} end of group IR_Public_Types */ + +/** @defgroup IR_Public_Constants + * @{ + */ + +/** @defgroup IR_DIRECTION_TYPE + * @{ + */ +#define IS_IR_DIRECTION_TYPE(type) (((type) == IR_TX) || \ + ((type) == IR_RX) || \ + ((type) == IR_TXRX)) + +/** @defgroup IR_WORD_TYPE + * @{ + */ +#define IS_IR_WORD_TYPE(type) (((type) == IR_WORD_0) || \ + ((type) == IR_WORD_1)) + +/** @defgroup IR_RXMODE_TYPE + * @{ + */ +#define IS_IR_RXMODE_TYPE(type) (((type) == IR_RX_NEC) || \ + ((type) == IR_RX_RC5) || \ + ((type) == IR_RX_SWM)) + +/** @defgroup IR_INT_TYPE + * @{ + */ +#define IS_IR_INT_TYPE(type) (((type) == IR_INT_TX) || \ + ((type) == IR_INT_RX) || \ + ((type) == IR_INT_ALL)) + +/** @defgroup IR_FIFOSTATUS_TYPE + * @{ + */ +#define IS_IR_FIFOSTATUS_TYPE(type) (((type) == IR_RX_FIFO_UNDERFLOW) || \ + ((type) == IR_RX_FIFO_OVERFLOW)) + +/*@} end of group IR_Public_Constants */ + +/** @defgroup IR_Public_Macros + * @{ + */ +#define IR_RX_FIFO_SIZE 64 + +/*@} end of group IR_Public_Macros */ + +/** @defgroup IR_Public_Functions + * @{ + */ + +/** + * @brief IR Functions + */ +#ifndef BFLB_USE_HAL_DRIVER +void IRRX_IRQHandler(void); +void IRTX_IRQHandler(void); +#endif +BL_Err_Type IR_TxInit(IR_TxCfg_Type *irTxCfg); +BL_Err_Type IR_TxPulseWidthConfig(IR_TxPulseWidthCfg_Type *irTxPulseWidthCfg); +BL_Err_Type IR_TxSWMPulseWidthConfig(IR_TxSWMPulseWidthCfg_Type *irTxSWMPulseWidthCfg); +BL_Err_Type IR_RxInit(IR_RxCfg_Type *irRxCfg); +BL_Err_Type IR_DeInit(void); +BL_Err_Type IR_Enable(IR_Direction_Type direct); +BL_Err_Type IR_Disable(IR_Direction_Type direct); +BL_Err_Type IR_TxSWM(BL_Fun_Type txSWM); +BL_Err_Type IR_RxFIFOClear(void); +BL_Err_Type IR_SendData(IR_Word_Type irWord,uint32_t data); +BL_Err_Type IR_SWMSendData(uint16_t *data,uint8_t length); +BL_Err_Type IR_SendCommand(uint32_t word1,uint32_t word0); +BL_Err_Type IR_SWMSendCommand(uint16_t *data,uint8_t length); +BL_Err_Type IR_SendNEC(uint8_t address,uint8_t command); +BL_Err_Type IR_IntMask(IR_INT_Type intType,BL_Mask_Type intMask); +BL_Err_Type IR_ClrIntStatus(IR_INT_Type intType); +BL_Err_Type IR_Int_Callback_Install(IR_INT_Type intType,intCallback_Type *cbFun); +BL_Sts_Type IR_GetIntStatus(IR_INT_Type intType); +BL_Sts_Type IR_GetRxFIFOStatus(IR_FifoStatus_Type fifoSts); +uint32_t IR_ReceiveData(IR_Word_Type irWord); +uint8_t IR_SWMReceiveData(uint16_t *data,uint8_t length); +BL_Err_Type IR_ReceiveNEC(uint8_t *address,uint8_t *command); +uint8_t IR_GetRxDataBitCount(void); +uint8_t IR_GetRxFIFOCount(void); +IR_RxMode_Type IR_LearnToInit(uint32_t *data,uint8_t *length); +BL_Err_Type IR_LearnToSend(IR_RxMode_Type mode,uint32_t *data,uint8_t length); +uint8_t IR_LearnToReceive(IR_RxMode_Type mode,uint32_t *data); +BL_Sts_Type IR_LEDInit(HBN_XCLK_CLK_Type clk,uint8_t div,uint8_t unit,uint8_t code0H,uint8_t code0L,uint8_t code1H, + uint8_t code1L); +BL_Sts_Type IR_LEDSend(uint32_t data); + +/*@} end of group IR_Public_Functions */ + +/*@} end of group IR */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_IR_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_it.h b/drivers/bl602_driver/std_drv/inc/bl602_it.h new file mode 100644 index 00000000..52ec46be --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_it.h @@ -0,0 +1,51 @@ +#ifndef __BL602_IT_H__ +#define __BL602_IT_H__ + +#include "bl602.h" +#include "bl_common.h" + +/** @addtogroup BL606_Peripheral_Driver + * @{ + */ + +/** @addtogroup COMMON + * @{ + */ + +/** @defgroup COMMON_Public_Types + * @{ + */ + +/*@} end of group COMMON_Public_Types */ + +/** @defgroup COMMON_Public_Constants + * @{ + */ + +/** @defgroup DRIVER_INT_PERIPH + * @{ + */ +#define IS_INT_PERIPH(INT_PERIPH) ((INT_PERIPH) < IRQn_LAST) + +/*@} end of group DRIVER_INT_PERIPH */ + +/** @defgroup DRIVER_INT_MASK + * @{ + */ +#define IS_BL_MASK_TYPE(type) (((type) == MASK) || ((type) == UNMASK)) + +/*@} end of group COMMON_Public_Constants */ + +/*@} end of group DRIVER_Public_Macro */ + +/** @defgroup DRIVER_Public_FunctionDeclaration + * @brief DRIVER functions declaration + * @{ + */ +void Interrupt_Handler_Register(IRQn_Type irq,pFunc interruptFun); + +/*@} end of group DRIVER_COMMON */ + +#endif /* __BL602_COMMON_H__ */ + + diff --git a/drivers/bl602_driver/std_drv/inc/bl602_l1c.h b/drivers/bl602_driver/std_drv/inc/bl602_l1c.h new file mode 100644 index 00000000..a829268a --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_l1c.h @@ -0,0 +1,187 @@ +/** + ****************************************************************************** + * @file bl602_l1c.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_L1C_H__ +#define __BL602_L1C_H__ + +#include "l1c_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup L1C + * @{ + */ + +/** @defgroup L1C_Public_Types + * @{ + */ + +/** + * @brief L1C configuration structure type definition + */ +typedef struct { + BL_Fun_Type wrapDis; /*!< wrap disable */ + BL_Fun_Type bypassEn; /*!< bypass cache enable */ + uint8_t wayDis; /*!< Disable part of cache ways & used as ITCM */ + BL_Fun_Type cntEn; /*!< l1c count enable */ +}L1C_CACHE_Cfg_Type; + +/** + * @brief L1C BMX arb mode type definition + */ +typedef enum { + L1C_BMX_ARB_FIX, /*!< 0->fix */ + L1C_BMX_ARB_ROUND_ROBIN, /*!< 2->round-robin */ + L1C_BMX_ARB_RANDOM, /*!< 3->random */ +}L1C_BMX_ARB_Type; + +/** + * @brief L1C BMX configuration structure type definition + */ +typedef struct { + uint8_t timeoutEn; /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */ + BL_Fun_Type errEn; /*!< Bus error response enable */ + L1C_BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */ +}L1C_BMX_Cfg_Type; + +/** + * @brief L1C BMX bus err type definition + */ +typedef enum { + L1C_BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */ + L1C_BMX_BUS_ERR_ADDR_DECODE, /*!< Bus addr decode error */ +}L1C_BMX_BUS_ERR_Type; + +/** + * @brief L1C BMX bus err interrupt type definition + */ +typedef enum { + L1C_BMX_ERR_INT_ERR, /*!< L1C BMX bus err interrupt */ + L1C_BMX_ERR_INT_ALL, /*!< L1C BMX bus err interrupt max num */ +}L1C_BMX_ERR_INT_Type; + +/** + * @brief L1C BMX time out interrupt type definition + */ +typedef enum { + L1C_BMX_TO_INT_TIMEOUT, /*!< L1C_BMX timeout interrupt */ + L1C_BMX_TO_INT_ALL, /*!< L1C_BMX timeout interrupt max num */ +}L1C_BMX_TO_INT_Type; + +/*@} end of group L1C_Public_Types */ + +/** @defgroup L1C_Public_Constants + * @{ + */ + +/** @defgroup L1C_BMX_ARB_TYPE + * @{ + */ +#define IS_L1C_BMX_ARB_TYPE(type) (((type) == L1C_BMX_ARB_FIX) || \ + ((type) == L1C_BMX_ARB_ROUND_ROBIN) || \ + ((type) == L1C_BMX_ARB_RANDOM)) + +/** @defgroup L1C_BMX_BUS_ERR_TYPE + * @{ + */ +#define IS_L1C_BMX_BUS_ERR_TYPE(type) (((type) == L1C_BMX_BUS_ERR_TRUSTZONE_DECODE) || \ + ((type) == L1C_BMX_BUS_ERR_ADDR_DECODE)) + +/** @defgroup L1C_BMX_ERR_INT_TYPE + * @{ + */ +#define IS_L1C_BMX_ERR_INT_TYPE(type) (((type) == L1C_BMX_ERR_INT_ERR) || \ + ((type) == L1C_BMX_ERR_INT_ALL)) + +/** @defgroup L1C_BMX_TO_INT_TYPE + * @{ + */ +#define IS_L1C_BMX_TO_INT_TYPE(type) (((type) == L1C_BMX_TO_INT_TIMEOUT) || \ + ((type) == L1C_BMX_TO_INT_ALL)) + +/*@} end of group L1C_Public_Constants */ + +/** @defgroup L1C_Public_Macros + * @{ + */ +#if 1 +/*NP config address */ +#define L1C_CONF_REG_NP (L1C_BASE+0x00) +#define L1C_HIT_CNT_LSB_REG_NP (L1C_BASE+0x04) +#define L1C_HIT_CNT_MSB_REG_NP (L1C_BASE+0x08) +#define L1C_MISS_CNT_REG_NP (L1C_BASE+0x0C) +/* Get miss and hit count */ +#define L1C_Get_Miss_Cnt_NP() BL602_REG_RD(L1C_MISS_CNT_REG_NP) +#define L1C_Get_Hit_Cnt_LSB_NP() BL602_REG_RD(L1C_HIT_CNT_LSB_REG_NP) +#define L1C_Get_Hit_Cnt_MSB_NP() BL602_REG_RD(L1C_HIT_CNT_MSB_REG_NP) +#endif + +/*@} end of group L1C_Public_Macros */ + +/** @defgroup L1C_Public_Functions + * @{ + */ +/*----------*/ +#ifndef BFLB_USE_HAL_DRIVER +void L1C_BMX_ERR_IRQHandler(void); +void L1C_BMX_TO_IRQHandler(void); +#endif +/*----------*/ +BL_Err_Type L1C_Set_Wrap(BL_Fun_Type wrap); +BL_Err_Type L1C_Set_Way_Disable(uint8_t disableVal); +BL_Err_Type L1C_IROM_2T_Access_Set(uint8_t enable); +/*----------*/ +BL_Err_Type L1C_BMX_Init(L1C_BMX_Cfg_Type *l1cBmxCfg); +BL_Err_Type L1C_BMX_Addr_Monitor_Enable(void); +BL_Err_Type L1C_BMX_Addr_Monitor_Disable(void); +BL_Err_Type L1C_BMX_BusErrResponse_Enable(void); +BL_Err_Type L1C_BMX_BusErrResponse_Disable(void); +BL_Sts_Type L1C_BMX_Get_Status(L1C_BMX_BUS_ERR_Type errType); +uint32_t L1C_BMX_Get_Err_Addr(void); +BL_Err_Type L1C_BMX_ERR_INT_Callback_Install(L1C_BMX_ERR_INT_Type intType,intCallback_Type* cbFun); +BL_Err_Type L1C_BMX_TIMEOUT_INT_Callback_Install(L1C_BMX_TO_INT_Type intType, + intCallback_Type* cbFun); +/*----------*/; + +/*@} end of group L1C_Public_Functions */ + +/*@} end of group L1C */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_L1C_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_mfg_efuse.h b/drivers/bl602_driver/std_drv/inc/bl602_mfg_efuse.h new file mode 100644 index 00000000..def78ec7 --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_mfg_efuse.h @@ -0,0 +1,24 @@ +#ifndef __BL602_MFG_EFUSE_H__ +#define __BL602_MFG_EFUSE_H__ + +#include "stdint.h" + +uint8_t mfg_efuse_get_rf_cal_slots(void); +void mfg_efuse_set_rf_cal_slots(uint8_t slots); +uint8_t mfg_efuse_is_xtal_capcode_slot_empty(uint8_t reload); +int8_t mfg_efuse_write_xtal_capcode_pre(uint8_t capcode,uint8_t program); +void mfg_efuse_write_xtal_capcode(void); +int8_t mfg_efuse_read_xtal_capcode(uint8_t *capcode,uint8_t reload); +uint8_t mfg_efuse_is_poweroffset_slot_empty(uint8_t reload); +int8_t mfg_efuse_write_poweroffset_pre(int8_t pwrOffset[14],uint8_t program); +void mfg_efuse_write_poweroffset(void); +int8_t mfg_efuse_read_poweroffset(int8_t pwrOffset[14],uint8_t reload); +uint8_t mfg_efuse_is_macaddr_slot_empty(uint8_t reload); +int8_t mfg_efuse_write_macaddr_pre(uint8_t mac[6],uint8_t program); +void mfg_efuse_write_macaddr(void); +int8_t mfg_efuse_read_macaddr(uint8_t mac[6],uint8_t reload); +int8_t mfg_efuse_read(uint32_t addr,uint32_t *data,uint32_t countInword,uint8_t reload); +int8_t mfg_efuse_program(void); +int8_t mfg_efuse_write_pre(uint32_t addr,uint32_t *data,uint32_t countInword); + +#endif/*__MFG_GPIO_API_H__*/ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_pds.h b/drivers/bl602_driver/std_drv/inc/bl602_pds.h new file mode 100644 index 00000000..a9e8ae4e --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_pds.h @@ -0,0 +1,495 @@ +/** + ****************************************************************************** + * @file bl602_pds.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_PDS_H__ +#define __BL602_PDS_H__ + +#include "pds_reg.h" +#include "bl602_ef_ctrl.h" +#include "bl602_aon.h" +#include "bl602_hbn.h" +#include "bl602_sflash.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup PDS + * @{ + */ + +/** @defgroup PDS_Public_Types + * @{ + */ + +/** + * @brief PDS LDO level type definition + */ +typedef enum { + PDS_LDO_LEVEL_0P60V=0, /*!< PDS LDO voltage 0.60V */ + PDS_LDO_LEVEL_0P65V=1, /*!< PDS LDO voltage 0.65V */ + PDS_LDO_LEVEL_0P70V=2, /*!< PDS LDO voltage 0.70V */ + PDS_LDO_LEVEL_0P75V=3, /*!< PDS LDO voltage 0.75V */ + PDS_LDO_LEVEL_0P80V=4, /*!< PDS LDO voltage 0.80V */ + PDS_LDO_LEVEL_0P85V=5, /*!< PDS LDO voltage 0.85V */ + PDS_LDO_LEVEL_0P90V=6, /*!< PDS LDO voltage 0.90V */ + PDS_LDO_LEVEL_0P95V=7, /*!< PDS LDO voltage 0.95V */ + PDS_LDO_LEVEL_1P00V=8, /*!< PDS LDO voltage 1.00V */ + PDS_LDO_LEVEL_1P05V=9, /*!< PDS LDO voltage 1.05V */ + PDS_LDO_LEVEL_1P10V=10, /*!< PDS LDO voltage 1.10V */ + PDS_LDO_LEVEL_1P15V=11, /*!< PDS LDO voltage 1.15V */ + PDS_LDO_LEVEL_1P20V=12, /*!< PDS LDO voltage 1.20V */ + PDS_LDO_LEVEL_1P25V=13, /*!< PDS LDO voltage 1.25V */ + PDS_LDO_LEVEL_1P30V=14, /*!< PDS LDO voltage 1.30V */ + PDS_LDO_LEVEL_1P35V=15, /*!< PDS LDO voltage 1.35V */ +}PDS_LDO_LEVEL_Type; + +/** + * @brief PDS configuration type definition + */ +typedef struct { + uint32_t pdsStart : 1; /*!< [0]PDS Start */ + uint32_t sleepForever : 1; /*!< [1]PDS sleep forever */ + uint32_t xtalForceOff : 1; /*!< [2]Power off xtal force */ + uint32_t saveWiFiState : 1; /*!< [3]Save WIFI State Before Enter PDS */ + uint32_t dcdc18Off : 1; /*!< [4]power down dcdc18 during PDS */ + uint32_t bgSysOff : 1; /*!< [5]power down bg_sys during PDS */ + uint32_t rsv6_7 : 2; /*!< [7:6]reserve */ + uint32_t clkOff : 1; /*!< [8]gate clock during PDS (each pwr domain has its own control) */ + uint32_t memStby : 1; /*!< [9]mem_stby during PDS (each power domain can has its own control) */ + uint32_t rsv10 : 1; /*!< [10]reserve */ + uint32_t isolation : 1; /*!< [11]Isolation during PDS (each power domain can has its own control) */ + uint32_t waitXtalRdy : 1; /*!< [12]wait XTAL Ready during before PDS Interrupt */ + uint32_t pdsPwrOff : 1; /*!< [13]Power off during PDS (each power domain can has its own control) */ + uint32_t xtalOff : 1; /*!< [14]xtal power down during PDS */ + uint32_t socEnbForceOn : 1; /*!< [15]pds_soc_enb always active */ + uint32_t pdsRstSocEn : 1; /*!< [16]pds_rst controlled by PDS */ + uint32_t pdsRC32mOn : 1; /*!< [17]RC32M always on or RC32M on/off controlled by PDS state */ + uint32_t pdsLdoVselEn : 1; /*!< [18]PDS "SLEEP" control LDO voltage enable */ + uint32_t rsv19_20 : 2; /*!< [20:19]reserve */ + uint32_t wfiMask : 1; /*!< [21]pds start condition mask np_wfi */ + uint32_t ldo11Off : 1; /*!< [22]power down ldo11 during PDS */ + uint32_t rsv23 : 1; /*!< [23]reserve */ + uint32_t pdsLdoVol : 4; /*!< [27:24]LDO voltage value in PDS mode */ + uint32_t pdsCtlRfSel : 2; /*!< [29:28]select the way RF controlled by PDS */ + uint32_t pdsCtlPllSel : 2; /*!< [31:30]select the way PLL controlled by PDS */ +}PDS_CTL_Type; + +/** + * @brief PDS force configuration type definition + */ +typedef struct { + uint32_t cpuPwrOff : 1; /*!< [0] */ + uint32_t cpuRst : 1; /*!< [1] */ + uint32_t cpuMemStby : 1; /*!< [2] */ + uint32_t cpuGateClk : 1; /*!< [3] */ + uint32_t rsv4_11 : 8; /*!< [11:4]reserve */ + uint32_t WbPwrOff : 1; /*!< [12] */ + uint32_t WbRst : 1; /*!< [13] */ + uint32_t WbMemStby : 1; /*!< [14] */ + uint32_t WbGateClk : 1; /*!< [15] */ + uint32_t rsv16_23 : 8; /*!< [23:16]reserve */ + uint32_t MiscPwrOff : 1; /*!< [24] */ + uint32_t MiscRst : 1; /*!< [25] */ + uint32_t MiscMemStby : 1; /*!< [26] */ + uint32_t MiscGateClk : 1; /*!< [27] */ + uint32_t rsv28_31 : 4; /*!< [31:28]reserve */ +}PDS_CTL4_Type; + +/** + * @brief PDS interrupt type definition + */ +typedef enum { + PDS_INT_WAKEUP=0, /*!< PDS wakeup interrupt(assert bit while wakeup, include PDS_Timer/...) */ + PDS_INT_HBN_GPIO_IRRX_BLE_WIFI=1, /*!< PDS in interrupt source HBN_Wakeup_Source/All_GPIO_Wakeup/IRRX/BLE_Wakeup_Eveent/WIFI_Wakeup_Event */ + PDS_INT_RF_DONE=2, /*!< PDS RF done interrupt */ + PDS_INT_PLL_DONE=3, /*!< PDS PLL done interrupt */ + PDS_INT_MAX=4, /*!< PDS int max number */ +}PDS_INT_Type; + +/** + * @brief PDS force configuration type definition + */ +typedef struct { + uint32_t forceCpuPwrOff : 1; /*!< [0]manual force NP power off */ + uint32_t rsv1 : 1; /*!< [1]reserve */ + uint32_t forceWbPwrOff : 1; /*!< [2]manual force WB power off */ + uint32_t rsv3 : 1; /*!< [3]reserve */ + uint32_t forceCpuIsoPwrOff : 1; /*!< [4]manual force NP isolation */ + uint32_t rsv5 : 1; /*!< [5]reserve */ + uint32_t forceWbIsoPwrOff : 1; /*!< [6]manual force WB isolation */ + uint32_t rsv7 : 1; /*!< [7]reserve */ + uint32_t forceCpuPdsRst : 1; /*!< [8]manual force NP pds reset */ + uint32_t rsv9 : 1; /*!< [9]reserve */ + uint32_t forceWbPdsRst : 1; /*!< [10]manual force WB pds reset */ + uint32_t rsv11 : 1; /*!< [11]reserve */ + uint32_t forceCpuMemStby : 1; /*!< [12]manual force NP memory sleep */ + uint32_t rsv13 : 1; /*!< [13]reserve */ + uint32_t forceWbMemStby : 1; /*!< [14]manual force WB memory sleep */ + uint32_t rsv15 : 1; /*!< [15]reserve */ + uint32_t forceCpuGateClk : 1; /*!< [16]manual force NP clock gated */ + uint32_t rsv17 : 1; /*!< [17]reserve */ + uint32_t forceWbGateClk : 1; /*!< [18]manual force WB clock gated */ + uint32_t rsv19_31 : 12; /*!< [31:19]reserve */ +}PDS_CTL2_Type; + +/** + * @brief PDS force configuration type definition + */ +typedef struct { + uint32_t rsv0 : 1; /*!< [0]reserve */ + uint32_t forceMiscPwrOff : 1; /*!< [1]manual force MISC pwr_off */ + uint32_t rsv2_3 : 2; /*!< [3:2]reserve */ + uint32_t forceMiscIsoEn : 1; /*!< [4]manual force MISC iso_en */ + uint32_t rsv5_6 : 2; /*!< [6:5]reserve */ + uint32_t forceMiscPdsRst : 1; /*!< [7]manual force MISC pds_rst */ + uint32_t rsv8_9 : 2; /*!< [9:8]reserve */ + uint32_t forceMiscMemStby : 1; /*!< [10]manual force MISC mem_stby */ + uint32_t rsv11_12 : 2; /*!< [12:11]reserve */ + uint32_t forceMiscGateClk : 1; /*!< [13]manual force MISC gate_clk */ + uint32_t rsv14_23 : 10; /*!< [23:14]reserve */ + uint32_t CpuIsoEn : 1; /*!< [24]make NP isolated at PDS Sleep state */ + uint32_t rsv25_26 : 2; /*!< [26:25]reserve */ + uint32_t WbIsoEn : 1; /*!< [27]make WB isolated at PDS Sleep state */ + uint32_t rsv28_29 : 2; /*!< [29:28]reserve */ + uint32_t MiscIsoEn : 1; /*!< [30]make misc isolated at PDS Sleep state */ + uint32_t rsv31 : 1; /*!< [31]reserve */ +}PDS_CTL3_Type; + +/** + * @brief PDS default level configuration type definition + */ +typedef struct { + PDS_CTL_Type pdsCtl; /*!< PDS_CTL configuration */ + PDS_CTL2_Type pdsCtl2; /*!< PDS_CTL2 configuration */ + PDS_CTL3_Type pdsCtl3; /*!< PDS_CTL3 configuration */ + PDS_CTL4_Type pdsCtl4; /*!< PDS_CTL4 configuration */ +}PDS_DEFAULT_LV_CFG_Type; + +/** + * @brief PDS PLL status type definition + */ +typedef enum { + PDS_PLL_STS_OFF=0, /*!< 2'b00 */ + PDS_PLL_STS_SFREG=1, /*!< 2'b01 */ + PDS_PLL_STS_PU=2, /*!< 2'b10 */ + PDS_PLL_STS_RDY=3, /*!< 2'b11 */ +}PDS_PLL_STS_Type; + +/** + * @brief PDS RF status type definition + */ +typedef enum { + PDS_RF_STS_OFF=0, /*!< 4'b0000 */ + PDS_RF_STS_PU_MBG=1, /*!< 4'b0001 */ + PDS_RF_STS_PU_LDO15RF=3, /*!< 4'b0011 */ + PDS_RF_STS_PU_SFREG=7, /*!< 4'b0111 */ + PDS_RF_STS_WB_EN_AON=15, /*!< 4'b1111 */ +}PDS_RF_STS_Type; + +/** + * @brief PDS status type definition + */ +typedef enum { + PDS_STS_IDLE=0, /*!< 4'b0000 */ + PDS_STS_ECG=8, /*!< 4'b1000 */ + PDS_STS_ERST=12, /*!< 4'b1100 */ + PDS_STS_EISO=15, /*!< 4'b1111 */ + PDS_STS_POFF=7, /*!< 4'b0111 */ + PDS_STS_PRE_BGON=3, /*!< 4'b0011 */ + PDS_STS_PRE_BGON1=1, /*!< 4'b0001 */ + PDS_STS_BGON=5, /*!< 4'b0101 */ + PDS_STS_CLK_SW_32M=4, /*!< 4'b0100 */ + PDS_STS_PON_DCDC=6, /*!< 4'b0110 */ + PDS_STS_PON_LDO11_MISC=14, /*!< 4'b1110 */ + PDS_STS_PON=10, /*!< 4'b1010 */ + PDS_STS_DISO=2, /*!< 4'b0010 */ + PDS_STS_DCG=13, /*!< 4'b1101 */ + PDS_STS_DRST=11, /*!< 4'b1011 */ + PDS_STS_WAIT_EFUSE=9, /*!< 4'b1001 */ +}PDS_STS_Type; + +/** + * @brief PDS RAM configuration type definition + */ +typedef struct { + uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_RET : 1; /*!< [0] 0~16KB cpu_ram RET */ + uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_RET : 1; /*!< [1] 16~32KB cpu_ram RET */ + uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_RET : 1; /*!< [2] 32~48KB cpu_ram RET */ + uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_RET : 1; /*!< [3] 48~64KB cpu_ram RET */ + uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_SLP : 1; /*!< [4] 0~16KB cpu_ram SLP */ + uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_SLP : 1; /*!< [5] 16~32KB cpu_ram SLP */ + uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_SLP : 1; /*!< [6] 32~48KB cpu_ram SLP */ + uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_SLP : 1; /*!< [7] 48~64KB cpu_ram SLP */ + uint32_t PDS_RAM_CFG_RSV : 24; /*!< [31:8]reserve */ +}PDS_RAM_CFG_Type; + +/** + * @brief PLL XTAL type definition + */ +typedef enum { + PDS_PLL_XTAL_NONE, /*!< XTAL is none */ + PDS_PLL_XTAL_24M, /*!< XTAL is 24M */ + PDS_PLL_XTAL_32M, /*!< XTAL is 32M */ + PDS_PLL_XTAL_38P4M, /*!< XTAL is 38.4M */ + PDS_PLL_XTAL_40M, /*!< XTAL is 40M */ + PDS_PLL_XTAL_26M, /*!< XTAL is 26M */ + PDS_PLL_XTAL_RC32M, /*!< XTAL is RC32M */ +}PDS_PLL_XTAL_Type; + +/** + * @brief PLL output clock type definition + */ +typedef enum { + PDS_PLL_CLK_480M, /*!< PLL output clock:480M */ + PDS_PLL_CLK_240M, /*!< PLL output clock:240M */ + PDS_PLL_CLK_192M, /*!< PLL output clock:192M */ + PDS_PLL_CLK_160M, /*!< PLL output clock:160M */ + PDS_PLL_CLK_120M, /*!< PLL output clock:120M */ + PDS_PLL_CLK_96M, /*!< PLL output clock:96M */ + PDS_PLL_CLK_80M, /*!< PLL output clock:80M */ + PDS_PLL_CLK_48M, /*!< PLL output clock:48M */ + PDS_PLL_CLK_32M, /*!< PLL output clock:32M */ +}PDS_PLL_CLK_Type; + +/** + * @brief PDS level 0/1/2/3 mode HBN GPIO interrupt trigger type definition + */ +typedef enum { + PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync falling edge trigger */ + PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync rising edge trigger */ + PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync low level trigger */ + PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync high level trigger */ + PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async falling edge trigger */ + PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async rising edge trigger */ + PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async low level trigger */ + PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async high level trigger */ +}PDS_AON_GPIO_INT_Trigger_Type; + +/** + * @brief PDS APP configuration type definition + */ +typedef struct { + uint8_t pdsLevel; /*!< PDS level */ + uint8_t turnOffRF; /*!< Wheather turn off RF */ + uint8_t useXtal32k; /*!< Wheather use xtal 32K as 32K clock source,otherwise use rc32k */ + uint8_t pdsAonGpioWakeupSrc; /*!< PDS level 0/1/2/3 mode always on GPIO Wakeup source(HBN wakeup pin) */ + PDS_AON_GPIO_INT_Trigger_Type pdsAonGpioTrigType; /*!< PDS level 0/1/2/3 mode always on GPIO Triger type(HBN wakeup pin) */ + uint8_t powerDownFlash; /*!< Whether power down flash */ + uint8_t turnOffFlashPad; /*!< Whether turn off embedded flash pad */ + uint8_t ocramRetetion; /*!< Whether OCRAM Retention */ + uint8_t turnoffPLL; /*!< Whether trun off PLL */ + uint8_t xtalType; /*!< XTal type, used when user choose turn off PLL, PDS will turn on when exit PDS mode */ + uint8_t flashContRead; /*!< Whether enable flash continue read */ + uint32_t sleepTime; /*!< PDS sleep time */ + SPI_Flash_Cfg_Type *flashCfg; /*!< Flash config pointer, used when power down flash */ + PDS_LDO_LEVEL_Type ldoLevel; /*!< LDO level */ + void (*preCbFun)(void); /*!< Pre callback function */ + void (*postCbFun)(void); /*!< Post callback function */ +}PDS_APP_CFG_Type; + +/*@} end of group PDS_Public_Types */ + +/** @defgroup PDS_Public_Constants + * @{ + */ + +/** @defgroup PDS_LDO_LEVEL_TYPE + * @{ + */ +#define IS_PDS_LDO_LEVEL_TYPE(type) (((type) == PDS_LDO_LEVEL_0P60V) || \ + ((type) == PDS_LDO_LEVEL_0P65V) || \ + ((type) == PDS_LDO_LEVEL_0P70V) || \ + ((type) == PDS_LDO_LEVEL_0P75V) || \ + ((type) == PDS_LDO_LEVEL_0P80V) || \ + ((type) == PDS_LDO_LEVEL_0P85V) || \ + ((type) == PDS_LDO_LEVEL_0P90V) || \ + ((type) == PDS_LDO_LEVEL_0P95V) || \ + ((type) == PDS_LDO_LEVEL_1P00V) || \ + ((type) == PDS_LDO_LEVEL_1P05V) || \ + ((type) == PDS_LDO_LEVEL_1P10V) || \ + ((type) == PDS_LDO_LEVEL_1P15V) || \ + ((type) == PDS_LDO_LEVEL_1P20V) || \ + ((type) == PDS_LDO_LEVEL_1P25V) || \ + ((type) == PDS_LDO_LEVEL_1P30V) || \ + ((type) == PDS_LDO_LEVEL_1P35V)) + +/** @defgroup PDS_INT_TYPE + * @{ + */ +#define IS_PDS_INT_TYPE(type) (((type) == PDS_INT_WAKEUP) || \ + ((type) == PDS_INT_HBN_GPIO_IRRX_BLE_WIFI) || \ + ((type) == PDS_INT_RF_DONE) || \ + ((type) == PDS_INT_PLL_DONE) || \ + ((type) == PDS_INT_MAX)) + +/** @defgroup PDS_PLL_STS_TYPE + * @{ + */ +#define IS_PDS_PLL_STS_TYPE(type) (((type) == PDS_PLL_STS_OFF) || \ + ((type) == PDS_PLL_STS_SFREG) || \ + ((type) == PDS_PLL_STS_PU) || \ + ((type) == PDS_PLL_STS_RDY)) + +/** @defgroup PDS_RF_STS_TYPE + * @{ + */ +#define IS_PDS_RF_STS_TYPE(type) (((type) == PDS_RF_STS_OFF) || \ + ((type) == PDS_RF_STS_PU_MBG) || \ + ((type) == PDS_RF_STS_PU_LDO15RF) || \ + ((type) == PDS_RF_STS_PU_SFREG) || \ + ((type) == PDS_RF_STS_WB_EN_AON)) + +/** @defgroup PDS_STS_TYPE + * @{ + */ +#define IS_PDS_STS_TYPE(type) (((type) == PDS_STS_IDLE) || \ + ((type) == PDS_STS_ECG) || \ + ((type) == PDS_STS_ERST) || \ + ((type) == PDS_STS_EISO) || \ + ((type) == PDS_STS_POFF) || \ + ((type) == PDS_STS_PRE_BGON) || \ + ((type) == PDS_STS_PRE_BGON1) || \ + ((type) == PDS_STS_BGON) || \ + ((type) == PDS_STS_CLK_SW_32M) || \ + ((type) == PDS_STS_PON_DCDC) || \ + ((type) == PDS_STS_PON_LDO11_MISC) || \ + ((type) == PDS_STS_PON) || \ + ((type) == PDS_STS_DISO) || \ + ((type) == PDS_STS_DCG) || \ + ((type) == PDS_STS_DRST) || \ + ((type) == PDS_STS_WAIT_EFUSE)) + +/** @defgroup PDS_PLL_XTAL_TYPE + * @{ + */ +#define IS_PDS_PLL_XTAL_TYPE(type) (((type) == PDS_PLL_XTAL_NONE) || \ + ((type) == PDS_PLL_XTAL_24M) || \ + ((type) == PDS_PLL_XTAL_32M) || \ + ((type) == PDS_PLL_XTAL_38P4M) || \ + ((type) == PDS_PLL_XTAL_40M) || \ + ((type) == PDS_PLL_XTAL_26M) || \ + ((type) == PDS_PLL_XTAL_RC32M)) + +/** @defgroup PDS_PLL_CLK_TYPE + * @{ + */ +#define IS_PDS_PLL_CLK_TYPE(type) (((type) == PDS_PLL_CLK_480M) || \ + ((type) == PDS_PLL_CLK_240M) || \ + ((type) == PDS_PLL_CLK_192M) || \ + ((type) == PDS_PLL_CLK_160M) || \ + ((type) == PDS_PLL_CLK_120M) || \ + ((type) == PDS_PLL_CLK_96M) || \ + ((type) == PDS_PLL_CLK_80M) || \ + ((type) == PDS_PLL_CLK_48M) || \ + ((type) == PDS_PLL_CLK_32M)) + +/** @defgroup PDS_AON_GPIO_INT_TRIGGER_TYPE + * @{ + */ +#define IS_PDS_AON_GPIO_INT_TRIGGER_TYPE(type) (((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL)) + +/*@} end of group PDS_Public_Constants */ + +/** @defgroup PDS_Public_Macros + * @{ + */ +#define PDS_LDO_MIN_PU_CNT (25) /* LDO need 25 cycles to power up */ +#define PDS_WARMUP_LATENCY_CNT (38) /* LDO hw warmup compensation latency cycles */ +#define PDS_FORCE_PWR_OFF_OFFSET (0) +#define PDS_FORCE_ISO_EN_OFFSET (4) +#define PDS_FORCE_PDS_RST_OFFSET (8) +#define PDS_FORCE_MEM_STBY_OFFSET (12) +#define PDS_FORCE_GATE_CLK_OFFSET (16) +#define PDS_INT_MASK_BIT_OFFSET (8) +#define PDS_AON_WAKEUP_GPIO_NONE (0x00) +#define PDS_AON_WAKEUP_GPIO_7 (0x01) +#define PDS_AON_WAKEUP_GPIO_8 (0x02) +#define PDS_AON_WAKEUP_GPIO_ALL (0x03) + +/*@} end of group PDS_Public_Macros */ + +/** @defgroup PDS_Public_Functions + * @{ + */ +/*----------*/ +#ifndef BFLB_USE_HAL_DRIVER +void PDS_WAKEUP_IRQHandler(void); +#endif +/*----------*/ +BL_Err_Type PDS_Reset(void); +BL_Err_Type PDS_Enable(PDS_CTL_Type *cfg,PDS_CTL4_Type *cfg4,uint32_t pdsSleepCnt); +BL_Err_Type PDS_Force_Config(PDS_CTL2_Type *cfg2,PDS_CTL3_Type *cfg3); +BL_Err_Type PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg); +/*----------*/ +BL_Err_Type PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, + PDS_RAM_CFG_Type *ramCfg,uint32_t pdsSleepCnt); +/*----------*/ +BL_Err_Type PDS_IntMask(PDS_INT_Type intType,BL_Mask_Type intMask); +BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType); +BL_Err_Type PDS_IntClear(void); +PDS_PLL_STS_Type PDS_Get_PdsPllStstus(void); +PDS_RF_STS_Type PDS_Get_PdsRfStstus(void); +PDS_STS_Type PDS_Get_PdsStstus(void); +BL_Err_Type PDS_WAKEUP_IRQHandler_Install(void); +BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType,intCallback_Type* cbFun); +/*----------*/ +BL_Err_Type PDS_Trim_RC32M(void); +BL_Err_Type PDS_Select_RC32M_As_PLL_Ref(void); +BL_Err_Type PDS_Select_XTAL_As_PLL_Ref(void); +BL_Err_Type PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType); +BL_Err_Type PDS_Fix_Xtal_Settig(void); +BL_Err_Type PDS_Enable_PLL_All_Clks(void); +BL_Err_Type PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk); +BL_Err_Type PDS_Disable_PLL_All_Clks(void); +BL_Err_Type PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk); +BL_Err_Type PDS_Power_Off_PLL(void); +/*----------*/; + +/*@} end of group PDS_Public_Functions */ + +/*@} end of group PDS */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_PDS_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_pwm.h b/drivers/bl602_driver/std_drv/inc/bl602_pwm.h new file mode 100644 index 00000000..3469b6f6 --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_pwm.h @@ -0,0 +1,195 @@ +/** + ****************************************************************************** + * @file bl602_pwm.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_PWM_H__ +#define __BL602_PWM_H__ + +#include "pwm_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup PWM + * @{ + */ + +/** @defgroup PWM_Public_Types + * @{ + */ + +/** + * @brief PWM No. type definition + */ +typedef enum { + PWM_CH0 = 0, /*!< PWM Channel 0 define */ + PWM_CH1, /*!< PWM Channel 1 define */ + PWM_CH2, /*!< PWM Channel 2 define */ + PWM_CH3, /*!< PWM Channel 3 define */ + PWM_CH4, /*!< PWM Channel 4 define */ + PWM_CH_MAX, /*!< */ +}PWM_CH_ID_Type; + +/** + * @brief PWM Clock definition + */ +typedef enum { + PWM_CLK_XCLK = 0, /*!< PWM Clock source :XTAL CLK */ + PWM_CLK_BCLK, /*!< PWM Clock source :Bus CLK */ + PWM_CLK_32K, /*!< PWM Clock source :32K CLK */ +}PWM_Clk_Type; + +/** + * @brief PWM Stop Mode definition + */ +typedef enum { + PWM_STOP_ABRUPT = 0, /*!< PWM stop abrupt select define */ + PWM_STOP_GRACEFUL, /*!< PWM stop graceful select define */ +}PWM_Stop_Mode_Type; + +/** + * @brief PWM mode type def + */ +typedef enum { + PWM_POL_NORMAL = 0, /*!< PWM normal polarity mode define */ + PWM_POL_INVERT, /*!< PWM invert polarity mode define */ +}PWM_Polarity_Type; + +/** + * @brief PWM interrupt type def + */ +typedef enum { + PWM_INT_PULSE_CNT = 0, /*!< PWM Pulse count interrupt define */ + PWM_INT_ALL, /*!< */ +}PWM_INT_Type; + +/** + * @brief PWM configuration structure type definition + */ +typedef struct { + PWM_CH_ID_Type ch; /*!< PWM channel */ + PWM_Clk_Type clk; /*!< PWM Clock */ + PWM_Stop_Mode_Type stopMode; /*!< PWM Stop Mode */ + PWM_Polarity_Type pol; /*!< PWM mode type */ + uint16_t clkDiv; /*!< PWM clkDiv num */ + uint16_t period; /*!< PWM period set */ + uint16_t threshold1; /*!< PWM threshold1 num */ + uint16_t threshold2; /*!< PWM threshold2 num */ + uint16_t intPulseCnt; /*!< PWM interrupt pulse count */ +}PWM_CH_CFG_Type; + +/*@} end of group PWM_Public_Types */ + +/** @defgroup PWM_Public_Constants + * @{ + */ + +/** @defgroup PWM_CH_ID_TYPE + * @{ + */ +#define IS_PWM_CH_ID_TYPE(type) (((type) == PWM_CH0 ) || \ + ((type) == PWM_CH1) || \ + ((type) == PWM_CH2) || \ + ((type) == PWM_CH3) || \ + ((type) == PWM_CH4) || \ + ((type) == PWM_CH_MAX)) + +/** @defgroup PWM_CLK_TYPE + * @{ + */ +#define IS_PWM_CLK_TYPE(type) (((type) == PWM_CLK_XCLK ) || \ + ((type) == PWM_CLK_BCLK) || \ + ((type) == PWM_CLK_32K)) + +/** @defgroup PWM_STOP_MODE_TYPE + * @{ + */ +#define IS_PWM_STOP_MODE_TYPE(type) (((type) == PWM_STOP_ABRUPT ) || \ + ((type) == PWM_STOP_GRACEFUL)) + +/** @defgroup PWM_POLARITY_TYPE + * @{ + */ +#define IS_PWM_POLARITY_TYPE(type) (((type) == PWM_POL_NORMAL ) || \ + ((type) == PWM_POL_INVERT)) + +/** @defgroup PWM_INT_TYPE + * @{ + */ +#define IS_PWM_INT_TYPE(type) (((type) == PWM_INT_PULSE_CNT ) || \ + ((type) == PWM_INT_ALL)) + +/*@} end of group PWM_Public_Constants */ + +/** @defgroup PWM_Public_Macros + * @{ + */ +#define IS_PWM_CH(CH) ((CH) < PWM_CH_MAX) + +/*@} end of group PWM_Public_Macros */ + +/** @defgroup PWM_Public_Functions + * @{ + */ + +/** + * @brief PWM Functions + */ +#ifndef BFLB_USE_HAL_DRIVER +void PWM_IRQHandler(void); +#endif +BL_Err_Type PWM_Channel_Init(PWM_CH_CFG_Type *chCfg); +void PWM_Channel_Update(PWM_CH_ID_Type ch,uint16_t period,uint16_t threshold1,uint16_t threshold2); +void PWM_Channel_Set_Div(PWM_CH_ID_Type ch,uint16_t div); +void PWM_Channel_Set_Threshold1(PWM_CH_ID_Type ch,uint16_t threshold1); +void PWM_Channel_Set_Threshold2(PWM_CH_ID_Type ch,uint16_t threshold2); +void PWM_Channel_Set_Period(PWM_CH_ID_Type ch,uint16_t period); +void PWM_Channel_Get(PWM_CH_ID_Type ch,uint16_t *period,uint16_t *threshold1,uint16_t *threshold2); +void PWM_IntMask(PWM_CH_ID_Type ch,PWM_INT_Type intType,BL_Mask_Type intMask); +void PWM_Channel_Enable(PWM_CH_ID_Type ch); +void PWM_Channel_Disable(PWM_CH_ID_Type ch); +void PWM_SW_Mode(PWM_CH_ID_Type ch,BL_Fun_Type enable); +void PWM_SW_Force_Value(PWM_CH_ID_Type ch,uint8_t value); +void PWM_Int_Callback_Install(PWM_CH_ID_Type ch,uint32_t intType,intCallback_Type* cbFun); +BL_Err_Type PWM_Smart_Configure(PWM_CH_ID_Type ch,uint32_t frequency,uint8_t dutyCycle); + +/*@} end of group PWM_Public_Functions */ + +/*@} end of group PWM */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_PWM_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_romdriver.h b/drivers/bl602_driver/std_drv/inc/bl602_romdriver.h new file mode 100644 index 00000000..5b211ee1 --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_romdriver.h @@ -0,0 +1,810 @@ +/** + ****************************************************************************** + * @file bl602_romdriver.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_ROMDRIVER_H__ +#define __BL602_ROMDRIVER_H__ + +#include "bl602_common.h" +#include "bl602_aon.h" +#include "bl602_glb.h" +#include "bl602_hbn.h" +#include "bl602_xip_sflash.h" +#include "bl602_sflash.h" +#include "bl602_sf_ctrl.h" +#include "bl602_sec_eng.h" +#include "softcrc.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup ROMDRIVER + * @{ + */ + +/** @defgroup ROMDRIVER_Public_Types + * @{ + */ + +#define ROMAPI_INDEX_SECT_SIZE (0x800) +#define ROMAPI_INDEX_MAX (ROMAPI_INDEX_SECT_SIZE / 4 - 1) + +typedef enum { + ROM_API_INDEX_VERSION = 0, + ROM_API_INDEX_RSVD_0 , + ROM_API_INDEX_RSVD_1, + ROM_API_INDEX_RSVD_LAST, + + + ROM_API_INDEX_AON_Power_On_MBG, + ROM_API_INDEX_AON_Power_Off_MBG, + ROM_API_INDEX_AON_Power_On_XTAL, + ROM_API_INDEX_AON_Set_Xtal_CapCode, + ROM_API_INDEX_AON_Get_Xtal_CapCode, + ROM_API_INDEX_AON_Power_Off_XTAL, + ROM_API_INDEX_AON_Power_On_BG, + ROM_API_INDEX_AON_Power_Off_BG, + ROM_API_INDEX_AON_Power_On_LDO11_SOC, + ROM_API_INDEX_AON_Power_Off_LDO11_SOC, + ROM_API_INDEX_AON_Power_On_LDO15_RF, + ROM_API_INDEX_AON_Power_Off_LDO15_RF, + ROM_API_INDEX_AON_Power_On_SFReg, + ROM_API_INDEX_AON_Power_Off_SFReg, + ROM_API_INDEX_AON_LowPower_Enter_PDS0, + ROM_API_INDEX_AON_LowPower_Exit_PDS0, + + ROM_API_INDEX_ASM_Delay_Us, + + ROM_API_INDEX_BL602_Delay_US, + ROM_API_INDEX_BL602_Delay_MS, + ROM_API_INDEX_BL602_MemCpy, + ROM_API_INDEX_BL602_MemCpy4, + ROM_API_INDEX_BL602_MemCpy_Fast, + ROM_API_INDEX_BL602_MemSet, + ROM_API_INDEX_BL602_MemSet4, + ROM_API_INDEX_BL602_MemCmp, + + ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0, + ROM_API_INDEX_EF_Ctrl_Program_Efuse_0, + ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0, + ROM_API_INDEX_EF_Ctrl_Busy, + ROM_API_INDEX_EF_Ctrl_AutoLoad_Done, + ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity, + ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim, + ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim, + ROM_API_INDEX_EF_Ctrl_Clear, + + ROM_API_INDEX_GLB_Get_Root_CLK_Sel, + ROM_API_INDEX_GLB_Set_System_CLK_Div, + ROM_API_INDEX_GLB_Get_BCLK_Div, + ROM_API_INDEX_GLB_Get_HCLK_Div, + + ROM_API_INDEX_Update_SystemCoreClockWith_XTAL, + + ROM_API_INDEX_GLB_Set_System_CLK, + + ROM_API_INDEX_System_Core_Clock_Update_From_RC32M, + + ROM_API_INDEX_GLB_Set_SF_CLK, + ROM_API_INDEX_GLB_Set_PKA_CLK_Sel, + ROM_API_INDEX_GLB_SW_System_Reset, + ROM_API_INDEX_GLB_SW_CPU_Reset, + ROM_API_INDEX_GLB_SW_POR_Reset, + ROM_API_INDEX_GLB_Select_Internal_Flash, + ROM_API_INDEX_GLB_Select_External_Flash, + ROM_API_INDEX_GLB_Deswap_Flash_Pin, + ROM_API_INDEX_GLB_Swap_Flash_Pin, + ROM_API_INDEX_GLB_GPIO_Init, + ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable, + ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable, + ROM_API_INDEX_GLB_GPIO_Set_HZ, + ROM_API_INDEX_GLB_GPIO_Get_Fun, + + ROM_API_INDEX_HBN_Mode_Enter, + ROM_API_INDEX_HBN_Power_Down_Flash, + ROM_API_INDEX_HBN_Enable, + ROM_API_INDEX_HBN_Reset, + ROM_API_INDEX_HBN_Set_Ldo11_Aon_Vout, + ROM_API_INDEX_HBN_Set_Ldo11_Rt_Vout, + ROM_API_INDEX_HBN_Set_Ldo11_Soc_Vout, + ROM_API_INDEX_HBN_32K_Sel, + ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel, + ROM_API_INDEX_HBN_Power_On_Xtal_32K, + ROM_API_INDEX_HBN_Power_Off_Xtal_32K, + ROM_API_INDEX_HBN_Power_On_RC32K, + ROM_API_INDEX_HBN_Power_Off_RC32K, + ROM_API_INDEX_HBN_Trim_RC32K, + ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg, + ROM_API_INDEX_HBN_Pin_WakeUp_Mask, + ROM_API_INDEX_HBN_GPIO7_Dbg_Pull_Cfg, + ROM_API_INDEX_HBN_Set_Embedded_Flash_Pullup, + + ROM_API_INDEX_L1C_Set_Wrap, + ROM_API_INDEX_L1C_Set_Way_Disable, + ROM_API_INDEX_L1C_IROM_2T_Access_Set, + + ROM_API_INDEX_PDS_Reset, + ROM_API_INDEX_PDS_Enable, + ROM_API_INDEX_PDS_Force_Config, + ROM_API_INDEX_PDS_RAM_Config, + ROM_API_INDEX_PDS_Default_Level_Config, + ROM_API_INDEX_PDS_Trim_RC32M, + ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref, + ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref, + ROM_API_INDEX_PDS_Power_On_PLL, + ROM_API_INDEX_PDS_Enable_PLL_All_Clks, + ROM_API_INDEX_PDS_Disable_PLL_All_Clks, + ROM_API_INDEX_PDS_Enable_PLL_Clk, + ROM_API_INDEX_PDS_Disable_PLL_Clk, + ROM_API_INDEX_PDS_Power_Off_PLL, + + ROM_API_INDEX_SEC_Eng_Turn_On_Sec_Ring, + ROM_API_INDEX_SEC_Eng_Turn_Off_Sec_Ring, + + ROM_API_INDEX_SFlash_Init, + ROM_API_INDEX_SFlash_SetSPIMode, + ROM_API_INDEX_SFlash_Read_Reg, + ROM_API_INDEX_SFlash_Write_Reg, + ROM_API_INDEX_SFlash_Busy, + ROM_API_INDEX_SFlash_Write_Enable, + ROM_API_INDEX_SFlash_Qspi_Enable, + ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable, + ROM_API_INDEX_SFlash_Chip_Erase, + ROM_API_INDEX_SFlash_Sector_Erase, + ROM_API_INDEX_SFlash_Blk32_Erase, + ROM_API_INDEX_SFlash_Blk64_Erase, + ROM_API_INDEX_SFlash_Erase, + ROM_API_INDEX_SFlash_Program, + ROM_API_INDEX_SFlash_GetUniqueId, + ROM_API_INDEX_SFlash_GetJedecId, + ROM_API_INDEX_SFlash_GetDeviceId, + ROM_API_INDEX_SFlash_Powerdown, + ROM_API_INDEX_SFlash_Releae_Powerdown, + ROM_API_INDEX_SFlash_SetBurstWrap, + ROM_API_INDEX_SFlash_DisableBurstWrap, + ROM_API_INDEX_SFlash_Software_Reset, + ROM_API_INDEX_SFlash_Reset_Continue_Read, + ROM_API_INDEX_SFlash_Set_IDbus_Cfg, + ROM_API_INDEX_SFlash_IDbus_Read_Enable, + ROM_API_INDEX_SFlash_Cache_Enable_Set, + ROM_API_INDEX_SFlash_Cache_Flush, + ROM_API_INDEX_SFlash_Cache_Read_Enable, + ROM_API_INDEX_SFlash_Cache_Hit_Count_Get, + ROM_API_INDEX_SFlash_Cache_Miss_Count_Get, + ROM_API_INDEX_SFlash_Cache_Read_Disable, + ROM_API_INDEX_SFlash_Read, + ROM_API_INDEX_SFlash_Read_Reg_With_Cmd, + ROM_API_INDEX_SFlash_Write_Reg_With_Cmd, + ROM_API_INDEX_SFlash_Restore_From_Powerdown, + + ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio, + ROM_API_INDEX_SF_Cfg_Init_Internal_Flash_Gpio, + ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio, + ROM_API_INDEX_SF_Cfg_Restore_GPIO17_Fun, + ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock, + ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio, + ROM_API_INDEX_SF_Cfg_Flash_Identify, + ROM_API_INDEX_SF_Ctrl_Enable, + ROM_API_INDEX_SF_Ctrl_Select_Pad, + ROM_API_INDEX_SF_Ctrl_Set_Owner, + ROM_API_INDEX_SF_Ctrl_Disable, + ROM_API_INDEX_SF_Ctrl_AES_Enable_BE, + ROM_API_INDEX_SF_Ctrl_AES_Enable_LE, + ROM_API_INDEX_SF_Ctrl_AES_Set_Region, + ROM_API_INDEX_SF_Ctrl_AES_Set_Key, + ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE, + ROM_API_INDEX_SF_Ctrl_AES_Set_IV, + ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE, + ROM_API_INDEX_SF_Ctrl_AES_Enable, + ROM_API_INDEX_SF_Ctrl_AES_Disable, + ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset, + ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset, + ROM_API_INDEX_SF_Ctrl_Select_Clock, + ROM_API_INDEX_SF_Ctrl_SendCmd, + ROM_API_INDEX_SF_Ctrl_Icache_Set, + ROM_API_INDEX_SF_Ctrl_Icache2_Set, + ROM_API_INDEX_SF_Ctrl_GetBusyState, + ROM_API_INDEX_SF_Ctrl_Is_AES_Enable, + ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay, + ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay, + + ROM_API_INDEX_XIP_SFlash_State_Save, + ROM_API_INDEX_XIP_SFlash_State_Restore, + ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock, + ROM_API_INDEX_XIP_SFlash_Write_Need_Lock, + ROM_API_INDEX_XIP_SFlash_Read_Need_Lock, + ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock, + ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock, + ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock, + ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock, + ROM_API_INDEX_XIP_SFlash_Read_With_Lock, + ROM_API_INDEX_XIP_SFlash_Write_With_Lock, + ROM_API_INDEX_XIP_SFlash_Erase_With_Lock, + ROM_API_INDEX_XIP_SFlash_Opt_Enter, + ROM_API_INDEX_XIP_SFlash_Opt_Exit, + + ROM_API_INDEX_BFLB_Soft_CRC32, + + ROM_API_INDEX_FUNC_EMPTY_START, + + ROM_API_INDEX_FUNC_EMPTY_END = ROMAPI_INDEX_MAX + +} ROM_API_INDEX_e; + +/*@} end of group ROMDRIVER_Public_Types */ + +/** @defgroup ROMDRIVER_Public_Constants + * @{ + */ + +/*@} end of group ROMDRIVER_Public_Constants */ + +/** @defgroup ROMDRIVER_Public_Macros + * @{ + */ + + +#define ROM_APITABLE ((uint32_t *)0x21010800) + + +#define RomDriver_AON_Power_On_MBG \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_MBG]) + +#define RomDriver_AON_Power_Off_MBG \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_MBG]) + +#define RomDriver_AON_Power_On_XTAL \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_XTAL]) + +#define RomDriver_AON_Set_Xtal_CapCode \ + ((BL_Err_Type (*) (uint8_t capIn,uint8_t capOut))ROM_APITABLE[ROM_API_INDEX_AON_Set_Xtal_CapCode]) + +#define RomDriver_AON_Get_Xtal_CapCode \ + ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Get_Xtal_CapCode]) + +#define RomDriver_AON_Power_Off_XTAL \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_XTAL]) + +#define RomDriver_AON_Power_On_BG \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_BG]) + +#define RomDriver_AON_Power_Off_BG \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_BG]) + +#define RomDriver_AON_Power_On_LDO11_SOC \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_LDO11_SOC]) + +#define RomDriver_AON_Power_Off_LDO11_SOC \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_LDO11_SOC]) + +#define RomDriver_AON_Power_On_LDO15_RF \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_LDO15_RF]) + +#define RomDriver_AON_Power_Off_LDO15_RF \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_LDO15_RF]) + +#define RomDriver_AON_Power_On_SFReg \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_SFReg]) + +#define RomDriver_AON_Power_Off_SFReg \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_SFReg]) + +#define RomDriver_AON_LowPower_Enter_PDS0 \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_LowPower_Enter_PDS0]) + +#define RomDriver_AON_LowPower_Exit_PDS0 \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_LowPower_Exit_PDS0]) + +#define RomDriver_ASM_Delay_Us \ + ((void (*) (uint32_t core,uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_ASM_Delay_Us]) + +#define RomDriver_BL602_Delay_US \ + ((void (*) (uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_BL602_Delay_US]) + +#define RomDriver_BL602_Delay_MS \ + ((void (*) (uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_BL602_Delay_MS]) + +#define RomDriver_BL602_MemCpy \ + ((void* (*) (void *dst, const void *src, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemCpy]) + +#define RomDriver_BL602_MemCpy4 \ + ((uint32_t* (*) (uint32_t *dst, const uint32_t *src, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemCpy4]) + +#define RomDriver_BL602_MemCpy_Fast \ + ((void* (*) (void *pdst, const void *psrc, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemCpy_Fast]) + +#define RomDriver_BL602_MemSet \ + ((void* (*) (void *s, uint8_t c, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemSet]) + +#define RomDriver_BL602_MemSet4 \ + ((uint32_t* (*) (uint32_t *dst, const uint32_t val, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemSet4]) + +#define RomDriver_BL602_MemCmp \ + ((int (*) (const void *s1, const void *s2, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemCmp]) + +#define RomDriver_EF_Ctrl_Sw_AHB_Clk_0 \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0]) + +#define RomDriver_EF_Ctrl_Program_Efuse_0 \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Program_Efuse_0]) + +#define RomDriver_EF_Ctrl_Load_Efuse_R0 \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0]) + +#define RomDriver_EF_Ctrl_Busy \ + ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Busy]) + +#define RomDriver_EF_Ctrl_AutoLoad_Done \ + ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_AutoLoad_Done]) + +#define RomDriver_EF_Ctrl_Get_Trim_Parity \ + ((uint8_t (*) (uint32_t val,uint8_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity]) + +#define RomDriver_EF_Ctrl_Read_RC32M_Trim \ + ((void (*) ( Efuse_Ana_RC32M_Trim_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim]) + +#define RomDriver_EF_Ctrl_Read_RC32K_Trim \ + ((void (*) ( Efuse_Ana_RC32K_Trim_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim]) + +#define RomDriver_EF_Ctrl_Clear \ + ((void (*) (uint32_t index, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Clear]) + +#define RomDriver_GLB_Get_Root_CLK_Sel \ + ((GLB_ROOT_CLK_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_Root_CLK_Sel]) + +#define RomDriver_GLB_Set_System_CLK_Div \ + ((BL_Err_Type (*) (uint8_t hclkDiv,uint8_t bclkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Set_System_CLK_Div]) + +#define RomDriver_GLB_Get_BCLK_Div \ + ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_BCLK_Div]) + +#define RomDriver_GLB_Get_HCLK_Div \ + ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_HCLK_Div]) + +#define RomDriver_Update_SystemCoreClockWith_XTAL \ + ((BL_Err_Type (*) (GLB_PLL_XTAL_Type xtalType))ROM_APITABLE[ROM_API_INDEX_Update_SystemCoreClockWith_XTAL]) + +#define RomDriver_GLB_Set_System_CLK \ + ((BL_Err_Type (*) (GLB_PLL_XTAL_Type xtalType,GLB_SYS_CLK_Type clkFreq))ROM_APITABLE[ROM_API_INDEX_GLB_Set_System_CLK]) + +#define RomDriver_System_Core_Clock_Update_From_RC32M \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_System_Core_Clock_Update_From_RC32M]) + +#define RomDriver_GLB_Set_SF_CLK \ + ((BL_Err_Type (*) (uint8_t enable,GLB_SFLASH_CLK_Type clkSel,uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SF_CLK]) + +#define RomDriver_GLB_Set_PKA_CLK_Sel \ + ((BL_Err_Type (*) (GLB_PKA_CLK_Type clkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_PKA_CLK_Sel]) + +#define RomDriver_GLB_SW_System_Reset \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_System_Reset]) + +#define RomDriver_GLB_SW_CPU_Reset \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_CPU_Reset]) + +#define RomDriver_GLB_SW_POR_Reset \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_POR_Reset]) + +#define RomDriver_GLB_Select_Internal_Flash \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Select_Internal_Flash]) + +#define RomDriver_GLB_Select_External_Flash \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Select_External_Flash]) + +#define RomDriver_GLB_Deswap_Flash_Pin \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Deswap_Flash_Pin]) + +#define RomDriver_GLB_Swap_Flash_Pin \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Swap_Flash_Pin]) + +#define RomDriver_GLB_GPIO_Init \ + ((BL_Err_Type (*) (GLB_GPIO_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Init]) + +#define RomDriver_GLB_GPIO_OUTPUT_Enable \ + ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable]) + +#define RomDriver_GLB_GPIO_OUTPUT_Disable \ + ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable]) + +#define RomDriver_GLB_GPIO_Set_HZ \ + ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Set_HZ]) + +#define RomDriver_GLB_GPIO_Get_Fun \ + ((uint8_t (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Get_Fun]) + +#define RomDriver_HBN_Mode_Enter \ + ((void (*) (HBN_APP_CFG_Type *cfg))ROM_APITABLE[ROM_API_INDEX_HBN_Mode_Enter]) + +#define RomDriver_HBN_Power_Down_Flash \ + ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Down_Flash]) + +#define RomDriver_HBN_Enable \ + ((void (*) (uint8_t aGPIOIeCfg,HBN_LDO_LEVEL_Type ldoLevel,HBN_LEVEL_Type hbnLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Enable]) + +#define RomDriver_HBN_Reset \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Reset]) + +#define RomDriver_HBN_Set_Ldo11_Aon_Vout \ + ((BL_Err_Type (*) (HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_Aon_Vout]) + +#define RomDriver_HBN_Set_Ldo11_Rt_Vout \ + ((BL_Err_Type (*) (HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_Rt_Vout]) + +#define RomDriver_HBN_Set_Ldo11_Soc_Vout \ + ((BL_Err_Type (*) (HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_Soc_Vout]) + +#define RomDriver_HBN_32K_Sel \ + ((BL_Err_Type (*) (HBN_32K_CLK_Type clkType))ROM_APITABLE[ROM_API_INDEX_HBN_32K_Sel]) + +#define RomDriver_HBN_Set_ROOT_CLK_Sel \ + ((BL_Err_Type (*) (HBN_ROOT_CLK_Type rootClk))ROM_APITABLE[ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel]) + +#define RomDriver_HBN_Power_On_Xtal_32K \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_On_Xtal_32K]) + +#define RomDriver_HBN_Power_Off_Xtal_32K \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Off_Xtal_32K]) + +#define RomDriver_HBN_Power_On_RC32K \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_On_RC32K]) + +#define RomDriver_HBN_Power_Off_RC32K \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Off_RC32K]) + +#define RomDriver_HBN_Trim_RC32K \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Trim_RC32K]) + +#define RomDriver_HBN_Hw_Pu_Pd_Cfg \ + ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg]) + +#define RomDriver_HBN_Pin_WakeUp_Mask \ + ((BL_Err_Type (*) (uint8_t maskVal))ROM_APITABLE[ROM_API_INDEX_HBN_Pin_WakeUp_Mask]) + +#define RomDriver_HBN_GPIO7_Dbg_Pull_Cfg \ + ((BL_Err_Type (*) (BL_Fun_Type pupdEn,BL_Fun_Type iesmtEn,BL_Fun_Type dlyEn,uint8_t dlySec))ROM_APITABLE[ROM_API_INDEX_HBN_GPIO7_Dbg_Pull_Cfg]) + +#define RomDriver_HBN_Set_Embedded_Flash_Pullup \ + ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Embedded_Flash_Pullup]) + +#define RomDriver_L1C_Set_Wrap \ + ((BL_Err_Type (*) (BL_Fun_Type wrap))ROM_APITABLE[ROM_API_INDEX_L1C_Set_Wrap]) + +#define RomDriver_L1C_Set_Way_Disable \ + ((BL_Err_Type (*) (uint8_t disableVal))ROM_APITABLE[ROM_API_INDEX_L1C_Set_Way_Disable]) + +#define RomDriver_L1C_IROM_2T_Access_Set \ + ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_L1C_IROM_2T_Access_Set]) + +#define RomDriver_PDS_Reset \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Reset]) + +#define RomDriver_PDS_Enable \ + ((BL_Err_Type (*) (PDS_CTL_Type *cfg,PDS_CTL4_Type *cfg4,uint32_t pdsSleepCnt))ROM_APITABLE[ROM_API_INDEX_PDS_Enable]) + +#define RomDriver_PDS_Force_Config \ + ((BL_Err_Type (*) (PDS_CTL2_Type *cfg2,PDS_CTL3_Type *cfg3))ROM_APITABLE[ROM_API_INDEX_PDS_Force_Config]) + +#define RomDriver_PDS_RAM_Config \ + ((BL_Err_Type (*) (PDS_RAM_CFG_Type *ramCfg))ROM_APITABLE[ROM_API_INDEX_PDS_RAM_Config]) + +#define RomDriver_PDS_Default_Level_Config \ + ((BL_Err_Type (*) (PDS_DEFAULT_LV_CFG_Type *defaultLvCfg,PDS_RAM_CFG_Type *ramCfg,uint32_t pdsSleepCnt))ROM_APITABLE[ROM_API_INDEX_PDS_Default_Level_Config]) + +#define RomDriver_PDS_Trim_RC32M \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Trim_RC32M]) + +#define RomDriver_PDS_Select_RC32M_As_PLL_Ref \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref]) + +#define RomDriver_PDS_Select_XTAL_As_PLL_Ref \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref]) + +#define RomDriver_PDS_Power_On_PLL \ + ((BL_Err_Type (*) (PDS_PLL_XTAL_Type xtalType))ROM_APITABLE[ROM_API_INDEX_PDS_Power_On_PLL]) + +#define RomDriver_PDS_Enable_PLL_All_Clks \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Enable_PLL_All_Clks]) + +#define RomDriver_PDS_Disable_PLL_All_Clks \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Disable_PLL_All_Clks]) + +#define RomDriver_PDS_Enable_PLL_Clk \ + ((BL_Err_Type (*) (PDS_PLL_CLK_Type pllClk))ROM_APITABLE[ROM_API_INDEX_PDS_Enable_PLL_Clk]) + +#define RomDriver_PDS_Disable_PLL_Clk \ + ((BL_Err_Type (*) (PDS_PLL_CLK_Type pllClk))ROM_APITABLE[ROM_API_INDEX_PDS_Disable_PLL_Clk]) + +#define RomDriver_PDS_Power_Off_PLL \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Power_Off_PLL]) + +#define RomDriver_SEC_Eng_Turn_On_Sec_Ring \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SEC_Eng_Turn_On_Sec_Ring]) + +#define RomDriver_SEC_Eng_Turn_Off_Sec_Ring \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SEC_Eng_Turn_Off_Sec_Ring]) + +#define RomDriver_SFlash_Init \ + ((void (*) (const SF_Ctrl_Cfg_Type *pSfCtrlCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Init]) + +#define RomDriver_SFlash_SetSPIMode \ + ((BL_Err_Type (*) (SF_Ctrl_Mode_Type mode))ROM_APITABLE[ROM_API_INDEX_SFlash_SetSPIMode]) + +#define RomDriver_SFlash_Read_Reg \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,uint8_t regIndex,uint8_t *regValue,uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg]) + +#define RomDriver_SFlash_Write_Reg \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,uint8_t regIndex,uint8_t *regValue,uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg]) + +#define RomDriver_SFlash_Busy \ + ((BL_Sts_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Busy]) + +#define RomDriver_SFlash_Write_Enable \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Enable]) + +#define RomDriver_SFlash_Qspi_Enable \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Enable]) + +#define RomDriver_SFlash_Volatile_Reg_Write_Enable \ + ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable]) + +#define RomDriver_SFlash_Chip_Erase \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Chip_Erase]) + +#define RomDriver_SFlash_Sector_Erase \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,uint32_t secNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Sector_Erase]) + +#define RomDriver_SFlash_Blk32_Erase \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,uint32_t blkNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Blk32_Erase]) + +#define RomDriver_SFlash_Blk64_Erase \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,uint32_t blkNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Blk64_Erase]) + +#define RomDriver_SFlash_Erase \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,uint32_t startaddr,uint32_t endaddr))ROM_APITABLE[ROM_API_INDEX_SFlash_Erase]) + +#define RomDriver_SFlash_Program \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint32_t addr,uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_SFlash_Program]) + +#define RomDriver_SFlash_GetUniqueId \ + ((void (*) (uint8_t *data,uint8_t idLen))ROM_APITABLE[ROM_API_INDEX_SFlash_GetUniqueId]) + +#define RomDriver_SFlash_GetJedecId \ + ((void (*) (SPI_Flash_Cfg_Type *flashCfg,uint8_t *data))ROM_APITABLE[ROM_API_INDEX_SFlash_GetJedecId]) + +#define RomDriver_SFlash_GetDeviceId \ + ((void (*) (uint8_t *data))ROM_APITABLE[ROM_API_INDEX_SFlash_GetDeviceId]) + +#define RomDriver_SFlash_Powerdown \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SFlash_Powerdown]) + +#define RomDriver_SFlash_Releae_Powerdown \ + ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Releae_Powerdown]) + +#define RomDriver_SFlash_SetBurstWrap \ + ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_SetBurstWrap]) + +#define RomDriver_SFlash_DisableBurstWrap \ + ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_DisableBurstWrap]) + +#define RomDriver_SFlash_Software_Reset \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Software_Reset]) + +#define RomDriver_SFlash_Reset_Continue_Read \ + ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Reset_Continue_Read]) + +#define RomDriver_SFlash_Set_IDbus_Cfg \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint8_t contRead,uint32_t addr,uint32_t len))ROM_APITABLE[ROM_API_INDEX_SFlash_Set_IDbus_Cfg]) + +#define RomDriver_SFlash_IDbus_Read_Enable \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint8_t contRead))ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Enable]) + +#define RomDriver_SFlash_Cache_Enable_Set \ + ((BL_Err_Type (*) (uint8_t wayDisable))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Enable_Set]) + +#define RomDriver_SFlash_Cache_Flush \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Flush]) + +#define RomDriver_SFlash_Cache_Read_Enable \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint8_t contRead,uint8_t wayDisable))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Enable]) + +#define RomDriver_SFlash_Cache_Hit_Count_Get \ + ((void (*) (uint32_t *hitCountLow,uint32_t *hitCountHigh))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Hit_Count_Get]) + +#define RomDriver_SFlash_Cache_Miss_Count_Get \ + ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Miss_Count_Get]) + +#define RomDriver_SFlash_Cache_Read_Disable \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Disable]) + +#define RomDriver_SFlash_Read \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint8_t contRead,uint32_t addr,uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_SFlash_Read]) + +#define RomDriver_SFlash_Read_Reg_With_Cmd \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,uint8_t readRegCmd,uint8_t *regValue,uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd]) + +#define RomDriver_SFlash_Write_Reg_With_Cmd \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,uint8_t writeRegCmd,uint8_t *regValue,uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd]) + +#define RomDriver_SFlash_Restore_From_Powerdown \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint8_t flashContRead))ROM_APITABLE[ROM_API_INDEX_SFlash_Restore_From_Powerdown]) + +#define RomDriver_SF_Cfg_Init_Ext_Flash_Gpio \ + ((void (*) (uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio]) + +#define RomDriver_SF_Cfg_Init_Internal_Flash_Gpio \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Internal_Flash_Gpio]) + +#define RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio \ + ((void (*) (uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio]) + +#define RomDriver_SF_Cfg_Restore_GPIO17_Fun \ + ((void (*) (uint8_t fun))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Restore_GPIO17_Fun]) + +#define RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock \ + ((BL_Err_Type (*) (uint32_t flashID,SPI_Flash_Cfg_Type * pFlashCfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock]) + +#define RomDriver_SF_Cfg_Init_Flash_Gpio \ + ((void (*) (uint8_t flashPinCfg,uint8_t restoreDefault))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio]) + +#define RomDriver_SF_Cfg_Flash_Identify \ + ((uint32_t (*) (uint8_t callFromFlash,uint32_t autoScan,uint32_t flashPinCfg,uint8_t restoreDefault,SPI_Flash_Cfg_Type * pFlashCfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify]) + +#define RomDriver_SF_Ctrl_Enable \ + ((void (*) (const SF_Ctrl_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Enable]) + +#define RomDriver_SF_Ctrl_Select_Pad \ + ((void (*) (SF_Ctrl_Pad_Sel sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Pad]) + +#define RomDriver_SF_Ctrl_Set_Owner \ + ((void (*) (SF_Ctrl_Owner_Type owner))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Owner]) + +#define RomDriver_SF_Ctrl_Disable \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Disable]) + +#define RomDriver_SF_Ctrl_AES_Enable_BE \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable_BE]) + +#define RomDriver_SF_Ctrl_AES_Enable_LE \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable_LE]) + +#define RomDriver_SF_Ctrl_AES_Set_Region \ + ((void (*) (uint8_t region,uint8_t enable,uint8_t hwKey,uint32_t startAddr,uint32_t endAddr,uint8_t locked))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Region]) + +#define RomDriver_SF_Ctrl_AES_Set_Key \ + ((void (*) (uint8_t region,uint8_t *key, SF_Ctrl_AES_Key_Type keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key]) + +#define RomDriver_SF_Ctrl_AES_Set_Key_BE \ + ((void (*) (uint8_t region,uint8_t *key, SF_Ctrl_AES_Key_Type keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE]) + +#define RomDriver_SF_Ctrl_AES_Set_IV \ + ((void (*) (uint8_t region,uint8_t *iv,uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV]) + +#define RomDriver_SF_Ctrl_AES_Set_IV_BE \ + ((void (*) (uint8_t region,uint8_t *iv,uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE]) + +#define RomDriver_SF_Ctrl_AES_Enable \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable]) + +#define RomDriver_SF_Ctrl_AES_Disable \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Disable]) + +#define RomDriver_SF_Ctrl_Set_Flash_Image_Offset \ + ((void (*) (uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset]) + +#define RomDriver_SF_Ctrl_Get_Flash_Image_Offset \ + ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset]) + +#define RomDriver_SF_Ctrl_Select_Clock \ + ((void (*) (SF_Ctrl_Sahb_Type sahbType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Clock]) + +#define RomDriver_SF_Ctrl_SendCmd \ + ((void (*) (SF_Ctrl_Cmd_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_SendCmd]) + +#define RomDriver_SF_Ctrl_Icache_Set \ + ((void (*) (SF_Ctrl_Cmd_Cfg_Type *cfg,uint8_t cmdValid))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Icache_Set]) + +#define RomDriver_SF_Ctrl_Icache2_Set \ + ((void (*) (SF_Ctrl_Cmd_Cfg_Type *cfg,uint8_t cmdValid))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Icache2_Set]) + +#define RomDriver_SF_Ctrl_GetBusyState \ + ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_GetBusyState]) + +#define RomDriver_SF_Ctrl_Is_AES_Enable \ + ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_AES_Enable]) + +#define RomDriver_SF_Ctrl_Get_Clock_Delay \ + ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay]) + +#define RomDriver_SF_Ctrl_Set_Clock_Delay \ + ((void (*) (uint8_t delay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay]) + +#define RomDriver_XIP_SFlash_State_Save \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint32_t *offset))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Save]) + +#define RomDriver_XIP_SFlash_State_Restore \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint32_t offset))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Restore]) + +#define RomDriver_XIP_SFlash_Erase_Need_Lock \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint32_t startaddr,uint32_t endaddr))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock]) + +#define RomDriver_XIP_SFlash_Write_Need_Lock \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr,uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock]) + +#define RomDriver_XIP_SFlash_Read_Need_Lock \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr,uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock]) + +#define RomDriver_XIP_SFlash_GetJedecId_Need_Lock \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock]) + +#define RomDriver_XIP_SFlash_GetDeviceId_Need_Lock \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock]) + +#define RomDriver_XIP_SFlash_GetUniqueId_Need_Lock \ + ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data,uint8_t idLen))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock]) + +#define RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock \ + ((BL_Err_Type (*) (uint32_t addr,uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock]) + +#define RomDriver_XIP_SFlash_Read_With_Lock \ + ((int (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *dst, int len))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_With_Lock]) + +#define RomDriver_XIP_SFlash_Write_With_Lock \ + ((int (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *src, int len))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_With_Lock]) + +#define RomDriver_XIP_SFlash_Erase_With_Lock \ + ((int (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, int len))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_With_Lock]) + +#define RomDriver_XIP_SFlash_Opt_Enter \ + ((void (*) (uint8_t *aesEnable))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Opt_Enter]) + +#define RomDriver_XIP_SFlash_Opt_Exit \ + ((void (*) (uint8_t aesEnable))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Opt_Exit]) + +#define RomDriver_BFLB_Soft_CRC32 \ + ((uint32_t (*) (void *dataIn, uint32_t len))ROM_APITABLE[ROM_API_INDEX_BFLB_Soft_CRC32]) + +/*@} end of group ROMDRIVER_Public_Macros */ + +/** @defgroup ROMDRIVER_Public_Functions + * @{ + */ + +/*@} end of group ROMDRIVER_Public_Functions */ + +/*@} end of group ROMDRIVER */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_ROMDRIVER_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_sdu.h b/drivers/bl602_driver/std_drv/inc/bl602_sdu.h new file mode 100644 index 00000000..72387513 --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_sdu.h @@ -0,0 +1,194 @@ +#ifndef __BL602_SDU_H__ +#define __BL602_SDU_H__ + +#include "bl602.h" +#include "bl602_common.h" + +#define NUM_FUNC 1 +#define FUNC_WIFI 0 + +// SDIO I/O Enable +#define BL_SDIO_IO_ENABLE SDU_BASE + 0x00000002 +//CCCR (Fn0) Registers + +// SDIO Device Sleep +#define BL_SDIO_DEV_SLEEP SDU_BASE + 0x00000092 + +// Start Address of CCR +#define BL_SDIO_CCR_BASE SDU_BASE + 0x00000100 +// Address offset of CCR between two functions +#define BL_SDIO_CCR_FUNC_OFFSET 0x00000100 + + +// Address for sdio block size information +#define SDIO_FN1_BLK_SIZE_0 (SDU_BASE + 0x00000028) +#define SDIO_FN1_BLK_SIZE_1 (SDU_BASE + 0x00000029) +#define SDIO_FN1_BLK_SIZE_1_MASK 0x01 + +#define BL_FUNC_SCRATCH_BASE SDU_BASE + 0x00000160 + +typedef struct +{ + uint8_t HostToCardEvent; // 0x100/200 + uint8_t HostIntCause; // 0x101/201 + uint8_t HostIntMask; // 0x102/202 + uint8_t HostIntStatus; // 0x103/203 + uint16_t RdBitMap; // 0x104/204 + uint16_t WrBitMap; // 0x106/206 + uint16_t RdLen[16]; // 0x108/208 + uint8_t HostTransferStatus;// 0x128/228 + uint8_t reserved1[0x130-0x128-1]; + uint8_t CardToHostEvent; // 0x130/230 + uint8_t reserved2[3]; + uint8_t CardIntMask; // 0x134/234 + uint8_t reserved3[3]; + uint8_t CardIntStatus; // 0x138/238 + uint8_t reserved4[3]; + uint8_t CardIntMode; // 0x13C/23C + uint8_t reserved5[3]; + uint32_t SqReadBase; // 0x140/240 + uint32_t SqWriteBase; // 0x144/244 + uint8_t RdIdx; // 0x148/248 + uint8_t WrIdx; // 0x149/249 + uint8_t DnldQueueWrPtr; // 0x14A/24A + uint8_t UpldQueueWrPtr; // 0x14B/24B + uint8_t DnldQueue[8]; // 0x14C/24C + uint8_t UpldQueue[8]; // 0x154/254 + uint8_t ChipRev; // 0x15C //RO + uint8_t reserved6; // 0x15D //NOT_DEFINE + uint8_t IPRev0; // 0x15E //RO + uint8_t IPRev1; // 0x15F //RO + uint8_t reserved7[4]; // 0x160/260 + uint16_t Scratch2; // 0x164/264 + uint16_t Scratch1; // 0x166/266 + uint8_t Ocr0; // 0x168/268 + uint8_t Ocr1; // 0x169/269 + uint8_t Ocr2; // 0x16A/26A + uint8_t Config; // 0x16B/26B + uint32_t Config2; // 0x16C/26C + uint32_t Debug; // 0x170/270 + uint32_t DmaAddr; // 0x174/274 + uint8_t IoPort[3]; // 0x178/278 +} __attribute__((packed)) HidSdio_RegMap_t, *pHidSdio_RegMap_t; + +// Common I/O Area Registers (CIA) Offset +// +// Bit Def. Host To Card Interrupt Event (Offset 0x100/200) +#define SDIO_HCR_CONFIG_HostPwrUp (1<<1) + +// Bit Def. Host Transfer Status (Offset 0x128/228) +#define SDIO_CCR_HOST_INT_DnLdReStart (1<<0) +#define SDIO_CCR_HOST_INT_UpLdReStart (1<<1) +#define SDIO_CCR_HOST_INT_DnLdCRC_err (1<<2) + +// Bit Def. Card To Host Interrupt Event (Offset 0x130/230) +#define SDIO_CCR_CS_DnLdRdy (1<<0) +#define SDIO_CCR_CS_UpLdRdy (1<<1) +#define SDIO_CCR_CS_ReadCISRdy (1<<2) +#define SDIO_CCR_CS_IORdy (1<<3) + + +// Bit Def. Card Interrupt Mask (Offset 0x134/234) +#define SDIO_CCR_CIM_DnLdOvr (1<<0) +#define SDIO_CCR_CIM_UpLdOvr (1<<1) +#define SDIO_CCR_CIM_Abort (1<<2) +#define SDIO_CCR_CIM_PwrDn (1<<3) +#define SDIO_CCR_CIM_PwrUp (1<<4) + +#define SDIO_CCR_CIM_MASK 0x0007 + + +// Bit Def. Card Interrupt Status (Offset 0x138/238) +#define SDIO_CCR_CIC_DnLdOvr (1<<0) +#define SDIO_CCR_CIC_UpLdOvr (1<<1) +#define SDIO_CCR_CIC_Abort (1<<2) +#define SDIO_CCR_CIC_PwrDn (1<<3) +#define SDIO_CCR_CIC_PwrUp (1<<4) + + + +#define SDIO_CCR_CIC_MASK 0x001F + +// Bit Def. Card Interrupt RSR (Offset 0x13C/23C) +#define SDIO_CCR_CIO_DnLdOvr (1<<0) +#define SDIO_CCR_CIO_UpLdOvr (1<<1) +#define SDIO_CCR_CIO_Abort (1<<2) +#define SDIO_CCR_CIO_PwrDn (1<<3) +#define SDIO_CCR_CIO_PwrUp (1<<4) +#define SDIO_CCR_CIO_MASK 0x001F + + +//Config2 register mask +#define CONFIG2_MSK 0x00000C00 + + +//CardIntMode register mask + +#define CARD_INT_MODE_MSK 0x00000003 +#define HOST_INT_MSK 0x00000002 + +//============================================================================= +// PUBLIC MACROS +//============================================================================= + +#define BL_REGS8(x) (*(volatile unsigned char *)(x)) +#define BL_REGS16(x) (*(volatile unsigned short *)(x)) +#define BL_REGS32(x) (*(volatile unsigned long *)(x)) + +#define BL_READ_REGS8(reg,val) ((val) = BL_REGS8(reg)) +#define BL_READ_REGS16(reg,val) ((val) = BL_REGS16(reg)) +#define BL_READ_REGS32(reg,val) ((val) = BL_REGS32(reg)) +#define BL_READ_BYTE(reg,val) ((val) = BL_REGS8(reg)) +#define BL_READ_HWORD(reg,val) ((val) = BL_REGS16(reg)) /*half word; */ +#define BL_READ_WORD(reg,val) ((val) = BL_REGS32(reg)) /*32 bits */ + +#define BL_WRITE_REGS8(reg,val) (BL_REGS8(reg) = (val)) +#define BL_WRITE_REGS16(reg,val) (BL_REGS16(reg) = (val)) +#define BL_WRITE_REGS32(reg,val) (BL_REGS32(reg) = (val)) +#define BL_WRITE_BYTE(reg,val) (BL_REGS8(reg) = (val)) +#define BL_WRITE_HWORD(reg,val) (BL_REGS16(reg) = (val)) /*half word; */ +#define BL_WRITE_WORD(reg,val) (BL_REGS32(reg) = (val)) /*32 bits */ +// Write uint32 to a low 16-bit register and a high 16-bit register +#define WRITE2REGS(lo,hi,u32) \ + BL_WRITE_HWORD(lo, (uint16_t)((u32) & 0xffff)); \ + BL_WRITE_HWORD(hi, (uint16_t)(((u32) >> 16) & 0xffff)) + +#define BL_REGS8_SETBITS(reg, val) (BL_REGS8(reg) |= (uint8)(val)) +#define BL_REGS16_SETBITS(reg, val) (BL_REGS16(reg) |= (uint16)(val)) +#define BL_REGS32_SETBITS(reg, val) (BL_REGS32(reg) |= (val)) +#define BL_REGS8_CLRBITS(reg, val) (BL_REGS8(reg) = (uint8)(BL_REGS8(reg)&~(val))) +#define BL_REGS16_CLRBITS(reg, val) (BL_REGS16(reg) = (uint16)(BL_REGS16(reg)&~(val))) +#define BL_REGS32_CLRBITS(reg, val) (BL_REGS32(reg) = (BL_REGS32(reg)&~(val))) + +//============================================================================= +// ENUM TYPE DEFINITION +//============================================================================= + +/******************************************************************/ +/*! + * \enum SDIO_CMD_TYPE + * + *******************************************************************/ +typedef enum +{ + IOCTL_GET_CONFIG = 0, /*!< Get configuration info */ + + + /* HID IOCTLs*/ + IOCTL_HID_GET_BLOCK_SIZE, /*!< Get Block size */ + +} SDIO_CMD_TYPE; + +//============================================================================= +// FUNCTION DECLARATION +//============================================================================= +extern void sdio_GEN_CARD2HOST_INT(uint32_t port_id, uint16_t value); +extern uint32_t sdio_ioctl(uint32_t port_id, SDIO_CMD_TYPE cmd, void *arg); + +//============================================================================= +// Variable DECLARATION +//============================================================================= +extern volatile pHidSdio_RegMap_t SdioFuncReg[]; +extern uint8_t flag_mport[]; +#endif /* __BL602_SDU_H__ */ + diff --git a/drivers/bl602_driver/std_drv/inc/bl602_sec_dbg.h b/drivers/bl602_driver/std_drv/inc/bl602_sec_dbg.h new file mode 100644 index 00000000..b8843c6b --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_sec_dbg.h @@ -0,0 +1,82 @@ +/** + ****************************************************************************** + * @file bl602_sec_dbg.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_SEC_DBG_H__ +#define __BL602_SEC_DBG_H__ + +#include "sec_dbg_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SEC_DBG + * @{ + */ + +/** @defgroup SEC_DBG_Public_Types + * @{ + */ + +/*@} end of group SEC_DBG_Public_Types */ + +/** @defgroup SEC_DBG_Public_Constants + * @{ + */ + +/*@} end of group SEC_DBG_Public_Constants */ + +/** @defgroup SEC_DBG_Public_Macros + * @{ + */ + +/*@} end of group SEC_DBG_Public_Macros */ + +/** @defgroup SEC_DBG_Public_Functions + * @{ + */ +void Sec_Dbg_Read_Chip_ID(uint8_t id[8]); +void Sec_Dbg_Read_WiFi_MAC(uint8_t macAddr[6]); +uint32_t Sec_Dbg_Read_Dbg_Mode(void); +uint32_t Sec_Dbg_Read_Dbg_Enable(void); + +/*@} end of group SEC_DBG_Public_Functions */ + +/*@} end of group SEC_DBG */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_SEC_DBG_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_sec_eng.h b/drivers/bl602_driver/std_drv/inc/bl602_sec_eng.h new file mode 100644 index 00000000..21d7e582 --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_sec_eng.h @@ -0,0 +1,552 @@ +/** + ****************************************************************************** + * @file bl602_sec_eng.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_SEC_ENG_H__ +#define __BL602_SEC_ENG_H__ + +#include "sec_eng_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SEC_ENG + * @{ + */ + +/** @defgroup SEC_ENG_Public_Types + * @{ + */ + +/** + * @brief AES port type definition + */ +typedef enum { + SEC_ENG_AES_ID0, /*!< AES0 port define */ +}SEC_ENG_AES_ID_Type; + +/** + * @brief SHA port type definition + */ +typedef enum { + SEC_ENG_SHA_ID0, /*!< SHA0 port define */ +}SEC_ENG_SHA_ID_Type; + +/** + * @brief SHA type definition + */ +typedef enum { + SEC_ENG_SHA256, /*!< SHA type:SHA256 */ + SEC_ENG_SHA224, /*!< SHA type:SHA224 */ + SEC_ENG_SHA1, /*!< SHA type:SHA1 */ + SEC_ENG_SHA1_RSVD, /*!< SHA type:SHA1 */ +}SEC_ENG_SHA_Type; + +/** + * @brief AES type definition + */ +typedef enum { + SEC_ENG_AES_ECB, /*!< AES mode type:ECB */ + SEC_ENG_AES_CTR, /*!< AES mode type:CTR */ + SEC_ENG_AES_CBC, /*!< AES mode type:CBC */ +}SEC_ENG_AES_Type; + +/** + * @brief AES KEY type definition + */ +typedef enum { + SEC_ENG_AES_KEY_128BITS, /*!< AES KEY type:128 bits */ + SEC_ENG_AES_KEY_256BITS, /*!< AES KEY type:256 bits */ + SEC_ENG_AES_KEY_192BITS, /*!< AES KEY type:192 bits */ + SEC_ENG_AES_DOUBLE_KEY_128BITS, /*!< AES double KEY type:128 bits */ +}SEC_ENG_AES_Key_Type; + +/** + * @brief AES CTR mode counter type definition + */ +typedef enum { + SEC_ENG_AES_COUNTER_BYTE_4, /*!< AES CTR mode counter type:4 bytes */ + SEC_ENG_AES_COUNTER_BYTE_1, /*!< AES CTR mode counter type:1 byte */ + SEC_ENG_AES_COUNTER_BYTE_2, /*!< AES CTR mode counter type:2 bytes */ + SEC_ENG_AES_COUNTER_BYTE_3, /*!< AES CTR mode counter type:3 bytes */ +}SEC_ENG_AES_Counter_Type; + +/** + * @brief AES use new or old value type definition + */ +typedef enum { + SEC_ENG_AES_USE_NEW, /*!< Use new value */ + SEC_ENG_AES_USE_OLD, /*!< Use old value same as last one */ +}SEC_ENG_AES_ValueUsed_Type; + +/** + * @brief AES KEY source type definition + */ +typedef enum { + SEC_ENG_AES_KEY_SW, /*!< AES KEY from software */ + SEC_ENG_AES_KEY_HW, /*!< AES KEY from hardware */ +}SEC_ENG_AES_Key_Src_Type; + +/** + * @brief AES KEY source type definition + */ +typedef enum { + SEC_ENG_AES_ENCRYPTION, /*!< AES encryption */ + SEC_ENG_AES_DECRYPTION, /*!< AES decryption */ +}SEC_ENG_AES_EnDec_Type; + +/** + * @brief AES PKA register size type definition + */ +typedef enum { + SEC_ENG_PKA_REG_SIZE_8=1, /*!< Register size is 8 Bytes */ + SEC_ENG_PKA_REG_SIZE_16, /*!< Register size is 16 Bytes */ + SEC_ENG_PKA_REG_SIZE_32, /*!< Register size is 32 Bytes */ + SEC_ENG_PKA_REG_SIZE_64, /*!< Register size is 64 Bytes */ + SEC_ENG_PKA_REG_SIZE_96, /*!< Register size is 96 Bytes */ + SEC_ENG_PKA_REG_SIZE_128, /*!< Register size is 128 Bytes */ + SEC_ENG_PKA_REG_SIZE_192, /*!< Register size is 192 Bytes */ + SEC_ENG_PKA_REG_SIZE_256, /*!< Register size is 256 Bytes */ + SEC_ENG_PKA_REG_SIZE_384, /*!< Register size is 384 Bytes */ + SEC_ENG_PKA_REG_SIZE_512, /*!< Register size is 512 Bytes */ +}SEC_ENG_PKA_REG_SIZE_Type; + +/** + * @brief AES PKA register size type definition + */ +typedef enum { + SEC_ENG_PKA_OP_PPSEL, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MOD2N=0x11, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LDIV2N=0x12, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LMUL2N=0x13, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LDIV=0x14, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LSQR=0x15, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LMUL=0x16, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LSUB=0x17, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LADD=0x18, /*!< PKA operation type */ + SEC_ENG_PKA_OP_LCMP=0x19, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MDIV2=0x21, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MINV=0x22, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MEXP=0x23, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MSQR=0x24, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MMUL=0x25, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MREM=0x26, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MSUB=0x27, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MADD=0x28, /*!< PKA operation type */ + SEC_ENG_PKA_OP_RESIZE =0x31, /*!< PKA operation type */ + SEC_ENG_PKA_OP_MOVDAT=0x32, /*!< PKA operation type */ + SEC_ENG_PKA_OP_NLIR=0x33, /*!< PKA operation type */ + SEC_ENG_PKA_OP_SLIR=0x34, /*!< PKA operation type */ + SEC_ENG_PKA_OP_CLIR=0x35, /*!< PKA operation type */ + SEC_ENG_PKA_OP_CFLIRI_BUFFER=0x36, /*!< PKA operation type */ + SEC_ENG_PKA_OP_CTLIRI_PLD=0x37, /*!< PKA operation type */ + SEC_ENG_PKA_OP_CFLIR_BUFFER=0x38, /*!< PKA operation type */ + SEC_ENG_PKA_OP_CTLIR_PLD=0x39, /*!< PKA operation type */ +}SEC_ENG_PKA_OP_Type; + +/** + * @brief Sec Eng Interrupt Type Def + */ +typedef enum { + SEC_ENG_INT_TRNG, /*!< Sec Eng Trng Interrupt Type */ + SEC_ENG_INT_AES, /*!< Sec Eng Aes Interrupt Type */ + SEC_ENG_INT_SHA, /*!< Sec Eng Sha Interrupt Type */ + SEC_ENG_INT_PKA, /*!< Sec Eng Pka Interrupt Type */ + SEC_ENG_INT_CDET, /*!< Sec Eng Cdet Interrupt Type */ + SEC_ENG_INT_GMAC, /*!< Sec Eng Gmac Interrupt Type */ + SEC_ENG_INT_ALL, /*!< Sec Eng All Interrupt Types */ +}SEC_ENG_INT_Type; + +/** + * @brief SEC_ENG SHA context + */ +typedef struct { + uint32_t total[2]; /*!< Number of bytes processed */ + uint32_t *shaBuf; /*!< Data not processed but in this temp buffer */ + uint32_t *shaPadding; /*!< Padding data */ + uint8_t shaFeed; /*!< Sha has feed data */ +}SEC_Eng_SHA256_Ctx; + +/** + * @brief SEC_ENG SHA link mode context + */ +typedef struct { + uint32_t total[2]; /*!< Number of bytes processed */ + uint32_t *shaBuf; /*!< Data not processed but in this temp buffer */ + uint32_t *shaPadding; /*!< Padding data */ + uint32_t linkAddr; /*!< Link configure address */ +}SEC_Eng_SHA256_Link_Ctx; + +/** + * @brief SEC_ENG AES context + */ +typedef struct { + uint8_t aesFeed; /*!< AES has feed data */ + SEC_ENG_AES_Type mode; /*!< AES mode */ +}SEC_Eng_AES_Ctx; + +/** + * @brief SEC_ENG SHA link config structure type definition + */ +typedef struct { + uint32_t :2; /*!< [1:0]reserved */ + uint32_t shaMode:3; /*!< [4:2]Sha-256/sha-224/sha-1/sha-1 */ + uint32_t :1; /*!< [5]reserved */ + uint32_t shaHashSel:1; /*!< [6]New hash or accumulate last hash */ + uint32_t :2; /*!< [8:7]reserved */ + uint32_t shaIntClr:1; /*!< [9]Clear interrupt */ + uint32_t shaIntSet:1; /*!< [10]Set interrupt */ + uint32_t :5; /*!< [15:11]reserved */ + uint32_t shaMsgLen:16; /*!< [31:16]Number of 512-bit block */ + uint32_t shaSrcAddr; /*!< Message source address */ + uint32_t result[8]; /*!< Result of SHA */ +}__attribute__ ((aligned(4)))SEC_Eng_SHA_Link_Config_Type; + +/** + * @brief SEC_ENG AES link config structure type definition + */ +typedef struct { + uint32_t :3; /*!< [2:0]Reserved */ + uint32_t aesMode:2; /*!< [4:3]128-bit/256-bit/192-bit/128-bit-double key mode select */ + uint32_t aesDecEn:1; /*!< [5]Encode or decode */ + uint32_t aesDecKeySel:1; /*!< [6]Use new key or use same key as last one */ + uint32_t aesHwKeyEn:1; /*!< [7]Enable or disable using hardware hey */ + uint32_t :1; /*!< [8]Reserved */ + uint32_t aesIntClr:1; /*!< [9]Clear interrupt */ + uint32_t aesIntSet:1; /*!< [10]Set interrupt */ + uint32_t :1; /*!< [11]Reserved */ + uint32_t aesBlockMode:2; /*!< [13:12]ECB/CTR/CBC mode select */ + uint32_t aesIVSel:1; /*!< [14]Use new iv or use same iv as last one */ + uint32_t :1; /*!< [15]Reserved */ + uint32_t aesMsgLen:16; /*!< [31:16]Number of 128-bit block */ + uint32_t aesSrcAddr; /*!< Message source address */ + uint32_t aesDstAddr; /*!< Message destination address */ + uint32_t aesIV0; /*!< Big endian initial vector(MSB) */ + uint32_t aesIV1; /*!< Big endian initial vector */ + uint32_t aesIV2; /*!< Big endian initial vector */ + uint32_t aesIV3; /*!< Big endian initial vector(LSB)(CTR mode:counter initial value) */ + uint32_t aesKey0; /*!< Big endian aes key(aes-128/256 key MSB) */ + uint32_t aesKey1; /*!< Big endian aes key */ + uint32_t aesKey2; /*!< Big endian aes key */ + uint32_t aesKey3; /*!< Big endian aes key(aes-128 key LSB) */ + uint32_t aesKey4; /*!< Big endian aes key */ + uint32_t aesKey5; /*!< Big endian aes key */ + uint32_t aesKey6; /*!< Big endian aes key */ + uint32_t aesKey7; /*!< Big endian aes key(aes-256 key LSB) */ +}__attribute__ ((aligned(4)))SEC_Eng_AES_Link_Config_Type; + +/** + * @brief SEC_ENG GMAC link config structure type definition + */ +typedef struct { + uint32_t :9; /*!< [8:0]reserved */ + uint32_t gmacIntClr:1; /*!< [9]Clear interrupt */ + uint32_t gmacIntSet:1; /*!< [10]Set interrupt */ + uint32_t :5; /*!< [15:11]reserved */ + uint32_t gmacMsgLen:16; /*!< [31:16]Number of 128-bit block */ + uint32_t gmacSrcAddr; /*!< Message source address */ + uint32_t gmacKey0; /*!< GMAC key */ + uint32_t gmacKey1; /*!< GMAC key */ + uint32_t gmacKey2; /*!< GMAC key */ + uint32_t gmacKey3; /*!< GMAC key */ + uint32_t result[4]; /*!< Result of GMAC */ +}__attribute__ ((aligned(4)))SEC_Eng_GMAC_Link_Config_Type; + +/*@} end of group SEC_ENG_Public_Types */ + +/** @defgroup SEC_ENG_Public_Constants + * @{ + */ + +/** @defgroup SEC_ENG_AES_ID_TYPE + * @{ + */ +#define IS_SEC_ENG_AES_ID_TYPE(type) (((type) == SEC_ENG_AES_ID0)) + +/** @defgroup SEC_ENG_SHA_ID_TYPE + * @{ + */ +#define IS_SEC_ENG_SHA_ID_TYPE(type) (((type) == SEC_ENG_SHA_ID0)) + +/** @defgroup SEC_ENG_SHA_TYPE + * @{ + */ +#define IS_SEC_ENG_SHA_TYPE(type) (((type) == SEC_ENG_SHA256) || \ + ((type) == SEC_ENG_SHA224) || \ + ((type) == SEC_ENG_SHA1) || \ + ((type) == SEC_ENG_SHA1_RSVD)) + +/** @defgroup SEC_ENG_AES_TYPE + * @{ + */ +#define IS_SEC_ENG_AES_TYPE(type) (((type) == SEC_ENG_AES_ECB) || \ + ((type) == SEC_ENG_AES_CTR) || \ + ((type) == SEC_ENG_AES_CBC)) + +/** @defgroup SEC_ENG_AES_KEY_TYPE + * @{ + */ +#define IS_SEC_ENG_AES_KEY_TYPE(type) (((type) == SEC_ENG_AES_KEY_128BITS) || \ + ((type) == SEC_ENG_AES_KEY_256BITS) || \ + ((type) == SEC_ENG_AES_KEY_192BITS) || \ + ((type) == SEC_ENG_AES_DOUBLE_KEY_128BITS)) + +/** @defgroup SEC_ENG_AES_COUNTER_TYPE + * @{ + */ +#define IS_SEC_ENG_AES_COUNTER_TYPE(type) (((type) == SEC_ENG_AES_COUNTER_BYTE_4) || \ + ((type) == SEC_ENG_AES_COUNTER_BYTE_1) || \ + ((type) == SEC_ENG_AES_COUNTER_BYTE_2) || \ + ((type) == SEC_ENG_AES_COUNTER_BYTE_3)) + +/** @defgroup SEC_ENG_AES_VALUEUSED_TYPE + * @{ + */ +#define IS_SEC_ENG_AES_VALUEUSED_TYPE(type) (((type) == SEC_ENG_AES_USE_NEW) || \ + ((type) == SEC_ENG_AES_USE_OLD)) + +/** @defgroup SEC_ENG_AES_KEY_SRC_TYPE + * @{ + */ +#define IS_SEC_ENG_AES_KEY_SRC_TYPE(type) (((type) == SEC_ENG_AES_KEY_SW) || \ + ((type) == SEC_ENG_AES_KEY_HW)) + +/** @defgroup SEC_ENG_AES_ENDEC_TYPE + * @{ + */ +#define IS_SEC_ENG_AES_ENDEC_TYPE(type) (((type) == SEC_ENG_AES_ENCRYPTION) || \ + ((type) == SEC_ENG_AES_DECRYPTION)) + +/** @defgroup SEC_ENG_PKA_REG_SIZE_TYPE + * @{ + */ +#define IS_SEC_ENG_PKA_REG_SIZE_TYPE(type) (((type) == SEC_ENG_PKA_REG_SIZE_8) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_16) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_32) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_64) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_96) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_128) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_192) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_256) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_384) || \ + ((type) == SEC_ENG_PKA_REG_SIZE_512)) + +/** @defgroup SEC_ENG_PKA_OP_TYPE + * @{ + */ +#define IS_SEC_ENG_PKA_OP_TYPE(type) (((type) == SEC_ENG_PKA_OP_PPSEL) || \ + ((type) == SEC_ENG_PKA_OP_MOD2N) || \ + ((type) == SEC_ENG_PKA_OP_LDIV2N) || \ + ((type) == SEC_ENG_PKA_OP_LMUL2N) || \ + ((type) == SEC_ENG_PKA_OP_LDIV) || \ + ((type) == SEC_ENG_PKA_OP_LSQR) || \ + ((type) == SEC_ENG_PKA_OP_LMUL) || \ + ((type) == SEC_ENG_PKA_OP_LSUB) || \ + ((type) == SEC_ENG_PKA_OP_LADD) || \ + ((type) == SEC_ENG_PKA_OP_LCMP) || \ + ((type) == SEC_ENG_PKA_OP_MDIV2) || \ + ((type) == SEC_ENG_PKA_OP_MINV) || \ + ((type) == SEC_ENG_PKA_OP_MEXP) || \ + ((type) == SEC_ENG_PKA_OP_MSQR) || \ + ((type) == SEC_ENG_PKA_OP_MMUL) || \ + ((type) == SEC_ENG_PKA_OP_MREM) || \ + ((type) == SEC_ENG_PKA_OP_MSUB) || \ + ((type) == SEC_ENG_PKA_OP_MADD) || \ + ((type) == SEC_ENG_PKA_OP_RESIZE ) || \ + ((type) == SEC_ENG_PKA_OP_MOVDAT) || \ + ((type) == SEC_ENG_PKA_OP_NLIR) || \ + ((type) == SEC_ENG_PKA_OP_SLIR) || \ + ((type) == SEC_ENG_PKA_OP_CLIR) || \ + ((type) == SEC_ENG_PKA_OP_CFLIRI_BUFFER) || \ + ((type) == SEC_ENG_PKA_OP_CTLIRI_PLD) || \ + ((type) == SEC_ENG_PKA_OP_CFLIR_BUFFER) || \ + ((type) == SEC_ENG_PKA_OP_CTLIR_PLD)) + +/** @defgroup SEC_ENG_INT_TYPE + * @{ + */ +#define IS_SEC_ENG_INT_TYPE(type) (((type) == SEC_ENG_INT_TRNG) || \ + ((type) == SEC_ENG_INT_AES) || \ + ((type) == SEC_ENG_INT_SHA) || \ + ((type) == SEC_ENG_INT_PKA) || \ + ((type) == SEC_ENG_INT_CDET) || \ + ((type) == SEC_ENG_INT_GMAC) || \ + ((type) == SEC_ENG_INT_ALL)) + +/*@} end of group SEC_ENG_Public_Constants */ + +/** @defgroup SEC_ENG_Public_Macros + * @{ + */ +#define SEC_ENG_PKA_STATUS_LAST_OPC_OFFSET 24 +#define SEC_ENG_PKA_STATUS_LAST_OPC_MASK 0x01000000 + +/*@} end of group SEC_ENG_Public_Macros */ + +/** @defgroup SEC_ENG_Public_Functions + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +void SEC_GMAC_IRQHandler(void); +void SEC_CDET_IRQHandler(void); +void SEC_TRNG_IRQHandler(void); +void SEC_PKA_IRQHandler(void); +void SEC_AES_IRQHandler(void); +void SEC_SHA_IRQHandler(void); +#endif +void Sec_Eng_SHA256_Init(SEC_Eng_SHA256_Ctx *shaCtx,SEC_ENG_SHA_ID_Type shaNo,SEC_ENG_SHA_Type type, + uint32_t shaTmpBuf[16], +uint32_t padding[16]); +void Sec_Eng_SHA_Start(SEC_ENG_SHA_ID_Type shaNo); +BL_Err_Type Sec_Eng_SHA256_Update(SEC_Eng_SHA256_Ctx *shaCtx,SEC_ENG_SHA_ID_Type shaNo,const uint8_t *input, + uint32_t len); +BL_Err_Type Sec_Eng_SHA256_Finish(SEC_Eng_SHA256_Ctx *shaCtx,SEC_ENG_SHA_ID_Type shaNo,uint8_t *hash); +void Sec_Eng_SHA_Enable_Link(SEC_ENG_SHA_ID_Type shaNo); +void Sec_Eng_SHA_Disable_Link(SEC_ENG_SHA_ID_Type shaNo); +void Sec_Eng_SHA256_Link_Init(SEC_Eng_SHA256_Link_Ctx *shaCtx,SEC_ENG_SHA_ID_Type shaNo,uint32_t linkAddr, + uint32_t shaTmpBuf[16],uint32_t padding[16]); +BL_Err_Type Sec_Eng_SHA256_Link_Update(SEC_Eng_SHA256_Link_Ctx *shaCtx,SEC_ENG_SHA_ID_Type shaNo, + const uint8_t *input, uint32_t len); +BL_Err_Type Sec_Eng_SHA256_Link_Finish(SEC_Eng_SHA256_Link_Ctx *shaCtx,SEC_ENG_SHA_ID_Type shaNo, + uint8_t *hash); +BL_Err_Type Sec_Eng_AES_Init(SEC_Eng_AES_Ctx *aesCtx,SEC_ENG_AES_ID_Type aesNo,SEC_ENG_AES_Type aesType, + SEC_ENG_AES_Key_Type keyType,SEC_ENG_AES_EnDec_Type enDecType); +void Sec_Eng_AES_Enable_LE(SEC_ENG_AES_ID_Type aesNo); +void Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID_Type aesNo); +void Sec_Eng_AES_Enable_Link(SEC_ENG_AES_ID_Type aesNo); +void Sec_Eng_AES_Disable_Link(SEC_ENG_AES_ID_Type aesNo); +BL_Err_Type Sec_Eng_AES_Link_Work(SEC_ENG_AES_ID_Type aesNo,uint32_t linkAddr,const uint8_t *in,uint32_t len, + uint8_t *out); +void Sec_Eng_AES_Set_Hw_Key_Src(SEC_ENG_AES_ID_Type aesNo,uint8_t src); +void Sec_Eng_AES_Set_Key_IV(SEC_ENG_AES_ID_Type aesNo,SEC_ENG_AES_Key_Src_Type keySrc,const uint8_t *key, + const uint8_t *iv); +void Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID_Type aesNo,SEC_ENG_AES_Key_Src_Type keySrc,const uint8_t *key, + const uint8_t *iv); +void Sec_Eng_AES_Set_Counter_Byte(SEC_ENG_AES_ID_Type aesNo,SEC_ENG_AES_Counter_Type counterType); +BL_Err_Type Sec_Eng_AES_Crypt(SEC_Eng_AES_Ctx *aesCtx,SEC_ENG_AES_ID_Type aesNo,const uint8_t *in, uint32_t len, + uint8_t *out); +BL_Err_Type Sec_Eng_AES_Finish(SEC_ENG_AES_ID_Type aesNo); +BL_Err_Type Sec_Eng_Trng_Enable(void); +void Sec_Eng_Trng_Int_Enable(void); +void Sec_Eng_Trng_Int_Disable(void); +BL_Err_Type Sec_Eng_Trng_Read(uint8_t data[32]); +void Sec_Eng_Trng_Int_Read_Trigger(void); +void Sec_Eng_Trng_Int_Read(uint8_t data[32]); +void Sec_Eng_Trng_Disable(void); +void Sec_Eng_PKA_Reset(void); +void Sec_Eng_PKA_BigEndian_Enable(void); +void Sec_Eng_PKA_LittleEndian_Enable(void); +void Sec_Eng_PKA_Write_Data( SEC_ENG_PKA_REG_SIZE_Type regType,uint8_t regIndex,const uint32_t *data,uint16_t size, + uint8_t lastOp); +void Sec_Eng_PKA_Read_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIdx, uint32_t *result, uint8_t retSize); +void Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_Type dRegType, uint8_t dRegIdx, uint8_t size,uint8_t lastOp); +void Sec_Eng_PKA_Write_Immediate( SEC_ENG_PKA_REG_SIZE_Type regType,uint8_t regIndex,uint32_t data,uint8_t lastOp); +void Sec_Eng_PKA_NREG(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,uint8_t lastOp); +void Sec_Eng_PKA_Move_Data(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,uint8_t lastOp); +void Sec_Eng_PKA_RESIZE(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,uint8_t lastOp); +void Sec_Eng_PKA_MADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, +uint8_t s1RegType, + uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx,uint8_t lastOp); +void Sec_Eng_PKA_MSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, +uint8_t s1RegType, + uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx,uint8_t lastOp); +void Sec_Eng_PKA_MREM(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, +uint8_t s2RegType, + uint8_t s2RegIdx,uint8_t lastOp); +void Sec_Eng_PKA_MMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, +uint8_t s1RegType, + uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx,uint8_t lastOp); +void Sec_Eng_PKA_MSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, +uint8_t s2RegType, + uint8_t s2RegIdx,uint8_t lastOp); +void Sec_Eng_PKA_MEXP(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, +uint8_t s1RegType, + uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx,uint8_t lastOp); +void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, +uint8_t s2RegType, + uint8_t s2RegIdx,uint8_t lastOp); +void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, +uint8_t s2RegType, + uint8_t s2RegIdx,uint8_t lastOp); +void Sec_Eng_PKA_LCMP(uint8_t *cout, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx); +void Sec_Eng_PKA_LADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, +uint8_t s1RegType, + uint8_t s1RegIdx,uint8_t lastOp); +void Sec_Eng_PKA_LSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, +uint8_t s1RegType, + uint8_t s1RegIdx,uint8_t lastOp); +void Sec_Eng_PKA_LMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, +uint8_t s1RegType, + uint8_t s1RegIdx,uint8_t lastOp); +void Sec_Eng_PKA_LSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,uint8_t lastOp); +void Sec_Eng_PKA_LDIV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, +uint8_t s2RegType, + uint8_t s2RegIdx,uint8_t lastOp); +void Sec_Eng_PKA_LMUL2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, +uint16_t bit_shift, + uint8_t lastOp); +void Sec_Eng_PKA_LDIV2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, +uint16_t bit_shift, + uint8_t lastOp); +void Sec_Eng_PKA_LMOD2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, +uint16_t bit_shift, + uint8_t lastOp); +void Sec_Eng_PKA_GF2Mont(uint8_t dRegType, uint8_t dRegIdx, uint8_t sRegType, uint8_t sRegIdx,uint32_t size, + uint8_t tRegType, uint8_t tRegIdx,uint8_t pRegType, uint8_t pRegIdx); +void Sec_Eng_PKA_Mont2GF(uint8_t dRegType, uint8_t dRegIdx, uint8_t aRegType, uint8_t aRegIdx, uint8_t invrRegType, + uint8_t invrRegIdx, +uint8_t tRegType, uint8_t tRegIdx,uint8_t pRegType, uint8_t pRegIdx); +void Sec_Eng_GMAC_Enable_LE(void); +void Sec_Eng_GMAC_Enable_BE(void); +void Sec_Eng_GMAC_Enable_Link(void); +void Sec_Eng_GMAC_Disable_Link(void); +BL_Err_Type Sec_Eng_GMAC_Link_Work(uint32_t linkAddr,const uint8_t *in,uint32_t len,uint8_t *out); +void SEC_Eng_IntMask(SEC_ENG_INT_Type intType, BL_Mask_Type intMask); +void SEC_Eng_ClrIntStatus(SEC_ENG_INT_Type intType); +void SEC_Eng_Int_Callback_Install(SEC_ENG_INT_Type intType,intCallback_Type* cbFun); +BL_Sts_Type SEC_Eng_GetIntStatus(SEC_ENG_INT_Type intType); +/*----------*/ +void SEC_Eng_Turn_On_Sec_Ring(void); +void SEC_Eng_Turn_Off_Sec_Ring(void); +/*----------*/; + +/*@} end of group SEC_ENG_Public_Functions */ + +/*@} end of group SEC_ENG */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_SEC_ENG_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_sf_cfg.h b/drivers/bl602_driver/std_drv/inc/bl602_sf_cfg.h new file mode 100644 index 00000000..ad4bb0f7 --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_sf_cfg.h @@ -0,0 +1,112 @@ +/** + ****************************************************************************** + * @file bl602_sf_cfg.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_SF_CFG_H__ +#define __BL602_SF_CFG_H__ + +#include "string.h" +#include "bl602_sflash.h" +#include "bl602_sf_ctrl.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CFG + * @{ + */ + +/** @defgroup SF_CFG_Public_Types + * @{ + */ + +/*@} end of group SF_CFG_Public_Types */ + +/** @defgroup SF_CFG_Public_Constants + * @{ + */ + +/*@} end of group SF_CFG_Public_Constants */ + +/** @defgroup SF_CFG_Public_Macros + * @{ + */ +/*Flash option 0*/ +/*Flash CLK*/ +#define BFLB_EXTFLASH_CLK0_GPIO GLB_GPIO_PIN_22 +/*FLASH CS*/ +#define BFLB_EXTFLASH_CS0_GPIO GLB_GPIO_PIN_21 +/*FLASH DATA*/ +#define BFLB_EXTFLASH_DATA00_GPIO GLB_GPIO_PIN_20 +#define BFLB_EXTFLASH_DATA10_GPIO GLB_GPIO_PIN_19 +#define BFLB_EXTFLASH_DATA20_GPIO GLB_GPIO_PIN_18 +#define BFLB_EXTFLASH_DATA30_GPIO GLB_GPIO_PIN_17 +/*Flash option 1*/ +/*Flash CLK*/ +#define BFLB_EXTFLASH_CLK1_GPIO GLB_GPIO_PIN_22 +/*FLASH CS*/ +#define BFLB_EXTFLASH_CS1_GPIO GLB_GPIO_PIN_21 +/*FLASH DATA*/ +#define BFLB_EXTFLASH_DATA01_GPIO GLB_GPIO_PIN_20 +#define BFLB_EXTFLASH_DATA11_GPIO GLB_GPIO_PIN_0 +#define BFLB_EXTFLASH_DATA21_GPIO GLB_GPIO_PIN_1 +#define BFLB_EXTFLASH_DATA31_GPIO GLB_GPIO_PIN_2 +#define BFLB_FLASH_CFG_DESWAP 1 +#define BFLB_FLASH_CFG_EXT0_17_22 2 +#define BFLB_FLASH_CFG_EXT1_0_2_20_22 3 +#define BFLB_FLASH_ID_VALID_FLAG 0x80000000 +#define BFLB_FLASH_ID_VALID_MASK 0x7FFFFFFF + +/*@} end of group SF_CFG_Public_Macros */ + +/** @defgroup SF_CFG_Public_Functions + * @{ + */ +BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID,SPI_Flash_Cfg_Type * pFlashCfg); +void SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg,uint8_t restoreDefault); +void SF_Cfg_Restore_GPIO17_Fun(uint8_t fun); +uint32_t SF_Cfg_Flash_Identify(uint8_t callFromFlash,uint32_t autoScan,uint32_t flashPinCfg,uint8_t restoreDefault, + SPI_Flash_Cfg_Type * pFlashCfg); +void SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin); +void SF_Cfg_Init_Internal_Flash_Gpio(void); +void SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin); + +/*@} end of group SF_CFG_Public_Functions */ + +/*@} end of group SF_CFG */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_SF_CFG_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_sf_cfg_ext.h b/drivers/bl602_driver/std_drv/inc/bl602_sf_cfg_ext.h new file mode 100644 index 00000000..11ed4fbb --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_sf_cfg_ext.h @@ -0,0 +1,82 @@ +/** + ****************************************************************************** + * @file bl602_sf_cfg_ext.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_SF_CFG_EXT_H__ +#define __BL602_SF_CFG_EXT_H__ + +#include "string.h" +#include "bl602_sflash.h" +#include "bl602_sf_ctrl.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CFG_EXT + * @{ + */ + +/** @defgroup SF_CFG_EXT_Public_Types + * @{ + */ + +/*@} end of group SF_CFG_EXT_Public_Types */ + +/** @defgroup SF_CFG_EXT_Public_Constants + * @{ + */ + +/*@} end of group SF_CFG_EXT_Public_Constants */ + +/** @defgroup SF_CFG_EXT_Public_Macros + * @{ + */ + +/*@} end of group SF_CFG_EXT_Public_Macros */ + +/** @defgroup SF_CFG_EXT_Public_Functions + * @{ + */ +BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID,SPI_Flash_Cfg_Type * pFlashCfg); +uint32_t SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash,uint32_t autoScan,uint32_t flashPinCfg, + uint8_t restoreDefault,SPI_Flash_Cfg_Type * pFlashCfg); + +/*@} end of group SF_CFG_EXT_Public_Functions */ + +/*@} end of group SF_CFG_EXT */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_SF_CFG_EXT_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_sf_ctrl.h b/drivers/bl602_driver/std_drv/inc/bl602_sf_ctrl.h new file mode 100644 index 00000000..ba3f0622 --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_sf_ctrl.h @@ -0,0 +1,325 @@ +/** + ****************************************************************************** + * @file bl602_sf_ctrl.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_SF_CTRL_H__ +#define __BL602_SF_CTRL_H__ + +#include "sf_ctrl_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CTRL + * @{ + */ + +/** @defgroup SF_CTRL_Public_Types + * @{ + */ + +/** + * @brief Serial flash pad select type definition + */ +typedef enum { + SF_CTRL_EMBEDDED_SEL, /*!< Embedded flash select */ + SF_CTRL_EXTERNAL_17TO22_SEL, /*!< External flash select gpio 17-22 */ + SF_CTRL_EXTERNAL_0TO2_20TO22_SEL, /*!< External flash select gpio 0-2 and 20-22 */ +}SF_Ctrl_Pad_Sel; + +/** + * @brief Serial flash controller owner type definition + */ +typedef enum { + SF_CTRL_OWNER_SAHB, /*!< System AHB bus control serial flash controller */ + SF_CTRL_OWNER_IAHB, /*!< I-Code AHB bus control serial flash controller */ +}SF_Ctrl_Owner_Type; + +/** + * @brief Serial flash controller select clock type definition + */ +typedef enum { + SF_CTRL_SAHB_CLOCK, /*!< Serial flash controller select default sahb clock */ + SF_CTRL_FLASH_CLOCK, /*!< Serial flash controller select flash clock */ +}SF_Ctrl_Sahb_Type; + +/** + * @brief Serial flash controller owner type definition + */ +typedef enum { + HIGH_SPEED_MODE_CLOCK, /*!< Serial flash controller high speed mode clk_ahb>clk_sf */ + REMOVE_CLOCK_CONSTRAIN, /*!< Serial flash controller remove clock constrain */ +}SF_Ctrl_Ahb2sif_Type; + +/** + * @brief Read and write type definition + */ +typedef enum { + SF_CTRL_READ, /*!< Serail flash read command flag */ + SF_CTRL_WRITE, /*!< Serail flash write command flag */ +}SF_Ctrl_RW_Type; + +/** + * @brief Serail flash interface IO type definition + */ +typedef enum { + SF_CTRL_NIO_MODE, /*!< Normal IO mode define */ + SF_CTRL_DO_MODE, /*!< Dual Output mode define */ + SF_CTRL_QO_MODE, /*!< Quad Output mode define */ + SF_CTRL_DIO_MODE, /*!< Dual IO mode define */ + SF_CTRL_QIO_MODE, /*!< Quad IO mode define */ +}SF_Ctrl_IO_Type; + +/** + * @brief Serail flash controller interface mode type definition + */ +typedef enum { + SF_CTRL_SPI_MODE, /*!< SPI mode define */ + SF_CTRL_QPI_MODE, /*!< QPI mode define */ +}SF_Ctrl_Mode_Type; + +/** + * @brief Serail flash controller command mode type definition + */ +typedef enum { + SF_CTRL_CMD_1_LINE, /*!< Command in one line mode */ + SF_CTRL_CMD_4_LINES, /*!< Command in four lines mode */ +}SF_Ctrl_Cmd_Mode_Type; + +/** + * @brief Serail flash controller address mode type definition + */ +typedef enum { + SF_CTRL_ADDR_1_LINE, /*!< Address in one line mode */ + SF_CTRL_ADDR_2_LINES, /*!< Address in two lines mode */ + SF_CTRL_ADDR_4_LINES, /*!< Address in four lines mode */ +}SF_Ctrl_Addr_Mode_Type; + +/** + * @brief Serail flash controller dummy mode type definition + */ +typedef enum { + SF_CTRL_DUMMY_1_LINE, /*!< Dummy in one line mode */ + SF_CTRL_DUMMY_2_LINES, /*!< Dummy in two lines mode */ + SF_CTRL_DUMMY_4_LINES, /*!< Dummy in four lines mode */ +}SF_Ctrl_Dmy_Mode_Type; + +/** + * @brief Serail flash controller data mode type definition + */ +typedef enum { + SF_CTRL_DATA_1_LINE, /*!< Data in one line mode */ + SF_CTRL_DATA_2_LINES, /*!< Data in two lines mode */ + SF_CTRL_DATA_4_LINES, /*!< Data in four lines mode */ +}SF_Ctrl_Data_Mode_Type; + +/** + * @brief Serail flash controller AES type definition + */ +typedef enum { + SF_CTRL_AES_128BITS, /*!< Serail flash AES key 128 bits length */ + SF_CTRL_AES_256BITS, /*!< Serail flash AES key 256 bits length */ + SF_CTRL_AES_192BITS, /*!< Serail flash AES key 192 bits length */ + SF_CTRL_AES_128BITS_DOUBLE_KEY, /*!< Serail flash AES key 128 bits length double key */ +}SF_Ctrl_AES_Key_Type; + +/** + * @brief Serail flash controller configuration structure type definition + */ +typedef struct { + SF_Ctrl_Owner_Type owner; /*!< Sflash interface bus owner */ + SF_Ctrl_Sahb_Type sahbClock; /*!< Sflash clock sahb sram select */ + SF_Ctrl_Ahb2sif_Type ahb2sifMode; /*!< Sflash ahb2sif mode */ + uint8_t clkDelay; /*!< Clock count for read due to pad delay */ + uint8_t clkInvert; /*!< Clock invert */ + uint8_t rxClkInvert; /*!< RX clock invert */ + uint8_t doDelay; /*!< Data out delay */ + uint8_t diDelay; /*!< Data in delay */ + uint8_t oeDelay; /*!< Output enable delay */ +}SF_Ctrl_Cfg_Type; + +/** + * @brief Serail flash command configuration structure type definition + */ +typedef struct { + uint8_t rwFlag; /*!< Read write flag */ + SF_Ctrl_Cmd_Mode_Type cmdMode; /*!< Command mode */ + SF_Ctrl_Addr_Mode_Type addrMode; /*!< Address mode */ + uint8_t addrSize; /*!< Address size */ + uint8_t dummyClks; /*!< Dummy clocks */ + SF_Ctrl_Dmy_Mode_Type dummyMode; /*!< Dummy mode */ + SF_Ctrl_Data_Mode_Type dataMode; /*!< Data mode */ + uint8_t rsv[1]; /*!< */ + uint32_t nbData; /*!< Transfer number of bytes */ + uint32_t cmdBuf[2]; /*!< Command buffer */ +}SF_Ctrl_Cmd_Cfg_Type; + +/*@} end of group SF_CTRL_Public_Types */ + +/** @defgroup SF_CTRL_Public_Constants + * @{ + */ + +/** @defgroup SF_CTRL_PAD_SEL + * @{ + */ +#define IS_SF_CTRL_PAD_SEL(type) (((type) == SF_CTRL_EMBEDDED_SEL) || \ + ((type) == SF_CTRL_EXTERNAL_17TO22_SEL) || \ + ((type) == SF_CTRL_EXTERNAL_0TO2_20TO22_SEL)) + +/** @defgroup SF_CTRL_OWNER_TYPE + * @{ + */ +#define IS_SF_CTRL_OWNER_TYPE(type) (((type) == SF_CTRL_OWNER_SAHB) || \ + ((type) == SF_CTRL_OWNER_IAHB)) + +/** @defgroup SF_CTRL_SAHB_TYPE + * @{ + */ +#define IS_SF_CTRL_SAHB_TYPE(type) (((type) == SF_CTRL_SAHB_CLOCK) || \ + ((type) == SF_CTRL_FLASH_CLOCK)) + +/** @defgroup SF_CTRL_AHB2SIF_TYPE + * @{ + */ +#define IS_SF_CTRL_AHB2SIF_TYPE(type) (((type) == HIGH_SPEED_MODE_CLOCK) || \ + ((type) == REMOVE_CLOCK_CONSTRAIN)) + +/** @defgroup SF_CTRL_RW_TYPE + * @{ + */ +#define IS_SF_CTRL_RW_TYPE(type) (((type) == SF_CTRL_READ) || \ + ((type) == SF_CTRL_WRITE)) + +/** @defgroup SF_CTRL_IO_TYPE + * @{ + */ +#define IS_SF_CTRL_IO_TYPE(type) (((type) == SF_CTRL_NIO_MODE) || \ + ((type) == SF_CTRL_DO_MODE) || \ + ((type) == SF_CTRL_QO_MODE) || \ + ((type) == SF_CTRL_DIO_MODE) || \ + ((type) == SF_CTRL_QIO_MODE)) + +/** @defgroup SF_CTRL_MODE_TYPE + * @{ + */ +#define IS_SF_CTRL_MODE_TYPE(type) (((type) == SF_CTRL_SPI_MODE) || \ + ((type) == SF_CTRL_QPI_MODE)) + +/** @defgroup SF_CTRL_CMD_MODE_TYPE + * @{ + */ +#define IS_SF_CTRL_CMD_MODE_TYPE(type) (((type) == SF_CTRL_CMD_1_LINE) || \ + ((type) == SF_CTRL_CMD_4_LINES)) + +/** @defgroup SF_CTRL_ADDR_MODE_TYPE + * @{ + */ +#define IS_SF_CTRL_ADDR_MODE_TYPE(type) (((type) == SF_CTRL_ADDR_1_LINE) || \ + ((type) == SF_CTRL_ADDR_2_LINES) || \ + ((type) == SF_CTRL_ADDR_4_LINES)) + +/** @defgroup SF_CTRL_DMY_MODE_TYPE + * @{ + */ +#define IS_SF_CTRL_DMY_MODE_TYPE(type) (((type) == SF_CTRL_DUMMY_1_LINE) || \ + ((type) == SF_CTRL_DUMMY_2_LINES) || \ + ((type) == SF_CTRL_DUMMY_4_LINES)) + +/** @defgroup SF_CTRL_DATA_MODE_TYPE + * @{ + */ +#define IS_SF_CTRL_DATA_MODE_TYPE(type) (((type) == SF_CTRL_DATA_1_LINE) || \ + ((type) == SF_CTRL_DATA_2_LINES) || \ + ((type) == SF_CTRL_DATA_4_LINES)) + +/** @defgroup SF_CTRL_AES_KEY_TYPE + * @{ + */ +#define IS_SF_CTRL_AES_KEY_TYPE(type) (((type) == SF_CTRL_AES_128BITS) || \ + ((type) == SF_CTRL_AES_256BITS) || \ + ((type) == SF_CTRL_AES_192BITS) || \ + ((type) == SF_CTRL_AES_128BITS_DOUBLE_KEY)) + +/*@} end of group SF_CTRL_Public_Constants */ + +/** @defgroup SF_CTRL_Public_Macros + * @{ + */ +#define SF_CTRL_NO_ADDRESS 0xFFFFFFFF +#define FLASH_CTRL_BUF_SIZE 256 + +/*@} end of group SF_CTRL_Public_Macros */ + +/** @defgroup SF_CTRL_Public_Functions + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +void SF_Ctrl_IRQHandler(void); +#endif +void SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg); +void SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner); +void SF_Ctrl_Disable(void); +void SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Sel sel); +void SF_Ctrl_AES_Enable_BE(void); +void SF_Ctrl_AES_Enable_LE(void); +void SF_Ctrl_AES_Set_Region(uint8_t region,uint8_t enable, uint8_t hwKey,uint32_t startAddr, +uint32_t endAddr, + uint8_t locked); +void SF_Ctrl_AES_Set_Key(uint8_t region,uint8_t *key, SF_Ctrl_AES_Key_Type keyType); +void SF_Ctrl_AES_Set_Key_BE(uint8_t region,uint8_t *key, SF_Ctrl_AES_Key_Type keyType); +void SF_Ctrl_AES_Set_IV(uint8_t region,uint8_t *iv,uint32_t addrOffset); +void SF_Ctrl_AES_Set_IV_BE(uint8_t region,uint8_t *iv,uint32_t addrOffset); +void SF_Ctrl_AES_Enable(void); +void SF_Ctrl_AES_Disable(void); +void SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset); +uint32_t SF_Ctrl_Get_Flash_Image_Offset(void); +void SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType); +void SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg); +void SF_Ctrl_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg,uint8_t cmdValid); +void SF_Ctrl_Icache2_Set(SF_Ctrl_Cmd_Cfg_Type *cfg,uint8_t cmdValid); +BL_Sts_Type SF_Ctrl_GetBusyState(void); +uint8_t SF_Ctrl_Is_AES_Enable(void); +uint8_t SF_Ctrl_Get_Clock_Delay(void); +void SF_Ctrl_Set_Clock_Delay(uint8_t delay); + +/*@} end of group SF_CTRL_Public_Functions */ + +/*@} end of group SF_CTRL */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_SF_CTRL_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_sflash.h b/drivers/bl602_driver/std_drv/inc/bl602_sflash.h new file mode 100644 index 00000000..781b9f93 --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_sflash.h @@ -0,0 +1,198 @@ +/** + ****************************************************************************** + * @file bl602_sflah.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_SFLAH_H__ +#define __BL602_SFLAH_H__ + +#include "bl602_common.h" +#include "bl602_sf_ctrl.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SFLAH + * @{ + */ + +/** @defgroup SFLAH_Public_Types + * @{ + */ + +/** + * @brief Serial flash configuration structure type definition + */ +typedef struct { + uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ + uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ + uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ + uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ + uint8_t resetEnCmd; /*!< Flash enable reset command */ + uint8_t resetCmd; /*!< Flash reset command */ + uint8_t resetCreadCmd; /*!< Flash reset continuous read command */ + uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */ + uint8_t jedecIdCmd; /*!< JEDEC ID command */ + uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */ + uint8_t qpiJedecIdCmd; /*!< QPI JEDEC ID comamnd */ + uint8_t qpiJedecIdCmdDmyClk; /*!< QPI JEDEC ID command dummy clock */ + uint8_t sectorSize; /*!< *1024bytes */ + uint8_t mid; /*!< Manufacturer ID */ + uint16_t pageSize; /*!< Page size */ + uint8_t chipEraseCmd; /*!< Chip erase cmd */ + uint8_t sectorEraseCmd; /*!< Sector erase command */ + uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */ + uint8_t blk64EraseCmd; /*!< Block 64K erase command */ + uint8_t writeEnableCmd; /*!< Need before every erase or program */ + uint8_t pageProgramCmd; /*!< Page program cmd */ + uint8_t qpageProgramCmd; /*!< QIO page program cmd */ + uint8_t qppAddrMode; /*!< QIO page program address mode */ + uint8_t fastReadCmd; /*!< Fast read command */ + uint8_t frDmyClk; /*!< Fast read command dummy clock */ + uint8_t qpiFastReadCmd; /*!< QPI fast read command */ + uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */ + uint8_t fastReadDoCmd; /*!< Fast read dual output command */ + uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */ + uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */ + uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */ + uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */ + uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */ + uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */ + uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */ + uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */ + uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */ + uint8_t qpiPageProgramCmd; /*!< QPI program command */ + uint8_t writeVregEnableCmd; /*!< Enable write reg */ + uint8_t wrEnableIndex; /*!< Write enable register index */ + uint8_t qeIndex; /*!< Quad mode enable register index */ + uint8_t busyIndex; /*!< Busy status register index */ + uint8_t wrEnableBit; /*!< Write enable bit pos */ + uint8_t qeBit; /*!< Quad enable bit pos */ + uint8_t busyBit; /*!< Busy status bit pos */ + uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */ + uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */ + uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */ + uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */ + uint8_t releasePowerDown; /*!< Release power down command */ + uint8_t busyReadRegLen; /*!< Register length of contain busy status */ + uint8_t readRegCmd[4]; /*!< Read register command buffer */ + uint8_t writeRegCmd[4]; /*!< Write register command buffer */ + uint8_t enterQpi; /*!< Enter qpi command */ + uint8_t exitQpi; /*!< Exit qpi command */ + uint8_t cReadMode; /*!< Config data for continuous read mode */ + uint8_t cRExit; /*!< Config data for exit continuous read mode */ + uint8_t burstWrapCmd; /*!< Enable burst wrap command */ + uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */ + uint8_t burstWrapDataMode; /*!< Data and address mode for this command */ + uint8_t burstWrapData; /*!< Data to enable burst wrap */ + uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */ + uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */ + uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */ + uint8_t deBurstWrapData; /*!< Data to disable burst wrap */ + uint16_t timeEsector; /*!< 4K erase time */ + uint16_t timeE32k; /*!< 32K erase time */ + uint16_t timeE64k; /*!< 64K erase time */ + uint16_t timePagePgm; /*!< Page program time */ + uint16_t timeCe; /*!< Chip erase time in ms */ + uint8_t pdDelay; /*!< Release power down command delay time for wake up */ + uint8_t qeData; /*!< QE set data */ +}__attribute__ ((packed)) SPI_Flash_Cfg_Type; + +/*@} end of group SFLAH_Public_Types */ + +/** @defgroup SFLAH_Public_Constants + * @{ + */ + +/*@} end of group SFLAH_Public_Constants */ + +/** @defgroup SFLAH_Public_Macros + * @{ + */ +#define BFLB_SPIFLASH_BLK32K_SIZE (32*1024) +#define BFLB_SPIFLASH_BLK64K_SIZE (64*1024) +#define BFLB_SPIFLASH_CMD_INVALID 0xff + +/*@} end of group SFLAH_Public_Macros */ + +/** @defgroup SFLAH_Public_Functions + * @{ + */ +void SFlash_Init(const SF_Ctrl_Cfg_Type *sfCtrlCfg); +BL_Err_Type SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode); +BL_Err_Type SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg,uint8_t regIndex,uint8_t *regValue,uint8_t regLen); +BL_Err_Type SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg,uint8_t regIndex,uint8_t *regValue,uint8_t regLen); +BL_Sts_Type SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg); +void SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg,uint32_t secNum); +BL_Err_Type SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg,uint32_t blkNum); +BL_Err_Type SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg,uint32_t blkNum); +BL_Err_Type SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg,uint32_t startaddr,uint32_t endaddr); +BL_Err_Type SFlash_Program(SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint32_t addr,uint8_t *data, uint32_t len); +void SFlash_GetUniqueId(uint8_t *data,uint8_t idLen); +void SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg,uint8_t *data); +void SFlash_GetDeviceId(uint8_t *data); +void SFlash_Powerdown(void); +void SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg); +void SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg); +void SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg); +void SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint8_t contRead,uint32_t addr, + uint32_t len); +BL_Err_Type SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint8_t contRead); +BL_Err_Type SFlash_Cache_Enable_Set(uint8_t wayDisable); +BL_Err_Type SFlash_Cache_Flush(void); +BL_Err_Type SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint8_t contRead, + uint8_t wayDisable); +void SFlash_Cache_Hit_Count_Get(uint32_t *hitCountLow,uint32_t *hitCountHigh); +uint32_t SFlash_Cache_Miss_Count_Get(void); +void SFlash_Cache_Read_Disable(void); +BL_Err_Type SFlash_Read(SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint8_t contRead,uint32_t addr,uint8_t *data, + uint32_t len); +BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg,uint8_t readRegCmd,uint8_t *regValue, + uint8_t regLen); +BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg,uint8_t writeRegCmd,uint8_t *regValue, + uint8_t regLen); + +/*@} end of group SFLAH_Public_Functions */ + +/*@} end of group SFLAH */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_SFLAH_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_sflash_ext.h b/drivers/bl602_driver/std_drv/inc/bl602_sflash_ext.h new file mode 100644 index 00000000..6e2abec9 --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_sflash_ext.h @@ -0,0 +1,99 @@ +/** + ****************************************************************************** + * @file bl602_sflah_ext.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_SFLAH_EXT_H__ +#define __BL602_SFLAH_EXT_H__ + +#include "bl602_sflash.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SFLAH_EXT + * @{ + */ + +/** @defgroup SFLAH_EXT_Public_Types + * @{ + */ + +/** + * @brief Serial flash security register configuration + */ +typedef struct { + uint8_t eraseCmd; /*!< Erase security register command */ + uint8_t programCmd; /*!< Program security register command */ + uint8_t readCmd; /*!< Read security register command */ + uint8_t enterSecOptCmd; /*!< Enter security register option mode command */ + uint8_t exitSecOptCmd; /*!< Exit security register option mode command */ + uint8_t blockNum; /*!< Security register block number */ + uint8_t *data; /*!< Data pointer to be program/read */ + uint32_t addr; /*!< Start address to be program/read */ + uint32_t len; /*!< Data length to be program/read */ +}SFlash_Sec_Reg_Cfg; + +/*@} end of group SFLAH_EXT_Public_Types */ + +/** @defgroup SFLAH_EXT_Public_Constants + * @{ + */ + +/*@} end of group SFLAH_EXT_Public_Constants */ + +/** @defgroup SFLAH_EXT_Public_Macros + * @{ + */ + +/*@} end of group SFLAH_EXT_Public_Macros */ + +/** @defgroup SFLAH_EXT_Public_Functions + * @{ + */ +BL_Err_Type SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t flashContRead); +BL_Err_Type SFlash_RCV_Enable(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos); +BL_Err_Type SFlash_Erase_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg); +BL_Err_Type SFlash_Program_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, + SFlash_Sec_Reg_Cfg *pSecRegCfg); +BL_Err_Type SFlash_Read_Security_Register(SFlash_Sec_Reg_Cfg *pSecRegCfg); + +/*@} end of group SFLAH_EXT_Public_Functions */ + +/*@} end of group SFLAH_EXT */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_SFLAH_EXT_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_spi.h b/drivers/bl602_driver/std_drv/inc/bl602_spi.h new file mode 100644 index 00000000..539cc063 --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_spi.h @@ -0,0 +1,314 @@ +/** + ****************************************************************************** + * @file bl602_spi.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_SPI_H__ +#define __BL602_SPI_H__ + +#include "spi_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @defgroup SPI_Public_Types + * @{ + */ + +/** + * @brief SPI No. type definition + */ +typedef enum { + SPI_ID_0, /*!< SPI0 port define */ + SPI_ID_MAX, /*!< SPI MAX ID define */ +}SPI_ID_Type; + +/** + * @brief SPI byte inverse type definition + */ +typedef enum { + SPI_BYTE_INVERSE_BYTE0_FIRST, /*!< SPI byte 0 is sent out first */ + SPI_BYTE_INVERSE_BYTE3_FIRST, /*!< SPI byte 3 is sent out first */ +}SPI_BYTE_INVERSE_Type; + +/** + * @brief SPI bit inverse type definition + */ +typedef enum { + SPI_BIT_INVERSE_MSB_FIRST, /*!< SPI each byte is sent out MSB first */ + SPI_BIT_INVERSE_LSB_FIRST, /*!< SPI each byte is sent out LSB first */ +}SPI_BIT_INVERSE_Type; + +/** + * @brief SPI clock phase inverse type definition + */ +typedef enum { + SPI_CLK_PHASE_INVERSE_0, /*!< SPI clock phase inverse 0 */ + SPI_CLK_PHASE_INVERSE_1, /*!< SPI clock phase inverse 1 */ +}SPI_CLK_PHASE_INVERSE_Type; + +/** + * @brief SPI clock polarity type definition + */ +typedef enum { + SPI_CLK_POLARITY_LOW, /*!< SPI clock output low at IDLE state */ + SPI_CLK_POLARITY_HIGH, /*!< SPI clock output high at IDLE state */ +}SPI_CLK_POLARITY_Type; + +/** + * @brief SPI frame size(also the valid width for each fifo entry) type definition + */ +typedef enum { + SPI_FRAME_SIZE_8, /*!< SPI frame size 8 bit */ + SPI_FRAME_SIZE_16, /*!< SPI frame size 16 bit */ + SPI_FRAME_SIZE_24, /*!< SPI frame size 24 bit */ + SPI_FRAME_SIZE_32, /*!< SPI frame size 32 bit */ +}SPI_FrameSize_Type; + +/** + * @brief SPI work mode select type definition + */ +typedef enum { + SPI_WORK_MODE_SLAVE, /*!< SPI work at slave mode */ + SPI_WORK_MODE_MASTER, /*!< SPI work at master mode */ +}SPI_WORK_MODE_Type; + +/** + * @brief SPI enable or disable timeout judgment definition + */ +typedef enum { + SPI_TIMEOUT_DISABLE, /*!< SPI disable timeout judgment */ + SPI_TIMEOUT_ENABLE, /*!< SPI enable timeout judgment */ +}SPI_Timeout_Type; + +/** + * @brief SPI fifo overflow/underflow flag type definition + */ +typedef enum { + SPI_FIFO_TX_OVERFLOW, /*!< SPI tx fifo overflow flag */ + SPI_FIFO_TX_UNDERFLOW, /*!< SPI tx fifo underflow flag */ + SPI_FIFO_RX_OVERFLOW, /*!< SPI rx fifo overflow flag */ + SPI_FIFO_RX_UNDERFLOW, /*!< SPI rx fifo underflow flag */ +}SPI_FifoStatus_Type; + +/** + * @brief SPI interrupt type definition + */ +typedef enum { + SPI_INT_END, /*!< SPI transfer end interrupt,shared by both master and slave mode */ + SPI_INT_TX_FIFO_REQ, /*!< SPI tx fifo ready interrupt(tx fifo count > tx fifo threshold) */ + SPI_INT_RX_FIFO_REQ, /*!< SPI rx fifo ready interrupt(rx fifo count > rx fifo threshold) */ + SPI_INT_SLAVE_TIMEOUT, /*!< SPI slave mode transfer time-out interrupt,triggered when spi bus is idle for the given value */ + SPI_INT_SLAVE_UNDERRUN, /*!< SPI slave mode tx underrun error interrupt,triggered when tx is not ready during transfer */ + SPI_INT_FIFO_ERROR, /*!< SPI tx/rx fifo error interrupt(overflow/underflow) */ + SPI_INT_ALL, /*!< All the interrupt */ +}SPI_INT_Type; + +/** + * @brief SPI configuration type definition + */ +typedef struct { + BL_Fun_Type deglitchEnable; /*!< Enable or disable de-glitch function */ + BL_Fun_Type continuousEnable; /*!< Enable or disable master continuous transfer mode,enable:SS will stay asserted if next data is valid */ + SPI_BYTE_INVERSE_Type byteSequence; /*!< The byte is sent first in SPI transfer */ + SPI_BIT_INVERSE_Type bitSequence; /*!< The bit is sent first in SPI transfer */ + SPI_CLK_PHASE_INVERSE_Type clkPhaseInv; /*!< Inverse SPI clock phase */ + SPI_CLK_POLARITY_Type clkPolarity; /*!< SPI clock plarity */ + SPI_FrameSize_Type frameSize; /*!< SPI frame size(also the valid width for each fifo entry) */ +}SPI_CFG_Type; + +/** + * @brief SPI configuration type definition + */ +typedef struct { + uint8_t startLen; /*!< Length of start condition */ + uint8_t stopLen; /*!< Length of stop condition */ + uint8_t dataPhase0Len; /*!< Length of data phase 0,affecting clock */ + uint8_t dataPhase1Len; /*!< Length of data phase 1,affecting clock */ + uint8_t intervalLen; /*!< Length of interval between frame */ +}SPI_ClockCfg_Type; + +/** + * @brief SPI DMA configuration type definition + */ +typedef struct { + uint8_t txFifoThreshold; /*!< SPI tx FIFO threshold */ + uint8_t rxFifoThreshold; /*!< SPI rx FIFO threshold */ + BL_Fun_Type txFifoDmaEnable; /*!< Enable or disable tx dma req/ack interface */ + BL_Fun_Type rxFifoDmaEnable; /*!< Enable or disable rx dma req/ack interface */ +}SPI_FifoCfg_Type; + +/*@} end of group SPI_Public_Types */ + +/** @defgroup SPI_Public_Constants + * @{ + */ + +/** @defgroup SPI_ID_TYPE + * @{ + */ +#define IS_SPI_ID_TYPE(type) (((type) == SPI_ID_0) || \ + ((type) == SPI_ID_MAX)) + +/** @defgroup SPI_BYTE_INVERSE_TYPE + * @{ + */ +#define IS_SPI_BYTE_INVERSE_TYPE(type) (((type) == SPI_BYTE_INVERSE_BYTE0_FIRST) || \ + ((type) == SPI_BYTE_INVERSE_BYTE3_FIRST)) + +/** @defgroup SPI_BIT_INVERSE_TYPE + * @{ + */ +#define IS_SPI_BIT_INVERSE_TYPE(type) (((type) == SPI_BIT_INVERSE_MSB_FIRST) || \ + ((type) == SPI_BIT_INVERSE_LSB_FIRST)) + +/** @defgroup SPI_CLK_PHASE_INVERSE_TYPE + * @{ + */ +#define IS_SPI_CLK_PHASE_INVERSE_TYPE(type) (((type) == SPI_CLK_PHASE_INVERSE_0) || \ + ((type) == SPI_CLK_PHASE_INVERSE_1)) + +/** @defgroup SPI_CLK_POLARITY_TYPE + * @{ + */ +#define IS_SPI_CLK_POLARITY_TYPE(type) (((type) == SPI_CLK_POLARITY_LOW) || \ + ((type) == SPI_CLK_POLARITY_HIGH)) + +/** @defgroup SPI_FRAMESIZE_TYPE + * @{ + */ +#define IS_SPI_FRAMESIZE_TYPE(type) (((type) == SPI_FRAME_SIZE_8) || \ + ((type) == SPI_FRAME_SIZE_16) || \ + ((type) == SPI_FRAME_SIZE_24) || \ + ((type) == SPI_FRAME_SIZE_32)) + +/** @defgroup SPI_WORK_MODE_TYPE + * @{ + */ +#define IS_SPI_WORK_MODE_TYPE(type) (((type) == SPI_WORK_MODE_SLAVE) || \ + ((type) == SPI_WORK_MODE_MASTER)) + +/** @defgroup SPI_TIMEOUT_TYPE + * @{ + */ +#define IS_SPI_TIMEOUT_TYPE(type) (((type) == SPI_TIMEOUT_DISABLE) || \ + ((type) == SPI_TIMEOUT_ENABLE)) + +/** @defgroup SPI_FIFOSTATUS_TYPE + * @{ + */ +#define IS_SPI_FIFOSTATUS_TYPE(type) (((type) == SPI_FIFO_TX_OVERFLOW) || \ + ((type) == SPI_FIFO_TX_UNDERFLOW) || \ + ((type) == SPI_FIFO_RX_OVERFLOW) || \ + ((type) == SPI_FIFO_RX_UNDERFLOW)) + +/** @defgroup SPI_INT_TYPE + * @{ + */ +#define IS_SPI_INT_TYPE(type) (((type) == SPI_INT_END) || \ + ((type) == SPI_INT_TX_FIFO_REQ) || \ + ((type) == SPI_INT_RX_FIFO_REQ) || \ + ((type) == SPI_INT_SLAVE_TIMEOUT) || \ + ((type) == SPI_INT_SLAVE_UNDERRUN) || \ + ((type) == SPI_INT_FIFO_ERROR) || \ + ((type) == SPI_INT_ALL)) + +/*@} end of group SPI_Public_Constants */ + +/** @defgroup SPI_Public_Macros + * @{ + */ +#define SPI_RX_FIFO_SIZE 4 +#define SPI_TX_FIFO_SIZE 4 + +/*@} end of group SPI_Public_Macros */ + +/** @defgroup SPI_Public_Functions + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +void SPI_IRQHandler(void); +#endif +BL_Err_Type SPI_Init(SPI_ID_Type spiNo,SPI_CFG_Type *spiCfg); +BL_Err_Type SPI_DeInit(SPI_ID_Type spiNo); +BL_Err_Type SPI_ClockConfig(SPI_ID_Type spiNo,SPI_ClockCfg_Type *clockCfg); +BL_Err_Type SPI_FifoConfig(SPI_ID_Type spiNo,SPI_FifoCfg_Type *fifoCfg); +BL_Err_Type SPI_Enable(SPI_ID_Type spiNo,SPI_WORK_MODE_Type modeType); +BL_Err_Type SPI_Disable(SPI_ID_Type spiNo,SPI_WORK_MODE_Type modeType); +BL_Err_Type SPI_SetTimeOutValue(SPI_ID_Type spiNo,uint16_t value); +BL_Err_Type SPI_SetDeglitchCount(SPI_ID_Type spiNo,uint8_t cnt); +BL_Err_Type SPI_RxIgnoreEnable(SPI_ID_Type spiNo,uint8_t startPoint,uint8_t stopPoint); +BL_Err_Type SPI_RxIgnoreDisable(SPI_ID_Type spiNo); +BL_Err_Type SPI_ClrTxFifo(SPI_ID_Type spiNo); +BL_Err_Type SPI_ClrRxFifo(SPI_ID_Type spiNo); +BL_Err_Type SPI_ClrIntStatus(SPI_ID_Type spiNo,SPI_INT_Type intType); +BL_Err_Type SPI_IntMask(SPI_ID_Type spiNo,SPI_INT_Type intType,BL_Mask_Type intMask); +BL_Err_Type SPI_Int_Callback_Install(SPI_ID_Type spiNo,SPI_INT_Type intType,intCallback_Type *cbFun); +BL_Err_Type SPI_SendData(SPI_ID_Type spiNo,uint32_t data); +BL_Err_Type SPI_Send_8bits(SPI_ID_Type spiNo,uint8_t *buff,uint32_t length,SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_Send_16bits(SPI_ID_Type spiNo,uint16_t *buff,uint32_t length,SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_Send_24bits(SPI_ID_Type spiNo,uint32_t *buff,uint32_t length,SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_Send_32bits(SPI_ID_Type spiNo,uint32_t *buff,uint32_t length,SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_Recv_8bits(SPI_ID_Type spiNo,uint8_t *buff,uint32_t length,SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_Recv_16bits(SPI_ID_Type spiNo,uint16_t *buff,uint32_t length,SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_Recv_24bits(SPI_ID_Type spiNo,uint32_t *buff,uint32_t length,SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_Recv_32bits(SPI_ID_Type spiNo,uint32_t *buff,uint32_t length,SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_SendRecv_8bits(SPI_ID_Type spiNo,uint8_t *sendBuff,uint8_t *recvBuff,uint32_t length, + SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_SendRecv_16bits(SPI_ID_Type spiNo,uint16_t *sendBuff,uint16_t *recvBuff,uint32_t length, + SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_SendRecv_24bits(SPI_ID_Type spiNo,uint32_t *sendBuff,uint32_t *recvBuff,uint32_t length, + SPI_Timeout_Type timeoutType); +BL_Err_Type SPI_SendRecv_32bits(SPI_ID_Type spiNo,uint32_t *sendBuff,uint32_t *recvBuff,uint32_t length, + SPI_Timeout_Type timeoutType); +uint32_t SPI_ReceiveData(SPI_ID_Type spiNo); +uint8_t SPI_GetTxFifoCount(SPI_ID_Type spiNo); +uint8_t SPI_GetRxFifoCount(SPI_ID_Type spiNo); +BL_Sts_Type SPI_GetIntStatus(SPI_ID_Type spiNo,SPI_INT_Type intType); +BL_Sts_Type SPI_GetFifoStatus(SPI_ID_Type spiNo,SPI_FifoStatus_Type fifoSts); +BL_Sts_Type SPI_GetBusyStatus(SPI_ID_Type spiNo); +BL_Err_Type SPI_SetClock(SPI_ID_Type spiNo,uint32_t clk); + +/*@} end of group SPI_Public_Functions */ + +/*@} end of group SPI */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_SPI_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_timer.h b/drivers/bl602_driver/std_drv/inc/bl602_timer.h new file mode 100644 index 00000000..867b487b --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_timer.h @@ -0,0 +1,243 @@ +/** + ****************************************************************************** + * @file bl602_timer.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_TIMER_H__ +#define __BL602_TIMER_H__ + +#include "timer_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup TIMER + * @{ + */ + +/** @defgroup TIMER_Public_Types + * @{ + */ + +/** + * @brief TIMER channel type definition + */ +typedef enum { + TIMER_CH0, /*!< TIMER channel 0 port define */ + TIMER_CH1, /*!< TIMER channel 1 port define */ + TIMER_CH_MAX, /*!< */ +}TIMER_Chan_Type; + +/** + * @brief TIMER clock source type definition + */ +typedef enum { + TIMER_CLKSRC_FCLK, /*!< TIMER clock source :System CLK */ + TIMER_CLKSRC_32K, /*!< TIMER clock source :32K CLK */ + TIMER_CLKSRC_1K, /*!< TIMER clock source :1K CLK,Only for Timer not for Watchdog */ + TIMER_CLKSRC_XTAL, /*!< TIMER clock source :XTAL CLK */ +}TIMER_ClkSrc_Type; + +/** + * @brief TIMER match compare ID type definition + */ +typedef enum { + TIMER_COMP_ID_0, /*!< TIMER match compare ID 0 define */ + TIMER_COMP_ID_1, /*!< TIMER match compare ID 1 define */ + TIMER_COMP_ID_2, /*!< TIMER match compare ID 2 define */ +}TIMER_Comp_ID_Type; + +/** + * @brief TIMER preload source type definition + */ +typedef enum { + TIMER_PRELOAD_TRIG_NONE, /*!< TIMER no preload source, just free run */ + TIMER_PRELOAD_TRIG_COMP0, /*!< TIMER count register preload triggered by comparator 0 */ + TIMER_PRELOAD_TRIG_COMP1, /*!< TIMER count register preload triggered by comparator 1 */ + TIMER_PRELOAD_TRIG_COMP2, /*!< TIMER count register preload triggered by comparator 2 */ +}TIMER_PreLoad_Trig_Type; + +/** + * @brief TIMER count register run mode type definition + */ +typedef enum { + TIMER_COUNT_PRELOAD, /*!< TIMER count register preload from comparator register */ + TIMER_COUNT_FREERUN, /*!< TIMER count register free run */ +}TIMER_CountMode_Type; + +/** + * @brief TIMER interrupt type definition + */ +typedef enum { + TIMER_INT_COMP_0, /*!< Comparator 0 match cause interrupt */ + TIMER_INT_COMP_1, /*!< Comparator 1 match cause interrupt */ + TIMER_INT_COMP_2, /*!< Comparator 2 match cause interrupt */ + TIMER_INT_ALL, /*!< */ +}TIMER_INT_Type; + +/** + * @brief Watchdog timer interrupt type definition + */ +typedef enum { + WDT_INT, /*!< Comparator 0 match cause interrupt */ + WDT_INT_ALL, /*!< */ +}WDT_INT_Type; + +/** + * @brief TIMER configuration structure type definition + */ +typedef struct { + TIMER_Chan_Type timerCh; /*!< Timer channel */ + TIMER_ClkSrc_Type clkSrc; /*!< Timer clock source */ + TIMER_PreLoad_Trig_Type plTrigSrc; /*!< Timer count register preload trigger source slelect */ + TIMER_CountMode_Type countMode; /*!< Timer count mode */ + uint8_t clockDivision; /*!< Timer clock divison value */ + uint32_t matchVal0; /*!< Timer match 0 value 0 */ + uint32_t matchVal1; /*!< Timer match 1 value 0 */ + uint32_t matchVal2; /*!< Timer match 2 value 0 */ + uint32_t preLoadVal; /*!< Timer preload value */ +}TIMER_CFG_Type; + +/*@} end of group TIMER_Public_Types */ + +/** @defgroup TIMER_Public_Constants + * @{ + */ + +/** @defgroup TIMER_CHAN_TYPE + * @{ + */ +#define IS_TIMER_CHAN_TYPE(type) (((type) == TIMER_CH0) || \ + ((type) == TIMER_CH1) || \ + ((type) == TIMER_CH_MAX)) + +/** @defgroup TIMER_CLKSRC_TYPE + * @{ + */ +#define IS_TIMER_CLKSRC_TYPE(type) (((type) == TIMER_CLKSRC_FCLK) || \ + ((type) == TIMER_CLKSRC_32K) || \ + ((type) == TIMER_CLKSRC_1K) || \ + ((type) == TIMER_CLKSRC_XTAL)) + +/** @defgroup TIMER_COMP_ID_TYPE + * @{ + */ +#define IS_TIMER_COMP_ID_TYPE(type) (((type) == TIMER_COMP_ID_0) || \ + ((type) == TIMER_COMP_ID_1) || \ + ((type) == TIMER_COMP_ID_2)) + +/** @defgroup TIMER_PRELOAD_TRIG_TYPE + * @{ + */ +#define IS_TIMER_PRELOAD_TRIG_TYPE(type) (((type) == TIMER_PRELOAD_TRIG_NONE) || \ + ((type) == TIMER_PRELOAD_TRIG_COMP0) || \ + ((type) == TIMER_PRELOAD_TRIG_COMP1) || \ + ((type) == TIMER_PRELOAD_TRIG_COMP2)) + +/** @defgroup TIMER_COUNTMODE_TYPE + * @{ + */ +#define IS_TIMER_COUNTMODE_TYPE(type) (((type) == TIMER_COUNT_PRELOAD) || \ + ((type) == TIMER_COUNT_FREERUN)) + +/** @defgroup TIMER_INT_TYPE + * @{ + */ +#define IS_TIMER_INT_TYPE(type) (((type) == TIMER_INT_COMP_0) || \ + ((type) == TIMER_INT_COMP_1) || \ + ((type) == TIMER_INT_COMP_2) || \ + ((type) == TIMER_INT_ALL)) + +/** @defgroup WDT_INT_TYPE + * @{ + */ +#define IS_WDT_INT_TYPE(type) (((type) == WDT_INT) || \ + ((type) == WDT_INT_ALL)) + +/*@} end of group TIMER_Public_Constants */ + +/** @defgroup TIMER_Public_Macros + * @{ + */ +#define WDT_ENABLE_ACCESS() {BL_WR_REG(TIMER_BASE,TIMER_WFAR,BL_SET_REG_BITS_VAL(BL_RD_REG(TIMER_BASE,TIMER_WFAR),TIMER_WFAR,0xBABA));\ + BL_WR_REG(TIMER_BASE,TIMER_WSAR,BL_SET_REG_BITS_VAL(BL_RD_REG(TIMER_BASE,TIMER_WSAR),TIMER_WSAR,0xEB10));} + +/*@} end of group TIMER_Public_Macros */ + +/** @defgroup TIMER_Public_Functions + * @{ + */ + +/** + * @brief UART Functions + */ +#ifndef BFLB_USE_HAL_DRIVER +void TIMER_CH0_IRQHandler(void); +void TIMER_CH1_IRQHandler(void); +void TIMER_WDT_IRQHandler(void); +#endif +BL_Err_Type TIMER_Init(TIMER_CFG_Type* timerCfg); +uint32_t TIMER_GetCompValue(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo); +void TIMER_SetCompValue(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo, uint32_t val); +uint32_t TIMER_GetCounterValue(TIMER_Chan_Type timerCh); +BL_Sts_Type TIMER_GetMatchStatus(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo); +uint32_t TIMER_GetPreloadValue(TIMER_Chan_Type timerCh); +void TIMER_SetPreloadValue(TIMER_Chan_Type timerCh,uint32_t val); +void TIMER_SetPreloadSrc(TIMER_Chan_Type timerCh, TIMER_PreLoad_Trig_Type plSrc); +void TIMER_SetCountMode(TIMER_Chan_Type timerCh, TIMER_CountMode_Type countMode); +void TIMER_ClearIntStatus(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo); +void TIMER_Enable(TIMER_Chan_Type timerCh); +void TIMER_Disable(TIMER_Chan_Type timerCh); +void TIMER_IntMask(TIMER_Chan_Type timerCh,TIMER_INT_Type intType, BL_Mask_Type intMask); +void WDT_Set_Clock(TIMER_ClkSrc_Type clkSrc,uint8_t div); +uint16_t WDT_GetMatchValue(void); +void WDT_SetCompValue(uint16_t val); +uint16_t WDT_GetCounterValue(void); +void WDT_ResetCounterValue(void); +BL_Sts_Type WDT_GetResetStatus(void); +void WDT_ClearResetStatus(void); +void WDT_Enable(void); +void WDT_Disable(void); +void WDT_IntMask(WDT_INT_Type intType, BL_Mask_Type intMask); +void Timer_Int_Callback_Install(TIMER_Chan_Type timerChan,TIMER_INT_Type intType,intCallback_Type* cbFun); +void WDT_Int_Callback_Install(WDT_INT_Type wdtInt,intCallback_Type* cbFun); + +/*@} end of group TIMER_Public_Functions */ + +/*@} end of group TIMER */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_TIMER_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_tzc_sec.h b/drivers/bl602_driver/std_drv/inc/bl602_tzc_sec.h new file mode 100644 index 00000000..b4deea3d --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_tzc_sec.h @@ -0,0 +1,80 @@ +/** + ****************************************************************************** + * @file bl602_tzc_sec.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_TZC_SEC_H__ +#define __BL602_TZC_SEC_H__ + +#include "tzc_sec_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup TZC_SEC + * @{ + */ + +/** @defgroup TZC_SEC_Public_Types + * @{ + */ + +/*@} end of group TZC_SEC_Public_Types */ + +/** @defgroup TZC_SEC_Public_Constants + * @{ + */ + +/*@} end of group TZC_SEC_Public_Constants */ + +/** @defgroup TZC_SEC_Public_Macros + * @{ + */ + +/*@} end of group TZC_SEC_Public_Macros */ + +/** @defgroup TZC_SEC_Public_Functions + * @{ + */ +void TZC_Sboot_Set(uint8_t Val); +void TZC_Set_Rom0_R0_Protect(uint32_t start,uint32_t end); + +/*@} end of group TZC_SEC_Public_Functions */ + +/*@} end of group TZC_SEC */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_TZC_SEC_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_uart.h b/drivers/bl602_driver/std_drv/inc/bl602_uart.h new file mode 100644 index 00000000..14dbffb4 --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_uart.h @@ -0,0 +1,314 @@ +/** + ****************************************************************************** + * @file bl602_uart.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_UART_H__ +#define __BL602_UART_H__ + +#include "uart_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/** @defgroup UART_Public_Types + * @{ + */ + +/** + * @brief UART port type definition + */ +typedef enum { + UART0_ID, /*!< UART0 port define */ + UART1_ID, /*!< UART1 port define */ + UART_ID_MAX, /*!< UART MAX ID define */ +}UART_ID_Type; + +/** + * @brief UART direction type definition + */ +typedef enum { + UART_TX, /*!< UART TX Direction */ + UART_RX, /*!< UART RX Direction */ + UART_TXRX, /*!< UART TX and RX Direction */ +}UART_Direction_Type; + +/** + * @brief UART parity type definition + */ +typedef enum { + UART_PARITY_NONE, /*!< UART parity none define */ + UART_PARITY_ODD, /*!< UART parity odd define */ + UART_PARITY_EVEN, /*!< UART parity even define */ +}UART_Parity_Type; + +/** + * @brief UART data bits type definiton + */ +typedef enum { + UART_DATABITS_5, /*!< UART data bits length:5 bits */ + UART_DATABITS_6, /*!< UART data bits length:6 bits */ + UART_DATABITS_7, /*!< UART data bits length:7 bits */ + UART_DATABITS_8, /*!< UART data bits length:8 bits */ +}UART_DataBits_Type; + +/** + * @brief UART stop bits type definiton + */ +typedef enum { + UART_STOPBITS_1, /*!< UART data stop bits length:1 bits */ + UART_STOPBITS_1_5, /*!< UART data stop bits length:1.5 bits */ + UART_STOPBITS_2, /*!< UART data stop bits length:2 bits */ +}UART_StopBits_Type; + +/** + * @brief UART each data byte is send out LSB-first or MSB-first type definiton + */ +typedef enum { + UART_LSB_FIRST, /*!< UART each byte is send out LSB-first */ + UART_MSB_FIRST, /*!< UART each byte is send out MSB-first */ +}UART_ByteBitInverse_Type; + +/** + * @brief UART auto baudrate detection using codeword 0x55 or start bit definiton + */ +typedef enum { + UART_AUTOBAUD_0X55, /*!< UART auto baudrate detection using codeword 0x55 */ + UART_AUTOBAUD_STARTBIT, /*!< UART auto baudrate detection using start bit */ +}UART_AutoBaudDetection_Type; + +/** + * @brief UART interrupt type definition + */ +typedef enum { + UART_INT_TX_END, /*!< UART tx transfer end interrupt */ + UART_INT_RX_END, /*!< UART rx transfer end interrupt */ + UART_INT_TX_FIFO_REQ, /*!< UART tx fifo interrupt when tx fifo count reaches,auto clear */ + UART_INT_RX_FIFO_REQ, /*!< UART rx fifo interrupt when rx fifo count reaches,auto clear */ + UART_INT_RTO, /*!< UART rx time-out interrupt */ + UART_INT_PCE, /*!< UART rx parity check error interrupt */ + UART_INT_TX_FER, /*!< UART tx fifo overflow/underflow error interrupt */ + UART_INT_RX_FER, /*!< UART rx fifo overflow/underflow error interrupt */ + UART_INT_ALL, /*!< All the interrupt */ +}UART_INT_Type; + +/** + * @brief UART overflow or underflow type definition + */ +typedef enum { + UART_TX_OVERFLOW, /*!< UART tx fifo overflow */ + UART_TX_UNDERFLOW, /*!< UART tx fifo underflow */ + UART_RX_OVERFLOW, /*!< UART rx fifo overflow */ + UART_RX_UNDERFLOW, /*!< UART rx fifo underflow */ +}UART_Overflow_Type; + +/** + * @brief UART configuration structure type definition + */ +typedef struct { + uint32_t uartClk; /*!< Uart module clock */ + uint32_t baudRate; /*!< Uart baudrate */ + UART_DataBits_Type dataBits; /*!< Uart frame length of data bit */ + UART_StopBits_Type stopBits; /*!< Uart frame length of stop bit */ + UART_Parity_Type parity; /*!< Uart parity check type */ + BL_Fun_Type ctsFlowControl; /*!< Enable or disable tx CTS flow control */ + BL_Fun_Type rxDeglitch; /*!< Enable or disable rx input de-glitch function */ + BL_Fun_Type rtsSoftwareControl; /*!< Enable or disable rx RTS output SW control mode */ + UART_ByteBitInverse_Type byteBitInverse; /*!< Uart each data byte is send out LSB-first or MSB-first */ +}UART_CFG_Type; + +/** + * @brief UART FIFO configuration structure type definition + */ +typedef struct { + uint8_t txFifoDmaThreshold; /*!< TX FIFO threshold, dma tx request will not be asserted if tx fifo count is less than this value */ + uint8_t rxFifoDmaThreshold; /*!< RX FIFO threshold, dma rx request will not be asserted if rx fifo count is less than this value */ + BL_Fun_Type txFifoDmaEnable; /*!< Enable or disable tx dma req/ack interface */ + BL_Fun_Type rxFifoDmaEnable; /*!< Enable or disable rx dma req/ack interface */ +}UART_FifoCfg_Type; + +/** + * @brief UART infrared configuration structure type definition + */ +typedef struct { + BL_Fun_Type txIrEnable; /*!< Enable or disable uart tx ir mode */ + BL_Fun_Type rxIrEnable; /*!< Enable or disable uart rx ir mode */ + BL_Fun_Type txIrInverse; /*!< Enable or disable inverse signal of uart tx output in ir mode */ + BL_Fun_Type rxIrInverse; /*!< Enable or disable inverse signal of uart rx input in ir mode */ + uint16_t txIrPulseStart; /*!< Set start position of uart tx ir pulse */ + uint16_t txIrPulseStop; /*!< Set stop position of uart tx ir pulse */ + uint16_t rxIrPulseStart; /*!< Set start position of uart rx pulse recovered from ir signal */ +}UART_IrCfg_Type; + +/*@} end of group UART_Public_Types */ + +/** @defgroup UART_Public_Constants + * @{ + */ + +/** @defgroup UART_ID_TYPE + * @{ + */ +#define IS_UART_ID_TYPE(type) (((type) == UART0_ID) || \ + ((type) == UART1_ID) || \ + ((type) == UART_ID_MAX)) + +/** @defgroup UART_DIRECTION_TYPE + * @{ + */ +#define IS_UART_DIRECTION_TYPE(type) (((type) == UART_TX) || \ + ((type) == UART_RX) || \ + ((type) == UART_TXRX)) + +/** @defgroup UART_PARITY_TYPE + * @{ + */ +#define IS_UART_PARITY_TYPE(type) (((type) == UART_PARITY_NONE) || \ + ((type) == UART_PARITY_ODD) || \ + ((type) == UART_PARITY_EVEN)) + +/** @defgroup UART_DATABITS_TYPE + * @{ + */ +#define IS_UART_DATABITS_TYPE(type) (((type) == UART_DATABITS_5) || \ + ((type) == UART_DATABITS_6) || \ + ((type) == UART_DATABITS_7) || \ + ((type) == UART_DATABITS_8)) + +/** @defgroup UART_STOPBITS_TYPE + * @{ + */ +#define IS_UART_STOPBITS_TYPE(type) (((type) == UART_STOPBITS_1) || \ + ((type) == UART_STOPBITS_1_5) || \ + ((type) == UART_STOPBITS_2)) + +/** @defgroup UART_BYTEBITINVERSE_TYPE + * @{ + */ +#define IS_UART_BYTEBITINVERSE_TYPE(type) (((type) == UART_LSB_FIRST) || \ + ((type) == UART_MSB_FIRST)) + +/** @defgroup UART_AUTOBAUDDETECTION_TYPE + * @{ + */ +#define IS_UART_AUTOBAUDDETECTION_TYPE(type) (((type) == UART_AUTOBAUD_0X55) || \ + ((type) == UART_AUTOBAUD_STARTBIT)) + +/** @defgroup UART_INT_TYPE + * @{ + */ +#define IS_UART_INT_TYPE(type) (((type) == UART_INT_TX_END) || \ + ((type) == UART_INT_RX_END) || \ + ((type) == UART_INT_TX_FIFO_REQ) || \ + ((type) == UART_INT_RX_FIFO_REQ) || \ + ((type) == UART_INT_RTO) || \ + ((type) == UART_INT_PCE) || \ + ((type) == UART_INT_TX_FER) || \ + ((type) == UART_INT_RX_FER) || \ + ((type) == UART_INT_ALL)) + +/** @defgroup UART_OVERFLOW_TYPE + * @{ + */ +#define IS_UART_OVERFLOW_TYPE(type) (((type) == UART_TX_OVERFLOW) || \ + ((type) == UART_TX_UNDERFLOW) || \ + ((type) == UART_RX_OVERFLOW) || \ + ((type) == UART_RX_UNDERFLOW)) + +/*@} end of group UART_Public_Constants */ + +/** @defgroup UART_Public_Macros + * @{ + */ +#define UART_RX_FIFO_SIZE 32 +#define UART_TX_FIFO_SIZE 32 +#define UART_DEFAULT_RECV_TIMEOUT 80 + +/*@} end of group UART_Public_Macros */ + +/** @defgroup UART_Public_Functions + * @{ + */ + +/** + * @brief UART Functions + */ +#if 1//(!defined BFLB_USE_HAL_DRIVER)||(defined BFLB_EFLASH_LOADER) +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +#endif +BL_Err_Type UART_Init(UART_ID_Type uartId,UART_CFG_Type* uartCfg); +BL_Err_Type UART_DeInit(UART_ID_Type uartId); +BL_Err_Type UART_FifoConfig(UART_ID_Type uartId,UART_FifoCfg_Type* fifoCfg); +BL_Err_Type UART_IrConfig(UART_ID_Type uartId,UART_IrCfg_Type* irCfg); +BL_Err_Type UART_Enable(UART_ID_Type uartId,UART_Direction_Type direct); +BL_Err_Type UART_Disable(UART_ID_Type uartId,UART_Direction_Type direct); +BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId,uint16_t length); +BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId,uint16_t length); +BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId,uint8_t time); +BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId,uint8_t deglitchCnt); +BL_Err_Type UART_SetBaudrate(UART_ID_Type uartId,UART_AutoBaudDetection_Type autoBaudDet); +BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId); +BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId); +BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId,BL_Fun_Type txFreeRun); +BL_Err_Type UART_AutoBaudDetection(UART_ID_Type uartId,BL_Fun_Type autoBaud); +BL_Err_Type UART_TxFifoClear(UART_ID_Type uartId); +BL_Err_Type UART_RxFifoClear(UART_ID_Type uartId); +BL_Err_Type UART_IntMask(UART_ID_Type uartId,UART_INT_Type intType,BL_Mask_Type intMask); +BL_Err_Type UART_IntClear(UART_ID_Type uartId,UART_INT_Type intType); +BL_Err_Type UART_Int_Callback_Install(UART_ID_Type uartId,UART_INT_Type intType,intCallback_Type* cbFun); +BL_Err_Type UART_SendData(UART_ID_Type uartId,uint8_t* data,uint32_t len); +BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId,uint8_t* data,uint32_t len); +uint32_t UART_ReceiveData(UART_ID_Type uartId,uint8_t* data,uint32_t maxLen); +uint16_t UART_GetAutoBaudCount(UART_ID_Type uartId,UART_AutoBaudDetection_Type autoBaudDet); +uint8_t UART_GetTxFifoCount(UART_ID_Type uartId); +uint8_t UART_GetRxFifoCount(UART_ID_Type uartId); +BL_Sts_Type UART_GetIntStatus(UART_ID_Type uartId,UART_INT_Type intType); +BL_Sts_Type UART_GetTxBusBusyStatus(UART_ID_Type uartId); +BL_Sts_Type UART_GetRxBusBusyStatus(UART_ID_Type uartId); +BL_Sts_Type UART_GetOverflowStatus(UART_ID_Type uartId,UART_Overflow_Type overflow); +uint32_t UART_GetBaudrate(UART_ID_Type uartId); + +/*@} end of group UART_Public_Functions */ + +/*@} end of group UART */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_UART_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_xip_sflash.h b/drivers/bl602_driver/std_drv/inc/bl602_xip_sflash.h new file mode 100644 index 00000000..3f60cc05 --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_xip_sflash.h @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file bl602_xip_sflash.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_XIP_SFLASH_H__ +#define __BL602_XIP_SFLASH_H__ + +#include "bl602_common.h" +#include "bl602_sflash.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup XIP_SFLASH + * @{ + */ + +/** @defgroup XIP_SFLASH_Public_Types + * @{ + */ + +/*@} end of group XIP_SFLASH_Public_Types */ + +/** @defgroup XIP_SFLASH_Public_Constants + * @{ + */ + +/*@} end of group XIP_SFLASH_Public_Constants */ + +/** @defgroup XIP_SFLASH_Public_Macros + * @{ + */ + +/*@} end of group XIP_SFLASH_Public_Macros */ + +/** @defgroup XIP_SFLASH_Public_Functions + * @{ + */ +BL_Err_Type XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t *offset); +BL_Err_Type XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t offset); +BL_Err_Type XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t startaddr,uint32_t endaddr); +BL_Err_Type XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr,uint8_t *data, + uint32_t len); +BL_Err_Type XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr,uint8_t *data,uint32_t len); +BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data); +BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data); +BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data,uint8_t idLen); +BL_Err_Type XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr,uint8_t *data,uint32_t len); +int XIP_SFlash_Read_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *dst, int len); +int XIP_SFlash_Write_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *src, int len); +int XIP_SFlash_Erase_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, int len); +void XIP_SFlash_Opt_Enter(uint8_t *aesEnable); +void XIP_SFlash_Opt_Exit(uint8_t aesEnable); + +/*@} end of group XIP_SFLASH_Public_Functions */ + +/*@} end of group XIP_SFLASH */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_XIP_SFLASH_H__ */ diff --git a/drivers/bl602_driver/std_drv/inc/bl602_xip_sflash_ext.h b/drivers/bl602_driver/std_drv/inc/bl602_xip_sflash_ext.h new file mode 100644 index 00000000..a576ad18 --- /dev/null +++ b/drivers/bl602_driver/std_drv/inc/bl602_xip_sflash_ext.h @@ -0,0 +1,86 @@ +/** + ****************************************************************************** + * @file bl602_xip_sflash_ext.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_XIP_SFLASH_EXT_H__ +#define __BL602_XIP_SFLASH_EXT_H__ + +#include "bl602_common.h" +#include "bl602_sflash.h" +#include "bl602_xip_sflash.h" +#include "bl602_sf_cfg.h" +#include "bl602_sf_cfg_ext.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup XIP_SFLASH + * @{ + */ + +/** @defgroup XIP_SFLASH_EXT_Public_Types + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Public_Types */ + +/** @defgroup XIP_SFLASH_EXT_Public_Constants + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Public_Constants */ + +/** @defgroup XIP_SFLASH_EXT_Public_Macros + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Public_Macros */ + +/** @defgroup XIP_SFLASH_EXT_Public_Functions + * @{ + */ + +BL_Err_Type XIP_SFlash_Init(SPI_Flash_Cfg_Type *pFlashCfg); +int XIP_SFlash_Read(uint32_t addr, uint8_t *dst, int len); +int XIP_SFlash_Write(uint32_t addr, uint8_t *src, int len); +int XIP_SFlash_Erase(uint32_t addr, int len); + +/*@} end of group XIP_SFLASH_EXT_Public_Functions */ + +/*@} end of group XIP_SFLASH */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_XIP_SFLASH_EXT_H__ */ diff --git a/drivers/bl602_driver/std_drv/src/bl602_acomp.c b/drivers/bl602_driver/std_drv/src/bl602_acomp.c new file mode 100644 index 00000000..05b0c59a --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_acomp.c @@ -0,0 +1,201 @@ +/** + ****************************************************************************** + * @file bl602_acomp.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_acomp.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup ACOMP + * @{ + */ + +/** @defgroup ACOMP_Private_Macros + * @{ + */ + +/*@} end of group ACOMP_Private_Macros */ + +/** @defgroup ACOMP_Private_Types + * @{ + */ + +/*@} end of group ACOMP_Private_Types */ + +/** @defgroup ACOMP_Private_Variables + * @{ + */ + +/*@} end of group ACOMP_Private_Variables */ + +/** @defgroup ACOMP_Global_Variables + * @{ + */ + +/*@} end of group ACOMP_Global_Variables */ + +/** @defgroup ACOMP_Private_Fun_Declaration + * @{ + */ + +/*@} end of group ACOMP_Private_Fun_Declaration */ + +/** @defgroup ACOMP_Private_Functions + * @{ + */ + +/*@} end of group ACOMP_Private_Functions */ + +/** @defgroup ACOMP_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief Analog compare init + * + * @param acompNo: Compare ID + * @param cfg: Compare consideration pointer + * + * @return None + * +*******************************************************************************/ +void AON_ACOMP_Init(AON_ACOMP_ID_Type acompNo,AON_ACOMP_CFG_Type *cfg) +{ + uint32_t tmpVal = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo)); + + if(acompNo==AON_ACOMP0_ID){ + /* Disable ACOMP first */ + tmpVal=BL_RD_REG(AON_BASE,AON_ACOMP0_CTRL); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_ACOMP0_EN); + tmpVal=BL_WR_REG(AON_BASE,AON_ACOMP0_CTRL,tmpVal); + + /* Set ACOMP config */ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP0_MUXEN,cfg->muxEn); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP0_POS_SEL,cfg->posChanSel); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP0_NEG_SEL,cfg->negChanSel); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP0_LEVEL_SEL,cfg->levelFactor); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP0_BIAS_PROG,cfg->biasProg); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP0_HYST_SELP,cfg->hysteresisPosVolt); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP0_HYST_SELN,cfg->hysteresisNegVolt); + + tmpVal=BL_WR_REG(AON_BASE,AON_ACOMP0_CTRL,tmpVal); + + }else{ + /* Disable ACOMP first */ + tmpVal=BL_RD_REG(AON_BASE,AON_ACOMP1_CTRL); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_ACOMP1_EN); + tmpVal=BL_WR_REG(AON_BASE,AON_ACOMP1_CTRL,tmpVal); + + /* Set ACOMP config */ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP1_MUXEN,cfg->muxEn); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP1_POS_SEL,cfg->posChanSel); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP1_NEG_SEL,cfg->negChanSel); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP1_LEVEL_SEL,cfg->levelFactor); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP1_BIAS_PROG,cfg->biasProg); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP1_HYST_SELP,cfg->hysteresisPosVolt); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP1_HYST_SELN,cfg->hysteresisNegVolt); + + tmpVal=BL_WR_REG(AON_BASE,AON_ACOMP1_CTRL,tmpVal); + } +} + +/****************************************************************************//** + * @brief Analog compare enable + * + * @param acompNo: Compare ID + * + * @return None + * +*******************************************************************************/ +void AON_ACOMP_Enable(AON_ACOMP_ID_Type acompNo) +{ + uint32_t tmpVal = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo)); + + if(acompNo==AON_ACOMP0_ID){ + tmpVal=BL_RD_REG(AON_BASE,AON_ACOMP0_CTRL); + tmpVal=BL_SET_REG_BIT(tmpVal,AON_ACOMP0_EN); + tmpVal=BL_WR_REG(AON_BASE,AON_ACOMP0_CTRL,tmpVal); + }else{ + tmpVal=BL_RD_REG(AON_BASE,AON_ACOMP1_CTRL); + tmpVal=BL_SET_REG_BIT(tmpVal,AON_ACOMP1_EN); + tmpVal=BL_WR_REG(AON_BASE,AON_ACOMP1_CTRL,tmpVal); + } +} + +/****************************************************************************//** + * @brief Analog compare enable + * + * @param acompNo: Compare ID + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type AON_ACOMP_Get_Result(AON_ACOMP_ID_Type acompNo) +{ + uint32_t tmpVal = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo)); + + tmpVal=BL_RD_REG(AON_BASE,AON_ACOMP_CTRL); + /* Disable ACOMP first */ + if(acompNo==AON_ACOMP0_ID){ + if(BL_IS_REG_BIT_SET(tmpVal,AON_ACOMP0_OUT_RAW)){ + return SET; + }else{ + return RESET; + } + }else{ + if(BL_IS_REG_BIT_SET(tmpVal,AON_ACOMP1_OUT_RAW)){ + return SET; + }else{ + return RESET; + } + } +} + +/*@} end of group ACOMP_Public_Functions */ + +/*@} end of group ACOMP */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/bl602_driver/std_drv/src/bl602_adc.c b/drivers/bl602_driver/std_drv/src/bl602_adc.c new file mode 100644 index 00000000..dd0ac06c --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_adc.c @@ -0,0 +1,1366 @@ +/** + ****************************************************************************** + * @file bl602_adc.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_adc.h" +#include "bl602_ef_ctrl.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/** @defgroup ADC_Private_Macros + * @{ + */ +#undef MSG +#define MSG(...) +#define AON_CLK_SET_DUMMY_WAIT {__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();} +#define ADC_RESTART_DUMMY_WAIT BL602_Delay_US(100) + +/*@} end of group ADC_Private_Macros */ + +/** @defgroup ADC_Private_Types + * @{ + */ + +/*@} end of group ADC_Private_Types */ + +/** @defgroup ADC_Private_Variables + * @{ + */ +static intCallback_Type * adcIntCbfArra[ADC_INT_ALL]={NULL}; +static ADC_Gain_Coeff_Type adcGainCoeffCal = { + .adcGainCoeffEnable = DISABLE, + .adcgainCoeffVal = 0, + .coe=1, +}; + +/*@} end of group ADC_Private_Variables */ + +/** @defgroup ADC_Global_Variables + * @{ + */ + +/*@} end of group ADC_Global_Variables */ + +/** @defgroup ADC_Private_Fun_Declaration + * @{ + */ + +/*@} end of group ADC_Private_Fun_Declaration */ + +/** @defgroup ADC_Private_Functions + * @{ + */ + +/*@} end of group ADC_Private_Functions */ + +/** @defgroup ADC_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief Software reset the whole ADC + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_Reset(void) +{ + uint32_t regCmd; + + /* reset ADC */ + regCmd=BL_RD_REG(AON_BASE,AON_GPADC_REG_CMD); + BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,BL_SET_REG_BIT(regCmd,AON_GPADC_SOFT_RST)); + AON_CLK_SET_DUMMY_WAIT; + BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,BL_CLR_REG_BIT(regCmd,AON_GPADC_SOFT_RST)); +} + +/****************************************************************************//** + * @brief ADC glable enable + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_Enable(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_CMD); + tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_GLOBAL_EN); + BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,tmpVal); +} + +/****************************************************************************//** + * @brief ADC glable disable + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_Disable(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_CMD); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_GLOBAL_EN); + BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,tmpVal); +} + + +/****************************************************************************//** + * @brief ADC normal mode init + * + * @param cfg: ADC normal mode configuration + * + * @return None + * +*******************************************************************************/ +void ADC_Init(ADC_CFG_Type* cfg) +{ + uint32_t regCfg1; + uint32_t regCfg2; + uint32_t regCalib; + + CHECK_PARAM(IS_ADC_V18_SEL_TYPE(cfg->v18Sel)); + CHECK_PARAM(IS_ADC_V11_SEL_TYPE(cfg->v11Sel)); + CHECK_PARAM(IS_ADC_CLK_TYPE(cfg->clkDiv)); + CHECK_PARAM(IS_ADC_PGA_GAIN_TYPE(cfg->gain1)); + CHECK_PARAM(IS_ADC_PGA_GAIN_TYPE(cfg->gain2)); + CHECK_PARAM(IS_ADC_CHOP_MOD_TYPE(cfg->chopMode)); + CHECK_PARAM(IS_ADC_BIAS_SEL_TYPE(cfg->biasSel)); + CHECK_PARAM(IS_ADC_PGA_VCM_TYPE(cfg->vcm)); + CHECK_PARAM(IS_ADC_VREF_TYPE(cfg->vref)); + CHECK_PARAM(IS_ADC_SIG_INPUT_TYPE(cfg->inputMode)); + CHECK_PARAM(IS_ADC_DATA_WIDTH_TYPE(cfg->resWidth)); + + /* config 1 */ + regCfg1=BL_RD_REG(AON_BASE,AON_GPADC_REG_CONFIG1); + regCfg1=BL_SET_REG_BITS_VAL(regCfg1,AON_GPADC_V18_SEL,cfg->v18Sel); + regCfg1=BL_SET_REG_BITS_VAL(regCfg1,AON_GPADC_V11_SEL,cfg->v11Sel); + regCfg1=BL_CLR_REG_BIT(regCfg1,AON_GPADC_DITHER_EN); + regCfg1=BL_CLR_REG_BIT(regCfg1,AON_GPADC_SCAN_EN); + regCfg1=BL_SET_REG_BITS_VAL(regCfg1,AON_GPADC_SCAN_LENGTH,0); + regCfg1=BL_SET_REG_BITS_VAL(regCfg1,AON_GPADC_CLK_DIV_RATIO,cfg->clkDiv); + regCfg1=BL_CLR_REG_BIT(regCfg1,AON_GPADC_CLK_ANA_INV); + regCfg1=BL_SET_REG_BITS_VAL(regCfg1,AON_GPADC_CAL_OS_EN,cfg->offsetCalibEn); + regCfg1=BL_SET_REG_BITS_VAL(regCfg1,AON_GPADC_RES_SEL,cfg->resWidth); + BL_WR_REG(AON_BASE,AON_GPADC_REG_CONFIG1,regCfg1); + AON_CLK_SET_DUMMY_WAIT; + + /* config 2 */ + regCfg2=BL_RD_REG(AON_BASE,AON_GPADC_REG_CONFIG2); + regCfg2=BL_SET_REG_BITS_VAL(regCfg2,AON_GPADC_DLY_SEL,0); + regCfg2=BL_SET_REG_BITS_VAL(regCfg2,AON_GPADC_PGA1_GAIN,cfg->gain1); + regCfg2=BL_SET_REG_BITS_VAL(regCfg2,AON_GPADC_PGA2_GAIN,cfg->gain2); + regCfg2=BL_SET_REG_BITS_VAL(regCfg2,AON_GPADC_BIAS_SEL,cfg->biasSel); + + /* chopmode cannot be set by user any more*/ + if((cfg->gain1!=ADC_PGA_GAIN_NONE)||(cfg->gain2!=ADC_PGA_GAIN_NONE)){ + regCfg2=BL_SET_REG_BITS_VAL(regCfg2,AON_GPADC_CHOP_MODE,2); + }else{ + regCfg2=BL_SET_REG_BITS_VAL(regCfg2,AON_GPADC_CHOP_MODE,1); + } + /* pga_vcmi_en is for mic */ + regCfg2=BL_CLR_REG_BIT(regCfg2,AON_GPADC_PGA_VCMI_EN); + if((cfg->gain1!=ADC_PGA_GAIN_NONE)||(cfg->gain2!=ADC_PGA_GAIN_NONE)){ + regCfg2=BL_SET_REG_BIT(regCfg2,AON_GPADC_PGA_EN); + }else{ + regCfg2=BL_CLR_REG_BIT(regCfg2,AON_GPADC_PGA_EN); + } + /* pga_os_cal is for mic */ + regCfg2=BL_SET_REG_BITS_VAL(regCfg2,AON_GPADC_PGA_OS_CAL,8); + regCfg2=BL_SET_REG_BITS_VAL(regCfg2,AON_GPADC_PGA_VCM,cfg->vcm); + regCfg2=BL_SET_REG_BITS_VAL(regCfg2,AON_GPADC_VREF_SEL,cfg->vref); + regCfg2=BL_SET_REG_BITS_VAL(regCfg2,AON_GPADC_DIFF_MODE,cfg->inputMode); + + BL_WR_REG(AON_BASE,AON_GPADC_REG_CONFIG2,regCfg2); + + /* calibration offset */ + regCalib=BL_RD_REG(AON_BASE,AON_GPADC_REG_DEFINE); + regCalib=BL_SET_REG_BITS_VAL(regCalib,AON_GPADC_OS_CAL_DATA,cfg->offsetCalibVal); + BL_WR_REG(AON_BASE,AON_GPADC_REG_DEFINE,regCalib); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(GPADC_DMA_IRQn,GPADC_DMA_IRQHandler); +#endif + + ADC_Gain_Trim(); +} + +/****************************************************************************//** + * @brief ADC normal mode channel config + * + * @param posCh: ADC pos channel type + * @param negCh: ADC neg channel type + * @param contEn: ENABLE or DISABLE continuous mode + * + * @return None + * +*******************************************************************************/ +void ADC_Channel_Config(ADC_Chan_Type posCh,ADC_Chan_Type negCh,BL_Fun_Type contEn) +{ + uint32_t regCmd; + uint32_t regCfg1; + + CHECK_PARAM(IS_AON_ADC_CHAN_TYPE(posCh)); + CHECK_PARAM(IS_AON_ADC_CHAN_TYPE(negCh)); + + /* set channel */ + regCmd=BL_RD_REG(AON_BASE,AON_GPADC_REG_CMD); + regCmd=BL_SET_REG_BITS_VAL(regCmd,AON_GPADC_POS_SEL,posCh); + regCmd=BL_SET_REG_BITS_VAL(regCmd,AON_GPADC_NEG_SEL,negCh); + BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,regCmd); + + /* set continuous mode */ + regCfg1=BL_RD_REG(AON_BASE,AON_GPADC_REG_CONFIG1); + regCfg1=BL_SET_REG_BITS_VAL(regCfg1,AON_GPADC_CONT_CONV_EN,contEn); + regCfg1=BL_CLR_REG_BIT(regCfg1,AON_GPADC_SCAN_EN); + BL_WR_REG(AON_BASE,AON_GPADC_REG_CONFIG1,regCfg1); + +} + +/****************************************************************************//** + * @brief ADC scan mode channel config + * + * @param posChList[]: ADC pos channel list type + * @param negChList[]: ADC neg channel list type + * @param scanLength: ADC scan length + * @param contEn: ENABLE or DISABLE continuous mode + * + * @return None + * +*******************************************************************************/ +void ADC_Scan_Channel_Config(ADC_Chan_Type posChList[],ADC_Chan_Type negChList[],uint8_t scanLength,BL_Fun_Type contEn) +{ + uint32_t tmpVal,i; + uint32_t dealLen; + + CHECK_PARAM((scanLength<13)); + + /* Deal with the first 6 */ + dealLen=6; + if(scanLengthdealLen){ + tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_SCN_POS2); + for(i=0;ififoThreshold)); + + /* + * DMA enable : ,When the fifo data is exceeded to fifoThreshold DMA request will occur + * DMA disable : fifoThreshold determine how many data will raise FIFO ready interrupt + */ + + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPADC_FIFO_THL,fifoCfg->fifoThreshold); + + /* Enable DMA */ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPADC_DMA_EN,fifoCfg->dmaEn); + + BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal); + + /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG); + tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPADC_FIFO_CLR); + BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal); + +} + +/****************************************************************************//** + * @brief ADC get DMA FIFO data count + * + * @param None + * + * @return data count in FIFO + * +*******************************************************************************/ +uint8_t ADC_Get_FIFO_Count(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG); + + return BL_GET_REG_BITS_VAL(tmpVal,GPIP_GPADC_FIFO_DATA_COUNT); +} + +/****************************************************************************//** + * @brief ADC get DMA FIFO full status + * + * @param None + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type ADC_FIFO_Is_Full(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG); + + if(BL_IS_REG_BIT_SET(tmpVal,GPIP_GPADC_FIFO_FULL)){ + return SET; + }else{ + return RESET; + } +} + +/****************************************************************************//** + * @brief ADC get DMA FIFO empty status + * + * @param None + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type ADC_FIFO_Is_Empty(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG); + + if(BL_IS_REG_BIT_SET(tmpVal,GPIP_GPADC_FIFO_NE)){ + return RESET; + }else{ + return SET; + } +} + + + + +/****************************************************************************//** + * @brief ADC read DMA FIFO data + * + * @param None + * + * @return ADC result if return 0 that means this is error data,user should ignore this data. + * +*******************************************************************************/ +uint32_t ADC_Read_FIFO(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_DMA_RDATA); + + return (tmpVal); +} + +/****************************************************************************//** + * @brief ADC parse result + * + * @param orgVal: Original A to D value + * @param len: Original AD vaule count + * @param result: Final Result array pointer + * + * @return None + * +*******************************************************************************/ +void ADC_Parse_Result(uint32_t *orgVal,uint32_t len,ADC_Result_Type *result) +{ + uint8_t neg=0; + uint32_t tmpVal1=0,tmpVal2=0; + ADC_Data_Width_Type dataType; + ADC_SIG_INPUT_Type sigType; + float ref=2.0; + uint32_t i=0; + + float coe=1.0; + + if(adcGainCoeffCal.adcGainCoeffEnable){ + coe=adcGainCoeffCal.coe; + } + + tmpVal1=BL_RD_REG(AON_BASE,AON_GPADC_REG_CONFIG1); + tmpVal2=BL_RD_REG(AON_BASE,AON_GPADC_REG_CONFIG2); + dataType=BL_GET_REG_BITS_VAL(tmpVal1,AON_GPADC_RES_SEL); + sigType=BL_GET_REG_BITS_VAL(tmpVal2,AON_GPADC_DIFF_MODE); + + if(BL_GET_REG_BITS_VAL(tmpVal2,AON_GPADC_VREF_SEL)==ADC_VREF_3P2V){ + ref=3.2; + } + if(sigType==ADC_INPUT_SINGLE_END){ + for(i=0;i>21; + result[i].negChan=-1; + if(dataType==ADC_DATA_WIDTH_12){ + result[i].value=(unsigned int)(((orgVal[i]&0xffff)>>4)/coe); + result[i].volt=result[i].value/4096.0*ref; + }else if(dataType==ADC_DATA_WIDTH_14_WITH_16_AVERAGE){ + result[i].value=(unsigned int)(((orgVal[i]&0xffff)>>2)/coe); + result[i].volt=result[i].value/16384.0*ref; + }else if(dataType==ADC_DATA_WIDTH_16_WITH_64_AVERAGE||dataType==ADC_DATA_WIDTH_16_WITH_256_AVERAGE){ + result[i].value=(unsigned int)((orgVal[i]&0xffff)/coe); + result[i].volt=result[i].value/65536.0*ref; + } + } + }else{ + for(i=0;i>21; + result[i].negChan=(orgVal[i]>>16)&0x1F; + + if(orgVal[i]&0x8000){ + orgVal[i] = ~orgVal[i]; + orgVal[i] += 1; + neg = 1; + } + if(dataType==ADC_DATA_WIDTH_12){ + result[i].value=(unsigned int)(((orgVal[i]&0xffff)>>4)/coe); + result[i].volt=result[i].value/2048.0*ref; + }else if(dataType==ADC_DATA_WIDTH_14_WITH_16_AVERAGE){ + result[i].value=(unsigned int)(((orgVal[i]&0xffff)>>2)/coe); + result[i].volt=result[i].value/8192.0*ref; + }else if(dataType==ADC_DATA_WIDTH_16_WITH_64_AVERAGE||dataType==ADC_DATA_WIDTH_16_WITH_256_AVERAGE){ + result[i].value=(unsigned int)((orgVal[i]&0xffff)/coe); + result[i].volt=result[i].value/32768.0*ref; + } + if(neg){ + result[i].volt = - result[i].volt; + } + } + } +} + +/****************************************************************************//** + * @brief ADC mask or unmask certain or all interrupt + * + * @param intType: interrupt type + * @param intMask: mask or unmask + * + * @return None + * +*******************************************************************************/ +void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); + CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); + + switch(intType) + { + case ADC_INT_POS_SATURATION: + tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_ISR); + if(intMask == UNMASK){ + /* Enable this interrupt */ + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_POS_SATUR_MASK); + }else{ + /* Disable this interrupt */ + tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_POS_SATUR_MASK); + } + BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal); + break; + case ADC_INT_NEG_SATURATION: + tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_ISR); + if(intMask == UNMASK){ + /* Enable this interrupt */ + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_NEG_SATUR_MASK); + }else{ + /* Disable this interrupt */ + tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_NEG_SATUR_MASK); + } + BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal); + break; + case ADC_INT_FIFO_UNDERRUN: + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG); + if(intMask == UNMASK){ + /* Enable this interrupt */ + tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_FIFO_UNDERRUN_MASK); + }else{ + /* Disable this interrupt */ + tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPADC_FIFO_UNDERRUN_MASK); + } + BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal); + break; + case ADC_INT_FIFO_OVERRUN: + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG); + if(intMask == UNMASK){ + /* Enable this interrupt */ + tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_FIFO_OVERRUN_MASK); + }else{ + /* Disable this interrupt */ + tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPADC_FIFO_OVERRUN_MASK); + } + BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal); + break; + case ADC_INT_ADC_READY: + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG); + if(intMask == UNMASK){ + /* Enable this interrupt */ + tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_RDY_MASK); + }else{ + /* Disable this interrupt */ + tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPADC_RDY_MASK); + } + BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal); + break; + case ADC_INT_ALL: + if(intMask == UNMASK){ + /* Enable this interrupt */ + tmpVal=BL_RD_REG(GPIP_BASE,AON_GPADC_REG_ISR); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_POS_SATUR_MASK); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_NEG_SATUR_MASK); + BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal); + + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG); + tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_FIFO_UNDERRUN_MASK); + tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_FIFO_OVERRUN_MASK); + tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_RDY_MASK); + BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal); + }else{ + /* Disable this interrupt */ + tmpVal=BL_RD_REG(GPIP_BASE,AON_GPADC_REG_ISR); + tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_POS_SATUR_MASK); + tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_NEG_SATUR_MASK); + BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal); + + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG); + tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPADC_FIFO_OVERRUN_MASK); + tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPADC_FIFO_UNDERRUN_MASK); + tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPADC_RDY_MASK); + BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal); + } + break; + default: + break; + } +} + +/****************************************************************************//** + * @brief ADC clear certain or all interrupt + * + * @param intType: interrupt type + * + * @return None + * +*******************************************************************************/ +void ADC_IntClr(ADC_INT_Type intType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); + + switch(intType) + { + case ADC_INT_POS_SATURATION: + tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_ISR); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_POS_SATUR_CLR); + BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal); + + tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_POS_SATUR_CLR); + BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal); + + /*Manual reset*/ + tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_ISR); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_POS_SATUR_CLR); + BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal); + + break; + case ADC_INT_NEG_SATURATION: + tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_ISR); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal); + + tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal); + + /*Manual reset*/ + tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_ISR); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal); + + break; + case ADC_INT_FIFO_UNDERRUN: + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG); + tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_FIFO_UNDERRUN_CLR); + BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal); + + tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPADC_FIFO_UNDERRUN_CLR); + BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal); + + /*Manual reset*/ + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG); + tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_FIFO_UNDERRUN_CLR); + BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal); + + break; + case ADC_INT_FIFO_OVERRUN: + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG); + tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_FIFO_OVERRUN_CLR); + BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal); + + tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPADC_FIFO_OVERRUN_CLR); + BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal); + + /*Manual reset*/ + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG); + tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_FIFO_OVERRUN_CLR); + BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal); + + break; + case ADC_INT_ADC_READY: + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG); + tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal); + + tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal); + + /*Manual reset*/ + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG); + tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal); + + break; + case ADC_INT_ALL: + tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_ISR); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_POS_SATUR_CLR); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal); + + tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_POS_SATUR_CLR); + tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal); + + /*Manual reset*/ + tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_ISR); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_POS_SATUR_CLR); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal); + + + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG); + tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_FIFO_UNDERRUN_CLR); + tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_FIFO_OVERRUN_CLR); + tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal); + + tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPADC_FIFO_UNDERRUN_CLR); + tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPADC_FIFO_OVERRUN_CLR); + tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal); + + /*Manual reset*/ + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG); + tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_FIFO_UNDERRUN_CLR); + tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_FIFO_OVERRUN_CLR); + tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal); + + + break; + default: + break; + } +} + +/****************************************************************************//** + * @brief ADC get interrupt status + * + * @param intType: interrupt type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type ADC_GetIntStatus(ADC_INT_Type intType) +{ + uint32_t tmpVal; + BL_Sts_Type bitStatus = RESET; + + /* Check the parameters */ + CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); + + switch(intType) + { + case ADC_INT_POS_SATURATION: + tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_ISR); + bitStatus = (BL_IS_REG_BIT_SET(tmpVal,AON_GPADC_POS_SATUR))?SET:RESET; + break; + case ADC_INT_NEG_SATURATION: + tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_ISR); + bitStatus = (BL_IS_REG_BIT_SET(tmpVal,AON_GPADC_NEG_SATUR))?SET:RESET; + break; + case ADC_INT_FIFO_UNDERRUN: + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG); + bitStatus = (BL_IS_REG_BIT_SET(tmpVal,GPIP_GPADC_FIFO_UNDERRUN)) ? SET : RESET; + break; + case ADC_INT_FIFO_OVERRUN: + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG); + bitStatus = (BL_IS_REG_BIT_SET(tmpVal,GPIP_GPADC_FIFO_OVERRUN)) ? SET : RESET; + break; + case ADC_INT_ADC_READY: + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG); + bitStatus = (BL_IS_REG_BIT_SET(tmpVal,GPIP_GPADC_RDY)) ? SET : RESET; + break; + case ADC_INT_ALL: + break; + default: + break; + } + + return bitStatus; +} + +/****************************************************************************//** + * @brief ADC install interrupt callback + * + * @param intType: ADC interrupt type + * @param cbFun: ADC interrupt callback + * + * @return None + * +*******************************************************************************/ +void ADC_Int_Callback_Install(ADC_INT_Type intType,intCallback_Type* cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); + + adcIntCbfArra[intType] = cbFun; +} + +/****************************************************************************//** + * @brief ADC DMA interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void GPADC_DMA_IRQHandler(void) +{ + if( ADC_GetIntStatus(ADC_INT_POS_SATURATION)==SET ){ + ADC_IntClr(ADC_INT_POS_SATURATION); + if(adcIntCbfArra[ADC_INT_POS_SATURATION] != NULL){ + adcIntCbfArra[ADC_INT_POS_SATURATION](); + } + } + if( ADC_GetIntStatus(ADC_INT_NEG_SATURATION)==SET ){ + ADC_IntClr(ADC_INT_NEG_SATURATION); + if(adcIntCbfArra[ADC_INT_NEG_SATURATION] != NULL){ + adcIntCbfArra[ADC_INT_NEG_SATURATION](); + } + } + + if( ADC_GetIntStatus(ADC_INT_FIFO_UNDERRUN)==SET ){ + ADC_IntClr(ADC_INT_FIFO_UNDERRUN); + if(adcIntCbfArra[ADC_INT_FIFO_UNDERRUN] != NULL){ + adcIntCbfArra[ADC_INT_FIFO_UNDERRUN](); + } + } + + if( ADC_GetIntStatus(ADC_INT_FIFO_OVERRUN)==SET ){ + ADC_IntClr(ADC_INT_FIFO_OVERRUN); + if(adcIntCbfArra[ADC_INT_FIFO_OVERRUN] != NULL){ + adcIntCbfArra[ADC_INT_FIFO_OVERRUN](); + } + } + + if( ADC_GetIntStatus(ADC_INT_ADC_READY)==SET ){ + ADC_IntClr(ADC_INT_ADC_READY); + if(adcIntCbfArra[ADC_INT_ADC_READY] != NULL){ + adcIntCbfArra[ADC_INT_ADC_READY](); + } + } +} +#endif + +/****************************************************************************//** + * @brief ADC VBAT enable + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_Vbat_Enable(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_CONFIG2); + tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_VBAT_EN); + BL_WR_REG(AON_BASE,AON_GPADC_REG_CONFIG2,tmpVal); +} + +/****************************************************************************//** + * @brief ADC VBAT disable + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_Vbat_Disable(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_CONFIG2); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_VBAT_EN); + BL_WR_REG(AON_BASE,AON_GPADC_REG_CONFIG2,tmpVal); +} + +/****************************************************************************//** + * @brief ADC TSEN Config + * + * @param tsenMod: None + * + * @return None + * +*******************************************************************************/ +void ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_AON_ADC_TSEN_MOD_TYPE(type)); + + /* config gpadc_reg_cmd */ + tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_CMD); + /* enable sensor dc test mux*/ + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_SEN_TEST_EN); + /*selected sen output current channel*/ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_GPADC_SEN_SEL,0); + /* enable chip sensor*/ + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_CHIP_SEN_PU); + /*dwa_en */ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_GPADC_DWA_EN,1); + BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,tmpVal); + + /* config 2 */ + tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_CONFIG2); + /*tsvbe low=0*/ + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_TSVBE_LOW); + /*dly_sel=2*/ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_GPADC_DLY_SEL,2); + /*test_sel=0*/ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_GPADC_TEST_SEL,0); + /*test_en=0*/ + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_TEST_EN); + /*ts_en*/ + tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_TS_EN); + /*select tsen ext or inner*/ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_GPADC_TSEXT_SEL,tsenMod); + + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_GPADC_PGA_VCM,2); + /*pga vcmi enable*/ + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_PGA_VCMI_EN); + /*0:512uS;1:16mS;2:32mS;3:64mS*/ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_GPADC_PGA_OS_CAL,0); + + BL_WR_REG(AON_BASE,AON_GPADC_REG_CONFIG2,tmpVal); + + /* config 3 */ + tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_CONFIG1); + /* set gpadc_dither_en */ + tmpVal = BL_SET_REG_BIT(tmpVal,AON_GPADC_DITHER_EN); + BL_WR_REG(AON_BASE,AON_GPADC_REG_CONFIG1,tmpVal); + + /* set 4000F90C[19](gpadc_mic2_diff) = 1 + * debug advise form Ran + * 2020.08.26 + */ + tmpVal = BL_RD_REG(AON_BASE,AON_GPADC_REG_CMD); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,AON_GPADC_MIC2_DIFF,1); + BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,tmpVal); +} + + +/****************************************************************************//** + * @brief TSEN_Get_V_Error + * + * @param None + * + * @return None + * +*******************************************************************************/ +uint32_t TSEN_Get_V_Error(void) +{ + uint32_t v0 = 0, v1 = 0; + uint32_t v_error = 0; + uint32_t regVal = 0; + ADC_Result_Type result; + uint32_t tmpVal; + uint8_t gainCalEnabled=0; + + /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + ADC_SET_TSVBE_LOW(); + + ADC_Start(); + while (ADC_Get_FIFO_Count() == 0) + ; + regVal = ADC_Read_FIFO(); + gainCalEnabled=adcGainCoeffCal.adcGainCoeffEnable; + adcGainCoeffCal.adcGainCoeffEnable=0; + ADC_Parse_Result(®Val, 1, &result); + adcGainCoeffCal.adcGainCoeffEnable=gainCalEnabled; + v0 = result.value; + + /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + + ADC_SET_TSVBE_HIGH(); + + ADC_Start(); + while (ADC_Get_FIFO_Count() == 0) + ; + regVal = ADC_Read_FIFO(); + gainCalEnabled=adcGainCoeffCal.adcGainCoeffEnable; + adcGainCoeffCal.adcGainCoeffEnable=0; + ADC_Parse_Result(®Val, 1, &result); + adcGainCoeffCal.adcGainCoeffEnable=gainCalEnabled; + v1 = result.value; + + v_error = v0 - v1; + + return v_error; +} + + +/****************************************************************************//** + * @brief Trim TSEN + * + * @param tsen_offset: None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION ADC_Trim_TSEN(uint16_t * tsen_offset) +{ + uint8_t average_index = 0; + uint32_t v_error_sum=0; + uint32_t tmpVal=0; + float A1=0.0,A2=0.0,C=0.0,delta=0.0; + Efuse_TSEN_Refcode_Corner_Type trim; + + EF_Ctrl_Read_TSEN_Trim(&trim); + + if(trim.tsenRefcodeCornerEn){ + if(trim.tsenRefcodeCornerParity==EF_Ctrl_Get_Trim_Parity(trim.tsenRefcodeCorner,12)){ + + MSG("TSEN ATE Version = %d\r\n",trim.tsenRefcodeCornerVersion); + + *tsen_offset = trim.tsenRefcodeCorner; + + if(trim.tsenRefcodeCornerVersion == 0){ + /* debug advise by ran + * 2020.9.04 + */ + + //set 4000F90C[19](gpadc_mic2_diff) = 0 + tmpVal = BL_RD_REG(AON_BASE,AON_GPADC_REG_CMD); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,AON_GPADC_MIC2_DIFF,0); + BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,tmpVal); + + for(average_index=0;average_index<50;average_index++){ + v_error_sum += TSEN_Get_V_Error(); + } + + v_error_sum /= 50; + + MSG("A1 = %d\r\n",v_error_sum); + A1 = v_error_sum; + + v_error_sum = 0; + + //set 4000F90C[19](gpadc_mic2_diff) = 1 + tmpVal = BL_RD_REG(AON_BASE,AON_GPADC_REG_CMD); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,AON_GPADC_MIC2_DIFF,1); + BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,tmpVal); + + for(average_index=0;average_index<50;average_index++){ + v_error_sum += TSEN_Get_V_Error(); + } + + v_error_sum /= 50; + + MSG("A2 = %d\r\n",v_error_sum); + A2 = v_error_sum; + + MSG("C = %d\r\n",*tsen_offset); + C = *tsen_offset; + + delta = A2 - (7.753 / 5.62 * A1) + 2.133 / 5.62 * C + 72; + + MSG("delta=A2-7.753/5.62*A1+2.133/5.62*C+72x; delta = %d\r\n",(uint16_t)delta); + + *tsen_offset = delta + C; + + } + return SUCCESS; + } + } + + return ERROR; +} + +/****************************************************************************//** + * @brief SET ADC TSEN TSVBE LOW/HIGH + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_SET_TSVBE_LOW(void) +{ + uint32_t tmpVal; + tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_CONFIG2); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_TSVBE_LOW); + BL_WR_REG(AON_BASE,AON_GPADC_REG_CONFIG2,tmpVal); +} + +/****************************************************************************//** + * @brief SET ADC TSEN TSVBE LOW/HIGH + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_SET_TSVBE_HIGH(void) +{ + uint32_t tmpVal; + tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_CONFIG2); + tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_TSVBE_LOW); + BL_WR_REG(AON_BASE,AON_GPADC_REG_CONFIG2,tmpVal); +} + +/****************************************************************************//** + * @brief SET ADC TSEN TSVBE LOW/HIGH + * + * @param tsen_offset: tsen_offset form efuse trim data + * + * @return tempture + * +*******************************************************************************/ +float TSEN_Get_Temp(uint32_t tsen_offset) +{ + uint32_t v0 = 0, v1 = 0; + float temp = 0; + uint32_t regVal = 0; + ADC_Result_Type result; + uint32_t tmpVal; + uint8_t gainCalEnabled=0; + + /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + ADC_SET_TSVBE_LOW(); + + ADC_Start(); + while (ADC_Get_FIFO_Count() == 0) + ; + regVal = ADC_Read_FIFO(); + + gainCalEnabled=adcGainCoeffCal.adcGainCoeffEnable; + adcGainCoeffCal.adcGainCoeffEnable=0; + ADC_Parse_Result(®Val, 1, &result); + adcGainCoeffCal.adcGainCoeffEnable=gainCalEnabled; + v0 = result.value; + + /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + + ADC_SET_TSVBE_HIGH(); + + ADC_Start(); + while (ADC_Get_FIFO_Count() == 0) + ; + regVal = ADC_Read_FIFO(); + gainCalEnabled=adcGainCoeffCal.adcGainCoeffEnable; + adcGainCoeffCal.adcGainCoeffEnable=0; + ADC_Parse_Result(®Val, 1, &result); + adcGainCoeffCal.adcGainCoeffEnable=gainCalEnabled; + v1 = result.value; + + if (v0 > v1) + { + temp = (((float)v0 - (float)v1) - (float)tsen_offset) / 7.753; + } + else + { + temp = (((float)v1 - (float)v0) - (float)tsen_offset) / 7.753; + } + + return temp; +} + + +/****************************************************************************//** + * @brief ADC MIC Config + * + * @param adc_mic_config: adc_mic_config + * + * @return success or not + * +*******************************************************************************/ +BL_Err_Type ADC_Mic_Init(ADC_MIC_Type * adc_mic_config) +{ + uint32_t tmpVal1=0,tmpVal2=0; + + CHECK_PARAM(IS_ADC_MICBOOST_DB_Type(adc_mic_config->micboostDb)); + CHECK_PARAM(IS_PGA2_GAIN_Type(adc_mic_config->micPga2Gain)); + CHECK_PARAM(IS_ADC_MIC_MODE_Type(adc_mic_config->mic1Mode)); + CHECK_PARAM(IS_ADC_MIC_MODE_Type(adc_mic_config->mic2Mode)); + CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->dwaEn)); + CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micboostBypassEn)); + CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micPgaEn)); + CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micBiasEn)); + + tmpVal2 = BL_RD_REG(AON_BASE,AON_GPADC_REG_CONFIG2); + + tmpVal1=BL_RD_REG(AON_BASE,AON_GPADC_REG_CMD); + tmpVal1=BL_SET_REG_BITS_VAL(tmpVal1,AON_GPADC_MICBOOST_32DB_EN,adc_mic_config->micboostDb); + tmpVal1=BL_SET_REG_BITS_VAL(tmpVal1,AON_GPADC_MIC_PGA2_GAIN,adc_mic_config->micPga2Gain); + tmpVal1=BL_SET_REG_BITS_VAL(tmpVal1,AON_GPADC_MIC1_DIFF,adc_mic_config->mic1Mode); + tmpVal1=BL_SET_REG_BITS_VAL(tmpVal1,AON_GPADC_MIC2_DIFF,adc_mic_config->mic2Mode); + tmpVal1=BL_SET_REG_BITS_VAL(tmpVal1,AON_GPADC_DWA_EN,adc_mic_config->dwaEn); + tmpVal1=BL_SET_REG_BITS_VAL(tmpVal1,AON_GPADC_BYP_MICBOOST,adc_mic_config->micboostBypassEn); + + if(BL_IS_REG_BIT_SET(tmpVal2,AON_GPADC_PGA_EN) && adc_mic_config->micPgaEn == ENABLE){ + /* 0x4000F914[13] and 0x4000F90c[15] Cannot be both Enable*/ + return ERROR; + }else{ + tmpVal1=BL_SET_REG_BITS_VAL(tmpVal1,AON_GPADC_MICPGA_EN,adc_mic_config->micPgaEn); + } + + tmpVal1=BL_SET_REG_BITS_VAL(tmpVal1,AON_GPADC_MICBIAS_EN,adc_mic_config->micBiasEn); + + BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,tmpVal1); + + return SUCCESS; + +} + + +/****************************************************************************//** + * @brief ADC MIC bias control + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_MIC_Bias_Enable(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_CMD); + tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_MICBIAS_EN); + BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,tmpVal); +} + + +/****************************************************************************//** + * @brief ADC MIC bias control + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ADC_MIC_Bias_Disable(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_CMD); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_MICBIAS_EN); + BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,tmpVal); +} + + +/****************************************************************************//** + * @brief Trim ADC Gain + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION ADC_Gain_Trim(void) +{ + Efuse_ADC_Gain_Coeff_Type trim; + uint32_t tmp; + + EF_Ctrl_Read_ADC_Gain_Trim(&trim); + + if(trim.adcGainCoeffEn){ + if(trim.adcGainCoeffParity==EF_Ctrl_Get_Trim_Parity(trim.adcGainCoeff,12)){ + adcGainCoeffCal.adcGainCoeffEnable = ENABLE; + adcGainCoeffCal.adcgainCoeffVal = trim.adcGainCoeff; + tmp=adcGainCoeffCal.adcgainCoeffVal; + if(tmp & 0x800){ + tmp = ~ tmp; + tmp += 1; + tmp = tmp&0xfff; + //printf("val==%08x\r\n",(unsigned int)tmp); + adcGainCoeffCal.coe=(1.0+((float)tmp/2048.0)); + //printf("coe==%0f\r\n",adcGainCoeffCal.coe); + }else{ + adcGainCoeffCal.coe=(1.0-((float)tmp/2048.0)); + //printf("coe==%0f\r\n",adcGainCoeffCal.coe); + } + + return SUCCESS; + } + } + + return ERROR; +} + +/*@} end of group ADC_Public_Functions */ + +/*@} end of group ADC */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/bl602_driver/std_drv/src/bl602_aon.c b/drivers/bl602_driver/std_drv/src/bl602_aon.c new file mode 100644 index 00000000..c9cf2c5a --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_aon.c @@ -0,0 +1,541 @@ +/** + ****************************************************************************** + * @file bl602_aon.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_aon.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup AON + * @{ + */ + +/** @defgroup AON_Private_Macros + * @{ + */ +#define AON_CLK_SET_DUMMY_WAIT {__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();} + +/*@} end of group AON_Private_Macros */ + +/** @defgroup AON_Private_Types + * @{ + */ + +/*@} end of group AON_Private_Types */ + +/** @defgroup AON_Private_Variables + * @{ + */ + +/*@} end of group AON_Private_Variables */ + +/** @defgroup AON_Global_Variables + * @{ + */ + +/*@} end of group AON_Global_Variables */ + +/** @defgroup AON_Private_Fun_Declaration + * @{ + */ + +/*@} end of group AON_Private_Fun_Declaration */ + +/** @defgroup AON_Private_Functions + * @{ + */ + +/*@} end of group AON_Private_Functions */ + +/** @defgroup AON_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief Power on MXX band gap + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void) +{ + uint32_t tmpVal = 0; + + /* Power up RF for PLL to work */ + tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON); + tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_MBG_AON); + BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal); + + BL602_Delay_US(55); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief Power off MXX band gap + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void) +{ + uint32_t tmpVal = 0; + + /* Power OFF */ + tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_MBG_AON); + BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief Power on XTAL + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void) +{ + uint32_t tmpVal = 0; + uint32_t timeOut=0; + + tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON); + tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_XTAL_AON); + tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_XTAL_BUF_AON); + BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal); + + /* Polling for ready */ + do{ + BL602_Delay_US(10); + timeOut++; + tmpVal=BL_RD_REG(AON_BASE,AON_TSEN); + }while(!BL_IS_REG_BIT_SET(tmpVal,AON_XTAL_RDY)&&timeOut<120); + + if(timeOut>=120){ + return TIMEOUT; + } + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief Set XTAL cap code + * + * @param capIn: Cap code in + * @param capOut: Cap code out + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn,uint8_t capOut) +{ + uint32_t tmpVal = 0; + + tmpVal=BL_RD_REG(AON_BASE,AON_XTAL_CFG); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_XTAL_CAPCODE_IN_AON,capIn); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_XTAL_CAPCODE_OUT_AON,capOut); + BL_WR_REG(AON_BASE,AON_XTAL_CFG,tmpVal); + + BL602_Delay_US(100); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief Get XTAL cap code + * + * @param None + * + * @return Cap code + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void) +{ + uint32_t tmpVal = 0; + + tmpVal=BL_RD_REG(AON_BASE,AON_XTAL_CFG); + + return BL_GET_REG_BITS_VAL(tmpVal,AON_XTAL_CAPCODE_IN_AON); +} +#endif + +/****************************************************************************//** + * @brief Power off XTAL + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void) +{ + uint32_t tmpVal = 0; + + tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_XTAL_AON); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_XTAL_BUF_AON); + BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief Power on bandgap system + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void) +{ + uint32_t tmpVal = 0; + + /* power up RF for PLL to work */ + tmpVal=BL_RD_REG(AON_BASE,AON_BG_SYS_TOP); + tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_BG_SYS_AON); + BL_WR_REG(AON_BASE,AON_BG_SYS_TOP,tmpVal); + + BL602_Delay_US(55); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief Power off bandgap system + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void) +{ + uint32_t tmpVal = 0; + + /* power up RF for PLL to work */ + tmpVal=BL_RD_REG(AON_BASE,AON_BG_SYS_TOP); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_BG_SYS_AON); + BL_WR_REG(AON_BASE,AON_BG_SYS_TOP,tmpVal); + + BL602_Delay_US(55); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief Power on LDO11 + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO11_SOC(void) +{ + uint32_t tmpVal = 0; + + tmpVal=BL_RD_REG(AON_BASE,AON_LDO11SOC_AND_DCTEST); + tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_LDO11SOC_AON); + BL_WR_REG(AON_BASE,AON_LDO11SOC_AND_DCTEST,tmpVal); + + BL602_Delay_US(55); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief Power off LDO11 + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO11_SOC(void) +{ + uint32_t tmpVal = 0; + + tmpVal=BL_RD_REG(AON_BASE,AON_LDO11SOC_AND_DCTEST); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_LDO11SOC_AON); + BL_WR_REG(AON_BASE,AON_LDO11SOC_AND_DCTEST,tmpVal); + + BL602_Delay_US(55); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief Power on LDO15_RF + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void) +{ + uint32_t tmpVal = 0; + + /* ldo15rf power on */ + tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON); + tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_LDO15RF_AON); + BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal); + + BL602_Delay_US(90); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief Power off LDO15_RF + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO15_RF(void) +{ + uint32_t tmpVal = 0; + + /* ldo15rf power off */ + tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_LDO15RF_AON); + BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief power on source follow regular + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void) +{ + uint32_t tmpVal = 0; + + /* power on sfreg */ + tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON); + tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_SFREG_AON); + BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal); + + BL602_Delay_US(10); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief power off source follow regular + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void) +{ + uint32_t tmpVal = 0; + + /* power off sfreg */ + tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_SFREG_AON); + BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief Power off the power can be shut down in PDS0 + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Enter_PDS0(void) +{ + uint32_t tmpVal = 0; + + /* power off sfreg */ + tmpVal=BL_RD_REG(AON_BASE,AON_MISC); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_SW_WB_EN_AON); + BL_WR_REG(AON_BASE,AON_MISC,tmpVal); + + tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_SFREG_AON); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_LDO15RF_AON); + tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_MBG_AON); + BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal); + + /* gating Clock */ + tmpVal=BL_RD_REG(GLB_BASE,GLB_CGEN_CFG0); + tmpVal=tmpVal&(~(1<<6)); + tmpVal=tmpVal&(~(1<<7)); + BL_WR_REG(GLB_BASE,GLB_CGEN_CFG0,tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief Power on the power powered down in PDS0 + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void) +{ + uint32_t tmpVal = 0; + + tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON); + + tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_MBG_AON); + BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal); + + BL602_Delay_US(20); + + tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_LDO15RF_AON); + BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal); + + BL602_Delay_US(60); + + tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_SFREG_AON); + BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal); + + BL602_Delay_US(20); + + /* power on wb */ + tmpVal=BL_RD_REG(AON_BASE,AON_MISC); + tmpVal=BL_SET_REG_BIT(tmpVal,AON_SW_WB_EN_AON); + BL_WR_REG(AON_BASE,AON_MISC,tmpVal); + + /* ungating Clock */ + tmpVal=BL_RD_REG(GLB_BASE,GLB_CGEN_CFG0); + tmpVal=tmpVal|((1<<6)); + tmpVal=tmpVal|((1<<7)); + BL_WR_REG(GLB_BASE,GLB_CGEN_CFG0,tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief Power on the power powered down in PDS0 + * + * @param delay: None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((delay<=0x3)); + + /* config ldo11soc_sstart_delay_aon */ + tmpVal=BL_RD_REG(AON_BASE,AON_LDO11SOC_AND_DCTEST); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_LDO11SOC_SSTART_DELAY_AON,delay); + BL_WR_REG(AON_BASE,AON_LDO11SOC_AND_DCTEST,tmpVal); + + return SUCCESS; +} + +/*@} end of group AON_Public_Functions */ + +/*@} end of group AON */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/bl602_driver/std_drv/src/bl602_common.c b/drivers/bl602_driver/std_drv/src/bl602_common.c new file mode 100644 index 00000000..d7f41400 --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_common.c @@ -0,0 +1,329 @@ +#include "l1c_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Periph_Driver + * @{ + */ + +/** @defgroup DRIVER_COMMON DRIVER_COMMON + * @brief Digger driver common functions + * @{ + */ + +/** @defgroup DRIVER_Private_Type + * @{ + */ + + +/*@} end of group DRIVER_Private_Type*/ + +/** @defgroup DRIVER_Private_Defines + * @{ + */ + +/*@} end of group DRIVER_Private_Defines */ + +/** @defgroup DRIVER_Private_Variables + * @{ + */ +pFunc __Interrupt_Handlers[IRQn_LAST]={0}; + +/*@} end of group DRIVER_Private_Variables */ + +/** @defgroup DRIVER_Global_Variables + * @{ + */ + +/*@} end of group DRIVER_Global_Variables */ + +/** @defgroup DRIVER_Private_FunctionDeclaration + * @{ + */ + +/*@} end of group DRIVER_Private_FunctionDeclaration */ + +/** @defgroup DRIVER_Private_Functions + * @{ + */ + +/*@} end of group DRIVER_Private_Functions */ + +/** @defgroup DRIVER_Public_Functions + * @{ + */ + +void Trap_Handler(void){ + unsigned long cause; + unsigned long epc; + unsigned long tval; + + MSG("Trap_Handler\r\n"); + + cause = read_csr(mcause); + MSG("mcause=%08x\r\n",(uint32_t)cause); + epc=read_csr(mepc); + MSG("mepc:%08x\r\n",(uint32_t)epc); + tval=read_csr(mtval); + MSG("mtval:%08x\r\n",(uint32_t)tval); + + cause=(cause&0x3ff); + switch(cause){ + case 1: + MSG("Instruction access fault\r\n"); + break; + case 2: + MSG("Illegal instruction\r\n"); + break; + case 3: + MSG("Breakpoint\r\n"); + break; + case 4: + MSG("Load address misaligned\r\n"); + break; + case 5: + MSG("Load access fault\r\n"); + break; + case 6: + MSG("Store/AMO address misaligned\r\n"); + break; + case 7: + MSG("Store/AMO access fault\r\n"); + break; + case 8: + MSG("Environment call from U-mode\r\n"); + epc+=4; + write_csr(mepc,epc); + break; + case 9: + MSG("Environment call from M-mode\r\n"); + epc+=4; + write_csr(mepc,epc); + break; + default: + MSG("Cause num=%d\r\n",(uint32_t)cause); + epc+=4; + write_csr(mepc,epc); + break; + } + while(1); +} + +void Interrupt_Handler_Register(IRQn_Type irq,pFunc interruptFun) +{ + if(irq=IRQ_NUM_BASE){ + MSG("Peripheral Interrupt num:%d \r\n",(unsigned int)num-IRQ_NUM_BASE); + } + while(1); + } + }else{ + MSG("Unexpected interrupt num:%d\r\n",(unsigned int)num); + } + } +} + +void FreeRTOS_Interrupt_Handler(void) +{ + Interrupt_Handler(); +} + +/****************************************************************************//** + * @brief delay us + * + * @param[in] core: systemcoreclock + * + * @param[in] cnt: delay cnt us + * + * @return none + * + *******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +#ifdef ARCH_ARM +#ifndef __GNUC__ +__WEAK +__ASM void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core,uint32_t cnt) +{ + lsrs r0,#0x10 + muls r0,r1,r0 + mov r2,r0 + lsrs r2,#0x04 + lsrs r2,#0x03 + cmp r2,#0x01 + beq end + cmp r2,#0x00 + beq end +loop + mov r0,r0 + mov r0,r0 + mov r0,r0 + mov r0,r0 + mov r0,r0 + subs r2,r2,#0x01 + cmp r2,#0x00 + bne loop +end + bx lr +} +#else +__WEAK +void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core,uint32_t cnt) +{ + __asm__ __volatile__( + "lsr r0,#0x10\n\t" + "mul r0,r1,r0\n\t" + "mov r2,r0\n\t" + "lsr r2,#0x04\n\t" + "lsr r2,#0x03\n\t" + "cmp r2,#0x01\n\t" + "beq end\n\t" + "cmp r2,#0x00\n\t" + "beq end\n" + "loop :" + "mov r0,r0\n\t" + "mov r0,r0\n\t" + "mov r0,r0\n\t" + "mov r0,r0\n\t" + "mov r0,r0\n\t" + "sub r2,r2,#0x01\n\t" + "cmp r2,#0x00\n\t" + "bne loop\n" + "end :" + "mov r0,r0\n\t" + ); +} +#endif +#endif +#ifdef ARCH_RISCV +__WEAK +void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core,uint32_t cnt) +{ + uint32_t codeAddress = 0; + uint32_t divVal = 40; + + codeAddress = (uint32_t)&ASM_Delay_Us; + + /* 1M=100K*10, so multiple is 10 */ + /* loop function take 4 instructions, so instructionNum is 4 */ + /* if codeAddress locate at IROM space and irom_2t_access is 1, then irom2TAccess=2, else irom2TAccess=1 */ + /* divVal = multiple*instructionNum*irom2TAccess */ + if(((codeAddress&(0xF<<24))>>24)==0x01){ + /* IROM space */ + if(BL_GET_REG_BITS_VAL(BL_RD_REG(L1C_BASE,L1C_CONFIG),L1C_IROM_2T_ACCESS)){ + /* instruction 2T */ + divVal = 80; + } + } + + __asm__ __volatile__( + ".align 4\n\t" + "lw a4,%1\n\t" + "lui a5,0x18\n\t" + "addi a5,a5,1696\n\t" + "divu a5,a4,a5\n\t" + "sw a5,%1\n\t" + "lw a4,%1\n\t" + "lw a5,%0\n\t" + "mul a5,a4,a5\n\t" + "sw a5,%1\n\t" + "lw a4,%1\n\t" + "lw a5,%2\n\t" + "divu a5,a4,a5\n\t" + "sw a5,%1\n\t" + "lw a5,%1\n\t" + "li a4,0x1\n\t" + "beq a5,zero,end\n\t" + "beq a5,a4,end\n\t" + "nop\n\t" + "nop\n\t" + ".align 4\n\t" + "loop :\n" + "addi a4,a5,-1\n\t" + "mv a5,a4\n\t" + "bnez a5,loop\n\t" + "nop\n\t" + "end :\n\t" + "nop\n" + : /* output */ + :"m"(cnt),"m"(core),"m"(divVal) /* input */ + :"t1","a4","a5" /* destruct description */ + ); +} +#endif + + +/****************************************************************************//** + * @brief delay us + * + * @param[in] cnt: delay cnt us + * + * @return none + * + *******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION BL602_Delay_US(uint32_t cnt) +{ + ASM_Delay_Us(SystemCoreClockGet(),cnt); +} + +/****************************************************************************//** + * @brief delay ms + * + * @param[in] cnt: delay cnt ms + * + * @return none + * + *******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION BL602_Delay_MS(uint32_t cnt) +{ + uint32_t i = 0; + uint32_t count = 0; + + if(cnt>=1024){ + /* delay (n*1024) ms */ + count = 1024; + for(i=0;i<(cnt/1024);i++){ + BL602_Delay_US(1024*1000); + } + } + if(cnt&0x3FF){ + /* delay (1-1023)ms */ + count = cnt & 0x3FF; + BL602_Delay_US(count*1000); + } + //BL602_Delay_US((count<<10)-(count<<4)-(count<<3)); +} +#endif +/*@} end of group DRIVER_Public_Functions */ + +/*@} end of group DRIVER_COMMON */ + +/*@} end of group BL602_Periph_Driver */ + + diff --git a/drivers/bl602_driver/std_drv/src/bl602_dac.c b/drivers/bl602_driver/std_drv/src/bl602_dac.c new file mode 100644 index 00000000..4f489dfd --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_dac.c @@ -0,0 +1,527 @@ +/** + ****************************************************************************** + * @file bl602_dac.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_dac.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/** @defgroup DAC_Private_Macros + * @{ + */ +#define GPIP_CLK_SET_DUMMY_WAIT {__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();} + +/*@} end of group DAC_Private_Macros */ + +/** @defgroup DAC_Private_Types + * @{ + */ + +/*@} end of group DAC_Private_Types */ + +/** @defgroup DAC_Private_Variables + * @{ + */ + +/*@} end of group DAC_Private_Variables */ + +/** @defgroup DAC_Global_Variables + * @{ + */ + +/*@} end of group DAC_Global_Variables */ + +/** @defgroup DAC_Private_Fun_Declaration + * @{ + */ + +/*@} end of group DAC_Private_Fun_Declaration */ + +/** @defgroup DAC_Private_Functions + * @{ + */ + +/*@} end of group DAC_Private_Functions */ + +/** @defgroup DAC_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief DAC initialization + * + * @param cfg: DAC configuration pointer + * + * @return None + * +*******************************************************************************/ +void GLB_DAC_Init(GLB_DAC_Cfg_Type *cfg) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_GLB_DAC_REF_SEL_TYPE(cfg->refSel)); + + /* Set DAC config */ + tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_CTRL); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_REF_SEL,cfg->refSel); + if(ENABLE==cfg->resetChanA){ + tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_GPDACA_RSTN_ANA); + tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_CTRL,tmpVal); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + } + if(ENABLE==cfg->resetChanB){ + tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_GPDACB_RSTN_ANA); + tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_CTRL,tmpVal); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + } + + /* Clear reset */ + tmpVal=BL_SET_REG_BIT(tmpVal,GLB_GPDACA_RSTN_ANA); + tmpVal=BL_SET_REG_BIT(tmpVal,GLB_GPDACB_RSTN_ANA); + tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_CTRL,tmpVal); +} + +/****************************************************************************//** + * @brief DAC channel A initialization + * + * @param cfg: DAC channel configuration pointer + * + * @return None + * +*******************************************************************************/ +void GLB_DAC_Set_ChanA_Config(GLB_DAC_Chan_Cfg_Type *cfg) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_GLB_DAC_CHAN_TYPE(cfg->outMux)); + + /* Set channel A config */ + tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_ACTRL); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_A_OUTMUX,cfg->outMux); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_IOA_EN,cfg->outputEn); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_A_EN,cfg->chanEn); + + tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_ACTRL,tmpVal); +} + +/****************************************************************************//** + * @brief DAC channel B initialization + * + * @param cfg: DAC channel configuration pointer + * + * @return None + * +*******************************************************************************/ +void GLB_DAC_Set_ChanB_Config(GLB_DAC_Chan_Cfg_Type *cfg) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_GLB_DAC_CHAN_TYPE(cfg->outMux)); + + /* Set channel A config */ + tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_BCTRL); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_B_OUTMUX,cfg->outMux); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_IOB_EN,cfg->outputEn); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_B_EN,cfg->chanEn); + + tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_BCTRL,tmpVal); +} + +/****************************************************************************//** + * @brief Select DAC channel B source + * + * @param src: DAC channel B source selection type + * + * @return None + * +*******************************************************************************/ +void GPIP_Set_DAC_ChanB_SRC_SEL(GPIP_DAC_ChanB_SRC_Type src) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GPIP_DAC_CHANB_SRC_TYPE(src)); + + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_CH_B_SEL,src); + BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal); +} + +/****************************************************************************//** + * @brief Select DAC channel A source + * + * @param src: DAC channel A source selection type + * + * @return None + * +*******************************************************************************/ +void GPIP_Set_DAC_ChanA_SRC_SEL(GPIP_DAC_ChanA_SRC_Type src) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GPIP_DAC_CHANA_SRC_TYPE(src)); + + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_CH_A_SEL,src); + BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal); +} + +/****************************************************************************//** + * @brief Select DAC mode + * + * @param mod: DAC mode selection type + * + * @return None + * +*******************************************************************************/ +void GPIP_Set_DAC_Mod_SEL(GPIP_DAC_MOD_Type mod) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GPIP_DAC_MOD_TYPE(mod)); + + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_MODE,mod); + BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal); +} + +/****************************************************************************//** + * @brief Enable DAC channel B + * + * @param None + * + * @return None + * +*******************************************************************************/ +void GPIP_DAC_ChanB_Enable(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG); + tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPDAC_EN2); + BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal); +} + +/****************************************************************************//** + * @brief Disable DAC channel B + * + * @param None + * + * @return None + * +*******************************************************************************/ +void GPIP_DAC_ChanB_Disable(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG); + tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPDAC_EN2); + BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal); +} + +/****************************************************************************//** + * @brief Enable DAC channel A + * + * @param None + * + * @return None + * +*******************************************************************************/ +void GPIP_DAC_ChanA_Enable(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG); + tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPDAC_EN); + BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal); +} + +/****************************************************************************//** + * @brief Disable DAC channel A + * + * @param None + * + * @return None + * +*******************************************************************************/ +void GPIP_DAC_ChanA_Disable(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG); + tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPDAC_EN); + BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal); +} + +/****************************************************************************//** + * @brief Select DAC DMA TX format + * + * @param fmt: DAC DMA TX format selection type + * + * @return None + * +*******************************************************************************/ +void GPIP_Set_DAC_DMA_TX_FORMAT_SEL(GPIP_DAC_DMA_TX_FORMAT_Type fmt) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(fmt)); + + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_DMA_CONFIG); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_DMA_FORMAT,fmt); + BL_WR_REG(GPIP_BASE,GPIP_GPDAC_DMA_CONFIG,tmpVal); +} + +/****************************************************************************//** + * @brief Enable DAC DMA TX + * + * @param None + * + * @return None + * +*******************************************************************************/ +void GPIP_Set_DAC_DMA_TX_Enable(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_DMA_CONFIG); + tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPDAC_DMA_TX_EN); + BL_WR_REG(GPIP_BASE,GPIP_GPDAC_DMA_CONFIG,tmpVal); +} + +/****************************************************************************//** + * @brief Disable DAC DMA TX + * + * @param None + * + * @return None + * +*******************************************************************************/ +void GPIP_Set_DAC_DMA_TX_Disable(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_DMA_CONFIG); + tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPDAC_DMA_TX_EN); + BL_WR_REG(GPIP_BASE,GPIP_GPDAC_DMA_CONFIG,tmpVal); +} + +/****************************************************************************//** + * @brief Disable DAC DMA TX + * + * @param data: The data to be send + * + * @return None + * +*******************************************************************************/ +void GPIP_DAC_DMA_WriteData(uint32_t data) +{ + BL_WR_REG(GPIP_BASE,GPIP_GPDAC_DMA_WDATA,data); +} + +/****************************************************************************//** + * @brief AON and GPIP DAC config + * + * @param cfg: AON and GPIP DAC configuration + * + * @return config success or not + * +*******************************************************************************/ +BL_Err_Type GLB_GPIP_DAC_Init(GLB_GPIP_DAC_Cfg_Type* cfg) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GLB_DAC_REF_SEL_TYPE(cfg->refSel)); + CHECK_PARAM(IS_GPIP_DAC_MOD_TYPE(cfg->mod)); + CHECK_PARAM(IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(cfg->dmaFmt)); + + /* AON Set DAC config */ + tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_CTRL); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_REF_SEL,cfg->refSel); + if(ENABLE==cfg->resetChanA){ + tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_GPDACA_RSTN_ANA); + tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_CTRL,tmpVal); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + } + if(ENABLE==cfg->resetChanB){ + tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_GPDACB_RSTN_ANA); + tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_CTRL,tmpVal); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + } + + /* AON Clear reset */ + tmpVal=BL_SET_REG_BIT(tmpVal,GLB_GPDACA_RSTN_ANA); + tmpVal=BL_SET_REG_BIT(tmpVal,GLB_GPDACB_RSTN_ANA); + tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_CTRL,tmpVal); + + if(cfg->dmaEn == DISABLE && cfg->mod == GPIP_DAC_MOD_512K){ + return ERROR;/*512K mode only used in DMA mode*/ + } + + /* GPIP Set DAC config */ + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_MODE,cfg->mod); + BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal); + + /* GPIP Set DMA config */ + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_DMA_CONFIG); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_DMA_TX_EN,cfg->dmaEn); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_DMA_FORMAT,cfg->dmaFmt); + BL_WR_REG(GPIP_BASE,GPIP_GPDAC_DMA_CONFIG,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief AON and GPIP DAC channel A config + * + * @param cfg: AON and GPIP DAC channel A configuration + * + * @return None + * +*******************************************************************************/ +void GLB_GPIP_DAC_Set_ChanA_Config(GLB_GPIP_DAC_ChanA_Cfg_Type *cfg) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GPIP_DAC_CHANA_SRC_TYPE(cfg->src)); + + /* GPIP select source */ + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_CH_A_SEL,cfg->src); + BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal); + + /* GPIP enable or disable channel */ + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_EN,cfg->chanEn); + BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal); + + /* AON enable or disable channel */ + tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_ACTRL); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_IOA_EN,cfg->outputEn); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_A_EN,cfg->chanCovtEn); + tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_ACTRL,tmpVal); +} + +/****************************************************************************//** + * @brief AON and GPIP DAC channel B config + * + * @param cfg: AON and GPIP DAC channel B configuration + * + * @return None + * +*******************************************************************************/ +void GLB_GPIP_DAC_Set_ChanB_Config(GLB_GPIP_DAC_ChanB_Cfg_Type *cfg) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GPIP_DAC_CHANB_SRC_TYPE(cfg->src)); + + /* GPIP select source */ + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_CH_B_SEL,cfg->src); + BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal); + + /* GPIP enable or disable channel */ + tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_EN2,cfg->chanEn); + BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal); + + /* AON enable or disable channel */ + tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_BCTRL); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_IOB_EN,cfg->outputEn); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_B_EN,cfg->chanCovtEn); + tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_BCTRL,tmpVal); +} + +/****************************************************************************//** + * @brief DAC channel A set value + * + * @param val: DAC value + * + * @return None + * +*******************************************************************************/ +void GLB_DAC_Set_ChanA_Value(uint16_t val) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_DATA); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_A_DATA,val); + tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_DATA,tmpVal); +} + +/****************************************************************************//** + * @brief DAC channel B set value + * + * @param val: DAC value + * + * @return None + * +*******************************************************************************/ +void GLB_DAC_Set_ChanB_Value(uint16_t val) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_DATA); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_B_DATA,val); + tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_DATA,tmpVal); +} + +/*@} end of group DAC_Public_Functions */ + +/*@} end of group DAC */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/bl602_driver/std_drv/src/bl602_dma.c b/drivers/bl602_driver/std_drv/src/bl602_dma.c new file mode 100644 index 00000000..c2be48db --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_dma.c @@ -0,0 +1,752 @@ +/** + ****************************************************************************** + * @file bl602_dma.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602.h" +#include "bl602_dma.h" +#include "string.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/** @defgroup DMA_Private_Macros + * @{ + */ +#define DMA_CHANNEL_OFFSET 0x100 +#define DMA_Get_Channel(ch) (DMA_BASE+DMA_CHANNEL_OFFSET+(ch)*0x100) +static intCallback_Type * dmaIntCbfArra[DMA_CH_MAX][DMA_INT_ALL]= { +{NULL, NULL}, +{NULL, NULL}, +{NULL, NULL}, +{NULL, NULL} +}; +static DMA_LLI_Ctrl_Type PingPongListArra[DMA_CH_MAX][2]; + +/*@} end of group DMA_Private_Macros */ + +/** @defgroup DMA_Private_Types + * @{ + */ + +/*@} end of group DMA_Private_Types */ + +/** @defgroup DMA_Private_Variables + * @{ + */ + +/*@} end of group DMA_Private_Variables */ + +/** @defgroup DMA_Global_Variables + * @{ + */ + +/*@} end of group DMA_Global_Variables */ + +/** @defgroup DMA_Private_Fun_Declaration + * @{ + */ + +/*@} end of group DMA_Private_Fun_Declaration */ + +/** @defgroup DMA_Private_Functions + * @{ + */ + +/****************************************************************************//** + * @brief DMA interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void DMA_ALL_IRQHandler(void) +{ + uint32_t tmpVal; + uint32_t intClr; + uint8_t ch; + /* Get DMA register */ + uint32_t DMAChs = DMA_BASE; + + for(ch=0;chch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(chCfg->ch)); + CHECK_PARAM(IS_DMA_TRANS_WIDTH_TYPE(chCfg->srcTransfWidth)); + CHECK_PARAM(IS_DMA_TRANS_WIDTH_TYPE(chCfg->dstTransfWidth)); + CHECK_PARAM(IS_DMA_BURST_SIZE_TYPE(chCfg->srcBurstSzie)); + CHECK_PARAM(IS_DMA_BURST_SIZE_TYPE(chCfg->dstBurstSzie)); + CHECK_PARAM(IS_DMA_TRANS_DIR_TYPE(chCfg->dir)); + CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(chCfg->dstPeriph)); + CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(chCfg->srcPeriph)); + + /* Config channel config */ + BL_WR_REG(DMAChs, DMA_SRCADDR, chCfg->srcDmaAddr); + BL_WR_REG(DMAChs, DMA_DSTADDR, chCfg->destDmaAddr); + + tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, chCfg->transfLength); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SWIDTH, chCfg->srcTransfWidth); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DWIDTH, chCfg->dstTransfWidth); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SBSIZE, chCfg->srcBurstSzie); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DBSIZE, chCfg->dstBurstSzie); + /* FIXME: how to deal with SLargerD */ + tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_SLARGERD); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SI, chCfg->srcAddrInc); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DI, chCfg->destAddrInc); + BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); + + tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FLOWCNTRL, chCfg->dir); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DSTPERIPHERAL, chCfg->dstPeriph); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SRCPERIPHERAL, chCfg->srcPeriph); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); +} + +/****************************************************************************//** + * @brief DMA channel update source memory address and len + * + * @param ch: DMA channel + * @param memAddr: source memoty address + * @param len: source memory data length + * + * @return None + * +*******************************************************************************/ +void DMA_Channel_Update_SrcMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + + /* config channel config*/ + BL_WR_REG(DMAChs, DMA_SRCADDR, memAddr); + tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, len); + BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); +} + +/****************************************************************************//** + * @brief DMA channel update destination memory address and len + * + * @param ch: DMA channel + * @param memAddr: destination memoty address + * @param len: destination memory data length + * + * @return None + * +*******************************************************************************/ +void DMA_Channel_Update_DstMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + + /* config channel config*/ + BL_WR_REG(DMAChs, DMA_DSTADDR, memAddr); + tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, len); + BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); +} + +/****************************************************************************//** + * @brief Get DMA channel tranfersize + * + * @param ch: DMA channel + * + * @return tranfersize size + * +*******************************************************************************/ +uint32_t DMA_Channel_TranferSize(uint8_t ch) +{ + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + + return BL_GET_REG_BITS_VAL(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_TRANSFERSIZE); +} + +/****************************************************************************//** + * @brief Get DMA channel busy status + * + * @param ch: DMA channel + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type DMA_Channel_Is_Busy(uint8_t ch) +{ + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + + return BL_IS_REG_BIT_SET(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_E) == 1 ? SET:RESET; +} + + +/****************************************************************************//** + * @brief DMA enable + * + * @param ch: DMA channel number + * + * @return None + * +*******************************************************************************/ +void DMA_Channel_Enable(uint8_t ch) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + + tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, DMA_E); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); +} + +/****************************************************************************//** + * @brief DMA disable + * + * @param ch: DMA channel number + * + * @return None + * +*******************************************************************************/ +void DMA_Channel_Disable(uint8_t ch) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + + tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_E); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); +} + +/****************************************************************************//** + * @brief DMA init LLI transfer + * + * @param ch: DMA channel number + * @param lliCfg: LLI configuration + * + * @return None + * +*******************************************************************************/ +void DMA_LLI_Init(uint8_t ch,DMA_LLI_Cfg_Type *lliCfg) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + CHECK_PARAM(IS_DMA_TRANS_DIR_TYPE(lliCfg->dir)); + CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(lliCfg->dstPeriph)); + CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(lliCfg->srcPeriph)); + + tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FLOWCNTRL, lliCfg->dir); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DSTPERIPHERAL, lliCfg->dstPeriph); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SRCPERIPHERAL, lliCfg->srcPeriph); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); +} + +/****************************************************************************//** + * @brief DMA channel update LLI + * + * @param ch: DMA channel number + * @param LLI: LLI addr + * + * @return None + * +*******************************************************************************/ +void DMA_LLI_Update(uint8_t ch, uint32_t LLI) +{ + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + + /* Config channel config */ + //BL_WR_REG(DMAChs, DMA_LLI, LLI); + BL602_MemCpy4((uint32_t*)DMAChs,(uint32_t*)LLI,4); +} + +/****************************************************************************//** + * @brief DMA LLI PingPong Structure Initial + * + * @param dmaPpStruct: DMA LLI PingPong Config Parameter + * + * @return start success or not + * +*******************************************************************************/ +BL_Err_Type DMA_LLI_PpStruct_Init(DMA_LLI_PP_Struct *dmaPpStruct) +{ + //setup lliList + dmaPpStruct->dmaCtrlRegVal.I=1; + dmaPpStruct->trans_index = 0; + + if(dmaPpStruct->DMA_LLI_Cfg->dir == DMA_TRNS_M2P){ + PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].srcDmaAddr = dmaPpStruct->chache_buf_addr[0]; + PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].destDmaAddr= dmaPpStruct->operatePeriphAddr; + + PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].srcDmaAddr = dmaPpStruct->chache_buf_addr[1]; + PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].destDmaAddr= dmaPpStruct->operatePeriphAddr; + } + else if(dmaPpStruct->DMA_LLI_Cfg->dir == DMA_TRNS_P2M){ + PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].srcDmaAddr = dmaPpStruct->operatePeriphAddr; + PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].destDmaAddr= dmaPpStruct->chache_buf_addr[0]; + + PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].srcDmaAddr = dmaPpStruct->operatePeriphAddr; + PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].destDmaAddr = dmaPpStruct->chache_buf_addr[1]; + }else{ + return ERROR; + /*V1.0 version DMA LLI Ping-Pong structure not support P2P & M2M MODE*/ + } + + PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].nextLLI = (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX]; + PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl = dmaPpStruct->dmaCtrlRegVal; + + if(dmaPpStruct->is_single_mode == 1){ + /* + * if is is_single_mode is 1 ping-pong will only run once atfer start singal + * or ping-pong will run forever unless stop singal occour + */ + PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].nextLLI = 0; + }else{ + PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].nextLLI = (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX]; + } + + PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl = dmaPpStruct->dmaCtrlRegVal; + + DMA_LLI_Init(dmaPpStruct->dmaChan, dmaPpStruct->DMA_LLI_Cfg); + + DMA_LLI_Update(dmaPpStruct->dmaChan, (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX]); + + return SUCCESS; +} + + +/****************************************************************************//** + * @brief DMA LLI PingPong Structure Start + * + * @param dmaPpStruct: None + * + * @return None + * +*******************************************************************************/ +void DMA_LLI_PpStruct_Start(DMA_LLI_PP_Struct *dmaPpStruct){ + if(dmaPpStruct->is_single_mode == 1){ + DMA_LLI_Update(dmaPpStruct->dmaChan, (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX]); + } + + DMA_Channel_Enable(dmaPpStruct->dmaChan); +} + + + +/****************************************************************************//** + * @brief DMA LLI PingPong Structure Stop + * + * @param dmaPpStruct: None + * + * @return None + * +*******************************************************************************/ +void DMA_LLI_PpStruct_Stop(DMA_LLI_PP_Struct *dmaPpStruct){ + DMA_Channel_Disable(dmaPpStruct->dmaChan); +} + +/****************************************************************************//** + * @brief DMA LLI PingPong Structure Start + * + * @param dmaPpStruct: dma pp struct pointer + * @param Ping_Transfer_len: ping len + * @param Pong_Transfer_len: pong len + * + * @return Succrss or not + * +*******************************************************************************/ +BL_Err_Type DMA_LLI_PpStruct_Set_Transfer_Len(DMA_LLI_PP_Struct *dmaPpStruct,uint16_t Ping_Transfer_len,uint16_t Pong_Transfer_len){ + struct DMA_Control_Reg dmaCtrlRegVal_temp; + + if(Ping_Transfer_len > 4096 || Pong_Transfer_len >4096){ + return ERROR; + } + + dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl ; + dmaCtrlRegVal_temp.TransferSize = Ping_Transfer_len; + PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl = dmaCtrlRegVal_temp; + + dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl ; + dmaCtrlRegVal_temp.TransferSize = Pong_Transfer_len; + PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl = dmaCtrlRegVal_temp; + + DMA_LLI_Init(dmaPpStruct->dmaChan, dmaPpStruct->DMA_LLI_Cfg); + DMA_LLI_Update(dmaPpStruct->dmaChan, (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX]); + + return SUCCESS; + +} + + + + +/****************************************************************************//** + * @brief DMA LLI Start New Transmit for Ping-Pong Buf + * + * @param dmaPpBuf: DMA LLI Ping-Pong Buf + * + * @return None + * +*******************************************************************************/ +void DMA_LLI_PpBuf_Start_New_Transmit(DMA_LLI_PP_Buf *dmaPpBuf) +{ + NVIC_DisableIRQ(DMA_ALL_IRQn); + if(dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex] != NULL){ + DMA_LLI_Update(dmaPpBuf->dmaChan, (uint32_t)dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex]); + DMA_Channel_Enable(dmaPpBuf->dmaChan); + dmaPpBuf->idleIndex = (dmaPpBuf->idleIndex==0)?1:0; + } + NVIC_EnableIRQ(DMA_ALL_IRQn); +} + +/****************************************************************************//** + * @brief DMA LLI Remove Completed Ping-Pong Buf List + * + * @param dmaPpBuf: DMA LLI Ping-Pong Buf + * + * @return Next Ping-Pong Buf List Header + * +*******************************************************************************/ +DMA_LLI_Ctrl_Type * DMA_LLI_PpBuf_Remove_Completed_List(DMA_LLI_PP_Buf *dmaPpBuf) +{ + NVIC_DisableIRQ(DMA_ALL_IRQn); + + dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex] = NULL; + NVIC_EnableIRQ(DMA_ALL_IRQn); + return dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex]; +} + +/****************************************************************************//** + * @brief DMA LLI Append Buf to List + * + * @param dmaPpBuf: DMA LLI Ping-Pong Buf + * @param dmaLliList: New LLI Buf to Append + * + * @return None + * +*******************************************************************************/ +void DMA_LLI_PpBuf_Append(DMA_LLI_PP_Buf *dmaPpBuf, DMA_LLI_Ctrl_Type *dmaLliList) +{ + DMA_LLI_Ctrl_Type *pLliList = NULL; + NVIC_DisableIRQ(DMA_ALL_IRQn); + + pLliList = dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex]; + if(pLliList == NULL){ + dmaLliList->nextLLI = 0; + dmaLliList->dmaCtrl.I = 1; + dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex] = dmaLliList; + }else{ + /*Append to last */ + while(pLliList->nextLLI != 0){ + pLliList = (DMA_LLI_Ctrl_Type*)pLliList->nextLLI; + } + pLliList->nextLLI = (uint32_t)dmaLliList; + pLliList->dmaCtrl.I = 0; + dmaLliList->nextLLI = 0; + dmaLliList->dmaCtrl.I = 1; + } + + if(DMA_Channel_Is_Busy(dmaPpBuf->dmaChan) == RESET){ + /* DMA stopped: maybe stop just a few minutes ago(not enter INT due to NVIC_DisableIRQ) + or has already stopped before this function is called */ + if(dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex] == NULL){ + /* DMA has already stopped before this function is called */ + DMA_LLI_PpBuf_Start_New_Transmit(dmaPpBuf); + } + } + NVIC_EnableIRQ(DMA_ALL_IRQn); +} + +/****************************************************************************//** + * @brief DMA LLi Destroy Ping-Pong Buf + * + * @param dmaPpBuf: DMA LLI Ping-Pong Buf + * + * @return None + * +*******************************************************************************/ +void DMA_LLI_PpBuf_Destroy(DMA_LLI_PP_Buf *dmaPpBuf) +{ + /* DMA LLI Disable */ + DMA_Channel_Disable(dmaPpBuf->dmaChan); + if(dmaPpBuf->lliListHeader[0] != NULL && dmaPpBuf->onTransCompleted != NULL){ + dmaPpBuf->onTransCompleted(dmaPpBuf->lliListHeader[0]); + } + dmaPpBuf->lliListHeader[0] = NULL; + if(dmaPpBuf->lliListHeader[1] != NULL && dmaPpBuf->onTransCompleted != NULL){ + dmaPpBuf->onTransCompleted(dmaPpBuf->lliListHeader[1]); + } + dmaPpBuf->lliListHeader[1] = NULL; + dmaPpBuf->idleIndex = 0; +} + + +/****************************************************************************//** + * @brief Mask/Unmask the DMA interrupt + * + * @param ch: DMA channel number + * @param intType: Specifies the interrupt type + * @param intMask: Enable/Disable Specified interrupt type + * + * @return None + * +*******************************************************************************/ +void DMA_IntMask(uint8_t ch,DMA_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t DMAChs = DMA_Get_Channel(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); + CHECK_PARAM(IS_DMA_INT_TYPE(intType)); + + switch(intType) + { + case DMA_INT_TCOMPLETED: + if(intMask == UNMASK) + { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_ITC); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); + tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_I); + BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); + } + else + { + /* MASK(Disable) this interrupt */ + tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_ITC); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); + tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_I); + BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); + } + break; + case DMA_INT_ERR: + if(intMask == UNMASK) + { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_IE); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); + } + else + { + /* MASK(Disable) this interrupt */ + tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_IE); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); + } + break; + case DMA_INT_ALL: + if(intMask == UNMASK) + { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_ITC); + tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_IE); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); + tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); + tmpVal = BL_SET_REG_BIT(tmpVal, DMA_I); + BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); + } + else + { + /* MASK(Disable) this interrupt */ + tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, DMA_ITC); + tmpVal = BL_SET_REG_BIT(tmpVal, DMA_IE); + BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); + tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); + tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_I); + BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); + } + break; + + default: + break; + } +} + +/****************************************************************************//** + * @brief Install DMA interrupt callback function + * + * @param dmaChan: DMA Channel type + * @param intType: DMA interrupt type + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return None + * +*******************************************************************************/ +void DMA_Int_Callback_Install(DMA_Chan_Type dmaChan,DMA_INT_Type intType,intCallback_Type* cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_DMA_CHAN_TYPE(dmaChan)); + CHECK_PARAM(IS_DMA_INT_TYPE(intType)); + + dmaIntCbfArra[dmaChan][intType] = cbFun; +} + +/*@} end of group DMA_Public_Functions */ + +/*@} end of group DMA */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/bl602_driver/std_drv/src/bl602_ef_ctrl.c b/drivers/bl602_driver/std_drv/src/bl602_ef_ctrl.c new file mode 100644 index 00000000..df74ff87 --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_ef_ctrl.c @@ -0,0 +1,1760 @@ +/** + ****************************************************************************** + * @file bl602_sec_ef_ctrl.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "string.h" +#include "bl602_ef_ctrl.h" +#include "ef_data_0_reg.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SEC_EF_CTRL + * @{ + */ + +/** @defgroup SEC_EF_CTRL_Private_Macros + * @{ + */ +#define EF_CTRL_EFUSE_CYCLE_PROTECT (0xbf<<24) +#define EF_CTRL_EFUSE_CTRL_PROTECT (0xbf<<8) +#define EF_CTRL_DFT_TIMEOUT_VAL (160*1000) +#ifndef BOOTROM +#define EF_CTRL_LOAD_BEFORE_READ_R0 EF_Ctrl_Load_Efuse_R0() +#else +#define EF_CTRL_LOAD_BEFORE_READ_R0 +#endif +#define EF_CTRL_DATA0_CLEAR EF_Ctrl_Clear(0,EF_CTRL_EFUSE_R0_SIZE/4) + +/*@} end of group SEC_EF_CTRL_Private_Macros */ + +/** @defgroup SEC_EF_CTRL_Private_Types + * @{ + */ + +/*@} end of group SEC_EF_CTRL_Private_Types */ + +/** @defgroup SEC_EF_CTRL_Private_Variables + * @{ + */ + +/*@} end of group SEC_EF_CTRL_Private_Variables */ + +/** @defgroup SEC_EF_CTRL_Global_Variables + * @{ + */ + +/*@} end of group SEC_EF_CTRL_Global_Variables */ + +/** @defgroup SEC_EF_CTRL_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SEC_EF_CTRL_Private_Fun_Declaration */ + +/** @defgroup SEC_EF_CTRL_Private_Functions + * @{ + */ + +/****************************************************************************//** + * @brief Switch efuse region 0 control to AHB clock + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION EF_Ctrl_Sw_AHB_Clk_0(void) +{ + uint32_t tmpVal; + uint32_t timeout=EF_CTRL_DFT_TIMEOUT_VAL; + + while(EF_Ctrl_Busy()==SET){ + timeout--; + if(timeout==0){ + break; + } + } + + tmpVal=(EF_CTRL_EFUSE_CTRL_PROTECT)| \ + (EF_CTRL_OP_MODE_AUTO<ef_dbg_mode); + tmpVal= BL_SET_REG_BITS_VAL(tmpVal,EF_DATA_0_EF_DBG_JTAG_0_DIS,cfg->ef_dbg_jtag_0_dis); + tmpVal= BL_SET_REG_BITS_VAL(tmpVal,EF_DATA_0_EF_SBOOT_EN,cfg->ef_sboot_en); + BL_WR_REG(EF_DATA_BASE,EF_DATA_0_EF_CFG_0,tmpVal); + + if(program){ + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************//** + * @brief Efuse read security configuration + * + * @param cfg: security configuration pointer + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg) +{ + uint32_t tmpVal; + + /* Trigger read data from efuse */ + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_CFG_0); + + cfg->ef_dbg_mode =(EF_Ctrl_Dbg_Mode_Type)BL_GET_REG_BITS_VAL(tmpVal,EF_DATA_0_EF_DBG_MODE); + cfg->ef_dbg_jtag_0_dis=BL_GET_REG_BITS_VAL(tmpVal,EF_DATA_0_EF_DBG_JTAG_0_DIS); + cfg->ef_sboot_en =BL_GET_REG_BITS_VAL(tmpVal,EF_DATA_0_EF_SBOOT_EN); + cfg->ef_no_hd_boot_en=BL_GET_REG_BITS_VAL(tmpVal,EF_DATA_0_EF_NO_HD_BOOT_EN); +} + +/****************************************************************************//** + * @brief Efuse write security boot configuration + * + * @param sign[1]: Sign configuration pointer + * @param aes[1]: AES configuration pointer + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1],uint8_t program) +{ + uint32_t tmpVal; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + tmpVal=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_CFG_0); + + tmpVal= BL_SET_REG_BITS_VAL(tmpVal,EF_DATA_0_EF_SBOOT_SIGN_MODE,sign[0]); + + if(aes[0]!=EF_CTRL_SF_AES_NONE){ + tmpVal= BL_SET_REG_BITS_VAL(tmpVal,EF_DATA_0_EF_SF_AES_MODE,aes[0]); + tmpVal= BL_SET_REG_BITS_VAL(tmpVal,EF_DATA_0_EF_CPU0_ENC_EN,1); + } + + BL_WR_REG(EF_DATA_BASE,EF_DATA_0_EF_CFG_0,tmpVal); + + if( program){ + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************//** + * @brief Efuse write security boot configuration + * + * @param sign[1]: Sign configuration pointer + * @param aes[1]: AES configuration pointer + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1]) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + /* Trigger read data from efuse */ + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_CFG_0); + + tmpVal2=BL_GET_REG_BITS_VAL(tmpVal,EF_DATA_0_EF_SBOOT_SIGN_MODE); + sign[0]=(EF_Ctrl_Sign_Type)(tmpVal2&0x01); + + tmpVal2=BL_GET_REG_BITS_VAL(tmpVal,EF_DATA_0_EF_CPU0_ENC_EN); + if(tmpVal2){ + aes[0]=(EF_Ctrl_SF_AES_Type)BL_GET_REG_BITS_VAL(tmpVal,EF_DATA_0_EF_SF_AES_MODE); + }else{ + aes[0]=EF_CTRL_SF_AES_NONE; + } +} + +/****************************************************************************//** + * @brief Get whether do RC32K and RC32M trim + * + * @param None + * + * @return 1 for enable trim RC32M and RC32K, 0 for not + * +*******************************************************************************/ +uint8_t EF_Ctrl_Get_Trim_Enable(void) +{ + uint32_t tmpVal; + + /* Trigger read data from efuse */ + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_CFG_0); + + return BL_GET_REG_BITS_VAL(tmpVal,EF_DATA_0_EF_TRIM_EN); +} + +/****************************************************************************//** + * @brief Analog Trim parity calculate + * + * @param val: Value of efuse trim data + * @param len: Length of bit to calculate + * + * @return Parity bit value + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint8_t ATTR_CLOCK_SECTION EF_Ctrl_Get_Trim_Parity(uint32_t val,uint8_t len) +{ + uint8_t cnt=0; + uint8_t i=0; + + for(i=0;itrimRc32mCodeFrExt=(tmpVal>>10)&0xff; + trim->trimRc32mCodeFrExtParity=(tmpVal>>18)&0x01; + trim->trimRc32mExtCodeEn=(tmpVal>>19)&0x01; +} +#endif + +/****************************************************************************//** + * @brief Efuse read RC32K trim + * + * @param trim: Trim data pointer + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32K_Trim( Efuse_Ana_RC32K_Trim_Type *trim) +{ + uint32_t tmpVal=0; + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_ANA_TRIM_0); + trim->trimRc32kCodeFrExt=(tmpVal>>20)&0x3ff; + trim->trimRc32kCodeFrExtParity=(tmpVal>>30)&0x01; + trim->trimRc32kExtCodeEn=(tmpVal>>31)&0x01; +} +#endif + +/****************************************************************************//** + * @brief Efuse read TSEN trim + * + * @param trim: Trim data pointer + * + * @return None + * +*******************************************************************************/ +void ATTR_CLOCK_SECTION EF_Ctrl_Read_TSEN_Trim( Efuse_TSEN_Refcode_Corner_Type *trim) +{ + uint32_t tmpVal=0; + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_KEY_SLOT_5_W3); + trim->tsenRefcodeCornerEn=tmpVal&0x01; + + tmpVal=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_LOCK); + trim->tsenRefcodeCorner=tmpVal&0xfff; + trim->tsenRefcodeCornerParity=(tmpVal >> 12)&0x01; + + tmpVal=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_KEY_SLOT_5_W1); + trim->tsenRefcodeCornerVersion=(tmpVal >> 30)&0x01; + +} + + +/****************************************************************************//** + * @brief Efuse read ADC Gain trim + * + * @param trim: Trim data pointer + * + * @return None + * +*******************************************************************************/ +void ATTR_CLOCK_SECTION EF_Ctrl_Read_ADC_Gain_Trim( Efuse_ADC_Gain_Coeff_Type *trim) +{ + uint32_t tmpVal=0; + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_KEY_SLOT_5_W3); + trim -> adcGainCoeff = (tmpVal >> 1) & 0xfff; + trim -> adcGainCoeffParity = (tmpVal >> 13) & 0x01; + trim -> adcGainCoeffEn = (tmpVal >> 14) & 0x01; +} + + + +/****************************************************************************//** + * @brief Efuse write software usage + * + * @param index: index of software usage + * @param usage: usage value + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage,uint8_t program) +{ + /* switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + if(index==0){ + BL_WR_REG(EF_DATA_BASE,EF_DATA_0_EF_SW_USAGE_0,usage); + } + + if(program){ + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************//** + * @brief Efuse read software usage + * + * @param index: index of software usage + * @param usage: usage value + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_Sw_Usage( uint32_t index, uint32_t *usage) +{ + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + EF_CTRL_LOAD_BEFORE_READ_R0; + + if(index==0){ + *usage=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_SW_USAGE_0); + } +} + +/****************************************************************************//** + * @brief Efuse read software usage + * + * @param index: index of software usage + * @param program: usage value + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program) +{ + uint32_t tmpVal; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + tmpVal=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_LOCK); + + if(index==0){ + tmpVal= BL_SET_REG_BIT(tmpVal,EF_DATA_0_WR_LOCK_SW_USAGE_0); + } + BL_WR_REG(EF_DATA_BASE,EF_DATA_0_LOCK,tmpVal); + + if(program){ + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************//** + * @brief Efuse write MAC address + * + * @param mac[6]: MAC address buffer + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Write_MAC_Address(uint8_t mac[6],uint8_t program) +{ + uint8_t *maclow=(uint8_t *)mac; + uint8_t *machigh=(uint8_t *)(mac+4); + uint32_t tmpVal; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + /* The low 32 bits */ + BL_WR_REG(EF_DATA_BASE,EF_DATA_0_EF_WIFI_MAC_LOW,BL_RDWD_FRM_BYTEP(maclow)); + /* The high 16 bits */ + tmpVal=machigh[0]+(machigh[1]<<8); + BL_WR_REG(EF_DATA_BASE,EF_DATA_0_EF_WIFI_MAC_HIGH,tmpVal); + + if( program){ + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************//** + * @brief Efuse Ctrl get zero bit count + * + * @param val: Value to count + * + * @return Zero bit count + * +*******************************************************************************/ +static uint32_t EF_Ctrl_Get_Byte_Zero_Cnt(uint8_t val) +{ + uint32_t cnt=0; + uint32_t i=0; + for(i=0;i<8;i++){ + if((val&(1<>8)&0xff; + + /* Check parity */ + for(i=0;i<6;i++){ + cnt+=EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]); + } + if((cnt&0x3f)==((tmpVal>>16)&0x3f)){ + /* Change to network order */ + for(i=0;i<3;i++){ + tmpVal=mac[i]; + mac[i]=mac[5-i]; + mac[5-i]=tmpVal; + } + return SUCCESS; + }else{ + return ERROR; + } +} + +/****************************************************************************//** + * @brief Efuse read MAC address + * + * @param mac[7]: MAC address buffer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]) +{ + uint8_t *maclow=(uint8_t *)mac; + uint8_t *machigh=(uint8_t *)(mac+4); + uint32_t tmpVal; + + /* Trigger read data from efuse */ + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_WIFI_MAC_LOW); + BL_WRWD_TO_BYTEP(maclow,tmpVal); + + tmpVal=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_WIFI_MAC_HIGH); + machigh[0]=tmpVal&0xff; + machigh[1]=(tmpVal>>8)&0xff; + machigh[2]=(tmpVal>>16)&0xff; + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Efuse lock writing for MAC address + * + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Writelock_MAC_Address(uint8_t program) +{ + uint32_t tmpVal; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + tmpVal=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_LOCK); + tmpVal= BL_SET_REG_BIT(tmpVal,EF_DATA_0_WR_LOCK_WIFI_MAC); + BL_WR_REG(EF_DATA_BASE,EF_DATA_0_LOCK,tmpVal); + + if( program){ + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************//** + * @brief Whether a value bits is all zero + * + * @param val: value to check + * @param start: start bit + * @param len: total length of bits to check + * + * @return 1 for all bits zero 0 for others + * +*******************************************************************************/ +uint8_t EF_Ctrl_Is_All_Bits_Zero(uint32_t val,uint8_t start,uint8_t len) +{ + uint32_t mask=0; + + val=(val>>start); + if(len>=32){ + mask=0xffffffff; + }else{ + mask=(1<=3){ + return ERROR; + } + + /* Change to local order */ + for(i=0;i<3;i++){ + tmpVal=mac[i]; + mac[i]=mac[5-i]; + mac[5-i]=tmpVal; + } + if(slot==2){ + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + }else{ + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + } + + /* The low 32 bits */ + if(slot==0){ + BL_WR_REG(EF_DATA_BASE,EF_DATA_0_EF_WIFI_MAC_LOW,BL_RDWD_FRM_BYTEP(maclow)); + }else if(slot==1){ + BL_WR_REG(EF_DATA_BASE,EF_DATA_0_EF_KEY_SLOT_5_W0,BL_RDWD_FRM_BYTEP(maclow)); + }else if(slot==2){ + BL_WR_REG(EF_DATA_BASE,EF_DATA_0_EF_DBG_PWD_LOW,BL_RDWD_FRM_BYTEP(maclow)); + } + /* The high 16 bits */ + tmpVal=machigh[0]+(machigh[1]<<8); + cnt=0; + for(i=0;i<6;i++){ + cnt+=EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]); + } + tmpVal|=((cnt&0x3f)<<16); + + if(slot==0){ + BL_WR_REG(EF_DATA_BASE,EF_DATA_0_EF_WIFI_MAC_HIGH,tmpVal); + }else if(slot==1){ + BL_WR_REG(EF_DATA_BASE,EF_DATA_0_EF_KEY_SLOT_5_W1,tmpVal); + }else if(slot==2){ + BL_WR_REG(EF_DATA_BASE,EF_DATA_0_EF_DBG_PWD_HIGH,tmpVal); + } + + if( program){ + if(slot==2){ + EF_Ctrl_Program_Efuse_0(); + }else{ + EF_Ctrl_Program_Efuse_0(); + } + } + return SUCCESS; +} + +/****************************************************************************//** + * @brief Efuse read optional MAC address + * + * @param slot: MAC address slot + * @param mac[6]: MAC address buffer + * @param reload: Whether reload + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot,uint8_t mac[6],uint8_t reload) +{ + uint8_t *maclow=(uint8_t *)mac; + uint8_t *machigh=(uint8_t *)(mac+4); + uint32_t tmpVal=0; + uint32_t i=0; + uint32_t cnt=0; + + if(slot>=3){ + return ERROR; + } + + /* Trigger read data from efuse */ + if(reload){ + if(slot==2){ + EF_CTRL_LOAD_BEFORE_READ_R0; + }else{ + EF_CTRL_LOAD_BEFORE_READ_R0; + } + } + + if(slot==0){ + tmpVal=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_WIFI_MAC_LOW); + }else if(slot==1){ + tmpVal=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_KEY_SLOT_5_W0); + }else if(slot==2){ + tmpVal=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_DBG_PWD_LOW); + } + BL_WRWD_TO_BYTEP(maclow,tmpVal); + + if(slot==0){ + tmpVal=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_WIFI_MAC_HIGH); + }else if(slot==1){ + tmpVal=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_KEY_SLOT_5_W1); + }else if(slot==2){ + tmpVal=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_DBG_PWD_HIGH); + } + machigh[0]=tmpVal&0xff; + machigh[1]=(tmpVal>>8)&0xff; + + /* Check parity */ + for(i=0;i<6;i++){ + cnt+=EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]); + } + if((cnt&0x3f)==((tmpVal>>16)&0x3f)){ + /* Change to network order */ + for(i=0;i<3;i++){ + tmpVal=mac[i]; + mac[i]=mac[5-i]; + mac[5-i]=tmpVal; + } + return SUCCESS; + }else{ + return ERROR; + } +} + +/****************************************************************************//** + * @brief Efuse read chip ID + * + * @param chipID[8]: Chip ID buffer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t chipID[8]) +{ + chipID[6]=0; + chipID[7]=0; + return EF_Ctrl_Read_MAC_Address(chipID); +} + +/****************************************************************************//** + * @brief Efuse read device info + * + * @param deviceInfo: Device info pointer + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo) +{ + uint32_t tmpVal; + uint32_t *p=(uint32_t *)deviceInfo; + + /* Trigger read data from efuse */ + EF_CTRL_LOAD_BEFORE_READ_R0; + + tmpVal=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_WIFI_MAC_HIGH); + *p=tmpVal; +} + +/****************************************************************************//** + * @brief Whether Capcode slot is empty + * + * @param slot: Cap code slot + * @param reload: Whether reload + * + * @return 0 for all slots full,1 for others + * +*******************************************************************************/ +uint8_t EF_Ctrl_Is_CapCode_Slot_Empty(uint8_t slot,uint8_t reload) +{ + uint32_t tmp=0xffffffff; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + if(reload){ + EF_CTRL_LOAD_BEFORE_READ_R0; + } + + if(slot==0){ + tmp=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_ANA_TRIM_0); + return(EF_Ctrl_Is_All_Bits_Zero(tmp,2,8)); + }else if(slot==1){ + tmp=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_KEY_SLOT_5_W1); + return(EF_Ctrl_Is_All_Bits_Zero(tmp,22,8)); + }else if(slot==2){ + tmp=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_DBG_PWD_HIGH); + return(EF_Ctrl_Is_All_Bits_Zero(tmp,22,8)); + } + + return 0; +} + +/****************************************************************************//** + * @brief Efuse write Cap code + * + * @param slot: Cap code slot + * @param code: Cap code value + * @param program: Whether program + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Write_CapCode_Opt(uint8_t slot,uint8_t code,uint8_t program) +{ + uint32_t tmp; + uint8_t trim; + + if(slot>=3){ + return ERROR; + } + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + EF_CTRL_LOAD_BEFORE_READ_R0; + + if(slot==0){ + tmp=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_ANA_TRIM_0); + }else if(slot==1){ + tmp=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_KEY_SLOT_5_W1); + }else if(slot==2){ + tmp=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_DBG_PWD_HIGH); + } + + trim=code; + trim|=((EF_Ctrl_Get_Trim_Parity(code,6))<<6); + trim|=(1<<7); + + if(slot==0){ + BL_WR_REG(EF_DATA_BASE,EF_DATA_0_EF_ANA_TRIM_0,tmp|(trim<<2)); + }else if(slot==1){ + BL_WR_REG(EF_DATA_BASE,EF_DATA_0_EF_KEY_SLOT_5_W1,tmp|(trim<<22)); + }else if(slot==2){ + BL_WR_REG(EF_DATA_BASE,EF_DATA_0_EF_DBG_PWD_HIGH,tmp|(trim<<22)); + } + + if(program){ + EF_Ctrl_Program_Efuse_0(); + } + while(SET==EF_Ctrl_Busy()); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Efuse read Cap code + * + * @param slot: Cap code slot + * @param code: Cap code pointer + * @param reload: Whether reload + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Read_CapCode_Opt(uint8_t slot,uint8_t *code,uint8_t reload) +{ + uint32_t tmp; + Efuse_Capcode_Info_Type *trim=(Efuse_Capcode_Info_Type *)&tmp; + + if(slot>=3){ + return ERROR; + } + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + if(reload){ + EF_CTRL_LOAD_BEFORE_READ_R0; + } + + if(slot==0){ + tmp=(BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_ANA_TRIM_0))>>2; + }else if(slot==1){ + tmp=(BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_KEY_SLOT_5_W1))>>22; + }else if(slot==2){ + tmp=(BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_DBG_PWD_HIGH))>>22; + } + + if(trim->en){ + if(trim->parity==EF_Ctrl_Get_Trim_Parity(trim->capCode,6)){ + *code=trim->capCode; + return SUCCESS; + } + } + return ERROR; +} + +/****************************************************************************//** + * @brief Whether power offset slot is empty + * + * @param slot: Power offset code slot + * @param reload: Whether reload + * + * @return 0 for all slots full,1 for others + * +*******************************************************************************/ +uint8_t EF_Ctrl_Is_PowerOffset_Slot_Empty(uint8_t slot,uint8_t reload) +{ + uint32_t tmp1=0xffffffff; + uint32_t part1Empty=0,part2Empty=0; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + if(reload){ + EF_CTRL_LOAD_BEFORE_READ_R0; + } + + if(slot==0){ + tmp1=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_KEY_SLOT_5_W3); + part1Empty=(EF_Ctrl_Is_All_Bits_Zero(tmp1,15,17)); + part2Empty=1; + }else if(slot==1){ + tmp1=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_KEY_SLOT_5_W2); + part1Empty=(EF_Ctrl_Is_All_Bits_Zero(tmp1,0,16)); + + tmp1=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_ANA_TRIM_0); + part2Empty=(EF_Ctrl_Is_All_Bits_Zero(tmp1,0,1)); + }else if(slot==2){ + tmp1=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_KEY_SLOT_5_W2); + part1Empty=(EF_Ctrl_Is_All_Bits_Zero(tmp1,16,16)); + + tmp1=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_ANA_TRIM_0); + part2Empty=(EF_Ctrl_Is_All_Bits_Zero(tmp1,1,1)); + } + + return (part1Empty&&part2Empty); +} + +/****************************************************************************//** + * @brief Efuse write power offset + * + * @param slot: Power offset slot + * @param pwrOffset[3]: Power offset value array + * @param program: Whether program + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Write_PowerOffset_Opt(uint8_t slot,int8_t pwrOffset[3],uint8_t program) +{ + uint64_t tmp=0; + uint32_t k=0; + uint64_t Value=0; + uint8_t parity; + + if(slot>=3){ + return ERROR; + } + + for(k=0;k<3;k++){ + /* Use 5 bits as signed value */ + if(pwrOffset[k]>15){ + pwrOffset[k]=15; + } + if(pwrOffset[k]<-16){ + pwrOffset[k]=-16; + } + tmp=((uint64_t)((pwrOffset[k])&0x1f))<<(k*5); + Value+=tmp; + } + parity=EF_Ctrl_Get_Trim_Parity(Value,15); + + if(slot==0){ + tmp=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_KEY_SLOT_5_W3); + tmp|=(Value<<16); + tmp|=(1<<15); + tmp|=(uint32_t)(parity<<31); + BL_WR_REG(EF_DATA_BASE,EF_DATA_0_EF_KEY_SLOT_5_W3,tmp); + }else if(slot==1){ + tmp=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_KEY_SLOT_5_W2); + tmp|=(Value<<0); + tmp|=(uint32_t)(parity<<15); + BL_WR_REG(EF_DATA_BASE,EF_DATA_0_EF_KEY_SLOT_5_W2,tmp); + + tmp=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_ANA_TRIM_0); + tmp|=(1<<0); + BL_WR_REG(EF_DATA_BASE,EF_DATA_0_EF_ANA_TRIM_0,tmp); + }else if(slot==2){ + tmp=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_KEY_SLOT_5_W2); + tmp|=(Value<<16); + tmp|=(uint32_t)(parity<<31); + BL_WR_REG(EF_DATA_BASE,EF_DATA_0_EF_KEY_SLOT_5_W2,tmp); + + tmp=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_ANA_TRIM_0); + tmp|=(1<<1); + BL_WR_REG(EF_DATA_BASE,EF_DATA_0_EF_ANA_TRIM_0,tmp); + } + + if(program){ + EF_Ctrl_Program_Efuse_0(); + } + + while(SET==EF_Ctrl_Busy()); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Efuse read poweroffset value + * + * @param slot: Power offset slot + * @param pwrOffset[3]: Power offset array + * @param reload: Whether reload + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type EF_Ctrl_Read_PowerOffset_Opt(uint8_t slot,int8_t pwrOffset[3],uint8_t reload) +{ + uint64_t pwrOffsetValue=0; + + uint32_t tmp = 0,k; + uint8_t en=0,parity=0; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + if(reload){ + EF_CTRL_LOAD_BEFORE_READ_R0; + } + + if(slot==0){ + tmp=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_KEY_SLOT_5_W3); + en=(tmp>>15)&0x01; + pwrOffsetValue=(tmp>>16)&0x7fff; + parity=(tmp>>31)&0x01; + }else if(slot==1){ + tmp=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_KEY_SLOT_5_W2); + pwrOffsetValue=(tmp>>0)&0x7fff; + parity=(tmp>>15)&0x01; + + tmp=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_ANA_TRIM_0); + en=(tmp>>0)&0x01; + }else if(slot==2){ + tmp=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_KEY_SLOT_5_W2); + pwrOffsetValue=(tmp>>16)&0x7fff; + parity=(tmp>>31)&0x01; + + tmp=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_EF_ANA_TRIM_0); + en=(tmp>>1)&0x01; + } + + if(en){ + if(parity==EF_Ctrl_Get_Trim_Parity(pwrOffsetValue,15)){ + for(k=0;k<3;k++){ + tmp=(pwrOffsetValue>>(k*5))&0x1f; + if(tmp>=16){ + pwrOffset[k]=tmp-32; + }else{ + pwrOffset[k]=tmp; + } + } + return SUCCESS; + } + } + return ERROR; +} + +/****************************************************************************//** + * @brief Efuse write AES key + * + * @param index: index of key slot + * @param keyData: key data buffer + * @param len: key data length in words + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Write_AES_Key(uint8_t index,uint32_t *keyData,uint32_t len,uint8_t program) +{ + uint32_t *pAESKeyStart0=(uint32_t *)(EF_DATA_BASE+0x1C); + + if(index>5){ + return; + } + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + /* Every key is 4 words len*/ + BL602_MemCpy4(pAESKeyStart0+index*4,keyData,len); + + if( program){ + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************//** + * @brief Efuse read AES key from specified region and index + * + * @param index: index of key slot + * @param keyData: key data buffer + * @param len: key data length in words + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_AES_Key(uint8_t index,uint32_t *keyData,uint32_t len) +{ + uint32_t *pAESKeyStart0=(uint32_t *)(EF_DATA_BASE+0x1C); + + if(index>5){ + return; + } + /* Trigger read data from efuse*/ + EF_CTRL_LOAD_BEFORE_READ_R0; + + /* Every key is 4 words len*/ + BL602_MemCpy4(keyData,pAESKeyStart0+index*4,len); +} + +/****************************************************************************//** + * @brief Efuse lock writing for aes key + * + * @param index: index of key slot + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Writelock_AES_Key(uint8_t index,uint8_t program) +{ + uint32_t tmpVal; + + if(index>5){ + return; + } + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + tmpVal=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_LOCK); + if(index<=3){ + tmpVal|=(1<<(index+19)); + }else{ + tmpVal|=(1<<(index+19)); + tmpVal|=(1<<(index-4+13)); + } + BL_WR_REG(EF_DATA_BASE,EF_DATA_0_LOCK,tmpVal); + + if( program){ + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************//** + * @brief Efuse lock reading for aes key + * + * @param index: index of key slot + * @param program: program to efuse entity or not + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Readlock_AES_Key(uint8_t index,uint8_t program) +{ + uint32_t tmpVal; + + if(index>5){ + return; + } + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + tmpVal=BL_RD_REG(EF_DATA_BASE,EF_DATA_0_LOCK); + tmpVal|=(1<<(index+26)); + BL_WR_REG(EF_DATA_BASE,EF_DATA_0_LOCK,tmpVal); + + if( program){ + EF_Ctrl_Program_Efuse_0(); + } +} + +/****************************************************************************//** + * @brief Program data to efuse region 0 + * + * @param index: index of efuse in word + * @param data: data buffer + * @param len: data length + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len) +{ + uint32_t *pEfuseStart0=(uint32_t *)(EF_DATA_BASE+0x00); + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + /* Add delay for CLK to be stable */ + BL602_Delay_US(4); + + BL602_MemCpy4(pEfuseStart0+index,data,len); + + EF_Ctrl_Program_Efuse_0(); +} + +/****************************************************************************//** + * @brief Read data from efuse region 0 + * + * @param index: index of efuse in word + * @param data: data buffer + * @param len: data length + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len) +{ + uint32_t *pEfuseStart0=(uint32_t *)(EF_DATA_BASE+0x00); + + EF_CTRL_LOAD_BEFORE_READ_R0; + + BL602_MemCpy4(data,pEfuseStart0+index,len); +} + +/****************************************************************************//** + * @brief Write data to efuse region 0 without program + * + * @param index: index of efuse in word + * @param data: data buffer + * @param len: data length + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Write_R0(uint32_t index, uint32_t *data, uint32_t len) +{ + uint32_t *pEfuseStart0=(uint32_t *)(EF_DATA_BASE+0x00); + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + /* Add delay for CLK to be stable */ + BL602_Delay_US(4); + + BL602_MemCpy4(pEfuseStart0+index,data,len); +} + +/****************************************************************************//** + * @brief Read data from efuse region 0 without reload + * + * @param index: index of efuse in word + * @param data: data buffer + * @param len: data length + * + * @return None + * +*******************************************************************************/ +void EF_Ctrl_Read_R0(uint32_t index, uint32_t *data, uint32_t len) +{ + uint32_t *pEfuseStart0=(uint32_t *)(EF_DATA_BASE+0x00); + + BL602_MemCpy4(data,pEfuseStart0+index,len); +} + +/****************************************************************************//** + * @brief Clear efuse data register + * + * @param index: index of efuse in word + * @param len: data length + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION EF_Ctrl_Clear(uint32_t index, uint32_t len) +{ + uint32_t *pEfuseStart0=(uint32_t *)(EF_DATA_BASE+0x00); + uint32_t i=0; + + /* Switch to AHB clock */ + EF_Ctrl_Sw_AHB_Clk_0(); + + /* Clear data */ + for(i=0;i
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_glb.h" +#include "bl602_hbn.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup GLB + * @{ + */ + +/** @defgroup GLB_Private_Macros + * @{ + */ +#define GLB_CLK_SET_DUMMY_WAIT {__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();} +#define GLB_GPIO_Get_Reg(pin) (glb_gpio_reg_t*)(GLB_BASE+GLB_GPIO_OFFSET+(pin/2)*4) +#define GLB_GPIO_INT0_NUM (23) +#define GLB_REG_BCLK_DIS_TRUE (*(volatile uint32_t *)(0x40000FFC)=(0x00000001)) +#define GLB_REG_BCLK_DIS_FALSE (*(volatile uint32_t *)(0x40000FFC)=(0x00000000)) +#define GLB_GPIO_INT0_CLEAR_TIMEOUT (32) + +/*@} end of group GLB_Private_Macros */ + +/** @defgroup GLB_Private_Types + * @{ + */ + +/*@} end of group GLB_Private_Types */ + +/** @defgroup GLB_Private_Variables + * @{ + */ +static intCallback_Type * glbBmxErrIntCbfArra[BMX_ERR_INT_ALL]={NULL}; +static intCallback_Type * glbBmxToIntCbfArra[BMX_TO_INT_ALL]={NULL}; +static intCallback_Type * glbGpioInt0CbfArra[GLB_GPIO_INT0_NUM]={NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL, + NULL,NULL,NULL,NULL,NULL,NULL,NULL}; + + +/*@} end of group GLB_Private_Variables */ + +/** @defgroup GLB_Global_Variables + * @{ + */ + +/*@} end of group GLB_Global_Variables */ + +/** @defgroup GLB_Private_Fun_Declaration + * @{ + */ + +/*@} end of group GLB_Private_Fun_Declaration */ + +/** @defgroup GLB_Private_Functions + * @{ + */ + +/*@} end of group GLB_Private_Functions */ + +/** @defgroup GLB_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief get root clock selection + * + * @param None + * + * @return root clock selection + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +GLB_ROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_Root_CLK_Sel(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE,GLB_CLK_CFG0); + + switch(BL_GET_REG_BITS_VAL(tmpVal,GLB_HBN_ROOT_CLK_SEL)){ + case 0: + return GLB_ROOT_CLK_RC32M; + case 1: + return GLB_ROOT_CLK_XTAL; + case 2: + return GLB_ROOT_CLK_PLL; + case 3: + return GLB_ROOT_CLK_PLL; + default : + return GLB_ROOT_CLK_RC32M; + } +} +#endif + +/****************************************************************************//** + * @brief Set System clock divider + * + * @param hclkDiv: HCLK divider + * @param bclkDiv: BCLK divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK_Div(uint8_t hclkDiv,uint8_t bclkDiv) +{ + /***********************************************************************************/ + /* NOTE */ + /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */ + /* OCRAM use bclk as source clock. Pay attention to risks when using this API. */ + /***********************************************************************************/ + uint32_t tmpVal; + + /* recommended: fclk<=160MHz, bclk<=80MHz */ + tmpVal=BL_RD_REG(GLB_BASE,GLB_CLK_CFG0); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_REG_HCLK_DIV,hclkDiv); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_REG_BCLK_DIV,bclkDiv); + BL_WR_REG(GLB_BASE,GLB_CLK_CFG0,tmpVal); + GLB_REG_BCLK_DIS_TRUE; + GLB_REG_BCLK_DIS_FALSE; + SystemCoreClockSet(SystemCoreClockGet()/((uint16_t)hclkDiv+1)); + GLB_CLK_SET_DUMMY_WAIT; + + tmpVal=BL_RD_REG(GLB_BASE,GLB_CLK_CFG0); + tmpVal=BL_SET_REG_BIT(tmpVal,GLB_REG_HCLK_EN); + tmpVal=BL_SET_REG_BIT(tmpVal,GLB_REG_BCLK_EN); + BL_WR_REG(GLB_BASE,GLB_CLK_CFG0,tmpVal); + GLB_CLK_SET_DUMMY_WAIT; + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief Get Bus clock divider + * + * @param None + * + * @return Clock Divider + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint8_t ATTR_CLOCK_SECTION GLB_Get_BCLK_Div(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(GLB_BASE,GLB_CLK_CFG0); + + return BL_GET_REG_BITS_VAL(tmpVal,GLB_REG_BCLK_DIV); +} +#endif + +/****************************************************************************//** + * @brief Get CPU clock divider + * + * @param None + * + * @return Clock Divider + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint8_t ATTR_CLOCK_SECTION GLB_Get_HCLK_Div(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(GLB_BASE,GLB_CLK_CFG0); + + return BL_GET_REG_BITS_VAL(tmpVal,GLB_REG_HCLK_DIV); +} +#endif + +/****************************************************************************//** + * @brief update SystemCoreClock value + * + * @param xtalType: XTAL frequency type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION Update_SystemCoreClockWith_XTAL(GLB_PLL_XTAL_Type xtalType) +{ + CHECK_PARAM(IS_GLB_PLL_XTAL_TYPE(xtalType)); + + switch(xtalType){ + case GLB_PLL_XTAL_NONE: + break; + case GLB_PLL_XTAL_24M: + SystemCoreClockSet(24000000); + break; + case GLB_PLL_XTAL_32M: + SystemCoreClockSet(32000000); + break; + case GLB_PLL_XTAL_38P4M: + SystemCoreClockSet(38400000); + break; + case GLB_PLL_XTAL_40M: + SystemCoreClockSet(40000000); + break; + case GLB_PLL_XTAL_26M: + SystemCoreClockSet(26000000); + break; + case GLB_PLL_XTAL_RC32M: + SystemCoreClockSet(32000000); + break; + default : + break; + } + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief Set System clock + * + * @param xtalType: XTAL frequency type + * @param clkFreq: clock frequency selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK(GLB_PLL_XTAL_Type xtalType,GLB_SYS_CLK_Type clkFreq) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GLB_PLL_XTAL_TYPE(xtalType)); + CHECK_PARAM(IS_GLB_SYS_CLK_TYPE(clkFreq)); + + /* reg_bclk_en = reg_hclk_en = reg_fclk_en = 1, cannot be zero */ + tmpVal = BL_RD_REG(GLB_BASE,GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BIT(tmpVal,GLB_REG_BCLK_EN); + tmpVal = BL_SET_REG_BIT(tmpVal,GLB_REG_HCLK_EN); + tmpVal = BL_SET_REG_BIT(tmpVal,GLB_REG_FCLK_EN); + BL_WR_REG(GLB_BASE,GLB_CLK_CFG0,tmpVal); + + /* Before config XTAL and PLL ,make sure root clk is from RC32M */ + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M); + GLB_Set_System_CLK_Div(0,0); + SystemCoreClockSet(32*1000*1000); + + /* Select PKA clock from hclk */ + GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_HCLK); + + if(xtalType==GLB_PLL_XTAL_NONE){ + if(clkFreq==GLB_SYS_CLK_RC32M){ + return SUCCESS; + }else{ + return ERROR; + } + } + + if(xtalType!=GLB_PLL_XTAL_RC32M){ + /* power on xtal first */ + AON_Power_On_XTAL(); + } + + /* always power up PLL and enable all PLL clock output */ + PDS_Power_On_PLL((PDS_PLL_XTAL_Type)xtalType); + BL602_Delay_US(55); + PDS_Enable_PLL_All_Clks(); + + /* reg_pll_en = 1, cannot be zero */ + tmpVal = BL_RD_REG(GLB_BASE,GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BIT(tmpVal,GLB_REG_PLL_EN); + BL_WR_REG(GLB_BASE,GLB_CLK_CFG0,tmpVal); + + /* select pll output clock before select root clock */ + if(clkFreq>=GLB_SYS_CLK_PLL48M){ + tmpVal = BL_RD_REG(GLB_BASE,GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_REG_PLL_SEL,clkFreq-GLB_SYS_CLK_PLL48M); + BL_WR_REG(GLB_BASE,GLB_CLK_CFG0,tmpVal); + } + /* select root clock */ + switch(clkFreq){ + case GLB_SYS_CLK_RC32M: + break; + case GLB_SYS_CLK_XTAL: + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + Update_SystemCoreClockWith_XTAL(xtalType); + break; + case GLB_SYS_CLK_PLL48M: + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_PLL); + SystemCoreClockSet(48*1000*1000); + break; + case GLB_SYS_CLK_PLL120M: + GLB_Set_System_CLK_Div(0,1); + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_PLL); + SystemCoreClockSet(120*1000*1000); + break; + case GLB_SYS_CLK_PLL160M: + L1C_IROM_2T_Access_Set(ENABLE); + GLB_Set_System_CLK_Div(0,1); + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_PLL); + SystemCoreClockSet(160*1000*1000); + break; + case GLB_SYS_CLK_PLL192M: + L1C_IROM_2T_Access_Set(ENABLE); + GLB_Set_System_CLK_Div(0,1); + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_PLL); + SystemCoreClockSet(192*1000*1000); + break; + default : + break; + } + + GLB_CLK_SET_DUMMY_WAIT; + + /* select PKA clock from 120M since we power up PLL */ + GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_PLL120M); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief This is demo for user that use RC32M as default bootup clock instead of PLL,when APP is + * started, this function can be called to set PLL to 160M + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION System_Core_Clock_Update_From_RC32M(void) +{ + SF_Ctrl_Cfg_Type sfCtrlCfg={ + .owner=SF_CTRL_OWNER_IAHB, + .clkDelay=1, + .clkInvert=1, + .rxClkInvert=1, + .doDelay=0, + .diDelay=0, + .oeDelay=0, + }; + /* Use RC32M as PLL ref source to set up PLL to 160M */ + GLB_Set_System_CLK(GLB_PLL_XTAL_RC32M,GLB_SYS_CLK_PLL160M); + /* Flash controller also need changes since system (bus) clock changed */ + SF_Ctrl_Enable(&sfCtrlCfg); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief set BLE clock + * + * @param enable: Enable or disable BLE clock + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_BLE_CLK(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE,GLB_CLK_CFG1); + if(enable){ + tmpVal = BL_SET_REG_BIT(tmpVal,GLB_BLE_EN); + }else{ + tmpVal = BL_CLR_REG_BIT(tmpVal,GLB_BLE_EN); + } + BL_WR_REG(GLB_BASE,GLB_CLK_CFG1,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief set wifi core clock divider + * + * @param clkDiv: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_WiFi_Core_CLK(uint8_t clkDiv) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((clkDiv<=0x3)); + + tmpVal = BL_RD_REG(GLB_BASE,GLB_CLK_CFG1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_WIFI_MAC_CORE_DIV,clkDiv); + BL_WR_REG(GLB_BASE,GLB_CLK_CFG1,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief set wifi encryption clock + * + * @param clkDiv: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_WiFi_Encrypt_CLK(uint8_t clkDiv) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((clkDiv<=0x3)); + + tmpVal = BL_RD_REG(GLB_BASE,GLB_CLK_CFG1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_WIFI_MAC_WT_DIV,clkDiv); + BL_WR_REG(GLB_BASE,GLB_CLK_CFG1,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief set DMA clock + * + * @param enable: Enable or disable BLE clock + * @param clk: DMA clock type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable,GLB_DMA_CLK_ID_Type clk) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + tmpVal=BL_RD_REG(GLB_BASE,GLB_CLK_CFG2); + tmpVal2=BL_GET_REG_BITS_VAL(tmpVal,GLB_DMA_CLK_EN); + if(enable){ + tmpVal2 |=(1<timeoutEn)<=0xF); + + tmpVal=BL_RD_REG(GLB_BASE,GLB_BMX_CFG1); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_BMX_TIMEOUT_EN,BmxCfg->timeoutEn); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_BMX_ERR_EN,BmxCfg->errEn); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_BMX_ARB_MODE,BmxCfg->arbMod); + BL_WR_REG(GLB_BASE,GLB_BMX_CFG1,tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(BMX_ERR_IRQn,BMX_ERR_IRQHandler); + Interrupt_Handler_Register(BMX_TO_IRQn,BMX_TO_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************//** + * @brief BMX address monitor enable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_Addr_Monitor_Enable(void) +{ + uint32_t tmpVal = 0; + + tmpVal=BL_RD_REG(GLB_BASE,GLB_BMX_CFG2); + tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_BMX_ERR_ADDR_DIS); + BL_WR_REG(GLB_BASE,GLB_BMX_CFG2,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief BMX address monitor disable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_Addr_Monitor_Disable(void) +{ + uint32_t tmpVal = 0; + + tmpVal=BL_RD_REG(GLB_BASE,GLB_BMX_CFG2); + tmpVal=BL_SET_REG_BIT(tmpVal,GLB_BMX_ERR_ADDR_DIS); + BL_WR_REG(GLB_BASE,GLB_BMX_CFG2,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief BMX bus error response enable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_BusErrResponse_Enable(void) +{ + uint32_t tmpVal = 0; + + tmpVal=BL_RD_REG(GLB_BASE,GLB_BMX_CFG1); + tmpVal=BL_SET_REG_BIT(tmpVal,GLB_BMX_ERR_EN); + BL_WR_REG(GLB_BASE,GLB_BMX_CFG1,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief BMX bus error response disable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_BusErrResponse_Disable(void) +{ + uint32_t tmpVal = 0; + + tmpVal=BL_RD_REG(GLB_BASE,GLB_BMX_CFG1); + tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_BMX_ERR_EN); + BL_WR_REG(GLB_BASE,GLB_BMX_CFG1,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Get BMX error status + * + * @param errType: BMX error status type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_BMX_BUS_ERR_TYPE(errType)); + + tmpVal=BL_RD_REG(GLB_BASE,GLB_BMX_CFG2); + if(errType==BMX_BUS_ERR_TRUSTZONE_DECODE){ + return BL_GET_REG_BITS_VAL(tmpVal,GLB_BMX_ERR_TZ)?SET:RESET; + }else{ + return BL_GET_REG_BITS_VAL(tmpVal,GLB_BMX_ERR_DEC)?SET:RESET; + } +} + +/****************************************************************************//** + * @brief Get BMX error address + * + * @param None + * + * @return NP BMX error address + * +*******************************************************************************/ +uint32_t GLB_BMX_Get_Err_Addr(void) +{ + return BL_RD_REG(GLB_BASE,GLB_BMX_ERR_ADDR); +} + +/****************************************************************************//** + * @brief BMX error interrupt callback install + * + * @param intType: BMX error interrupt type + * @param cbFun: callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type BMX_ERR_INT_Callback_Install(BMX_ERR_INT_Type intType,intCallback_Type* cbFun) +{ + CHECK_PARAM(IS_BMX_ERR_INT_TYPE(intType)); + + glbBmxErrIntCbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************//** + * @brief BMX ERR interrupt IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void BMX_ERR_IRQHandler(void) +{ + BMX_ERR_INT_Type intType; + + for(intType=BMX_ERR_INT_ERR;intType10 && gpio<14){ + tmpVal=BL_RD_REG(GLB_BASE,GLB_LED_DRIVER); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_IR_RX_GPIO_SEL,gpio-10); + BL_WR_REG(GLB_BASE,GLB_LED_DRIVER,tmpVal); + } + + /* Close ir rx */ + if(gpio == 0){ + tmpVal=BL_RD_REG(GLB_BASE,GLB_LED_DRIVER); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_IR_RX_GPIO_SEL,0); + BL_WR_REG(GLB_BASE,GLB_LED_DRIVER,tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Enable ir led driver + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_IR_LED_Driver_Enable(void) +{ + uint32_t tmpVal=0; + + /* Enable led driver */ + tmpVal=BL_RD_REG(GLB_BASE,GLB_LED_DRIVER); + tmpVal=BL_SET_REG_BIT(tmpVal,GLB_PU_LEDDRV); + BL_WR_REG(GLB_BASE,GLB_LED_DRIVER,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Disable ir led driver + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_IR_LED_Driver_Disable(void) +{ + uint32_t tmpVal=0; + + /* Disable led driver */ + tmpVal=BL_RD_REG(GLB_BASE,GLB_LED_DRIVER); + tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_PU_LEDDRV); + BL_WR_REG(GLB_BASE,GLB_LED_DRIVER,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Set ir led driver ibias + * + * @param ibias: Ibias value,0x0:0mA~0xf:120mA,8mA/step + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias) +{ + uint32_t tmpVal=0; + + /* Set driver ibias */ + tmpVal=BL_RD_REG(GLB_BASE,GLB_LED_DRIVER); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_LEDDRV_IBIAS,ibias&0xF); + BL_WR_REG(GLB_BASE,GLB_LED_DRIVER,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief GPIO initialization + * + * @param cfg: GPIO configuration + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg) +{ + uint8_t gpioPin=cfg->gpioPin; + uint32_t *pOut; + uint32_t pos; + uint32_t tmpOut; + uint32_t tmpVal; + + /* drive strength(drive) = 0 <=> 8.0mA @ 3.3V */ + /* drive strength(drive) = 1 <=> 9.6mA @ 3.3V */ + /* drive strength(drive) = 2 <=> 11.2mA @ 3.3V */ + /* drive strength(drive) = 3 <=> 12.8mA @ 3.3V */ + + pOut=(uint32_t *)(GLB_BASE+GLB_GPIO_OUTPUT_EN_OFFSET+((gpioPin>>5)<<2)); + pos=gpioPin%32; + tmpOut=*pOut; + + /* Disable output anyway*/ + tmpOut &= (~(1<gpioMode!=GPIO_MODE_ANALOG){ + /* not analog mode */ + + /* Set input or output */ + if(cfg->gpioMode==GPIO_MODE_OUTPUT){ + tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_GPIO_0_IE); + tmpOut |= (1<pullType==GPIO_PULL_UP){ + tmpVal=BL_SET_REG_BIT(tmpVal,GLB_REG_GPIO_0_PU); + }else if(cfg->pullType==GPIO_PULL_DOWN){ + tmpVal=BL_SET_REG_BIT(tmpVal,GLB_REG_GPIO_0_PD); + } + }else{ + /* analog mode */ + + /* clear ie && oe */ + tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_GPIO_0_IE); + tmpOut &= ~(1<drive); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_REG_GPIO_0_SMT,cfg->smtCtrl); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_REG_GPIO_0_FUNC_SEL,cfg->gpioFun); + }else{ + if(cfg->gpioMode!=GPIO_MODE_ANALOG){ + /* not analog mode */ + + /* Set input or output */ + if(cfg->gpioMode==GPIO_MODE_OUTPUT) { + tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_GPIO_1_IE); + tmpOut |= (1<pullType==GPIO_PULL_UP){ + tmpVal=BL_SET_REG_BIT(tmpVal,GLB_REG_GPIO_1_PU); + }else if(cfg->pullType==GPIO_PULL_DOWN){ + tmpVal=BL_SET_REG_BIT(tmpVal,GLB_REG_GPIO_1_PD); + } + }else{ + /* analog mode */ + + /* clear ie && oe */ + tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_GPIO_1_IE); + tmpOut &= ~(1<drive); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_REG_GPIO_1_SMT,cfg->smtCtrl); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_REG_GPIO_1_FUNC_SEL,cfg->gpioFun); + } + BL_WR_WORD(GLB_BASE+GLB_GPIO_OFFSET+gpioPin/2*4,tmpVal); + + *pOut=tmpOut; + + return SUCCESS; +} + +/****************************************************************************//** + * @brief init GPIO function in pin list + * + * @param gpioFun: GPIO pin function + * @param pinList: GPIO pin list + * @param cnt: GPIO pin count + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun,GLB_GPIO_Type *pinList,uint8_t cnt) +{ + GLB_GPIO_Cfg_Type gpioCfg = { + .gpioPin=GLB_GPIO_PIN_0, + .gpioFun=(uint8_t)gpioFun, + .gpioMode=GPIO_MODE_AF, + .pullType=GPIO_PULL_UP, + .drive=1, + .smtCtrl=1 + }; + + if(gpioFun==GPIO_FUN_ANALOG){ + gpioCfg.gpioMode=GPIO_MODE_ANALOG; + } + + for(uint8_t i=0;i>1)<<2; + tmpVal=*(uint32_t *)(GLB_BASE+GLB_GPIO_OFFSET+pinOffset); + if(gpioPin%2==0){ + /* [0] is ie */ + tmpVal=BL_SET_REG_BIT(tmpVal,GLB_REG_GPIO_0_IE); + }else{ + /* [16] is ie */ + tmpVal=BL_SET_REG_BIT(tmpVal,GLB_REG_GPIO_1_IE); + } + *(uint32_t *)(GLB_BASE+GLB_GPIO_OFFSET+pinOffset)=tmpVal; + + return SUCCESS; +} + +/****************************************************************************//** + * @brief GPIO set input function disable + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + uint32_t pinOffset; + + pinOffset=(gpioPin>>1)<<2; + tmpVal=*(uint32_t *)(GLB_BASE+GLB_GPIO_OFFSET+pinOffset); + if(gpioPin%2==0){ + /* [0] is ie */ + tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_GPIO_0_IE); + }else{ + /* [16] is ie */ + tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_GPIO_1_IE); + } + *(uint32_t *)(GLB_BASE+GLB_GPIO_OFFSET+pinOffset)=tmpVal; + + return SUCCESS; +} + +/****************************************************************************//** + * @brief GPIO set output function enable + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(GLB_BASE,GLB_GPIO_CFGCTL34); + tmpVal=tmpVal|(1<>5)<<2)); + pos=gpioPin%32; + tmpOut=*pOut; + + /* Disable output anyway*/ + tmpOut &= (~(1<>5)<<2)); + uint32_t pos=gpioPin%32; + uint32_t tmpOut; + + tmpOut=*pOut; + if(val>0){ + tmpOut |= (1<>5)<<2)); + uint32_t pos=gpioPin%32; + + if((*p)&(1<>(bitVal*3); + return (tmpVal>>2)?GLB_GPIO_INT_CONTROL_ASYNC:GLB_GPIO_INT_CONTROL_SYNC; + }else if((gpioPin>GLB_GPIO_PIN_9)&&(gpioPin>(bitVal*3); + return (tmpVal>>2)?GLB_GPIO_INT_CONTROL_ASYNC:GLB_GPIO_INT_CONTROL_SYNC; + }else{ + /* GPIO20 - GPIO29 */ + bitVal=gpioPin-20; + tmpVal=BL_RD_REG(GLB_BASE,GLB_GPIO_INT_MODE_SET3); + tmpVal=(tmpVal&(0x7<<(bitVal*3)))>>(bitVal*3); + return (tmpVal>>2)?GLB_GPIO_INT_CONTROL_ASYNC:GLB_GPIO_INT_CONTROL_SYNC; + } +} + +/****************************************************************************//** + * @brief GPIO INT0 IRQHandler install + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void) +{ +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(GPIO_INT0_IRQn,GPIO_INT0_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************//** + * @brief GPIO interrupt IRQ handler callback install + * + * @param gpioPin: GPIO pin type + * @param cbFun: callback function + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin,intCallback_Type* cbFun) +{ + if(gpioPin<32){ + glbGpioInt0CbfArra[gpioPin] = cbFun; + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief GPIO interrupt IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void GPIO_INT0_IRQHandler(void) +{ + GLB_GPIO_Type gpioPin; + uint32_t timeOut=0; + + for(gpioPin=GLB_GPIO_PIN_0;gpioPin<=GLB_GPIO_PIN_22;gpioPin++){ + if(SET==GLB_Get_GPIO_IntStatus(gpioPin)){ + GLB_GPIO_IntClear(gpioPin,SET); + + /* timeout check */ + timeOut=GLB_GPIO_INT0_CLEAR_TIMEOUT; + do{ + timeOut--; + }while((SET==GLB_Get_GPIO_IntStatus(gpioPin))&&timeOut); + if(!timeOut){ + MSG("WARNING: Clear GPIO interrupt status fail.\r\n"); + } + + /* if timeOut==0, GPIO interrupt status not cleared */ + GLB_GPIO_IntClear(gpioPin,RESET); + + if(glbGpioInt0CbfArra[gpioPin] != NULL) { + /* Call the callback function */ + glbGpioInt0CbfArra[gpioPin](); + } + } + } +} +#endif + +/*@} end of group GLB_Public_Functions */ + +/*@} end of group GLB */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/bl602_driver/std_drv/src/bl602_hbn.c b/drivers/bl602_driver/std_drv/src/bl602_hbn.c new file mode 100644 index 00000000..115a7fa3 --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_hbn.c @@ -0,0 +1,1840 @@ +/** + ****************************************************************************** + * @file bl602_hbn.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_hbn.h" +#include "bl602_glb.h" +#include "bl602_xip_sflash.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup HBN + * @{ + */ + +/** @defgroup HBN_Private_Macros + * @{ + */ +#define HBN_CLK_SET_DUMMY_WAIT {__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();} + +/*@} end of group HBN_Private_Macros */ + +/** @defgroup HBN_Private_Types + * @{ + */ + +/*@} end of group HBN_Private_Types */ + +/** @defgroup HBN_Private_Variables + * @{ + */ +static intCallback_Type * hbnInt0CbfArra[3]={NULL,NULL,NULL}; +static intCallback_Type * hbnInt1CbfArra[4]={NULL,NULL,NULL,NULL}; + + +/*@} end of group HBN_Private_Variables */ + +/** @defgroup HBN_Global_Variables + * @{ + */ + +/*@} end of group HBN_Global_Variables */ + +/** @defgroup HBN_Private_Fun_Declaration + * @{ + */ + +/*@} end of group HBN_Private_Fun_Declaration */ + +/** @defgroup HBN_Private_Functions + * @{ + */ + +/*@} end of group HBN_Private_Functions */ + +/** @defgroup HBN_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief Enter HBN + * + * @param cfg: HBN APP Config + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION HBN_Mode_Enter(HBN_APP_CFG_Type *cfg) +{ + uint32_t valLow=0,valHigh=0; + uint64_t val; + + if(cfg->useXtal32k){ + HBN_32K_Sel(HBN_32K_XTAL); + }else{ + HBN_32K_Sel(HBN_32K_RC); + HBN_Power_Off_Xtal_32K(); + } + + /* always disable HBN pin pull up/down to reduce PDS/HBN current, 0x4000F014[16]=0 */ + HBN_Hw_Pu_Pd_Cfg(DISABLE); + + HBN_Pin_WakeUp_Mask(~(cfg->gpioWakeupSrc)); + if(cfg->gpioWakeupSrc!=0){ + HBN_Aon_Pad_IeSmt_Cfg(ENABLE); + HBN_GPIO_INT_Enable(cfg->gpioTrigType); + }else{ + HBN_Aon_Pad_IeSmt_Cfg(DISABLE); + } + + /* HBN RTC config and enable */ + HBN_Clear_RTC_Counter(); + if(cfg->sleepTime!=0){ + HBN_Get_RTC_Timer_Val(&valLow,&valHigh); + val=valLow+((uint64_t)valHigh<<32); + val+=cfg->sleepTime*32768; + HBN_Set_RTC_Timer(HBN_RTC_INT_DELAY_0T,val&0xffffffff,val>>32,HBN_RTC_COMP_BIT0_39); + HBN_Enable_RTC_Counter(); + } + + HBN_Power_Down_Flash(cfg->flashCfg); + HBN_Set_Embedded_Flash_Pullup(ENABLE); /* E_ITEM_06 */ + + GLB_Set_System_CLK(GLB_PLL_XTAL_NONE,GLB_SYS_CLK_RC32M); + + HBN_Enable(cfg->gpioWakeupSrc,cfg->ldoLevel,cfg->hbnLevel); +} + +/****************************************************************************//** + * @brief Enter HBN + * + * @param cfg: HBN APP Config + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION HBN_Mode_Enter_Ext(HBN_APP_CFG_Type *cfg) +{ + uint32_t valLow=0,valHigh=0; + uint64_t val; + + if(cfg->useXtal32k){ + HBN_32K_Sel(HBN_32K_XTAL); + }else{ + HBN_32K_Sel(HBN_32K_RC); + HBN_Power_Off_Xtal_32K(); + } + + /* always disable HBN pin pull up/down to reduce PDS/HBN current, 0x4000F014[16]=0 */ + HBN_Hw_Pu_Pd_Cfg(DISABLE); + + HBN_Pin_WakeUp_Mask(~(cfg->gpioWakeupSrc)); + if(cfg->gpioWakeupSrc!=0){ + HBN_Aon_Pad_IeSmt_Cfg(ENABLE); + HBN_GPIO_INT_Enable(cfg->gpioTrigType); + }else{ + HBN_Aon_Pad_IeSmt_Cfg(DISABLE); + } + + /* HBN RTC config and enable */ + if(cfg->sleepTime!=0){ + HBN_Clear_RTC_Counter(); + HBN_Get_RTC_Timer_Val(&valLow,&valHigh); + val=valLow+((uint64_t)valHigh<<32); + val+=cfg->sleepTime; + HBN_Set_RTC_Timer(HBN_RTC_INT_DELAY_0T,val&0xffffffff,val>>32,HBN_RTC_COMP_BIT0_39); + HBN_Enable_RTC_Counter(); + } + + HBN_Power_Down_Flash(cfg->flashCfg); + HBN_Set_Embedded_Flash_Pullup(ENABLE); /* E_ITEM_06 */ + + GLB_Set_System_CLK(GLB_PLL_XTAL_NONE,GLB_SYS_CLK_RC32M); + + HBN_Enable_Ext(cfg->gpioWakeupSrc,cfg->ldoLevel,cfg->hbnLevel); +} + +/****************************************************************************//** + * @brief power down and switch clock + * + * @param flashCfg: None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg) +{ + SPI_Flash_Cfg_Type bhFlashCfg; + + if(flashCfg==NULL){ + SFlash_Cache_Flush(); + XIP_SFlash_Read_Via_Cache_Need_Lock(BL602_FLASH_XIP_BASE+8+4,(uint8_t *)(&bhFlashCfg),sizeof(SPI_Flash_Cfg_Type)); + SFlash_Cache_Flush(); + + SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); + SFlash_Reset_Continue_Read(&bhFlashCfg); + }else{ + SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); + SFlash_Reset_Continue_Read(flashCfg); + } + + SFlash_Powerdown(); +} +#endif + +/****************************************************************************//** + * @brief Enable HBN mode + * + * @param aGPIOIeCfg: AON GPIO input enable config. Bit(s) of Wakeup GPIO(s) must not be set to + * 0(s),say when use GPIO7 as wake up pin,aGPIOIeCfg should be 0x01. + * @param ldoLevel: LDO volatge level + * @param hbnLevel: HBN work level + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION HBN_Enable(uint8_t aGPIOIeCfg,HBN_LDO_LEVEL_Type ldoLevel,HBN_LEVEL_Type hbnLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + CHECK_PARAM(IS_HBN_LEVEL_TYPE(hbnLevel)); + + /* Setting from guide */ + /* RAM Retion */ + BL_WR_REG(HBN_BASE,HBN_SRAM,0x24); + /* AON GPIO IE */ + tmpVal=BL_RD_REG(HBN_BASE,HBN_IRQ_MODE); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_REG_AON_PAD_IE_SMT,aGPIOIeCfg); + tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_REG_EN_HW_PU_PD); + BL_WR_REG(HBN_BASE,HBN_IRQ_MODE,tmpVal); + ///* Power off 1.8V */ + //tmpVal=BL_RD_REG(AON_BASE,AON_PMIP); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_TOPLDO11_SOC); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_TOPLDO18_RF); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_TOPLDO18_IO); + ///* SOC11 enum is not the same as VDD11*/ + //tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_TOPLDO11_SOC_VOUT_SEL,ldoLevel-1); + //BL_WR_REG(AON_BASE,AON_PMIP,tmpVal); + // + ///* Set RT voltage */ + //tmpVal=BL_RD_REG(AON_BASE,AON); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_SW3); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_SW2); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_SW1); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_BYPASS); + //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_LDO18_AON); + ///* RT11 enum is not the same as VDD11*/ + //tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_TOPLDO11_RT_VOUT_SEL,ldoLevel-1); + //tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_VDD11_SEL,ldoLevel); + //BL_WR_REG(AON_BASE,AON,tmpVal); + + /* Select RC32M */ + tmpVal=BL_RD_REG(HBN_BASE,HBN_GLB); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_ROOT_CLK_SEL,0); + BL_WR_REG(HBN_BASE,HBN_GLB,tmpVal); + __NOP();__NOP();__NOP();__NOP(); + + /* Set HBN flag */ + BL_WR_REG(HBN_BASE,HBN_RSV0,HBN_STATUS_ENTER_FLAG); + + tmpVal=BL_RD_REG(HBN_BASE,HBN_CTL); + /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */ + switch(hbnLevel){ + case HBN_LEVEL_0: + tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_PWRDN_HBN_CORE); + tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_1: + tmpVal=BL_SET_REG_BIT(tmpVal,HBN_PWRDN_HBN_CORE); + tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_2: + tmpVal=BL_SET_REG_BIT(tmpVal,HBN_PWRDN_HBN_CORE); + tmpVal=BL_SET_REG_BIT(tmpVal,HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_3: + tmpVal=BL_SET_REG_BIT(tmpVal,HBN_PWRDN_HBN_CORE); + tmpVal=BL_SET_REG_BIT(tmpVal,HBN_PWRDN_HBN_RTC); + break; + + default : + break; + } + /* Set power on option:0 for por reset twice for robust 1 for reset only once*/ + tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_PWR_ON_OPTION); + BL_WR_REG(HBN_BASE,HBN_CTL,tmpVal); + + /* Enable HBN mode */ + tmpVal=BL_RD_REG(HBN_BASE,HBN_CTL); + tmpVal=BL_SET_REG_BIT(tmpVal,HBN_MODE); + BL_WR_REG(HBN_BASE,HBN_CTL,tmpVal); + + while(1){ + BL602_Delay_MS(1000); + } +} +#endif + +/****************************************************************************//** + * @brief Enable HBN mode + * + * @param aGPIOIeCfg: AON GPIO input enable config. Bit(s) of Wakeup GPIO(s) must not be set to + * 0(s),say when use GPIO7 as wake up pin,aGPIOIeCfg should be 0x01. + * @param ldoLevel: LDO volatge level + * @param hbnLevel: HBN work level + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION HBN_Enable_Ext(uint8_t aGPIOIeCfg,HBN_LDO_LEVEL_Type ldoLevel,HBN_LEVEL_Type hbnLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + CHECK_PARAM(IS_HBN_LEVEL_TYPE(hbnLevel)); + + /* Setting from guide */ + /* RAM Retion */ + BL_WR_REG(HBN_BASE,HBN_SRAM,0x24); + /* AON GPIO IE */ + tmpVal=BL_RD_REG(HBN_BASE,HBN_IRQ_MODE); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_REG_AON_PAD_IE_SMT,aGPIOIeCfg); + tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_REG_EN_HW_PU_PD); + BL_WR_REG(HBN_BASE,HBN_IRQ_MODE,tmpVal); + + /* HBN mode LDO level */ + tmpVal=BL_RD_REG(HBN_BASE,HBN_CTL); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_LDO11_AON_VOUT_SEL,ldoLevel); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_LDO11_RT_VOUT_SEL,ldoLevel); + BL_WR_REG(HBN_BASE,HBN_CTL,tmpVal); + + /* Select RC32M */ + tmpVal=BL_RD_REG(HBN_BASE,HBN_GLB); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_ROOT_CLK_SEL,0); + BL_WR_REG(HBN_BASE,HBN_GLB,tmpVal); + __NOP();__NOP();__NOP();__NOP(); + + /* Set HBN flag */ + BL_WR_REG(HBN_BASE,HBN_RSV0,HBN_STATUS_ENTER_FLAG); + + tmpVal=BL_RD_REG(HBN_BASE,HBN_CTL); + /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */ + switch(hbnLevel){ + case HBN_LEVEL_0: + tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_PWRDN_HBN_CORE); + tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_1: + tmpVal=BL_SET_REG_BIT(tmpVal,HBN_PWRDN_HBN_CORE); + tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_2: + tmpVal=BL_SET_REG_BIT(tmpVal,HBN_PWRDN_HBN_CORE); + tmpVal=BL_SET_REG_BIT(tmpVal,HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_3: + tmpVal=BL_SET_REG_BIT(tmpVal,HBN_PWRDN_HBN_CORE); + tmpVal=BL_SET_REG_BIT(tmpVal,HBN_PWRDN_HBN_RTC); + break; + + default : + break; + } + /* Set power on option:0 for por reset twice for robust 1 for reset only once*/ + tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_PWR_ON_OPTION); + BL_WR_REG(HBN_BASE,HBN_CTL,tmpVal); + + /* Enable HBN mode */ + tmpVal=BL_RD_REG(HBN_BASE,HBN_CTL); + tmpVal=BL_SET_REG_BIT(tmpVal,HBN_MODE); + BL_WR_REG(HBN_BASE,HBN_CTL,tmpVal); + + while(1){ + BL602_Delay_MS(1000); + } +} + +/****************************************************************************//** + * @brief Reset HBN mode + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_Reset(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(HBN_BASE,HBN_CTL); + /* Reset HBN mode */ + tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_SW_RST); + BL_WR_REG(HBN_BASE,HBN_CTL,tmpVal); + + tmpVal=BL_SET_REG_BIT(tmpVal,HBN_SW_RST); + BL_WR_REG(HBN_BASE,HBN_CTL,tmpVal); + + tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_SW_RST); + BL_WR_REG(HBN_BASE,HBN_CTL,tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief reset HBN by software + * + * @param npXtalType: NP clock type + * @param bclkDiv: NP clock div + * @param apXtalType: AP clock type + * @param fclkDiv: AP clock div + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_App_Reset(uint8_t npXtalType,uint8_t bclkDiv,uint8_t apXtalType,uint8_t fclkDiv) +{ + uint32_t tmp[12]; + + tmp[0]=BL_RD_REG(HBN_BASE,HBN_CTL); + tmp[1]=BL_RD_REG(HBN_BASE,HBN_TIME_L); + tmp[2]=BL_RD_REG(HBN_BASE,HBN_TIME_H); + tmp[3]=BL_RD_REG(HBN_BASE,HBN_IRQ_MODE); + tmp[4]=BL_RD_REG(HBN_BASE,HBN_IRQ_CLR); + tmp[5]=BL_RD_REG(HBN_BASE,HBN_PIR_CFG); + tmp[6]=BL_RD_REG(HBN_BASE,HBN_PIR_VTH); + tmp[7]=BL_RD_REG(HBN_BASE,HBN_PIR_INTERVAL); + tmp[8]=BL_RD_REG(HBN_BASE,HBN_SRAM); + tmp[9]=BL_RD_REG(HBN_BASE,HBN_RSV0); + tmp[10]=BL_RD_REG(HBN_BASE,HBN_RSV1); + tmp[11]=BL_RD_REG(HBN_BASE,HBN_RSV2); + /* DO HBN reset */ + HBN_Reset(); + /* HBN need 3 32k cyclce to recovery */ + BL602_Delay_US(100); + /* Recover HBN value */ + BL_WR_REG(HBN_BASE,HBN_TIME_L,tmp[1]); + BL_WR_REG(HBN_BASE,HBN_TIME_H,tmp[2]); + BL_WR_REG(HBN_BASE,HBN_CTL,tmp[0]); + + BL_WR_REG(HBN_BASE,HBN_IRQ_MODE,tmp[3]); + BL_WR_REG(HBN_BASE,HBN_IRQ_CLR,tmp[4]); + BL_WR_REG(HBN_BASE,HBN_PIR_CFG,tmp[5]); + BL_WR_REG(HBN_BASE,HBN_PIR_VTH,tmp[6]); + BL_WR_REG(HBN_BASE,HBN_PIR_INTERVAL,tmp[7]); + BL_WR_REG(HBN_BASE,HBN_SRAM,tmp[8]); + BL_WR_REG(HBN_BASE,HBN_RSV0,tmp[9]); + BL_WR_REG(HBN_BASE,HBN_RSV1,tmp[10]); + BL_WR_REG(HBN_BASE,HBN_RSV2,tmp[11]); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Disable HBN mode + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Disable(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(HBN_BASE,HBN_CTL); + /* Disable HBN mode */ + tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_MODE); + BL_WR_REG(HBN_BASE,HBN_CTL,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Enable HBN PIR + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_PIR_Enable(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(HBN_BASE,HBN_PIR_CFG); + tmpVal=BL_SET_REG_BIT(tmpVal,HBN_PIR_EN); + BL_WR_REG(HBN_BASE,HBN_PIR_CFG,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Disable HBN PIR + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_PIR_Disable(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(HBN_BASE,HBN_PIR_CFG); + tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_PIR_EN); + BL_WR_REG(HBN_BASE,HBN_PIR_CFG,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Config HBN PIR interrupt + * + * @param pirIntCfg: HBN PIR interrupt configuration + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type* pirIntCfg) +{ + uint32_t tmpVal; + uint32_t bit4 = 0; + uint32_t bit5 = 0; + uint32_t bitVal = 0; + + tmpVal=BL_RD_REG(HBN_BASE,HBN_PIR_CFG); + + /* low trigger interrupt */ + if(pirIntCfg->lowIntEn==ENABLE){ + bit5 = 0; + }else{ + bit5 = 1; + } + + /* high trigger interrupt */ + if(pirIntCfg->highIntEn==ENABLE){ + bit4 = 0; + }else{ + bit4 = 1; + } + + bitVal = bit4|(bit5<<1); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_PIR_DIS,bitVal); + BL_WR_REG(HBN_BASE,HBN_PIR_CFG,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Select HBN PIR low pass filter + * + * @param lpf: HBN PIR low pass filter selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_PIR_LPF_TYPE(lpf)); + + tmpVal=BL_RD_REG(HBN_BASE,HBN_PIR_CFG); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_PIR_LPF_SEL,lpf); + BL_WR_REG(HBN_BASE,HBN_PIR_CFG,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Select HBN PIR high pass filter + * + * @param hpf: HBN PIR high pass filter selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_PIR_HPF_TYPE(hpf)); + + tmpVal=BL_RD_REG(HBN_BASE,HBN_PIR_CFG); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_PIR_HPF_SEL,hpf); + BL_WR_REG(HBN_BASE,HBN_PIR_CFG,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Set HBN PIR threshold value + * + * @param threshold: HBN PIR threshold value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold) +{ + uint32_t tmpVal; + + CHECK_PARAM((threshold<=0x3FFF)); + + tmpVal=BL_RD_REG(HBN_BASE,HBN_PIR_VTH); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_PIR_VTH,threshold); + BL_WR_REG(HBN_BASE,HBN_PIR_VTH,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Get HBN PIR threshold value + * + * @param None + * + * @return HBN PIR threshold value + * +*******************************************************************************/ +uint16_t HBN_Get_PIR_Threshold(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(HBN_BASE,HBN_PIR_VTH); + + return BL_GET_REG_BITS_VAL(tmpVal,HBN_PIR_VTH); +} + +/****************************************************************************//** + * @brief Set HBN PIR interval value + * + * @param interval: HBN PIR interval value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval) +{ + uint32_t tmpVal; + + CHECK_PARAM((interval<=0xFFF)); + + tmpVal=BL_RD_REG(HBN_BASE,HBN_PIR_INTERVAL); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_PIR_INTERVAL,interval); + BL_WR_REG(HBN_BASE,HBN_PIR_INTERVAL,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Get HBN PIR interval value + * + * @param None + * + * @return HBN PIR interval value + * +*******************************************************************************/ +uint16_t HBN_Get_PIR_Interval(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(HBN_BASE,HBN_PIR_INTERVAL); + + return BL_GET_REG_BITS_VAL(tmpVal,HBN_PIR_INTERVAL); +} + +/****************************************************************************//** + * @brief get HBN bor out state + * + * @param None + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type HBN_Get_BOR_OUT_State(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE,HBN_BOR_CFG),HBN_R_BOR_OUT)?SET:RESET; +} + +/****************************************************************************//** + * @brief set HBN bor config + * + * @param enable: ENABLE or DISABLE, if enable, Power up Brown Out Reset + * @param threshold: bor threshold + * @param mode: bor work mode with por + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_BOR_Config(uint8_t enable,HBN_BOR_THRES_Type threshold,HBN_BOR_MODE_Type mode) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_BOR_THRES_TYPE(threshold)); + CHECK_PARAM(IS_HBN_BOR_MODE_TYPE(mode)); + + tmpVal=BL_RD_REG(HBN_BASE,HBN_BOR_CFG); + if(enable){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_PU_BOR,1); + }else{ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_PU_BOR,0); + } + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_BOR_VTH,threshold); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_BOR_SEL,mode); + BL_WR_REG(HBN_BASE,HBN_BOR_CFG,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief HBN set ldo11aon voltage out + * + * @param ldoLevel: LDO volatge level + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + + tmpVal=BL_RD_REG(HBN_BASE,HBN_GLB); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_SW_LDO11_AON_VOUT_SEL,ldoLevel); + BL_WR_REG(HBN_BASE,HBN_GLB,tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief HBN set ldo11rt voltage out + * + * @param ldoLevel: LDO volatge level + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + + tmpVal=BL_RD_REG(HBN_BASE,HBN_GLB); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_SW_LDO11_RT_VOUT_SEL,ldoLevel); + BL_WR_REG(HBN_BASE,HBN_GLB,tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief HBN set ldo11soc voltage out + * + * @param ldoLevel: LDO volatge level + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + + tmpVal=BL_RD_REG(HBN_BASE,HBN_GLB); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_SW_LDO11SOC_VOUT_SEL_AON,ldoLevel); + BL_WR_REG(HBN_BASE,HBN_GLB,tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief HBN set ldo11 all voltage out + * + * @param ldoLevel: LDO volatge level + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + + tmpVal=BL_RD_REG(HBN_BASE,HBN_GLB); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_SW_LDO11_AON_VOUT_SEL,ldoLevel); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_SW_LDO11_RT_VOUT_SEL,ldoLevel); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_SW_LDO11SOC_VOUT_SEL_AON,ldoLevel); + BL_WR_REG(HBN_BASE,HBN_GLB,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief HBN select 32K + * + * @param clkType: HBN 32k clock type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION HBN_32K_Sel(HBN_32K_CLK_Type clkType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_HBN_32K_CLK_TYPE(clkType)); + + HBN_Trim_RC32K(); + + tmpVal=BL_RD_REG(HBN_BASE,HBN_GLB); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_F32K_SEL,clkType); + BL_WR_REG(HBN_BASE,HBN_GLB,tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief Select uart clock source + * + * @param clkSel: uart clock type selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel)); + + tmpVal=BL_RD_REG(HBN_BASE,HBN_GLB); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_UART_CLK_SEL,clkSel); + BL_WR_REG(HBN_BASE,HBN_GLB,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Select xclk clock source + * + * @param xClk: xclk clock type selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_HBN_XCLK_CLK_TYPE(xClk)); + + tmpVal=BL_RD_REG(HBN_BASE,HBN_GLB); + tmpVal2=BL_GET_REG_BITS_VAL(tmpVal,HBN_ROOT_CLK_SEL); + switch(xClk){ + case HBN_XCLK_CLK_RC32M: + tmpVal2&=(~(1<<0)); + break; + case HBN_XCLK_CLK_XTAL: + tmpVal2|=(1<<0); + break; + default : + break; + } + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_ROOT_CLK_SEL,tmpVal2); + BL_WR_REG(HBN_BASE,HBN_GLB,tmpVal); + HBN_CLK_SET_DUMMY_WAIT; + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Select root clk source + * + * @param rootClk: root clock type selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_HBN_ROOT_CLK_TYPE(rootClk)); + + tmpVal=BL_RD_REG(HBN_BASE,HBN_GLB); + tmpVal2=BL_GET_REG_BITS_VAL(tmpVal,HBN_ROOT_CLK_SEL); + switch(rootClk){ + case HBN_ROOT_CLK_RC32M: + tmpVal2=0x0; + break; + case HBN_ROOT_CLK_XTAL: + tmpVal2=0x1; + break; + case HBN_ROOT_CLK_PLL: + tmpVal2|=(1<<1); + break; + default : + break; + } + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_ROOT_CLK_SEL,tmpVal2); + BL_WR_REG(HBN_BASE,HBN_GLB,tmpVal); + HBN_CLK_SET_DUMMY_WAIT; + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief set HBN_RAM sleep mode + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_HRAM_slp(void) +{ + uint32_t tmpVal = 0; + + tmpVal=BL_RD_REG(HBN_BASE,HBN_SRAM); + tmpVal=BL_SET_REG_BIT(tmpVal,HBN_RETRAM_SLP); + tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_RETRAM_RET); + BL_WR_REG(HBN_BASE,HBN_SRAM,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief set HBN_RAM retension mode + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_HRAM_Ret(void) +{ + uint32_t tmpVal = 0; + + tmpVal=BL_RD_REG(HBN_BASE,HBN_SRAM); + tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_RETRAM_SLP); + tmpVal=BL_SET_REG_BIT(tmpVal,HBN_RETRAM_RET); + BL_WR_REG(HBN_BASE,HBN_SRAM,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Power on XTAL 32K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_Xtal_32K(void) +{ + uint32_t tmpVal = 0; + + tmpVal=BL_RD_REG(HBN_BASE,HBN_XTAL32K); + tmpVal=BL_SET_REG_BIT(tmpVal,HBN_PU_XTAL32K); + tmpVal=BL_SET_REG_BIT(tmpVal,HBN_PU_XTAL32K_BUF); + BL_WR_REG(HBN_BASE,HBN_XTAL32K,tmpVal); + + /* Delay >1s */ + BL602_Delay_US(1100); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief Power off XTAL 32K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_Xtal_32K(void) +{ + uint32_t tmpVal = 0; + + tmpVal=BL_RD_REG(HBN_BASE,HBN_XTAL32K); + tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_PU_XTAL32K); + tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_PU_XTAL32K_BUF); + BL_WR_REG(HBN_BASE,HBN_XTAL32K,tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief Power on RC32K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_RC32K(void) +{ + uint32_t tmpVal = 0; + + tmpVal=BL_RD_REG(HBN_BASE,HBN_GLB); + tmpVal=BL_SET_REG_BIT(tmpVal,HBN_PU_RC32K); + BL_WR_REG(HBN_BASE,HBN_GLB,tmpVal); + + /* Delay >800us */ + BL602_Delay_US(880); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Power off RC3K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_RC32K(void) +{ + uint32_t tmpVal = 0; + + tmpVal=BL_RD_REG(HBN_BASE,HBN_GLB); + tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_PU_RC32K); + BL_WR_REG(HBN_BASE,HBN_GLB,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Trim RC32K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION HBN_Trim_RC32K(void) +{ + Efuse_Ana_RC32K_Trim_Type trim; + int32_t tmpVal = 0; + + EF_Ctrl_Read_RC32K_Trim(&trim); + if(trim.trimRc32kExtCodeEn){ + if(trim.trimRc32kCodeFrExtParity==EF_Ctrl_Get_Trim_Parity(trim.trimRc32kCodeFrExt,10)){ + tmpVal=BL_RD_REG(HBN_BASE,HBN_RC32K_CTRL0); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_RC32K_CODE_FR_EXT,trim.trimRc32kCodeFrExt); + tmpVal=BL_SET_REG_BIT(tmpVal,HBN_RC32K_EXT_CODE_EN); + BL_WR_REG(HBN_BASE,HBN_RC32K_CTRL0,tmpVal); + BL602_Delay_US(2); + return SUCCESS; + } + } + + return ERROR; +} +#endif + +/****************************************************************************//** + * @brief Get HBN status flag + * + * @param None + * + * @return HBN status flag value + * +*******************************************************************************/ +uint32_t HBN_Get_Status_Flag(void) +{ + return BL_RD_REG(HBN_BASE,HBN_RSV0); +} + +/****************************************************************************//** + * @brief Set HBN status flag + * + * @param flag: Status Flag + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_Status_Flag(uint32_t flag) +{ + BL_WR_REG(HBN_BASE,HBN_RSV0,flag); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Get HBN wakeup address + * + * @param None + * + * @return HBN wakeup address + * +*******************************************************************************/ +uint32_t HBN_Get_Wakeup_Addr(void) +{ + return BL_RD_REG(HBN_BASE,HBN_RSV1); +} + +/****************************************************************************//** + * @brief Set HBN wakeup address + * + * @param addr: HBN wakeup address + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr) +{ + BL_WR_REG(HBN_BASE,HBN_RSV1,addr); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief HBN clear RTC timer counter + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Clear_RTC_Counter(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(HBN_BASE,HBN_CTL); + /* Clear RTC control bit0 */ + BL_WR_REG(HBN_BASE,HBN_CTL,tmpVal&0xfffffffe); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief HBN clear RTC timer counter + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Enable_RTC_Counter(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(HBN_BASE,HBN_CTL); + /* Set RTC control bit0 */ + BL_WR_REG(HBN_BASE,HBN_CTL,tmpVal|0x01); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief HBN set RTC timer configuration + * + * @param delay: RTC interrupt delay 32 clocks + * @param compValLow: RTC interrupt commpare value low 32 bits + * @param compValHigh: RTC interrupt commpare value high 32 bits + * @param compMode: RTC interrupt commpare + * mode:HBN_RTC_COMP_BIT0_39,HBN_RTC_COMP_BIT0_23,HBN_RTC_COMP_BIT13_39 + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay,uint32_t compValLow,uint32_t compValHigh,uint8_t compMode) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_HBN_RTC_INT_DELAY_TYPE(delay)); + + BL_WR_REG(HBN_BASE,HBN_TIME_L,compValLow); + BL_WR_REG(HBN_BASE,HBN_TIME_H,compValHigh&0xff); + + tmpVal=BL_RD_REG(HBN_BASE,HBN_CTL); + /* Set interrupt delay option */ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_RTC_DLY_OPTION,delay); + /* Set RTC compare mode */ + tmpVal |= (compMode<<1); + BL_WR_REG(HBN_BASE,HBN_CTL,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief HBN get RTC timer count value + * + * @param valLow: RTC count value pointer for low 32 bits + * @param valHigh: RTC count value pointer for high 8 bits + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow,uint32_t *valHigh) +{ + uint32_t tmpVal; + + /* Tigger RTC val read */ + tmpVal=BL_RD_REG(HBN_BASE,HBN_RTC_TIME_H); + tmpVal=BL_SET_REG_BIT(tmpVal,HBN_RTC_TIME_LATCH); + BL_WR_REG(HBN_BASE,HBN_RTC_TIME_H,tmpVal); + tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_RTC_TIME_LATCH); + BL_WR_REG(HBN_BASE,HBN_RTC_TIME_H,tmpVal); + + /* Read RTC val */ + *valLow=BL_RD_REG(HBN_BASE,HBN_RTC_TIME_L); + *valHigh=(BL_RD_REG(HBN_BASE,HBN_RTC_TIME_H)&0xff); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief HBN clear RTC timer interrupt,this function must be called to clear delayed rtc IRQ + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Clear_RTC_INT(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(HBN_BASE,HBN_CTL); + /* Clear RTC commpare:bit1-3 for clearing Delayed RTC IRQ */ + BL_WR_REG(HBN_BASE,HBN_CTL,tmpVal&0xfffffff1); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief HBN enable GPIO interrupt + * + * @param gpioIntTrigType: HBN GPIO interrupt trigger type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_HBN_GPIO_INT_TRIGGER_TYPE(gpioIntTrigType)); + + tmpVal=BL_RD_REG(HBN_BASE,HBN_IRQ_MODE); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_PIN_WAKEUP_MODE,gpioIntTrigType); + BL_WR_REG(HBN_BASE,HBN_IRQ_MODE,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief HBN disable GPIO interrupt + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_GPIO_INT_Disable(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(HBN_BASE,HBN_IRQ_MODE); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_PIN_WAKEUP_MASK,0); + BL_WR_REG(HBN_BASE,HBN_IRQ_MODE,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief HBN get interrupt status + * + * @param irqType: HBN interrupt type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + + tmpVal=BL_RD_REG(HBN_BASE,HBN_IRQ_STAT); + + if(tmpVal&(1<=1)&&(dlySec<=7))); + + tmpVal=BL_RD_REG(HBN_BASE,HBN_IRQ_MODE); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_PIN_WAKEUP_EN,dlyEn); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_PIN_WAKEUP_SEL,dlySec); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_REG_EN_HW_PU_PD,pupdEn); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_REG_AON_PAD_IE_SMT,iesmtEn); + BL_WR_REG(HBN_BASE,HBN_IRQ_MODE,tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief Set Embedded Flash Pullup enabe or disable + * + * @param enable: Enable or disable + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Embedded_Flash_Pullup(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal=BL_RD_REG(HBN_BASE,HBN_RSV3); + + enable=(!enable); + tmpVal=((tmpVal&0xfffffffe)|(enable&0x01)); + + BL_WR_REG(HBN_BASE,HBN_RSV3,tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief Set Embedded Flash Pullup enabe or disable + * + * @param cfg: Enable or disable + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_BOR_Cfg(HBN_BOR_CFG_Type *cfg) +{ + uint32_t tmpVal = 0; + + if(cfg->enableBorInt){ + HBN_Enable_BOR_IRQ(); + }else{ + HBN_Disable_BOR_IRQ(); + } + + tmpVal=BL_RD_REG(HBN_BASE,HBN_BOR_CFG); + + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_BOR_VTH,cfg->borThreshold); + if(cfg->enablePorInBor){ + tmpVal=BL_SET_REG_BIT(tmpVal,HBN_BOR_SEL); + }else{ + tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_BOR_SEL); + } + + if(cfg->enableBor){ + tmpVal=BL_SET_REG_BIT(tmpVal,HBN_PU_BOR); + }else{ + tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_PU_BOR); + } + + BL_WR_REG(HBN_BASE,HBN_BOR_CFG,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief HBN OUT0 interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void HBN_OUT0_IRQHandler(void) +{ + /* GPIO7 GPIO8 and RTC */ + if(SET==HBN_Get_INT_State(HBN_INT_GPIO7)){ + /* gpio7 sync/async mode */ + HBN_Clear_IRQ(HBN_INT_GPIO7); + if(hbnInt0CbfArra[HBN_OUT0_INT_GPIO7] != NULL) { + hbnInt0CbfArra[HBN_OUT0_INT_GPIO7](); + } + } + if(SET==HBN_Get_INT_State(HBN_INT_GPIO8)){ + /* gpio8 sync/async mode */ + HBN_Clear_IRQ(HBN_INT_GPIO8); + if(hbnInt0CbfArra[HBN_OUT0_INT_GPIO8] != NULL) { + hbnInt0CbfArra[HBN_OUT0_INT_GPIO8](); + } + } + if(SET==HBN_Get_INT_State(HBN_INT_RTC)){ + HBN_Clear_IRQ(HBN_INT_RTC); + HBN_Clear_RTC_INT(); + if(hbnInt0CbfArra[HBN_OUT0_INT_RTC] != NULL) { + hbnInt0CbfArra[HBN_OUT0_INT_RTC](); + } + } +} +#endif + +/****************************************************************************//** + * @brief HBN OUT1 interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void HBN_OUT1_IRQHandler(void) +{ + /* PIR */ + if(SET==HBN_Get_INT_State(HBN_INT_PIR)){ + HBN_Clear_IRQ(HBN_INT_PIR); + if(hbnInt1CbfArra[HBN_OUT1_INT_PIR] != NULL) { + hbnInt1CbfArra[HBN_OUT1_INT_PIR](); + } + } + /* BOR */ + if(SET==HBN_Get_INT_State(HBN_INT_BOR)){ + HBN_Clear_IRQ(HBN_INT_BOR); + if(hbnInt1CbfArra[HBN_OUT1_INT_BOR] != NULL) { + hbnInt1CbfArra[HBN_OUT1_INT_BOR](); + } + } + /* ACOMP0 */ + if(SET==HBN_Get_INT_State(HBN_INT_ACOMP0)){ + HBN_Clear_IRQ(HBN_INT_ACOMP0); + if(hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0] != NULL) { + hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0](); + } + } + /* ACOMP1 */ + if(SET==HBN_Get_INT_State(HBN_INT_ACOMP1)){ + HBN_Clear_IRQ(HBN_INT_ACOMP1); + if(hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1] != NULL) { + hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1](); + } + } +} +#endif + + +/*@} end of group HBN_Public_Functions */ + +/*@} end of group HBN */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/bl602_driver/std_drv/src/bl602_i2c.c b/drivers/bl602_driver/std_drv/src/bl602_i2c.c new file mode 100644 index 00000000..bee09b30 --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_i2c.c @@ -0,0 +1,749 @@ +/** + ****************************************************************************** + * @file bl602_i2c.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_i2c.h" +#include "bl602_glb.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @defgroup I2C_Private_Macros + * @{ + */ +#define I2C_FIFO_STATUS_TIMEOUT (160*1000*2) +#define PUT_UINT32_LE(n,b,i) \ +{ \ + (b)[(i) ] = (uint8_t) ( (n) ); \ + (b)[(i) + 1] = (uint8_t) ( (n) >> 8 ); \ + (b)[(i) + 2] = (uint8_t) ( (n) >> 16 ); \ + (b)[(i) + 3] = (uint8_t) ( (n) >> 24 ); \ +} + +/*@} end of group I2C_Private_Macros */ + +/** @defgroup I2C_Private_Types + * @{ + */ + +/*@} end of group I2C_Private_Types */ + +/** @defgroup I2C_Private_Variables + * @{ + */ +intCallback_Type * i2cIntCbfArra[I2C_ID_MAX][I2C_INT_ALL]= {{NULL}}; + +/*@} end of group I2C_Private_Variables */ + +/** @defgroup I2C_Global_Variables + * @{ + */ + +/*@} end of group I2C_Global_Variables */ + +/** @defgroup I2C_Private_Fun_Declaration + * @{ + */ + +/*@} end of group I2C_Private_Fun_Declaration */ + +/** @defgroup I2C_Private_Functions + * @{ + */ + +/****************************************************************************//** + * @brief I2C interrupt handler + * + * @param i2cNo: I2C ID type + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +static void I2C_IntHandler(I2C_ID_Type i2cNo) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS); + if(BL_IS_REG_BIT_SET(tmpVal,I2C_END_INT)){ + if(i2cIntCbfArra[i2cNo][I2C_TRANS_END_INT] != NULL){ + /* Call the callback function */ + i2cIntCbfArra[i2cNo][I2C_TRANS_END_INT](); + } + } + if(BL_IS_REG_BIT_SET(tmpVal,I2C_TXF_INT)){ + if(i2cIntCbfArra[i2cNo][I2C_TX_FIFO_READY_INT] != NULL){ + /* Call the callback function */ + i2cIntCbfArra[i2cNo][I2C_TX_FIFO_READY_INT](); + } + } + if(BL_IS_REG_BIT_SET(tmpVal,I2C_RXF_INT)){ + if(i2cIntCbfArra[i2cNo][I2C_RX_FIFO_READY_INT] != NULL){ + /* Call the callback function */ + i2cIntCbfArra[i2cNo][I2C_RX_FIFO_READY_INT](); + } + } + if(BL_IS_REG_BIT_SET(tmpVal,I2C_NAK_INT)){ + if(i2cIntCbfArra[i2cNo][I2C_NACK_RECV_INT] != NULL){ + /* Call the callback function */ + i2cIntCbfArra[i2cNo][I2C_NACK_RECV_INT](); + } + } + if(BL_IS_REG_BIT_SET(tmpVal,I2C_ARB_INT)){ + if(i2cIntCbfArra[i2cNo][I2C_ARB_LOST_INT] != NULL){ + /* Call the callback function */ + i2cIntCbfArra[i2cNo][I2C_ARB_LOST_INT](); + } + } + if(BL_IS_REG_BIT_SET(tmpVal,I2C_FER_INT)){ + if(i2cIntCbfArra[i2cNo][I2C_FIFO_ERR_INT] != NULL){ + /* Call the callback function */ + i2cIntCbfArra[i2cNo][I2C_FIFO_ERR_INT](); + } + } +} +#endif + +/*@} end of group I2C_Private_Functions */ + +/** @defgroup I2C_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief I2C write word data + * + * @param i2cNo: I2C ID type + * @param data: Data word + * + * @return None + * +*******************************************************************************/ +void I2C_SendWord(I2C_ID_Type i2cNo, uint32_t data) +{ + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + BL_WR_REG(I2Cx, I2C_FIFO_WDATA, data); +} + +/****************************************************************************//** + * @brief I2C read word data + * + * @param i2cNo: I2C ID type + * + * @return word data + * +*******************************************************************************/ +uint32_t I2C_RecieveWord(I2C_ID_Type i2cNo) +{ + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + return BL_RD_REG(I2Cx, I2C_FIFO_RDATA); +} + +/****************************************************************************//** + * @brief I2C enable + * + * @param i2cNo: I2C ID type + * + * @return None + * +*******************************************************************************/ +void I2C_Enable(I2C_ID_Type i2cNo) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + tmpVal = BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_RX_FIFO_CLR); + BL_WR_REG(I2Cx, I2C_FIFO_CONFIG_0, tmpVal); + + tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_M_EN); + + BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); +} + +/****************************************************************************//** + * @brief I2C disable + * + * @param i2cNo: I2C ID type + * + * @return None + * +*******************************************************************************/ +void I2C_Disable(I2C_ID_Type i2cNo) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_M_EN); + BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); + + /* Clear I2C fifo */ + tmpVal = BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_TX_FIFO_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_RX_FIFO_CLR); + BL_WR_REG(I2Cx, I2C_FIFO_CONFIG_0, tmpVal); + + /* Clear I2C interrupt status */ + tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_CLR); + BL_WR_REG(I2Cx, I2C_INT_STS, tmpVal); +} + +/****************************************************************************//** + * @brief I2C set global reset function + * + * @param i2cNo: I2C ID type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type I2C_Reset(I2C_ID_Type i2cNo) +{ + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_I2C); + return SUCCESS; +} + +/****************************************************************************//** + * @brief I2C init function + * + * @param i2cNo: I2C ID type + * @param direct: I2C read or write direct + * @param cfg: I2C transfer config struct + * + * @return None + * +*******************************************************************************/ +void I2C_Init(I2C_ID_Type i2cNo, I2C_Direction_Type direct, I2C_Transfer_Cfg *cfg) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + /* I2C write config */ + tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); + if(direct == I2C_WRITE){ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_PKT_DIR); + }else{ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_PKT_DIR); + } + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_SLV_ADDR, cfg->slaveAddr); + if(cfg->subAddrSize > 0){ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_SUB_ADDR_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_SUB_ADDR_BC, cfg->subAddrSize-1); + }else{ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_SUB_ADDR_EN); + } + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PKT_LEN, cfg->dataSize-1); + BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); + + /* Set sub address */ + BL_WR_REG(I2Cx, I2C_SUB_ADDR, cfg->subAddr); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(I2C_IRQn,I2C_IRQHandler); +#endif +} + +/****************************************************************************//** + * @brief Set i2c prd + * + * @param i2cNo: I2C ID type + * @param phase: I2C phase value + * + * @return None + * +*******************************************************************************/ +void I2C_SetPrd(I2C_ID_Type i2cNo, uint8_t phase) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + //phase_cycles = (32000000 / phase / 4) - 1; + tmpVal = BL_RD_REG(I2Cx, I2C_PRD_START); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_0, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_1, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_2, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_3, phase); + BL_WR_REG(I2Cx, I2C_PRD_START, tmpVal); + tmpVal = BL_RD_REG(I2Cx, I2C_PRD_STOP); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_0, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_1, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_2, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_3, phase); + BL_WR_REG(I2Cx, I2C_PRD_STOP, tmpVal); + tmpVal = BL_RD_REG(I2Cx, I2C_PRD_DATA); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_0, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_1, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_2, phase); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_3, phase); + BL_WR_REG(I2Cx, I2C_PRD_DATA, tmpVal); +} + +/****************************************************************************//** + * @brief I2C set scl output clock + * + * @param i2cNo: I2C ID type + * @param clk: Clock set + * + * @return None + * +*******************************************************************************/ +void I2C_ClockSet(I2C_ID_Type i2cNo, uint32_t clk) +{ + uint8_t bclkDiv = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + bclkDiv = GLB_Get_BCLK_Div(); + if(clk >= 100000){ + GLB_Set_I2C_CLK(1, 0); + I2C_SetPrd(i2cNo, (SystemCoreClockGet()/(bclkDiv+1)) / (clk*4)-1); + }else if(clk >= 8000){ + GLB_Set_I2C_CLK(1, 9); + I2C_SetPrd(i2cNo, ((SystemCoreClockGet()/(bclkDiv+1))/10) / (clk*4)-1); + }else if(clk >= 800){ + GLB_Set_I2C_CLK(1, 99); + I2C_SetPrd(i2cNo, ((SystemCoreClockGet()/(bclkDiv+1))/100) / (clk*4)-1); + }else{ + GLB_Set_I2C_CLK(1, 255); + I2C_SetPrd(i2cNo, ((SystemCoreClockGet()/(bclkDiv+1))/256) / (clk*4)-1); + } + + /* Disable i2c scl sync to get current i2c clock */ + I2C_SetSclSync(i2cNo, 0); +} + +/****************************************************************************//** + * @brief I2C set scl sync + * + * @param i2cNo: I2C ID type + * @param enable: Enable or disable I2C scl sync + * + * @return None + * +*******************************************************************************/ +void I2C_SetSclSync(I2C_ID_Type i2cNo, uint8_t enable) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); + if(enable){ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_SCL_SYNC_EN); + }else{ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_SCL_SYNC_EN); + } + BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); +} + +/****************************************************************************//** + * @brief Get i2c busy state + * + * @param i2cNo: I2C ID type + * + * @return RESET or SET + * +*******************************************************************************/ +BL_Sts_Type I2C_IsBusy(I2C_ID_Type i2cNo) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS); + return ((BL_IS_REG_BIT_SET(tmpVal, I2C_END_INT)) ? RESET: SET); +} + +/****************************************************************************//** + * @brief I2C master write block data + * + * @param i2cNo: I2C ID type + * @param cfg: I2C transfer config struct + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type I2C_MasterSendBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg) +{ + uint8_t i; + uint32_t timeOut = 0; + uint32_t temp = 0; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + I2C_Disable(i2cNo); + I2C_Init(i2cNo, I2C_WRITE, cfg); + I2C_Enable(i2cNo); + + /* Set I2C write data */ + for(i=0; idataSize; i++){ + temp += (cfg->data[i] << ((i % 4) * 8)); + if((i + 1) % 4 == 0){ + timeOut = I2C_FIFO_STATUS_TIMEOUT; + while(BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_TX_FIFO_CNT) == 0){ + timeOut--; + if(timeOut == 0){ + I2C_Disable(i2cNo); + return TIMEOUT; + } + } + BL_WR_REG(I2Cx, I2C_FIFO_WDATA, temp); + temp = 0; + } + } + if((cfg->dataSize%4) != 0){ + timeOut = I2C_FIFO_STATUS_TIMEOUT; + while(BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_TX_FIFO_CNT) == 0){ + timeOut--; + if(timeOut == 0){ + I2C_Disable(i2cNo); + return TIMEOUT; + } + } + BL_WR_REG(I2Cx, I2C_FIFO_WDATA, temp); + } + + timeOut = I2C_FIFO_STATUS_TIMEOUT; + while(I2C_IsBusy(i2cNo)){ + timeOut--; + if(timeOut == 0){ + I2C_Disable(i2cNo); + return TIMEOUT; + } + } + + I2C_Disable(i2cNo); + return SUCCESS; +} + +/****************************************************************************//** + * @brief I2C master read block data + * + * @param i2cNo: I2C ID type + * @param cfg: I2C transfer config struct + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type I2C_MasterReceiveBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg) +{ + uint8_t i = 0; + uint32_t timeOut = 0; + uint32_t temp = 0; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + + I2C_Disable(i2cNo); + I2C_Init(i2cNo, I2C_READ, cfg); + I2C_Enable(i2cNo); + + /* Read I2C data */ + while(cfg->dataSize - i >= 4){ + timeOut = I2C_FIFO_STATUS_TIMEOUT; + while(BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_RX_FIFO_CNT) == 0){ + timeOut--; + if(timeOut == 0){ + I2C_Disable(i2cNo); + return TIMEOUT; + } + } + temp = BL_RD_REG(I2Cx, I2C_FIFO_RDATA); + PUT_UINT32_LE(temp, cfg->data, i); + i += 4; + } + if(i < cfg->dataSize){ + timeOut = I2C_FIFO_STATUS_TIMEOUT; + while(BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_RX_FIFO_CNT) == 0){ + timeOut--; + if(timeOut == 0){ + I2C_Disable(i2cNo); + return TIMEOUT; + } + } + temp = BL_RD_REG(I2Cx, I2C_FIFO_RDATA); + while(i < cfg->dataSize){ + cfg->data[i] = (temp & 0xff); + temp = (temp >> 8); + i ++; + } + } + + timeOut = I2C_FIFO_STATUS_TIMEOUT; + while(I2C_IsBusy(i2cNo)){ + timeOut--; + if(timeOut == 0){ + I2C_Disable(i2cNo); + return TIMEOUT; + } + } + + I2C_Disable(i2cNo); + return SUCCESS; +} + +/****************************************************************************//** + * @brief Mask/Unmask the I2C interrupt + * + * @param i2cNo: I2C ID type + * @param intType: Specifies the interrupt type + * @param intMask: Enable/Disable Specified interrupt type + * + * @return None + * +*******************************************************************************/ +void I2C_IntMask(I2C_ID_Type i2cNo, I2C_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + uint32_t I2Cx = I2C_BASE; + + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + CHECK_PARAM(IS_I2C_INT_TYPE(intType)); + CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); + + tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS); + switch(intType) + { + case I2C_TRANS_END_INT: + if(intMask == UNMASK) + { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK); + } + else + { + /* MASK(Disable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK); + } + break; + case I2C_TX_FIFO_READY_INT: + if(intMask == UNMASK) + { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK); + } + else + { + /* MASK(Disable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK); + } + break; + case I2C_RX_FIFO_READY_INT: + if(intMask == UNMASK) + { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK); + } + else + { + /* MASK(Disable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK); + } + break; + case I2C_NACK_RECV_INT: + if(intMask == UNMASK) + { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK); + } + else + { + /* MASK(Disable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK); + } + break; + case I2C_ARB_LOST_INT: + if(intMask == UNMASK) + { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK); + } + else + { + /* MASK(Disable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK); + } + break; + case I2C_FIFO_ERR_INT: + if(intMask == UNMASK) + { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK); + } + else + { + /* MASK(Disable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK); + } + break; + case I2C_INT_ALL: + if(intMask == UNMASK) + { + /* UNMASK(Enable) this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK); + } + else + { + /* MASK(Disable) this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK); + } + break; + + default: + break; + } + BL_WR_REG(I2Cx, I2C_INT_STS, tmpVal); +} + +/****************************************************************************//** + * @brief Install I2C interrupt callback function + * + * @param i2cNo: I2C ID type + * @param intType: Specifies the interrupt type + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void I2C_Int_Callback_Install(I2C_ID_Type i2cNo, I2C_INT_Type intType, intCallback_Type* cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); + CHECK_PARAM(IS_I2C_INT_TYPE(intType)); + + i2cIntCbfArra[i2cNo][intType] = cbFun; +} +#endif + +/****************************************************************************//** + * @brief I2C IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void I2C_IRQHandler(void) +{ + I2C_IntHandler(I2C0_ID); +} +#endif + + +/*@} end of group I2C_Public_Functions */ + +/*@} end of group I2C */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/bl602_driver/std_drv/src/bl602_ir.c b/drivers/bl602_driver/std_drv/src/bl602_ir.c new file mode 100644 index 00000000..78fadfc9 --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_ir.c @@ -0,0 +1,1137 @@ +/** + ****************************************************************************** + * @file bl602_ir.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_ir.h" +#include "bl602_glb.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup IR + * @{ + */ + +/** @defgroup IR_Private_Macros + * @{ + */ +#define NEC_HEAD_H_MIN 17000 +#define NEC_HEAD_H_MAX 19000 +#define NEC_HEAD_L_MIN 8400 +#define NEC_HEAD_L_MAX 9600 +#define NEC_BIT0_H_MIN 525 +#define NEC_BIT0_H_MAX 1725 +#define RC5_ONE_PLUSE_MIN 1175 +#define RC5_ONE_PLUSE_MAX 2375 +#define RC5_TWO_PLUSE_MIN 2955 +#define RC5_TWO_PLUSE_MAX 4155 +#define IR_TX_INT_TIMEOUT_COUNT (100*160*1000) +#define IR_RX_INT_TIMEOUT_COUNT (100*160*1000) + +/*@} end of group IR_Private_Macros */ + +/** @defgroup IR_Private_Types + * @{ + */ + +/*@} end of group IR_Private_Types */ + +/** @defgroup IR_Private_Variables + * @{ + */ +static intCallback_Type * irIntCbfArra[IR_INT_ALL]= {NULL,NULL}; + + +/*@} end of group IR_Private_Variables */ + +/** @defgroup IR_Global_Variables + * @{ + */ + +/*@} end of group IR_Global_Variables */ + +/** @defgroup IR_Private_Fun_Declaration + * @{ + */ + +/*@} end of group IR_Private_Fun_Declaration */ + +/** @defgroup IR_Private_Functions + * @{ + */ + +/*@} end of group IR_Private_Functions */ + +/** @defgroup IR_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief IR RX IRQ handler function + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void IRRX_IRQHandler(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(IR_BASE,IRRX_INT_STS); + if(BL_IS_REG_BIT_SET(tmpVal,IRRX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal,IR_CR_IRRX_END_MASK)){ + BL_WR_REG(IR_BASE,IRRX_INT_STS,BL_SET_REG_BIT(tmpVal,IR_CR_IRRX_END_CLR)); + if(irIntCbfArra[IR_INT_RX] != NULL){ + irIntCbfArra[IR_INT_RX](); + } + } +} +#endif + +/****************************************************************************//** + * @brief IR TX IRQ handler function + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void IRTX_IRQHandler(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(IR_BASE,IRTX_INT_STS); + if(BL_IS_REG_BIT_SET(tmpVal,IRTX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal,IR_CR_IRTX_END_MASK)){ + BL_WR_REG(IR_BASE,IRTX_INT_STS,BL_SET_REG_BIT(tmpVal,IR_CR_IRTX_END_CLR)); + if(irIntCbfArra[IR_INT_TX] != NULL){ + irIntCbfArra[IR_INT_TX](); + } + } +} +#endif + +/****************************************************************************//** + * @brief IR tx initialization function + * + * @param irTxCfg: IR tx configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_TxInit(IR_TxCfg_Type *irTxCfg) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(IR_BASE,IRTX_CONFIG); + /* Set data bit */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRTX_DATA_NUM,irTxCfg->dataBits-1); + /* Set tail pulse */ + ENABLE == irTxCfg->tailPulseInverse ? (tmpVal=BL_SET_REG_BIT(tmpVal,IR_CR_IRTX_TAIL_HL_INV)):(tmpVal=BL_CLR_REG_BIT(tmpVal,IR_CR_IRTX_TAIL_HL_INV)); + ENABLE == irTxCfg->tailPulse ? (tmpVal=BL_SET_REG_BIT(tmpVal,IR_CR_IRTX_TAIL_EN)):(tmpVal=BL_CLR_REG_BIT(tmpVal,IR_CR_IRTX_TAIL_EN)); + /* Set head pulse */ + ENABLE == irTxCfg->headPulseInverse ? (tmpVal=BL_SET_REG_BIT(tmpVal,IR_CR_IRTX_HEAD_HL_INV)):(tmpVal=BL_CLR_REG_BIT(tmpVal,IR_CR_IRTX_HEAD_HL_INV)); + ENABLE == irTxCfg->headPulse ? (tmpVal=BL_SET_REG_BIT(tmpVal,IR_CR_IRTX_HEAD_EN)):(tmpVal=BL_CLR_REG_BIT(tmpVal,IR_CR_IRTX_HEAD_EN)); + /* Enable or disable logic 1 and 0 pulse inverse */ + ENABLE == irTxCfg->logic1PulseInverse ? (tmpVal=BL_SET_REG_BIT(tmpVal,IR_CR_IRTX_LOGIC1_HL_INV)):(tmpVal=BL_CLR_REG_BIT(tmpVal,IR_CR_IRTX_LOGIC1_HL_INV)); + ENABLE == irTxCfg->logic0PulseInverse ? (tmpVal=BL_SET_REG_BIT(tmpVal,IR_CR_IRTX_LOGIC0_HL_INV)):(tmpVal=BL_CLR_REG_BIT(tmpVal,IR_CR_IRTX_LOGIC0_HL_INV)); + /* Enable or disable data pulse */ + ENABLE == irTxCfg->dataPulse ? (tmpVal=BL_SET_REG_BIT(tmpVal,IR_CR_IRTX_DATA_EN)):(tmpVal=BL_CLR_REG_BIT(tmpVal,IR_CR_IRTX_DATA_EN)); + /* Enable or disable output modulation */ + ENABLE == irTxCfg->outputModulation ? (tmpVal=BL_SET_REG_BIT(tmpVal,IR_CR_IRTX_MOD_EN)):(tmpVal=BL_CLR_REG_BIT(tmpVal,IR_CR_IRTX_MOD_EN)); + /* Enable or disable output inverse */ + ENABLE == irTxCfg->outputInverse ? (tmpVal=BL_SET_REG_BIT(tmpVal,IR_CR_IRTX_OUT_INV)):(tmpVal=BL_CLR_REG_BIT(tmpVal,IR_CR_IRTX_OUT_INV)); + + /* Write back */ + BL_WR_REG(IR_BASE,IRTX_CONFIG,tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(IRTX_IRQn,IRTX_IRQHandler); +#endif + return SUCCESS; +} + +/****************************************************************************//** + * @brief IR tx pulse width configure function + * + * @param irTxPulseWidthCfg: IR tx pulse width configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_TxPulseWidthConfig(IR_TxPulseWidthCfg_Type *irTxPulseWidthCfg) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(IR_BASE,IRTX_PW); + /* Set logic 0 pulse phase 0 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRTX_LOGIC0_PH0_W,irTxPulseWidthCfg->logic0PulseWidth_0-1); + /* Set logic 0 pulse phase 1 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRTX_LOGIC0_PH1_W,irTxPulseWidthCfg->logic0PulseWidth_1-1); + /* Set logic 1 pulse phase 0 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRTX_LOGIC1_PH0_W,irTxPulseWidthCfg->logic1PulseWidth_0-1); + /* Set logic 1 pulse phase 1 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRTX_LOGIC1_PH1_W,irTxPulseWidthCfg->logic1PulseWidth_1-1); + /* Set head pulse phase 0 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRTX_HEAD_PH0_W,irTxPulseWidthCfg->headPulseWidth_0-1); + /* Set head pulse phase 1 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRTX_HEAD_PH1_W,irTxPulseWidthCfg->headPulseWidth_1-1); + /* Set tail pulse phase 0 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRTX_TAIL_PH0_W,irTxPulseWidthCfg->tailPulseWidth_0-1); + /* Set tail pulse phase 1 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRTX_TAIL_PH1_W,irTxPulseWidthCfg->tailPulseWidth_1-1); + BL_WR_REG(IR_BASE,IRTX_PW,tmpVal); + + tmpVal = BL_RD_REG(IR_BASE,IRTX_PULSE_WIDTH); + /* Set modulation phase 0 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRTX_MOD_PH0_W,irTxPulseWidthCfg->moduWidth_0-1); + /* Set modulation phase 1 width */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRTX_MOD_PH1_W,irTxPulseWidthCfg->moduWidth_1-1); + /* Set pulse width unit */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRTX_PW_UNIT,irTxPulseWidthCfg->pulseWidthUnit-1); + BL_WR_REG(IR_BASE,IRTX_PULSE_WIDTH,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief IR tx software mode pulse width(multiples of pulse width unit) configure function + * + * @param irTxSWMPulseWidthCfg: IR tx software mode pulse width configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_TxSWMPulseWidthConfig(IR_TxSWMPulseWidthCfg_Type *irTxSWMPulseWidthCfg) +{ + /* Set swm pulse width,multiples of pulse width unit */ + BL_WR_REG(IR_BASE,IRTX_SWM_PW_0,irTxSWMPulseWidthCfg->swmData0); + BL_WR_REG(IR_BASE,IRTX_SWM_PW_1,irTxSWMPulseWidthCfg->swmData1); + BL_WR_REG(IR_BASE,IRTX_SWM_PW_2,irTxSWMPulseWidthCfg->swmData2); + BL_WR_REG(IR_BASE,IRTX_SWM_PW_3,irTxSWMPulseWidthCfg->swmData3); + BL_WR_REG(IR_BASE,IRTX_SWM_PW_4,irTxSWMPulseWidthCfg->swmData4); + BL_WR_REG(IR_BASE,IRTX_SWM_PW_5,irTxSWMPulseWidthCfg->swmData5); + BL_WR_REG(IR_BASE,IRTX_SWM_PW_6,irTxSWMPulseWidthCfg->swmData6); + BL_WR_REG(IR_BASE,IRTX_SWM_PW_7,irTxSWMPulseWidthCfg->swmData7); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief IR rx initialization function + * + * @param irRxCfg: IR rx configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_RxInit(IR_RxCfg_Type *irRxCfg) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_RXMODE_TYPE(irRxCfg->rxMode)); + + tmpVal = BL_RD_REG(IR_BASE,IRRX_CONFIG); + /* Set rx mode */ + switch(irRxCfg->rxMode) + { + case IR_RX_NEC: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRRX_MODE,0x0); + break; + case IR_RX_RC5: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRRX_MODE,0x1); + break; + case IR_RX_SWM: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRRX_MODE,0x2); + break; + default: + break; + } + /* Enable or disable input inverse */ + ENABLE == irRxCfg->inputInverse ? (tmpVal=BL_SET_REG_BIT(tmpVal,IR_CR_IRRX_IN_INV)):(tmpVal=BL_CLR_REG_BIT(tmpVal,IR_CR_IRRX_IN_INV)); + /* Enable or disable rx input de-glitch function */ + ENABLE == irRxCfg->rxDeglitch ? (tmpVal=BL_SET_REG_BIT(tmpVal,IR_CR_IRRX_DEG_EN)):(tmpVal=BL_CLR_REG_BIT(tmpVal,IR_CR_IRRX_DEG_EN)); + /* Set de-glitch function cycle count */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRRX_DEG_CNT,irRxCfg->DeglitchCnt); + /* Write back */ + BL_WR_REG(IR_BASE,IRRX_CONFIG,tmpVal); + + tmpVal = BL_RD_REG(IR_BASE,IRRX_PW_CONFIG); + /* Set pulse width threshold to trigger end condition */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRRX_END_TH,irRxCfg->endThreshold-1); + /* Set pulse width threshold for logic0/1 detection */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRRX_DATA_TH,irRxCfg->dataThreshold-1); + /* Write back */ + BL_WR_REG(IR_BASE,IRRX_PW_CONFIG,tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(IRRX_IRQn,IRRX_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************//** + * @brief IR set default value of all registers function + * + * @param None + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_DeInit(void) +{ + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_IRR); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief IR enable function + * + * @param direct: IR direction type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_Enable(IR_Direction_Type direct) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_DIRECTION_TYPE(direct)); + + if(direct == IR_TX || direct == IR_TXRX){ + /* Enable ir tx unit */ + tmpVal = BL_RD_REG(IR_BASE,IRTX_CONFIG); + BL_WR_REG(IR_BASE,IRTX_CONFIG,BL_SET_REG_BIT(tmpVal,IR_CR_IRTX_EN)); + } + + if(direct == IR_RX || direct == IR_TXRX){ + /* Enable ir rx unit */ + tmpVal = BL_RD_REG(IR_BASE,IRRX_CONFIG); + BL_WR_REG(IR_BASE,IRRX_CONFIG,BL_SET_REG_BIT(tmpVal,IR_CR_IRRX_EN)); + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief IR disable function + * + * @param direct: IR direction type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_Disable(IR_Direction_Type direct) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_DIRECTION_TYPE(direct)); + + if(direct == IR_TX || direct == IR_TXRX){ + /* Disable ir tx unit */ + tmpVal = BL_RD_REG(IR_BASE,IRTX_CONFIG); + BL_WR_REG(IR_BASE,IRTX_CONFIG,BL_CLR_REG_BIT(tmpVal,IR_CR_IRTX_EN)); + } + + if(direct == IR_RX || direct == IR_TXRX){ + /* Disable ir rx unit */ + tmpVal = BL_RD_REG(IR_BASE,IRRX_CONFIG); + BL_WR_REG(IR_BASE,IRRX_CONFIG,BL_CLR_REG_BIT(tmpVal,IR_CR_IRRX_EN)); + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief IR tx software mode enable or disable function + * + * @param txSWM: Enable or disable + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_TxSWM(BL_Fun_Type txSWM) +{ + uint32_t tmpVal; + + /* Enable or disable tx swm */ + tmpVal = BL_RD_REG(IR_BASE,IRTX_CONFIG); + if(ENABLE == txSWM){ + BL_WR_REG(IR_BASE,IRTX_CONFIG,BL_SET_REG_BIT(tmpVal,IR_CR_IRTX_SWM_EN)); + }else{ + BL_WR_REG(IR_BASE,IRTX_CONFIG,BL_CLR_REG_BIT(tmpVal,IR_CR_IRTX_SWM_EN)); + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief IR clear rx fifo function + * + * @param None + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_RxFIFOClear(void) +{ + uint32_t tmpVal; + + /* Clear rx fifo */ + tmpVal = BL_RD_REG(IR_BASE,IRRX_SWM_FIFO_CONFIG_0); + BL_WR_REG(IR_BASE,IRRX_SWM_FIFO_CONFIG_0,BL_SET_REG_BIT(tmpVal,IR_RX_FIFO_CLR)); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief IR send data function + * + * @param irWord: IR tx data word 0 or 1 + * @param data: data to send + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_SendData(IR_Word_Type irWord,uint32_t data) +{ + /* Check the parameters */ + CHECK_PARAM(IS_IR_WORD_TYPE(irWord)); + + /* Write word 0 or word 1 */ + if(IR_WORD_0 == irWord){ + BL_WR_REG(IR_BASE,IRTX_DATA_WORD0,data); + } + else{ + BL_WR_REG(IR_BASE,IRTX_DATA_WORD1,data); + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief IR software mode send pulse width data function + * + * @param data: data to send + * @param length: Length of send buffer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_SWMSendData(uint16_t *data,uint8_t length) +{ + uint8_t i = 0,j = 0; + uint16_t minData = data[0]; + uint32_t tmpVal; + uint32_t pwVal = 0; + uint32_t count = (length+7)/8; + + /* Search for min value */ + for(i=1;idata[i] && data[i]!=0){ + minData = data[i]; + } + } + + /* Set pulse width unit */ + tmpVal = BL_RD_REG(IR_BASE,IRTX_PULSE_WIDTH); + BL_WR_REG(IR_BASE,IRTX_PULSE_WIDTH,BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRTX_PW_UNIT,minData)); + + /* Set tx SWM pulse width data as multiples of pulse width unit */ + for(i=0;i0){ + /* Read data */ + data[rxLen++] = BL_RD_REG(IR_BASE,IRRX_SWM_FIFO_RDATA)&0xffff; + } + return rxLen; +} + +/****************************************************************************//** + * @brief IR receive in NEC protocol + * + * @param address: Address + * @param command: Command + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type IR_ReceiveNEC(uint8_t* address,uint8_t* command) +{ + uint32_t tmpVal = IR_ReceiveData(IR_WORD_0); + + *address = tmpVal&0xff; + *command = (tmpVal>>16)&0xff; + + if((~(*address)&0xff) != ((tmpVal>>8)&0xff) || (~(*command)&0xff) != ((tmpVal>>24)&0xff)){ + return ERROR; + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief IR get rx data bit count function + * + * @param None + * + * @return IR rx data bit count + * +*******************************************************************************/ +uint8_t IR_GetRxDataBitCount(void) +{ + uint32_t tmpVal; + + /* Read rx data bit count */ + tmpVal = BL_RD_REG(IR_BASE,IRRX_DATA_COUNT); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal,IR_STS_IRRX_DATA_CNT); + + return tmpVal; +} + +/****************************************************************************//** + * @brief IR get rx fifo count function + * + * @param None + * + * @return IR rx fifo available count + * +*******************************************************************************/ +uint8_t IR_GetRxFIFOCount(void) +{ + uint32_t tmpVal; + + /* Read rx fifo count */ + tmpVal = BL_RD_REG(IR_BASE,IRRX_SWM_FIFO_CONFIG_0); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal,IR_RX_FIFO_CNT); + + return tmpVal; +} + +/****************************************************************************//** + * @brief IR learning to set rx and tx mode function + * + * @param data: Buffer to save data + * @param length: Length of data + * + * @return Protocol type + * +*******************************************************************************/ +IR_RxMode_Type IR_LearnToInit(uint32_t* data,uint8_t* length) +{ + uint32_t tmpVal; + uint32_t timeoutCnt = IR_RX_INT_TIMEOUT_COUNT; + + /* Disable rx,set rx in software mode and enable rx input inverse */ + tmpVal = BL_RD_REG(IR_BASE,IRRX_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal,IR_CR_IRRX_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRRX_MODE,0x2); + tmpVal = BL_SET_REG_BIT(tmpVal,IR_CR_IRRX_IN_INV); + BL_WR_REG(IR_BASE,IRRX_CONFIG,tmpVal); + /* Set pulse width threshold to trigger end condition */ + tmpVal = BL_RD_REG(IR_BASE,IRRX_PW_CONFIG); + BL_WR_REG(IR_BASE,IRRX_PW_CONFIG,BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRRX_END_TH,19999)); + + /* Clear and mask rx interrupt */ + tmpVal = BL_RD_REG(IR_BASE,IRRX_INT_STS); + tmpVal = BL_SET_REG_BIT(tmpVal,IR_CR_IRRX_END_MASK); + BL_WR_REG(IR_BASE,IRRX_INT_STS,BL_SET_REG_BIT(tmpVal,IR_CR_IRRX_END_CLR)); + + /* Enable rx */ + tmpVal = BL_RD_REG(IR_BASE,IRRX_CONFIG); + BL_WR_REG(IR_BASE,IRRX_CONFIG,BL_SET_REG_BIT(tmpVal,IR_CR_IRRX_EN)); + + /* Wait for rx interrupt */ + while(SET != IR_GetIntStatus(IR_INT_RX)){ + timeoutCnt--; + if(timeoutCnt == 0){ + IR_Disable(IR_RX); + + return TIMEOUT; + } + } + + /* Disable rx */ + tmpVal = BL_RD_REG(IR_BASE,IRRX_CONFIG); + BL_WR_REG(IR_BASE,IRRX_CONFIG,BL_CLR_REG_BIT(tmpVal,IR_CR_IRRX_EN)); + + /* Clear rx interrupt */ + tmpVal = BL_RD_REG(IR_BASE,IRRX_INT_STS); + BL_WR_REG(IR_BASE,IRRX_INT_STS,BL_SET_REG_BIT(tmpVal,IR_CR_IRRX_END_CLR)); + + /*Receive data */ + *length = IR_GetRxFIFOCount(); + *length = IR_SWMReceiveData((uint16_t*)data,*length); + + /* Judge protocol type */ + if(NEC_HEAD_H_MIN<(data[0]&0xffff)&&(data[0]&0xffff)>16)&&(data[0]>>16)>16)&&(data[0]>>16)>16)&&(data[0]>>16)>16) != 0){ + /* Set tx in software mode */ + /* Tx configure */ + BL_WR_REG(IR_BASE,IRTX_CONFIG,*length<<12 | 0xc); + /* Set modulation phase width */ + BL_WR_REG(IR_BASE,IRTX_PULSE_WIDTH,0x22110000); + + return IR_RX_SWM; + }else{ + tmpVal = BL_RD_REG(IR_BASE,IRRX_CONFIG); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal,IR_CR_IRRX_MODE); + if(tmpVal == 0){ + return IR_RX_NEC; + }else if(tmpVal == 1){ + return IR_RX_RC5; + }else{ + return IR_RX_SWM; + } + } +} + +/****************************************************************************//** + * @brief IR receive data according to mode which is learned function + * + * @param mode: Protocol type + * @param data: Buffer to save data + * + * @return Length of data + * +*******************************************************************************/ +uint8_t IR_LearnToReceive(IR_RxMode_Type mode,uint32_t* data) +{ + uint8_t length = 0; + uint32_t timeoutCnt = IR_RX_INT_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_RXMODE_TYPE(mode)); + + /* Disable ir rx */ + IR_Disable(IR_RX); + + /* Clear and mask rx interrupt */ + IR_ClrIntStatus(IR_INT_RX); + IR_IntMask(IR_INT_RX,MASK); + + /* Enable ir rx */ + IR_Enable(IR_RX); + + /* Wait for rx interrupt */ + while(SET != IR_GetIntStatus(IR_INT_RX)){ + timeoutCnt--; + if(timeoutCnt == 0){ + IR_Disable(IR_RX); + + return TIMEOUT; + } + } + + /* Disable ir rx */ + IR_Disable(IR_RX); + + /* Clear rx interrupt */ + IR_ClrIntStatus(IR_INT_RX); + + /* Receive data according to mode */ + if(mode == IR_RX_NEC || mode == IR_RX_RC5){ + /* Get data bit count */ + length = IR_GetRxDataBitCount(); + data[0] = IR_ReceiveData(IR_WORD_0); + }else{ + /* Get fifo count */ + length = IR_GetRxFIFOCount(); + length = IR_SWMReceiveData((uint16_t*)data,length); + } + + return length; +} + + +/****************************************************************************//** + * @brief IR send data according to mode which is learned function + * + * @param mode: Protocol type + * @param data: Buffer of data to send + * @param length: Length of data + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type IR_LearnToSend(IR_RxMode_Type mode,uint32_t* data,uint8_t length) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_IR_RXMODE_TYPE(mode)); + + /* Set send length */ + tmpVal = BL_RD_REG(IR_BASE,IRTX_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRTX_DATA_NUM,length-1); + BL_WR_REG(IR_BASE,IRTX_CONFIG,tmpVal); + + if(mode == IR_RX_NEC || mode == IR_RX_RC5){ + IR_SendCommand(0,data[0]); + }else{ + IR_SWMSendCommand((uint16_t*)data,length); + } + + return SUCCESS; +} + + +/****************************************************************************//** + * @brief IR init to control led function + * + * @param clk: Clock source + * @param div: Clock division(1~64) + * @param unit: Pulse width unit(multiples of clock pulse width, 1~4096) + * @param code0H: code 0 high level time(multiples of pulse width unit, 1~16) + * @param code0L: code 0 low level time(multiples of pulse width unit, 1~16) + * @param code1H: code 1 high level time(multiples of pulse width unit, 1~16) + * @param code1L: code 1 low level time(multiples of pulse width unit, 1~16) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Sts_Type IR_LEDInit(HBN_XCLK_CLK_Type clk,uint8_t div,uint8_t unit,uint8_t code0H,uint8_t code0L,uint8_t code1H,uint8_t code1L) +{ + IR_TxCfg_Type txCfg = { + 24, /* 24-bit data */ + DISABLE, /* Disable signal of tail pulse inverse */ + DISABLE, /* Disable signal of tail pulse */ + DISABLE, /* Disable signal of head pulse inverse */ + DISABLE, /* Disable signal of head pulse */ + DISABLE, /* Disable signal of logic 1 pulse inverse */ + DISABLE, /* Disable signal of logic 0 pulse inverse */ + ENABLE, /* Enable signal of data pulse */ + DISABLE, /* Disable signal of output modulation */ + ENABLE /* Enable signal of output inverse */ + }; + + IR_TxPulseWidthCfg_Type txPWCfg = { + code0L, /* Pulse width of logic 0 pulse phase 1 */ + code0H, /* Pulse width of logic 0 pulse phase 0 */ + code1L, /* Pulse width of logic 1 pulse phase 1 */ + code1H, /* Pulse width of logic 1 pulse phase 0 */ + 1, /* Pulse width of head pulse phase 1 */ + 1, /* Pulse width of head pulse phase 0 */ + 1, /* Pulse width of tail pulse phase 1 */ + 1, /* Pulse width of tail pulse phase 0 */ + 1, /* Modulation phase 1 width */ + 1, /* Modulation phase 0 width */ + unit /* Pulse width unit */ + }; + + HBN_Set_XCLK_CLK_Sel(clk); + GLB_Set_IR_CLK(ENABLE,GLB_IR_CLK_SRC_XCLK,div-1); + + /* Disable ir before config */ + IR_Disable(IR_TXRX); + + /* IR tx init */ + IR_TxInit(&txCfg); + IR_TxPulseWidthConfig(&txPWCfg); + + return SUCCESS; +} + + +/****************************************************************************//** + * @brief IR send 24-bit data to control led function + * + * @param data: Data to send(24-bit) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Sts_Type IR_LEDSend(uint32_t data) +{ + /* Change MSB_first to LSB_first */ + data = ((data>>1)&0x55555555)|((data<<1)&0xaaaaaaaa); + data = ((data>>2)&0x33333333)|((data<<2)&0xcccccccc); + data = ((data>>4)&0x0f0f0f0f)|((data<<4)&0xf0f0f0f0); + data = ((data>>16)&0xff)|(data&0xff00)|((data<<16)&0xff0000); + IR_SendCommand(0,data); + + return SUCCESS; +} + + +/*@} end of group IR_Public_Functions */ + +/*@} end of group IR */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/bl602_driver/std_drv/src/bl602_l1c.c b/drivers/bl602_driver/std_drv/src/bl602_l1c.c new file mode 100644 index 00000000..b7195b6e --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_l1c.c @@ -0,0 +1,422 @@ +/** + ****************************************************************************** + * @file bl602_l1c.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_l1c.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup L1C + * @{ + */ + +/** @defgroup L1C_Private_Macros + * @{ + */ + +/*@} end of group L1C_Private_Macros */ + +/** @defgroup L1C_Private_Types + * @{ + */ + +/*@} end of group L1C_Private_Types */ + +/** @defgroup L1C_Private_Variables + * @{ + */ +static intCallback_Type * l1cBmxErrIntCbfArra[L1C_BMX_ERR_INT_ALL]={NULL}; +static intCallback_Type * l1cBmxToIntCbfArra[L1C_BMX_TO_INT_ALL]={NULL}; + + +/*@} end of group L1C_Private_Variables */ + +/** @defgroup L1C_Global_Variables + * @{ + */ + +/*@} end of group L1C_Global_Variables */ + +/** @defgroup L1C_Private_Fun_Declaration + * @{ + */ + +/*@} end of group L1C_Private_Fun_Declaration */ + +/** @defgroup L1C_Private_Functions + * @{ + */ + +/*@} end of group L1C_Private_Functions */ + +/** @defgroup L1C_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief wrap set + * + * @param wrap: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION L1C_Set_Wrap(BL_Fun_Type wrap) +{ + uint32_t tmpVal = 0; + uint8_t cacheEn = 0; + + tmpVal=BL_RD_REG(L1C_BASE,L1C_CONFIG); + cacheEn = BL_IS_REG_BIT_SET(L1C_BASE,L1C_CACHEABLE); + if(cacheEn != 0){ + tmpVal=BL_CLR_REG_BIT(tmpVal,L1C_CACHEABLE); + BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal); + } + + tmpVal=BL_RD_REG(L1C_BASE,L1C_CONFIG); + if(wrap == ENABLE){ + tmpVal=BL_CLR_REG_BIT(tmpVal,L1C_WRAP_DIS); + }else{ + tmpVal=BL_SET_REG_BIT(tmpVal,L1C_WRAP_DIS); + } + BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal); + + if(cacheEn != 0){ + tmpVal=BL_SET_REG_BIT(tmpVal,L1C_CACHEABLE); + BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal); + } + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief cache way disable set + * + * @param disableVal: cache way disable value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION L1C_Set_Way_Disable(uint8_t disableVal) +{ + uint32_t tmpVal = 0; + uint8_t cacheEn = 0; + + tmpVal=BL_RD_REG(L1C_BASE,L1C_CONFIG); + cacheEn = BL_IS_REG_BIT_SET(L1C_BASE,L1C_CACHEABLE); + if(cacheEn != 0){ + tmpVal=BL_CLR_REG_BIT(tmpVal,L1C_CACHEABLE); + BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal); + } + + tmpVal=BL_RD_REG(L1C_BASE,L1C_CONFIG); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,L1C_WAY_DIS,disableVal); + BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal); + + if(cacheEn != 0){ + tmpVal=BL_SET_REG_BIT(tmpVal,L1C_CACHEABLE); + BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal); + } + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief Set for ROM 2T access if CPU freq >120MHz + * + * @param enable: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION L1C_IROM_2T_Access_Set(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal=BL_RD_REG(L1C_BASE,L1C_CONFIG); + if(enable){ + tmpVal=BL_SET_REG_BIT(tmpVal,L1C_IROM_2T_ACCESS); + }else{ + tmpVal=BL_CLR_REG_BIT(tmpVal,L1C_IROM_2T_ACCESS); + } + BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief L1C BMX init + * + * @param l1cBmxCfg: L1C BMX config + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_Init(L1C_BMX_Cfg_Type *l1cBmxCfg) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((l1cBmxCfg->timeoutEn)<=0xF); + + tmpVal=BL_RD_REG(L1C_BASE,L1C_CONFIG); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,L1C_BMX_TIMEOUT_EN,l1cBmxCfg->timeoutEn); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,L1C_BMX_ERR_EN,l1cBmxCfg->errEn); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,L1C_BMX_ARB_MODE,l1cBmxCfg->arbMod); + BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(L1C_BMX_ERR_IRQn,L1C_BMX_ERR_IRQHandler); + Interrupt_Handler_Register(L1C_BMX_TO_IRQn,L1C_BMX_TO_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************//** + * @brief L1C BMX address monitor enable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_Addr_Monitor_Enable(void) +{ + uint32_t tmpVal = 0; + + tmpVal=BL_RD_REG(L1C_BASE,L1C_BMX_ERR_ADDR_EN); + tmpVal=BL_CLR_REG_BIT(tmpVal,L1C_BMX_ERR_ADDR_DIS); + BL_WR_REG(L1C_BASE,L1C_BMX_ERR_ADDR_EN,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief L1C BMX address monitor disable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_Addr_Monitor_Disable(void) +{ + uint32_t tmpVal = 0; + + tmpVal=BL_RD_REG(L1C_BASE,L1C_BMX_ERR_ADDR_EN); + tmpVal=BL_SET_REG_BIT(tmpVal,L1C_BMX_ERR_ADDR_DIS); + BL_WR_REG(L1C_BASE,L1C_BMX_ERR_ADDR_EN,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief L1C BMX bus error response enable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_BusErrResponse_Enable(void) +{ + uint32_t tmpVal = 0; + + tmpVal=BL_RD_REG(L1C_BASE,L1C_CONFIG); + tmpVal=BL_SET_REG_BIT(tmpVal,L1C_BMX_ERR_EN); + BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief L1C BMX bus error response disable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_BusErrResponse_Disable(void) +{ + uint32_t tmpVal = 0; + + tmpVal=BL_RD_REG(L1C_BASE,L1C_CONFIG); + tmpVal=BL_CLR_REG_BIT(tmpVal,L1C_BMX_ERR_EN); + BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Get L1C BMX error status + * + * @param errType: L1C BMX error status type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type L1C_BMX_Get_Status(L1C_BMX_BUS_ERR_Type errType) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_L1C_BMX_BUS_ERR_TYPE(errType)); + + tmpVal=BL_RD_REG(L1C_BASE,L1C_BMX_ERR_ADDR_EN); + if(errType==L1C_BMX_BUS_ERR_TRUSTZONE_DECODE){ + return BL_GET_REG_BITS_VAL(tmpVal,L1C_BMX_ERR_TZ)?SET:RESET; + }else{ + return BL_GET_REG_BITS_VAL(tmpVal,L1C_BMX_ERR_DEC)?SET:RESET; + } +} + +/****************************************************************************//** + * @brief Get L1C BMX error address + * + * @param None + * + * @return NP L1C BMX error address + * +*******************************************************************************/ +uint32_t L1C_BMX_Get_Err_Addr(void) +{ + return BL_RD_REG(L1C_BASE,L1C_BMX_ERR_ADDR); +} + +/****************************************************************************//** + * @brief L1C BMX error interrupt callback install + * + * @param intType: L1C BMX error interrupt type + * @param cbFun: callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_ERR_INT_Callback_Install(L1C_BMX_ERR_INT_Type intType,intCallback_Type* cbFun) +{ + CHECK_PARAM(IS_L1C_BMX_ERR_INT_TYPE(intType)); + + l1cBmxErrIntCbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************//** + * @brief L1C BMX ERR interrupt IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void L1C_BMX_ERR_IRQHandler(void) +{ + L1C_BMX_ERR_INT_Type intType; + + for(intType=L1C_BMX_ERR_INT_ERR;intType=1&&EF_Ctrl_Is_CapCode_Slot_Empty(0,reload)){ + mfg_print("Empty slot:%d\r\n",0); + empty=1; + }else if(rf_cal_slots>=2&&EF_Ctrl_Is_CapCode_Slot_Empty(1,reload)){ + mfg_print("Empty slot:%d\r\n",1); + empty=1; + }else if(rf_cal_slots>=3&&EF_Ctrl_Is_CapCode_Slot_Empty(2,reload)){ + mfg_print("Empty slot:%d\r\n",2); + empty=1; + }else{ + mfg_print("No empty slot found\r\n"); + } + + GLB_Set_System_CLK_Div(hdiv,bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); +#endif + return empty; +} + +int8_t mfg_efuse_write_xtal_capcode_pre(uint8_t capcode,uint8_t program) +{ + BL_Err_Type ret=SUCCESS; + uint8_t slot=0xff; + uint8_t hdiv=0,bdiv=0; + HBN_ROOT_CLK_Type rtClk=GLB_Get_Root_CLK_Sel(); + + bdiv=GLB_Get_BCLK_Div(); + hdiv=GLB_Get_HCLK_Div(); +#if 1 + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + if(rf_cal_slots>=1&&EF_Ctrl_Is_CapCode_Slot_Empty(0,1)){ + slot=0; + }else if(rf_cal_slots>=2&&EF_Ctrl_Is_CapCode_Slot_Empty(1,1)){ + slot=1; + }else if(rf_cal_slots>=3&&EF_Ctrl_Is_CapCode_Slot_Empty(2,1)){ + slot=2; + }else{ + mfg_print("No empty slot found\r\n"); + } + + if(slot!=0xff){ + ret=EF_Ctrl_Write_CapCode_Opt(slot,capcode,program); + mfg_print("Write slot:%d\r\n",slot); + } + GLB_Set_System_CLK_Div(hdiv,bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); +#endif + if(ret==SUCCESS){ + return 0; + }else{ + return -1; + } +} + +void mfg_efuse_write_xtal_capcode(void) +{ + uint8_t hdiv=0,bdiv=0; + HBN_ROOT_CLK_Type rtClk=GLB_Get_Root_CLK_Sel(); + + bdiv=GLB_Get_BCLK_Div(); + hdiv=GLB_Get_HCLK_Div(); +#if 1 + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + EF_Ctrl_Program_Direct_R0(0,NULL,0); + while(SET==EF_Ctrl_Busy()); + + GLB_Set_System_CLK_Div(hdiv,bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); +#endif +} + +int8_t mfg_efuse_read_xtal_capcode(uint8_t *capcode,uint8_t reload) +{ + uint8_t slot=0xff; + BL_Err_Type ret=ERROR; + uint8_t hdiv=0,bdiv=0; + HBN_ROOT_CLK_Type rtClk=GLB_Get_Root_CLK_Sel(); + + bdiv=GLB_Get_BCLK_Div(); + hdiv=GLB_Get_HCLK_Div(); +#if 1 + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + if(rf_cal_slots>=3&&(!EF_Ctrl_Is_CapCode_Slot_Empty(2,reload))){ + slot=2; + }else if(rf_cal_slots>=2&&(!EF_Ctrl_Is_CapCode_Slot_Empty(1,reload))){ + slot=1; + }else if(rf_cal_slots>=1&&(!EF_Ctrl_Is_CapCode_Slot_Empty(0,reload))){ + slot=0; + } + + if(slot!=0xff){ + mfg_print("Read slot:%d\r\n",slot); + ret=EF_Ctrl_Read_CapCode_Opt(slot,capcode,reload); + }else{ + mfg_print("No written slot found\r\n"); + } + + GLB_Set_System_CLK_Div(hdiv,bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); +#endif + if(ret==SUCCESS){ + return 0; + }else{ + return -1; + } +} + +uint8_t mfg_efuse_is_poweroffset_slot_empty(uint8_t reload) +{ + uint8_t empty=0; + uint8_t hdiv=0,bdiv=0; + HBN_ROOT_CLK_Type rtClk=GLB_Get_Root_CLK_Sel(); + + bdiv=GLB_Get_BCLK_Div(); + hdiv=GLB_Get_HCLK_Div(); +#if 1 + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + if(rf_cal_slots>=1&&EF_Ctrl_Is_PowerOffset_Slot_Empty(0,reload)){ + mfg_print("Empty slot:%d\r\n",0); + empty=1; + }else if(rf_cal_slots>=2&&EF_Ctrl_Is_PowerOffset_Slot_Empty(1,reload)){ + mfg_print("Empty slot:%d\r\n",1); + empty=1; + }else if(rf_cal_slots>=3&&EF_Ctrl_Is_PowerOffset_Slot_Empty(2,reload)){ + mfg_print("Empty slot:%d\r\n",2); + empty=1; + }else{ + mfg_print("No empty slot found\r\n"); + } + + GLB_Set_System_CLK_Div(hdiv,bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); +#endif + return empty; +} + +int8_t mfg_efuse_write_poweroffset_pre(int8_t pwrOffset[14],uint8_t program) +{ + BL_Err_Type ret=SUCCESS; + uint8_t slot=0xff; + int8_t pwrOffsetTmp[3]; + uint8_t hdiv=0,bdiv=0; + HBN_ROOT_CLK_Type rtClk=GLB_Get_Root_CLK_Sel(); + + bdiv=GLB_Get_BCLK_Div(); + hdiv=GLB_Get_HCLK_Div(); + +#if 1 + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + if(rf_cal_slots>=1&&EF_Ctrl_Is_PowerOffset_Slot_Empty(0,1)){ + slot=0; + }else if(rf_cal_slots>=2&&EF_Ctrl_Is_PowerOffset_Slot_Empty(1,1)){ + slot=1; + }else if(rf_cal_slots>=3&&EF_Ctrl_Is_PowerOffset_Slot_Empty(2,1)){ + slot=2; + }else{ + mfg_print("No empty slot found\r\n"); + } + + if(slot!=0xff){ + pwrOffsetTmp[0]=pwrOffset[0]; + pwrOffsetTmp[1]=pwrOffset[6]; + pwrOffsetTmp[2]=pwrOffset[12]; + ret=EF_Ctrl_Write_PowerOffset_Opt(slot,pwrOffsetTmp,program); + mfg_print("Write slot:%d\r\n",slot); + } + + GLB_Set_System_CLK_Div(hdiv,bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); +#endif + + if(ret==SUCCESS){ + return 0; + }else{ + return -1; + } +} + +void mfg_efuse_write_poweroffset(void) +{ + uint8_t hdiv=0,bdiv=0; + HBN_ROOT_CLK_Type rtClk=GLB_Get_Root_CLK_Sel(); + + bdiv=GLB_Get_BCLK_Div(); + hdiv=GLB_Get_HCLK_Div(); +#if 1 + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + EF_Ctrl_Program_Direct_R0(0,NULL,0); + while(SET==EF_Ctrl_Busy()); + + GLB_Set_System_CLK_Div(hdiv,bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); +#endif +} + +int8_t mfg_efuse_read_poweroffset(int8_t pwrOffset[14],uint8_t reload) +{ + uint8_t slot=0xff; + BL_Err_Type ret=ERROR; + int8_t pwrOffsetTmp[3]; + + int32_t step=0; + uint8_t hdiv=0,bdiv=0; + HBN_ROOT_CLK_Type rtClk=GLB_Get_Root_CLK_Sel(); + + bdiv=GLB_Get_BCLK_Div(); + hdiv=GLB_Get_HCLK_Div(); + +#if 1 + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + if(rf_cal_slots>=3&&(!EF_Ctrl_Is_PowerOffset_Slot_Empty(2,reload))){ + slot=2; + }else if(rf_cal_slots>=2&&(!EF_Ctrl_Is_PowerOffset_Slot_Empty(1,reload))){ + slot=1; + }else if(rf_cal_slots>=1&&(!EF_Ctrl_Is_PowerOffset_Slot_Empty(0,reload))){ + slot=0; + } + + if(slot!=0xff){ + mfg_print("Read slot:%d\r\n",slot); + ret=EF_Ctrl_Read_PowerOffset_Opt(slot,pwrOffsetTmp,reload); + memset(pwrOffset,0,14); + + pwrOffset[0]=pwrOffsetTmp[0]; + + step=(pwrOffsetTmp[1]-pwrOffsetTmp[0])*100/6; + pwrOffset[1]=(step+50)/100+pwrOffsetTmp[0]; + pwrOffset[2]=(step*2+50)/100+pwrOffsetTmp[0]; + pwrOffset[3]=(step*3+50)/100+pwrOffsetTmp[0]; + pwrOffset[4]=(step*4+50)/100+pwrOffsetTmp[0]; + pwrOffset[5]=(step*5+50)/100+pwrOffsetTmp[0]; + + pwrOffset[6]=pwrOffsetTmp[1]; + + step=(pwrOffsetTmp[2]-pwrOffsetTmp[1])*100/6; + pwrOffset[7]=(step+50)/100+pwrOffsetTmp[1]; + pwrOffset[8]=(step*2+50)/100+pwrOffsetTmp[1]; + pwrOffset[9]=(step*3+50)/100+pwrOffsetTmp[1]; + pwrOffset[10]=(step*4+50)/100+pwrOffsetTmp[1]; + pwrOffset[11]=(step*5+50)/100+pwrOffsetTmp[1]; + + pwrOffset[12]=pwrOffsetTmp[2]; + + pwrOffset[13]=(step*7+50)/100+pwrOffsetTmp[1]; + }else{ + mfg_print("No written slot found\r\n"); + } + + GLB_Set_System_CLK_Div(hdiv,bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); +#endif + if(ret==SUCCESS){ + return 0; + }else{ + return -1; + } +} + +uint8_t mfg_efuse_is_macaddr_slot_empty(uint8_t reload) +{ + uint8_t empty=0; + uint8_t hdiv=0,bdiv=0; + HBN_ROOT_CLK_Type rtClk=GLB_Get_Root_CLK_Sel(); + + bdiv=GLB_Get_BCLK_Div(); + hdiv=GLB_Get_HCLK_Div(); +#if 1 + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + if(rf_cal_slots>=1&&EF_Ctrl_Is_MAC_Address_Slot_Empty(0,reload)){ + mfg_print("Empty slot:%d\r\n",0); + empty=1; + }else if(rf_cal_slots>=2&&EF_Ctrl_Is_MAC_Address_Slot_Empty(1,reload)){ + mfg_print("Empty slot:%d\r\n",1); + empty=1; + }else if(rf_cal_slots>=3&&EF_Ctrl_Is_MAC_Address_Slot_Empty(2,reload)){ + mfg_print("Empty slot:%d\r\n",2); + empty=1; + }else{ + mfg_print("No empty slot found\r\n"); + } + + GLB_Set_System_CLK_Div(hdiv,bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); +#endif + return empty; +} + +int8_t mfg_efuse_write_macaddr_pre(uint8_t mac[6],uint8_t program) +{ + BL_Err_Type ret=SUCCESS; + uint8_t slot=0xff; + uint8_t hdiv=0,bdiv=0; + HBN_ROOT_CLK_Type rtClk=GLB_Get_Root_CLK_Sel(); + + bdiv=GLB_Get_BCLK_Div(); + hdiv=GLB_Get_HCLK_Div(); + +#if 1 + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + if(rf_cal_slots>=1&&EF_Ctrl_Is_MAC_Address_Slot_Empty(0,1)){ + slot=0; + }else if(rf_cal_slots>=2&&EF_Ctrl_Is_MAC_Address_Slot_Empty(1,1)){ + slot=1; + }else if(rf_cal_slots>=3&&EF_Ctrl_Is_MAC_Address_Slot_Empty(2,1)){ + slot=2; + }else{ + mfg_print("No empty slot found\r\n"); + } + + if(slot!=0xff){ + ret=EF_Ctrl_Write_MAC_Address_Opt(slot,mac,program); + mfg_print("Write slot:%d\r\n",slot); + } + + GLB_Set_System_CLK_Div(hdiv,bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); + +#endif + if(ret==SUCCESS){ + return 0; + }else{ + return -1; + } +} + +void mfg_efuse_write_macaddr(void) +{ + uint8_t hdiv=0,bdiv=0; + HBN_ROOT_CLK_Type rtClk=GLB_Get_Root_CLK_Sel(); + + bdiv=GLB_Get_BCLK_Div(); + hdiv=GLB_Get_HCLK_Div(); +#if 1 + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + EF_Ctrl_Program_Direct_R0(0,NULL,0); + while(SET==EF_Ctrl_Busy()); + //EF_Ctrl_Program_Direct_R1(0,NULL,0); + //while(SET==EF_Ctrl_Busy()); + + GLB_Set_System_CLK_Div(hdiv,bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); +#endif +} + +int8_t mfg_efuse_read_macaddr(uint8_t mac[6],uint8_t reload) +{ + uint8_t slot=0xff; + BL_Err_Type ret=ERROR; + uint8_t hdiv=0,bdiv=0; + HBN_ROOT_CLK_Type rtClk=GLB_Get_Root_CLK_Sel(); + + bdiv=GLB_Get_BCLK_Div(); + hdiv=GLB_Get_HCLK_Div(); + +#if 1 + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + if(rf_cal_slots>=3&&(!EF_Ctrl_Is_MAC_Address_Slot_Empty(2,reload))){ + slot=2; + }else if(rf_cal_slots>=2&&(!EF_Ctrl_Is_MAC_Address_Slot_Empty(1,reload))){ + slot=1; + }else if(rf_cal_slots>=1&&(!EF_Ctrl_Is_MAC_Address_Slot_Empty(0,reload))){ + slot=0; + } + + if(slot!=0xff){ + mfg_print("Read slot:%d\r\n",slot); + ret=EF_Ctrl_Read_MAC_Address_Opt(slot,mac,reload); + }else{ + mfg_print("No written slot found\r\n"); + } + + GLB_Set_System_CLK_Div(hdiv,bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); +#endif + if(ret==SUCCESS){ + return 0; + }else{ + return -1; + } +} + +int8_t mfg_efuse_write_pre(uint32_t addr,uint32_t *data,uint32_t countInword) +{ + BL_Err_Type ret=SUCCESS; + uint8_t hdiv=0,bdiv=0; + HBN_ROOT_CLK_Type rtClk=GLB_Get_Root_CLK_Sel(); + + if(addr>128){ + return -1; + } + + bdiv=GLB_Get_BCLK_Div(); + hdiv=GLB_Get_HCLK_Div(); + + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + EF_Ctrl_Write_R0(addr/4,data,countInword); + + GLB_Set_System_CLK_Div(hdiv,bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); + + if(ret==SUCCESS){ + return 0; + }else{ + return -1; + } +} + +int8_t mfg_efuse_read(uint32_t addr,uint32_t *data,uint32_t countInword,uint8_t reload) +{ + BL_Err_Type ret=SUCCESS; + uint8_t hdiv=0,bdiv=0; + HBN_ROOT_CLK_Type rtClk=GLB_Get_Root_CLK_Sel(); + + if(addr>128){ + return -1; + } + + bdiv=GLB_Get_BCLK_Div(); + hdiv=GLB_Get_HCLK_Div(); + + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + if(reload){ + EF_Ctrl_Read_Direct_R0(addr/4,data,countInword); + }else{ + EF_Ctrl_Read_R0(addr/4,data,countInword); + } + + GLB_Set_System_CLK_Div(hdiv,bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); + + if(ret==SUCCESS){ + return 0; + }else{ + return -1; + } +} + +int8_t mfg_efuse_program(void) +{ + BL_Err_Type ret=SUCCESS; + uint8_t hdiv=0,bdiv=0; + HBN_ROOT_CLK_Type rtClk=GLB_Get_Root_CLK_Sel(); + + bdiv=GLB_Get_BCLK_Div(); + hdiv=GLB_Get_HCLK_Div(); + + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + + EF_Ctrl_Program_Direct_R0(0,NULL,0); + while(SET==EF_Ctrl_Busy()); + + GLB_Set_System_CLK_Div(hdiv,bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); + + if(ret==SUCCESS){ + return 0; + }else{ + return -1; + } +} diff --git a/drivers/bl602_driver/std_drv/src/bl602_mfg_flash.c b/drivers/bl602_driver/std_drv/src/bl602_mfg_flash.c new file mode 100644 index 00000000..b2dba3c0 --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_mfg_flash.c @@ -0,0 +1,233 @@ +#include "bl602_mfg_flash.h" +#include "partition.h" +#include "softcrc.h" + +static rf_para_flash_t rf_para; +static uint32_t rf_para_addr=0; +static SPI_Flash_Cfg_Type *pFlashCfg; + +#ifdef BFLB_MCU_SDK +#include "bflb_platform.h" +#define mfg_print MSG +#else +#define mfg_print printf +#endif +//#define RF_PARA_MAGIC_FLAG 0x41504652 +#define RF_PARA_MAGIC_FLAG 0x41 +#define RF_PARA_VALID_FLAG 0x5A +#define RF_PARA_PART_NAME "rf_para" + + +PtTable_Stuff_Config ptTableStuff[2]; +PtTable_Entry_Config ptEntry={0}; + +/*partiton need this*/ +void main(void) +{ + +} + +static BL_Err_Type PtTable_Flash_Read (uint32_t addr,uint8_t *data, uint32_t len) +{ + XIP_SFlash_Read_Need_Lock(pFlashCfg,addr,data,len); + return SUCCESS; +} + +int8_t mfg_flash_init( SPI_Flash_Cfg_Type *flashCfg) +{ + PtTable_ID_Type activeID; + PtTable_Error_Type ret; + + pFlashCfg=flashCfg; + if(pFlashCfg!=NULL){ + PtTable_Set_Flash_Operation(NULL,NULL,PtTable_Flash_Read); + activeID=PtTable_Get_Active_Partition_Need_Lock(ptTableStuff); + if(PT_TABLE_ID_INVALID==activeID){ + mfg_print("No valid PT\r\n"); + return -1; + } + ret=PtTable_Get_Active_Entries_By_Name(&ptTableStuff[activeID],(uint8_t*)RF_PARA_PART_NAME,&ptEntry); + if(PT_ERROR_SUCCESS==ret){ + rf_para_addr=ptEntry.Address[0]; + mfg_print("RF para flash address=%08x\r\n",(unsigned int)rf_para_addr); + return 0; + }else{ + mfg_print("Not found "RF_PARA_PART_NAME"\r\n"); + return -1; + } + } + return -1; +} + +static int8_t mfg_flash_program(void) +{ + BL_Err_Type ret; + + mfg_print("mfg_flash_write\r\n"); + + ret=XIP_SFlash_Erase_Need_Lock(pFlashCfg,rf_para_addr,rf_para_addr+15); + if(ret!=SUCCESS){ + mfg_print("Flash erase error\r\n"); + return -1; + } + + ret=XIP_SFlash_Write_Need_Lock(pFlashCfg,rf_para_addr,(uint8_t *)&rf_para,sizeof(rf_para)); + if(ret!=SUCCESS){ + mfg_print("Flash write error\r\n"); + return -1; + } + + return 0; +} + +static int8_t mfg_flash_read(void) +{ + BL_Err_Type ret; + + mfg_print("mfg_flash_read\r\n"); + + ret=XIP_SFlash_Read_Need_Lock(pFlashCfg,rf_para_addr,(uint8_t *)&rf_para,sizeof(rf_para)); + if(ret!=SUCCESS){ + mfg_print("Flash write error\r\n"); + return -1; + } + + return 0; +} + +int8_t mfg_flash_write_xtal_capcode_pre(uint8_t capcode,uint8_t program) +{ + rf_para.magic=RF_PARA_MAGIC_FLAG; + rf_para.capcode_valid=RF_PARA_VALID_FLAG; + rf_para.capcode=capcode; + rf_para.crc32=BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8); + + if(program){ + return mfg_flash_program(); + }else{ + return 0; + } +} + +void mfg_flash_write_xtal_capcode(void) +{ + mfg_flash_program(); +} + +int8_t mfg_flash_read_xtal_capcode(uint8_t *capcode,uint8_t reload) +{ + if((reload!=0)&&(mfg_flash_read()!=0)){ + return -1; + } + if(rf_para.magic==RF_PARA_MAGIC_FLAG){ + if(rf_para.crc32==(BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8))){ + if(rf_para.capcode_valid==RF_PARA_VALID_FLAG){ + *capcode=rf_para.capcode; + return 0; + } + } + } + return -1; +} + +int8_t mfg_flash_write_poweroffset_pre(int8_t pwrOffset[14],uint8_t program) +{ + rf_para.magic=RF_PARA_MAGIC_FLAG; + rf_para.poweroffset_valid=RF_PARA_VALID_FLAG; + rf_para.poweroffset[0]=pwrOffset[0]; + rf_para.poweroffset[1]=pwrOffset[6]; + rf_para.poweroffset[2]=pwrOffset[12]; + rf_para.crc32=BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8); + + if(program){ + return mfg_flash_program(); + }else{ + return 0; + } +} + +void mfg_flash_write_poweroffset(void) +{ + mfg_flash_program(); +} + +int8_t mfg_flash_read_poweroffset(int8_t pwrOffset[14],uint8_t reload) +{ + int8_t pwrOffsetTmp[3]; + int32_t step=0; + + if((reload!=0)&&(mfg_flash_read()!=0)){ + return -1; + } + if(rf_para.magic==RF_PARA_MAGIC_FLAG){ + if(rf_para.crc32==(BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8))){ + if(rf_para.poweroffset_valid==RF_PARA_VALID_FLAG){ + memset(pwrOffset,0,14); + pwrOffsetTmp[0]=rf_para.poweroffset[0]; + pwrOffsetTmp[1]=rf_para.poweroffset[1]; + pwrOffsetTmp[2]=rf_para.poweroffset[2]; + + pwrOffset[0]=pwrOffsetTmp[0]; + + step=(pwrOffsetTmp[1]-pwrOffsetTmp[0])*100/6; + pwrOffset[1]=(step+50)/100+pwrOffsetTmp[0]; + pwrOffset[2]=(step*2+50)/100+pwrOffsetTmp[0]; + pwrOffset[3]=(step*3+50)/100+pwrOffsetTmp[0]; + pwrOffset[4]=(step*4+50)/100+pwrOffsetTmp[0]; + pwrOffset[5]=(step*5+50)/100+pwrOffsetTmp[0]; + + pwrOffset[6]=pwrOffsetTmp[1]; + + step=(pwrOffsetTmp[2]-pwrOffsetTmp[1])*100/6; + pwrOffset[7]=(step+50)/100+pwrOffsetTmp[1]; + pwrOffset[8]=(step*2+50)/100+pwrOffsetTmp[1]; + pwrOffset[9]=(step*3+50)/100+pwrOffsetTmp[1]; + pwrOffset[10]=(step*4+50)/100+pwrOffsetTmp[1]; + pwrOffset[11]=(step*5+50)/100+pwrOffsetTmp[1]; + + pwrOffset[12]=pwrOffsetTmp[2]; + + pwrOffset[13]=(step*7+50)/100+pwrOffsetTmp[1]; + return 0; + } + } + } + return -1; +} + +int8_t mfg_flash_write_macaddr_pre(uint8_t mac[6],uint8_t program) +{ + rf_para.magic=RF_PARA_MAGIC_FLAG; + rf_para.mac_valid=RF_PARA_VALID_FLAG; + memcpy(rf_para.mac,mac,6); + rf_para.crc32=BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8); + + if(program){ + return mfg_flash_program(); + }else{ + return 0; + } +} + +void mfg_flash_write_macaddr(void) +{ + mfg_flash_program(); +} + +int8_t mfg_flash_read_macaddr(uint8_t mac[6],uint8_t reload) +{ + if((reload!=0)&&(mfg_flash_read()!=0)){ + mfg_print("mfg_flash_read fail\r\n"); + return -1; + } + if(rf_para.magic==RF_PARA_MAGIC_FLAG){ + if(rf_para.crc32==(BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8))){ + if(rf_para.mac_valid==RF_PARA_VALID_FLAG){ + memcpy(mac,rf_para.mac,6); + return 0; + } + } + } + return -1; +} + diff --git a/drivers/bl602_driver/std_drv/src/bl602_mfg_media.c b/drivers/bl602_driver/std_drv/src/bl602_mfg_media.c new file mode 100644 index 00000000..e0c0bb85 --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_mfg_media.c @@ -0,0 +1,220 @@ +#include "bl602_mfg_media.h" + +static uint8_t rf_para_on_flash=0; + +int8_t mfg_media_init_need_lock( SPI_Flash_Cfg_Type *flashCfg) +{ + if(0==mfg_flash_init(flashCfg)){ + rf_para_on_flash=1; + }else{ + rf_para_on_flash=0; + } + return 0; +} + +int8_t mfg_media_init_with_lock( SPI_Flash_Cfg_Type *flashCfg) +{ + int8_t ret; + + __disable_irq(); + ret=mfg_media_init_need_lock(flashCfg); + __enable_irq(); + + return ret; +} + +uint8_t mfg_media_is_xtal_capcode_slot_empty(uint8_t reload) +{ + if(rf_para_on_flash){ + return 1; + }else{ + return mfg_efuse_is_xtal_capcode_slot_empty(reload); + } +} + +int8_t mfg_media_write_xtal_capcode_pre_need_lock(uint8_t capcode,uint8_t program) +{ + if(rf_para_on_flash){ + return mfg_flash_write_xtal_capcode_pre(capcode,program); + }else{ + return mfg_efuse_write_xtal_capcode_pre(capcode,program); + } +} + +int8_t mfg_media_write_xtal_capcode_pre_with_lock(uint8_t capcode,uint8_t program) +{ + int8_t ret; + + __disable_irq(); + ret=mfg_media_write_xtal_capcode_pre_need_lock(capcode,program); + __enable_irq(); + + return ret; +} + +void mfg_media_write_xtal_capcode_need_lock(void) +{ + if(rf_para_on_flash){ + return mfg_flash_write_xtal_capcode(); + }else{ + return mfg_efuse_write_xtal_capcode(); + } +} + +void mfg_media_write_xtal_capcode_with_lock(void) +{ + __disable_irq(); + mfg_media_write_xtal_capcode_need_lock(); + __enable_irq(); +} + +int8_t mfg_media_read_xtal_capcode_need_lock(uint8_t *capcode,uint8_t reload) +{ + if(rf_para_on_flash){ + return mfg_flash_read_xtal_capcode(capcode,reload); + }else{ + return mfg_efuse_read_xtal_capcode(capcode,reload); + } +} + +int8_t mfg_media_read_xtal_capcode_with_lock(uint8_t *capcode,uint8_t reload) +{ + int8_t ret; + + __disable_irq(); + ret=mfg_media_read_xtal_capcode_need_lock(capcode,reload); + __enable_irq(); + + return ret; +} + +uint8_t mfg_media_is_poweroffset_slot_empty(uint8_t reload) +{ + if(rf_para_on_flash){ + return 1; + }else{ + return mfg_efuse_is_poweroffset_slot_empty(reload); + } +} + +int8_t mfg_media_write_poweroffset_pre_need_lock(int8_t pwrOffset[14],uint8_t program) +{ + if(rf_para_on_flash){ + return mfg_flash_write_poweroffset_pre(pwrOffset,program); + }else{ + return mfg_efuse_write_poweroffset_pre(pwrOffset,program); + } +} + +int8_t mfg_media_write_poweroffset_pre_with_lock(int8_t pwrOffset[14],uint8_t program) +{ + int ret; + + __disable_irq(); + ret=mfg_media_write_poweroffset_pre_need_lock(pwrOffset,program); + __enable_irq(); + + return ret; +} + +void mfg_media_write_poweroffset_need_lock(void) +{ + if(rf_para_on_flash){ + return mfg_flash_write_poweroffset(); + }else{ + return mfg_efuse_write_poweroffset(); + } +} + +void mfg_media_write_poweroffset_with_lock(void) +{ + __disable_irq(); + mfg_media_write_poweroffset_need_lock(); + __enable_irq(); +} + +int8_t mfg_media_read_poweroffset_need_lock(int8_t pwrOffset[14],uint8_t reload) +{ + if(rf_para_on_flash){ + return mfg_flash_read_poweroffset(pwrOffset,reload); + }else{ + return mfg_efuse_read_poweroffset(pwrOffset,reload); + } +} + +int8_t mfg_media_read_poweroffset_with_lock(int8_t pwrOffset[14],uint8_t reload) +{ + int ret; + + __disable_irq(); + ret=mfg_media_read_poweroffset_need_lock(pwrOffset,reload); + __enable_irq(); + + return ret; +} + +uint8_t mfg_media_is_macaddr_slot_empty(uint8_t reload) +{ + if(rf_para_on_flash){ + return 1; + }else{ + return mfg_efuse_is_macaddr_slot_empty(reload); + } +} + +int8_t mfg_media_write_macaddr_pre_need_lock(uint8_t mac[6],uint8_t program) +{ + if(rf_para_on_flash){ + return mfg_flash_write_macaddr_pre(mac,program); + }else{ + return mfg_efuse_write_macaddr_pre(mac,program); + } +} + +int8_t mfg_media_write_macaddr_pre_with_lock(uint8_t mac[6],uint8_t program) +{ + int ret; + + __disable_irq(); + ret=mfg_media_write_macaddr_pre_need_lock(mac,program); + __enable_irq(); + + return ret; +} + +void mfg_media_write_macaddr_need_lock(void) +{ + if(rf_para_on_flash){ + return mfg_flash_write_macaddr(); + }else{ + return mfg_efuse_write_macaddr(); + } +} + +void mfg_media_write_macaddr_with_lock(void) +{ + __disable_irq(); + mfg_media_write_macaddr_need_lock(); + __enable_irq(); +} + +int8_t mfg_media_read_macaddr_need_lock(uint8_t mac[6],uint8_t reload) +{ + if(rf_para_on_flash){ + return mfg_flash_read_macaddr(mac,reload); + }else{ + return mfg_efuse_read_macaddr(mac,reload); + } +} + +int8_t mfg_media_read_macaddr_with_lock(uint8_t mac[6],uint8_t reload) +{ + int ret; + + __disable_irq(); + ret=mfg_media_read_macaddr_need_lock(mac,reload); + __enable_irq(); + + return ret; +} + diff --git a/drivers/bl602_driver/std_drv/src/bl602_pds.c b/drivers/bl602_driver/std_drv/src/bl602_pds.c new file mode 100644 index 00000000..6cfc96b7 --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_pds.c @@ -0,0 +1,816 @@ +/** + ****************************************************************************** + * @file bl602_pds.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602.h" +#include "bl602_pds.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup PDS + * @{ + */ + +/** @defgroup PDS_Private_Macros + * @{ + */ + +/*@} end of group PDS_Private_Macros */ + +/** @defgroup PDS_Private_Types + * @{ + */ + +/*@} end of group PDS_Private_Types */ + +/** @defgroup PDS_Private_Variables + * @{ + */ +static intCallback_Type * pdsIntCbfArra[4][1]={{NULL},{NULL},{NULL},{NULL}}; + + +/*@} end of group PDS_Private_Variables */ + +/** @defgroup PDS_Global_Variables + * @{ + */ + +/*@} end of group PDS_Global_Variables */ + +/** @defgroup PDS_Private_Fun_Declaration + * @{ + */ + +/*@} end of group PDS_Private_Fun_Declaration */ + +/** @defgroup PDS_Private_Functions + * @{ + */ + +/*@} end of group PDS_Private_Functions */ + +/** @defgroup PDS_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief PDS software reset + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION PDS_Reset(void) +{ + uint32_t tmpVal = 0; + + tmpVal = *(uint32_t *)0x40000014; + tmpVal = tmpVal | (1<<14); + *(uint32_t *)0x40000014 = tmpVal; + + tmpVal = *(uint32_t *)0x40000014; + tmpVal = tmpVal & ~(1<<14); + *(uint32_t *)0x40000014 = tmpVal; + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief Enable power down sleep + * + * @param cfg: power down sleep configuration 1 + * @param cfg4: power down sleep configuration 2 + * @param pdsSleepCnt: power down sleep count cycle + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION PDS_Enable(PDS_CTL_Type *cfg,PDS_CTL4_Type *cfg4,uint32_t pdsSleepCnt) +{ + + /* PDS sleep time 0 <=> sleep forever */ + /* PDS sleep time 1~PDS_WARMUP_LATENCY_CNT <=> error */ + /* PDS sleep time >PDS_WARMUP_LATENCY_CNT <=> correct */ + if(!pdsSleepCnt){ + cfg->sleepForever = 1; + }else if((pdsSleepCnt)&&(pdsSleepCnt<=PDS_WARMUP_LATENCY_CNT)){ + return ERROR; + }else{ + BL_WR_REG(PDS_BASE,PDS_TIME1,pdsSleepCnt-PDS_WARMUP_LATENCY_CNT); + } + + /* PDS_CTL4 config */ + BL_WR_REG(PDS_BASE,PDS_CTL4,*(uint32_t *)cfg4); + + /* PDS_CTL config */ + if(cfg->pdsStart){ + BL_WR_REG(PDS_BASE,PDS_CTL,(*(uint32_t *)cfg&~(1<<0))); + BL_WR_REG(PDS_BASE,PDS_CTL,(*(uint32_t *)cfg|(1<<0))); + }else{ + BL_WR_REG(PDS_BASE,PDS_CTL,*(uint32_t *)cfg); + } + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief power down sleep force configure + * + * @param cfg2: power down sleep force configuration 1 + * @param cfg3: power down sleep force configuration 2 + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION PDS_Force_Config(PDS_CTL2_Type *cfg2,PDS_CTL3_Type *cfg3) +{ + /* PDS_CTL2 config */ + BL_WR_REG(PDS_BASE,PDS_CTL2,*(uint32_t *)cfg2); + + /* PDS_CTL3 config */ + BL_WR_REG(PDS_BASE,PDS_CTL3,*(uint32_t *)cfg3); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief power down sleep ram configure + * + * @param ramCfg: power down sleep force ram configuration + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg) +{ + uint32_t tmpVal = 0; + + if(NULL==ramCfg){ + return SUCCESS; + } + tmpVal = BL_RD_REG(GLB_BASE,GLB_MBIST_CTL); + /* enter bist mode (make ram idle/slp) */ + //tmpVal = tmpVal&~0x1F; + //tmpVal = tmpVal|0x18; + /* enter bist mode (make ram ret) */ + tmpVal = tmpVal|(0x1<<3); + BL_WR_REG(GLB_BASE,GLB_MBIST_CTL,tmpVal); + + /* PDS_RAM1 config */ + BL_WR_REG(PDS_BASE,PDS_RAM1,*(uint32_t *)ramCfg); + + tmpVal = BL_RD_REG(GLB_BASE,GLB_MBIST_CTL); + /* exit bist mode (make ram idle/slp) */ + //tmpVal = tmpVal&~0x1F; + /* exit bist mode (make ram ret) */ + tmpVal = tmpVal&~(0x1<<3); + BL_WR_REG(GLB_BASE,GLB_MBIST_CTL,tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief power down sleep force configure + * + * @param defaultLvCfg: power down sleep default level configuration + * @param ramCfg: ram configuration + * @param pdsSleepCnt: power down sleep time count + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg,PDS_RAM_CFG_Type *ramCfg,uint32_t pdsSleepCnt) +{ + /* RAM config need fix after ECO */ + PDS_RAM_Config(ramCfg); + PDS_Force_Config((PDS_CTL2_Type *)&(defaultLvCfg->pdsCtl2),(PDS_CTL3_Type *)&(defaultLvCfg->pdsCtl3)); + PDS_Enable((PDS_CTL_Type *)&(defaultLvCfg->pdsCtl),(PDS_CTL4_Type *)&(defaultLvCfg->pdsCtl4),pdsSleepCnt); + + return SUCCESS; +} +#endif + +/****************************************************************************//** + * @brief power down sleep int mask + * + * @param intType: PDS int type + * @param intMask: MASK or UNMASK + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type PDS_IntMask(PDS_INT_Type intType,BL_Mask_Type intMask) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(PDS_BASE,PDS_INT); + if(intMask!=UNMASK){ + tmpVal = tmpVal|(1<<(intType+PDS_INT_MASK_BIT_OFFSET)); + }else{ + tmpVal = tmpVal&~(1<<(intType+PDS_INT_MASK_BIT_OFFSET)); + } + BL_WR_REG(PDS_BASE,PDS_INT,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief get power down sleep int status + * + * @param intType: PDS int type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType) +{ + return (BL_RD_REG(PDS_BASE,PDS_INT)&(1<
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_pwm.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup PWM + * @{ + */ + +/** @defgroup PWM_Private_Macros + * @{ + */ +#define PWM_Get_Channel_Reg(ch) (PWM_BASE+PWM_CHANNEL_OFFSET+(ch)*0x20) +#define PWM_INT_TIMEOUT_COUNT (160*1000) +#define PWM_STOP_TIMEOUT_COUNT (160*1000) + +/*@} end of group PWM_Private_Macros */ + +/** @defgroup PWM_Private_Types + * @{ + */ + +/*@} end of group PWM_Private_Types */ + +/** @defgroup PWM_Private_Variables + * @{ + */ + +/** + * @brief PWM interrupt callback function address array + */ +static intCallback_Type * PWMIntCbfArra[PWM_CH_MAX][PWM_INT_ALL]= { + {NULL} +}; + + +/*@} end of group PWM_Private_Variables */ + +/** @defgroup PWM_Global_Variables + * @{ + */ + +/*@} end of group PWM_Global_Variables */ + +/** @defgroup PWM_Private_Fun_Declaration + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +static BL_Err_Type PWM_IntHandler(IRQn_Type intPeriph); +#endif + +/*@} end of group PWM_Private_Fun_Declaration */ + +/** @defgroup PWM_Private_Functions + * @{ + */ + +/****************************************************************************//** + * @brief PWM interrupt handle + * + * @param intPeriph: Select the peripheral, such as PWM0_IRQn + * + * @return SUCCESS + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +static BL_Err_Type PWM_IntHandler(IRQn_Type intPeriph) +{ + uint32_t i; + uint32_t tmpVal; + uint32_t timeoutCnt = PWM_INT_TIMEOUT_COUNT; + /* Get channel register */ + uint32_t PWMx = PWM_BASE; + + for (i = 0; i < PWM_CH_MAX; i++) { + tmpVal = BL_RD_REG(PWMx, PWM_INT_CONFIG); + if ((BL_GET_REG_BITS_VAL(tmpVal, PWM_INTERRUPT_STS) & (1 << i)) != 0) { + /* Clear interrupt */ + tmpVal |= (1 << (i + PWM_INT_CLEAR_POS)); + BL_WR_REG(PWMx, PWM_INT_CONFIG, tmpVal); + /* FIXME: we need set pwm_int_clear to 0 by software and + before this,we must make sure pwm_interrupt_sts is 0*/ + do{ + tmpVal = BL_RD_REG(PWMx, PWM_INT_CONFIG); + timeoutCnt--; + if(timeoutCnt == 0){ + break; + } + }while(BL_GET_REG_BITS_VAL(tmpVal,PWM_INTERRUPT_STS)&(1 << i)); + + tmpVal &= (~(1 << (i + PWM_INT_CLEAR_POS))); + BL_WR_REG(PWMx, PWM_INT_CONFIG, tmpVal); + if (PWMIntCbfArra[i][PWM_INT_PULSE_CNT] != NULL) { + /* Call the callback function */ + PWMIntCbfArra[i][PWM_INT_PULSE_CNT](); + } + } + } + return SUCCESS; +} +#endif + +/*@} end of group PWM_Private_Functions */ + +/** @defgroup PWM_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief PWM channel init + * + * @param chCfg: PWM configuration + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type PWM_Channel_Init(PWM_CH_CFG_Type *chCfg) +{ + uint32_t tmpVal; + uint32_t timeoutCnt = PWM_STOP_TIMEOUT_COUNT; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(chCfg->ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(chCfg->ch)); + CHECK_PARAM(IS_PWM_CLK_TYPE(chCfg->clk)); + CHECK_PARAM(IS_PWM_POLARITY_TYPE(chCfg->pol)); + CHECK_PARAM(IS_PWM_STOP_MODE_TYPE(chCfg->stopMode)); + + /* Config pwm clock and polarity */ + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN)); + while(!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)){ + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + } + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL, chCfg->clk); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_OUT_INV, chCfg->pol); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_STOP_MODE, chCfg->stopMode); + BL_WR_REG(PWMx, PWM_CONFIG, tmpVal); + + /* Config pwm division */ + BL_WR_REG(PWMx, PWM_CLKDIV, chCfg->clkDiv); + + /* Config pwm period and duty */ + BL_WR_REG(PWMx, PWM_THRE1, chCfg->threshold1); + BL_WR_REG(PWMx, PWM_THRE2, chCfg->threshold2); + BL_WR_REG(PWMx, PWM_PERIOD, chCfg->period); + + /* Config interrupt pulse count */ + tmpVal = BL_RD_REG(PWMx, PWM_INTERRUPT); + BL_WR_REG(PWMx, PWM_INTERRUPT, BL_SET_REG_BITS_VAL(tmpVal, PWM_INT_PERIOD_CNT, chCfg->intPulseCnt)); + PWM_IntMask(chCfg->ch,PWM_INT_PULSE_CNT,chCfg->intPulseCnt!=0?UNMASK:MASK); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(PWM_IRQn,PWM_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************//** + * @brief PWM channel update source memory address and len + * + * @param ch: PWM channel + * @param period: period + * @param threshold1: threshold1 + * @param threshold2: threshold2 + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Update(PWM_CH_ID_Type ch,uint16_t period,uint16_t threshold1,uint16_t threshold2) +{ + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + /* Config pwm period and duty */ + BL_WR_REG(PWMx, PWM_THRE1, threshold1); + BL_WR_REG(PWMx, PWM_THRE2, threshold2); + BL_WR_REG(PWMx, PWM_PERIOD, period); +} + +/****************************************************************************//** + * @brief PWM channel update clock divider + * + * @param ch: PWM channel + * @param div: Clock divider + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Set_Div(PWM_CH_ID_Type ch,uint16_t div) +{ + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + BL_WR_REG(PWMx, PWM_CLKDIV, div); +} + +/****************************************************************************//** + * @brief PWM channel update threshold1 + * + * @param ch: PWM channel + * @param threshold1: threshold1 + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Set_Threshold1(PWM_CH_ID_Type ch,uint16_t threshold1) +{ + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + /* Config pwm period and duty */ + BL_WR_REG(PWMx, PWM_THRE1, threshold1); +} + +/****************************************************************************//** + * @brief PWM channel update threshold2 + * + * @param ch: PWM channel + * @param threshold2: threshold2 + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Set_Threshold2(PWM_CH_ID_Type ch,uint16_t threshold2) +{ + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + /* Config pwm period and duty */ + BL_WR_REG(PWMx, PWM_THRE2, threshold2); +} + +/****************************************************************************//** + * @brief PWM channel update period + * + * @param ch: PWM channel + * @param period: period + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Set_Period(PWM_CH_ID_Type ch,uint16_t period) +{ + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + /* Config pwm period and duty */ + BL_WR_REG(PWMx, PWM_PERIOD, period); +} + +/****************************************************************************//** + * @brief PWM get configuration + * + * @param ch: PWM channel + * @param period: period pointer + * @param threshold1: threshold1 pointer + * @param threshold2: threshold2 pointer + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Get(PWM_CH_ID_Type ch,uint16_t *period,uint16_t *threshold1,uint16_t *threshold2) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + /* get pwm period and duty */ + tmpVal = BL_RD_REG(PWMx, PWM_THRE1); + *threshold1 = BL_GET_REG_BITS_VAL(tmpVal, PWM_THRE1); + tmpVal = BL_RD_REG(PWMx, PWM_THRE2); + *threshold2 = BL_GET_REG_BITS_VAL(tmpVal, PWM_THRE2); + tmpVal = BL_RD_REG(PWMx, PWM_PERIOD); + *period = BL_GET_REG_BITS_VAL(tmpVal, PWM_PERIOD); +} + +/****************************************************************************//** + * @brief PWM enable + * + * @param ch: PWM channel number + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Enable(PWM_CH_ID_Type ch) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + /* Config pwm clock to enable pwm */ + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + BL_WR_REG(PWMx, PWM_CONFIG, BL_CLR_REG_BIT(tmpVal, PWM_STOP_EN)); +} + +/****************************************************************************//** + * @brief PWM disable + * + * @param ch: PWM channel number + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Disable(PWM_CH_ID_Type ch) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + /* Config pwm clock to disable pwm */ + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN)); + PWM_IntMask(ch,PWM_INT_PULSE_CNT,MASK); +} + +/****************************************************************************//** + * @brief PWM channel software mode enable or disable + * + * @param ch: PWM channel number + * @param enable: Enable or disable + * + * @return None + * +*******************************************************************************/ +void PWM_SW_Mode(PWM_CH_ID_Type ch,BL_Fun_Type enable) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + tmpVal = BL_RD_REG(PWMx,PWM_CONFIG); + BL_WR_REG(PWMx,PWM_CONFIG,BL_SET_REG_BITS_VAL(tmpVal,PWM_SW_MODE,enable)); +} + +/****************************************************************************//** + * @brief PWM channel force output high or low + * + * @param ch: PWM channel number + * @param value: Output value + * + * @return None + * +*******************************************************************************/ +void PWM_SW_Force_Value(PWM_CH_ID_Type ch,uint8_t value) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + tmpVal = BL_RD_REG(PWMx,PWM_CONFIG); + BL_WR_REG(PWMx,PWM_CONFIG,BL_SET_REG_BITS_VAL(tmpVal,PWM_SW_FORCE_VAL,value)); +} + + +/****************************************************************************//** + * @brief PWM channel force output high + * + * @param ch: PWM channel number + * + * @return None + * +*******************************************************************************/ +void PWM_Channel_Fource_Output(PWM_CH_ID_Type ch) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_SW_MODE)); +} + +/****************************************************************************//** + * @brief Mask/Unmask the PWM interrupt + * + * @param ch: PWM channel number + * @param intType: Specifies the interrupt type + * @param intMask: Enable/Disable Specified interrupt type + * + * @return None + * +*******************************************************************************/ +void PWM_IntMask(PWM_CH_ID_Type ch,PWM_INT_Type intType,BL_Mask_Type intMask) +{ + uint32_t tmpVal; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + /* Check the parameters */ + CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch)); + CHECK_PARAM(IS_PWM_INT_TYPE(intType)); + + tmpVal = BL_RD_REG(PWMx, PWM_INTERRUPT); + + switch(intType) { + case PWM_INT_PULSE_CNT: + if(intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + BL_WR_REG(PWMx, PWM_INTERRUPT, BL_SET_REG_BIT(tmpVal, PWM_INT_ENABLE)); + } + else { + /* MASK(Disable) this interrupt */ + BL_WR_REG(PWMx, PWM_INTERRUPT, BL_CLR_REG_BIT(tmpVal, PWM_INT_ENABLE)); + } + break; + case PWM_INT_ALL: + if(intMask == UNMASK) { + /* UNMASK(Enable) this interrupt */ + BL_WR_REG(PWMx, PWM_INTERRUPT, BL_SET_REG_BIT(tmpVal, PWM_INT_ENABLE)); + } + else { + /* MASK(Disable) this interrupt */ + BL_WR_REG(PWMx, PWM_INTERRUPT, BL_CLR_REG_BIT(tmpVal, PWM_INT_ENABLE)); + } + break; + + default: + break; + } +} + +/****************************************************************************//** + * @brief Install PWM interrupt callback function + * + * @param ch: PWM channel number + * @param intType: PWM interrupt type + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return None + * +*******************************************************************************/ +void PWM_Int_Callback_Install(PWM_CH_ID_Type ch,uint32_t intType,intCallback_Type* cbFun) +{ + PWMIntCbfArra[ch][intType] = cbFun; +} + +/****************************************************************************//** + * @brief PWM smart configure according to frequency and duty cycle function + * + * @param ch: PWM channel number + * @param frequency: PWM frequency + * @param dutyCycle: PWM duty cycle + * + * @return SUCCESS or TIMEOUT + * +*******************************************************************************/ +BL_Err_Type PWM_Smart_Configure(PWM_CH_ID_Type ch,uint32_t frequency,uint8_t dutyCycle) +{ + uint32_t tmpVal; + uint16_t clkDiv,period,threshold2; + uint32_t timeoutCnt = PWM_STOP_TIMEOUT_COUNT; + /* Get channel register */ + uint32_t PWMx = PWM_Get_Channel_Reg(ch); + + if(frequency <= 78){ + clkDiv = 1250; + period = 64000/frequency; + threshold2 = 640*dutyCycle/frequency; + }else if(frequency <= 155){ + clkDiv = 16; + period = 5000000/frequency; + threshold2 = 50000*dutyCycle/frequency; + }else if(frequency <= 310){ + clkDiv = 8; + period = 10000000/frequency; + threshold2 = 100000*dutyCycle/frequency; + }else if(frequency <=620){ + clkDiv = 4; + period = 20000000/frequency; + threshold2 = 200000*dutyCycle/frequency; + }else if(frequency <=1230){ + clkDiv = 2; + period = 40000000/frequency; + threshold2 = 400000*dutyCycle/frequency; + }else{ + clkDiv = 1; + period = 80000000/frequency; + threshold2 = 800000*dutyCycle/frequency; + } + + tmpVal = BL_RD_REG(PWMx, PWM_CONFIG); + if(BL_GET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL) != 1){ + BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN)); + while(!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)){ + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + } + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL, PWM_CLK_BCLK); + } + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_OUT_INV, PWM_POL_NORMAL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_STOP_MODE, PWM_STOP_GRACEFUL); + BL_WR_REG(PWMx, PWM_CONFIG, tmpVal); + + /* Config pwm division */ + BL_WR_REG(PWMx, PWM_CLKDIV, clkDiv); + + /* Config pwm period and duty */ + BL_WR_REG(PWMx, PWM_PERIOD, period); + BL_WR_REG(PWMx, PWM_THRE1, 0); + BL_WR_REG(PWMx, PWM_THRE2, threshold2); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief PWM interrupt function + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void PWM_IRQHandler(void) +{ + PWM_IntHandler(PWM_IRQn); +} +#endif + +/*@} end of group PWM_Public_Functions */ + +/*@} end of group PWM */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/bl602_driver/std_drv/src/bl602_romapi.c b/drivers/bl602_driver/std_drv/src/bl602_romapi.c new file mode 100644 index 00000000..33f48c80 --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_romapi.c @@ -0,0 +1,872 @@ +#include "bl602_romdriver.h" + + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void){ + return RomDriver_AON_Power_On_MBG(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void){ + return RomDriver_AON_Power_Off_MBG(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void){ + return RomDriver_AON_Power_On_XTAL(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn,uint8_t capOut){ + return RomDriver_AON_Set_Xtal_CapCode(capIn,capOut); +} + +__ALWAYS_INLINE +uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void){ + return RomDriver_AON_Get_Xtal_CapCode(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void){ + return RomDriver_AON_Power_Off_XTAL(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void){ + return RomDriver_AON_Power_On_BG(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void){ + return RomDriver_AON_Power_Off_BG(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO11_SOC(void){ + return RomDriver_AON_Power_On_LDO11_SOC(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO11_SOC(void){ + return RomDriver_AON_Power_Off_LDO11_SOC(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void){ + return RomDriver_AON_Power_On_LDO15_RF(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO15_RF(void){ + return RomDriver_AON_Power_Off_LDO15_RF(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void){ + return RomDriver_AON_Power_On_SFReg(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void){ + return RomDriver_AON_Power_Off_SFReg(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Enter_PDS0(void){ + return RomDriver_AON_LowPower_Enter_PDS0(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void){ + return RomDriver_AON_LowPower_Exit_PDS0(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core,uint32_t cnt){ + return RomDriver_ASM_Delay_Us(core,cnt); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION BL602_Delay_US(uint32_t cnt){ + return RomDriver_BL602_Delay_US(cnt); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION BL602_Delay_MS(uint32_t cnt){ + return RomDriver_BL602_Delay_MS(cnt); +} + +__ALWAYS_INLINE +void* ATTR_TCM_SECTION BL602_MemCpy(void *dst, const void *src, uint32_t n){ + return RomDriver_BL602_MemCpy(dst,src,n); +} + +__ALWAYS_INLINE +uint32_t* ATTR_TCM_SECTION BL602_MemCpy4(uint32_t *dst, const uint32_t *src, uint32_t n){ + return RomDriver_BL602_MemCpy4(dst,src,n); +} + +__ALWAYS_INLINE +void* ATTR_TCM_SECTION BL602_MemCpy_Fast(void *pdst, const void *psrc, uint32_t n){ + return RomDriver_BL602_MemCpy_Fast(pdst,psrc,n); +} + +__ALWAYS_INLINE +void* ATTR_TCM_SECTION BL602_MemSet(void *s, uint8_t c, uint32_t n){ + return RomDriver_BL602_MemSet(s,c,n); +} + +__ALWAYS_INLINE +uint32_t* ATTR_TCM_SECTION BL602_MemSet4(uint32_t *dst, const uint32_t val, uint32_t n){ + return RomDriver_BL602_MemSet4(dst,val,n); +} + +__ALWAYS_INLINE +int ATTR_TCM_SECTION BL602_MemCmp(const void *s1, const void *s2, uint32_t n){ + return RomDriver_BL602_MemCmp(s1,s2,n); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION EF_Ctrl_Sw_AHB_Clk_0(void){ + return RomDriver_EF_Ctrl_Sw_AHB_Clk_0(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION EF_Ctrl_Program_Efuse_0(void){ + return RomDriver_EF_Ctrl_Program_Efuse_0(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION EF_Ctrl_Load_Efuse_R0(void){ + return RomDriver_EF_Ctrl_Load_Efuse_R0(); +} + +__ALWAYS_INLINE +BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_Busy(void){ + return RomDriver_EF_Ctrl_Busy(); +} + +__ALWAYS_INLINE +BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_AutoLoad_Done(void){ + return RomDriver_EF_Ctrl_AutoLoad_Done(); +} + +__ALWAYS_INLINE +uint8_t ATTR_CLOCK_SECTION EF_Ctrl_Get_Trim_Parity(uint32_t val,uint8_t len){ + return RomDriver_EF_Ctrl_Get_Trim_Parity(val,len); +} + +__ALWAYS_INLINE +void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32M_Trim( Efuse_Ana_RC32M_Trim_Type *trim){ + return RomDriver_EF_Ctrl_Read_RC32M_Trim(trim); +} + +__ALWAYS_INLINE +void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32K_Trim( Efuse_Ana_RC32K_Trim_Type *trim){ + return RomDriver_EF_Ctrl_Read_RC32K_Trim(trim); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION EF_Ctrl_Clear(uint32_t index, uint32_t len){ + return RomDriver_EF_Ctrl_Clear(index,len); +} + +__ALWAYS_INLINE +GLB_ROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_Root_CLK_Sel(void){ + return RomDriver_GLB_Get_Root_CLK_Sel(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK_Div(uint8_t hclkDiv,uint8_t bclkDiv){ + return RomDriver_GLB_Set_System_CLK_Div(hclkDiv,bclkDiv); +} + +__ALWAYS_INLINE +uint8_t ATTR_CLOCK_SECTION GLB_Get_BCLK_Div(void){ + return RomDriver_GLB_Get_BCLK_Div(); +} + +__ALWAYS_INLINE +uint8_t ATTR_CLOCK_SECTION GLB_Get_HCLK_Div(void){ + return RomDriver_GLB_Get_HCLK_Div(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION Update_SystemCoreClockWith_XTAL(GLB_PLL_XTAL_Type xtalType){ + return RomDriver_Update_SystemCoreClockWith_XTAL(xtalType); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK(GLB_PLL_XTAL_Type xtalType,GLB_SYS_CLK_Type clkFreq){ + return RomDriver_GLB_Set_System_CLK(xtalType,clkFreq); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION System_Core_Clock_Update_From_RC32M(void){ + return RomDriver_System_Core_Clock_Update_From_RC32M(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_SF_CLK(uint8_t enable,GLB_SFLASH_CLK_Type clkSel,uint8_t div){ + return RomDriver_GLB_Set_SF_CLK(enable,clkSel,div); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel){ + return RomDriver_GLB_Set_PKA_CLK_Sel(clkSel); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_SW_System_Reset(void){ + return RomDriver_GLB_SW_System_Reset(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_SW_CPU_Reset(void){ + return RomDriver_GLB_SW_CPU_Reset(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_SW_POR_Reset(void){ + return RomDriver_GLB_SW_POR_Reset(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_Select_Internal_Flash(void){ + return RomDriver_GLB_Select_Internal_Flash(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_Select_External_Flash(void){ + return RomDriver_GLB_Select_External_Flash(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_Deswap_Flash_Pin(void){ + return RomDriver_GLB_Deswap_Flash_Pin(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_Swap_Flash_Pin(void){ + return RomDriver_GLB_Swap_Flash_Pin(); +} + +#if 0 +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg){ + return RomDriver_GLB_GPIO_Init(cfg); +} +#endif + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin){ + return RomDriver_GLB_GPIO_OUTPUT_Enable(gpioPin); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin){ + return RomDriver_GLB_GPIO_OUTPUT_Disable(gpioPin); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin){ + return RomDriver_GLB_GPIO_Set_HZ(gpioPin); +} + +__ALWAYS_INLINE +uint8_t ATTR_TCM_SECTION GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin){ + return RomDriver_GLB_GPIO_Get_Fun(gpioPin); +} + +#if 0 +__ALWAYS_INLINE +void ATTR_TCM_SECTION HBN_Mode_Enter(HBN_APP_CFG_Type *cfg){ + return RomDriver_HBN_Mode_Enter(cfg); +} +#endif + +__ALWAYS_INLINE +void ATTR_TCM_SECTION HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg){ + return RomDriver_HBN_Power_Down_Flash(flashCfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION HBN_Enable(uint8_t aGPIOIeCfg,HBN_LDO_LEVEL_Type ldoLevel,HBN_LEVEL_Type hbnLevel){ + return RomDriver_HBN_Enable(aGPIOIeCfg,ldoLevel,hbnLevel); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_Reset(void){ + return RomDriver_HBN_Reset(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel){ + return RomDriver_HBN_Set_Ldo11_Aon_Vout(ldoLevel); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel){ + return RomDriver_HBN_Set_Ldo11_Rt_Vout(ldoLevel); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel){ + return RomDriver_HBN_Set_Ldo11_Soc_Vout(ldoLevel); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION HBN_32K_Sel(HBN_32K_CLK_Type clkType){ + return RomDriver_HBN_32K_Sel(clkType); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk){ + return RomDriver_HBN_Set_ROOT_CLK_Sel(rootClk); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_Xtal_32K(void){ + return RomDriver_HBN_Power_On_Xtal_32K(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_Xtal_32K(void){ + return RomDriver_HBN_Power_Off_Xtal_32K(); +} + +#if 0 +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_RC32K(void){ + return RomDriver_HBN_Power_On_RC32K(); +} +#endif + +#if 0 +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_RC32K(void){ + return RomDriver_HBN_Power_Off_RC32K(); +} +#endif + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION HBN_Trim_RC32K(void){ + return RomDriver_HBN_Trim_RC32K(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_Hw_Pu_Pd_Cfg(uint8_t enable){ + return RomDriver_HBN_Hw_Pu_Pd_Cfg(enable); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_Pin_WakeUp_Mask(uint8_t maskVal){ + return RomDriver_HBN_Pin_WakeUp_Mask(maskVal); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_GPIO7_Dbg_Pull_Cfg(BL_Fun_Type pupdEn,BL_Fun_Type iesmtEn,BL_Fun_Type dlyEn,uint8_t dlySec){ + return RomDriver_HBN_GPIO7_Dbg_Pull_Cfg(pupdEn,iesmtEn,dlyEn,dlySec); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Embedded_Flash_Pullup(uint8_t enable){ + return RomDriver_HBN_Set_Embedded_Flash_Pullup(enable); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION L1C_Set_Wrap(BL_Fun_Type wrap){ + return RomDriver_L1C_Set_Wrap(wrap); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION L1C_Set_Way_Disable(uint8_t disableVal){ + return RomDriver_L1C_Set_Way_Disable(disableVal); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION L1C_IROM_2T_Access_Set(uint8_t enable){ + return RomDriver_L1C_IROM_2T_Access_Set(enable); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION PDS_Reset(void){ + return RomDriver_PDS_Reset(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION PDS_Enable(PDS_CTL_Type *cfg,PDS_CTL4_Type *cfg4,uint32_t pdsSleepCnt){ + return RomDriver_PDS_Enable(cfg,cfg4,pdsSleepCnt); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION PDS_Force_Config(PDS_CTL2_Type *cfg2,PDS_CTL3_Type *cfg3){ + return RomDriver_PDS_Force_Config(cfg2,cfg3); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg){ + return RomDriver_PDS_RAM_Config(ramCfg); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg,PDS_RAM_CFG_Type *ramCfg,uint32_t pdsSleepCnt){ + return RomDriver_PDS_Default_Level_Config(defaultLvCfg,ramCfg,pdsSleepCnt); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Trim_RC32M(void){ + return RomDriver_PDS_Trim_RC32M(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_RC32M_As_PLL_Ref(void){ + return RomDriver_PDS_Select_RC32M_As_PLL_Ref(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_XTAL_As_PLL_Ref(void){ + return RomDriver_PDS_Select_XTAL_As_PLL_Ref(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType){ + return RomDriver_PDS_Power_On_PLL(xtalType); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_All_Clks(void){ + return RomDriver_PDS_Enable_PLL_All_Clks(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_All_Clks(void){ + return RomDriver_PDS_Disable_PLL_All_Clks(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk){ + return RomDriver_PDS_Enable_PLL_Clk(pllClk); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk){ + return RomDriver_PDS_Disable_PLL_Clk(pllClk); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_Off_PLL(void){ + return RomDriver_PDS_Power_Off_PLL(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SEC_Eng_Turn_On_Sec_Ring(void){ + return RomDriver_SEC_Eng_Turn_On_Sec_Ring(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SEC_Eng_Turn_Off_Sec_Ring(void){ + return RomDriver_SEC_Eng_Turn_Off_Sec_Ring(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg){ + return RomDriver_SFlash_Init(pSfCtrlCfg); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode){ + return RomDriver_SFlash_SetSPIMode(mode); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg,uint8_t regIndex,uint8_t *regValue,uint8_t regLen){ + return RomDriver_SFlash_Read_Reg(flashCfg,regIndex,regValue,regLen); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg,uint8_t regIndex,uint8_t *regValue,uint8_t regLen){ + return RomDriver_SFlash_Write_Reg(flashCfg,regIndex,regValue,regLen); +} + +__ALWAYS_INLINE +BL_Sts_Type ATTR_TCM_SECTION SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg){ + return RomDriver_SFlash_Busy(flashCfg); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg){ + return RomDriver_SFlash_Write_Enable(flashCfg); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg){ + return RomDriver_SFlash_Qspi_Enable(flashCfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg){ + return RomDriver_SFlash_Volatile_Reg_Write_Enable(flashCfg); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg){ + return RomDriver_SFlash_Chip_Erase(flashCfg); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg,uint32_t secNum){ + return RomDriver_SFlash_Sector_Erase(flashCfg,secNum); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg,uint32_t blkNum){ + return RomDriver_SFlash_Blk32_Erase(flashCfg,blkNum); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg,uint32_t blkNum){ + return RomDriver_SFlash_Blk64_Erase(flashCfg,blkNum); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg,uint32_t startaddr,uint32_t endaddr){ + return RomDriver_SFlash_Erase(flashCfg,startaddr,endaddr); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Program(SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint32_t addr,uint8_t *data, uint32_t len){ + return RomDriver_SFlash_Program(flashCfg,ioMode,addr,data,len); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_GetUniqueId(uint8_t *data,uint8_t idLen){ + return RomDriver_SFlash_GetUniqueId(data,idLen); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg,uint8_t *data){ + return RomDriver_SFlash_GetJedecId(flashCfg,data); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_GetDeviceId(uint8_t *data){ + return RomDriver_SFlash_GetDeviceId(data); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_Powerdown(void){ + return RomDriver_SFlash_Powerdown(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg){ + return RomDriver_SFlash_Releae_Powerdown(flashCfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg){ + return RomDriver_SFlash_SetBurstWrap(flashCfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg){ + return RomDriver_SFlash_DisableBurstWrap(flashCfg); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg){ + return RomDriver_SFlash_Software_Reset(flashCfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg){ + return RomDriver_SFlash_Reset_Continue_Read(flashCfg); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint8_t contRead,uint32_t addr,uint32_t len){ + return RomDriver_SFlash_Set_IDbus_Cfg(flashCfg,ioMode,contRead,addr,len); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint8_t contRead){ + return RomDriver_SFlash_IDbus_Read_Enable(flashCfg,ioMode,contRead); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Enable_Set(uint8_t wayDisable){ + return RomDriver_SFlash_Cache_Enable_Set(wayDisable); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Flush(void){ + return RomDriver_SFlash_Cache_Flush(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint8_t contRead,uint8_t wayDisable){ + return RomDriver_SFlash_Cache_Read_Enable(flashCfg,ioMode,contRead,wayDisable); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_Cache_Hit_Count_Get(uint32_t *hitCountLow,uint32_t *hitCountHigh){ + return RomDriver_SFlash_Cache_Hit_Count_Get(hitCountLow,hitCountHigh); +} + +__ALWAYS_INLINE +uint32_t ATTR_TCM_SECTION SFlash_Cache_Miss_Count_Get(void){ + return RomDriver_SFlash_Cache_Miss_Count_Get(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_Cache_Read_Disable(void){ + return RomDriver_SFlash_Cache_Read_Disable(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Read(SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint8_t contRead,uint32_t addr,uint8_t *data, uint32_t len){ + return RomDriver_SFlash_Read(flashCfg,ioMode,contRead,addr,data,len); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg,uint8_t readRegCmd,uint8_t *regValue,uint8_t regLen){ + return RomDriver_SFlash_Read_Reg_With_Cmd(flashCfg,readRegCmd,regValue,regLen); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg,uint8_t writeRegCmd,uint8_t *regValue,uint8_t regLen){ + return RomDriver_SFlash_Write_Reg_With_Cmd(flashCfg,writeRegCmd,regValue,regLen); +} + +#if 0 +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t flashContRead){ + return RomDriver_SFlash_Restore_From_Powerdown(pFlashCfg,flashContRead); +} +#endif + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin){ + return RomDriver_SF_Cfg_Init_Ext_Flash_Gpio(extFlashPin); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Cfg_Init_Internal_Flash_Gpio(void){ + return RomDriver_SF_Cfg_Init_Internal_Flash_Gpio(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin){ + return RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio(extFlashPin); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Cfg_Restore_GPIO17_Fun(uint8_t fun){ + return RomDriver_SF_Cfg_Restore_GPIO17_Fun(fun); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID,SPI_Flash_Cfg_Type * pFlashCfg){ + return RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID,pFlashCfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg,uint8_t restoreDefault){ + return RomDriver_SF_Cfg_Init_Flash_Gpio(flashPinCfg,restoreDefault); +} + +__ALWAYS_INLINE +uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify(uint8_t callFromFlash,uint32_t autoScan,uint32_t flashPinCfg,uint8_t restoreDefault,SPI_Flash_Cfg_Type * pFlashCfg){ + return RomDriver_SF_Cfg_Flash_Identify(callFromFlash,autoScan,flashPinCfg,restoreDefault,pFlashCfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg){ + return RomDriver_SF_Ctrl_Enable(cfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Sel sel){ + return RomDriver_SF_Ctrl_Select_Pad(sel); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner){ + return RomDriver_SF_Ctrl_Set_Owner(owner); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Disable(void){ + return RomDriver_SF_Ctrl_Disable(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_BE(void){ + return RomDriver_SF_Ctrl_AES_Enable_BE(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_LE(void){ + return RomDriver_SF_Ctrl_AES_Enable_LE(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Region(uint8_t region,uint8_t enable,uint8_t hwKey,uint32_t startAddr,uint32_t endAddr,uint8_t locked){ + return RomDriver_SF_Ctrl_AES_Set_Region(region,enable,hwKey,startAddr,endAddr,locked); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key(uint8_t region,uint8_t *key, SF_Ctrl_AES_Key_Type keyType){ + return RomDriver_SF_Ctrl_AES_Set_Key(region,key,keyType); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key_BE(uint8_t region,uint8_t *key, SF_Ctrl_AES_Key_Type keyType){ + return RomDriver_SF_Ctrl_AES_Set_Key_BE(region,key,keyType); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV(uint8_t region,uint8_t *iv,uint32_t addrOffset){ + return RomDriver_SF_Ctrl_AES_Set_IV(region,iv,addrOffset); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV_BE(uint8_t region,uint8_t *iv,uint32_t addrOffset){ + return RomDriver_SF_Ctrl_AES_Set_IV_BE(region,iv,addrOffset); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Enable(void){ + return RomDriver_SF_Ctrl_AES_Enable(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Disable(void){ + return RomDriver_SF_Ctrl_AES_Disable(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset){ + return RomDriver_SF_Ctrl_Set_Flash_Image_Offset(addrOffset); +} + +__ALWAYS_INLINE +uint32_t ATTR_TCM_SECTION SF_Ctrl_Get_Flash_Image_Offset(void){ + return RomDriver_SF_Ctrl_Get_Flash_Image_Offset(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType){ + return RomDriver_SF_Ctrl_Select_Clock(sahbType); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg){ + return RomDriver_SF_Ctrl_SendCmd(cfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg,uint8_t cmdValid){ + return RomDriver_SF_Ctrl_Icache_Set(cfg,cmdValid); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Icache2_Set(SF_Ctrl_Cmd_Cfg_Type *cfg,uint8_t cmdValid){ + return RomDriver_SF_Ctrl_Icache2_Set(cfg,cmdValid); +} + +__ALWAYS_INLINE +BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_GetBusyState(void){ + return RomDriver_SF_Ctrl_GetBusyState(); +} + +__ALWAYS_INLINE +uint8_t ATTR_TCM_SECTION SF_Ctrl_Is_AES_Enable(void){ + return RomDriver_SF_Ctrl_Is_AES_Enable(); +} + +__ALWAYS_INLINE +uint8_t ATTR_TCM_SECTION SF_Ctrl_Get_Clock_Delay(void){ + return RomDriver_SF_Ctrl_Get_Clock_Delay(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Set_Clock_Delay(uint8_t delay){ + return RomDriver_SF_Ctrl_Set_Clock_Delay(delay); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t *offset){ + return RomDriver_XIP_SFlash_State_Save(pFlashCfg,offset); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t offset){ + return RomDriver_XIP_SFlash_State_Restore(pFlashCfg,offset); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t startaddr,uint32_t endaddr){ + return RomDriver_XIP_SFlash_Erase_Need_Lock(pFlashCfg,startaddr,endaddr); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr,uint8_t *data, uint32_t len){ + return RomDriver_XIP_SFlash_Write_Need_Lock(pFlashCfg,addr,data,len); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr,uint8_t *data, uint32_t len){ + return RomDriver_XIP_SFlash_Read_Need_Lock(pFlashCfg,addr,data,len); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data){ + return RomDriver_XIP_SFlash_GetJedecId_Need_Lock(pFlashCfg,data); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data){ + return RomDriver_XIP_SFlash_GetDeviceId_Need_Lock(pFlashCfg,data); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data,uint8_t idLen){ + return RomDriver_XIP_SFlash_GetUniqueId_Need_Lock(pFlashCfg,data,idLen); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr,uint8_t *data, uint32_t len){ + return RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock(addr,data,len); +} + +__ALWAYS_INLINE +int ATTR_TCM_SECTION XIP_SFlash_Read_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *dst, int len){ + return RomDriver_XIP_SFlash_Read_With_Lock(pFlashCfg,addr,dst,len); +} + +__ALWAYS_INLINE +int ATTR_TCM_SECTION XIP_SFlash_Write_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *src, int len){ + return RomDriver_XIP_SFlash_Write_With_Lock(pFlashCfg,addr,src,len); +} + +__ALWAYS_INLINE +int ATTR_TCM_SECTION XIP_SFlash_Erase_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, int len){ + return RomDriver_XIP_SFlash_Erase_With_Lock(pFlashCfg,addr,len); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION XIP_SFlash_Opt_Enter(uint8_t *aesEnable){ + return RomDriver_XIP_SFlash_Opt_Enter(aesEnable); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION XIP_SFlash_Opt_Exit(uint8_t aesEnable){ + return RomDriver_XIP_SFlash_Opt_Exit(aesEnable); +} + +__ALWAYS_INLINE +uint32_t ATTR_TCM_SECTION BFLB_Soft_CRC32(void *dataIn, uint32_t len){ + return RomDriver_BFLB_Soft_CRC32(dataIn,len); +} \ No newline at end of file diff --git a/drivers/bl602_driver/std_drv/src/bl602_romdriver.c b/drivers/bl602_driver/std_drv/src/bl602_romdriver.c new file mode 100644 index 00000000..a8f35d52 --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_romdriver.c @@ -0,0 +1,296 @@ +/** + ****************************************************************************** + * @file bl602_romdriver.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_romdriver.h" +#include + +/** @addtogroup BL602_Periph_Driver + * @{ + */ + +/** @defgroup ROMDRIVER + * @brief ROMDRIVER common functions + * @{ + */ + +/** @defgroup ROMDRIVER_Private_Type + * @{ + */ + +/*@} end of group ROMDRIVER_Private_Type*/ + +/** @defgroup ROMDRIVER_Private_Defines + * @{ + */ + +/*@} end of group ROMDRIVER_Private_Defines */ + +/** @defgroup ROMDRIVER_Private_Variables + * @{ + */ + +/*@} end of group ROMDRIVER_Private_Variables */ + +/** @defgroup ROMDRIVER_Global_Variables + * @{ + */ + + +uint32_t const romDriverTable[]={ + 0x06020002, + 0x00000000, + 0x00000000, + 0x00000000, + + + [ROM_API_INDEX_AON_Power_On_MBG] = (uint32_t)AON_Power_On_MBG, + [ROM_API_INDEX_AON_Power_Off_MBG] = (uint32_t)AON_Power_Off_MBG, + [ROM_API_INDEX_AON_Power_On_XTAL] = (uint32_t)AON_Power_On_XTAL, + [ROM_API_INDEX_AON_Set_Xtal_CapCode] = (uint32_t)AON_Set_Xtal_CapCode, + [ROM_API_INDEX_AON_Get_Xtal_CapCode] = (uint32_t)AON_Get_Xtal_CapCode, + [ROM_API_INDEX_AON_Power_Off_XTAL] = (uint32_t)AON_Power_Off_XTAL, + [ROM_API_INDEX_AON_Power_On_BG] = (uint32_t)AON_Power_On_BG, + [ROM_API_INDEX_AON_Power_Off_BG] = (uint32_t)AON_Power_Off_BG, + [ROM_API_INDEX_AON_Power_On_LDO11_SOC] = (uint32_t)AON_Power_On_LDO11_SOC, + [ROM_API_INDEX_AON_Power_Off_LDO11_SOC] = (uint32_t)AON_Power_Off_LDO11_SOC, + [ROM_API_INDEX_AON_Power_On_LDO15_RF] = (uint32_t)AON_Power_On_LDO15_RF, + [ROM_API_INDEX_AON_Power_Off_LDO15_RF] = (uint32_t)AON_Power_Off_LDO15_RF, + [ROM_API_INDEX_AON_Power_On_SFReg] = (uint32_t)AON_Power_On_SFReg, + [ROM_API_INDEX_AON_Power_Off_SFReg] = (uint32_t)AON_Power_Off_SFReg, + [ROM_API_INDEX_AON_LowPower_Enter_PDS0] = (uint32_t)AON_LowPower_Enter_PDS0, + [ROM_API_INDEX_AON_LowPower_Exit_PDS0] = (uint32_t)AON_LowPower_Exit_PDS0, + + [ROM_API_INDEX_ASM_Delay_Us] = (uint32_t)ASM_Delay_Us, + + [ROM_API_INDEX_BL602_Delay_US] = (uint32_t)BL602_Delay_US, + [ROM_API_INDEX_BL602_Delay_MS] = (uint32_t)BL602_Delay_MS, + [ROM_API_INDEX_BL602_MemCpy] = (uint32_t)BL602_MemCpy, + [ROM_API_INDEX_BL602_MemCpy4] = (uint32_t)BL602_MemCpy4, + [ROM_API_INDEX_BL602_MemCpy_Fast] = (uint32_t)BL602_MemCpy_Fast, + [ROM_API_INDEX_BL602_MemSet] = (uint32_t)BL602_MemSet, + [ROM_API_INDEX_BL602_MemSet4] = (uint32_t)BL602_MemSet4, + [ROM_API_INDEX_BL602_MemCmp] = (uint32_t)BL602_MemCmp, + + [ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0] = (uint32_t)EF_Ctrl_Sw_AHB_Clk_0, + [ROM_API_INDEX_EF_Ctrl_Program_Efuse_0] = (uint32_t)EF_Ctrl_Program_Efuse_0, + [ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0] = (uint32_t)EF_Ctrl_Load_Efuse_R0, + [ROM_API_INDEX_EF_Ctrl_Busy] = (uint32_t)EF_Ctrl_Busy, + [ROM_API_INDEX_EF_Ctrl_AutoLoad_Done] = (uint32_t)EF_Ctrl_AutoLoad_Done, + [ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity] = (uint32_t)EF_Ctrl_Get_Trim_Parity, + [ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim] = (uint32_t)EF_Ctrl_Read_RC32M_Trim, + [ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim] = (uint32_t)EF_Ctrl_Read_RC32K_Trim, + [ROM_API_INDEX_EF_Ctrl_Clear] = (uint32_t)EF_Ctrl_Clear, + + [ROM_API_INDEX_GLB_Get_Root_CLK_Sel] = (uint32_t)GLB_Get_Root_CLK_Sel, + [ROM_API_INDEX_GLB_Set_System_CLK_Div] = (uint32_t)GLB_Set_System_CLK_Div, + [ROM_API_INDEX_GLB_Get_BCLK_Div] = (uint32_t)GLB_Get_BCLK_Div, + [ROM_API_INDEX_GLB_Get_HCLK_Div] = (uint32_t)GLB_Get_HCLK_Div, + + [ROM_API_INDEX_Update_SystemCoreClockWith_XTAL] = (uint32_t)Update_SystemCoreClockWith_XTAL, + + [ROM_API_INDEX_GLB_Set_System_CLK] = (uint32_t)GLB_Set_System_CLK, + + [ROM_API_INDEX_System_Core_Clock_Update_From_RC32M] = (uint32_t)System_Core_Clock_Update_From_RC32M, + + [ROM_API_INDEX_GLB_Set_SF_CLK] = (uint32_t)GLB_Set_SF_CLK, + [ROM_API_INDEX_GLB_Set_PKA_CLK_Sel] = (uint32_t)GLB_Set_PKA_CLK_Sel, + [ROM_API_INDEX_GLB_SW_System_Reset] = (uint32_t)GLB_SW_System_Reset, + [ROM_API_INDEX_GLB_SW_CPU_Reset] = (uint32_t)GLB_SW_CPU_Reset, + [ROM_API_INDEX_GLB_SW_POR_Reset] = (uint32_t)GLB_SW_POR_Reset, + [ROM_API_INDEX_GLB_Select_Internal_Flash] = (uint32_t)GLB_Select_Internal_Flash, + [ROM_API_INDEX_GLB_Select_External_Flash] = (uint32_t)GLB_Select_External_Flash, + [ROM_API_INDEX_GLB_Deswap_Flash_Pin] = (uint32_t)GLB_Deswap_Flash_Pin, + [ROM_API_INDEX_GLB_Swap_Flash_Pin] = (uint32_t)GLB_Swap_Flash_Pin, + [ROM_API_INDEX_GLB_GPIO_Init] = (uint32_t)GLB_GPIO_Init, + [ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable] = (uint32_t)GLB_GPIO_OUTPUT_Enable, + [ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable] = (uint32_t)GLB_GPIO_OUTPUT_Disable, + [ROM_API_INDEX_GLB_GPIO_Set_HZ] = (uint32_t)GLB_GPIO_Set_HZ, + [ROM_API_INDEX_GLB_GPIO_Get_Fun] = (uint32_t)GLB_GPIO_Get_Fun, + + [ROM_API_INDEX_HBN_Mode_Enter] = (uint32_t)HBN_Mode_Enter, + [ROM_API_INDEX_HBN_Power_Down_Flash] = (uint32_t)HBN_Power_Down_Flash, + [ROM_API_INDEX_HBN_Enable] = (uint32_t)HBN_Enable, + [ROM_API_INDEX_HBN_Reset] = (uint32_t)HBN_Reset, + [ROM_API_INDEX_HBN_Set_Ldo11_Aon_Vout] = (uint32_t)HBN_Set_Ldo11_Aon_Vout, + [ROM_API_INDEX_HBN_Set_Ldo11_Rt_Vout] = (uint32_t)HBN_Set_Ldo11_Rt_Vout, + [ROM_API_INDEX_HBN_Set_Ldo11_Soc_Vout] = (uint32_t)HBN_Set_Ldo11_Soc_Vout, + [ROM_API_INDEX_HBN_32K_Sel] = (uint32_t)HBN_32K_Sel, + [ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel] = (uint32_t)HBN_Set_ROOT_CLK_Sel, + [ROM_API_INDEX_HBN_Power_On_Xtal_32K] = (uint32_t)HBN_Power_On_Xtal_32K, + [ROM_API_INDEX_HBN_Power_Off_Xtal_32K] = (uint32_t)HBN_Power_Off_Xtal_32K, + [ROM_API_INDEX_HBN_Power_On_RC32K] = (uint32_t)HBN_Power_On_RC32K, + [ROM_API_INDEX_HBN_Power_Off_RC32K] = (uint32_t)HBN_Power_Off_RC32K, + [ROM_API_INDEX_HBN_Trim_RC32K] = (uint32_t)HBN_Trim_RC32K, + [ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg] = (uint32_t)HBN_Hw_Pu_Pd_Cfg, + [ROM_API_INDEX_HBN_Pin_WakeUp_Mask] = (uint32_t)HBN_Pin_WakeUp_Mask, + [ROM_API_INDEX_HBN_GPIO7_Dbg_Pull_Cfg] = (uint32_t)HBN_GPIO7_Dbg_Pull_Cfg, + [ROM_API_INDEX_HBN_Set_Embedded_Flash_Pullup] = (uint32_t)HBN_Set_Embedded_Flash_Pullup, + + [ROM_API_INDEX_L1C_Set_Wrap] = (uint32_t)L1C_Set_Wrap, + [ROM_API_INDEX_L1C_Set_Way_Disable] = (uint32_t)L1C_Set_Way_Disable, + [ROM_API_INDEX_L1C_IROM_2T_Access_Set] = (uint32_t)L1C_IROM_2T_Access_Set, + + [ROM_API_INDEX_PDS_Reset] = (uint32_t)PDS_Reset, + [ROM_API_INDEX_PDS_Enable] = (uint32_t)PDS_Enable, + [ROM_API_INDEX_PDS_Force_Config] = (uint32_t)PDS_Force_Config, + [ROM_API_INDEX_PDS_RAM_Config] = (uint32_t)PDS_RAM_Config, + [ROM_API_INDEX_PDS_Default_Level_Config] = (uint32_t)PDS_Default_Level_Config, + [ROM_API_INDEX_PDS_Trim_RC32M] = (uint32_t)PDS_Trim_RC32M, + [ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref] = (uint32_t)PDS_Select_RC32M_As_PLL_Ref, + [ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref] = (uint32_t)PDS_Select_XTAL_As_PLL_Ref, + [ROM_API_INDEX_PDS_Power_On_PLL] = (uint32_t)PDS_Power_On_PLL, + [ROM_API_INDEX_PDS_Enable_PLL_All_Clks] = (uint32_t)PDS_Enable_PLL_All_Clks, + [ROM_API_INDEX_PDS_Disable_PLL_All_Clks] = (uint32_t)PDS_Disable_PLL_All_Clks, + [ROM_API_INDEX_PDS_Enable_PLL_Clk] = (uint32_t)PDS_Enable_PLL_Clk, + [ROM_API_INDEX_PDS_Disable_PLL_Clk] = (uint32_t)PDS_Disable_PLL_Clk, + [ROM_API_INDEX_PDS_Power_Off_PLL] = (uint32_t)PDS_Power_Off_PLL, + + [ROM_API_INDEX_SEC_Eng_Turn_On_Sec_Ring] = (uint32_t)SEC_Eng_Turn_On_Sec_Ring, + [ROM_API_INDEX_SEC_Eng_Turn_Off_Sec_Ring] = (uint32_t)SEC_Eng_Turn_Off_Sec_Ring, + + [ROM_API_INDEX_SFlash_Init] = (uint32_t)SFlash_Init, + [ROM_API_INDEX_SFlash_SetSPIMode] = (uint32_t)SFlash_SetSPIMode, + [ROM_API_INDEX_SFlash_Read_Reg] = (uint32_t)SFlash_Read_Reg, + [ROM_API_INDEX_SFlash_Write_Reg] = (uint32_t)SFlash_Write_Reg, + [ROM_API_INDEX_SFlash_Busy] = (uint32_t)SFlash_Busy, + [ROM_API_INDEX_SFlash_Write_Enable] = (uint32_t)SFlash_Write_Enable, + [ROM_API_INDEX_SFlash_Qspi_Enable] = (uint32_t)SFlash_Qspi_Enable, + [ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable] = (uint32_t)SFlash_Volatile_Reg_Write_Enable, + [ROM_API_INDEX_SFlash_Chip_Erase] = (uint32_t)SFlash_Chip_Erase, + [ROM_API_INDEX_SFlash_Sector_Erase] = (uint32_t)SFlash_Sector_Erase, + [ROM_API_INDEX_SFlash_Blk32_Erase] = (uint32_t)SFlash_Blk32_Erase, + [ROM_API_INDEX_SFlash_Blk64_Erase] = (uint32_t)SFlash_Blk64_Erase, + [ROM_API_INDEX_SFlash_Erase] = (uint32_t)SFlash_Erase, + [ROM_API_INDEX_SFlash_Program] = (uint32_t)SFlash_Program, + [ROM_API_INDEX_SFlash_GetUniqueId] = (uint32_t)SFlash_GetUniqueId, + [ROM_API_INDEX_SFlash_GetJedecId] = (uint32_t)SFlash_GetJedecId, + [ROM_API_INDEX_SFlash_GetDeviceId] = (uint32_t)SFlash_GetDeviceId, + [ROM_API_INDEX_SFlash_Powerdown] = (uint32_t)SFlash_Powerdown, + [ROM_API_INDEX_SFlash_Releae_Powerdown] = (uint32_t)SFlash_Releae_Powerdown, + [ROM_API_INDEX_SFlash_SetBurstWrap] = (uint32_t)SFlash_SetBurstWrap, + [ROM_API_INDEX_SFlash_DisableBurstWrap] = (uint32_t)SFlash_DisableBurstWrap, + [ROM_API_INDEX_SFlash_Software_Reset] = (uint32_t)SFlash_Software_Reset, + [ROM_API_INDEX_SFlash_Reset_Continue_Read] = (uint32_t)SFlash_Reset_Continue_Read, + [ROM_API_INDEX_SFlash_Set_IDbus_Cfg] = (uint32_t)SFlash_Set_IDbus_Cfg, + [ROM_API_INDEX_SFlash_IDbus_Read_Enable] = (uint32_t)SFlash_IDbus_Read_Enable, + [ROM_API_INDEX_SFlash_Cache_Enable_Set] = (uint32_t)SFlash_Cache_Enable_Set, + [ROM_API_INDEX_SFlash_Cache_Flush] = (uint32_t)SFlash_Cache_Flush, + [ROM_API_INDEX_SFlash_Cache_Read_Enable] = (uint32_t)SFlash_Cache_Read_Enable, + [ROM_API_INDEX_SFlash_Cache_Hit_Count_Get] = (uint32_t)SFlash_Cache_Hit_Count_Get, + [ROM_API_INDEX_SFlash_Cache_Miss_Count_Get] = (uint32_t)SFlash_Cache_Miss_Count_Get, + [ROM_API_INDEX_SFlash_Cache_Read_Disable] = (uint32_t)SFlash_Cache_Read_Disable, + [ROM_API_INDEX_SFlash_Read] = (uint32_t)SFlash_Read, + [ROM_API_INDEX_SFlash_Read_Reg_With_Cmd] = (uint32_t)SFlash_Read_Reg_With_Cmd, + [ROM_API_INDEX_SFlash_Write_Reg_With_Cmd] = (uint32_t)SFlash_Write_Reg_With_Cmd, + [ROM_API_INDEX_SFlash_Restore_From_Powerdown] = (uint32_t)SFlash_Restore_From_Powerdown, + + [ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Ext_Flash_Gpio, + [ROM_API_INDEX_SF_Cfg_Init_Internal_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Internal_Flash_Gpio, + [ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio] = (uint32_t)SF_Cfg_Deinit_Ext_Flash_Gpio, + [ROM_API_INDEX_SF_Cfg_Restore_GPIO17_Fun] = (uint32_t)SF_Cfg_Restore_GPIO17_Fun, + [ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock] = (uint32_t)SF_Cfg_Get_Flash_Cfg_Need_Lock, + [ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Flash_Gpio, + [ROM_API_INDEX_SF_Cfg_Flash_Identify] = (uint32_t)SF_Cfg_Flash_Identify, + [ROM_API_INDEX_SF_Ctrl_Enable] = (uint32_t)SF_Ctrl_Enable, + [ROM_API_INDEX_SF_Ctrl_Select_Pad] = (uint32_t)SF_Ctrl_Select_Pad, + [ROM_API_INDEX_SF_Ctrl_Set_Owner] = (uint32_t)SF_Ctrl_Set_Owner, + [ROM_API_INDEX_SF_Ctrl_Disable] = (uint32_t)SF_Ctrl_Disable, + [ROM_API_INDEX_SF_Ctrl_AES_Enable_BE] = (uint32_t)SF_Ctrl_AES_Enable_BE, + [ROM_API_INDEX_SF_Ctrl_AES_Enable_LE] = (uint32_t)SF_Ctrl_AES_Enable_LE, + [ROM_API_INDEX_SF_Ctrl_AES_Set_Region] = (uint32_t)SF_Ctrl_AES_Set_Region, + [ROM_API_INDEX_SF_Ctrl_AES_Set_Key] = (uint32_t)SF_Ctrl_AES_Set_Key, + [ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE] = (uint32_t)SF_Ctrl_AES_Set_Key_BE, + [ROM_API_INDEX_SF_Ctrl_AES_Set_IV] = (uint32_t)SF_Ctrl_AES_Set_IV, + [ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE] = (uint32_t)SF_Ctrl_AES_Set_IV_BE, + [ROM_API_INDEX_SF_Ctrl_AES_Enable] = (uint32_t)SF_Ctrl_AES_Enable, + [ROM_API_INDEX_SF_Ctrl_AES_Disable] = (uint32_t)SF_Ctrl_AES_Disable, + [ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset] = (uint32_t)SF_Ctrl_Set_Flash_Image_Offset, + [ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset] = (uint32_t)SF_Ctrl_Get_Flash_Image_Offset, + [ROM_API_INDEX_SF_Ctrl_Select_Clock] = (uint32_t)SF_Ctrl_Select_Clock, + [ROM_API_INDEX_SF_Ctrl_SendCmd] = (uint32_t)SF_Ctrl_SendCmd, + [ROM_API_INDEX_SF_Ctrl_Icache_Set] = (uint32_t)SF_Ctrl_Icache_Set, + [ROM_API_INDEX_SF_Ctrl_Icache2_Set] = (uint32_t)SF_Ctrl_Icache2_Set, + [ROM_API_INDEX_SF_Ctrl_GetBusyState] = (uint32_t)SF_Ctrl_GetBusyState, + [ROM_API_INDEX_SF_Ctrl_Is_AES_Enable] = (uint32_t)SF_Ctrl_Is_AES_Enable, + [ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay] = (uint32_t)SF_Ctrl_Get_Clock_Delay, + [ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay] = (uint32_t)SF_Ctrl_Set_Clock_Delay, + + [ROM_API_INDEX_XIP_SFlash_State_Save] = (uint32_t)XIP_SFlash_State_Save, + [ROM_API_INDEX_XIP_SFlash_State_Restore] = (uint32_t)XIP_SFlash_State_Restore, + [ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock] = (uint32_t)XIP_SFlash_Erase_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_Write_Need_Lock] = (uint32_t)XIP_SFlash_Write_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_Read_Need_Lock] = (uint32_t)XIP_SFlash_Read_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock] = (uint32_t)XIP_SFlash_GetJedecId_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock] = (uint32_t)XIP_SFlash_GetDeviceId_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock] = (uint32_t)XIP_SFlash_GetUniqueId_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock] = (uint32_t)XIP_SFlash_Read_Via_Cache_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_Read_With_Lock] = (uint32_t)XIP_SFlash_Read_With_Lock, + [ROM_API_INDEX_XIP_SFlash_Write_With_Lock] = (uint32_t)XIP_SFlash_Write_With_Lock, + [ROM_API_INDEX_XIP_SFlash_Erase_With_Lock] = (uint32_t)XIP_SFlash_Erase_With_Lock, + [ROM_API_INDEX_XIP_SFlash_Opt_Enter] = (uint32_t)XIP_SFlash_Opt_Enter, + [ROM_API_INDEX_XIP_SFlash_Opt_Exit] = (uint32_t)XIP_SFlash_Opt_Exit, + + [ROM_API_INDEX_BFLB_Soft_CRC32] = (uint32_t)BFLB_Soft_CRC32, + + [ROM_API_INDEX_FUNC_EMPTY_START ... ROM_API_INDEX_FUNC_EMPTY_END] = 0xdeedbeef, +}; + + +/*@} end of group ROMDRIVER_Global_Variables */ + +/** @defgroup ROMDRIVER_Private_FunctionDeclaration + * @{ + */ + +/*@} end of group ROMDRIVER_Private_FunctionDeclaration */ + +/** @defgroup ROMDRIVER_Private_Functions + * @{ + */ + +/*@} end of group ROMDRIVER_Private_Functions */ + +/** @defgroup ROMDRIVER_Public_Functions + * @{ + */ + +/*@} end of group ROMDRIVER_Public_Functions */ + +/*@} end of group ROMDRIVER_COMMON */ + +/*@} end of group BL602_Periph_Driver */ + + diff --git a/drivers/bl602_driver/std_drv/src/bl602_sdu.c b/drivers/bl602_driver/std_drv/src/bl602_sdu.c new file mode 100644 index 00000000..cced4c80 --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_sdu.c @@ -0,0 +1,76 @@ +#include "bl602_sdu.h" + +volatile pHidSdio_RegMap_t SdioFuncReg[] = +{ + (pHidSdio_RegMap_t)(BL_SDIO_CCR_BASE), +#if NUM_FUNC == 2 + (pHidSdio_RegMap_t)(BL_SDIO_CCR_BASE+BL_SDIO_CCR_FUNC_OFFSET) +#elif NUM_FUNC == 3 + (pHidSdio_RegMap_t)(BL_SDIO_CCR_BASE+BL_SDIO_CCR_FUNC_OFFSET), + (pHidSdio_RegMap_t)(BL_SDIO_CCR_BASE+(2 * BL_SDIO_CCR_FUNC_OFFSET)) +#endif +}; + +/* if flag_mport = 0, then it supports mport + * flag_mport = 1, then mport disabled + */ +uint8_t flag_mport[NUM_FUNC] = +{ + 0, +#if NUM_FUNC == 2 + 1 +#elif NUM_FUNC == 3 + 1,1 +#endif +}; + +void sdio_GEN_CARD2HOST_INT(uint32_t port_id, uint16_t value) +{ + /* We do not want to generate Download rdy for command port + * only. Currently there is a condition where if we generate + * download ready for command, followed by a download + * ready for data, the download ready for data would be gated + * by the SDIO controller. To avoid this we do not generate + * a download ready for command. Download ready is only generated for data. + */ + /* + if (!flag_mport[port_id] && + (value & SDIO_CCR_CS_DnLdRdy) && (prev_WrBitMap[port_id] == 0x01)) + { + value &= ~SDIO_CCR_CS_DnLdRdy; + if (!value) + { + return; + } + } + */ + SdioFuncReg[port_id]->CardToHostEvent = value; +} + + +uint32_t sdio_ioctl(uint32_t port_id, SDIO_CMD_TYPE cmd, void *arg) +{ + switch(cmd) + { + case IOCTL_HID_GET_BLOCK_SIZE: + { + if (port_id == FUNC_WIFI) + { + uint32_t blockSize = BL_REGS8(SDIO_FN1_BLK_SIZE_0); + + blockSize |= ((BL_REGS8(SDIO_FN1_BLK_SIZE_1) & + SDIO_FN1_BLK_SIZE_1_MASK ) << 8); + + if(blockSize == 0) + { + blockSize = 512; + } + return(blockSize); + } + break; + } + default: + break; + } + return 0; +} diff --git a/drivers/bl602_driver/std_drv/src/bl602_sec_dbg.c b/drivers/bl602_driver/std_drv/src/bl602_sec_dbg.c new file mode 100644 index 00000000..bc8dfaf9 --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_sec_dbg.c @@ -0,0 +1,151 @@ +/** + ****************************************************************************** + * @file bl602_sec_dbg.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "string.h" +#include "bl602_sec_dbg.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SEC_DBG + * @{ + */ + +/** @defgroup SEC_DBG_Private_Macros + * @{ + */ + +/*@} end of group SEC_DBG_Private_Macros */ + +/** @defgroup SEC_DBG_Private_Types + * @{ + */ + +/*@} end of group SEC_DBG_Private_Types */ + +/** @defgroup SEC_DBG_Private_Variables + * @{ + */ + +/*@} end of group SEC_DBG_Private_Variables */ + +/** @defgroup SEC_DBG_Global_Variables + * @{ + */ + +/*@} end of group SEC_DBG_Global_Variables */ + +/** @defgroup SEC_DBG_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SEC_DBG_Private_Fun_Declaration */ + +/** @defgroup SEC_DBG_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief Sec Dbg read chip ID + * + * @param id[8]: chip ID buffer + * + * @return None + * +*******************************************************************************/ +void Sec_Dbg_Read_Chip_ID(uint8_t id[8]) +{ + uint32_t idLow,idHigh; + + idLow=BL_RD_REG(SEC_DBG_BASE,SEC_DBG_SD_CHIP_ID_LOW); + BL_WRWD_TO_BYTEP(id,idLow); + + idHigh=BL_RD_REG(SEC_DBG_BASE,SEC_DBG_SD_CHIP_ID_HIGH); + BL_WRWD_TO_BYTEP((id+4),idHigh); +} + +/****************************************************************************//** + * @brief Sec Dbg read MAC address + * + * @param macAddr[6]: MAC address buffer + * + * @return None + * +*******************************************************************************/ +void Sec_Dbg_Read_WiFi_MAC(uint8_t macAddr[6]) +{ + uint32_t macLow,macHigh; + + macLow=BL_RD_REG(SEC_DBG_BASE,SEC_DBG_SD_WIFI_MAC_LOW); + BL_WRWD_TO_BYTEP(macAddr,macLow); + + macHigh=BL_RD_REG(SEC_DBG_BASE,SEC_DBG_SD_WIFI_MAC_HIGH); + macAddr[4]=(macHigh>>0)&0xff; + macAddr[5]=(macHigh>>8)&0xff; +} + +/****************************************************************************//** + * @brief Sec Dbg read debug mode + * + * @param None + * + * @return debug mode status + * +*******************************************************************************/ +uint32_t Sec_Dbg_Read_Dbg_Mode(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(SEC_DBG_BASE,SEC_DBG_SD_STATUS),SEC_DBG_SD_DBG_MODE); +} + +/****************************************************************************//** + * @brief Sec Dbg read debug enable status + * + * @param None + * + * @return enable status + * +*******************************************************************************/ +uint32_t Sec_Dbg_Read_Dbg_Enable(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(SEC_DBG_BASE,SEC_DBG_SD_STATUS),SEC_DBG_SD_DBG_ENA); +} + +/*@} end of group SEC_DBG_Public_Functions */ + +/*@} end of group SEC_DBG */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/bl602_driver/std_drv/src/bl602_sec_eng.c b/drivers/bl602_driver/std_drv/src/bl602_sec_eng.c new file mode 100644 index 00000000..ebe4a58b --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_sec_eng.c @@ -0,0 +1,3200 @@ +/** + ****************************************************************************** + * @file bl602_sec_eng.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "string.h" +#include "bl602_sec_eng.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SEC_ENG + * @{ + */ + +/** @defgroup SEC_ENG_Private_Macros + * @{ + */ +#define PUT_UINT32_BE(n,b,i) \ +{ \ + (b)[(i) ] = (uint8_t) ( (n) >> 24 ); \ + (b)[(i) + 1] = (uint8_t) ( (n) >> 16 ); \ + (b)[(i) + 2] = (uint8_t) ( (n) >> 8 ); \ + (b)[(i) + 3] = (uint8_t) ( (n) ); \ +} +#define PUT_UINT64_BE(n,b,i) \ +{ \ + (b)[(i) ] = (uint8_t) ( (n) >> 56 ); \ + (b)[(i) + 1] = (uint8_t) ( (n) >> 48 ); \ + (b)[(i) + 2] = (uint8_t) ( (n) >> 40 ); \ + (b)[(i) + 3] = (uint8_t) ( (n) >> 32 ); \ + (b)[(i) + 4] = (uint8_t) ( (n) >> 24 ); \ + (b)[(i) + 5] = (uint8_t) ( (n) >> 16 ); \ + (b)[(i) + 6] = (uint8_t) ( (n) >> 8 ); \ + (b)[(i) + 7] = (uint8_t) ( (n) ); \ +} +#define SEC_ENG_SHA_BUSY_TIMEOUT_COUNT (100*160*1000) +#define SEC_ENG_AES_BUSY_TIMEOUT_COUNT (100*160*1000) +#define SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT (100*160*1000) +#define SEC_ENG_PKA_INT_TIMEOUT_COUNT (100*160*1000) +#define SEC_ENG_GMAC_BUSY_TIMEOUT_COUNT (100*160*1000) + +/*@} end of group SEC_ENG_Private_Macros */ + +/** @defgroup SEC_ENG_Private_Types + * @{ + */ +struct pka0_pld_cfg { + union { + struct { + uint32_t size : 12; /*[11: 0], r/w, 0x0 */ + uint32_t d_reg_index : 8; /*[19:12], r/w, 0x0 */ + uint32_t d_reg_type : 4; /*[23:20], r/w, 0x0 */ + uint32_t op : 7; /*[30:24], r/w, 0x0 */ + uint32_t last_op : 1; /*[31:31], r/w, 0x0 */ + }BF; + uint32_t WORD; + } value; +}; + +struct pka0_pldi_cfg { + union { + struct { + uint32_t rsvd : 12; /*[11: 0], r/w, 0x0 */ + uint32_t d_reg_index : 8; /*[19:12], r/w, 0x0 */ + uint32_t d_reg_type : 4; /*[23:20], r/w, 0x0 */ + uint32_t op : 7; /*[30:24], r/w, 0x0 */ + uint32_t last_op : 1; /*[31:31], r/w, 0x0 */ + }BF; + uint32_t WORD; + } value; +}; + +struct pka0_common_op_first_cfg{ + union { + struct { + uint32_t s0_reg_idx : 8; /*[7: 0], r/w, 0x0 */ + uint32_t s0_reg_type : 4; /*[11:8], r/w, 0x0 */ + uint32_t d_reg_idx : 8; /*[19:12], r/w, 0x0 */ + uint32_t d_reg_type : 4; /*[23:20], r/w, 0x0 */ + uint32_t op : 7; /*[30:24], r/w, 0x0 */ + uint32_t last_op : 1; /*[31:31], r/w, 0x0 */ + }BF; + uint32_t WORD; + } value; +}; + +struct pka0_common_op_snd_cfg_S1_only{ + union { + struct { + uint32_t reserved_0_11 : 12; /*[11: 0], rsvd, 0x0 */ + uint32_t s1_reg_idx : 8; /*[19:12], r/w, 0x0 */ + uint32_t s1_reg_type : 4; /*[23:20], r/w, 0x0 */ + uint32_t reserved_24_31 : 8; /*[31:24], rsvd, 0x0 */ + }BF; + uint32_t WORD; + } value; +}; + +struct pka0_common_op_snd_cfg_S2_only{ + union { + struct { + uint32_t s2_reg_idx : 8; /*[7 : 0], r/w, 0x0 */ + uint32_t s2_reg_type : 4; /*[11: 8], r/w, 0x0 */ + uint32_t reserved_12_31 : 20; /*[31:12], rsvd, 0x0 */ + }BF; + uint32_t WORD; + } value; +}; + +struct pka0_common_op_snd_cfg_S1_S2{ + union { + struct { + uint32_t s2_reg_idx : 8; /*[7 : 0], r/w, 0x0 */ + uint32_t s2_reg_type : 4; /*[11: 8], r/w, 0x0 */ + uint32_t s1_reg_idx : 8; /*[19:12], r/w, 0x0 */ + uint32_t s1_reg_type : 4; /*[23:20], r/w, 0x0 */ + uint32_t reserved_24_31 : 8; /*[31:24], rsvd, 0x0 */ + }BF; + uint32_t WORD; + } value; +}; + +struct pka0_bit_shift_op_cfg{ + union { + struct { + uint32_t bit_shift : 15; /*[14: 0], r/w, 0x0 */ + uint32_t reserved_24_31 : 17; /*[31:15], rsvd, 0x0 */ + }BF; + uint32_t WORD; + } value; +}; + +/*@} end of group SEC_ENG_Private_Types */ + +/** @defgroup SEC_ENG_Private_Variables + * @{ + */ +static intCallback_Type* secEngIntCbfArra[SEC_ENG_INT_ALL]= {NULL}; + + +/*@} end of group SEC_ENG_Private_Variables */ + +/** @defgroup SEC_ENG_Global_Variables + * @{ + */ + +/*@} end of group SEC_ENG_Global_Variables */ + +/** @defgroup SEC_ENG_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SEC_ENG_Private_Fun_Declaration */ + +/** @defgroup SEC_ENG_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief SHA256 initialization function + * + * @param shaCtx: SHA256 context pointer + * @param shaNo: SHA ID type + * @param shaType: SHA type + * @param shaTmpBuf[16]: SHA temp buffer for store data that is less than 64 bytes + * @param padding[16]: SHA padding buffer for store padding data + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_SHA256_Init(SEC_Eng_SHA256_Ctx *shaCtx,SEC_ENG_SHA_ID_Type shaNo,SEC_ENG_SHA_Type shaType,uint32_t shaTmpBuf[16],uint32_t padding[16]) +{ + uint32_t SHAx = SEC_ENG_BASE+SEC_ENG_SHA_OFFSET; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); + CHECK_PARAM(IS_SEC_ENG_SHA_TYPE(shaType)); + + /* Deal SHA control register to set SHA mode */ + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_CTRL); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_SHA_MODE,shaType); + BL_WR_REG(SHAx,SEC_ENG_SE_SHA_CTRL,tmpVal); + + /* Clear context */ + memset(shaCtx,0,sizeof(SEC_Eng_SHA256_Ctx)); + + /* Init temp buffer and padding buffer */ + shaCtx->shaBuf=shaTmpBuf; + shaCtx->shaPadding=padding; + BL602_MemSet(shaCtx->shaPadding,0,64); + BL602_MemSet(shaCtx->shaPadding,0x80,1); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_SHA_IRQn,SEC_SHA_IRQHandler); +#endif +} + +/****************************************************************************//** + * @brief SHA start function + * + * @param shaNo: SHA ID type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_SHA_Start(SEC_ENG_SHA_ID_Type shaNo) +{ + uint32_t SHAx = SEC_ENG_BASE+SEC_ENG_SHA_OFFSET; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); + + /* Set SHA enable */ + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_CTRL); + + tmpVal=BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_SHA_EN); + /* Hash sel 0 for new start */ + tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_SHA_HASH_SEL); + + BL_WR_REG(SHAx,SEC_ENG_SE_SHA_CTRL,tmpVal); +} + +/****************************************************************************//** + * @brief SHA256 update input data function + * + * @param shaCtx: SHA256 context pointer + * @param shaNo: SHA ID type + * @param input: SHA input data pointer, and the address should be word align + * @param len: SHA input data length + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_SHA256_Update(SEC_Eng_SHA256_Ctx *shaCtx,SEC_ENG_SHA_ID_Type shaNo,const uint8_t *input, uint32_t len) +{ + uint32_t SHAx = SEC_ENG_BASE+SEC_ENG_SHA_OFFSET; + uint32_t tmpVal; + uint32_t fill; + uint32_t left; + uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + if( len == 0 ){ + return SUCCESS; + } + + do { + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_CTRL); + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + }while(BL_IS_REG_BIT_SET(tmpVal,SEC_ENG_SE_SHA_BUSY)); + + /* SHA need set se_sha_sel to 1 to keep the last SHA state */ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_SHA_HASH_SEL,shaCtx->shaFeed); + + left = shaCtx->total[0] & 0x3F; + fill = 64 - left; + + shaCtx->total[0] += (uint32_t) len; + shaCtx->total[0] &= 0xFFFFFFFF; + + if( shaCtx->total[0] < (uint32_t) len ){ + shaCtx->total[1]++; + } + + if( left && len >= fill ){ + BL602_MemCpy_Fast( (void *) ((uint8_t *)shaCtx->shaBuf + left), input, fill ); + /* Set data source address */ + BL_WR_REG(SHAx,SEC_ENG_SE_SHA_MSA,(uint32_t )shaCtx->shaBuf); + + /* Set data length */ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_SHA_MSG_LEN,1); + BL_WR_REG(SHAx,SEC_ENG_SE_SHA_CTRL,tmpVal); + /* Trigger */ + tmpVal=BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_SHA_TRIG_1T); + BL_WR_REG(SHAx,SEC_ENG_SE_SHA_CTRL,tmpVal); + + shaCtx->shaFeed=1; + input += fill; + len -= fill; + left = 0; + } + + fill=len/64; + len=len%64; + if( fill>0 ){ + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + do { + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_CTRL); + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + }while(BL_IS_REG_BIT_SET(tmpVal,SEC_ENG_SE_SHA_BUSY)); + + /* SHA need set se_sha_sel to 1 to keep the last sha state */ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_SHA_HASH_SEL,shaCtx->shaFeed); + + /* Fill data */ + BL_WR_REG(SHAx,SEC_ENG_SE_SHA_MSA,(uint32_t)input); + + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_SHA_MSG_LEN,fill); + BL_WR_REG(SHAx,SEC_ENG_SE_SHA_CTRL,tmpVal); + + tmpVal=BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_SHA_TRIG_1T); + BL_WR_REG(SHAx,SEC_ENG_SE_SHA_CTRL,tmpVal); + + input+=(fill*64); + shaCtx->shaFeed=1; + } + + if( len > 0 ){ + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + do { + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_CTRL); + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + }while(BL_IS_REG_BIT_SET(tmpVal,SEC_ENG_SE_SHA_BUSY)); + + /* Copy left data into temp buffer */ + BL602_MemCpy_Fast( (void *) ((uint8_t *)shaCtx->shaBuf + left), input, len ); + } + + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + do { + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_CTRL); + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + }while(BL_IS_REG_BIT_SET(tmpVal,SEC_ENG_SE_SHA_BUSY)); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief SHA256 finish to get output function + * + * @param shaCtx: SHA256 context pointer + * @param shaNo: SHA ID type + * @param hash: SHA output data of SHA result + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_SHA256_Finish(SEC_Eng_SHA256_Ctx *shaCtx,SEC_ENG_SHA_ID_Type shaNo,uint8_t *hash) +{ + uint32_t last, padn; + uint32_t high, low; + uint8_t shaMode; + uint8_t msgLen[8]; + uint8_t *p=(uint8_t *)hash; + uint32_t SHAx = SEC_ENG_BASE+SEC_ENG_SHA_OFFSET; + uint32_t tmpVal; + uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); + + /* Wait finished */ + do { + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_CTRL); + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + }while(BL_IS_REG_BIT_SET(tmpVal,SEC_ENG_SE_SHA_BUSY)); + + high = ( shaCtx->total[0] >> 29 ) + | ( shaCtx->total[1] << 3 ); + low = ( shaCtx->total[0] << 3 ); + + PUT_UINT32_BE( high, msgLen, 0 ); + PUT_UINT32_BE( low, msgLen, 4 ); + + last = shaCtx->total[0] & 0x3F; + padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last ); + + Sec_Eng_SHA256_Update(shaCtx,shaNo, (uint8_t *)shaCtx->shaPadding, padn ); + + /* Wait for shaPadding idle */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + do { + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_CTRL); + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + }while(BL_IS_REG_BIT_SET(tmpVal,SEC_ENG_SE_SHA_BUSY)); + + BL602_MemCpy_Fast(shaCtx->shaPadding,msgLen,8); + Sec_Eng_SHA256_Update(shaCtx,shaNo, (uint8_t *)shaCtx->shaPadding, 8 ); + + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + do { + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_CTRL); + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + }while(BL_IS_REG_BIT_SET(tmpVal,SEC_ENG_SE_SHA_BUSY)); + + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_CTRL); + shaMode=(SEC_ENG_SHA_Type)BL_GET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_SHA_MODE); + /* Copy SHA value */ + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_HASH_L_0); + *p++=(tmpVal&0xff);*p++=((tmpVal>>8)&0xff);*p++=((tmpVal>>16)&0xff);*p++=((tmpVal>>24)&0xff); + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_HASH_L_1); + *p++=(tmpVal&0xff);*p++=((tmpVal>>8)&0xff);*p++=((tmpVal>>16)&0xff);*p++=((tmpVal>>24)&0xff); + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_HASH_L_2); + *p++=(tmpVal&0xff);*p++=((tmpVal>>8)&0xff);*p++=((tmpVal>>16)&0xff);*p++=((tmpVal>>24)&0xff); + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_HASH_L_3); + *p++=(tmpVal&0xff);*p++=((tmpVal>>8)&0xff);*p++=((tmpVal>>16)&0xff);*p++=((tmpVal>>24)&0xff); + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_HASH_L_4); + *p++=(tmpVal&0xff);*p++=((tmpVal>>8)&0xff);*p++=((tmpVal>>16)&0xff);*p++=((tmpVal>>24)&0xff); + if (shaMode==SEC_ENG_SHA224 || shaMode==SEC_ENG_SHA256){ + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_HASH_L_5); + *p++=(tmpVal&0xff);*p++=((tmpVal>>8)&0xff);*p++=((tmpVal>>16)&0xff);*p++=((tmpVal>>24)&0xff); + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_HASH_L_6); + *p++=(tmpVal&0xff);*p++=((tmpVal>>8)&0xff);*p++=((tmpVal>>16)&0xff);*p++=((tmpVal>>24)&0xff); + if (shaMode==SEC_ENG_SHA256){ + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_HASH_L_7); + *p++=(tmpVal&0xff);*p++=((tmpVal>>8)&0xff);*p++=((tmpVal>>16)&0xff);*p++=((tmpVal>>24)&0xff); + } + } + + /* Disable SHA engine*/ + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_CTRL); + tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_SHA_HASH_SEL); + tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_SHA_EN); + BL_WR_REG(SHAx,SEC_ENG_SE_SHA_CTRL,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief SHA enable link mode and set link config address + * + * @param shaNo: SHA ID type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_SHA_Enable_Link(SEC_ENG_SHA_ID_Type shaNo) +{ + uint32_t SHAx = SEC_ENG_BASE; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); + + /* Enable sha and enable link mode */ + tmpVal = BL_RD_REG(SHAx,SEC_ENG_SE_SHA_0_CTRL); + tmpVal = BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_SHA_0_EN); + tmpVal = BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_SHA_0_LINK_MODE); + BL_WR_REG(SHAx,SEC_ENG_SE_SHA_0_CTRL,tmpVal); +} + +/****************************************************************************//** + * @brief SHA disable link mode + * + * @param shaNo: SHA ID type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_SHA_Disable_Link(SEC_ENG_SHA_ID_Type shaNo) +{ + uint32_t SHAx = SEC_ENG_BASE; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); + + /* Disable sha and disable link mode */ + tmpVal = BL_RD_REG(SHAx,SEC_ENG_SE_SHA_0_CTRL); + tmpVal = BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_SHA_0_LINK_MODE); + tmpVal = BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_SHA_0_EN); + BL_WR_REG(SHAx,SEC_ENG_SE_SHA_0_CTRL,tmpVal); +} + +/****************************************************************************//** + * @brief SHA256 link mode initialization function + * + * @param shaCtx: SHA256 link mode context pointer + * @param shaNo: SHA ID type + * @param linkAddr: SHA link configure address + * @param shaTmpBuf[16]: SHA temp buffer for store data that is less than 64 bytes + * @param padding[16]: SHA padding buffer for store padding data + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_SHA256_Link_Init(SEC_Eng_SHA256_Link_Ctx *shaCtx,SEC_ENG_SHA_ID_Type shaNo,uint32_t linkAddr,uint32_t shaTmpBuf[16],uint32_t padding[16]) +{ + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); + + /* Clear context */ + memset(shaCtx,0,sizeof(SEC_Eng_SHA256_Link_Ctx)); + + /* Init temp buffer,padding buffer and link address */ + shaCtx->shaBuf=shaTmpBuf; + shaCtx->shaPadding=padding; + BL602_MemSet(shaCtx->shaPadding,0,64); + BL602_MemSet(shaCtx->shaPadding,0x80,1); + shaCtx->linkAddr=linkAddr; + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_SHA_IRQn,SEC_SHA_IRQHandler); +#endif +} + +/****************************************************************************//** + * @brief SHA256 link mode update input data function + * + * @param shaCtx: SHA256 link mode context pointer + * @param shaNo: SHA ID type + * @param input: SHA input data pointer, and the address should be word align + * @param len: SHA input data length + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_SHA256_Link_Update(SEC_Eng_SHA256_Link_Ctx *shaCtx,SEC_ENG_SHA_ID_Type shaNo,const uint8_t *input, uint32_t len) +{ + uint32_t SHAx = SEC_ENG_BASE; + uint32_t tmpVal; + uint32_t fill; + uint32_t left; + uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + if( len == 0 ){ + return SUCCESS; + } + + do { + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_0_CTRL); + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + }while(BL_IS_REG_BIT_SET(tmpVal,SEC_ENG_SE_SHA_0_BUSY)); + + /* Set link address */ + BL_WR_REG(SHAx,SEC_ENG_SE_SHA_0_LINK,shaCtx->linkAddr); + + left = shaCtx->total[0] & 0x3F; + fill = 64 - left; + + shaCtx->total[0] += (uint32_t) len; + shaCtx->total[0] &= 0xFFFFFFFF; + + if( shaCtx->total[0] < (uint32_t) len ){ + shaCtx->total[1]++; + } + + if( left && len >= fill ){ + BL602_MemCpy_Fast( (void *) ((uint8_t *)shaCtx->shaBuf + left), input, fill ); + /* Set data source address */ + *(uint32_t *)(shaCtx->linkAddr+4) = (uint32_t)shaCtx->shaBuf; + + /* Set data length */ + *((uint16_t *)shaCtx->linkAddr+1) = 1; + /* Trigger */ + tmpVal = BL_RD_REG(SHAx,SEC_ENG_SE_SHA_0_CTRL); + BL_WR_REG(SHAx,SEC_ENG_SE_SHA_0_CTRL,BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_SHA_0_TRIG_1T)); + + /* Choose accumulating last hash in the next time */ + *((uint32_t *)shaCtx->linkAddr) |= 0x40; + input += fill; + len -= fill; + left = 0; + } + + fill=len/64; + len=len%64; + if( fill>0 ){ + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + do { + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_0_CTRL); + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + }while(BL_IS_REG_BIT_SET(tmpVal,SEC_ENG_SE_SHA_0_BUSY)); + + /* Fill data */ + *(uint32_t *)(shaCtx->linkAddr+4) = (uint32_t)input; + *((uint16_t *)shaCtx->linkAddr+1) = fill; + + /* Trigger */ + tmpVal = BL_RD_REG(SHAx,SEC_ENG_SE_SHA_0_CTRL); + BL_WR_REG(SHAx,SEC_ENG_SE_SHA_0_CTRL,BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_SHA_0_TRIG_1T)); + + input+=(fill*64); + /* Choose accumulating last hash in the next time */ + *((uint32_t *)shaCtx->linkAddr) |= 0x40; + } + + if( len > 0 ){ + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + do { + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_0_CTRL); + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + }while(BL_IS_REG_BIT_SET(tmpVal,SEC_ENG_SE_SHA_0_BUSY)); + + /* Copy left data into temp buffer */ + BL602_MemCpy_Fast( (void *) ((uint8_t *)shaCtx->shaBuf + left), input, len ); + } + + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + do { + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_0_CTRL); + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + }while(BL_IS_REG_BIT_SET(tmpVal,SEC_ENG_SE_SHA_0_BUSY)); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief SHA256 link mode finish to get output function + * + * @param shaCtx: SHA256 link mode context pointer + * @param shaNo: SHA ID type + * @param hash: SHA output data of SHA result + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_SHA256_Link_Finish(SEC_Eng_SHA256_Link_Ctx *shaCtx,SEC_ENG_SHA_ID_Type shaNo,uint8_t *hash) +{ + uint32_t last, padn; + uint32_t high, low; + uint8_t msgLen[8]; + uint32_t SHAx = SEC_ENG_BASE; + uint32_t tmpVal; + uint32_t shaMode = (*(uint32_t *)shaCtx->linkAddr)>>2&0x7; + uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); + + /* Wait finished */ + do { + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_0_CTRL); + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + }while(BL_IS_REG_BIT_SET(tmpVal,SEC_ENG_SE_SHA_0_BUSY)); + + /* Set link address */ + BL_WR_REG(SHAx,SEC_ENG_SE_SHA_0_LINK,shaCtx->linkAddr); + + high = ( shaCtx->total[0] >> 29 ) + | ( shaCtx->total[1] << 3 ); + low = ( shaCtx->total[0] << 3 ); + + PUT_UINT32_BE( high, msgLen, 0 ); + PUT_UINT32_BE( low, msgLen, 4 ); + + last = shaCtx->total[0] & 0x3F; + padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last ); + + Sec_Eng_SHA256_Link_Update(shaCtx,shaNo, (uint8_t *)shaCtx->shaPadding, padn ); + + /* Wait for shaPadding idle */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + do { + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_0_CTRL); + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + }while(BL_IS_REG_BIT_SET(tmpVal,SEC_ENG_SE_SHA_0_BUSY)); + + Sec_Eng_SHA256_Link_Update(shaCtx,shaNo, msgLen, 8 ); + + /* Wait finished */ + timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; + do { + tmpVal=BL_RD_REG(SHAx,SEC_ENG_SE_SHA_0_CTRL); + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + }while(BL_IS_REG_BIT_SET(tmpVal,SEC_ENG_SE_SHA_0_BUSY)); + + /* Get result according to SHA mode,result is placed in (link address + offset:8) */ + switch(shaMode){ + case 0: + BL602_MemCpy_Fast(hash,(uint8_t *)(shaCtx->linkAddr+8),32); + break; + case 1: + BL602_MemCpy_Fast(hash,(uint8_t *)(shaCtx->linkAddr+8),28); + break; + case 2: + BL602_MemCpy_Fast(hash,(uint8_t *)(shaCtx->linkAddr+8),20); + break; + case 3: + BL602_MemCpy_Fast(hash,(uint8_t *)(shaCtx->linkAddr+8),20); + break; + default: + break; + } + + /* Choose new hash in the next time */ + *((uint32_t *)shaCtx->linkAddr) &= ~0x40; + + return SUCCESS; +} + +/****************************************************************************//** + * @brief AES initialization function + * + * @param aesCtx: AES context pointer + * @param aesNo: AES ID type + * @param aesType: AES type:ECB,CTR,CBC + * @param keyType: AES key type:128,256,192 + * @param enDecType: AES encryption or decryption + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_AES_Init(SEC_Eng_AES_Ctx *aesCtx,SEC_ENG_AES_ID_Type aesNo,SEC_ENG_AES_Type aesType,SEC_ENG_AES_Key_Type keyType,SEC_ENG_AES_EnDec_Type enDecType) +{ + uint32_t AESx = SEC_ENG_BASE+SEC_ENG_AES_OFFSET; + uint32_t tmpVal; + uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + CHECK_PARAM(IS_SEC_ENG_AES_TYPE(aesType)); + CHECK_PARAM(IS_SEC_ENG_AES_KEY_TYPE(keyType)); + CHECK_PARAM(IS_SEC_ENG_AES_ENDEC_TYPE(enDecType)); + + /* Wait finished */ + do { + tmpVal=BL_RD_REG(AESx,SEC_ENG_SE_AES_CTRL); + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + }while(BL_IS_REG_BIT_SET(tmpVal,SEC_ENG_SE_AES_BUSY)); + + /* Set AES mode type*/ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_AES_BLOCK_MODE,aesType); + + /* Set AES key type */ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_AES_MODE,keyType); + + /* Set AES encryption or decryption */ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_AES_DEC_EN,enDecType); + + /* Clear dec_key_sel to select new key */ + tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_AES_DEC_KEY_SEL); + + /* Clear aes iv sel to select new iv */ + tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_AES_IV_SEL); + + /* Clear AES interrupt */ + tmpVal=BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_AES_INT_CLR_1T); + + /* Enable AES */ + tmpVal=BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_AES_EN); + + BL_WR_REG(AESx,SEC_ENG_SE_AES_CTRL,tmpVal); + + /* Clear AES context */ + memset(aesCtx,0,sizeof(SEC_Eng_AES_Ctx)); + + /* Enable ID0 Access for HW Key */ + BL_WR_REG(SEC_ENG_BASE,SEC_ENG_SE_AES_0_CTRL_PROT,0x03); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_AES_IRQn,SEC_AES_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************//** + * @brief AES enable function,set AES bigendian + * + * @param aesNo: AES ID type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID_Type aesNo) +{ + uint32_t AESx = SEC_ENG_BASE+SEC_ENG_AES_OFFSET; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + + BL_WR_REG(AESx,SEC_ENG_SE_AES_ENDIAN,0x0f); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_AES_IRQn,SEC_AES_IRQHandler); +#endif +} + +/****************************************************************************//** + * @brief AES enable function,set AES littleendian + * + * @param aesNo: AES ID type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Enable_LE(SEC_ENG_AES_ID_Type aesNo) +{ + uint32_t AESx = SEC_ENG_BASE+SEC_ENG_AES_OFFSET; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + + BL_WR_REG(AESx,SEC_ENG_SE_AES_ENDIAN,0x00); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_AES_IRQn,SEC_AES_IRQHandler); +#endif +} + +/****************************************************************************//** + * @brief AES enable link mode + * + * @param aesNo: AES ID type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Enable_Link(SEC_ENG_AES_ID_Type aesNo) +{ + uint32_t AESx = SEC_ENG_BASE; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + + /* Enable aes link mode */ + tmpVal = BL_RD_REG(AESx,SEC_ENG_SE_AES_0_CTRL); + BL_WR_REG(AESx,SEC_ENG_SE_AES_0_CTRL,BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_AES_0_LINK_MODE)); + + /* Enable ID0 Access for HW Key */ + BL_WR_REG(SEC_ENG_BASE,SEC_ENG_SE_AES_0_CTRL_PROT,0x03); +} + +/****************************************************************************//** + * @brief AES disable link mode + * + * @param aesNo: AES ID type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Disable_Link(SEC_ENG_AES_ID_Type aesNo) +{ + uint32_t AESx = SEC_ENG_BASE; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + + /* Disable aes link mode */ + tmpVal = BL_RD_REG(AESx,SEC_ENG_SE_AES_0_CTRL); + BL_WR_REG(AESx,SEC_ENG_SE_AES_0_CTRL,BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_AES_0_LINK_MODE)); +} + +/****************************************************************************//** + * @brief AES work in link mode + * + * @param aesNo: AES ID type + * @param linkAddr: Address of config structure in link mode + * @param in: AES input data buffer to deal with + * @param len: AES input data length + * @param out: AES output data buffer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_AES_Link_Work(SEC_ENG_AES_ID_Type aesNo,uint32_t linkAddr,const uint8_t *in,uint32_t len,uint8_t *out) +{ + uint32_t AESx = SEC_ENG_BASE; + uint32_t tmpVal; + uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + + /* Link address should word align */ + if((linkAddr&0x03) != 0 || len%16 != 0){ + return ERROR; + } + + /* Wait finished */ + do { + tmpVal=BL_RD_REG(AESx,SEC_ENG_SE_AES_0_CTRL); + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + }while(BL_IS_REG_BIT_SET(tmpVal,SEC_ENG_SE_AES_0_BUSY)); + + /* Set link address */ + BL_WR_REG(AESx,SEC_ENG_SE_AES_0_LINK,linkAddr); + + /* Change source buffer address and destination buffer address */ + *(uint32_t *)(linkAddr+4) = (uint32_t)in; + *(uint32_t *)(linkAddr+8) = (uint32_t)out; + + /* Set data length */ + *((uint16_t *)linkAddr+1) = len/16; + + /* Enable aes */ + tmpVal = BL_RD_REG(AESx,SEC_ENG_SE_AES_0_CTRL); + BL_WR_REG(AESx,SEC_ENG_SE_AES_0_CTRL,BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_AES_0_EN)); + + /* Start aes engine and wait finishing */ + tmpVal = BL_RD_REG(AESx,SEC_ENG_SE_AES_0_CTRL); + BL_WR_REG(AESx,SEC_ENG_SE_AES_0_CTRL,BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_AES_0_TRIG_1T)); + __NOP(); + __NOP(); + timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; + do { + tmpVal=BL_RD_REG(AESx,SEC_ENG_SE_AES_0_CTRL); + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + }while(BL_IS_REG_BIT_SET(tmpVal,SEC_ENG_SE_AES_0_BUSY)); + + /* Disable aes */ + BL_WR_REG(AESx,SEC_ENG_SE_AES_0_CTRL,BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_AES_0_EN)); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief AES set hardware key source:efuse region for CPU0 or region efuse for CPU1 + * + * @param aesNo: AES ID type + * @param src: AES key source type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Set_Hw_Key_Src(SEC_ENG_AES_ID_Type aesNo,uint8_t src) +{ + uint32_t AESx = SEC_ENG_BASE+SEC_ENG_AES_OFFSET; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + + tmpVal=BL_RD_REG(AESx,SEC_ENG_SE_AES_SBOOT); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_AES_SBOOT_KEY_SEL,src); + + BL_WR_REG(AESx,SEC_ENG_SE_AES_SBOOT,tmpVal); +} + +/****************************************************************************//** + * @brief AES set KEY and IV + * + * @param aesNo: AES ID type + * @param keySrc: AES KEY type:SEC_ENG_AES_KEY_HW or SEC_ENG_AES_KEY_SW + * @param key: AES KEY pointer + * @param iv: AES IV pointer + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Set_Key_IV(SEC_ENG_AES_ID_Type aesNo,SEC_ENG_AES_Key_Src_Type keySrc,const uint8_t *key,const uint8_t *iv) +{ + uint32_t AESx = SEC_ENG_BASE+SEC_ENG_AES_OFFSET; + uint32_t tmpVal; + uint32_t keyType; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + CHECK_PARAM(IS_SEC_ENG_AES_KEY_SRC_TYPE(keySrc)); + + /* Set IV */ + BL_WR_REG(AESx,SEC_ENG_SE_AES_IV_3,__REV(BL_RDWD_FRM_BYTEP(iv))); + iv+=4; + BL_WR_REG(AESx,SEC_ENG_SE_AES_IV_2,__REV(BL_RDWD_FRM_BYTEP(iv))); + iv+=4; + BL_WR_REG(AESx,SEC_ENG_SE_AES_IV_1,__REV(BL_RDWD_FRM_BYTEP(iv))); + iv+=4; + BL_WR_REG(AESx,SEC_ENG_SE_AES_IV_0,__REV(BL_RDWD_FRM_BYTEP(iv))); + iv+=4; + + /* Select hardware key */ + if(keySrc==SEC_ENG_AES_KEY_HW){ + tmpVal=BL_RD_REG(AESx,SEC_ENG_SE_AES_CTRL); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_AES_HW_KEY_EN,SEC_ENG_AES_KEY_HW); + BL_WR_REG(AESx,SEC_ENG_SE_AES_CTRL,tmpVal); + + tmpVal=BL_RD_REG(AESx,SEC_ENG_SE_AES_KEY_SEL_0); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_AES_KEY_SEL_0,*key); + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_SEL_0,tmpVal); + + tmpVal=BL_RD_REG(AESx,SEC_ENG_SE_AES_KEY_SEL_1); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_AES_KEY_SEL_1,*key); + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_SEL_1,tmpVal); + + return; + } + + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + + tmpVal=BL_RD_REG(AESx,SEC_ENG_SE_AES_CTRL); + keyType=BL_GET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_AES_MODE); + if(keyType==(uint32_t)SEC_ENG_AES_KEY_192BITS){ + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + }else if(keyType==(uint32_t)SEC_ENG_AES_KEY_256BITS || keyType==(uint32_t)SEC_ENG_AES_DOUBLE_KEY_128BITS){ + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_1,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_0,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + } + + /* Select software key */ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_AES_HW_KEY_EN,SEC_ENG_AES_KEY_SW); + + BL_WR_REG(AESx,SEC_ENG_SE_AES_CTRL,tmpVal); +} + +/****************************************************************************//** + * @brief AES set KEY and IV with bigendian + * + * @param aesNo: AES ID type + * @param keySrc: AES KEY type:SEC_ENG_AES_KEY_HW or SEC_ENG_AES_KEY_SW + * @param key: AES KEY pointer + * @param iv: AES IV pointer + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID_Type aesNo,SEC_ENG_AES_Key_Src_Type keySrc,const uint8_t *key,const uint8_t *iv) +{ + uint32_t AESx = SEC_ENG_BASE+SEC_ENG_AES_OFFSET; + uint32_t tmpVal; + uint32_t keyType; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + CHECK_PARAM(IS_SEC_ENG_AES_KEY_SRC_TYPE(keySrc)); + + /* Set IV */ + BL_WR_REG(AESx,SEC_ENG_SE_AES_IV_0,BL_RDWD_FRM_BYTEP(iv)); + iv+=4; + BL_WR_REG(AESx,SEC_ENG_SE_AES_IV_1,BL_RDWD_FRM_BYTEP(iv)); + iv+=4; + BL_WR_REG(AESx,SEC_ENG_SE_AES_IV_2,BL_RDWD_FRM_BYTEP(iv)); + iv+=4; + BL_WR_REG(AESx,SEC_ENG_SE_AES_IV_3,BL_RDWD_FRM_BYTEP(iv)); + iv+=4; + + /* Select hardware key */ + if(keySrc==SEC_ENG_AES_KEY_HW){ + tmpVal=BL_RD_REG(AESx,SEC_ENG_SE_AES_CTRL); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_AES_HW_KEY_EN,SEC_ENG_AES_KEY_HW); + BL_WR_REG(AESx,SEC_ENG_SE_AES_CTRL,tmpVal); + + tmpVal=BL_RD_REG(AESx,SEC_ENG_SE_AES_KEY_SEL_0); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_AES_KEY_SEL_0,*key); + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_SEL_0,tmpVal); + + tmpVal=BL_RD_REG(AESx,SEC_ENG_SE_AES_KEY_SEL_1); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_AES_KEY_SEL_1,*key); + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_SEL_1,tmpVal); + + return ; + } + + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); + key+=4; + + tmpVal=BL_RD_REG(AESx,SEC_ENG_SE_AES_CTRL); + keyType=BL_GET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_AES_MODE); + if(keyType==(uint32_t)SEC_ENG_AES_KEY_192BITS){ + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_4,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_5,BL_RDWD_FRM_BYTEP(key)); + key+=4; + }else if(keyType==(uint32_t)SEC_ENG_AES_KEY_256BITS || keyType==(uint32_t)SEC_ENG_AES_DOUBLE_KEY_128BITS){ + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_4,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_5,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_6,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(AESx,SEC_ENG_SE_AES_KEY_7,BL_RDWD_FRM_BYTEP(key)); + key+=4; + } + + /* Select software key */ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_AES_HW_KEY_EN,SEC_ENG_AES_KEY_SW); + + BL_WR_REG(AESx,SEC_ENG_SE_AES_CTRL,tmpVal); +} + +/****************************************************************************//** + * @brief AES set counter byte type in CTR mode + * + * @param aesNo: AES ID type + * @param counterType: AES counter type + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_AES_Set_Counter_Byte(SEC_ENG_AES_ID_Type aesNo,SEC_ENG_AES_Counter_Type counterType) +{ + uint32_t AESx = SEC_ENG_BASE; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); + CHECK_PARAM(IS_SEC_ENG_AES_COUNTER_TYPE(counterType)); + + /* Set counter type */ + tmpVal = BL_RD_REG(AESx,SEC_ENG_SE_AES_0_ENDIAN); + BL_WR_REG(AESx,SEC_ENG_SE_AES_0_ENDIAN,BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_AES_0_CTR_LEN,counterType)); +} + +/****************************************************************************//** + * @brief AES encrypt or decrypt input data + * + * @param aesCtx: AES context pointer + * @param aesNo: AES ID type + * @param in: AES input data buffer to deal with + * @param len: AES input data length + * @param out: AES output data buffer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_AES_Crypt(SEC_Eng_AES_Ctx *aesCtx,SEC_ENG_AES_ID_Type aesNo,const uint8_t *in, uint32_t len,uint8_t *out) +{ + uint32_t AESx = SEC_ENG_BASE+SEC_ENG_AES_OFFSET; + uint32_t tmpVal; + uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; + + if( len %16 !=0){ + return ERROR; + } + + /* Wait finished */ + do { + tmpVal=BL_RD_REG(AESx,SEC_ENG_SE_AES_CTRL); + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + }while(BL_IS_REG_BIT_SET(tmpVal,SEC_ENG_SE_AES_BUSY)); + + /* Clear trigger */ + tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_AES_TRIG_1T); + BL_WR_REG(AESx,SEC_ENG_SE_AES_CTRL,tmpVal); + + /* Set input and output address */ + BL_WR_REG(AESx,SEC_ENG_SE_AES_MSA,(uint32_t)in); + BL_WR_REG(AESx,SEC_ENG_SE_AES_MDA,(uint32_t)out); + + /* Set message length */ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_AES_MSG_LEN,len/16); + + if(aesCtx->mode==SEC_ENG_AES_CTR){ + tmpVal=BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_AES_DEC_KEY_SEL); + }else{ + tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_AES_DEC_KEY_SEL); + } + + /* Set IV sel:0 for new, 1 for last */ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_AES_IV_SEL,aesCtx->aesFeed); + BL_WR_REG(AESx,SEC_ENG_SE_AES_CTRL,tmpVal); + + /* Trigger AES Engine */ + tmpVal=BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_AES_TRIG_1T); + BL_WR_REG(AESx,SEC_ENG_SE_AES_CTRL,tmpVal); + + /* Wait finished */ + timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; + do { + tmpVal=BL_RD_REG(AESx,SEC_ENG_SE_AES_CTRL); + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + }while(BL_IS_REG_BIT_SET(tmpVal,SEC_ENG_SE_AES_BUSY)); + + aesCtx->aesFeed=1; + + return SUCCESS; +} + +/****************************************************************************//** + * @brief AES finish function, clean register + * + * @param aesNo: AES ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_AES_Finish(SEC_ENG_AES_ID_Type aesNo) +{ + uint32_t AESx = SEC_ENG_BASE+SEC_ENG_AES_OFFSET; + uint32_t tmpVal; + uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; + + /* Wait finished */ + do { + tmpVal=BL_RD_REG(AESx,SEC_ENG_SE_AES_CTRL); + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + }while(BL_IS_REG_BIT_SET(tmpVal,SEC_ENG_SE_AES_BUSY)); + + tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_AES_EN); + + tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_AES_DEC_KEY_SEL); + + tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_AES_IV_SEL); + + BL_WR_REG(AESx,SEC_ENG_SE_AES_CTRL,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief TRNG enable TRNG interrupt + * + * @param None + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_Trng_Enable(void) +{ + uint32_t TRNGx = SEC_ENG_BASE+SEC_ENG_TRNG_OFFSET; + uint32_t tmpVal; + uint32_t timeoutCnt = SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT; + + tmpVal=BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_CTRL_0); + + /* FIXME:default reseed number is 0x1ff, to verify, use 0xa to speed up */ + //tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_TRNG_RESEED_N,0x1ff); + + /* No interrupt as default */ + tmpVal=BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_TRNG_EN); + BL_WR_REG(TRNGx,SEC_ENG_SE_TRNG_CTRL_0,tmpVal); + tmpVal=BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_TRNG_INT_CLR_1T); + BL_WR_REG(TRNGx,SEC_ENG_SE_TRNG_CTRL_0,tmpVal); + /* busy will be set to 1 after trigger, the gap is 1T */ + __NOP(); + __NOP(); + __NOP(); + __NOP(); + do { + tmpVal=BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_CTRL_0); + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + }while(BL_IS_REG_BIT_SET(tmpVal,SEC_ENG_SE_TRNG_BUSY)); + /* Clear trng interrupt */ + tmpVal=BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_TRNG_INT_CLR_1T); + BL_WR_REG(TRNGx,SEC_ENG_SE_TRNG_CTRL_0,tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_TRNG_IRQn,SEC_TRNG_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************//** + * @brief TRNG enable TRNG interrupt + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_Trng_Int_Enable(void) +{ + uint32_t TRNGx = SEC_ENG_BASE+SEC_ENG_TRNG_OFFSET; + uint32_t tmpVal; + + tmpVal=BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_CTRL_0); + + tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_TRNG_INT_MASK); + + BL_WR_REG(TRNGx,SEC_ENG_SE_TRNG_CTRL_0,tmpVal); +} + +/****************************************************************************//** + * @brief TRNG disable TRNG interrupt + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_Trng_Int_Disable(void) +{ + uint32_t TRNGx = SEC_ENG_BASE+SEC_ENG_TRNG_OFFSET; + uint32_t tmpVal; + + tmpVal=BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_CTRL_0); + + tmpVal=BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_TRNG_INT_MASK); + + BL_WR_REG(TRNGx,SEC_ENG_SE_TRNG_CTRL_0,tmpVal); +} + +/****************************************************************************//** + * @brief TRNG get random data out + * + * @param data[32]: TRNG output data + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type Sec_Eng_Trng_Read(uint8_t data[32]) +{ + uint8_t *p=(uint8_t *)data; + uint32_t TRNGx = SEC_ENG_BASE+SEC_ENG_TRNG_OFFSET; + uint32_t tmpVal; + uint32_t timeoutCnt = SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT; + + tmpVal=BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_CTRL_0); + + /* Trigger */ + tmpVal=BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_TRNG_TRIG_1T); + BL_WR_REG(TRNGx,SEC_ENG_SE_TRNG_CTRL_0,tmpVal); + + /* busy will be set to 1 after trigger, the gap is 1T */ + __NOP(); + __NOP(); + __NOP(); + __NOP(); + do { + tmpVal=BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_CTRL_0); + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + }while(BL_IS_REG_BIT_SET(tmpVal,SEC_ENG_SE_TRNG_BUSY)); + + /* copy trng value */ + BL_WRWD_TO_BYTEP(p,BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_DOUT_0)); + p+=4; + BL_WRWD_TO_BYTEP(p,BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_DOUT_1)); + p+=4; + BL_WRWD_TO_BYTEP(p,BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_DOUT_2)); + p+=4; + BL_WRWD_TO_BYTEP(p,BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_DOUT_3)); + p+=4; + BL_WRWD_TO_BYTEP(p,BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_DOUT_4)); + p+=4; + BL_WRWD_TO_BYTEP(p,BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_DOUT_5)); + p+=4; + BL_WRWD_TO_BYTEP(p,BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_DOUT_6)); + p+=4; + BL_WRWD_TO_BYTEP(p,BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_DOUT_7)); + p+=4; + + tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_TRNG_TRIG_1T); + BL_WR_REG(TRNGx,SEC_ENG_SE_TRNG_CTRL_0,tmpVal); + + /* Clear data */ + tmpVal=BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_TRNG_DOUT_CLR_1T); + BL_WR_REG(TRNGx,SEC_ENG_SE_TRNG_CTRL_0,tmpVal); + + tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_TRNG_DOUT_CLR_1T); + BL_WR_REG(TRNGx,SEC_ENG_SE_TRNG_CTRL_0,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief TRNG Interrupt Read Trigger + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_Trng_Int_Read_Trigger(void) +{ + uint32_t TRNGx = SEC_ENG_BASE+SEC_ENG_TRNG_OFFSET; + uint32_t tmpVal; + + Sec_Eng_Trng_Int_Enable(); + + tmpVal=BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_CTRL_0); + /* Trigger */ + tmpVal=BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_TRNG_TRIG_1T); + BL_WR_REG(TRNGx,SEC_ENG_SE_TRNG_CTRL_0,tmpVal); +} + +/****************************************************************************//** + * @brief TRNG get random data out with Interrupt + * + * @param data[32]: TRNG output data + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_Trng_Int_Read(uint8_t data[32]) +{ + uint8_t *p=(uint8_t *)data; + uint32_t TRNGx = SEC_ENG_BASE+SEC_ENG_TRNG_OFFSET; + uint32_t tmpVal; + + tmpVal=BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_CTRL_0); + + /* copy trng value */ + BL_WRWD_TO_BYTEP(p,BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_DOUT_0)); + p+=4; + BL_WRWD_TO_BYTEP(p,BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_DOUT_1)); + p+=4; + BL_WRWD_TO_BYTEP(p,BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_DOUT_2)); + p+=4; + BL_WRWD_TO_BYTEP(p,BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_DOUT_3)); + p+=4; + BL_WRWD_TO_BYTEP(p,BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_DOUT_4)); + p+=4; + BL_WRWD_TO_BYTEP(p,BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_DOUT_5)); + p+=4; + BL_WRWD_TO_BYTEP(p,BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_DOUT_6)); + p+=4; + BL_WRWD_TO_BYTEP(p,BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_DOUT_7)); + p+=4; + + tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_TRNG_TRIG_1T); + BL_WR_REG(TRNGx,SEC_ENG_SE_TRNG_CTRL_0,tmpVal); + + /* Clear data */ + tmpVal=BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_TRNG_DOUT_CLR_1T); + BL_WR_REG(TRNGx,SEC_ENG_SE_TRNG_CTRL_0,tmpVal); + + tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_TRNG_DOUT_CLR_1T); + BL_WR_REG(TRNGx,SEC_ENG_SE_TRNG_CTRL_0,tmpVal); +} + +/****************************************************************************//** + * @brief Disable TRNG + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_Trng_Disable(void) +{ + uint32_t TRNGx = SEC_ENG_BASE+SEC_ENG_TRNG_OFFSET; + uint32_t tmpVal; + + tmpVal=BL_RD_REG(TRNGx,SEC_ENG_SE_TRNG_CTRL_0); + + tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_TRNG_EN); + //tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_TRNG_RESEED_N); + tmpVal=BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_TRNG_INT_CLR_1T); + + BL_WR_REG(TRNGx,SEC_ENG_SE_TRNG_CTRL_0,tmpVal); +} + +/****************************************************************************//** + * @brief PKA Reset + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_Reset(void) +{ + uint8_t val; + + //Disable sec engine + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, 0); + + //Enable sec engine + val = 1<<3; + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, val); +} + +/****************************************************************************//** + * @brief PKA Enable big endian + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_BigEndian_Enable(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); + tmpVal=BL_SET_REG_BIT(tmpVal,SEC_ENG_SE_PKA_0_ENDIAN); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_PKA_IRQn,SEC_PKA_IRQHandler); +#endif +} + +/****************************************************************************//** + * @brief PKA Enable little endian + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LittleEndian_Enable(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); + tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_PKA_0_ENDIAN); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SEC_PKA_IRQn,SEC_PKA_IRQHandler); +#endif +} + +/****************************************************************************//** + * @brief PKA clear interrupt + * + * @param None + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_Clear_Int(void) +{ + uint32_t ctrl; + + ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); + ctrl = BL_SET_REG_BIT(ctrl, SEC_ENG_SE_PKA_0_INT_CLR_1T); + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, ctrl); + + ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); + ctrl = BL_CLR_REG_BIT(ctrl, SEC_ENG_SE_PKA_0_INT_CLR_1T); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, ctrl); +} + +/****************************************************************************//** + * @brief PKA get Register size according to Register type + * + * @param reg_type: PKA Register type + * + * @return Register size + * +*******************************************************************************/ +static uint16_t Sec_Eng_PKA_Get_Reg_Size(SEC_ENG_PKA_REG_SIZE_Type reg_type) +{ + switch(reg_type) + { + case SEC_ENG_PKA_REG_SIZE_8: + return 8; + case SEC_ENG_PKA_REG_SIZE_16: + return 16; + case SEC_ENG_PKA_REG_SIZE_32: + return 32; + case SEC_ENG_PKA_REG_SIZE_64: + return 64; + case SEC_ENG_PKA_REG_SIZE_96: + return 96; + case SEC_ENG_PKA_REG_SIZE_128: + return 128; + case SEC_ENG_PKA_REG_SIZE_192: + return 192; + case SEC_ENG_PKA_REG_SIZE_256: + return 256; + case SEC_ENG_PKA_REG_SIZE_384: + return 384; + case SEC_ENG_PKA_REG_SIZE_512: + return 512; + default: + return 0; + } +} + +/****************************************************************************//** + * @brief PKA set pre-load register configuration + * + * @param size: Data size in word to write + * @param regIndex: Register index + * @param regType: Register type + * @param op: PKA operation + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +static void Sec_Eng_PKA_Write_Pld_Cfg(uint16_t size, uint8_t regIndex, SEC_ENG_PKA_REG_SIZE_Type regType, SEC_ENG_PKA_OP_Type op, uint8_t lastOp) +{ + struct pka0_pld_cfg cfg; + + cfg.value.BF.size = size; + cfg.value.BF.d_reg_index = regIndex; + cfg.value.BF.d_reg_type = regType; + cfg.value.BF.op = op; + cfg.value.BF.last_op = lastOp; + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); +} + +/****************************************************************************//** + * @brief PKA write common operation first configuration + * + * @param s0RegIndex: Register index + * @param s0RegType: Register type + * @param dRegIndex: Result Register index + * @param dRegType: Result Register type + * @param op: PKA operation + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +static void Sec_Eng_PKA_Write_Common_OP_First_Cfg(uint8_t s0RegIndex, uint8_t s0RegType, uint8_t dRegIndex, uint8_t dRegType, + uint8_t op, uint8_t lastOp) +{ + struct pka0_common_op_first_cfg cfg; + + cfg.value.BF.s0_reg_idx = s0RegIndex; + cfg.value.BF.s0_reg_type = s0RegType; + if(op != SEC_ENG_PKA_OP_LCMP) + { + cfg.value.BF.d_reg_idx = dRegIndex; + cfg.value.BF.d_reg_type = dRegType; + } + cfg.value.BF.op = op; + cfg.value.BF.last_op = lastOp; + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); +} + +/****************************************************************************//** + * @brief PKA write common operation second configuration1 + * + * @param s1RegIndex: Register index + * @param s1RegType: Register type + * + * @return None + * +*******************************************************************************/ +static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(uint8_t s1RegIndex, uint8_t s1RegType) +{ + struct pka0_common_op_snd_cfg_S1_only cfg; + + cfg.value.BF.s1_reg_idx = s1RegIndex; + cfg.value.BF.s1_reg_type = s1RegType; + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); +} + +/****************************************************************************//** + * @brief PKA write common operation second configuration2 + * + * @param s2RegIndex: Register index + * @param s2RegType: Register type + * + * @return None + * +*******************************************************************************/ +static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(uint8_t s2RegIndex, uint8_t s2RegType) +{ + struct pka0_common_op_snd_cfg_S2_only cfg; + + cfg.value.BF.s2_reg_idx = s2RegIndex; + cfg.value.BF.s2_reg_type = s2RegType; + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); +} + +/****************************************************************************//** + * @brief PKA write common operation second configuration1 and configuration 2 + * + * @param s1RegIndex: Configuration 1 Register index + * @param s1RegType: Configuration 1 Register type + * @param s2RegIndex: Configuration 2 Register index + * @param s2RegType: Configuration 3 Register type + * + * @return None + * +*******************************************************************************/ +static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(uint8_t s1RegIndex, uint8_t s1RegType, uint8_t s2RegIndex, uint8_t s2RegType) +{ + struct pka0_common_op_snd_cfg_S1_S2 cfg; + + cfg.value.BF.s1_reg_idx = s1RegIndex; + cfg.value.BF.s1_reg_type = s1RegType; + cfg.value.BF.s2_reg_idx = s2RegIndex; + cfg.value.BF.s2_reg_type = s2RegType; + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); +} + +/****************************************************************************//** + * @brief PKA wait for complete interrupt + * + * @param None + * + * @return SUCCESS + * +*******************************************************************************/ +static BL_Err_Type Sec_Eng_PKA_Wait_ISR(void) +{ + uint32_t pka0_ctrl; + uint32_t timeoutCnt = SEC_ENG_PKA_INT_TIMEOUT_COUNT; + + do{ + pka0_ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + }while(!BL_GET_REG_BITS_VAL(pka0_ctrl, SEC_ENG_SE_PKA_0_INT)); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief PKA read block data from register + * + * @param dest: Pointer to buffer address + * @param src: Pointer to register address + * @param len: Data len in word + * + * @return None + * +*******************************************************************************/ +#ifdef ARCH_ARM +#ifndef __GNUC__ +__ASM void Sec_Eng_PKA_Read_Block(uint32_t *dest,const uint32_t *src,uint32_t len) +{ + PUSH {R3-R6,LR} +Start0 + CMP R2,#4 + BLT Finish0 + LDR R3,[R1] + LDR R4,[R1] + LDR R5,[R1] + LDR R6,[R1] + STMIA R0!,{R3-R6} + SUBS R2,R2,#4 + B Start0 +Finish0 + POP {R3-R6,PC} +} +#else +void Sec_Eng_PKA_Read_Block(uint32_t *dest,const uint32_t *src,uint32_t len) +{ +__asm__ __volatile__("push {r3-r6,lr}\n\t" +"Start0 :" +"cmp r2,#4\n\t" +"blt Finish0\n\t" +"ldr r3,[r1]\n\t" +"ldr r4,[r1]\n\t" +"ldr r5,[r1]\n\t" +"ldr r6,[r1]\n\t" +"stmia r0!,{r3-r6}\n\t" +"sub r2,r2,#4\n\t" +"b Start0\n\t" +"Finish0 :" +"pop {r3-r6,pc}\n\t" +); +} +#endif +#endif +#ifdef ARCH_RISCV +void Sec_Eng_PKA_Read_Block(uint32_t *dest,const uint32_t *src,uint32_t len) +{ + uint32_t wrLen=len-len%4; + uint32_t i; + + for(i=0;iregLen/4){ + size=regLen/4; + } + Sec_Eng_PKA_Write_Block((uint32_t*)(SEC_ENG_BASE+SEC_ENG_SE_PKA_0_RW_OFFSET),data,size); + index=size-(size%4); + while(index < size) + { + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, data[index]); + index++; + } +} + +/****************************************************************************//** + * @brief PKA read data from register + * + * @param regType: Register type + * @param regIdx: Register index + * @param result: Data buffer + * @param retSize: Data length in word + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_Read_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIdx, uint32_t *result, uint8_t retSize) +{ + uint16_t regSize; + uint32_t dummyData = 0; + + regSize = Sec_Eng_PKA_Get_Reg_Size(regType); + if(retSize > regSize/4){ + result = NULL; + return; + } + + Sec_Eng_PKA_Write_Pld_Cfg(retSize, regIdx, regType, SEC_ENG_PKA_OP_CFLIR_BUFFER,1); + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); + + Sec_Eng_PKA_Get_Result(result, retSize,regSize); +} + +/****************************************************************************//** + * @brief PKA clear register + * + * @param dRegType: Register type + * @param dRegIdx: Register index + * @param size: Data length in word + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_Type dRegType, uint8_t dRegIdx, uint8_t size,uint8_t lastOp) +{ + uint32_t dummyData = 0; + + Sec_Eng_PKA_Write_Pld_Cfg(size, dRegIdx, dRegType, SEC_ENG_PKA_OP_CLIR, lastOp); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); + + if(lastOp){ + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************//** + * @brief PKA load data to register + * + * @param regType: regType: Register type + * @param regIndex: regIndex: Register index + * @param data: data: Data buffer + * @param lastOp: size: Data length in word + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_Write_Immediate( SEC_ENG_PKA_REG_SIZE_Type regType,uint8_t regIndex,uint32_t data,uint8_t lastOp) +{ + struct pka0_pldi_cfg cfg; + + cfg.value.BF.rsvd=0; + cfg.value.BF.d_reg_index = regIndex; + cfg.value.BF.d_reg_type = regType; + cfg.value.BF.op = SEC_ENG_PKA_OP_SLIR; + cfg.value.BF.last_op = lastOp; + + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, data); + + if(lastOp){ + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************//** + * @brief PKA negative source data:D = (1 << SIZE{S0})-S0 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source Register type + * @param s0RegIdx: Source Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_NREG(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,uint8_t lastOp) +{ + uint32_t dummyData = 0; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_NLIR, lastOp); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); + + if(lastOp){ + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************//** + * @brief PKA move data:D = S0 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source Register type + * @param s0RegIdx: Source Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_Move_Data(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,uint8_t lastOp) +{ + uint32_t dummyData = 0; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MOVDAT, lastOp); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); + + if(lastOp){ + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************//** + * @brief PKA resize data:D = S0, D.Size = S0.Size + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source Register type + * @param s0RegIdx: Source Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_RESIZE(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,uint8_t lastOp) +{ + uint32_t dummyData = 0; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_RESIZE, lastOp); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); + if(lastOp){ + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************//** + * @brief PKA mod add:D = (S0 + S1) mod S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_MADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx,uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MADD, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType); + + if(lastOp){ + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************//** + * @brief PKA mod sub:D = (S0 - S1) mod S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_MSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx,uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MSUB, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType); + + if(lastOp){ + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************//** + * @brief PKA mod :D = S0 mod S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_MREM(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s2RegType, uint8_t s2RegIdx,uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MREM, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType); + + if(lastOp){ + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************//** + * @brief PKA mod mul:D = (S0 * S1) mod S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_MMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx,uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MMUL, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType); + + if(lastOp){ + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************//** + * @brief PKA mod sqr:D = (S0 ^ 2) mod S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_MSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s2RegType, uint8_t s2RegIdx,uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MSQR, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType); + + if(lastOp){ + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************//** + * @brief PKA mod exp:D = (S0 ^ S1) mod S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_MEXP(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx,uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MEXP, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType); + + if(lastOp){ + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************//** + * @brief PKA mod exp:D = (S0 ^ (S2-2) ) mod S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s2RegType, uint8_t s2RegIdx,uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MINV, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType); + + if(lastOp){ + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************//** + * @brief PKA Report COUT to 1 when S0 < S1 + * + * @param cout: Compare result + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LCMP(uint8_t *cout, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx) +{ + uint32_t pka0_ctrl = 0x00; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, 0, 0, SEC_ENG_PKA_OP_LCMP, 1); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType); + + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + pka0_ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); + + *cout = (pka0_ctrl&SEC_ENG_PKA_STATUS_LAST_OPC_MASK)>>SEC_ENG_PKA_STATUS_LAST_OPC_OFFSET; +} + +/****************************************************************************//** + * @brief PKA add:D = S0 + S1 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, uint8_t s1RegIdx,uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LADD, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType); + + if(lastOp){ + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************//** + * @brief PKA sub:D = S0 - S1 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, uint8_t s1RegIdx,uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LSUB, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType); + + if(lastOp){ + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************//** + * @brief PKA mul:D = S0 * S1 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s1RegType: Source 1 Register type + * @param s1RegIdx: Source 1 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s1RegType, uint8_t s1RegIdx,uint8_t lastOp) +{ + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LMUL, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType); + + if(lastOp){ + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************//** + * @brief PKA sqr:D = S0^2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,uint8_t lastOp) +{ + uint32_t dummyData = 0; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LSQR, lastOp); + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); + + if(lastOp){ + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************//** + * @brief PKA div:D = S0 / S2 + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param s2RegType: Source 2 Register type + * @param s2RegIdx: Source 2 Register index + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LDIV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint8_t s2RegType, uint8_t s2RegIdx,uint8_t lastOp) +{ + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LDIV, lastOp); + Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType); + + if(lastOp){ + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************//** + * @brief PKA shift:D = S0 << BIT SHIFT + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param bit_shift: Bits to shift + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LMUL2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint16_t bit_shift,uint8_t lastOp) +{ + struct pka0_bit_shift_op_cfg cfg; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LMUL2N, 0); + + cfg.value.BF.bit_shift = bit_shift; + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); + + if(lastOp){ + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************//** + * @brief PKA shift:D = S0 >> BIT SHIFT + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param bit_shift: Bits to shift + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LDIV2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint16_t bit_shift,uint8_t lastOp) +{ + struct pka0_bit_shift_op_cfg cfg; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LDIV2N, 0); + + cfg.value.BF.bit_shift = bit_shift; + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); + + if(lastOp){ + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + +/****************************************************************************//** + * @brief PKA mod 2N:D = S0 % ((1 << BIT SHIFT)-1) + * + * @param dRegType: Destination Register type + * @param dRegIdx: Destination Register index + * @param s0RegType: Source 0 Register type + * @param s0RegIdx: Source 0 Register index + * @param bit_shift: Bits to shift + * @param lastOp: Last operation + * + * @return None + * +*******************************************************************************/ +void Sec_Eng_PKA_LMOD2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, + uint16_t bit_shift,uint8_t lastOp) +{ + struct pka0_bit_shift_op_cfg cfg; + + Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MOD2N, lastOp); + + cfg.value.BF.bit_shift = bit_shift; + BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); + + if(lastOp){ + Sec_Eng_PKA_Wait_ISR(); + Sec_Eng_PKA_Clear_Int(); + } +} + + +/****************************************************************************//** + * @brief PKA GF to Mont filed 2N:d = (a<
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_glb.h" +#include "bl602_sf_cfg.h" +#include "softcrc.h" +#include "bl602_xip_sflash.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CFG + * @{ + */ + +/** @defgroup SF_CFG_Private_Macros + * @{ + */ +#define BFLB_FLASH_CFG_MAGIC "FCFG" + +/*@} end of group SF_CFG_Private_Macros */ + +/** @defgroup SF_CFG_Private_Types + * @{ + */ +typedef struct { + uint32_t jedecID; + char *name; + const SPI_Flash_Cfg_Type *cfg; +}Flash_Info_t; + + +/*@} end of group SF_CFG_Private_Types */ + +/** @defgroup SF_CFG_Private_Variables + * @{ + */ +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_80DV={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0xef, + + .deBurstWrapCmd=0x77, + .deBurstWrapCmdDmyClk=0x3, + .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, + .deBurstWrapData=0xF0, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=1, + .qeBit=0x01, + .qeWriteRegLen=0x02, + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x35, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x01, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=16/8, + .cReadSupport=0, + .cReadMode=0xFF, + + .burstWrapCmd=0x77, + .burstWrapCmdDmyClk=0x3, + .burstWrapDataMode=SF_CTRL_DATA_4_LINES, + .burstWrapData=0x40, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x32, + .qppAddrMode=SF_CTRL_ADDR_1_LINE, + + .ioMode=SF_CTRL_QIO_MODE, + .clkDelay=1, + .clkInvert=0x3d, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=0, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=300, + .timeE32k=1200, + .timeE64k=1200, + .timePagePgm=5, + .timeCe=20*1000, + .pdDelay=3, + .qeData=0, +}; +#if 0 +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_80BV={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0xef, + + .deBurstWrapCmd=0x77, + .deBurstWrapCmdDmyClk=0x3, + .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, + .deBurstWrapData=0xF0, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=1, + .qeBit=0x01, + .qeWriteRegLen=0x02, /*Q08BV,Q16DV: 0x02.Q32FW,Q32FV: 0x01 */ + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x35, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x01, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=16/8, + .cReadSupport=1, + .cReadMode=0x20, + + .burstWrapCmd=0x77, + .burstWrapCmdDmyClk=0x3, + .burstWrapDataMode=SF_CTRL_DATA_4_LINES, + .burstWrapData=0x40, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x32, + .qppAddrMode=SF_CTRL_ADDR_1_LINE, + + .ioMode=SF_CTRL_QIO_MODE, + .clkDelay=1, + .clkInvert=0x3d, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=0, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=300, + .timeE32k=1200, + .timeE64k=1200, + .timePagePgm=5, + .timeCe=20*1000, + .pdDelay=3, + .qeData=0, +}; +#endif +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0xef, + + .deBurstWrapCmd=0x77, + .deBurstWrapCmdDmyClk=0x3, + .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, + .deBurstWrapData=0xF0, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=1, + .qeBit=0x01, + .qeWriteRegLen=0x01, + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x35, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x31, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=16/8, + .cReadSupport=1, + .cReadMode=0x20, + + .burstWrapCmd=0x77, + .burstWrapCmdDmyClk=0x3, + .burstWrapDataMode=SF_CTRL_DATA_4_LINES, + .burstWrapData=0x40, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x32, + .qppAddrMode=SF_CTRL_ADDR_1_LINE, + + .ioMode=SF_CTRL_QIO_MODE, + .clkDelay=1, + .clkInvert=0x3f, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=0, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=400, + .timeE32k=1600, + .timeE64k=2000, + .timePagePgm=5, + .timeCe=20*1000, + .pdDelay=3, + .qeData=0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Issi={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0x9d, + + .deBurstWrapCmd=0xC0, + .deBurstWrapCmdDmyClk=0x00, + .deBurstWrapDataMode=SF_CTRL_DATA_1_LINE, + .deBurstWrapData=0x00, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=0, + .qeBit=0x06, + .qeWriteRegLen=0x01, + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x35, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x31, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=16/8, + .cReadSupport=1, + .cReadMode=0xA0, + + .burstWrapCmd=0xC0, + .burstWrapCmdDmyClk=0x00, + .burstWrapDataMode=SF_CTRL_DATA_1_LINE, + .burstWrapData=0x06, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x32, + .qppAddrMode=SF_CTRL_ADDR_1_LINE, + + .ioMode=SF_CTRL_QIO_MODE, + .clkDelay=1, + .clkInvert=0x3f, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=0, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=300, + .timeE32k=1200, + .timeE64k=1200, + .timePagePgm=5, + .timeCe=20*1000, + .pdDelay=5, + .qeData=0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0xc8, + + .deBurstWrapCmd=0x77, + .deBurstWrapCmdDmyClk=0x3, + .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, + .deBurstWrapData=0xF0, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=1, + .qeBit=0x01, + .qeWriteRegLen=0x02, + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x35, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x01, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=16/8, + .cReadSupport=1, + .cReadMode=0x20, + + .burstWrapCmd=0x77, + .burstWrapCmdDmyClk=0x3, + .burstWrapDataMode=SF_CTRL_DATA_4_LINES, + .burstWrapData=0x40, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x32, + .qppAddrMode=SF_CTRL_ADDR_1_LINE, + + .ioMode=SF_CTRL_QIO_MODE, + .clkDelay=1, + .clkInvert=0x3f, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=0, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=300, + .timeE32k=1200, + .timeE64k=1200, + .timePagePgm=5, + .timeCe=20*1000, + .pdDelay=20, + .qeData=0, +}; +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q80E_Q16E={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0xc8, + + .deBurstWrapCmd=0x77, + .deBurstWrapCmdDmyClk=0x3, + .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, + .deBurstWrapData=0xF0, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=1, + .qeBit=0x01, + .qeWriteRegLen=0x02, + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x35, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x01, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=16/8, + .cReadSupport=1, + .cReadMode=0xA0, + + .burstWrapCmd=0x77, + .burstWrapCmdDmyClk=0x3, + .burstWrapDataMode=SF_CTRL_DATA_4_LINES, + .burstWrapData=0x40, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x32, + .qppAddrMode=SF_CTRL_ADDR_1_LINE, + + .ioMode=SF_CTRL_QIO_MODE, + .clkDelay=1, + .clkInvert=0x3f, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=0, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=300, + .timeE32k=1200, + .timeE64k=1200, + .timePagePgm=5, + .timeCe=20*1000, + .pdDelay=20, + .qeData=0, +}; +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_WQ80E_WQ16E={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0xc8, + + .deBurstWrapCmd=0x77, + .deBurstWrapCmdDmyClk=0x3, + .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, + .deBurstWrapData=0xF0, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=1, + .qeBit=0x01, + .qeWriteRegLen=0x02, + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x35, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x01, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=32/8, + .cReadSupport=1, + .cReadMode=0xA0, + + .burstWrapCmd=0x77, + .burstWrapCmdDmyClk=0x3, + .burstWrapDataMode=SF_CTRL_DATA_4_LINES, + .burstWrapData=0x40, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x32, + .qppAddrMode=SF_CTRL_ADDR_1_LINE, + + .ioMode=SF_CTRL_QIO_MODE, + .clkDelay=1, + .clkInvert=0x3f, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=8/8, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=300, + .timeE32k=1200, + .timeE64k=1200, + .timePagePgm=5, + .timeCe=20*1000, + .pdDelay=20, + .qeData=0x12, +}; +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q32C={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0xc8, + + .deBurstWrapCmd=0x77, + .deBurstWrapCmdDmyClk=0x3, + .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, + .deBurstWrapData=0xF0, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=1, + .qeBit=0x01, + .qeWriteRegLen=0x01, + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x35, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x31, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=16/8, + .cReadSupport=1, + .cReadMode=0x20, + + .burstWrapCmd=0x77, + .burstWrapCmdDmyClk=0x3, + .burstWrapDataMode=SF_CTRL_DATA_4_LINES, + .burstWrapData=0x40, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x32, + .qppAddrMode=SF_CTRL_ADDR_1_LINE, + + .ioMode=SF_CTRL_QIO_MODE, + .clkDelay=1, + .clkInvert=0x3f, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=0, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=300, + .timeE32k=1200, + .timeE64k=1200, + .timePagePgm=5, + .timeCe=20*1000, + .pdDelay=20, + .qeData=0, +}; +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0xC2, + + .deBurstWrapCmd=0xC0, + .deBurstWrapCmdDmyClk=0x00, + .deBurstWrapDataMode=SF_CTRL_DATA_1_LINE, + .deBurstWrapData=0x10, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=0, + .qeBit=0x06, + .qeWriteRegLen=0x02, + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x35, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x01, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=16/8, + .cReadSupport=1, + .cReadMode=0xA5, + + .burstWrapCmd=0xC0, + .burstWrapCmdDmyClk=0x00, + .burstWrapDataMode=SF_CTRL_DATA_1_LINE, + .burstWrapData=0x02, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x38, + .qppAddrMode=SF_CTRL_ADDR_4_LINES, + + .ioMode=SF_CTRL_QIO_MODE, + .clkDelay=1, + .clkInvert=0x3f, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=0, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=300, + .timeE32k=1200, + .timeE64k=1200, + .timePagePgm=5, + .timeCe=20*1000, + .pdDelay=45, + .qeData=0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic_1635F={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0xC2, + + .deBurstWrapCmd=0xC0, + .deBurstWrapCmdDmyClk=0x00, + .deBurstWrapDataMode=SF_CTRL_DATA_1_LINE, + .deBurstWrapData=0x10, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=0, + .qeBit=0x06, + .qeWriteRegLen=0x01, + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x35, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x01, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=16/8, + .cReadSupport=1, + .cReadMode=0xA5, + + .burstWrapCmd=0xC0, + .burstWrapCmdDmyClk=0x00, + .burstWrapDataMode=SF_CTRL_DATA_1_LINE, + .burstWrapData=0x02, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x38, + .qppAddrMode=SF_CTRL_ADDR_4_LINES, + + .ioMode=SF_CTRL_QIO_MODE, + .clkDelay=1, + .clkInvert=0x3f, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=0, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=300, + .timeE32k=1200, + .timeE64k=1200, + .timePagePgm=5, + .timeCe=20*1000, + .pdDelay=45, + .qeData=0, +}; +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Xtx_Q80B_F16B={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0x0B, + + .deBurstWrapCmd=0x77, + .deBurstWrapCmdDmyClk=0x3, + .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, + .deBurstWrapData=0xF0, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=0x01, + .qeBit=0x01, + .qeWriteRegLen=0x02, + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x35, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x01, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=16/8, + .cReadSupport=1, + .cReadMode=0x20, + + .burstWrapCmd=0x77, + .burstWrapCmdDmyClk=0x3, + .burstWrapDataMode=SF_CTRL_DATA_4_LINES, + .burstWrapData=0x40, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x32, + .qppAddrMode=SF_CTRL_ADDR_1_LINE, + + .ioMode=0x14, + .clkDelay=1, + .clkInvert=0x3f, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=0, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=6000, + .timeE32k=1200, + .timeE64k=1200, + .timePagePgm=5, + .timeCe=20*1000, + .pdDelay=20, + .qeData=0, +}; +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Xtx={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0x0B, + + .deBurstWrapCmd=0x77, + .deBurstWrapCmdDmyClk=0x3, + .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, + .deBurstWrapData=0xF0, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=0x01, + .qeBit=0x01, + .qeWriteRegLen=0x02, + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x35, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x01, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=16/8, + .cReadSupport=1, + .cReadMode=0x20, + + .burstWrapCmd=0x77, + .burstWrapCmdDmyClk=0x3, + .burstWrapDataMode=SF_CTRL_DATA_4_LINES, + .burstWrapData=0x40, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x32, + .qppAddrMode=SF_CTRL_ADDR_1_LINE, + + .ioMode=SF_CTRL_QIO_MODE, + .clkDelay=1, + .clkInvert=0x3f, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=0, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=6000, + .timeE32k=1200, + .timeE64k=1200, + .timePagePgm=5, + .timeCe=20*1000, + .pdDelay=20, + .qeData=0, +}; +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Puya_Q80L_Q80H_Q16H={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0x85, + + .deBurstWrapCmd=0x77, + .deBurstWrapCmdDmyClk=0x3, + .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, + .deBurstWrapData=0xF0, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=0x01, + .qeBit=0x01, + .qeWriteRegLen=0x02, + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x35, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x01, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=16/8, + .cReadSupport=1, + .cReadMode=0x20, + + .burstWrapCmd=0x77, + .burstWrapCmdDmyClk=0x3, + .burstWrapDataMode=SF_CTRL_DATA_4_LINES, + .burstWrapData=0x40, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x32, + .qppAddrMode=SF_CTRL_ADDR_1_LINE, + + .ioMode=SF_CTRL_QIO_MODE, + .clkDelay=1, + .clkInvert=0x3d, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=0, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=300, + .timeE32k=1200, + .timeE64k=1200, + .timePagePgm=5, + .timeCe=20*1000, + .pdDelay=8, + .qeData=0, +}; +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Puya_Q32H={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0x85, + + .deBurstWrapCmd=0x77, + .deBurstWrapCmdDmyClk=0x3, + .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, + .deBurstWrapData=0xF0, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=0x01, + .qeBit=0x01, + .qeWriteRegLen=0x01, + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x35, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x31, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=16/8, + .cReadSupport=1, + .cReadMode=0x20, + + .burstWrapCmd=0x77, + .burstWrapCmdDmyClk=0x3, + .burstWrapDataMode=SF_CTRL_DATA_4_LINES, + .burstWrapData=0x40, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x32, + .qppAddrMode=SF_CTRL_ADDR_1_LINE, + + .ioMode=SF_CTRL_QIO_MODE, + .clkDelay=1, + .clkInvert=0x3f, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=0, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=300, + .timeE32k=1200, + .timeE64k=1200, + .timePagePgm=5, + .timeCe=20*1000, + .pdDelay=8, + .qeData=0, +}; +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Boya={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0x68, + + .deBurstWrapCmd=0x77, + .deBurstWrapCmdDmyClk=0x3, + .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, + .deBurstWrapData=0xF0, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=0x01, + .qeBit=0x01, + .qeWriteRegLen=0x01, + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x35, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x31, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=16/8, + .cReadSupport=1, + .cReadMode=0x20, + + .burstWrapCmd=0x77, + .burstWrapCmdDmyClk=0x3, + .burstWrapDataMode=SF_CTRL_DATA_4_LINES, + .burstWrapData=0x40, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x32, + .qppAddrMode=SF_CTRL_ADDR_1_LINE, + + .ioMode=SF_CTRL_QIO_MODE, + .clkDelay=1, + .clkInvert=0x3f, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=0, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=300, + .timeE32k=1200, + .timeE64k=1200, + .timePagePgm=5, + .timeCe=20*1000, + .pdDelay=20, + .qeData=0, +}; +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_FT_VQ80={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0xef, + + .deBurstWrapCmd=0x77, + .deBurstWrapCmdDmyClk=0x3, + .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, + .deBurstWrapData=0xF0, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=1, + .qeBit=0x01, + .qeWriteRegLen=0x01, + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x35, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x31, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=16/8, + .cReadSupport=1, + .cReadMode=0x20, + + .burstWrapCmd=0x77, + .burstWrapCmdDmyClk=0x3, + .burstWrapDataMode=SF_CTRL_DATA_4_LINES, + .burstWrapData=0x40, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x32, + .qppAddrMode=SF_CTRL_ADDR_1_LINE, + + .ioMode=SF_CTRL_QIO_MODE, + .clkDelay=1, + .clkInvert=0x3f, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=0, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=300, + .timeE32k=1200, + .timeE64k=1200, + .timePagePgm=5, + .timeCe=20*1000, + .pdDelay=8, + .qeData=0, +}; + +static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[]={ + { + .jedecID=0x1440ef, + //.name="Winb_80DV_08_33", + .cfg=&flashCfg_Winb_80DV, + }, + { + .jedecID=0x1540ef, + //.name="Winb_16DV_16_33", + .cfg=&flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, + }, + { + .jedecID=0x1570ef, + //.name="Winb_16jV_16_33_DTR", + .cfg=&flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, + }, + { + .jedecID=0x1640ef, + //.name="Winb_32FV_32_33", + .cfg=&flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, + }, + { + .jedecID=0x1460ef, + //.name="Winb_80EW_08_18", + .cfg=&flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, + }, + { + .jedecID=0x1560ef, + //.name="Winb_16FW_16_18", + .cfg=&flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, + }, + { + .jedecID=0x1660ef, + //.name="Winb_32FW_32_18", + .cfg=&flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, + }, + { + .jedecID=0x1860ef, + //.name="Winb_128FW_128_18", + .cfg=&flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, + }, + { + .jedecID=0x1680ef, + //.name="Winb_32JW_32_18", + .cfg=&flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, + }, + { + .jedecID=0x13605e, + //.name="Zbit_04_33", + .cfg=&flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, + }, + { + .jedecID=0x14605e, + //.name="Zbit_08_33", + .cfg=&flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, + }, + { + .jedecID=0x14609d, + //.name="ISSI_08_33", + .cfg=&flashCfg_Issi, + }, + { + .jedecID=0x15609d, + //.name="ISSI_16_33", + .cfg=&flashCfg_Issi, + }, + { + .jedecID=0x16609d, + //.name="ISSI_32_33", + .cfg=&flashCfg_Issi, + }, + { + .jedecID=0x14709d, + //.name="ISSI_08_18", + .cfg=&flashCfg_Issi, + }, + { + .jedecID=0x15709d, + //.name="ISSI_16_18", + .cfg=&flashCfg_Issi, + }, + { + .jedecID=0x16709d, + //.name="ISSI_32_18", + .cfg=&flashCfg_Issi, + }, + { + .jedecID=0x1440C8, + //.name="GD_Q08E_08_33", + .cfg=&flashCfg_Gd_Q80E_Q16E, + }, + { + .jedecID=0x1540C8, + //.name="GD_Q16E_16_33", + .cfg=&flashCfg_Gd_Q80E_Q16E, + }, + { + .jedecID=0x1640C8, + //.name="GD_Q32C_32_33", + .cfg=&flashCfg_Gd_Q32C, + }, + { + .jedecID=0x1460C8, + //.name="GD_LQ08C_08_18", + .cfg=&flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, + }, + { + .jedecID=0x1560C8, + //.name="GD_LE16C_16_18", + .cfg=&flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, + }, + { + .jedecID=0x1660C8, + //.name="GD_LQ32D_32_18", + .cfg=&flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, + }, + { + .jedecID=0x1465C8, + //.name="GD_WQ80E_80_33", + .cfg=&flashCfg_Gd_WQ80E_WQ16E, + }, + { + .jedecID=0x1565C8, + //.name="GD_WQ16E_16_33", + .cfg=&flashCfg_Gd_WQ80E_WQ16E, + }, + { + .jedecID=0x1665C8, + //.name="GD_WQ32E_32_33", + .cfg=&flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, + }, + { + .jedecID=0x3425C2, + //.name="MX_25V80_08_18", + .cfg=&flashCfg_Mxic, + }, + { + .jedecID=0x3525C2, + //.name="MX_25U16_35_18", + .cfg=&flashCfg_Mxic_1635F, + }, + { + .jedecID=0x3625C2, + //.name="MX_25V32_32_18", + .cfg=&flashCfg_Mxic, + }, + { + .jedecID=0x13400B, + //.name="XT_25F04D_04_33", + .cfg=&flashCfg_Xtx, + }, + { + .jedecID=0x15400B, + //.name="XT_25F16B_16_33", + .cfg=&flashCfg_Xtx_Q80B_F16B, + }, + { + .jedecID=0x16400B, + //.name="XT_25F32B_32_33", + .cfg=&flashCfg_Xtx, + }, + { + .jedecID=0x14600B, + //.name="XT_25Q80B_08_18", + .cfg=&flashCfg_Xtx_Q80B_F16B, + }, + { + .jedecID=0x16600B, + //.name="XT_25Q32B_32_18", + .cfg=&flashCfg_Xtx, + }, + { + .jedecID=0x146085, + //.name="Puya_Q80L/H_08_18/33", + .cfg=&flashCfg_Puya_Q80L_Q80H_Q16H, + }, + { + .jedecID=0x156085, + //.name="Puya_Q16H_16_33", + .cfg=&flashCfg_Puya_Q80L_Q80H_Q16H, + }, + { + .jedecID=0x166085, + //.name="Puya_Q32H_32_33", + .cfg=&flashCfg_Puya_Q32H, + }, + { + .jedecID=0x154068, + //.name="Boya_Q16B_16_33", + .cfg=&flashCfg_Boya, + }, + { + .jedecID=0x164068, + //.name="Boya_Q32B_32_33", + .cfg=&flashCfg_Boya, + }, + { + .jedecID=0x174068, + //.name="Boya_Q64A_64_33", + .cfg=&flashCfg_Boya, + }, + { + .jedecID=0x184068, + //.name="Boya_Q128A_128_33", + .cfg=&flashCfg_Boya, + }, + { + .jedecID=0x14605E, + //.name="FT_VQ80", + .cfg=&flashCfg_FT_VQ80, + } +}; + +/*@} end of group SF_CFG_Private_Variables */ + +/** @defgroup SF_CFG_Global_Variables + * @{ + */ + +/*@} end of group SF_CFG_Global_Variables */ + +/** @defgroup SF_CFG_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SF_CFG_Private_Fun_Declaration */ + +/** @defgroup SF_CFG_Private_Functions + * @{ + */ + +/****************************************************************************//** + * @brief Init external flash GPIO according to flash GPIO config + * + * @param extFlashPin: Flash GPIO config + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin) +{ + GLB_GPIO_Cfg_Type cfg; + uint8_t gpiopins[6]; + uint8_t i=0; + + cfg.gpioMode=GPIO_MODE_AF; + cfg.pullType=GPIO_PULL_UP; + cfg.drive=1; + cfg.smtCtrl=1; + cfg.gpioFun=GPIO_FUN_FLASH; + + if(extFlashPin==0){ + gpiopins[0]=BFLB_EXTFLASH_CLK0_GPIO; + gpiopins[1]=BFLB_EXTFLASH_CS0_GPIO; + gpiopins[2]=BFLB_EXTFLASH_DATA00_GPIO; + gpiopins[3]=BFLB_EXTFLASH_DATA10_GPIO; + gpiopins[4]=BFLB_EXTFLASH_DATA20_GPIO; + gpiopins[5]=BFLB_EXTFLASH_DATA30_GPIO; + }else{ + gpiopins[0]=BFLB_EXTFLASH_CLK1_GPIO; + gpiopins[1]=BFLB_EXTFLASH_CS1_GPIO; + gpiopins[2]=BFLB_EXTFLASH_DATA01_GPIO; + gpiopins[3]=BFLB_EXTFLASH_DATA11_GPIO; + gpiopins[4]=BFLB_EXTFLASH_DATA21_GPIO; + gpiopins[5]=BFLB_EXTFLASH_DATA31_GPIO; + } + + for(i=0;i0){ + /*01: deswap flash PIN + 10: use ext flash 1(GPIO17-22) + 11: use ext flash 0(GPIO0-2, 20-22) + */ + if(flashPinCfg==BFLB_FLASH_CFG_DESWAP){ + SF_Ctrl_Select_Pad(SF_CTRL_EMBEDDED_SEL); + /*DONOT Swap flash PIN*/ + GLB_Deswap_Flash_Pin(); + }else{ + SF_Ctrl_Select_Pad(flashPinCfg-1); + GLB_Select_External_Flash(); + SF_Cfg_Init_Ext_Flash_Gpio(flashPinCfg-BFLB_FLASH_CFG_EXT0_17_22); + } + } +} + +/****************************************************************************//** + * @brief Identify one flash + * + * @param callFromFlash: code run at flash or ram + * @param autoScan: Auto scan all GPIO pin + * @param flashPinCfg: Specify flash GPIO config, not auto scan + * @param restoreDefault: Wether restore default flash GPIO config + * @param pFlashCfg: Flash config pointer + * + * @return Flash ID + * +*******************************************************************************/ +__WEAK +uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify(uint8_t callFromFlash, + uint32_t autoScan,uint32_t flashPinCfg,uint8_t restoreDefault,SPI_Flash_Cfg_Type * pFlashCfg) +{ + uint32_t jdecId=0; + uint32_t i=0; + uint32_t offset; + BL_Err_Type stat; + uint8_t gpio17_fun=0; + + BL602_MemCpy_Fast(pFlashCfg,&flashCfg_Gd_Q80E_Q16E,sizeof(SPI_Flash_Cfg_Type)); + if(callFromFlash == 1){ + stat=XIP_SFlash_State_Save(pFlashCfg,&offset); + if(stat!=SUCCESS){ + SFlash_Set_IDbus_Cfg(pFlashCfg,SF_CTRL_QIO_MODE,1,0,32); + return 0; + } + } + + if(autoScan){ + flashPinCfg=0; + do{ + if(flashPinCfg>BFLB_FLASH_CFG_EXT1_0_2_20_22){ + jdecId=0; + break; + } + if(flashPinCfg>BFLB_FLASH_CFG_EXT0_17_22){ + /*flashPinCfg=2 has make gpio17 into jtag,but not success*/ + SF_Cfg_Restore_GPIO17_Fun(gpio17_fun); + } + /* select media gpio */ + if(flashPinCfg==BFLB_FLASH_CFG_EXT0_17_22){ + gpio17_fun=GLB_GPIO_Get_Fun(GLB_GPIO_PIN_17); + } + SF_Cfg_Init_Flash_Gpio(flashPinCfg,restoreDefault); + SFlash_Reset_Continue_Read(pFlashCfg); + SFlash_DisableBurstWrap(pFlashCfg); + jdecId=0; + SFlash_GetJedecId(pFlashCfg,(uint8_t *)&jdecId); + SFlash_DisableBurstWrap(pFlashCfg); + jdecId=jdecId&0xffffff; + flashPinCfg++; + }while((jdecId&0x00ffff)==0||(jdecId&0xffff00)==0||(jdecId&0x00ffff)==0xffff||(jdecId&0xffff00)==0xffff00); + }else{ + /* select media gpio */ + SF_Cfg_Init_Flash_Gpio(flashPinCfg,restoreDefault); + SFlash_Reset_Continue_Read(pFlashCfg); + SFlash_DisableBurstWrap(pFlashCfg); + SFlash_GetJedecId(pFlashCfg,(uint8_t *)&jdecId); + SFlash_DisableBurstWrap(pFlashCfg); + jdecId=jdecId&0xffffff; + } + + for(i=0;i
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_glb.h" +#include "bl602_sf_cfg.h" +#include "bl602_sf_cfg_ext.h" +#include "bl602_xip_sflash.h" +#include "bl602_romdriver.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CFG_EXT + * @{ + */ + +/** @defgroup SF_CFG_EXT_Private_Macros + * @{ + */ +#define BFLB_FLASH_CFG_MAGIC "FCFG" + +/*@} end of group SF_CFG_EXT_Private_Macros */ + +/** @defgroup SF_CFG_EXT_Private_Types + * @{ + */ +typedef struct { + uint32_t jedecID; + char *name; + const SPI_Flash_Cfg_Type *cfg; +}Flash_Info_t; + +/*@} end of group SF_CFG_EXT_Private_Types */ + +/** @defgroup SF_CFG_EXT_Private_Variables + * @{ + */ +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_FM_25Q08={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0xc8, + + .deBurstWrapCmd=0x77, + .deBurstWrapCmdDmyClk=0x3, + .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, + .deBurstWrapData=0xF0, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=1, + .qeBit=0x01, + .qeWriteRegLen=0x02, + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x35, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x01, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=16/8, + .cReadSupport=1, + .cReadMode=0x20, + + .burstWrapCmd=0x77, + .burstWrapCmdDmyClk=0x3, + .burstWrapDataMode=SF_CTRL_DATA_4_LINES, + .burstWrapData=0x40, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x32, + .qppAddrMode=SF_CTRL_ADDR_1_LINE, + + .ioMode=SF_CTRL_QIO_MODE, + .clkDelay=1, + .clkInvert=0x3f, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=0, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=300, + .timeE32k=1200, + .timeE64k=1200, + .timePagePgm=5, + .timeCe=20*1000, + .pdDelay=20, + .qeData=0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Md_40D={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0x51, + + .deBurstWrapCmd=0x77, + .deBurstWrapCmdDmyClk=0x3, + .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, + .deBurstWrapData=0xF0, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=1, + .qeBit=0x01, + .qeWriteRegLen=0x02, + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x35, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x01, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=16/8, + .cReadSupport=0, + .cReadMode=0xA0, + + .burstWrapCmd=0x77, + .burstWrapCmdDmyClk=0x3, + .burstWrapDataMode=SF_CTRL_DATA_4_LINES, + .burstWrapData=0x40, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x32, + .qppAddrMode=SF_CTRL_ADDR_1_LINE, + + .ioMode=SF_CTRL_DO_MODE, + .clkDelay=1, + .clkInvert=0x3f, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=0, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=300, + .timeE32k=1200, + .timeE64k=1200, + .timePagePgm=5, + .timeCe=20*1000, + .pdDelay=20, + .qeData=0, +}; + +static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_XM25QH16={ + .resetCreadCmd=0xff, + .resetCreadCmdSize=3, + .mid=0x20, + + .deBurstWrapCmd=0x77, + .deBurstWrapCmdDmyClk=0x3, + .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, + .deBurstWrapData=0xF0, + + /*reg*/ + .writeEnableCmd=0x06, + .wrEnableIndex=0x00, + .wrEnableBit=0x01, + .wrEnableReadRegLen=0x01, + + .qeIndex=1, + .qeBit=0x01, + .qeWriteRegLen=0x01, + .qeReadRegLen=0x1, + + .busyIndex=0, + .busyBit=0x00, + .busyReadRegLen=0x1, + .releasePowerDown=0xab, + + .readRegCmd[0]=0x05, + .readRegCmd[1]=0x35, + .writeRegCmd[0]=0x01, + .writeRegCmd[1]=0x31, + + .fastReadQioCmd=0xeb, + .frQioDmyClk=16/8, + .cReadSupport=1, + .cReadMode=0x20, + + .burstWrapCmd=0x77, + .burstWrapCmdDmyClk=0x3, + .burstWrapDataMode=SF_CTRL_DATA_4_LINES, + .burstWrapData=0x40, + /*erase*/ + .chipEraseCmd=0xc7, + .sectorEraseCmd=0x20, + .blk32EraseCmd=0x52, + .blk64EraseCmd=0xd8, + /*write*/ + .pageProgramCmd=0x02, + .qpageProgramCmd=0x32, + .qppAddrMode=SF_CTRL_ADDR_1_LINE, + + .ioMode=SF_CTRL_QIO_MODE, + .clkDelay=1, + .clkInvert=0x3f, + + .resetEnCmd=0x66, + .resetCmd=0x99, + .cRExit=0xff, + .wrEnableWriteRegLen=0x00, + + /*id*/ + .jedecIdCmd=0x9f, + .jedecIdCmdDmyClk=0, + .qpiJedecIdCmd=0x9f, + .qpiJedecIdCmdDmyClk=0x00, + .sectorSize=4, + .pageSize=256, + + /*read*/ + .fastReadCmd=0x0b, + .frDmyClk=8/8, + .qpiFastReadCmd =0x0b, + .qpiFrDmyClk=8/8, + .fastReadDoCmd=0x3b, + .frDoDmyClk=8/8, + .fastReadDioCmd=0xbb, + .frDioDmyClk=0, + .fastReadQoCmd=0x6b, + .frQoDmyClk=8/8, + + .qpiFastReadQioCmd=0xeb, + .qpiFrQioDmyClk=16/8, + .qpiPageProgramCmd=0x02, + .writeVregEnableCmd=0x50, + + /* qpi mode */ + .enterQpi=0x38, + .exitQpi=0xff, + + /*AC*/ + .timeEsector=400, + .timeE32k=1600, + .timeE64k=2000, + .timePagePgm=5, + .timeCe=20*1000, + .pdDelay=3, + .qeData=0, +}; + +static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[]={ + { + .jedecID=0x1440A1, + //.name="FM_25Q08", + .cfg=&flashCfg_FM_25Q08, + }, + { + .jedecID=0x134051, + //.name="GD_MD04D_04_33", + .cfg=&flashCfg_Gd_Md_40D, + }, + { + .jedecID=0x144020, + //.name="XM_25QH80_80_33", + .cfg=&flashCfg_XM25QH16, + }, + { + .jedecID=0x154020, + //.name="XM_25QH16_16_33", + .cfg=&flashCfg_XM25QH16, + }, + { + .jedecID=0x164020, + //.name="XM_25QH32_32_33", + .cfg=&flashCfg_XM25QH16, + }, + { + .jedecID=0x15605E, + //.name="ZB_25VQ16_16_33", + .cfg=&flashCfg_XM25QH16, + }, +}; + +/*@} end of group SF_CFG_EXT_Private_Variables */ + +/** @defgroup SF_CFG_EXT_Global_Variables + * @{ + */ + +/*@} end of group SF_CFG_EXT_Global_Variables */ + +/** @defgroup SF_CFG_EXT_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SF_CFG_EXT_Private_Fun_Declaration */ + +/** @defgroup SF_CFG_EXT_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief Get flash config according to flash ID + * + * @param flashID: Flash ID + * @param pFlashCfg: Flash config pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID,SPI_Flash_Cfg_Type * pFlashCfg) +{ + uint32_t i; + uint8_t buf[sizeof(SPI_Flash_Cfg_Type)+8]; + uint32_t crc,*pCrc; + + if(flashID==0){ + XIP_SFlash_Read_Via_Cache_Need_Lock(8+BL602_FLASH_XIP_BASE,buf,sizeof(SPI_Flash_Cfg_Type)+8); + if(BL602_MemCmp(buf,BFLB_FLASH_CFG_MAGIC,4)==0){ + crc=BFLB_Soft_CRC32((uint8_t *)buf+4,sizeof(SPI_Flash_Cfg_Type)); + pCrc=(uint32_t *)(buf+4+sizeof(SPI_Flash_Cfg_Type)); + if(*pCrc==crc){ + BL602_MemCpy_Fast(pFlashCfg,(uint8_t *)buf+4,sizeof(SPI_Flash_Cfg_Type)); + return SUCCESS ; + } + } + }else{ + if(SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg)){ + return SUCCESS; + } + for(i=0;i
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_sf_ctrl.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CTRL + * @{ + */ + +/** @defgroup SF_CTRL_Private_Macros + * @{ + */ + +/*@} end of group SF_CTRL_Private_Macros */ + +/** @defgroup SF_CTRL_Private_Types + * @{ + */ + +/*@} end of group SF_CTRL_Private_Types */ + +/** @defgroup SF_CTRL_Private_Variables + * @{ + */ +#define SF_CTRL_BUSY_STATE_TIMEOUT (5*160*1000) +#define SF_Ctrl_Get_AES_Region(addr,r) (addr+SF_CTRL_AES_REGION_OFFSET+(r)*0x100) + +/*@} end of group SF_CTRL_Private_Variables */ + +/** @defgroup SF_CTRL_Global_Variables + * @{ + */ + +/*@} end of group SF_CTRL_Global_Variables */ + +/** @defgroup SF_CTRL_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SF_CTRL_Private_Fun_Declaration */ + +/** @defgroup SF_CTRL_Private_Functions + * @{ + */ + +/*@} end of group SF_CTRL_Private_Functions */ + +/** @defgroup SF_CTRL_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief Enable serail flash controller + * + * @param cfg: serial flash controller config + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg) +{ + uint32_t tmpVal = 0; + uint32_t timeOut = 0; + + if(cfg==NULL){ + return; + } + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(cfg->owner)); + + timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; + while(SET==SF_Ctrl_GetBusyState()){ + timeOut--; + if(timeOut == 0){ + return; + } + } + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_0); + + if(cfg->clkDelay>0){ + tmpVal=BL_SET_REG_BIT(tmpVal,SF_CTRL_SF_IF_READ_DLY_EN); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_READ_DLY_N,cfg->clkDelay-1); + }else{ + tmpVal=BL_CLR_REG_BIT(tmpVal,SF_CTRL_SF_IF_READ_DLY_EN); + } + + /* Serail out inverted, so sf ctrl send on negative edge */ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_CLK_OUT_INV_SEL,cfg->clkInvert); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_CLK_SF_RX_INV_SEL,cfg->rxClkInvert); + + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_0,tmpVal); + + /* Set do di and oe delay */ + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_SF_IF_IO_DLY_1); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IO_0_DO_DLY_SEL,cfg->doDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IO_0_DI_DLY_SEL,cfg->diDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IO_0_OE_DLY_SEL,cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF_IF_IO_DLY_1,tmpVal); + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_SF_IF_IO_DLY_2); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IO_1_DO_DLY_SEL,cfg->doDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IO_1_DI_DLY_SEL,cfg->diDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IO_1_OE_DLY_SEL,cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF_IF_IO_DLY_2,tmpVal); + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_SF_IF_IO_DLY_3); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IO_2_DO_DLY_SEL,cfg->doDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IO_2_DI_DLY_SEL,cfg->diDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IO_2_OE_DLY_SEL,cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF_IF_IO_DLY_3,tmpVal); + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_SF_IF_IO_DLY_4); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IO_3_DO_DLY_SEL,cfg->doDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IO_3_DI_DLY_SEL,cfg->diDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IO_3_OE_DLY_SEL,cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF_IF_IO_DLY_4,tmpVal); + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_SF2_IF_IO_DLY_1); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF2_IO_0_DO_DLY_SEL,cfg->doDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF2_IO_0_DI_DLY_SEL,cfg->diDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF2_IO_0_OE_DLY_SEL,cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF2_IF_IO_DLY_1,tmpVal); + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_SF2_IF_IO_DLY_2); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF2_IO_1_DO_DLY_SEL,cfg->doDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF2_IO_1_DI_DLY_SEL,cfg->diDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF2_IO_1_OE_DLY_SEL,cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF2_IF_IO_DLY_2,tmpVal); + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_SF2_IF_IO_DLY_3); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF2_IO_2_DO_DLY_SEL,cfg->doDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF2_IO_2_DI_DLY_SEL,cfg->diDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF2_IO_2_OE_DLY_SEL,cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF2_IF_IO_DLY_3,tmpVal); + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_SF2_IF_IO_DLY_4); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF2_IO_3_DO_DLY_SEL,cfg->doDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF2_IO_3_DI_DLY_SEL,cfg->diDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF2_IO_3_OE_DLY_SEL,cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF2_IF_IO_DLY_4,tmpVal); + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_SF3_IF_IO_DLY_1); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF3_IO_0_DO_DLY_SEL,cfg->doDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF3_IO_0_DI_DLY_SEL,cfg->diDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF3_IO_0_OE_DLY_SEL,cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF3_IF_IO_DLY_1,tmpVal); + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_SF3_IF_IO_DLY_2); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF3_IO_1_DO_DLY_SEL,cfg->doDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF3_IO_1_DI_DLY_SEL,cfg->diDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF3_IO_1_OE_DLY_SEL,cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF3_IF_IO_DLY_2,tmpVal); + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_SF3_IF_IO_DLY_3); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF3_IO_2_DO_DLY_SEL,cfg->doDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF3_IO_2_DI_DLY_SEL,cfg->diDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF3_IO_2_OE_DLY_SEL,cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF3_IF_IO_DLY_3,tmpVal); + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_SF3_IF_IO_DLY_4); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF3_IO_3_DO_DLY_SEL,cfg->doDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF3_IO_3_DI_DLY_SEL,cfg->diDelay); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF3_IO_3_OE_DLY_SEL,cfg->oeDelay); + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF3_IF_IO_DLY_4,tmpVal); + + /* Enable AHB access sram buffer and enable sf interface */ + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_1); + tmpVal=BL_SET_REG_BIT(tmpVal,SF_CTRL_SF_AHB2SRAM_EN); + tmpVal=BL_SET_REG_BIT(tmpVal,SF_CTRL_SF_IF_EN); + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_1,tmpVal); + + SF_Ctrl_Set_Owner(cfg->owner); +} + +/****************************************************************************//** + * @brief Flash pad select + * + * @param sel: pad type + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Sel sel) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_PAD_SEL(sel)); + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_2); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_PAD_SEL,sel); + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_2,tmpVal); +} + +/****************************************************************************//** + * @brief Set flash controller owner:I/D AHB or system AHB + * + * @param owner: owner type + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner) +{ + uint32_t tmpVal = 0; + uint32_t timeOut = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(owner)); + + timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; + while(SET==SF_Ctrl_GetBusyState()){ + timeOut--; + if(timeOut == 0){ + return; + } + } + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_1); + + /* Set owner */ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_FN_SEL,owner); + + /* Set iahb to flash interface */ + if(owner==SF_CTRL_OWNER_IAHB){ + tmpVal=BL_SET_REG_BIT(tmpVal,SF_CTRL_SF_AHB2SIF_EN); + }else{ + tmpVal=BL_CLR_REG_BIT(tmpVal,SF_CTRL_SF_AHB2SIF_EN); + } + + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_1,tmpVal); +} + +/****************************************************************************//** + * @brief Disable flash controller + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Disable(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_1); + + tmpVal=BL_CLR_REG_BIT(tmpVal,SF_CTRL_SF_IF_EN); + + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_1,tmpVal); +} + +/****************************************************************************//** + * @brief Enable flash controller AES with big indian + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_BE(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_0); + + tmpVal=BL_SET_REG_BIT(tmpVal,SF_CTRL_SF_AES_KEY_ENDIAN); + tmpVal=BL_SET_REG_BIT(tmpVal,SF_CTRL_SF_AES_IV_ENDIAN); + tmpVal=BL_SET_REG_BIT(tmpVal,SF_CTRL_SF_AES_DOUT_ENDIAN); + + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_0,tmpVal); +} + +/****************************************************************************//** + * @brief Enable flash controller AES with little indian + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_LE(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_0); + + tmpVal=BL_CLR_REG_BIT(tmpVal,SF_CTRL_SF_AES_KEY_ENDIAN); + tmpVal=BL_CLR_REG_BIT(tmpVal,SF_CTRL_SF_AES_IV_ENDIAN); + tmpVal=BL_CLR_REG_BIT(tmpVal,SF_CTRL_SF_AES_DOUT_ENDIAN); + + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_0,tmpVal); +} + +/****************************************************************************//** + * @brief Serial flash controller set AES region + * + * @param region: region number + * @param enable: enable or not + * @param hwKey: hardware key or software key + * @param startAddr: region start address + * @param endAddr: region end address + * @param locked: lock this region or not + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Region(uint8_t region,uint8_t enable, + uint8_t hwKey,uint32_t startAddr,uint32_t endAddr,uint8_t locked) +{ + /* Do flash key eco*/ + uint32_t regionRegBase=SF_Ctrl_Get_AES_Region(SF_CTRL_BASE,!region); + uint32_t tmpVal; + + tmpVal=BL_RD_REG(regionRegBase,SF_CTRL_SF_AES_CFG); + + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_AES_REGION_HW_KEY_EN,hwKey); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_AES_REGION_START,startAddr/1024); + /* sf_aes_end =1 means 1,11,1111,1111 */ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_AES_REGION_END,endAddr/1024); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_AES_REGION_EN,enable); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_AES_REGION_LOCK,locked); + + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_CFG,tmpVal); +} + +/****************************************************************************//** + * @brief Serial flash controller set AES key + * + * @param region: region number + * @param key: key data pointer + * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key(uint8_t region,uint8_t *key, SF_Ctrl_AES_Key_Type keyType) +{ + /* Do flash key eco*/ + uint32_t regionRegBase=SF_Ctrl_Get_AES_Region(SF_CTRL_BASE,!region); + uint32_t tmpVal,i=0; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_SF_AES); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_AES_MODE,keyType); + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF_AES,tmpVal); + + if(NULL!=key){ + if(keyType==SF_CTRL_AES_128BITS){ + i=4; + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + */ + }else if(keyType==SF_CTRL_AES_256BITS){ + i=8; + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + */ + }else if(keyType==SF_CTRL_AES_192BITS){ + i=6; + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + */ + } + tmpVal=SF_CTRL_SF_AES_KEY_7_OFFSET; + while(i--){ + BL_WR_WORD(regionRegBase+tmpVal,__REV(BL_RDWD_FRM_BYTEP(key))); + key+=4; + tmpVal-=4; + } + } +} + +/****************************************************************************//** + * @brief Serial flash controller set AES key with big endian + * + * @param region: region number + * @param key: key data pointer + * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key_BE(uint8_t region,uint8_t *key, SF_Ctrl_AES_Key_Type keyType) +{ + /* Do flash key eco*/ + uint32_t regionRegBase=SF_Ctrl_Get_AES_Region(SF_CTRL_BASE,!region); + uint32_t tmpVal,i=0; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_SF_AES); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_AES_MODE,keyType); + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF_AES,tmpVal); + + if(NULL!=key){ + if(keyType==SF_CTRL_AES_128BITS){ + i=4; + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); + key+=4; + */ + } else if(keyType==SF_CTRL_AES_256BITS){ + i=8; + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,BL_RDWD_FRM_BYTEP(key)); + key+=4; + */ + }else if(keyType==SF_CTRL_AES_192BITS){ + i=6; + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key)); + key+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key)); + */ + } + tmpVal=SF_CTRL_SF_AES_KEY_0_OFFSET; + while(i--){ + BL_WR_WORD(regionRegBase+tmpVal,BL_RDWD_FRM_BYTEP(key)); + key+=4; + tmpVal+=4; + } + } +} + +/****************************************************************************//** + * @brief Serial flash controller set AES iv + * + * @param region: region number + * @param iv: iv data pointer + * @param addrOffset: flash address offset + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV(uint8_t region,uint8_t *iv,uint32_t addrOffset) +{ + /* Do flash key eco*/ + uint32_t regionRegBase=SF_Ctrl_Get_AES_Region(SF_CTRL_BASE,!region); + uint32_t tmpVal,i=3; + + if(iv!=NULL){ + tmpVal=SF_CTRL_SF_AES_IV_W3_OFFSET; + while(i--){ + BL_WR_WORD(regionRegBase+tmpVal,__REV(BL_RDWD_FRM_BYTEP(iv))); + iv+=4; + tmpVal-=4; + } + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W3,__REV(BL_RDWD_FRM_BYTEP(iv))); + iv+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,__REV(BL_RDWD_FRM_BYTEP(iv))); + iv+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,__REV(BL_RDWD_FRM_BYTEP(iv))); + iv+=4; + */ + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W0,addrOffset); + iv+=4; + } +} + +/****************************************************************************//** + * @brief Serial flash controller set AES iv with big endian + * + * @param region: region number + * @param iv: iv data pointer + * @param addrOffset: flash address offset + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV_BE(uint8_t region,uint8_t *iv,uint32_t addrOffset) +{ + /* Do flash key eco*/ + uint32_t regionRegBase=SF_Ctrl_Get_AES_Region(SF_CTRL_BASE,!region); + uint32_t tmpVal,i=3; + + if(iv!=NULL){ + tmpVal=SF_CTRL_SF_AES_IV_W0_OFFSET; + while(i--){ + BL_WR_WORD(regionRegBase+tmpVal,BL_RDWD_FRM_BYTEP(iv)); + iv+=4; + tmpVal+=4; + } + /* + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W0,BL_RDWD_FRM_BYTEP(iv)); + iv+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,BL_RDWD_FRM_BYTEP(iv)); + iv+=4; + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,BL_RDWD_FRM_BYTEP(iv)); + iv+=4; + */ + BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W3,__REV(addrOffset)); + iv+=4; + } +} + +/****************************************************************************//** + * @brief Enable serial flash controller AES + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Enable(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_SF_AES); + tmpVal=BL_SET_REG_BIT(tmpVal,SF_CTRL_SF_AES_EN); + + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF_AES,tmpVal); +} + +/****************************************************************************//** + * @brief Disable serial flash controller AES + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_AES_Disable(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_SF_AES); + tmpVal=BL_CLR_REG_BIT(tmpVal,SF_CTRL_SF_AES_EN); + + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF_AES,tmpVal); +} + +/****************************************************************************//** + * @brief Set flash image offset + * + * @param addrOffset: Address offset value + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset) +{ + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF_ID0_OFFSET,addrOffset); +} + +/****************************************************************************//** + * @brief Get flash image offset + * + * @param None + * + * @return :Address offset value + * +*******************************************************************************/ +__WEAK +uint32_t ATTR_TCM_SECTION SF_Ctrl_Get_Flash_Image_Offset(void) +{ + return BL_RD_REG(SF_CTRL_BASE,SF_CTRL_SF_ID0_OFFSET); +} + +/****************************************************************************//** + * @brief SF controller send one command + * + * @param sahbType: Serial flash controller clock sahb sram select + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType) +{ + uint32_t tmpVal = 0; + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_0); + if(sahbType==SF_CTRL_SAHB_CLOCK){ + tmpVal=BL_CLR_REG_BIT(tmpVal,SF_CTRL_SF_CLK_SAHB_SRAM_SEL); + }else if(sahbType==SF_CTRL_FLASH_CLOCK){ + tmpVal=BL_SET_REG_BIT(tmpVal,SF_CTRL_SF_CLK_SAHB_SRAM_SEL); + } + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_0,tmpVal); +} + +/****************************************************************************//** + * @brief SF controller send one command + * + * @param cfg: Serial flash controller command configuration pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg) +{ + uint32_t tmpVal = 0; + uint32_t timeOut = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); + CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); + CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); + CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); + + timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; + while(SET==SF_Ctrl_GetBusyState()){ + timeOut--; + if(timeOut == 0){ + return; + } + } + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_1); + + if(BL_GET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_FN_SEL)!=SF_CTRL_OWNER_SAHB){ + return; + } + + /* Clear trigger */ + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_SF_IF_SAHB_0); + tmpVal=BL_CLR_REG_BIT(tmpVal,SF_CTRL_SF_IF_0_TRIG); + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF_IF_SAHB_0,tmpVal); + + /* Copy command buffer */ + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF_IF_SAHB_1,cfg->cmdBuf[0]); + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF_IF_SAHB_2,cfg->cmdBuf[1]); + + /* Configure SPI and IO mode*/ + if(SF_CTRL_CMD_1_LINE==cfg->cmdMode){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_0_QPI_MODE_EN,SF_CTRL_SPI_MODE); + }else{ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_0_QPI_MODE_EN,SF_CTRL_QPI_MODE); + } + + if(SF_CTRL_ADDR_1_LINE==cfg->addrMode){ + if(SF_CTRL_DATA_1_LINE==cfg->dataMode){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_0_SPI_MODE,SF_CTRL_NIO_MODE); + }else if(SF_CTRL_DATA_2_LINES==cfg->dataMode){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_0_SPI_MODE,SF_CTRL_DO_MODE); + }else if(SF_CTRL_DATA_4_LINES==cfg->dataMode){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_0_SPI_MODE,SF_CTRL_QO_MODE); + } + }else if(SF_CTRL_ADDR_2_LINES==cfg->addrMode){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_0_SPI_MODE,SF_CTRL_DIO_MODE); + }else if(SF_CTRL_ADDR_4_LINES==cfg->addrMode){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_0_SPI_MODE,SF_CTRL_QIO_MODE); + } + + /* Configure cmd */ + tmpVal=BL_SET_REG_BIT(tmpVal,SF_CTRL_SF_IF_0_CMD_EN); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_0_CMD_BYTE,0); + + /* Configure address */ + if(cfg->addrSize != 0){ + tmpVal=BL_SET_REG_BIT(tmpVal,SF_CTRL_SF_IF_0_ADR_EN); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_0_ADR_BYTE,cfg->addrSize-1); + }else{ + tmpVal=BL_CLR_REG_BIT(tmpVal,SF_CTRL_SF_IF_0_ADR_EN); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_0_ADR_BYTE,0); + } + + /* Configure dummy */ + if(cfg->dummyClks !=0){ + tmpVal=BL_SET_REG_BIT(tmpVal,SF_CTRL_SF_IF_0_DMY_EN); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_0_DMY_BYTE,cfg->dummyClks-1); + }else{ + tmpVal=BL_CLR_REG_BIT(tmpVal,SF_CTRL_SF_IF_0_DMY_EN); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_0_DMY_BYTE,0); + } + + /* Configure data */ + if(cfg->nbData !=0){ + tmpVal=BL_SET_REG_BIT(tmpVal,SF_CTRL_SF_IF_0_DAT_EN); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_0_DAT_BYTE,cfg->nbData-1); + }else{ + tmpVal=BL_CLR_REG_BIT(tmpVal,SF_CTRL_SF_IF_0_DAT_EN); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_0_DAT_BYTE,0); + } + + /* Set read write flag */ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_0_DAT_RW,cfg->rwFlag); + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF_IF_SAHB_0,tmpVal); + + //switch sf_clk_sahb_sram_sel = 1 + SF_Ctrl_Select_Clock(SF_CTRL_FLASH_CLOCK); + /* Trigger */ + tmpVal=BL_SET_REG_BIT(tmpVal,SF_CTRL_SF_IF_0_TRIG); + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF_IF_SAHB_0,tmpVal); + + timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; + while(SET==SF_Ctrl_GetBusyState()){ + timeOut--; + if(timeOut == 0){ + SF_Ctrl_Select_Clock(SF_CTRL_SAHB_CLOCK); + return; + } + } + //switch sf_clk_sahb_sram_sel = 0 + SF_Ctrl_Select_Clock(SF_CTRL_SAHB_CLOCK); +} + +/****************************************************************************//** + * @brief Config SF controller for I/D cache read + * + * @param cfg: Serial flash controller command configuration pointer + * @param cmdValid: command valid or not, for continous read, cache may need no command + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg,uint8_t cmdValid) +{ + uint32_t tmpVal = 0; + uint32_t timeOut = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); + CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); + CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); + CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); + + timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; + while(SET==SF_Ctrl_GetBusyState()){ + timeOut--; + if(timeOut == 0){ + return; + } + } + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_1); + + if(BL_GET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_FN_SEL)!=SF_CTRL_OWNER_IAHB){ + return; + } + + /* Copy command buffer */ + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF_IF_IAHB_1,cfg->cmdBuf[0]); + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF_IF_IAHB_2,cfg->cmdBuf[1]); + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_SF_IF_IAHB_0); + + /* Configure SPI and IO mode*/ + if(SF_CTRL_CMD_1_LINE==cfg->cmdMode){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_QPI_MODE_EN,SF_CTRL_SPI_MODE); + }else{ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_QPI_MODE_EN,SF_CTRL_QPI_MODE); + } + + if(SF_CTRL_ADDR_1_LINE==cfg->addrMode){ + if(SF_CTRL_DATA_1_LINE==cfg->dataMode){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_SPI_MODE,SF_CTRL_NIO_MODE); + }else if(SF_CTRL_DATA_2_LINES==cfg->dataMode){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_SPI_MODE,SF_CTRL_DO_MODE); + }else if(SF_CTRL_DATA_4_LINES==cfg->dataMode){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_SPI_MODE,SF_CTRL_QO_MODE); + } + }else if(SF_CTRL_ADDR_2_LINES==cfg->addrMode){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_SPI_MODE,SF_CTRL_DIO_MODE); + }else if(SF_CTRL_ADDR_4_LINES==cfg->addrMode){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_SPI_MODE,SF_CTRL_QIO_MODE); + } + + if(cmdValid){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_CMD_EN,1); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_CMD_BYTE,0); + }else{ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_CMD_EN,0); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_CMD_BYTE,0); + } + + /* Configure address */ + if(cfg->addrSize != 0){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_ADR_EN,1); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_ADR_BYTE,cfg->addrSize-1); + }else{ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_ADR_EN,0); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_ADR_BYTE,0); + } + + /* configure dummy */ + if(cfg->dummyClks !=0){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_DMY_EN,1); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_DMY_BYTE,cfg->dummyClks-1); + }else{ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_DMY_EN,0); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_DMY_BYTE,0); + } + + /* Configure data */ + if(cfg->nbData !=0){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_DAT_EN,1); + } else { + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_DAT_EN,0); + } + + /* Set read write flag */ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_DAT_RW,cfg->rwFlag); + + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF_IF_IAHB_0,tmpVal); +} + +/****************************************************************************//** + * @brief Config SF controller for I/D cache write + * + * @param cfg: Serial flash controller command configuration pointer + * @param cmdValid: command valid or not, cache may need no command + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Icache2_Set(SF_Ctrl_Cmd_Cfg_Type *cfg,uint8_t cmdValid) +{ + uint32_t tmpVal = 0; + uint32_t timeOut = 0; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); + CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); + CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); + CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); + + timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; + while(SET==SF_Ctrl_GetBusyState()){ + timeOut--; + if(timeOut == 0){ + return; + } + } + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_1); + + if(BL_GET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_FN_SEL)!=SF_CTRL_OWNER_IAHB){ + return; + } + + /* Copy command buffer */ + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF_IF_IAHB_4,cfg->cmdBuf[0]); + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF_IF_IAHB_5,cfg->cmdBuf[1]); + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_SF_IF_IAHB_3); + + /* Configure SPI and IO mode*/ + if(SF_CTRL_CMD_1_LINE==cfg->cmdMode){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_2_QPI_MODE_EN,SF_CTRL_SPI_MODE); + }else{ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_2_QPI_MODE_EN,SF_CTRL_QPI_MODE); + } + + if(SF_CTRL_ADDR_1_LINE==cfg->addrMode){ + if(SF_CTRL_DATA_1_LINE==cfg->dataMode){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_2_SPI_MODE,SF_CTRL_NIO_MODE); + }else if(SF_CTRL_DATA_2_LINES==cfg->dataMode){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_2_SPI_MODE,SF_CTRL_DO_MODE); + }else if(SF_CTRL_DATA_4_LINES==cfg->dataMode){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_2_SPI_MODE,SF_CTRL_QO_MODE); + } + }else if(SF_CTRL_ADDR_2_LINES==cfg->addrMode){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_2_SPI_MODE,SF_CTRL_DIO_MODE); + }else if(SF_CTRL_ADDR_4_LINES==cfg->addrMode){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_2_SPI_MODE,SF_CTRL_QIO_MODE); + } + + if(cmdValid){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_2_CMD_EN,1); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_2_CMD_BYTE,0); + }else{ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_2_CMD_EN,0); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_2_CMD_BYTE,0); + } + + /* Configure address */ + if(cfg->addrSize != 0){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_2_ADR_EN,1); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_2_ADR_BYTE,cfg->addrSize-1); + }else{ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_2_ADR_EN,0); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_2_ADR_BYTE,0); + } + + /* configure dummy */ + if(cfg->dummyClks !=0){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_2_DMY_EN,1); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_2_DMY_BYTE,cfg->dummyClks-1); + }else{ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_2_DMY_EN,0); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_2_DMY_BYTE,0); + } + + /* Configure data */ + if(cfg->nbData !=0){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_2_DAT_EN,1); + } else { + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_2_DAT_EN,0); + } + + /* Set read write flag */ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_2_DAT_RW,cfg->rwFlag); + + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_SF_IF_IAHB_3,tmpVal); +} + +/****************************************************************************//** + * @brief Get SF Ctrl busy state + * + * @param None + * + * @return SET for SF ctrl busy or RESET for SF ctrl not busy + * +*******************************************************************************/ +__WEAK +BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_GetBusyState(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_SF_IF_SAHB_0); + + if( BL_IS_REG_BIT_SET(tmpVal,SF_CTRL_SF_IF_BUSY)){ + return SET; + }else{ + return RESET; + } +} + +/****************************************************************************//** + * @brief Check is serial flash controller AES enable + * + * @param None + * + * @return Wether AES is enable + * +*******************************************************************************/ +__WEAK +uint8_t ATTR_TCM_SECTION SF_Ctrl_Is_AES_Enable(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_SF_AES); + return BL_IS_REG_BIT_SET(tmpVal,SF_CTRL_SF_AES_EN); +} + +/****************************************************************************//** + * @brief Get flash controller clock delay value + * + * @param None + * + * @return Clock delay value + * +*******************************************************************************/ +__WEAK +uint8_t ATTR_TCM_SECTION SF_Ctrl_Get_Clock_Delay(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_0); + + if(BL_GET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_READ_DLY_EN)==0){ + return 0; + }else{ + return BL_GET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_READ_DLY_N) +1; + } +} + +/****************************************************************************//** + * @brief Set flash controller clock delay value + * + * @param delay: Clock delay value + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SF_Ctrl_Set_Clock_Delay(uint8_t delay) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(SF_CTRL_BASE,SF_CTRL_0); + + if(delay>0){ + tmpVal=BL_SET_REG_BIT(tmpVal,SF_CTRL_SF_IF_READ_DLY_EN); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_READ_DLY_N,delay-1); + }else{ + tmpVal=BL_CLR_REG_BIT(tmpVal,SF_CTRL_SF_IF_READ_DLY_EN); + } + + BL_WR_REG(SF_CTRL_BASE,SF_CTRL_0,tmpVal); +} +#endif + +/****************************************************************************//** + * @brief SF Controller interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void SF_Ctrl_IRQHandler(void) +{ + /* TODO: Not implemented */ +} +#endif + +/*@} end of group SF_CTRL_Public_Functions */ + +/*@} end of group SF_CTRL */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/bl602_driver/std_drv/src/bl602_sflash.c b/drivers/bl602_driver/std_drv/src/bl602_sflash.c new file mode 100644 index 00000000..201279ad --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_sflash.c @@ -0,0 +1,1488 @@ +/** + ****************************************************************************** + * @file bl602_sflash.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "string.h" +#include "bl602_sflash.h" +#include "bl602_sf_ctrl.h" +#include "bl602_l1c.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SFLASH + * @{ + */ + +/** @defgroup SFLASH_Private_Macros + * @{ + */ + +/*@} end of group SFLASH_Private_Macros */ + +/** @defgroup SFLASH_Private_Types + * @{ + */ + +/*@} end of group SFLASH_Private_Types */ + +/** @defgroup SFLASH_Private_Variables + * @{ + */ +#define SFCTRL_BUSY_STATE_TIMEOUT (5*160*1000) + +/*@} end of group SFLASH_Private_Variables */ + +/** @defgroup SFLASH_Global_Variables + * @{ + */ + +/*@} end of group SFLASH_Global_Variables */ + +/** @defgroup SFLASH_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SFLASH_Private_Fun_Declaration */ + +/** @defgroup SFLASH_Private_Functions + * @{ + */ + +/*@} end of group SFLASH_Private_Functions */ + +/** @defgroup SFLASH_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief Init serial flash control interface + * + * @param pSfCtrlCfg: Serial flash controller configuration pointer + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg) +{ + SF_Ctrl_Enable(pSfCtrlCfg); +} + +/****************************************************************************//** + * @brief Set serial flash control interface SPI or QPI mode + * + * @param mode: Serial flash interface mode + * + * @return BFLB_RET:SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode) +{ + BL_Err_Type stat=SUCCESS; + + /* Check the parameters */ + CHECK_PARAM(IS_SF_CTRL_MODE_TYPE(mode)); + + return stat; +} + +/****************************************************************************//** + * @brief Read flash register + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param regIndex: register index + * @param regValue: register value pointer to store data + * @param regLen: register value length + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg,uint8_t regIndex,uint8_t *regValue,uint8_t regLen) +{ + uint8_t * const flashCtrlBuf=(uint8_t *)SF_CTRL_BUF_BASE; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint32_t cnt=0; + + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0]=(flashCfg->readRegCmd[regIndex])<<24; + flashCmd.rwFlag=SF_CTRL_READ; + flashCmd.nbData=regLen; + + SF_Ctrl_SendCmd(&flashCmd); + + while(SET==SF_Ctrl_GetBusyState()){ + BL602_Delay_US(1); + cnt++; + if(cnt>1000){ + return ERROR; + } + } + + BL602_MemCpy(regValue,flashCtrlBuf,regLen); + return SUCCESS; +} + +/****************************************************************************//** + * @brief Write flash register + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param regIndex: register index + * @param regValue: register value pointer storing data + * @param regLen: register value length + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg,uint8_t regIndex,uint8_t *regValue,uint8_t regLen) +{ + uint8_t * const flashCtrlBuf=(uint8_t *)SF_CTRL_BUF_BASE; + uint32_t cnt=0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + BL602_MemCpy(flashCtrlBuf,regValue,regLen); + + flashCmd.cmdBuf[0]=(flashCfg->writeRegCmd[regIndex])<<24; + flashCmd.rwFlag=SF_CTRL_WRITE; + flashCmd.nbData=regLen; + + SF_Ctrl_SendCmd(&flashCmd); + + /* take 40ms for tw(write status register) as default */ + while(SET==SFlash_Busy(flashCfg)){ + BL602_Delay_US(100); + cnt++; + if(cnt>400){ + return ERROR; + } + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Check flash busy status + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return SET for busy or RESET for not busy + * +*******************************************************************************/ +__WEAK +BL_Sts_Type ATTR_TCM_SECTION SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg) +{ + uint32_t stat=0; + SFlash_Read_Reg(flashCfg,flashCfg->busyIndex,(uint8_t *)&stat,flashCfg->busyReadRegLen); + if((stat&(1<busyBit))==0){ + return RESET; + } + + return SET; +} + +/****************************************************************************//** + * @brief Enable flash write function + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) +{ + uint32_t stat=0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + + /* Write enable*/ + flashCmd.cmdBuf[0]=(flashCfg->writeEnableCmd)<<24; + /* rwFlag don't care */ + flashCmd.rwFlag=SF_CTRL_READ; + SF_Ctrl_SendCmd(&flashCmd); + + SFlash_Read_Reg(flashCfg,flashCfg->wrEnableIndex,(uint8_t *)&stat,flashCfg->wrEnableReadRegLen); + + if((stat&(1<wrEnableBit))!=0){ + return SUCCESS; + } + + return ERROR; +} + +/****************************************************************************//** + * @brief Enable flash flash controller QSPI interface + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg) +{ + uint32_t stat=0,ret; + + if(flashCfg->qeReadRegLen==0){ + ret=SFlash_Write_Enable(flashCfg); + if(SUCCESS!=ret){ + return ERROR; + } + SFlash_Write_Reg(flashCfg,flashCfg->qeIndex,(uint8_t *)&stat,flashCfg->qeWriteRegLen); + return SUCCESS; + } + + SFlash_Read_Reg(flashCfg,flashCfg->qeIndex,(uint8_t *)&stat,flashCfg->qeReadRegLen); + + if(flashCfg->qeData==0){ + if((stat&(1<qeBit))!=0){ + return SUCCESS; + } + }else{ + if(((stat>>(flashCfg->qeBit&0x08))&0xff)==flashCfg->qeData){ + return SUCCESS; + } + } + + if(flashCfg->qeWriteRegLen!=1){ + /* This is read r0,read r1 write r0,r1 case*/ + SFlash_Read_Reg(flashCfg,0,(uint8_t *)&stat,1); + SFlash_Read_Reg(flashCfg,1,((uint8_t *)&stat)+1,1); + if(flashCfg->qeData==0){ + stat|=(1<<(flashCfg->qeBit+8*flashCfg->qeIndex)); + }else{ + stat=stat&(~(0xff<<(8*flashCfg->qeIndex))); + stat|=(flashCfg->qeData<<(8*flashCfg->qeIndex)); + } + }else{ + if(flashCfg->qeData==0){ + stat|=(1<<(flashCfg->qeBit%8)); + }else{ + stat=flashCfg->qeData; + } + } + + ret=SFlash_Write_Enable(flashCfg); + if(SUCCESS!=ret){ + return ERROR; + } + SFlash_Write_Reg(flashCfg,flashCfg->qeIndex,(uint8_t *)&stat,flashCfg->qeWriteRegLen); + SFlash_Read_Reg(flashCfg,flashCfg->qeIndex,(uint8_t *)&stat,flashCfg->qeReadRegLen); + + if(flashCfg->qeData==0){ + if((stat&(1<qeBit))!=0){ + return SUCCESS; + } + }else{ + if(((stat>>(flashCfg->qeBit&0x08))&0xff)==flashCfg->qeData){ + return SUCCESS; + } + } + + return ERROR; +} + +/****************************************************************************//** + * @brief Enable flash volatile register write enable + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) +{ + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0]=(flashCfg->writeVregEnableCmd)<<24; + flashCmd.rwFlag=SF_CTRL_WRITE; + + SF_Ctrl_SendCmd(&flashCmd); +} + +/****************************************************************************//** + * @brief Erase flash whole chip + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg) +{ + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint32_t cnt=0; + BL_Err_Type stat=SFlash_Write_Enable(flashCfg); + + + if(stat!=SUCCESS){ + return stat; + } + + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + + + flashCmd.cmdBuf[0]=(flashCfg->chipEraseCmd)<<24; + /* rwFlag don't care */ + flashCmd.rwFlag=SF_CTRL_READ; + + SF_Ctrl_SendCmd(&flashCmd); + + while(SET==SFlash_Busy(flashCfg)){ + BL602_Delay_US(500); + cnt++; + if(cnt>flashCfg->timeCe*3){ + return ERROR; + } + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Erase flash one sector + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param secNum: flash sector number + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg,uint32_t secNum) +{ + uint32_t cnt=0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + BL_Err_Type stat=SFlash_Write_Enable(flashCfg); + if(stat!=SUCCESS){ + return stat; + } + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0]=(flashCfg->sectorEraseCmd<<24)|(flashCfg->sectorSize*1024*secNum); + /* rwFlag don't care */ + flashCmd.rwFlag=SF_CTRL_READ; + flashCmd.addrSize=3; + + SF_Ctrl_SendCmd(&flashCmd); + + while(SET==SFlash_Busy(flashCfg)){ + BL602_Delay_US(500); + cnt++; + if(cnt>flashCfg->timeEsector*3){ + return ERROR; + } + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Erase flash one 32K block + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param blkNum: flash 32K block number + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg,uint32_t blkNum) +{ + uint32_t cnt=0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + BL_Err_Type stat=SFlash_Write_Enable(flashCfg); + if(stat!=SUCCESS){ + return stat; + } + + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0]=(flashCfg->blk32EraseCmd<<24)|(BFLB_SPIFLASH_BLK32K_SIZE*blkNum); + /* rwFlag don't care */ + flashCmd.rwFlag=SF_CTRL_READ; + flashCmd.addrSize=3; + + SF_Ctrl_SendCmd(&flashCmd); + + while(SET==SFlash_Busy(flashCfg)){ + BL602_Delay_US(500); + cnt++; + if(cnt>flashCfg->timeE32k*3){ + return ERROR; + } + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Erase flash one 64K block + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param blkNum: flash 64K block number + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg,uint32_t blkNum) +{ + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint32_t cnt=0; + BL_Err_Type stat=SFlash_Write_Enable(flashCfg); + + if(stat!=SUCCESS){ + return stat; + } + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0]=(flashCfg->blk64EraseCmd<<24)|(BFLB_SPIFLASH_BLK64K_SIZE*blkNum); + /* rwFlag don't care */ + flashCmd.rwFlag=SF_CTRL_READ; + flashCmd.addrSize=3; + + SF_Ctrl_SendCmd(&flashCmd); + + while(SET==SFlash_Busy(flashCfg)){ + BL602_Delay_US(500); + cnt++; + if(cnt>flashCfg->timeE64k*3){ + return ERROR; + } + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Erase flash one region + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param startaddr: start address to erase + * @param endaddr: end address(include this address) to erase + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg,uint32_t startaddr,uint32_t endaddr) +{ + uint32_t len=0; + uint32_t eraseLen=0; + BL_Err_Type ret=SUCCESS; + + while(startaddr<=endaddr){ + len=endaddr-startaddr+1; + if(flashCfg->blk64EraseCmd!=BFLB_SPIFLASH_CMD_INVALID && + (startaddr&(BFLB_SPIFLASH_BLK64K_SIZE-1))==0 && + len>(BFLB_SPIFLASH_BLK64K_SIZE-flashCfg->sectorSize*1024)){ + /* 64K margin address,and length > 64K-sector size, erase one first */ + ret=SFlash_Blk64_Erase(flashCfg,startaddr/BFLB_SPIFLASH_BLK64K_SIZE); + eraseLen=BFLB_SPIFLASH_BLK64K_SIZE; + }else if( flashCfg->blk32EraseCmd!=BFLB_SPIFLASH_CMD_INVALID && + (startaddr&(BFLB_SPIFLASH_BLK32K_SIZE-1))==0 && + len>(BFLB_SPIFLASH_BLK32K_SIZE-flashCfg->sectorSize*1024)){ + /* 32K margin address,and length > 32K-sector size, erase one first */ + ret=SFlash_Blk32_Erase(flashCfg,startaddr/BFLB_SPIFLASH_BLK32K_SIZE); + eraseLen=BFLB_SPIFLASH_BLK32K_SIZE; + }else{ + /* Sector erase */ + startaddr=((startaddr) & (~(flashCfg->sectorSize*1024 - 1))); + ret=SFlash_Sector_Erase(flashCfg,startaddr/flashCfg->sectorSize/1024); + eraseLen=flashCfg->sectorSize*1024; + } + + startaddr+=eraseLen; + if(ret!=SUCCESS){ + return ERROR; + } + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Program flash one region + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param ioMode: progran mode:SPI mode or QPI mode + * @param addr: start address to be programed + * @param data: data pointer to be programed + * @param len: data length to be programed + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, + SF_Ctrl_IO_Type ioMode,uint32_t addr,uint8_t *data, uint32_t len) +{ + uint8_t * const flashCtrlBuf=(uint8_t *)SF_CTRL_BUF_BASE; + uint32_t i=0,curLen=0; + uint32_t cnt=0; + BL_Err_Type stat; + uint8_t cmd; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + + if(SF_CTRL_NIO_MODE==ioMode||SF_CTRL_DO_MODE==ioMode||SF_CTRL_DIO_MODE==ioMode) + { + cmd=flashCfg->pageProgramCmd; + }else if(SF_CTRL_QIO_MODE==ioMode||SF_CTRL_QO_MODE==ioMode){ + flashCmd.addrMode=(SF_Ctrl_Addr_Mode_Type)flashCfg->qppAddrMode; + flashCmd.dataMode=SF_CTRL_DATA_4_LINES; + cmd=flashCfg->qpageProgramCmd; + }else{ + return ERROR; + } + + /* Prepare command */ + flashCmd.rwFlag=SF_CTRL_WRITE; + flashCmd.addrSize=3; + + for(i=0;ipageSize-addr%flashCfg->pageSize; + if(curLen>len-i){ + curLen=len-i; + } + + /* Prepare command */ + BL602_MemCpy_Fast(flashCtrlBuf,data,curLen); + flashCmd.cmdBuf[0]=(cmd<<24)|(addr); + flashCmd.nbData=curLen; + + SF_Ctrl_SendCmd(&flashCmd); + + /* Adjust address and programmed length */ + addr+=curLen; + i+=curLen; + data+=curLen; + + /* Wait for write done */ + cnt=0; + while(SET==SFlash_Busy(flashCfg)){ + BL602_Delay_US(100); + cnt++; + if(cnt>flashCfg->timePagePgm*20){ + return ERROR; + } + } + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Get flash unique ID + * + * @param data: data pointer to store read data + * @param idLen: unique ID len + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SFlash_GetUniqueId(uint8_t *data,uint8_t idLen) +{ + uint8_t * const flashCtrlBuf=(uint8_t *)SF_CTRL_BUF_BASE; + uint8_t cmd,dummyClks; + uint32_t timeOut=0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + + dummyClks=4; + cmd=0x4B; + flashCmd.cmdBuf[0]=(cmd<<24); + flashCmd.rwFlag=SF_CTRL_READ; + flashCmd.dummyClks=dummyClks; + flashCmd.nbData=idLen; + + SF_Ctrl_SendCmd(&flashCmd); + + timeOut=SFCTRL_BUSY_STATE_TIMEOUT; + while(SET==SF_Ctrl_GetBusyState()){ + timeOut--; + if(timeOut==0){ + return; + } + } + + BL602_MemCpy(data,flashCtrlBuf,idLen); +} + +/****************************************************************************//** + * @brief Get flash jedec ID + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param data: data pointer to store read data + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg,uint8_t *data) +{ + uint8_t * const flashCtrlBuf=(uint8_t *)SF_CTRL_BUF_BASE; + uint8_t cmd,dummyClks; + uint32_t timeOut=0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + + dummyClks=flashCfg->jedecIdCmdDmyClk; + cmd=flashCfg->jedecIdCmd; + flashCmd.cmdBuf[0]=(cmd<<24); + flashCmd.rwFlag=SF_CTRL_READ; + flashCmd.dummyClks=dummyClks; + flashCmd.nbData=3; + + SF_Ctrl_SendCmd(&flashCmd); + + timeOut=SFCTRL_BUSY_STATE_TIMEOUT; + while(SET==SF_Ctrl_GetBusyState()){ + timeOut--; + if(timeOut==0){ + return; + } + } + + BL602_MemCpy(data,flashCtrlBuf,3); +} + +/****************************************************************************//** + * @brief Get flash device ID + * + * @param data: data pointer to store read data + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SFlash_GetDeviceId(uint8_t *data) +{ + uint8_t * const flashCtrlBuf=(uint8_t *)SF_CTRL_BUF_BASE; + uint8_t cmd,dummyClks; + uint32_t timeOut=0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint32_t addr = 0x00000001; + uint8_t readMode = 0xFF; + + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + + flashCmd.addrMode=SF_CTRL_ADDR_4_LINES; + flashCmd.dataMode=SF_CTRL_DATA_4_LINES; + dummyClks=2; + cmd=0x94; + flashCmd.cmdBuf[0]=(cmd<<24)|(addr); + flashCmd.cmdBuf[1]=(readMode<<24); + flashCmd.rwFlag=SF_CTRL_READ; + flashCmd.addrSize=4; + flashCmd.dummyClks=dummyClks; + flashCmd.nbData=2; + + SF_Ctrl_SendCmd(&flashCmd); + + timeOut=SFCTRL_BUSY_STATE_TIMEOUT; + while(SET==SF_Ctrl_GetBusyState()){ + timeOut--; + if(timeOut==0){ + return; + } + } + + BL602_MemCpy(data,flashCtrlBuf,2); +} + +/****************************************************************************//** + * @brief Set flash power down + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SFlash_Powerdown(void) +{ + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint8_t cmd=0; + uint32_t timeOut=0; + + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + + cmd=0xB9; + flashCmd.cmdBuf[0]=(cmd<<24); + flashCmd.rwFlag=SF_CTRL_WRITE; + + SF_Ctrl_SendCmd(&flashCmd); + + timeOut=SFCTRL_BUSY_STATE_TIMEOUT; + while(SET==SF_Ctrl_GetBusyState()){ + timeOut--; + if(timeOut==0) + return; + } +} + +/****************************************************************************//** + * @brief Release flash power down for wake up + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg) +{ + uint8_t cmd; + uint32_t timeOut=0; + + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + cmd=flashCfg->releasePowerDown; + flashCmd.cmdBuf[0]=(cmd<<24); + flashCmd.rwFlag=SF_CTRL_WRITE; + + SF_Ctrl_SendCmd(&flashCmd); + + timeOut=SFCTRL_BUSY_STATE_TIMEOUT; + while(SET==SF_Ctrl_GetBusyState()){ + timeOut--; + if(timeOut==0) + return; + } +} + +/****************************************************************************//** + * @brief Set flash burst wrap config + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg) +{ + uint8_t * const flashCtrlBuf=(uint8_t *)SF_CTRL_BUF_BASE; + uint8_t cmd,dummyClks; + uint32_t wrapData; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if(((flashCfg->ioMode>>4)&0x01)==1){ + /* Disable burst wrap ,just return */ + return; + } + + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + + flashCmd.addrMode=(SF_Ctrl_Addr_Mode_Type)flashCfg->burstWrapDataMode; + flashCmd.dataMode=(SF_Ctrl_Data_Mode_Type)flashCfg->burstWrapDataMode; + dummyClks=flashCfg->burstWrapCmdDmyClk; + cmd=flashCfg->burstWrapCmd; + wrapData=flashCfg->burstWrapData; + BL602_MemCpy4((uint32_t *)flashCtrlBuf,&wrapData,4); + flashCmd.cmdBuf[0]=(cmd<<24); + flashCmd.rwFlag=SF_CTRL_WRITE; + flashCmd.dummyClks=dummyClks; + flashCmd.nbData=1; + + SF_Ctrl_SendCmd(&flashCmd); +} + +/****************************************************************************//** + * @brief Disable flash burst wrap config + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg) +{ + uint8_t * const flashCtrlBuf=(uint8_t *)SF_CTRL_BUF_BASE; + uint8_t cmd,dummyClks; + uint32_t wrapData; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + + flashCmd.addrMode=(SF_Ctrl_Addr_Mode_Type)flashCfg->deBurstWrapDataMode; + flashCmd.dataMode=(SF_Ctrl_Data_Mode_Type)flashCfg->deBurstWrapDataMode; + dummyClks=flashCfg->deBurstWrapCmdDmyClk; + cmd=flashCfg->deBurstWrapCmd; + wrapData=flashCfg->deBurstWrapData; + BL602_MemCpy4((uint32_t *)flashCtrlBuf,&wrapData,4); + flashCmd.cmdBuf[0]=(cmd<<24); + flashCmd.rwFlag=SF_CTRL_WRITE; + flashCmd.dummyClks=dummyClks; + flashCmd.nbData=1; + + SF_Ctrl_SendCmd(&flashCmd); +} + +/****************************************************************************//** + * @brief Software reset flash + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg) +{ + uint16_t cnt=0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + + /* Reset enable */ + flashCmd.cmdBuf[0]=(flashCfg->resetEnCmd)<<24; + /* rwFlag don't care */ + flashCmd.rwFlag=SF_CTRL_READ; + /* Wait for write done */ + while(SET==SFlash_Busy(flashCfg)){ + BL602_Delay_US(100); + cnt++; + if(cnt>20){ + return ERROR; + } + } + SF_Ctrl_SendCmd(&flashCmd); + + /* Reset */ + flashCmd.cmdBuf[0]=(flashCfg->resetCmd)<<24; + /* rwFlag don't care */ + flashCmd.rwFlag=SF_CTRL_READ; + SF_Ctrl_SendCmd(&flashCmd); + + BL602_Delay_US(50); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Reset flash continous read mode + * + * @param flashCfg: Serial flash parameter configuration pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg) +{ + SF_Ctrl_Cmd_Cfg_Type flashCmd; + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + + /* Reset continous read */ + BL602_MemSet(&flashCmd.cmdBuf[0],flashCfg->resetCreadCmd,4); + /* rwFlag don't care */ + flashCmd.rwFlag=SF_CTRL_READ; + flashCmd.addrSize=flashCfg->resetCreadCmdSize; + SF_Ctrl_SendCmd(&flashCmd); +} + +/****************************************************************************//** + * @brief Set I/D bus read flash configuration in flash controller + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param ioMode: flash controller interface mode + * @param contRead: Wether enable cont read mode + * @param addr: address to read/write + * @param len: data length to read/write + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, + SF_Ctrl_IO_Type ioMode,uint8_t contRead,uint32_t addr,uint32_t len) +{ + uint8_t cmd,dummyClks; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint8_t cmdValid=1; + uint8_t noReadModeCfg=0; + uint8_t cReadSupport=0; + + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB); + + if(SF_CTRL_NIO_MODE==ioMode){ + cmd=flashCfg->fastReadCmd; + dummyClks=flashCfg->frDmyClk; + }else if(SF_CTRL_DO_MODE==ioMode){ + flashCmd.dataMode=SF_CTRL_DATA_2_LINES; + cmd=flashCfg->fastReadDoCmd; + dummyClks=flashCfg->frDoDmyClk; + }else if(SF_CTRL_DIO_MODE==ioMode){ + flashCmd.addrMode=SF_CTRL_ADDR_2_LINES; + flashCmd.dataMode=SF_CTRL_DATA_2_LINES; + cmd=flashCfg->fastReadDioCmd; + dummyClks=flashCfg->frDioDmyClk; + }else if(SF_CTRL_QO_MODE==ioMode){ + flashCmd.dataMode=SF_CTRL_DATA_4_LINES; + cmd=flashCfg->fastReadQoCmd; + dummyClks=flashCfg->frQoDmyClk; + }else if(SF_CTRL_QIO_MODE==ioMode){ + flashCmd.addrMode=SF_CTRL_ADDR_4_LINES; + flashCmd.dataMode=SF_CTRL_DATA_4_LINES; + cmd=flashCfg->fastReadQioCmd; + dummyClks=flashCfg->frQioDmyClk; + }else{ + return ERROR; + } + + /*prepare command**/ + flashCmd.rwFlag=SF_CTRL_READ; + flashCmd.addrSize=3; + flashCmd.cmdBuf[0]=(cmd<<24)|addr; + if(SF_CTRL_QIO_MODE==ioMode||SF_CTRL_DIO_MODE==ioMode){ + noReadModeCfg=flashCfg->cReadSupport&0x02; + cReadSupport=flashCfg->cReadSupport&0x01; + if(noReadModeCfg==0){ + /* Read mode must be set*/ + if(cReadSupport==0){ + /* Not support cont read,but we still need set read mode(winbond 80dv)*/ + flashCmd.cmdBuf[1]=(flashCfg->cReadMode<<24); + }else{ + /* Flash support cont read, setting depend on user parameter */ + if(contRead){ + flashCmd.cmdBuf[0]=(addr<<8)|flashCfg->cReadMode; + cmdValid=0; + }else{ + flashCmd.cmdBuf[1]=((!flashCfg->cReadMode)<<24); + } + } + flashCmd.addrSize++; + } + } + flashCmd.dummyClks=dummyClks; + flashCmd.nbData=len; + SF_Ctrl_Icache_Set(&flashCmd,cmdValid); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Enable I/D bus read from flash + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param ioMode: flash controller interface mode + * @param contRead: Wether enable cont read mode + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint8_t contRead) +{ + BL_Err_Type stat; + + stat=SFlash_Set_IDbus_Cfg(flashCfg,ioMode,contRead,0,4); + if(SUCCESS!=stat){ + return stat; + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Enable cache + * + * @param wayDisable: cache way disable config + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Enable_Set(uint8_t wayDisable) +{ + uint32_t tmpVal; + uint32_t cnt=0; + + /* Set cacheable to 0 */ + tmpVal=BL_RD_REG(L1C_BASE,L1C_CONFIG); + tmpVal=BL_CLR_REG_BIT(tmpVal,L1C_CACHEABLE); + tmpVal=BL_SET_REG_BIT(tmpVal,L1C_BYPASS); + tmpVal=BL_CLR_REG_BIT(tmpVal,L1C_WAY_DIS); + tmpVal=BL_CLR_REG_BIT(tmpVal,L1C_CNT_EN); + BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal); + + tmpVal=BL_RD_REG(L1C_BASE,L1C_CONFIG); + /*Set Tag RAM to zero */ + tmpVal=BL_CLR_REG_BIT(tmpVal,L1C_INVALID_EN); + BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal); + /* Left space for hardware change status*/ + __NOP(); + __NOP(); + __NOP(); + __NOP(); + tmpVal=BL_SET_REG_BIT(tmpVal,L1C_INVALID_EN); + BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal); + /* Left space for hardware change status*/ + __NOP(); + __NOP(); + __NOP(); + __NOP(); + /* Polling for invalid done */ + do{ + BL602_Delay_US(1); + cnt++; + tmpVal=BL_RD_REG(L1C_BASE,L1C_CONFIG); + }while(!BL_IS_REG_BIT_SET(tmpVal,L1C_INVALID_DONE)&&cnt<100); + + + tmpVal=BL_SET_REG_BIT(tmpVal,L1C_BYPASS); + BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal); + + tmpVal=BL_CLR_REG_BIT(tmpVal,L1C_BYPASS); + tmpVal=BL_CLR_REG_BIT(tmpVal,L1C_WAY_DIS); + tmpVal=BL_SET_REG_BIT(tmpVal,L1C_CNT_EN); + BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal); + + tmpVal|=(wayDisable<>L1C_WAY_DIS_POS)&0xf); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Enable cache read from flash with cache + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param ioMode: flash controller interface mode + * @param contRead: Wether enable cont read mode + * @param wayDisable: cache way disable config + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, + SF_Ctrl_IO_Type ioMode,uint8_t contRead,uint8_t wayDisable) +{ + BL_Err_Type stat; + + /* Cache now only support 32 bytes read */ + stat=SFlash_Set_IDbus_Cfg(flashCfg,ioMode,contRead,0,32); + if(SUCCESS!=stat){ + return stat; + } + + return SFlash_Cache_Enable_Set(wayDisable); +} + +/****************************************************************************//** + * @brief Get cache hit count + * + * @param hitCountLow: hit count low 32 bits pointer + * @param hitCountHigh: hit count high 32 bits pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SFlash_Cache_Hit_Count_Get(uint32_t *hitCountLow,uint32_t *hitCountHigh) +{ + *hitCountLow=BL_RD_REG(L1C_BASE,L1C_HIT_CNT_LSB); + *hitCountHigh=BL_RD_REG(L1C_BASE,L1C_HIT_CNT_MSB); +} + +/****************************************************************************//** + * @brief Get cache miss count + * + * @param None + * + * @return Cache miss count + * +*******************************************************************************/ +__WEAK +uint32_t ATTR_TCM_SECTION SFlash_Cache_Miss_Count_Get(void) +{ + return BL_RD_REG(L1C_BASE,L1C_MISS_CNT); +} + +/****************************************************************************//** + * @brief Disable read from flash with cache + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION SFlash_Cache_Read_Disable(void) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(L1C_BASE,L1C_CONFIG); + tmpVal=BL_CLR_REG_BIT(tmpVal,L1C_CACHEABLE); + BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal); +} + +/****************************************************************************//** + * @brief Read data from flash + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param ioMode: flash controller interface mode + * @param contRead: Wether enable cont read mode + * @param addr: flash read start address + * @param data: data pointer to store data read from flash + * @param len: data length to read + * + * @return None + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, + SF_Ctrl_IO_Type ioMode,uint8_t contRead,uint32_t addr,uint8_t *data, uint32_t len) +{ + uint8_t * const flashCtrlBuf=(uint8_t *)SF_CTRL_BUF_BASE; + uint32_t curLen,i; + uint8_t cmd,dummyClks; + uint32_t timeOut=0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint8_t noReadModeCfg=0; + uint8_t cReadSupport=0; + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + + if(SF_CTRL_NIO_MODE==ioMode){ + cmd=flashCfg->fastReadCmd; + dummyClks=flashCfg->frDmyClk; + }else if(SF_CTRL_DO_MODE==ioMode){ + flashCmd.dataMode=SF_CTRL_DATA_2_LINES; + cmd=flashCfg->fastReadDoCmd; + dummyClks=flashCfg->frDoDmyClk; + }else if(SF_CTRL_DIO_MODE==ioMode){ + flashCmd.addrMode=SF_CTRL_ADDR_2_LINES; + flashCmd.dataMode=SF_CTRL_DATA_2_LINES; + cmd=flashCfg->fastReadDioCmd; + dummyClks=flashCfg->frDioDmyClk; + }else if(SF_CTRL_QO_MODE==ioMode){ + flashCmd.dataMode=SF_CTRL_DATA_4_LINES; + cmd=flashCfg->fastReadQoCmd; + dummyClks=flashCfg->frQoDmyClk; + }else if(SF_CTRL_QIO_MODE==ioMode){ + flashCmd.addrMode=SF_CTRL_ADDR_4_LINES; + flashCmd.dataMode=SF_CTRL_DATA_4_LINES; + cmd=flashCfg->fastReadQioCmd; + dummyClks=flashCfg->frQioDmyClk; + }else{ + return ERROR; + } + + /* Prepare command */ + flashCmd.rwFlag=SF_CTRL_READ; + flashCmd.addrSize=3; + if(SF_CTRL_QIO_MODE==ioMode||SF_CTRL_DIO_MODE==ioMode){ + noReadModeCfg=flashCfg->cReadSupport&0x02; + cReadSupport=flashCfg->cReadSupport&0x01; + if(noReadModeCfg==0){ + /* Read mode must be set*/ + if(cReadSupport==0){ + /* Not support cont read,but we still need set read mode(winbond 80dv)*/ + flashCmd.cmdBuf[1]=(flashCfg->cReadMode<<24); + }else{ + /* Flash support cont read, setting depend on user parameter */ + if(contRead){ + flashCmd.cmdBuf[1]=(flashCfg->cReadMode<<24); + }else{ + flashCmd.cmdBuf[1]=((!flashCfg->cReadMode)<<24); + } + } + flashCmd.addrSize++; + } + } + flashCmd.dummyClks=dummyClks; + + /* Read data */ + for(i=0;i=FLASH_CTRL_BUF_SIZE){ + curLen=FLASH_CTRL_BUF_SIZE; + flashCmd.nbData=curLen; + }else{ + /* Make sf_ctrl word read */ + flashCmd.nbData=((curLen+3)>>2)<<2; + } + + SF_Ctrl_SendCmd(&flashCmd); + + timeOut=SFCTRL_BUSY_STATE_TIMEOUT; + while(SET==SF_Ctrl_GetBusyState()){ + timeOut--; + if(timeOut==0){ + return TIMEOUT; + } + } + BL602_MemCpy_Fast(data,flashCtrlBuf,curLen); + + addr+=curLen; + i+=curLen; + data+=curLen; + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Read flash register with read command + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param readRegCmd: read command + * @param regValue: register value pointer to store data + * @param regLen: register value length + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg,uint8_t readRegCmd,uint8_t *regValue,uint8_t regLen) +{ + uint8_t * const flashCtrlBuf=(uint8_t *)SF_CTRL_BUF_BASE; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint32_t cnt=0; + + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + + flashCmd.cmdBuf[0]=readRegCmd<<24; + flashCmd.rwFlag=SF_CTRL_READ; + flashCmd.nbData=regLen; + + SF_Ctrl_SendCmd(&flashCmd); + + while(SET==SF_Ctrl_GetBusyState()){ + BL602_Delay_US(1); + cnt++; + if(cnt>1000){ + return ERROR; + } + } + + BL602_MemCpy(regValue,flashCtrlBuf,regLen); + return SUCCESS; +} + +/****************************************************************************//** + * @brief Write flash register with write command + * + * @param flashCfg: Serial flash parameter configuration pointer + * @param writeRegCmd: write command + * @param regValue: register value pointer storing data + * @param regLen: register value length + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg,uint8_t writeRegCmd,uint8_t *regValue,uint8_t regLen) +{ + uint8_t * const flashCtrlBuf=(uint8_t *)SF_CTRL_BUF_BASE; + uint32_t cnt=0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + BL602_MemCpy(flashCtrlBuf,regValue,regLen); + + flashCmd.cmdBuf[0]=writeRegCmd<<24; + flashCmd.rwFlag=SF_CTRL_WRITE; + flashCmd.nbData=regLen; + + SF_Ctrl_SendCmd(&flashCmd); + + /* take 40ms for tw(write status register) as default */ + while(SET==SFlash_Busy(flashCfg)){ + BL602_Delay_US(100); + cnt++; + if(cnt>400){ + return ERROR; + } + } + + return SUCCESS; +} +#endif + +/*@} end of group SFLASH_Public_Functions */ + +/*@} end of group SFLASH */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/bl602_driver/std_drv/src/bl602_sflash_ext.c b/drivers/bl602_driver/std_drv/src/bl602_sflash_ext.c new file mode 100644 index 00000000..c2f14c72 --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_sflash_ext.c @@ -0,0 +1,504 @@ +/** + ****************************************************************************** + * @file bl602_sflash_ext.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_l1c.h" +#include "bl602_sflash_ext.h" +#include "bl602_sf_ctrl.h" +#include "l1c_reg.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SFLASH_EXT + * @{ + */ + +/** @defgroup SFLASH_EXT_Private_Macros + * @{ + */ + +/*@} end of group SFLASH_EXT_Private_Macros */ + +/** @defgroup SFLASH_EXT_Private_Types + * @{ + */ + +/*@} end of group SFLASH_EXT_Private_Types */ + +/** @defgroup SFLASH_EXT_Private_Variables + * @{ + */ +#define SFCTRL_BUSY_STATE_TIMEOUT (5*160*1000) + +/*@} end of group SFLASH_EXT_Private_Variables */ + +/** @defgroup SFLASH_EXT_Global_Variables + * @{ + */ + +/*@} end of group SFLASH_EXT_Global_Variables */ + +/** @defgroup SFLASH_EXT_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SFLASH_EXT_Private_Fun_Declaration */ + +/** @defgroup SFLASH_EXT_Private_Functions + * @{ + */ + +/*@} end of group SFLASH_EXT_Private_Functions */ + +/** @defgroup SFLASH_EXT_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief Sflash restore from power down + * + * @param pFlashCfg: Flash configuration pointer + * @param flashContRead: Whether enable continuous read + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t flashContRead) +{ + BL_Err_Type stat=SUCCESS; + uint32_t jdecId=0; + uint8_t tmp[8]; + uint8_t ioMode=pFlashCfg->ioMode&0xf; + + /* Wake flash up from power down */ + SFlash_Releae_Powerdown(pFlashCfg); + BL602_Delay_US(120); + + SFlash_GetJedecId(pFlashCfg,(uint8_t *)&jdecId); + + if(SF_CTRL_QO_MODE==ioMode||SF_CTRL_QIO_MODE==ioMode){ + SFlash_Qspi_Enable(pFlashCfg); + } + + if(((pFlashCfg->ioMode>>4)&0x01)==1){ + /* unwrap */ + L1C_Set_Wrap(DISABLE); + }else{ + /* burst wrap */ + L1C_Set_Wrap(ENABLE); + /* For command that is setting register instead of send command, we need write enable */ + SFlash_Write_Enable(pFlashCfg); + SFlash_SetBurstWrap(pFlashCfg); + } + + if(flashContRead){ + stat=SFlash_Read(pFlashCfg,ioMode,1,0x00000000,(uint8_t *)tmp, sizeof(tmp)); + stat=SFlash_Set_IDbus_Cfg(pFlashCfg,ioMode,1,0,32); + }else{ + stat=SFlash_Set_IDbus_Cfg(pFlashCfg,ioMode,0,0,32); + } + return stat; +} + +/****************************************************************************//** + * @brief Sflash enable RCV mode to recovery for erase while power drop + * + * @param pFlashCfg: Flash configuration pointer + * @param rCmd: Read RCV register cmd + * @param wCmd: Write RCV register cmd + * @param bitPos: RCV register bit pos + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION SFlash_RCV_Enable(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos) +{ + BL_Err_Type stat; + uint32_t cnt = 0; + uint32_t tempVal = 0; + + while(SET == SFlash_Busy(pFlashCfg)){ + BL602_Delay_US(500); + cnt++; + if(cnt > 20000*3){ + return ERROR; + } + } + stat = SFlash_Read_Reg_With_Cmd(pFlashCfg, rCmd, (uint8_t *)&tempVal, 1); + if(SUCCESS != stat){ + stat = ERROR; + } + if(((tempVal>>bitPos)&0x01) > 0){ + return SUCCESS; + } + + tempVal |= (uint32_t)(1 << bitPos); + stat = SFlash_Write_Enable(pFlashCfg); + if(SUCCESS != stat){ + stat = ERROR; + } + stat = SFlash_Write_Reg_With_Cmd(pFlashCfg, wCmd, (uint8_t *)&tempVal, 1); + if(SUCCESS != stat){ + return stat; + } + while(SET == SFlash_Busy(pFlashCfg)){ + BL602_Delay_US(500); + cnt++; + if(cnt > 20000*3){ + return ERROR; + } + } + stat = SFlash_Read_Reg_With_Cmd(pFlashCfg, rCmd, (uint8_t *)&tempVal, 1); + if(SUCCESS != stat){ + stat = ERROR; + } + if(((tempVal>>bitPos)&0x01) <= 0){ + return ERROR; + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Erase flash security register one block + * + * @param pFlashCfg: Flash configuration pointer + * @param pSecRegCfg: Security register configuration pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION SFlash_Erase_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg) +{ + uint32_t cnt = 0; + uint8_t cmd = 0; + uint8_t secOptMode = 0; + uint32_t timeOut=0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if(pSecRegCfg->enterSecOptCmd != 0x00){ + secOptMode = 1; + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd<<24); + flashCmd.rwFlag = SF_CTRL_WRITE; + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + while(SET == SF_Ctrl_GetBusyState()){ + timeOut--; + if(timeOut == 0){ + return TIMEOUT; + } + } + } + + BL_Err_Type stat = SFlash_Write_Enable(pFlashCfg); + if(stat != SUCCESS){ + return stat; + } + if(((uint32_t)&flashCmd)%4 == 0){ + BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + } + + cmd = pSecRegCfg->eraseCmd; + flashCmd.cmdBuf[0] = (cmd<<24) | (pSecRegCfg->blockNum<<12); + /* rwFlag don't care */ + flashCmd.rwFlag = SF_CTRL_READ; + flashCmd.addrSize = 3; + + SF_Ctrl_SendCmd(&flashCmd); + + while(SET==SFlash_Busy(pFlashCfg)){ + BL602_Delay_US(500); + cnt++; + if(cnt > pFlashCfg->timeEsector*3){ + return ERROR; + } + } + + if(secOptMode > 0){ + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd<<24); + flashCmd.rwFlag = SF_CTRL_WRITE; + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + while(SET == SF_Ctrl_GetBusyState()){ + timeOut--; + if(timeOut == 0){ + return TIMEOUT; + } + } + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Program flash security register one block + * + * @param pFlashCfg: Flash configuration pointer + * @param pSecRegCfg: Security register configuration pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION SFlash_Program_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg) +{ + uint8_t * const flashCtrlBuf=(uint8_t *)SF_CTRL_BUF_BASE; + uint32_t i=0,curLen=0; + uint32_t cnt=0; + BL_Err_Type stat; + uint8_t cmd; + uint8_t secOptMode = 0; + uint8_t *data = pSecRegCfg->data; + uint32_t addr = pSecRegCfg->addr; + uint32_t len = pSecRegCfg->len; + uint32_t currentAddr=0; + uint32_t timeOut=0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if(pSecRegCfg->enterSecOptCmd != 0x00){ + secOptMode = 1; + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd<<24); + flashCmd.rwFlag = SF_CTRL_WRITE; + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + while(SET == SF_Ctrl_GetBusyState()){ + timeOut--; + if(timeOut == 0){ + return TIMEOUT; + } + } + } + + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + + /* Prepare command */ + flashCmd.rwFlag=SF_CTRL_WRITE; + flashCmd.addrSize=3; + cmd=pSecRegCfg->programCmd; + + for(i=0;ilen-i){ + curLen=len-i; + } + currentAddr = (pSecRegCfg->blockNum<<12) | addr; + + /* Prepare command */ + BL602_MemCpy_Fast(flashCtrlBuf,data,curLen); + flashCmd.cmdBuf[0]=(cmd<<24)|(currentAddr); + flashCmd.nbData=curLen; + + SF_Ctrl_SendCmd(&flashCmd); + + /* Adjust address and programmed length */ + addr+=curLen; + i+=curLen; + data+=curLen; + + /* Wait for write done */ + cnt=0; + while(SET==SFlash_Busy(pFlashCfg)){ + BL602_Delay_US(100); + cnt++; + if(cnt>pFlashCfg->timePagePgm*20){ + return ERROR; + } + } + } + + if(secOptMode > 0){ + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd<<24); + flashCmd.rwFlag = SF_CTRL_WRITE; + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + while(SET == SF_Ctrl_GetBusyState()){ + timeOut--; + if(timeOut == 0){ + return TIMEOUT; + } + } + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Read data from flash security register one block + * + * @param pSecRegCfg: Security register configuration pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Security_Register(SFlash_Sec_Reg_Cfg *pSecRegCfg) +{ + uint8_t * const flashCtrlBuf=(uint8_t *)SF_CTRL_BUF_BASE; + uint32_t curLen,i; + uint8_t cmd; + uint8_t secOptMode = 0; + uint8_t *data = pSecRegCfg->data; + uint32_t addr = pSecRegCfg->addr; + uint32_t len = pSecRegCfg->len; + uint32_t currentAddr=0; + uint32_t timeOut=0; + SF_Ctrl_Cmd_Cfg_Type flashCmd; + + if(pSecRegCfg->enterSecOptCmd != 0x00){ + secOptMode = 1; + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd<<24); + flashCmd.rwFlag = SF_CTRL_WRITE; + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + while(SET == SF_Ctrl_GetBusyState()){ + timeOut--; + if(timeOut == 0){ + return TIMEOUT; + } + } + } + + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + /* Prepare command */ + flashCmd.rwFlag=SF_CTRL_READ; + flashCmd.addrSize=3; + flashCmd.dummyClks=1; + cmd=pSecRegCfg->readCmd; + + /* Read data */ + for(i=0;iblockNum<<12) | addr; + /* Prepare command */ + flashCmd.cmdBuf[0]=(cmd<<24)|(currentAddr); + curLen=len-i; + if(curLen>=FLASH_CTRL_BUF_SIZE){ + curLen=FLASH_CTRL_BUF_SIZE; + flashCmd.nbData=curLen; + }else{ + /* Make sf_ctrl word read */ + flashCmd.nbData=((curLen+3)>>2)<<2; + } + + SF_Ctrl_SendCmd(&flashCmd); + + timeOut=SFCTRL_BUSY_STATE_TIMEOUT; + while(SET==SF_Ctrl_GetBusyState()){ + timeOut--; + if(timeOut==0){ + return TIMEOUT; + } + } + BL602_MemCpy_Fast(data,flashCtrlBuf,curLen); + + addr+=curLen; + i+=curLen; + data+=curLen; + } + + if(secOptMode > 0){ + if(((uint32_t)&flashCmd)%4==0){ + BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4); + }else{ + BL602_MemSet(&flashCmd,0,sizeof(flashCmd)); + } + flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd<<24); + flashCmd.rwFlag = SF_CTRL_WRITE; + SF_Ctrl_SendCmd(&flashCmd); + + timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + while(SET == SF_Ctrl_GetBusyState()){ + timeOut--; + if(timeOut == 0){ + return TIMEOUT; + } + } + } + + return SUCCESS; +} + +/*@} end of group SFLASH_EXT_Public_Functions */ + +/*@} end of group SFLASH_EXT */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/bl602_driver/std_drv/src/bl602_spi.c b/drivers/bl602_driver/std_drv/src/bl602_spi.c new file mode 100644 index 00000000..1a8c395c --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_spi.c @@ -0,0 +1,1711 @@ +/** + ****************************************************************************** + * @file bl602_spi.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_spi.h" +#include "bl602_glb.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @defgroup SPI_Private_Macros + * @{ + */ +#define SPI_TX_TIMEOUT_COUNT (160*1000) +#define SPI_RX_TIMEOUT_COUNT (160*1000) + +/*@} end of group SPI_Private_Macros */ + +/** @defgroup SPI_Private_Types + * @{ + */ + +/*@} end of group SPI_Private_Types */ + +/** @defgroup SPI_Private_Variables + * @{ + */ +static const uint32_t spiAddr[SPI_ID_MAX] = {SPI_BASE}; +static intCallback_Type * spiIntCbfArra[SPI_ID_MAX][SPI_INT_ALL]= { + {NULL} +}; + + +/*@} end of group SPI_Private_Variables */ + +/** @defgroup SPI_Global_Variables + * @{ + */ + +/*@} end of group SPI_Global_Variables */ + +/** @defgroup SPI_Private_Fun_Declaration + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +static void SPI_IntHandler(SPI_ID_Type spiNo); +#endif + +/*@} end of group SPI_Private_Fun_Declaration */ + +/** @defgroup SPI_Private_Functions + * @{ + */ + +/****************************************************************************//** + * @brief SPI interrupt common handler function + * + * @param spiNo: SPI ID type + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +static void SPI_IntHandler(SPI_ID_Type spiNo) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + tmpVal = BL_RD_REG(SPIx,SPI_INT_STS); + + /* Transfer end interrupt,shared by both master and slave mode */ + if(BL_IS_REG_BIT_SET(tmpVal,SPI_END_INT) && !BL_IS_REG_BIT_SET(tmpVal,SPI_CR_SPI_END_MASK)){ + BL_WR_REG(SPIx,SPI_INT_STS,BL_SET_REG_BIT(tmpVal,SPI_CR_SPI_END_CLR)); + if(spiIntCbfArra[spiNo][SPI_INT_END] != NULL){ + spiIntCbfArra[spiNo][SPI_INT_END](); + } + } + /* TX fifo ready interrupt(fifo count > fifo threshold) */ + if(BL_IS_REG_BIT_SET(tmpVal,SPI_TXF_INT) && !BL_IS_REG_BIT_SET(tmpVal,SPI_CR_SPI_TXF_MASK)){ + if(spiIntCbfArra[spiNo][SPI_INT_TX_FIFO_REQ] != NULL){ + spiIntCbfArra[spiNo][SPI_INT_TX_FIFO_REQ](); + } + } + /* RX fifo ready interrupt(fifo count > fifo threshold) */ + if(BL_IS_REG_BIT_SET(tmpVal,SPI_RXF_INT) && !BL_IS_REG_BIT_SET(tmpVal,SPI_CR_SPI_RXF_MASK)){ + if(spiIntCbfArra[spiNo][SPI_INT_RX_FIFO_REQ] != NULL){ + spiIntCbfArra[spiNo][SPI_INT_RX_FIFO_REQ](); + } + } + /* Slave mode transfer time-out interrupt,triggered when bus is idle for the given value */ + if(BL_IS_REG_BIT_SET(tmpVal,SPI_STO_INT) && !BL_IS_REG_BIT_SET(tmpVal,SPI_CR_SPI_STO_MASK)){ + BL_WR_REG(SPIx,SPI_INT_STS,BL_SET_REG_BIT(tmpVal,SPI_CR_SPI_STO_CLR)); + if(spiIntCbfArra[spiNo][SPI_INT_SLAVE_TIMEOUT] != NULL){ + spiIntCbfArra[spiNo][SPI_INT_SLAVE_TIMEOUT](); + } + } + /* Slave mode tx underrun error interrupt,trigged when tx is not ready during transfer */ + if(BL_IS_REG_BIT_SET(tmpVal,SPI_TXU_INT) && !BL_IS_REG_BIT_SET(tmpVal,SPI_CR_SPI_TXU_MASK)){ + BL_WR_REG(SPIx,SPI_INT_STS,BL_SET_REG_BIT(tmpVal,SPI_CR_SPI_TXU_CLR)); + if(spiIntCbfArra[spiNo][SPI_INT_SLAVE_UNDERRUN] != NULL){ + spiIntCbfArra[spiNo][SPI_INT_SLAVE_UNDERRUN](); + } + } + /* TX/RX fifo overflow/underflow interrupt */ + if(BL_IS_REG_BIT_SET(tmpVal,SPI_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal,SPI_CR_SPI_FER_MASK)){ + if(spiIntCbfArra[spiNo][SPI_INT_FIFO_ERROR] != NULL){ + spiIntCbfArra[spiNo][SPI_INT_FIFO_ERROR](); + } + } +} +#endif + + +/*@} end of group SPI_Private_Functions */ + +/** @defgroup SPI_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief SPI initialization function + * + * @param spiNo: SPI ID type + * @param spiCfg: SPI configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Init(SPI_ID_Type spiNo,SPI_CFG_Type* spiCfg) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(spiCfg->mod)); + CHECK_PARAM(IS_SPI_BYTE_INVERSE_TYPE(spiCfg->byteSequence)); + CHECK_PARAM(IS_SPI_BIT_INVERSE_TYPE(spiCfg->bitSequence)); + CHECK_PARAM(IS_SPI_CLK_PHASE_INVERSE_TYPE(spiCfg->clkPhaseInv)); + CHECK_PARAM(IS_SPI_CLK_POLARITY_TYPE(spiCfg->clkPolarity)); + + /* spi config */ + tmpVal = BL_RD_REG(SPIx,SPI_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_DEG_EN,spiCfg->deglitchEnable); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_M_CONT_EN,spiCfg->continuousEnable); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_BYTE_INV,spiCfg->byteSequence); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_BIT_INV,spiCfg->bitSequence); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_SCLK_PH,(spiCfg->clkPhaseInv+1)&1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_SCLK_POL,spiCfg->clkPolarity); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_FRAME_SIZE,spiCfg->frameSize); + BL_WR_REG(SPIx,SPI_CONFIG,tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(SPI_IRQn,SPI_IRQHandler); +#endif + return SUCCESS; +} + +/****************************************************************************//** + * @brief SPI set default value of all registers function + * + * @param spiNo: SPI ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_DeInit(SPI_ID_Type spiNo) +{ + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + if(SPI_ID_0 == spiNo){ + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_SPI); + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Length of data phase1/0,start/stop condition and interval between frame initialization + * function + * + * @param spiNo: SPI ID type + * @param clockCfg: Clock configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_ClockConfig(SPI_ID_Type spiNo,SPI_ClockCfg_Type *clockCfg) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Configure length of data phase1/0 and start/stop condition */ + tmpVal = BL_RD_REG(SPIx,SPI_PRD_0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_PRD_S,clockCfg->startLen-1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_PRD_P,clockCfg->stopLen-1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_PRD_D_PH_0,clockCfg->dataPhase0Len-1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_PRD_D_PH_1,clockCfg->dataPhase1Len-1); + BL_WR_REG(SPIx,SPI_PRD_0,tmpVal); + + /* Configure length of interval between frame */ + tmpVal = BL_RD_REG(SPIx,SPI_PRD_1); + BL_WR_REG(SPIx,SPI_PRD_1,BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_PRD_I,clockCfg->intervalLen-1)); + + return SUCCESS; +} + + +/****************************************************************************//** + * @brief Set SPI SCK Clcok + * + * @param spiNo: SPI ID type + * @param clk: Clk + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_SetClock(SPI_ID_Type spiNo,uint32_t clk) +{ + uint32_t glb_div = 1,spi_div = 1; + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + if(clk < 4882){ + clk = 4882; + } + + if(clk > 40000000){ + clk = 40000000; + } + + if(clk>156250){ + glb_div = 1; + spi_div = 40000000 / clk; + }else{ + spi_div = 256; + glb_div = clk >>8; + } + + /* Configure length of data phase1/0 and start/stop condition */ + tmpVal = BL_RD_REG(SPIx,SPI_PRD_0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_PRD_S,spi_div-1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_PRD_P,spi_div-1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_PRD_D_PH_0,spi_div-1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_PRD_D_PH_1,spi_div-1); + BL_WR_REG(SPIx,SPI_PRD_0,tmpVal); + + tmpVal = BL_RD_REG(SPIx,SPI_PRD_1); + BL_WR_REG(SPIx,SPI_PRD_1,BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_PRD_I,spi_div-1)); + + GLB_Set_SPI_CLK(ENABLE,glb_div-1); + + return SUCCESS; +} + + +/****************************************************************************//** + * @brief SPI configure fifo function + * + * @param spiNo: SPI ID type + * @param fifoCfg: FIFO configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_FifoConfig(SPI_ID_Type spiNo,SPI_FifoCfg_Type *fifoCfg) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Set fifo threshold value */ + tmpVal = BL_RD_REG(SPIx,SPI_FIFO_CONFIG_1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_TX_FIFO_TH,fifoCfg->txFifoThreshold-1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_RX_FIFO_TH,fifoCfg->rxFifoThreshold-1); + BL_WR_REG(SPIx,SPI_FIFO_CONFIG_1,tmpVal); + + /* Enable or disable dma function */ + tmpVal = BL_RD_REG(SPIx,SPI_FIFO_CONFIG_0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_DMA_TX_EN,fifoCfg->txFifoDmaEnable); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_DMA_RX_EN,fifoCfg->rxFifoDmaEnable); + BL_WR_REG(SPIx,SPI_FIFO_CONFIG_0,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Enable spi transfer + * + * @param spiNo: SPI ID type + * @param modeType: Master or slave mode select + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Enable(SPI_ID_Type spiNo,SPI_WORK_MODE_Type modeType) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(modeType)); + + tmpVal = BL_RD_REG(SPIx,SPI_CONFIG); + if(modeType != SPI_WORK_MODE_SLAVE){ + /* master mode */ + tmpVal = BL_CLR_REG_BIT(tmpVal,SPI_CR_SPI_S_EN); + tmpVal = BL_SET_REG_BIT(tmpVal,SPI_CR_SPI_M_EN); + }else{ + /* slave mode */ + tmpVal = BL_CLR_REG_BIT(tmpVal,SPI_CR_SPI_M_EN); + tmpVal = BL_SET_REG_BIT(tmpVal,SPI_CR_SPI_S_EN); + } + BL_WR_REG(SPIx,SPI_CONFIG,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Disable spi transfer + * + * @param spiNo: SPI ID type + * @param modeType: Master or slave mode select + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_Disable(SPI_ID_Type spiNo,SPI_WORK_MODE_Type modeType) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(modeType)); + + /* close master and slave */ + tmpVal = BL_RD_REG(SPIx,SPI_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal,SPI_CR_SPI_M_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal,SPI_CR_SPI_S_EN); + BL_WR_REG(SPIx,SPI_CONFIG,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Set time-out value to trigger interrupt when spi bus is idle for the given value + * + * @param spiNo: SPI ID type + * @param value: Time value + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_SetTimeOutValue(SPI_ID_Type spiNo,uint16_t value) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Set time-out value */ + tmpVal = BL_RD_REG(SPIx,SPI_STO_VALUE); + BL_WR_REG(SPIx,SPI_STO_VALUE,BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_STO_VALUE,value-1)); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Set de-glitch function cycle count value + * + * @param spiNo: SPI ID type + * @param cnt: De-glitch function cycle count + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_SetDeglitchCount(SPI_ID_Type spiNo,uint8_t cnt) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Set count value */ + tmpVal = BL_RD_REG(SPIx,SPI_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_DEG_CNT,cnt-1); + BL_WR_REG(SPIx,SPI_CONFIG,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Enable rx data ignore function and set start/stop point + * + * @param spiNo: SPI ID type + * @param startPoint: Start point + * @param stopPoint: Stop point + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type SPI_RxIgnoreEnable(SPI_ID_Type spiNo,uint8_t startPoint,uint8_t stopPoint) +{ + uint32_t tmpVal; + uint32_t SPIx = spiAddr[spiNo]; + + /* Check the parameters */ + CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); + + /* Enable rx ignore function */ + tmpVal = BL_RD_REG(SPIx,SPI_CONFIG); + BL_WR_REG(SPIx,SPI_CONFIG,BL_SET_REG_BIT(tmpVal,SPI_CR_SPI_RXD_IGNR_EN)); + + /* Set start and stop point */ + tmpVal = startPoint<
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_timer.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup TIMER + * @{ + */ + +/** @defgroup TIMER_Private_Macros + * @{ + */ +#define TIMER_MAX_MATCH 3 + +/*@} end of group TIMER_Private_Macros */ + +/** @defgroup TIMER_Private_Types + * @{ + */ + +/*@} end of group TIMER_Private_Types */ + +/** @defgroup TIMER_Private_Variables + * @{ + */ +intCallback_Type * timerIntCbfArra[3][TIMER_INT_ALL]= { +{NULL, NULL, NULL}, +{NULL, NULL, NULL}, +{NULL, NULL, NULL} +}; + +/*@} end of group TIMER_Private_Variables */ + +/** @defgroup TIMER_Global_Variables + * @{ + */ + +/*@} end of group TIMER_Global_Variables */ + +/** @defgroup TIMER_Private_Fun_Declaration + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +static void TIMER_IntHandler(IRQn_Type irqNo, TIMER_Chan_Type timerCh); +#endif + +/*@} end of group TIMER_Private_Fun_Declaration */ + +/** @defgroup TIMER_Private_Functions + * @{ + */ + +/****************************************************************************//** + * @brief TIMER interrupt common handler function + * + * @param irqNo: Interrupt ID type + * @param timerCh: TIMER channel type + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void TIMER_IntHandler(IRQn_Type irqNo, TIMER_Chan_Type timerCh) +{ + uint32_t intId; + uint32_t tmpVal; + uint32_t tmpAddr; + + intId=BL_RD_WORD(TIMER_BASE+TIMER_TMSR2_OFFSET+4*timerCh); + tmpAddr=TIMER_BASE+TIMER_TICR2_OFFSET+4*timerCh; + tmpVal=BL_RD_WORD(tmpAddr); + + /* Comparator 0 match interrupt */ + if( BL_IS_REG_BIT_SET(intId,TIMER_TMSR_0) ){ + BL_WR_WORD(tmpAddr,BL_SET_REG_BIT(tmpVal,TIMER_TCLR_0)); + if(timerIntCbfArra[irqNo-TIMER_CH0_IRQn][TIMER_INT_COMP_0] != NULL){ + /* Call the callback function */ + timerIntCbfArra[irqNo-TIMER_CH0_IRQn][TIMER_INT_COMP_0](); + } + } + + /* Comparator 1 match interrupt */ + if( BL_IS_REG_BIT_SET(intId,TIMER_TMSR_1) ){ + BL_WR_WORD(tmpAddr,BL_SET_REG_BIT(tmpVal,TIMER_TCLR_1)); + if(timerIntCbfArra[irqNo-TIMER_CH0_IRQn][TIMER_INT_COMP_1] != NULL){ + /* Call the callback function */ + timerIntCbfArra[irqNo-TIMER_CH0_IRQn][TIMER_INT_COMP_1](); + } + } + + /* Comparator 2 match interrupt */ + if( BL_IS_REG_BIT_SET(intId,TIMER_TMSR_2) ){ + BL_WR_WORD(tmpAddr,BL_SET_REG_BIT(tmpVal,TIMER_TCLR_2)); + if(timerIntCbfArra[irqNo-TIMER_CH0_IRQn][TIMER_INT_COMP_2] != NULL){ + /* Call the callback function */ + timerIntCbfArra[irqNo-TIMER_CH0_IRQn][TIMER_INT_COMP_2](); + } + } +} +#endif + +/****************************************************************************//** + * @brief Get the specified channel and match comparator value + * + * @param timerCh: TIMER channel type + * @param cmpNo: TIMER comparator ID type + * + * @return Match comapre register value + * +*******************************************************************************/ +uint32_t TIMER_GetCompValue(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo)); + + tmpVal=BL_RD_WORD(TIMER_BASE+TIMER_TMR2_0_OFFSET+4*(TIMER_MAX_MATCH*timerCh+cmpNo)); + return tmpVal; +} + +/****************************************************************************//** + * @brief TIMER set specified channel and comparator compare value + * + * @param timerCh: TIMER channel type + * @param cmpNo: TIMER comparator ID type + * @param val: TIMER match comapre register value + * + * @return None + * +*******************************************************************************/ +void TIMER_SetCompValue(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo, uint32_t val) +{ + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo)); + + BL_WR_WORD(TIMER_BASE+TIMER_TMR2_0_OFFSET+4*(TIMER_MAX_MATCH*timerCh+cmpNo),val); +} + +/****************************************************************************//** + * @brief TIMER get the specified channel count value + * + * @param timerCh: TIMER channel type + * + * @return TIMER count register value + * +*******************************************************************************/ +uint32_t TIMER_GetCounterValue(TIMER_Chan_Type timerCh) +{ + uint32_t tmpVal; + uint32_t tmpAddr; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + + /* TO avoid risk of reading, don't read TCVWR directly*/ + /* request for read*/ + tmpAddr=TIMER_BASE+TIMER_TCVWR2_OFFSET+4*timerCh; + BL_WR_WORD(tmpAddr,1); + + /* Need wait */ + tmpVal=BL_RD_WORD(tmpAddr); + tmpVal=BL_RD_WORD(tmpAddr); + tmpVal=BL_RD_WORD(tmpAddr); + + return tmpVal; +} + +/****************************************************************************//** + * @brief TIMER get specified channel and comparator match status + * + * @param timerCh: TIMER channel type + * @param cmpNo: TIMER comparator ID type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type TIMER_GetMatchStatus(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo) +{ + uint32_t tmpVal; + BL_Sts_Type bitStatus=RESET; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo)); + + tmpVal=BL_RD_WORD(TIMER_BASE+TIMER_TMSR2_OFFSET+4*timerCh); + switch(cmpNo) + { + case TIMER_COMP_ID_0: + bitStatus = BL_IS_REG_BIT_SET(tmpVal,TIMER_TMSR_0) ? SET : RESET; + break; + case TIMER_COMP_ID_1: + bitStatus = BL_IS_REG_BIT_SET(tmpVal,TIMER_TMSR_1) ? SET : RESET; + break; + case TIMER_COMP_ID_2: + bitStatus = BL_IS_REG_BIT_SET(tmpVal,TIMER_TMSR_2) ? SET : RESET; + break; + default: + break; + } + return bitStatus; +} + +/****************************************************************************//** + * @brief TIMER get specified channel preload value + * + * @param timerCh: TIMER channel type + * + * @return Preload register value + * +*******************************************************************************/ +uint32_t TIMER_GetPreloadValue(TIMER_Chan_Type timerCh) +{ + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + + return BL_RD_WORD(TIMER_BASE+TIMER_TPLVR2_OFFSET+4*timerCh); +} + +/****************************************************************************//** + * @brief TIMER set preload register low 32bits value + * + * @param timerCh: TIMER channel type + * @param val: Preload register low 32bits value + * + * @return None + * +*******************************************************************************/ +void TIMER_SetPreloadValue(TIMER_Chan_Type timerCh, uint32_t val) +{ + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + + BL_WR_WORD(TIMER_BASE+TIMER_TPLVR2_OFFSET+4*timerCh,val); +} + +/****************************************************************************//** + * @brief TIMER set preload trigger source,COMP0,COMP1,COMP2 or None + * + * @param timerCh: TIMER channel type + * @param plSrc: TIMER preload source type + * + * @return None + * +*******************************************************************************/ +void TIMER_SetPreloadTrigSrc(TIMER_Chan_Type timerCh, TIMER_PreLoad_Trig_Type plSrc) +{ + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + CHECK_PARAM(IS_TIMER_PRELOAD_TRIG_TYPE(plSrc)); + + BL_WR_WORD(TIMER_BASE+TIMER_TPLCR2_OFFSET+4*timerCh,plSrc); +} + +/****************************************************************************//** + * @brief TIMER set count mode:preload or free run + * + * @param timerCh: TIMER channel type + * @param countMode: TIMER count mode: TIMER_COUNT_PRELOAD or TIMER_COUNT_FREERUN + * + * @return None + * +*******************************************************************************/ +void TIMER_SetCountMode(TIMER_Chan_Type timerCh, TIMER_CountMode_Type countMode) +{ + uint32_t tmpval; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + CHECK_PARAM(IS_TIMER_COUNTMODE_TYPE(countMode)); + + tmpval=BL_RD_WORD(TIMER_BASE+TIMER_TCMR_OFFSET); + tmpval &= (~(1<<(timerCh+1))); + tmpval |= (countMode<<(timerCh+1)); + + BL_WR_WORD(TIMER_BASE+TIMER_TCMR_OFFSET,tmpval); +} + +/****************************************************************************//** + * @brief TIMER clear interrupt status + * + * @param timerCh: TIMER channel type + * @param cmpNo: TIMER macth comparator ID type + * + * @return None + * +*******************************************************************************/ +void TIMER_ClearIntStatus(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo) +{ + uint32_t tmpAddr; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo)); + + tmpAddr=TIMER_BASE+TIMER_TICR2_OFFSET+4*timerCh; + + tmpVal=BL_RD_WORD(tmpAddr); + tmpVal |=(1<timerCh; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CLKSRC_TYPE(timerCfg->clkSrc)); + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCfg->timerCh)); + CHECK_PARAM(IS_TIMER_PRELOAD_TRIG_TYPE(timerCfg->plTrigSrc)); + CHECK_PARAM(IS_TIMER_COUNTMODE_TYPE(timerCfg->countMode)); + + /* Configure timer clock source */ + tmpVal=BL_RD_REG(TIMER_BASE,TIMER_TCCR); + if(timerCh == TIMER_CH0){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TIMER_CS_1,timerCfg->clkSrc); + }else{ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TIMER_CS_2,timerCfg->clkSrc); + } + BL_WR_REG(TIMER_BASE,TIMER_TCCR,tmpVal); + + /* Configure timer clock division */ + tmpVal=BL_RD_REG(TIMER_BASE,TIMER_TCDR); + if(timerCh == TIMER_CH0){ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TIMER_TCDR2,timerCfg->clockDivision); + }else{ + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TIMER_TCDR3,timerCfg->clockDivision); + } + BL_WR_REG(TIMER_BASE,TIMER_TCDR,tmpVal); + + /* Configure timer count mode: preload or free run */ + TIMER_SetCountMode(timerCh,timerCfg->countMode); + + /* Configure timer preload trigger src */ + TIMER_SetPreloadTrigSrc(timerCh,timerCfg->plTrigSrc); + + if(timerCfg->countMode == TIMER_COUNT_PRELOAD){ + /* Configure timer preload value */ + TIMER_SetPreloadValue(timerCh, timerCfg->preLoadVal); + } + + /* Configure match compare values */ + TIMER_SetCompValue(timerCh,TIMER_COMP_ID_0,timerCfg->matchVal0); + TIMER_SetCompValue(timerCh,TIMER_COMP_ID_1,timerCfg->matchVal1); + TIMER_SetCompValue(timerCh,TIMER_COMP_ID_2,timerCfg->matchVal2); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(TIMER_CH0_IRQn,TIMER_CH0_IRQHandler); + Interrupt_Handler_Register(TIMER_CH1_IRQn,TIMER_CH1_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************//** + * @brief TIMER enable one channel function + * + * @param timerCh: TIMER channel type + * + * @return None + * +*******************************************************************************/ +void TIMER_Enable(TIMER_Chan_Type timerCh) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + + tmpVal=BL_RD_REG(TIMER_BASE,TIMER_TCER); + tmpVal |=(1<<(timerCh+1)); + + BL_WR_REG(TIMER_BASE,TIMER_TCER,tmpVal); +} + +/****************************************************************************//** + * @brief TIMER disable one channel function + * + * @param timerCh: TIMER channel type + * + * @return None + * +*******************************************************************************/ +void TIMER_Disable(TIMER_Chan_Type timerCh) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + + tmpVal=BL_RD_REG(TIMER_BASE,TIMER_TCER); + tmpVal &= (~(1<<(timerCh+1))); + + BL_WR_REG(TIMER_BASE,TIMER_TCER,tmpVal); +} + +/****************************************************************************//** + * @brief TIMER mask or unmask certain or all interrupt + * + * @param timerCh: TIMER channel type + * @param intType: TIMER interrupt type + * @param intMask: TIMER interrupt mask value:MASK:disbale interrupt.UNMASK:enable interrupt + * + * @return None + * +*******************************************************************************/ +void TIMER_IntMask(TIMER_Chan_Type timerCh,TIMER_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpAddr; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); + CHECK_PARAM(IS_TIMER_INT_TYPE(intType)); + CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); + + tmpAddr=TIMER_BASE+TIMER_TIER2_OFFSET+4*timerCh; + tmpVal=BL_RD_WORD(tmpAddr); + + switch(intType) + { + case TIMER_INT_COMP_0: + if(intMask == UNMASK){ + /* Enable this interrupt */ + BL_WR_WORD(tmpAddr,BL_SET_REG_BIT(tmpVal,TIMER_TIER_0)); + }else{ + /* Disable this interrupt */ + BL_WR_WORD(tmpAddr,BL_CLR_REG_BIT(tmpVal,TIMER_TIER_0)); + } + break; + + case TIMER_INT_COMP_1: + if(intMask == UNMASK){ + /* Enable this interrupt */ + BL_WR_WORD(tmpAddr,BL_SET_REG_BIT(tmpVal,TIMER_TIER_1)); + }else{ + /* Disable this interrupt */ + BL_WR_WORD(tmpAddr,BL_CLR_REG_BIT(tmpVal,TIMER_TIER_1)); + } + break; + + case TIMER_INT_COMP_2: + if(intMask == UNMASK){ + /* Enable this interrupt */ + BL_WR_WORD(tmpAddr,BL_SET_REG_BIT(tmpVal,TIMER_TIER_2)); + }else{ + /* Disable this interrupt */ + BL_WR_WORD(tmpAddr,BL_CLR_REG_BIT(tmpVal,TIMER_TIER_2)); + } + break; + + case TIMER_INT_ALL: + if(intMask == UNMASK){ + /* Enable this interrupt */ + BL_WR_WORD(tmpAddr,BL_SET_REG_BIT(tmpVal,TIMER_TIER_0)); + BL_WR_WORD(tmpAddr,BL_SET_REG_BIT(tmpVal,TIMER_TIER_1)); + BL_WR_WORD(tmpAddr,BL_SET_REG_BIT(tmpVal,TIMER_TIER_2)); + }else{ + /* Disable this interrupt */ + BL_WR_WORD(tmpAddr,BL_CLR_REG_BIT(tmpVal,TIMER_TIER_0)); + BL_WR_WORD(tmpAddr,BL_CLR_REG_BIT(tmpVal,TIMER_TIER_1)); + BL_WR_WORD(tmpAddr,BL_CLR_REG_BIT(tmpVal,TIMER_TIER_2)); + } + break; + + default: + break; + } +} + +/****************************************************************************//** + * @brief TIMER set watchdog clock source and clock division + * + * @param clkSrc: Watchdog timer clock source type + * @param div: Watchdog timer clock division value + * + * @return None + * +*******************************************************************************/ +void WDT_Set_Clock(TIMER_ClkSrc_Type clkSrc,uint8_t div) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CLKSRC_TYPE(clkSrc)); + + /* Configure watchdog timer clock source */ + tmpVal=BL_RD_REG(TIMER_BASE,TIMER_TCCR); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TIMER_CS_WDT,clkSrc); + BL_WR_REG(TIMER_BASE,TIMER_TCCR,tmpVal); + + /* Configure watchdog timer clock divison */ + tmpVal=BL_RD_REG(TIMER_BASE,TIMER_TCDR); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TIMER_WCDR,div); + BL_WR_REG(TIMER_BASE,TIMER_TCDR,tmpVal); +} + +/****************************************************************************//** + * @brief TIMER get watchdog match compare value + * + * @param None + * + * @return Watchdog match comapre register value + * +*******************************************************************************/ +uint16_t WDT_GetMatchValue(void) +{ + uint32_t tmpVal; + + WDT_ENABLE_ACCESS(); + + /* Get watchdog timer match register value */ + tmpVal=BL_RD_REG(TIMER_BASE,TIMER_WMR); + + return tmpVal; +} + +/****************************************************************************//** + * @brief TIMER set watchdog match compare value + * + * @param val: Watchdog match compare value + * + * @return None + * +*******************************************************************************/ +void WDT_SetCompValue(uint16_t val) +{ + WDT_ENABLE_ACCESS(); + + /* Set watchdog timer match register value */ + BL_WR_REG(TIMER_BASE,TIMER_WMR,val); +} + +/****************************************************************************//** + * @brief TIMER get watchdog count register value + * + * @param None + * + * @return Watchdog count register value + * +*******************************************************************************/ +uint16_t WDT_GetCounterValue(void) +{ + uint32_t tmpVal; + + WDT_ENABLE_ACCESS(); + + /* Get watchdog timer count register value */ + tmpVal=BL_RD_REG(TIMER_BASE,TIMER_WVR); + + return tmpVal; +} + +/****************************************************************************//** + * @brief TIMER reset watchdog count register value + * + * @param None + * + * @return None + * +*******************************************************************************/ +void WDT_ResetCounterValue(void) +{ + uint32_t tmpVal; + + /* Reset watchdog timer count register value */ + WDT_ENABLE_ACCESS(); + + tmpVal=BL_RD_REG(TIMER_BASE,TIMER_WCR); + + /* Set watchdog counter reset register bit0 to 1 */ + BL_WR_REG(TIMER_BASE,TIMER_WCR,BL_SET_REG_BIT(tmpVal,TIMER_WCR)); +} + +/****************************************************************************//** + * @brief TIMER get watchdog reset status + * + * @param None + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type WDT_GetResetStatus(void) +{ + uint32_t tmpVal; + + WDT_ENABLE_ACCESS(); + + /* Get watchdog status register */ + tmpVal=BL_RD_REG(TIMER_BASE,TIMER_WSR); + + return (BL_IS_REG_BIT_SET(tmpVal,TIMER_WTS)) ? SET : RESET; +} + +/****************************************************************************//** + * @brief TIMER clear watchdog reset status + * + * @param None + * + * @return None + * +*******************************************************************************/ +void WDT_ClearResetStatus(void) +{ + uint32_t tmpVal; + + WDT_ENABLE_ACCESS(); + + tmpVal=BL_RD_REG(TIMER_BASE,TIMER_WSR); + + /* Set watchdog status register */ + BL_WR_REG(TIMER_BASE,TIMER_WSR,BL_CLR_REG_BIT(tmpVal,TIMER_WTS)); +} + +/****************************************************************************//** + * @brief TIMER enable watchdog function + * + * @param None + * + * @return None + * +*******************************************************************************/ +void WDT_Enable(void) +{ + uint32_t tmpVal; + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(TIMER_WDT_IRQn,TIMER_WDT_IRQHandler); +#endif + + WDT_ENABLE_ACCESS(); + + tmpVal=BL_RD_REG(TIMER_BASE,TIMER_WMER); + + BL_WR_REG(TIMER_BASE,TIMER_WMER,BL_SET_REG_BIT(tmpVal,TIMER_WE)); +} + +/****************************************************************************//** + * @brief Watchdog timer disable function + * + * @param None + * + * @return None + * +*******************************************************************************/ +void WDT_Disable(void) +{ + uint32_t tmpVal; + + WDT_ENABLE_ACCESS(); + + tmpVal=BL_RD_REG(TIMER_BASE,TIMER_WMER); + + BL_WR_REG(TIMER_BASE,TIMER_WMER,BL_CLR_REG_BIT(tmpVal,TIMER_WE)); +} + +/****************************************************************************//** + * @brief Watchdog timer mask or unmask certain or all interrupt + * + * @param intType: Watchdog interrupt type + * @param intMask: Watchdog interrupt mask value:MASK:disbale interrupt.UNMASK:enable interrupt + * + * @return None + * +*******************************************************************************/ +void WDT_IntMask(WDT_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_WDT_INT_TYPE(intType)); + CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); + + WDT_ENABLE_ACCESS(); + + /* Deal with watchdog match/interrupt enable register, + WRIE:watchdog reset/interrupt enable */ + tmpVal=BL_RD_REG(TIMER_BASE,TIMER_WMER); + + switch(intType) + { + case WDT_INT: + if(intMask == UNMASK){ + /* Enable this interrupt */ + /* 0 means generates a watchdog interrupt, + a watchdog timer reset is not generated*/ + BL_WR_REG(TIMER_BASE,TIMER_WMER,BL_CLR_REG_BIT(tmpVal,TIMER_WRIE)); + }else { + /* Disable this interrupt */ + /* 1 means generates a watchdog timer reset, + a watchdog interrupt is not generated*/ + BL_WR_REG(TIMER_BASE,TIMER_WMER,BL_SET_REG_BIT(tmpVal,TIMER_WRIE)); + } + break; + default: + break; + } +} + +/****************************************************************************//** + * @brief TIMER channel 0 interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void TIMER_CH0_IRQHandler(void) +{ + TIMER_IntHandler(TIMER_CH0_IRQn,TIMER_CH0); +} +#endif + +/****************************************************************************//** + * @brief TIMER channel 1 interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void TIMER_CH1_IRQHandler(void) +{ + TIMER_IntHandler(TIMER_CH1_IRQn,TIMER_CH1); +} +#endif + +/****************************************************************************//** + * @brief TIMER watchdog interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void TIMER_WDT_IRQHandler(void) +{ + uint32_t tmpVal; + + WDT_ENABLE_ACCESS(); + + tmpVal=BL_RD_REG(TIMER_BASE,TIMER_WICR); + BL_WR_REG(TIMER_BASE,TIMER_WICR,BL_SET_REG_BIT(tmpVal,TIMER_WICLR)); + + if(timerIntCbfArra[TIMER_WDT_IRQn-TIMER_CH0_IRQn][WDT_INT] != NULL){ + /* Call the callback function */ + timerIntCbfArra[TIMER_WDT_IRQn-TIMER_CH0_IRQn][WDT_INT](); + } +} +#endif + +/****************************************************************************//** + * @brief TIMER install interrupt callback + * + * @param timerChan: TIMER channel type + * @param intType: TIMER interrupt type + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return None + * +*******************************************************************************/ +void Timer_Int_Callback_Install(TIMER_Chan_Type timerChan,TIMER_INT_Type intType,intCallback_Type* cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerChan)); + CHECK_PARAM(IS_TIMER_INT_TYPE(intType)); + + timerIntCbfArra[timerChan][intType] = cbFun; +} + +/****************************************************************************//** + * @brief Watchdog install interrupt callback + * + * @param wdtInt: Watchdog interrupt type + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return None + * +*******************************************************************************/ +void WDT_Int_Callback_Install(WDT_INT_Type wdtInt,intCallback_Type* cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_WDT_INT_TYPE(wdtInt)); + + timerIntCbfArra[2][wdtInt] = cbFun; +} + +/*@} end of group TIMER_Private_Functions */ + +/*@} end of group TIMER */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/bl602_driver/std_drv/src/bl602_tzc_sec.c b/drivers/bl602_driver/std_drv/src/bl602_tzc_sec.c new file mode 100644 index 00000000..49baa566 --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_tzc_sec.c @@ -0,0 +1,242 @@ +/** + ****************************************************************************** + * @file bl602_tzc_sec.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "string.h" +#include "bl602_tzc_sec.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup TZC_SEC + * @{ + */ + +/** @defgroup TZC_SEC_Private_Macros + * @{ + */ + +/*@} end of group TZC_SEC_Private_Macros */ + +/** @defgroup TZC_SEC_Private_Types + * @{ + */ + +/*@} end of group TZC_SEC_Private_Types */ + +/** @defgroup TZC_SEC_Private_Variables + * @{ + */ + +/*@} end of group TZC_SEC_Private_Variables */ + +/** @defgroup TZC_SEC_Global_Variables + * @{ + */ + +/*@} end of group TZC_SEC_Global_Variables */ + +/** @defgroup TZC_SEC_Private_Fun_Declaration + * @{ + */ + +/*@} end of group TZC_SEC_Private_Fun_Declaration */ + +/** @defgroup TZC_SEC_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief TZC Security boot set + * + * @param Val: 0 for security boot start, and 0xf for security boot finished + * + * @return None + * +*******************************************************************************/ +void TZC_Sboot_Set(uint8_t Val) +{ + uint32_t tmpVal; + + tmpVal=BL_RD_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM_CTRL); + + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_SBOOT_DONE,Val); + + BL_WR_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM_CTRL,tmpVal); +} + + +/****************************************************************************//** + * @brief TZC Set ROM0 R0 protect range + * + * @param start: Start address to protect + * @param end: End address to protect + * + * @return None + * +*******************************************************************************/ +void TZC_Set_Rom0_R0_Protect(uint32_t start,uint32_t end) +{ + uint32_t tmpVal; + + /* Set Range */ + tmpVal=BL_RD_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM0_R0); + + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R0_START,start>>10); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R0_END,end>>10); + + BL_WR_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM0_R0,tmpVal); + + + /* Enable */ + tmpVal=BL_RD_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM_CTRL); + + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R0_ID0_EN,0); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R0_ID1_EN,0); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R0_EN,1); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R0_LOCK,1); + + BL_WR_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM_CTRL,tmpVal); +} + + +/****************************************************************************//** + * @brief TZC Set ROM0 R1 protect range + * + * @param start: Start address to protect + * @param end: End address to protect + * + * @return None + * +*******************************************************************************/ +void TZC_Set_Rom0_R1_Protect(uint32_t start,uint32_t end) +{ + uint32_t tmpVal; + + /* Set Range */ + tmpVal=BL_RD_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM0_R1); + + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R1_START,start>>10); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R1_END,end>>10); + + BL_WR_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM0_R1,tmpVal); + + + /* Enable */ + tmpVal=BL_RD_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM_CTRL); + + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R1_ID0_EN,0); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R1_ID1_EN,0); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R1_EN,1); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R1_LOCK,1); + + BL_WR_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM_CTRL,tmpVal); +} + + +/****************************************************************************//** + * @brief TZC Set ROM1 R0 protect range + * + * @param start: Start address to protect + * @param end: End address to protect + * + * @return None + * +*******************************************************************************/ +void TZC_Set_Rom1_R0_Protect(uint32_t start,uint32_t end) +{ + uint32_t tmpVal; + + /* Set Range */ + tmpVal=BL_RD_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM1_R0); + + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R0_START,start>>10); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R0_END,end>>10); + + BL_WR_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM1_R0,tmpVal); + + + /* Enable */ + tmpVal=BL_RD_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM_CTRL); + + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R0_ID0_EN,0); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R0_ID1_EN,0); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R0_EN,1); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R0_LOCK,1); + + BL_WR_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM_CTRL,tmpVal); +} + + +/****************************************************************************//** + * @brief TZC Set ROM1 R1 protect range + * + * @param start: Start address to protect + * @param end: End address to protect + * + * @return None + * +*******************************************************************************/ +void TZC_Set_Rom1_R1_Protect(uint32_t start,uint32_t end) +{ + uint32_t tmpVal; + + /* Set Range */ + tmpVal=BL_RD_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM1_R1); + + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R1_START,start>>10); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R1_END,end>>10); + + BL_WR_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM1_R1,tmpVal); + + + /* Enable */ + tmpVal=BL_RD_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM_CTRL); + + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R1_ID0_EN,0); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R1_ID1_EN,0); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R1_EN,1); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R1_LOCK,1); + + BL_WR_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM_CTRL,tmpVal); +} + + +/*@} end of group TZC_SEC_Public_Functions */ + +/*@} end of group TZC_SEC */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/bl602_driver/std_drv/src/bl602_uart.c b/drivers/bl602_driver/std_drv/src/bl602_uart.c new file mode 100644 index 00000000..030fb98a --- /dev/null +++ b/drivers/bl602_driver/std_drv/src/bl602_uart.c @@ -0,0 +1,1210 @@ +/** + ****************************************************************************** + * @file bl602_uart.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_uart.h" +#include "bl602_glb.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/** @defgroup UART_Private_Macros + * @{ + */ +#define UART_TX_TIMEOUT_COUNT (160*1000) + +/*@} end of group UART_Private_Macros */ + +/** @defgroup UART_Private_Types + * @{ + */ + +/*@} end of group UART_Private_Types */ + +/** @defgroup UART_Private_Variables + * @{ + */ +static const uint32_t uartAddr[2] = {UART0_BASE,UART1_BASE}; +static intCallback_Type * uartIntCbfArra[2][UART_INT_ALL]= { + {NULL},{NULL} +}; + + +/*@} end of group UART_Private_Variables */ + +/** @defgroup UART_Global_Variables + * @{ + */ + +/*@} end of group UART_Global_Variables */ + +/** @defgroup UART_Private_Fun_Declaration + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +static void UART_IntHandler(UART_ID_Type uartId); +#endif + +/*@} end of group UART_Private_Fun_Declaration */ + +/** @defgroup UART_Private_Functions + * @{ + */ + +/****************************************************************************//** + * @brief UART interrupt common handler function + * + * @param uartId: UART ID type + * + * @return None + * +*******************************************************************************/ +#if 1//#ifndef BFLB_USE_HAL_DRIVER +static void UART_IntHandler(UART_ID_Type uartId) +{ + uint32_t tmpVal = 0; + uint32_t maskVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + tmpVal = BL_RD_REG(UARTx,UART_INT_STS); + maskVal = BL_RD_REG(UARTx,UART_INT_MASK); + + /* Length of uart tx data transfer arrived interrupt */ + if(BL_IS_REG_BIT_SET(tmpVal,UART_UTX_END_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_UTX_END_MASK)){ + BL_WR_REG(UARTx,UART_INT_CLEAR,0x1); + if(uartIntCbfArra[uartId][UART_INT_TX_END] != NULL){ + uartIntCbfArra[uartId][UART_INT_TX_END](); + } + } + + /* Length of uart rx data transfer arrived interrupt */ + if(BL_IS_REG_BIT_SET(tmpVal,UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_URX_END_MASK)){ + BL_WR_REG(UARTx,UART_INT_CLEAR,0x2); + if(uartIntCbfArra[uartId][UART_INT_RX_END] != NULL){ + uartIntCbfArra[uartId][UART_INT_RX_END](); + } + } + + /* Tx fifo ready interrupt,auto-cleared when data is pushed */ + if(BL_IS_REG_BIT_SET(tmpVal,UART_UTX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_UTX_FIFO_MASK)){ + if(uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ] != NULL){ + uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ](); + } + } + + /* Rx fifo ready interrupt,auto-cleared when data is popped */ + if(BL_IS_REG_BIT_SET(tmpVal,UART_URX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_URX_FIFO_MASK)){ + if(uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ] != NULL){ + uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ](); + } + } + + /* Rx time-out interrupt */ + if(BL_IS_REG_BIT_SET(tmpVal,UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_URX_RTO_MASK)){ + BL_WR_REG(UARTx,UART_INT_CLEAR,0x10); + if(uartIntCbfArra[uartId][UART_INT_RTO] != NULL){ + uartIntCbfArra[uartId][UART_INT_RTO](); + } + } + + /* Rx parity check error interrupt */ + if(BL_IS_REG_BIT_SET(tmpVal,UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_URX_PCE_MASK)){ + BL_WR_REG(UARTx,UART_INT_CLEAR,0x20); + if(uartIntCbfArra[uartId][UART_INT_PCE] != NULL){ + uartIntCbfArra[uartId][UART_INT_PCE](); + } + } + + /* Tx fifo overflow/underflow error interrupt */ + if(BL_IS_REG_BIT_SET(tmpVal,UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_UTX_FER_MASK)){ + if(uartIntCbfArra[uartId][UART_INT_TX_FER] != NULL){ + uartIntCbfArra[uartId][UART_INT_TX_FER](); + } + } + + /* Rx fifo overflow/underflow error interrupt */ + if(BL_IS_REG_BIT_SET(tmpVal,UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_URX_FER_MASK)){ + if(uartIntCbfArra[uartId][UART_INT_RX_FER] != NULL){ + uartIntCbfArra[uartId][UART_INT_RX_FER](); + } + } +} +#endif + + +/*@} end of group UART_Private_Functions */ + +/** @defgroup UART_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief UART initialization function + * + * @param uartId: UART ID type + * @param uartCfg: UART configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_Init(UART_ID_Type uartId,UART_CFG_Type* uartCfg) +{ + uint32_t tmpValTxCfg = 0; + uint32_t tmpValRxCfg = 0; + uint32_t fraction = 0; + uint32_t baudRateDivisor = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_PARITY_TYPE(uartCfg->parity)); + CHECK_PARAM(IS_UART_DATABITS_TYPE(uartCfg->dataBits)); + CHECK_PARAM(IS_UART_STOPBITS_TYPE(uartCfg->stopBits)); + CHECK_PARAM(IS_UART_BYTEBITINVERSE_TYPE(uartCfg->byteBitInverse)); + + /* Cal the baud rate divisor */ + fraction = uartCfg->uartClk * 10 / uartCfg->baudRate % 10; + baudRateDivisor = uartCfg->uartClk / uartCfg->baudRate; + if(fraction >= 5){ + ++baudRateDivisor; + } + + /* Set the baud rate register value */ + BL_WR_REG(UARTx,UART_BIT_PRD,((baudRateDivisor-1)<<0x10)|((baudRateDivisor-1)&0xFFFF)); + + /* Configure parity type */ + tmpValTxCfg = BL_RD_REG(UARTx,UART_UTX_CONFIG); + tmpValRxCfg = BL_RD_REG(UARTx,UART_URX_CONFIG); + switch(uartCfg->parity) + { + case UART_PARITY_NONE: + tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg,UART_CR_UTX_PRT_EN); + tmpValRxCfg = BL_CLR_REG_BIT(tmpValRxCfg,UART_CR_URX_PRT_EN); + break; + case UART_PARITY_ODD: + tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg,UART_CR_UTX_PRT_EN); + tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg,UART_CR_UTX_PRT_SEL); + tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg,UART_CR_URX_PRT_EN); + tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg,UART_CR_URX_PRT_SEL); + break; + case UART_PARITY_EVEN: + tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg,UART_CR_UTX_PRT_EN); + tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg,UART_CR_UTX_PRT_SEL); + tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg,UART_CR_URX_PRT_EN); + tmpValRxCfg = BL_CLR_REG_BIT(tmpValRxCfg,UART_CR_URX_PRT_SEL); + break; + default: + break; + } + + /* Configure data bits */ + tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg,UART_CR_UTX_BIT_CNT_D,(uartCfg->dataBits+4)); + tmpValRxCfg = BL_SET_REG_BITS_VAL(tmpValRxCfg,UART_CR_URX_BIT_CNT_D,(uartCfg->dataBits+4)); + + /* Configure tx stop bits */ + tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg,UART_CR_UTX_BIT_CNT_P,(uartCfg->stopBits+1)); + + /* Configure tx cts flow control function */ + if(ENABLE == uartCfg->ctsFlowControl){ + tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg,UART_CR_UTX_CTS_EN); + }else{ + tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg,UART_CR_UTX_CTS_EN); + } + + /* Configure rx input de-glitch function */ + if(ENABLE == uartCfg->rxDeglitch){ + tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg,UART_CR_URX_DEG_EN); + }else{ + tmpValRxCfg = BL_CLR_REG_BIT(tmpValRxCfg,UART_CR_URX_DEG_EN); + } + + /* Configure rx rts output SW control mode */ + if(ENABLE == uartCfg->rtsSoftwareControl){ + tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg,UART_CR_URX_RTS_SW_MODE); + }else{ + tmpValRxCfg = BL_CLR_REG_BIT(tmpValRxCfg,UART_CR_URX_RTS_SW_MODE); + } + + /* Write back */ + BL_WR_REG(UARTx,UART_UTX_CONFIG,tmpValTxCfg); + BL_WR_REG(UARTx,UART_URX_CONFIG,tmpValRxCfg); + + /* Configure LSB-first or MSB-first */ + tmpValTxCfg = BL_RD_REG(UARTx,UART_DATA_CONFIG); + if(UART_MSB_FIRST == uartCfg->byteBitInverse){ + tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg,UART_CR_UART_BIT_INV); + }else{ + tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg,UART_CR_UART_BIT_INV); + } + BL_WR_REG(UARTx,UART_DATA_CONFIG,tmpValTxCfg); + +#if 1//#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(UART0_IRQn,UART0_IRQHandler); + Interrupt_Handler_Register(UART1_IRQn,UART1_IRQHandler); +#endif + return SUCCESS; +} + +/****************************************************************************//** + * @brief UART set default value of all registers function + * + * @param uartId: UART ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_DeInit(UART_ID_Type uartId) +{ + if(UART0_ID==uartId){ + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART0); + }else if(UART1_ID==uartId){ + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART1); + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief UART configure fifo function + * + * @param uartId: UART ID type + * @param fifoCfg: FIFO configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_FifoConfig(UART_ID_Type uartId,UART_FifoCfg_Type* fifoCfg) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Deal with uart fifo configure register */ + tmpVal = BL_RD_REG(UARTx,UART_FIFO_CONFIG_1); + /* Configure dma tx fifo threshold */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,UART_TX_FIFO_TH,fifoCfg->txFifoDmaThreshold-1); + /* Configure dma rx fifo threshold */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,UART_RX_FIFO_TH,fifoCfg->rxFifoDmaThreshold-1); + /* Write back */ + BL_WR_REG(UARTx,UART_FIFO_CONFIG_1,tmpVal); + + /* Enable or disable uart fifo dma function */ + tmpVal = BL_RD_REG(UARTx,UART_FIFO_CONFIG_0); + if(ENABLE == fifoCfg->txFifoDmaEnable){ + tmpVal = BL_SET_REG_BIT(tmpVal,UART_DMA_TX_EN); + }else{ + tmpVal = BL_CLR_REG_BIT(tmpVal,UART_DMA_TX_EN); + } + if(ENABLE == fifoCfg->rxFifoDmaEnable){ + tmpVal = BL_SET_REG_BIT(tmpVal,UART_DMA_RX_EN); + }else{ + tmpVal = BL_CLR_REG_BIT(tmpVal,UART_DMA_RX_EN); + } + BL_WR_REG(UARTx,UART_FIFO_CONFIG_0,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief UART configure infra function + * + * @param uartId: UART ID type + * @param irCfg: IR configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_IrConfig(UART_ID_Type uartId, UART_IrCfg_Type* irCfg) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Configure tx ir mode */ + tmpVal = BL_RD_REG(UARTx,UART_UTX_CONFIG); + if(ENABLE == irCfg->txIrEnable){ + tmpVal = BL_SET_REG_BIT(tmpVal,UART_CR_UTX_IR_EN); + }else{ + tmpVal = BL_CLR_REG_BIT(tmpVal,UART_CR_UTX_IR_EN); + } + if(ENABLE == irCfg->txIrInverse){ + tmpVal = BL_SET_REG_BIT(tmpVal,UART_CR_UTX_IR_INV); + }else{ + tmpVal = BL_CLR_REG_BIT(tmpVal,UART_CR_UTX_IR_INV); + } + BL_WR_REG(UARTx,UART_UTX_CONFIG,tmpVal); + + /* Configure rx ir mode */ + tmpVal = BL_RD_REG(UARTx,UART_URX_CONFIG); + if(ENABLE == irCfg->rxIrEnable){ + tmpVal = BL_SET_REG_BIT(tmpVal,UART_CR_URX_IR_EN); + }else{ + tmpVal = BL_CLR_REG_BIT(tmpVal,UART_CR_URX_IR_EN); + } + if(ENABLE == irCfg->rxIrInverse){ + tmpVal = BL_SET_REG_BIT(tmpVal,UART_CR_URX_IR_INV); + }else{ + tmpVal = BL_CLR_REG_BIT(tmpVal,UART_CR_URX_IR_INV); + } + BL_WR_REG(UARTx,UART_URX_CONFIG,tmpVal); + + /* Configure tx ir pulse start and stop position */ + BL_WR_REG(UARTx,UART_UTX_IR_POSITION,irCfg->txIrPulseStop<<0x10|irCfg->txIrPulseStart); + + /* Configure rx ir pulse start position */ + BL_WR_REG(UARTx,UART_URX_IR_POSITION,irCfg->rxIrPulseStart); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Enable UART + * + * @param uartId: UART ID type + * @param direct: UART direction type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_Enable(UART_ID_Type uartId,UART_Direction_Type direct) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_DIRECTION_TYPE(direct)); + + if(direct == UART_TX || direct == UART_TXRX){ + /* Enable UART tx unit */ + tmpVal = BL_RD_REG(UARTx,UART_UTX_CONFIG); + BL_WR_REG(UARTx,UART_UTX_CONFIG,BL_SET_REG_BIT(tmpVal,UART_CR_UTX_EN)); + } + + if(direct == UART_RX || direct == UART_TXRX){ + /* Enable UART rx unit */ + tmpVal = BL_RD_REG(UARTx,UART_URX_CONFIG); + BL_WR_REG(UARTx,UART_URX_CONFIG,BL_SET_REG_BIT(tmpVal,UART_CR_URX_EN)); + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Disable UART + * + * @param uartId: UART ID type + * @param direct: UART direction type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_Disable(UART_ID_Type uartId,UART_Direction_Type direct) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_DIRECTION_TYPE(direct)); + + if(direct == UART_TX || direct == UART_TXRX){ + /* Disable UART tx unit */ + tmpVal = BL_RD_REG(UARTx,UART_UTX_CONFIG); + BL_WR_REG(UARTx,UART_UTX_CONFIG,BL_CLR_REG_BIT(tmpVal,UART_CR_UTX_EN)); + } + + if(direct == UART_RX || direct == UART_TXRX){ + /* Disable UART rx unit */ + tmpVal = BL_RD_REG(UARTx,UART_URX_CONFIG); + BL_WR_REG(UARTx,UART_URX_CONFIG,BL_CLR_REG_BIT(tmpVal,UART_CR_URX_EN)); + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief UART set length of tx data transfer,tx end interrupt will assert when this length is + * reached + * + * @param uartId: UART ID type + * @param length: Length of data (unit:character/byte) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId,uint16_t length) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Set length */ + tmpVal = BL_RD_REG(UARTx,UART_UTX_CONFIG); + BL_WR_REG(UARTx,UART_UTX_CONFIG,BL_SET_REG_BITS_VAL(tmpVal,UART_CR_UTX_LEN,length-1)); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief UART set length of rx data transfer,rx end interrupt will assert when this length is + * reached + * + * @param uartId: UART ID type + * @param length: Length of data (unit:character/byte) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId,uint16_t length) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Set length */ + tmpVal = BL_RD_REG(UARTx,UART_URX_CONFIG); + BL_WR_REG(UARTx,UART_URX_CONFIG,BL_SET_REG_BITS_VAL(tmpVal,UART_CR_URX_LEN,length-1)); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief UART set rx time-out value for triggering RTO interrupt + * + * @param uartId: UART ID type + * @param time: Time-out value (unit:bit time) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId,uint8_t time) +{ + uint32_t UARTx = uartAddr[uartId]; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Set time-out value */ + tmpVal = BL_RD_REG(UARTx,UART_URX_RTO_TIMER); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,UART_CR_URX_RTO_VALUE,time-1); + BL_WR_REG(UARTx,UART_URX_RTO_TIMER,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief UART set de-glitch function cycle count value + * + * @param uartId: UART ID type + * @param deglitchCnt: De-glitch function cycle count + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId,uint8_t deglitchCnt) +{ + uint32_t UARTx = uartAddr[uartId]; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Set count value */ + tmpVal = BL_RD_REG(UARTx,UART_URX_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal,UART_CR_URX_DEG_CNT,deglitchCnt-1); + BL_WR_REG(UARTx,UART_URX_CONFIG,tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief UART set tx and rx baudrate according to auto baudrate detection value + * + * @param uartId: UART ID type + * @param autoBaudDet: Choose detection value using codeword 0x55 or start bit + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SetBaudrate(UART_ID_Type uartId,UART_AutoBaudDetection_Type autoBaudDet) +{ + uint32_t UARTx = uartAddr[uartId]; + uint16_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Get detection value */ + tmpVal = UART_GetAutoBaudCount(uartId,autoBaudDet); + + /* Set tx baudrate */ + BL_WR_REG(UARTx,UART_BIT_PRD,tmpVal<<0x10 | tmpVal); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief UART set rx rts output software control value + * + * @param uartId: UART ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId) +{ + uint32_t UARTx = uartAddr[uartId]; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Rts set 1*/ + tmpVal = BL_RD_REG(UARTx,UART_URX_CONFIG); + BL_WR_REG(UARTx,UART_URX_CONFIG,BL_SET_REG_BIT(tmpVal,UART_CR_URX_RTS_SW_VAL)); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief UART clear rx rts output software control value + * + * @param uartId: UART ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId) +{ + uint32_t UARTx = uartAddr[uartId]; + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Rts clear 0 */ + tmpVal = BL_RD_REG(UARTx,UART_URX_CONFIG); + BL_WR_REG(UARTx,UART_URX_CONFIG,BL_CLR_REG_BIT(tmpVal,UART_CR_URX_RTS_SW_VAL)); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief UART configure tx free run mode function + * + * @param uartId: UART ID type + * @param txFreeRun: Enable or disable tx free run mode + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId,BL_Fun_Type txFreeRun) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Enable or disable tx free run mode */ + tmpVal = BL_RD_REG(UARTx,UART_UTX_CONFIG); + if(ENABLE == txFreeRun){ + BL_WR_REG(UARTx,UART_UTX_CONFIG,BL_SET_REG_BIT(tmpVal,UART_CR_UTX_FRM_EN)); + }else{ + BL_WR_REG(UARTx,UART_UTX_CONFIG,BL_CLR_REG_BIT(tmpVal,UART_CR_UTX_FRM_EN)); + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief UART configure auto baud rate detection function + * + * @param uartId: UART ID type + * @param autoBaud: Enable or disable auto function + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_AutoBaudDetection(UART_ID_Type uartId,BL_Fun_Type autoBaud) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Enable or disable auto baud rate detection function */ + tmpVal = BL_RD_REG(UARTx,UART_URX_CONFIG); + if(ENABLE == autoBaud){ + BL_WR_REG(UARTx,UART_URX_CONFIG,BL_SET_REG_BIT(tmpVal,UART_CR_URX_ABR_EN)); + }else{ + BL_WR_REG(UARTx,UART_URX_CONFIG,BL_CLR_REG_BIT(tmpVal,UART_CR_URX_ABR_EN)); + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief UART tx fifo clear + * + * @param uartId: UART ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_TxFifoClear(UART_ID_Type uartId) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameter */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Clear tx fifo */ + tmpVal = BL_RD_REG(UARTx,UART_FIFO_CONFIG_0); + BL_WR_REG(UARTx,UART_FIFO_CONFIG_0,BL_SET_REG_BIT(tmpVal,UART_TX_FIFO_CLR)); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief UART rx fifo clear + * + * @param uartId: UART ID type + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_RxFifoClear(UART_ID_Type uartId) +{ + uint32_t tmpVal = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameter */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Clear rx fifo */ + tmpVal = BL_RD_REG(UARTx,UART_FIFO_CONFIG_0); + BL_WR_REG(UARTx,UART_FIFO_CONFIG_0,BL_SET_REG_BIT(tmpVal,UART_RX_FIFO_CLR)); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief UART mask or unmask certain or all interrupt + * + * @param uartId: UART ID type + * @param intType: UART interrupt type + * @param intMask: UART interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt ) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_IntMask(UART_ID_Type uartId,UART_INT_Type intType,BL_Mask_Type intMask) +{ + uint32_t tmpVal; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_INT_TYPE(intType)); + CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); + + tmpVal = BL_RD_REG(UARTx,UART_INT_MASK); + + /* Mask or unmask certain or all interrupt */ + if(UART_INT_ALL == intType){ + if(MASK == intMask){ + tmpVal |= 0xff; + }else{ + tmpVal &= 0; + } + }else{ + if(MASK == intMask){ + tmpVal |= 1<0){ + BL_WR_BYTE(UARTx+UART_FIFO_WDATA_OFFSET,data[txLen++]); + timeoutCnt = UART_TX_TIMEOUT_COUNT; + }else{ + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + } + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief UART send data to tx fifo in block mode + * + * @param uartId: UART ID type + * @param data: The data to be send + * @param len: The length of the send buffer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId, uint8_t* data,uint32_t len) +{ + uint32_t txLen = 0; + uint32_t UARTx = uartAddr[uartId]; + uint32_t timeoutCnt = UART_TX_TIMEOUT_COUNT; + + /* Check the parameter */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Send data */ + while(txLen0){ + BL_WR_BYTE(UARTx+UART_FIFO_WDATA_OFFSET,data[txLen++]); + timeoutCnt = UART_TX_TIMEOUT_COUNT; + }else{ + timeoutCnt--; + if(timeoutCnt == 0){ + return TIMEOUT; + } + } + } + + while(UART_GetTxBusBusyStatus(uartId) == SET){} + + return SUCCESS; +} + +/****************************************************************************//** + * @brief UART receive data from rx fifo + * + * @param uartId: UART ID type + * @param data: The receive data buffer + * @param maxLen: The max length of the buffer + * + * @return The length of the received buffer + * +*******************************************************************************/ +uint32_t UART_ReceiveData(UART_ID_Type uartId,uint8_t* data,uint32_t maxLen) +{ + uint32_t rxLen = 0; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameter */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + /* Receive data */ + while(rxLen0){ + data[rxLen++] = BL_RD_BYTE(UARTx+UART_FIFO_RDATA_OFFSET); + } + + return rxLen; +} + +/****************************************************************************//** + * @brief UART get auto baud count value + * + * @param uartId: UART ID type + * @param autoBaudDet: Detection using codeword 0x55 or start bit + * + * @return Bit period of auto baudrate detection + * +*******************************************************************************/ +uint16_t UART_GetAutoBaudCount(UART_ID_Type uartId,UART_AutoBaudDetection_Type autoBaudDet) +{ + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameter */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_AUTOBAUDDETECTION_TYPE(autoBaudDet)); + + /* Select 0x55 or start bit detection value */ + if(UART_AUTOBAUD_0X55 == autoBaudDet){ + return BL_RD_REG(UARTx,UART_STS_URX_ABR_PRD)>>0x10&0xffff; + }else{ + return BL_RD_REG(UARTx,UART_STS_URX_ABR_PRD)&0xffff; + } +} + +/****************************************************************************//** + * @brief UART get tx fifo unoccupied count value + * + * @param uartId: UART ID type + * + * @return Tx fifo unoccupied count value + * +*******************************************************************************/ +uint8_t UART_GetTxFifoCount(UART_ID_Type uartId) +{ + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameter */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + return BL_GET_REG_BITS_VAL(BL_RD_REG(UARTx,UART_FIFO_CONFIG_1),UART_TX_FIFO_CNT); +} + +/****************************************************************************//** + * @brief UART get rx fifo occupied count value + * + * @param uartId: UART ID type + * + * @return Rx fifo occupied count value + * +*******************************************************************************/ +uint8_t UART_GetRxFifoCount(UART_ID_Type uartId) +{ + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameter */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + + return BL_GET_REG_BITS_VAL(BL_RD_REG(UARTx,UART_FIFO_CONFIG_1),UART_RX_FIFO_CNT); +} + +/****************************************************************************//** + * @brief Get uart interrupt status + * + * @param uartId: UART ID type + * @param intType: UART interrupt type + * + * @return Status of interrupt + * +*******************************************************************************/ +BL_Sts_Type UART_GetIntStatus(UART_ID_Type uartId,UART_INT_Type intType) +{ + uint32_t tmpVal; + uint32_t UARTx = uartAddr[uartId]; + + /* Check the parameters */ + CHECK_PARAM(IS_UART_ID_TYPE(uartId)); + CHECK_PARAM(IS_UART_INT_TYPE(intType)); + + /* Get certain or all interrupt status */ + tmpVal = BL_RD_REG(UARTx,UART_INT_STS); + if(UART_INT_ALL == intType){ + if((tmpVal&0xff) != 0) + { + return SET; + }else{ + return RESET; + } + }else{ + if((tmpVal&(1U<
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "string.h" +#include "bl602_xip_sflash.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup XIP_SFLASH + * @{ + */ + +/** @defgroup XIP_SFLASH_Private_Macros + * @{ + */ + +/*@} end of group XIP_SFLASH_Private_Macros */ + +/** @defgroup XIP_SFLASH_Private_Types + * @{ + */ + +/*@} end of group XIP_SFLASH_Private_Types */ + +/** @defgroup XIP_SFLASH_Private_Variables + * @{ + */ + +/*@} end of group XIP_SFLASH_Private_Variables */ + +/** @defgroup XIP_SFLASH_Global_Variables + * @{ + */ + +/*@} end of group XIP_SFLASH_Global_Variables */ + +/** @defgroup XIP_SFLASH_Private_Fun_Declaration + * @{ + */ + +/*@} end of group XIP_SFLASH_Private_Fun_Declaration */ + +/** @defgroup XIP_SFLASH_Private_Functions + * @{ + */ + +/****************************************************************************//** + * @brief Save flash controller state + * + * @param pFlashCfg: Flash config pointer + * @param offset: CPU XIP flash offset pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t *offset) +{ + /* XIP_SFlash_Delay */ + volatile uint32_t i=32*2; + while(i--); + + SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); + /* Exit form continous read for accepting command */ + SFlash_Reset_Continue_Read(pFlashCfg); + /* Send software reset command(80bv has no this command)to deburst wrap for ISSI like */ + SFlash_Software_Reset(pFlashCfg); + /* For disable command that is setting register instaed of send command, we need write enable */ + SFlash_DisableBurstWrap(pFlashCfg); + /* Enable QE again in case reset command make it reset */ + SFlash_Qspi_Enable(pFlashCfg); + /* Deburst again to make sure */ + SFlash_DisableBurstWrap(pFlashCfg); + + /* Clear offset setting*/ + *offset=SF_Ctrl_Get_Flash_Image_Offset(); + SF_Ctrl_Set_Flash_Image_Offset(0); + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Restore flash controller state + * + * @param pFlashCfg: Flash config pointer + * @param offset: CPU XIP flash offset + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t offset) +{ + uint32_t tmp[1]; + + SF_Ctrl_Set_Flash_Image_Offset(offset); + + SFlash_SetBurstWrap(pFlashCfg); + SFlash_Read(pFlashCfg,SF_CTRL_QIO_MODE,1,0x0,(uint8_t *)tmp, sizeof(tmp)); + SFlash_Set_IDbus_Cfg(pFlashCfg,SF_CTRL_QIO_MODE,1,0,32); + + return SUCCESS; +} + +/*@} end of group XIP_SFLASH_Private_Functions */ + +/** @defgroup XIP_SFLASH_Public_Functions + * @{ + */ + +/****************************************************************************//** + * @brief Erase flash one region + * + * @param pFlashCfg: Flash config pointer + * @param startaddr: start address to erase + * @param endaddr: end address(include this address) to erase + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t startaddr,uint32_t endaddr) +{ + BL_Err_Type stat; + uint32_t offset; + + stat=XIP_SFlash_State_Save(pFlashCfg,&offset); + if(stat!=SUCCESS){ + SFlash_Set_IDbus_Cfg(pFlashCfg,SF_CTRL_QIO_MODE,1,0,32); + }else{ + stat=SFlash_Erase(pFlashCfg,startaddr,endaddr); + XIP_SFlash_State_Restore(pFlashCfg,offset); + } + + return stat; +} + +/****************************************************************************//** + * @brief Program flash one region + * + * @param pFlashCfg: Flash config pointer + * @param addr: start address to be programed + * @param data: data pointer to be programed + * @param len: data length to be programed + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr,uint8_t *data, uint32_t len) +{ + BL_Err_Type stat; + uint32_t offset; + + stat=XIP_SFlash_State_Save(pFlashCfg,&offset); + if(stat!=SUCCESS){ + SFlash_Set_IDbus_Cfg(pFlashCfg,SF_CTRL_QIO_MODE,1,0,32); + }else{ + stat= SFlash_Program(pFlashCfg,SF_CTRL_QIO_MODE,addr,data,len); + XIP_SFlash_State_Restore(pFlashCfg,offset); + } + + return stat; +} + +/****************************************************************************//** + * @brief Read data from flash + * + * @param pFlashCfg: Flash config pointer + * @param addr: flash read start address + * @param data: data pointer to store data read from flash + * @param len: data length to read + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr,uint8_t *data, uint32_t len) +{ + BL_Err_Type stat; + uint32_t offset; + + stat=XIP_SFlash_State_Save(pFlashCfg,&offset); + if(stat!=SUCCESS){ + SFlash_Set_IDbus_Cfg(pFlashCfg,SF_CTRL_QIO_MODE,1,0,32); + }else{ + stat=SFlash_Read(pFlashCfg,SF_CTRL_QIO_MODE,0,addr, data,len); + XIP_SFlash_State_Restore(pFlashCfg,offset); + } + + return stat; +} + +/****************************************************************************//** + * @brief Get Flash Jedec ID + * + * @param pFlashCfg: Flash config pointer + * @param data: data pointer to store Jedec ID Read from flash + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data) +{ + BL_Err_Type stat; + uint32_t offset; + + stat=XIP_SFlash_State_Save(pFlashCfg,&offset); + if(stat!=SUCCESS){ + SFlash_Set_IDbus_Cfg(pFlashCfg,SF_CTRL_QIO_MODE,1,0,32); + }else{ + SFlash_GetJedecId(pFlashCfg,data); + XIP_SFlash_State_Restore(pFlashCfg,offset); + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Get Flash Device ID + * + * @param pFlashCfg: Flash config pointer + * @param data: data pointer to store Device ID Read from flash + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data) +{ + BL_Err_Type stat; + uint32_t offset; + + stat=XIP_SFlash_State_Save(pFlashCfg,&offset); + if(stat!=SUCCESS){ + SFlash_Set_IDbus_Cfg(pFlashCfg,SF_CTRL_QIO_MODE,1,0,32); + }else{ + SFlash_GetDeviceId(data); + XIP_SFlash_State_Restore(pFlashCfg,offset); + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Get Flash Unique ID + * + * @param pFlashCfg: Flash config pointer + * @param data: data pointer to store Device ID Read from flash + * @param idLen: Unique id len + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data,uint8_t idLen) +{ + BL_Err_Type stat; + uint32_t offset; + + stat=XIP_SFlash_State_Save(pFlashCfg,&offset); + if(stat!=SUCCESS){ + SFlash_Set_IDbus_Cfg(pFlashCfg,SF_CTRL_QIO_MODE,1,0,32); + }else{ + SFlash_GetUniqueId(data,idLen); + XIP_SFlash_State_Restore(pFlashCfg,offset); + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Read data from flash via XIP + * + * @param addr: flash read start address + * @param data: data pointer to store data read from flash + * @param len: data length to read + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr,uint8_t *data, uint32_t len) +{ + uint32_t offset; + + if(addr>=BL602_FLASH_XIP_BASE && addr
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "string.h" +#include "bl602_xip_sflash_ext.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup XIP_SFLASH + * @{ + */ + +/** @defgroup XIP_SFLASH_EXT_Private_Macros + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Private_Macros */ + +/** @defgroup XIP_SFLASH_EXT_Private_Types + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Private_Types */ + +/** @defgroup XIP_SFLASH_EXT_Private_Variables + * @{ + */ + +static SPI_Flash_Cfg_Type flashCfg; +static uint8_t aesEnable; + +/*@} end of group XIP_SFLASH_EXT_Private_Variables */ + +/** @defgroup XIP_SFLASH_EXT_Global_Variables + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Global_Variables */ + +/** @defgroup XIP_SFLASH_EXT_Private_Fun_Declaration + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Private_Fun_Declaration */ + +/** @defgroup XIP_SFLASH_EXT_Private_Functions + * @{ + */ + +/****************************************************************************//** + * @brief Read data from flash with lock + * + * @param pFlashCfg:Flash config pointer + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Init(SPI_Flash_Cfg_Type *pFlashCfg) +{ + uint32_t ret; + + if(pFlashCfg==NULL){ + /* Get flash config identify */ + XIP_SFlash_Opt_Enter(&aesEnable); + ret=SF_Cfg_Flash_Identify_Ext(1,1,0,0,&flashCfg); + XIP_SFlash_Opt_Exit(aesEnable); + if((ret&BFLB_FLASH_ID_VALID_FLAG)==0){ + return ERROR; + } + }else{ + memcpy(&flashCfg,pFlashCfg,sizeof(flashCfg)); + } + + return SUCCESS; +} + +/****************************************************************************//** + * @brief Read data from flash with lock + * + * @param addr: flash read start address + * @param dst: data pointer to store data read from flash + * @param len: data length to read + * + * @return 0 + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION XIP_SFlash_Read(uint32_t addr, uint8_t *dst, int len) +{ + __disable_irq(); + XIP_SFlash_Opt_Enter(&aesEnable); + XIP_SFlash_Read_Need_Lock(&flashCfg, addr, dst, len); + XIP_SFlash_Opt_Exit(aesEnable); + __enable_irq(); + return 0; +} + +/****************************************************************************//** + * @brief Program flash one region with lock + * + * @param addr: Start address to be programed + * @param src: Data pointer to be programed + * @param len: Data length to be programed + * + * @return 0 + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION XIP_SFlash_Write(uint32_t addr, uint8_t *src, int len) +{ + __disable_irq(); + XIP_SFlash_Opt_Enter(&aesEnable); + XIP_SFlash_Write_Need_Lock(&flashCfg, addr, src, len); + XIP_SFlash_Opt_Exit(aesEnable); + __enable_irq(); + return 0; +} + +/****************************************************************************//** + * @brief Erase flash one region with lock + * + * @param addr: Start address to be erased + * @param len: Data length to be erased + * + * @return 0 + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION XIP_SFlash_Erase(uint32_t addr, int len) +{ + __disable_irq(); + XIP_SFlash_Opt_Enter(&aesEnable); + XIP_SFlash_Erase_Need_Lock(&flashCfg, addr, addr + len - 1); + XIP_SFlash_Opt_Exit(aesEnable); + __enable_irq(); + return 0; +} + +/*@} end of group XIP_SFLASH_EXT_Public_Functions */ + +/*@} end of group XIP_SFLASH_EXT */ + +/*@} end of group BL602_Peripheral_Driver */