From c2f30724553ff92c9f0fd7ee816741665beeef28 Mon Sep 17 00:00:00 2001 From: jzlv Date: Fri, 4 Jun 2021 17:49:10 +0800 Subject: [PATCH] [fix] fix hal driver --- drivers/bl702_driver/bl702_flash.ld | 10 +- drivers/bl702_driver/bl702_ram.ld | 193 ++ drivers/bl702_driver/cpu_flags.cmake | 14 + .../hal_drv/default_config/power_config.h | 17 + .../hal_drv/default_config/pwm_config.h | 6 +- drivers/bl702_driver/hal_drv/inc/hal_adc.h | 91 +- drivers/bl702_driver/hal_drv/inc/hal_cam.h | 78 + drivers/bl702_driver/hal_drv/inc/hal_camera.h | 173 -- drivers/bl702_driver/hal_drv/inc/hal_clock.h | 24 +- drivers/bl702_driver/hal_drv/inc/hal_dma.h | 12 +- drivers/bl702_driver/hal_drv/inc/hal_flash.h | 10 +- drivers/bl702_driver/hal_drv/inc/hal_gpio.h | 2 +- drivers/bl702_driver/hal_drv/inc/hal_i2c.h | 3 - drivers/bl702_driver/hal_drv/inc/hal_mjpeg.h | 69 + drivers/bl702_driver/hal_drv/inc/hal_mtimer.h | 7 +- drivers/bl702_driver/hal_drv/inc/hal_power.h | 56 + drivers/bl702_driver/hal_drv/inc/hal_pwm.h | 17 +- .../bl702_driver/hal_drv/inc/hal_sec_aes.h | 58 + .../bl702_driver/hal_drv/inc/hal_sec_dsa.h | 59 + .../bl702_driver/hal_drv/inc/hal_sec_ecdsa.h | 57 + .../bl702_driver/hal_drv/inc/hal_sec_hash.h | 55 + drivers/bl702_driver/hal_drv/inc/hal_spi.h | 7 + drivers/bl702_driver/hal_drv/inc/hal_timer.h | 9 +- drivers/bl702_driver/hal_drv/inc/hal_uart.h | 13 +- drivers/bl702_driver/hal_drv/inc/hal_usb.h | 4 + drivers/bl702_driver/hal_drv/src/hal_adc.c | 120 +- drivers/bl702_driver/hal_drv/src/hal_cam.c | 148 ++ drivers/bl702_driver/hal_drv/src/hal_camera.c | 1874 ----------------- drivers/bl702_driver/hal_drv/src/hal_clock.c | 113 +- drivers/bl702_driver/hal_drv/src/hal_dac.c | 6 +- drivers/bl702_driver/hal_drv/src/hal_dma.c | 14 +- drivers/bl702_driver/hal_drv/src/hal_flash.c | 147 +- drivers/bl702_driver/hal_drv/src/hal_gpio.c | 51 +- drivers/bl702_driver/hal_drv/src/hal_i2c.c | 4 +- drivers/bl702_driver/hal_drv/src/hal_i2s.c | 6 +- drivers/bl702_driver/hal_drv/src/hal_mjpeg.c | 123 ++ drivers/bl702_driver/hal_drv/src/hal_mtimer.c | 105 +- drivers/bl702_driver/hal_drv/src/hal_power.c | 1505 +++++++++++++ drivers/bl702_driver/hal_drv/src/hal_pwm.c | 208 +- .../bl702_driver/hal_drv/src/hal_sec_aes.c | 117 + .../bl702_driver/hal_drv/src/hal_sec_dsa.c | 368 ++++ .../bl702_driver/hal_drv/src/hal_sec_ecdsa.c | 1202 +++++++++++ .../bl702_driver/hal_drv/src/hal_sec_hash.c | 243 +++ drivers/bl702_driver/hal_drv/src/hal_spi.c | 8 +- drivers/bl702_driver/hal_drv/src/hal_timer.c | 95 +- drivers/bl702_driver/hal_drv/src/hal_uart.c | 22 +- drivers/bl702_driver/hal_drv/src/hal_usb.c | 135 +- drivers/bl702_driver/regs/bl702.h | 34 +- drivers/bl702_driver/startup/interrupt.c | 2 +- drivers/bl702_driver/startup/system_bl702.c | 3 + drivers/bl702_driver/std_drv/inc/bl702_adc.h | 4 + drivers/bl702_driver/std_drv/inc/bl702_gpio.h | 4 +- .../bl702_driver/std_drv/inc/bl702_sec_eng.h | 1 + drivers/bl702_driver/std_drv/src/bl702_adc.c | 70 + .../bl702_driver/std_drv/src/bl702_sec_eng.c | 33 + drivers/bl702_driver/std_drv/src/bl702_uart.c | 4 +- 56 files changed, 5242 insertions(+), 2571 deletions(-) create mode 100644 drivers/bl702_driver/bl702_ram.ld create mode 100644 drivers/bl702_driver/cpu_flags.cmake create mode 100644 drivers/bl702_driver/hal_drv/default_config/power_config.h create mode 100644 drivers/bl702_driver/hal_drv/inc/hal_cam.h delete mode 100644 drivers/bl702_driver/hal_drv/inc/hal_camera.h create mode 100644 drivers/bl702_driver/hal_drv/inc/hal_mjpeg.h create mode 100644 drivers/bl702_driver/hal_drv/inc/hal_power.h create mode 100644 drivers/bl702_driver/hal_drv/inc/hal_sec_aes.h create mode 100644 drivers/bl702_driver/hal_drv/inc/hal_sec_dsa.h create mode 100644 drivers/bl702_driver/hal_drv/inc/hal_sec_ecdsa.h create mode 100644 drivers/bl702_driver/hal_drv/inc/hal_sec_hash.h create mode 100644 drivers/bl702_driver/hal_drv/src/hal_cam.c delete mode 100644 drivers/bl702_driver/hal_drv/src/hal_camera.c create mode 100644 drivers/bl702_driver/hal_drv/src/hal_mjpeg.c create mode 100644 drivers/bl702_driver/hal_drv/src/hal_power.c create mode 100644 drivers/bl702_driver/hal_drv/src/hal_sec_aes.c create mode 100644 drivers/bl702_driver/hal_drv/src/hal_sec_dsa.c create mode 100644 drivers/bl702_driver/hal_drv/src/hal_sec_ecdsa.c create mode 100644 drivers/bl702_driver/hal_drv/src/hal_sec_hash.c diff --git a/drivers/bl702_driver/bl702_flash.ld b/drivers/bl702_driver/bl702_flash.ld index 4d6949ef..b2fe4fcf 100644 --- a/drivers/bl702_driver/bl702_flash.ld +++ b/drivers/bl702_driver/bl702_flash.ld @@ -11,9 +11,9 @@ /* configure the CPU type */ OUTPUT_ARCH( "riscv" ) /* link with the standard c library */ -INPUT(-lc) +/* INPUT(-lc) */ /* link with the standard GCC library */ -INPUT(-lgcc) +/* INPUT(-lgcc) */ /* configure the entry point */ ENTRY(_enter) @@ -22,10 +22,10 @@ HeapSize = 0x1000; /* 4KB */ MEMORY { - xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 4096K + xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 1024K itcm_memory (rx) : ORIGIN = 0x22014000, LENGTH = 16K - dtcm_memory (rx) : ORIGIN = 0x42018000, LENGTH = 32K - ram_memory (!rx) : ORIGIN = 0x42020000, LENGTH = 48K + dtcm_memory (rx) : ORIGIN = 0x42018000, LENGTH = 16K + ram_memory (!rx) : ORIGIN = 0x4201C000, LENGTH = 96K } SECTIONS diff --git a/drivers/bl702_driver/bl702_ram.ld b/drivers/bl702_driver/bl702_ram.ld new file mode 100644 index 00000000..375f1c78 --- /dev/null +++ b/drivers/bl702_driver/bl702_ram.ld @@ -0,0 +1,193 @@ +/**************************************************************************************** +* @file map.txt +* +* @brief This file is the map file (gnuarm or armgcc). +* +* Copyright (C) BouffaloLab 2018 +* +**************************************************************************************** +*/ + +/* configure the CPU type */ +OUTPUT_ARCH( "riscv" ) +/* link with the standard c library */ +/* INPUT(-lc) */ +/* link with the standard GCC library */ +/* INPUT(-lgcc) */ +/* configure the entry point */ +ENTRY(_enter) + +StackSize = 0x0400; /* 1KB */ +HeapSize = 0x1000; /* 4KB */ + +MEMORY +{ + itcm_memory (rx) : ORIGIN = 0x22010000, LENGTH = 32K + dtcm_memory (rx) : ORIGIN = 0x42018000, LENGTH = 32K + ram_memory (!rx) : ORIGIN = 0x42020000, LENGTH = 48K +} + +SECTIONS +{ + PROVIDE(__metal_chicken_bit = 0); + + .text : + { + . = ALIGN(4); + __text_code_start__ = .; + + KEEP (*(.text.metal.init.enter)) + KEEP (*(SORT_NONE(.init))) + + *(.text) + *(.text.*) + + *(.rodata) + *(.rodata.*) + + *(.srodata) + *(.srodata.*) + + *(.tcm_code) + *(.tcm_const) + *(.sclock_rlt_code) + *(.sclock_rlt_const) + + . = ALIGN(4); + __text_code_end__ = .; + } > itcm_memory + + . = ALIGN(4); + __itcm_load_addr = .; + + .itcm_region : AT (__itcm_load_addr) + { + . = ALIGN(4); + __tcm_code_start__ = .; + + . = ALIGN(4); + __tcm_code_end__ = .; + } > itcm_memory + + __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); + + .dtcm_region : AT (__dtcm_load_addr) + { + . = ALIGN(4); + __tcm_data_start__ = .; + + *(.tcm_data) + + . = ALIGN(4); + __tcm_data_end__ = .; + } > dtcm_memory + + /* .heap_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of heap sections, and assign + * values to heap symbols later */ + .heap_dummy (NOLOAD): + { + . = ALIGN(0x4); + . = . + HeapSize; + . = ALIGN(0x4); + } > dtcm_memory + + _HeapBase = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory) - StackSize - HeapSize; + _HeapSize = HeapSize; + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(_HeapBase >= __tcm_data_end__, "region RAM overflowed with stack") + + /*************************************************************************/ + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + . = ALIGN(0x4); + . = . + StackSize; + . = ALIGN(0x4); + } > dtcm_memory + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") + /*************************************************************************/ + + __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); + + .system_ram_data_region : AT (__system_ram_load_addr) + { + . = ALIGN(4); + __system_ram_data_start__ = .; + + *(.system_ram) + + . = ALIGN(4); + __system_ram_data_end__ = .; + } > ram_memory + + __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); + + /* Data section */ + RAM_DATA : AT (__ram_load_addr) + { + . = ALIGN(4); + __ram_data_start__ = .; + + PROVIDE( __global_pointer$ = . + 0x800 ); + + *(.data) + *(.data.*) + *(.sdata) + *(.sdata.*) + *(.sdata2) + *(.sdata2.*) + + . = ALIGN(4); + __ram_data_end__ = .; + } > ram_memory + + .bss (NOLOAD) : + { + . = ALIGN(4); + __bss_start__ = .; + + *(.bss*) + *(.sbss*) + *(COMMON) + + . = ALIGN(4); + __bss_end__ = .; + } > ram_memory + + .noinit_data (NOLOAD) : + { + . = ALIGN(4); + __noinit_data_start__ = .; + + *(.noinit_data*) + + . = ALIGN(4); + __noinit_data_end__ = .; + } > ram_memory + + .heap (NOLOAD): + { + . = ALIGN(4); + __HeapBase = .; + + /*__end__ = .;*/ + /*end = __end__;*/ + KEEP(*(.heap*)) + + . = ALIGN(4); + __HeapLimit = .; + } > ram_memory + +} + diff --git a/drivers/bl702_driver/cpu_flags.cmake b/drivers/bl702_driver/cpu_flags.cmake new file mode 100644 index 00000000..0e0e287d --- /dev/null +++ b/drivers/bl702_driver/cpu_flags.cmake @@ -0,0 +1,14 @@ +SET(CPU_ARCH "RISCV") +SET(MCPU "riscv-e24") +if(${SUPPORT_FLOAT} STREQUAL "y") +SET(MARCH "rv32imafc") +SET(MABI "ilp32f") +else() +SET(MARCH "rv32imac") +SET(MABI "ilp32") +endif() + +list(APPEND GLOBAL_C_FLAGS -march=${MARCH} -mabi=${MABI}) +list(APPEND GLOBAL_LD_FLAGS -march=${MARCH} -mabi=${MABI}) + +SET(LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/bl702_flash.ld) \ No newline at end of file diff --git a/drivers/bl702_driver/hal_drv/default_config/power_config.h b/drivers/bl702_driver/hal_drv/default_config/power_config.h new file mode 100644 index 00000000..ef79fa99 --- /dev/null +++ b/drivers/bl702_driver/hal_drv/default_config/power_config.h @@ -0,0 +1,17 @@ +#ifndef _POWER_CONFIG_H +#define _POWER_CONFIG_H + + +#define DEAULT_LP_XTAL_TYPE GLB_DLL_XTAL_32M +#define DEFAULT_LP_LDO_LEVEL PDS_LDO_LEVEL_1P10V +#define DEFAULT_LP_PDS_AON_GPIO_WAKE_UP_SRC PDS_AON_WAKEUP_GPIO_NONE +#define DEFAULT_LP_PDS_AON_GPIO_TRIG_TYPE PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE + +#define DEFAULT_LP_PDS_FLASH_POWER_DOWN 1 +#define DEFAULT_LP_PDS_HOLD_GPIO 0 +#define DEFAULT_LP_PDS_TURN_OFF_FLASH_PAD 1 +#define DEFAULT_LP_PDS_TURN_OFF_XTAL_32M 1 +#define DEFAULT_LP_PDS_TURN_OFF_DLL 1 +#define DEFAULT_LP_PDS_TURN_OFF_RF 1 +#define DEFAULT_LP_PDS_USE_XTAL_32K 0 +#endif \ No newline at end of file diff --git a/drivers/bl702_driver/hal_drv/default_config/pwm_config.h b/drivers/bl702_driver/hal_drv/default_config/pwm_config.h index 0096a513..366de0e4 100644 --- a/drivers/bl702_driver/hal_drv/default_config/pwm_config.h +++ b/drivers/bl702_driver/hal_drv/default_config/pwm_config.h @@ -1,7 +1,7 @@ #ifndef _PWM_CONFIG_H #define _PWM_CONFIG_H -#define PWM_STOP_MODE_SEL (1) /*PWM_STOP_GRACEFUL */ -#define PWM_POL_SEL (0) /*!< PWM POL NORAML */ -#define PWM_MAX_CHANNEL (5) +#define PWM_STOP_MODE_SEL (PWM_STOP_GRACEFUL) +#define PWM_POL_SEL (PWM_POL_NORMAL) + #endif \ No newline at end of file diff --git a/drivers/bl702_driver/hal_drv/inc/hal_adc.h b/drivers/bl702_driver/hal_drv/inc/hal_adc.h index 59dde2f0..37f3467e 100644 --- a/drivers/bl702_driver/hal_drv/inc/hal_adc.h +++ b/drivers/bl702_driver/hal_drv/inc/hal_adc.h @@ -26,6 +26,14 @@ #include "drv_device.h" #include "bl702_config.h" +#define DEVICE_CTRL_ADC_CHANNEL_START 0x10 +#define DEVICE_CTRL_ADC_CHANNEL_STOP 0x11 +#define DEVICE_CTRL_ADC_CHANNEL_CONFIG 0x12 +#define DEVICE_CTRL_ADC_VBAT_ON 0x13 +#define DEVICE_CTRL_ADC_VBAT_OFF 0x14 +#define DEVICE_CTRL_ADC_TSEN_ON 0x15 +#define DEVICE_CTRL_ADC_TSEN_OFF 0x16 + enum adc_index_type { #ifdef BSP_USING_ADC0 @@ -34,9 +42,9 @@ enum adc_index_type ADC_MAX_INDEX }; -#define ADC_CLK_MAX (2000000) - -#define LEFT_SHIFT_BIT(x) (1 << x) +#define adc_channel_start(dev) device_control(dev,DEVICE_CTRL_ADC_CHANNEL_START,NULL) +#define adc_channel_stop(dev) device_control(dev,DEVICE_CTRL_ADC_CHANNEL_STOP,NULL) +#define adc_channel_config(dev,list) device_control(dev,DEVICE_CTRL_ADC_CHANNEL_CONFIG,list) typedef enum { ADC_CHANNEL0, /* GPIO 0, ADC channel 0 */ @@ -66,65 +74,84 @@ typedef enum { }adc_channel_t; typedef enum { - ADC_CLK_2MHZ, - ADC_CLK_1P3MHZ, - ADC_CLK_1MHZ, - ADC_CLK_500KHZ, -}adc_clk_t; + ADC_CLOCK_DIV_1, /*!< ADC clock:on 32M clock is 32M */ + ADC_CLOCK_DIV_4, /*!< ADC clock:on 32M clock is 8M */ + ADC_CLOCK_DIV_8, /*!< ADC clock:on 32M clock is 4M */ + ADC_CLOCK_DIV_12, /*!< ADC clock:on 32M clock is 2.666M */ + ADC_CLOCK_DIV_16, /*!< ADC clock:on 32M clock is 2M */ + ADC_CLOCK_DIV_20, /*!< ADC clock:on 32M clock is 1.6M */ + ADC_CLOCK_DIV_24, /*!< ADC clock:on 32M clock is 1.333M */ + ADC_CLOCK_DIV_32, /*!< ADC clock:on 32M clock is 1M */ +}adc_clk_div_t; typedef enum { ADC_VREF_3P2V = 0, /* ADC select 3.2V as reference voltage */ ADC_VREF_2P0V = 1, /* ADC select 2V as reference voltage */ }adc_vref_t; -typedef enum { - ADC_ONE_CONV = 0, /* ADC One shot conversion mode */ - ADC_CON_CONV = 1, /* ADC Continuous conversion mode */ -}adc_conv_t; - /** * @brief ADC data width type definition */ typedef enum { - ADC_DATA_WD_12, /*!< ADC 12 bits */ - ADC_DATA_WD_14_WITH_16_AVERAGE, /*!< ADC 14 bits,and the value is average of 16 converts */ - ADC_DATA_WD_16_WITH_64_AVERAGE, /*!< ADC 16 bits,and the value is average of 64 converts */ - ADC_DATA_WD_16_WITH_128_AVERAGE, /*!< ADC 16 bits,and the value is average of 128 converts */ - ADC_DATA_WD_16_WITH_256_AVERAGE, /*!< ADC 16 bits,and the value is average of 256 converts */ + ADC_DATA_WIDTH_12B, /*!< ADC 12 bits */ + ADC_DATA_WIDTH_14B_WITH_16_AVERAGE, /*!< ADC 14 bits,and the value is average of 16 converts */ + ADC_DATA_WIDTH_16B_WITH_64_AVERAGE, /*!< ADC 16 bits,and the value is average of 64 converts */ + ADC_DATA_WIDTH_16B_WITH_128_AVERAGE, /*!< ADC 16 bits,and the value is average of 128 converts */ + ADC_DATA_WIDTH_16B_WITH_256_AVERAGE, /*!< ADC 16 bits,and the value is average of 256 converts */ }adc_data_width_t; +/** + * @brief ADC FIFO threshold type definition + */ typedef enum { - ADC_SINGLE_ENDED_IN = 0, /* ADC signal is single-ended input */ - ADC_DIFFERENTIAL_IN = 1, /* ADC signal is differential input*/ -}adc_inputmode_t; + ADC_FIFO_THRESHOLD_1BYTE, /*!< ADC FIFO threshold is 1 */ + ADC_FIFO_THRESHOLD_4BYTE, /*!< ADC FIFO threshold is 4 */ + ADC_FIFO_THRESHOLD_8BYTE, /*!< ADC FIFO threshold is 8 */ + ADC_FIFO_THRESHOLD_16BYTE, /*!< ADC FIFO threshold is 16 */ +}adc_fifo_threshold_t; + +/** + * @brief ADC PGA gain type definition + */ +typedef enum { + ADC_GAIN_NONE, /*!< No PGA gain */ + ADC_GAIN_1, /*!< PGA gain 1 */ + ADC_GAIN_2, /*!< PGA gain 2 */ + ADC_GAIN_4, /*!< PGA gain 4 */ + ADC_GAIN_8, /*!< PGA gain 8 */ + ADC_GAIN_16, /*!< PGA gain 16 */ + ADC_GAIN_32, /*!< PGA gain 32 */ +}adc_pga_gain_t; typedef struct { - uint8_t *pinList; - uint8_t *posChList; - uint8_t *negChList; + uint8_t *pos_channel; + uint8_t *neg_channel; uint8_t num; - uint8_t dma_en; - adc_conv_t conv_mode; - adc_inputmode_t in_mode; -} adc_user_cfg_t; +} adc_channel_cfg_t; typedef struct { int8_t posChan; /*!< Positive channel */ int8_t negChan; /*!< Negative channel */ uint16_t value; /*!< ADC value */ float volt; /*!< ADC voltage result */ -}adc_res_val_t; +}adc_channel_val_t; typedef struct adc_device { struct device parent; - adc_clk_t clk; /* CLK is not more than 2Mhz */ + adc_clk_div_t clk_div; /* CLK is not more than 2Mhz */ adc_vref_t vref; /* ADC voltage reference*/ - adc_data_width_t resWidth; + bool continuous_conv_mode; /** conversion mode: shot conversion mode or continuous conversion mode. */ + bool differential_mode; /** Channel type: single-ended or differential. */ + adc_data_width_t data_width; + adc_fifo_threshold_t fifo_threshold; + adc_pga_gain_t gain; } adc_device_t; #define ADC_DEV(dev) ((adc_device_t*)dev) -int adc_register(enum adc_index_type index, const char *name, uint16_t flag, adc_user_cfg_t *adc_user_cfg); +int adc_register(enum adc_index_type index, const char *name, uint16_t flag); +int adc_trim_tsen(uint16_t * tsen_offset); +float adc_get_tsen(uint16_t tsen_offset); #endif \ No newline at end of file diff --git a/drivers/bl702_driver/hal_drv/inc/hal_cam.h b/drivers/bl702_driver/hal_drv/inc/hal_cam.h new file mode 100644 index 00000000..7c26c853 --- /dev/null +++ b/drivers/bl702_driver/hal_drv/inc/hal_cam.h @@ -0,0 +1,78 @@ +/** + * @file hal_cam.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef __HAL_CAM_H__ +#define __HAL_CAM_H__ + +#include "drv_device.h" +#include "bl702_cam.h" +#include "bl702_config.h" + +typedef enum +{ + CAM_AUTO_MODE, + CAM_MANUAL_MODE, +} cam_software_mode_t; + +typedef enum +{ + CAM_FRAME_PLANAR_MODE, + CAM_FRAME_INTERLEAVE_MODE, +} cam_frame_mode_t; + +typedef enum +{ + CAM_YUV_FORMAT_YUV422, + CAM_YUV_FORMAT_YUV420_EVEN, + CAM_YUV_FORMAT_YUV420_ODD, + CAM_YUV_FORMAT_YUV400_EVEN, + CAM_YUV_FORMAT_YUV400_ODD, +} cam_yuv_format_t; + +typedef struct cam_device +{ + struct device parent; + cam_software_mode_t software_mode; + cam_frame_mode_t frame_mode; + cam_yuv_format_t yuv_format; + uint32_t cam_write_ram_addr; + uint32_t cam_write_ram_size; + uint32_t cam_frame_size; + + // planar mode need use: + uint32_t cam_write_ram_addr1; + uint32_t cam_write_ram_size1; + uint32_t cam_frame_size1; +} cam_device_t; + +void cam_init(cam_device_t *cam_cfg); +void cam_start(void); +void cam_stop(void); +uint8_t cam_get_one_frame_interleave(uint8_t **pic, uint32_t *len); +uint8_t cam_get_one_frame_planar(CAM_YUV_Mode_Type yuv, uint8_t **picYY, uint32_t *lenYY, uint8_t **picUV, uint32_t *lenUV); +void cam_drop_one_frame_interleave(void); +void cam_drop_one_frame_planar(void); +void cam_hsync_crop(uint16_t start, uint16_t end); +void cam_vsync_crop(uint16_t start, uint16_t end); + +#endif diff --git a/drivers/bl702_driver/hal_drv/inc/hal_camera.h b/drivers/bl702_driver/hal_drv/inc/hal_camera.h deleted file mode 100644 index aa60db91..00000000 --- a/drivers/bl702_driver/hal_drv/inc/hal_camera.h +++ /dev/null @@ -1,173 +0,0 @@ -/** - * @file hal_camera.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __IMAGE_SENSOR_H__ -#define __IMAGE_SENSOR_H__ - -#include "bl702_common.h" -#include "bl702_cam.h" -#include "bl702_mjpeg.h" - -#define IMAGE_SENSOR_BF2013 0 -#define IMAGE_SENSOR_GC0308 1 -#define IMAGE_SENSOR_USE IMAGE_SENSOR_GC0308 - - -#define ENDADDR (0x42030000) -#define CAMERA_RESOLUTION_X 640 -#define CAMERA_RESOLUTION_Y 480 -#define CAMERA_FRAME_SIZE (CAMERA_RESOLUTION_X * CAMERA_RESOLUTION_Y * 2) -#define MJPEG_READ_ADDR 0x42020800//0x42022000 -#define MJPEG_READ_SIZE 2 -#define YUV_USE 1 -#if(YUV_USE == 1) -#define CAMERA_BUFFER_SIZE_WHEN_MJPEG (CAMERA_RESOLUTION_X * 2 * 8 * MJPEG_READ_SIZE) -#else -#define CAMERA_BUFFER_SIZE_WHEN_MJPEG (CAMERA_RESOLUTION_X * 8 * MJPEG_READ_SIZE) -#endif -#define MJPEG_WRITE_ADDR (MJPEG_READ_ADDR+CAMERA_BUFFER_SIZE_WHEN_MJPEG) -#define MJPEG_WRITE_SIZE (ENDADDR - MJPEG_READ_ADDR -CAMERA_BUFFER_SIZE_WHEN_MJPEG) - -extern CAM_CFG_Type cameraCfg; -extern MJPEG_CFG_Type mjpegCfg; - -void Image_Sensor_PSRAM_Init(void); -BL_Err_Type Image_Sensor_Init(BL_Fun_Type mjpegEn, CAM_CFG_Type *camCfg, MJPEG_CFG_Type *mjpegCfg); -void Image_Sensor_Dump_Register(void); -BL_Err_Type Image_Sensor_CAM_Get_Interleave(uint8_t **pic, uint32_t *len); -BL_Err_Type Image_Sensor_CAM_Get_Planar(CAM_YUV_Mode_Type yuv, uint8_t **picYY, uint32_t *lenYY, - uint8_t **picUV, uint32_t *lenUV); -uint8_t Image_Sensor_CAM_Frame_Count0(void); -uint8_t Image_Sensor_CAM_Frame_Count1(void); -void Image_Sensor_CAM_Release_Interleave(void); -void Image_Sensor_CAM_Release_Planar(void); -void Image_Sensor_CAM_Open(void); -void Image_Sensor_CAM_Close(void); -void Image_Sensor_CAM_Deinit(void); -BL_Err_Type Image_Sensor_MJPEG_Get(uint8_t **pic, uint32_t *len, uint8_t *q); -uint8_t Image_Sensor_MJPEG_Frame_Count(void); -void Image_Sensor_MJPEG_Release(void); -void Image_Sensor_MJPEG_Open(void); -void Image_Sensor_MJPEG_Close(void); -void Image_Sensor_MJPEG_Deinit(void); - -void ClkOutInit(void); -BL_Err_Type Timer_Init(void); -void Test_H(void); -void Test_L(void); -void Timer_Match0_Cbf(void); - -#endif - -// #ifndef __HAL_CAM__H__ -// #define __HAL_CAM__H__ - -// #include "drv_device.h" -// #include "bl702_config.h" - -// #define DEVICE_CTRL_CONFIG_CAM_START 0x10 -// #define DEVICE_CTRL_CONFIG_CAM_STOP 0x11 - -// typedef enum -// { -// CAMERA_PLANAR_MODE, -// CAMERA_INTERLEAVE_MODE, -// } camera_frame_mode_t; - -// typedef enum -// { -// CAMERA_YUV422, -// CAMERA_YUV420_EVEN, -// CAMERA_YUV420_ODD, -// CAMERA_YUV400_EVEN, -// CAMERA_YUV400_ODD, -// } camera_yuv_mode_t; - -// typedef struct -// { -// camera_frame_mode_t frame_mode; -// camera_yuv_mode_t yuv_mode; -// BL_Fun_Type mjpeg_enable; -// uint8_t mjpegQ; -// } camera_pic_format_t; - -// typedef enum -// { -// CAMERA_LINE_ACTIVE_POLARITY_LOW, /*!< CAMERA line active polarity low */ -// CAMERA_LINE_ACTIVE_POLARITY_HIGH, /*!< CAMERA line active polarity high */ -// } camera_line_active_polarity; - -// typedef enum -// { -// CAMERA_FRAME_ACTIVE_POLARITY_LOW, /*!< CAMERA frame active polarity low */ -// CAMERA_FRAME_ACTIVE_POLARITY_HIGH, /*!< CAMERA frame active polarity high */ -// } camera_frame_active_polarity; - -// typedef struct -// { -// uint8_t mclk; -// uint8_t pclk; -// uint8_t vsync; -// uint8_t hsync; -// uint8_t data0; -// uint8_t data1; -// uint8_t data2; -// uint8_t data3; -// uint8_t data4; -// uint8_t data5; -// uint8_t data6; -// uint8_t data7; -// BL_Fun_Type mclk_enable; -// } camera_pin_t; - -// typedef struct -// { -// uint8_t *base1; -// uint8_t *addr1; -// uint32_t length1; -// uint8_t *base2; -// uint8_t *addr2; -// uint32_t length2; -// } camera_picture_t; - -// typedef struct -// { -// struct device parent; -// uint8_t id; -// camera_pin_t pin; -// uint32_t pic_reso_x; -// uint32_t pic_reso_y; -// uint8_t *buffer; -// uint32_t length; -// camera_pic_format_t pic_format; -// camera_line_active_polarity line_pol; -// camera_frame_active_polarity frame_pol; -// uint8_t mjpeg_quality; -// camera_picture_t picture; -// } camera_device_t; - -// void camera_register(camera_device_t *device, const char *name, uint16_t flag); -// int device_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size); - -// extern camera_device_t camera_device; - -// #endif \ No newline at end of file diff --git a/drivers/bl702_driver/hal_drv/inc/hal_clock.h b/drivers/bl702_driver/hal_drv/inc/hal_clock.h index b959eddd..464ac233 100644 --- a/drivers/bl702_driver/hal_drv/inc/hal_clock.h +++ b/drivers/bl702_driver/hal_drv/inc/hal_clock.h @@ -34,21 +34,26 @@ #define ROOT_CLOCK_SOURCE_RC_32M 2 #define ROOT_CLOCK_SOURCE_XTAL_32M 3 -#define ROOT_CLOCK_SOURCE_DLL_57P6M 4 -#define ROOT_CLOCK_SOURCE_DLL_96M 5 -#define ROOT_CLOCK_SOURCE_DLL_144M 6 +#define ROOT_CLOCK_SOURCE_PLL_57P6M 4 +#define ROOT_CLOCK_SOURCE_PLL_96M 5 +#define ROOT_CLOCK_SOURCE_PLL_144M 6 + +#define ROOT_CLOCK_SOURCE_XCLK ROOT_CLOCK_SOURCE_XTAL_32M +#define ROOT_CLOCK_SOURCE_FCLK 7 +#define ROOT_CLOCK_SOURCE_HCLK 7 +#define ROOT_CLOCK_SOURCE_BCLK 8 -#define ROOT_CLOCK_SOURCE_DLL_FCLK 7 -#define ROOT_CLOCK_SOURCE_DLL_HCLK 7 -#define ROOT_CLOCK_SOURCE_DLL_BCLK 8 -#define ROOT_CLOCK_SOURCE_DLL_XCLK 3 #define ROOT_CLOCK_SOURCE_AUPLL 9 +#define AUDIO_PLL_CLOCK_12288000_HZ 0x90 +#define AUDIO_PLL_CLOCK_11289600_HZ 0x91 +#define AUDIO_PLL_CLOCK_5644800_HZ 0x92 +#define AUDIO_PLL_CLOCK_24576000_HZ 0x93 +#define AUDIO_PLL_CLOCK_24000000_HZ 0x94 #define OUTPUT_REF_CLOCK_SOURCE_NONE 0 #define OUTPUT_REF_CLOCK_SOURCE_I2S 1 -#define BSP_ROOT_CLOCK_SOURCE ROOT_CLOCK_SOURCE_DLL_144M #if (BSP_ROOT_CLOCK_SOURCE > 2) && (BSP_ROOT_CLOCK_SOURCE < 7) #define CLOCK_XTAL EXTERNAL_XTAL_32M #else @@ -61,6 +66,7 @@ enum system_clock_type SYSTEM_CLOCK_FCLK, SYSTEM_CLOCK_BCLK, SYSTEM_CLOCK_XCLK, + SYSTEM_CLOCK_AUPLL, }; enum peripheral_clock_type { @@ -70,6 +76,8 @@ enum peripheral_clock_type PERIPHERAL_CLOCK_ADC, PERIPHERAL_CLOCK_DAC, PERIPHERAL_CLOCK_I2S, + PERIPHERAL_CLOCK_PWM, + PERIPHERAL_CLOCK_CAM, }; void system_clock_init(void); diff --git a/drivers/bl702_driver/hal_drv/inc/hal_dma.h b/drivers/bl702_driver/hal_drv/inc/hal_dma.h index 297f5bbd..c7041272 100644 --- a/drivers/bl702_driver/hal_drv/inc/hal_dma.h +++ b/drivers/bl702_driver/hal_drv/inc/hal_dma.h @@ -107,8 +107,16 @@ enum dma_index_type #define DMA_REQUEST_SPI0_TX 0x0000000B /*!< DMA request peripheral:SPI TX */ #define DMA_REQUEST_I2S_RX 0x00000014 /*!< DMA request peripheral:I2S RX */ #define DMA_REQUEST_I2S_TX 0x00000015 /*!< DMA request peripheral:I2S TX */ -#define DMA_REQUEST_ADC0 0x00000016 /*!< DMA request peripheral:GPADC0 */ -#define DMA_REQUEST_DAC0 0x00000017 /*!< DMA request peripheral:GPADC1 */ +#define DMA_REQUEST_ADC0 0x00000016 /*!< DMA request peripheral:ADC0 */ +#define DMA_REQUEST_DAC0 0x00000017 /*!< DMA request peripheral:DAC0 */ +#define DMA_REQUEST_USB_EP0 0x00000018 /*!< DMA request peripheral:USB EP0*/ +#define DMA_REQUEST_USB_EP1 0x00000019 /*!< DMA request peripheral:USB EP1*/ +#define DMA_REQUEST_USB_EP2 0x0000001A /*!< DMA request peripheral:USB EP2*/ +#define DMA_REQUEST_USB_EP3 0x0000001B /*!< DMA request peripheral:USB EP3*/ +#define DMA_REQUEST_USB_EP4 0x0000001C /*!< DMA request peripheral:USB EP4*/ +#define DMA_REQUEST_USB_EP5 0x0000001D /*!< DMA request peripheral:USB EP5*/ +#define DMA_REQUEST_USB_EP6 0x0000001E /*!< DMA request peripheral:USB EP6*/ +#define DMA_REQUEST_USB_EP7 0x0000001F /*!< DMA request peripheral:USB EP7 */ #define DMA_BURST_1BYTE 0 #define DMA_BURST_4BYTE 1 diff --git a/drivers/bl702_driver/hal_drv/inc/hal_flash.h b/drivers/bl702_driver/hal_drv/inc/hal_flash.h index 9b95ac16..bf9ed2cc 100644 --- a/drivers/bl702_driver/hal_drv/inc/hal_flash.h +++ b/drivers/bl702_driver/hal_drv/inc/hal_flash.h @@ -27,8 +27,10 @@ #define FLASH_NOT_DETECT 0x10 -int flash_erase(uint32_t addr, uint32_t size); -int flash_read(uint32_t addr, uint8_t *data, uint32_t size); -int flash_write(uint32_t addr, uint8_t *data, uint32_t size); - +int flash_init(void); +int flash_read_jedec_id(uint8_t *data); +BL_Err_Type flash_read_xip(uint32_t addr,uint8_t *data, uint32_t len); +BL_Err_Type flash_write_xip(uint32_t addr, uint8_t *data, uint32_t len); +BL_Err_Type flash_erase_xip(uint32_t startaddr,uint32_t endaddr); +BL_Err_Type flash_set_cache(uint8_t cont_read,uint8_t cache_enable,uint8_t cache_way_disable, uint32_t flash_offset); #endif diff --git a/drivers/bl702_driver/hal_drv/inc/hal_gpio.h b/drivers/bl702_driver/hal_drv/inc/hal_gpio.h index e35a2114..daac42a0 100644 --- a/drivers/bl702_driver/hal_drv/inc/hal_gpio.h +++ b/drivers/bl702_driver/hal_drv/inc/hal_gpio.h @@ -94,6 +94,6 @@ void gpio_set_mode(uint32_t pin, uint32_t mode); void gpio_write(uint32_t pin, uint32_t value); void gpio_toggle(uint32_t pin); int gpio_read(uint32_t pin); -void gpio_attach_irq(uint32_t pin, void (*cbFun)(void)); +void gpio_attach_irq(uint32_t pin, void (*cbfun)(uint32_t pin)); void gpio_irq_enable(uint32_t pin,uint8_t enabled); #endif \ No newline at end of file diff --git a/drivers/bl702_driver/hal_drv/inc/hal_i2c.h b/drivers/bl702_driver/hal_drv/inc/hal_i2c.h index 2d2e3c23..c48d57ac 100644 --- a/drivers/bl702_driver/hal_drv/inc/hal_i2c.h +++ b/drivers/bl702_driver/hal_drv/inc/hal_i2c.h @@ -30,9 +30,6 @@ enum i2c_index_type { #ifdef BSP_USING_I2C0 I2C0_INDEX, -#endif -#ifdef BSP_USING_I2C1 - I2C1_INDEX, #endif I2C_MAX_INDEX }; diff --git a/drivers/bl702_driver/hal_drv/inc/hal_mjpeg.h b/drivers/bl702_driver/hal_drv/inc/hal_mjpeg.h new file mode 100644 index 00000000..58e685c3 --- /dev/null +++ b/drivers/bl702_driver/hal_drv/inc/hal_mjpeg.h @@ -0,0 +1,69 @@ +/** + * @file hal_mjpeg.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_MJPEG__H__ +#define __HAL_MJPEG__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +#define MJPEG_PACKET_ADD_NONE 0 +#define MJPEG_PACKET_ADD_DEFAULT 1 << 0 +#define MJPEG_PACKET_ADD_FRAME_HEAD 1 << 1 +#define MJPEG_PACKET_ADD_FRAME_TAIL 1 << 2 +#define MJPEG_PACKET_ADD_END_TAIL 1 << 3 +/** + * @brief MJPEG YUV format definition + */ +typedef enum { + MJPEG_YUV_FORMAT_YUV420, /*!< MJPEG YUV420 planar mode */ + MJPEG_YUV_FORMAT_YUV400, /*!< MJPEG YUV400 grey scale mode */ + MJPEG_YUV_FORMAT_YUV422_PLANAR, /*!< MJPEG YUV422 planar mode */ + MJPEG_YUV_FORMAT_YUV422_INTERLEAVE, /*!< MJPEG YUV422 interleave mode */ +}mjpeg_yuv_format_t; + +typedef struct mjpeg_device +{ + struct device parent; + uint8_t quality; + mjpeg_yuv_format_t yuv_format; + uint32_t write_buffer_addr; /*!< MJPEG buffer addr */ + uint32_t write_buffer_size; /*!< MJPEG buffer size */ + uint32_t read_buffer_addr; + uint32_t read_buffer_size; + uint16_t resolution_x; /*!< CAM RESOLUTION X */ + uint16_t resolution_y; /*!< CAM RESOLUTION Y */ + + uint8_t packet_cut_mode; + uint16_t frame_head_length; + uint16_t packet_head_length; + uint16_t packet_body_length; + uint16_t packet_tail_length; +} mjpeg_device_t; + +void mjpeg_init(mjpeg_device_t *mjpeg_cfg); +void mjpeg_start(void); +void mjpeg_stop(void); +uint8_t mjpeg_get_one_frame(uint8_t **pic, uint32_t *len, uint8_t *q); +void mjpeg_drop_one_frame(void); + +#endif \ No newline at end of file diff --git a/drivers/bl702_driver/hal_drv/inc/hal_mtimer.h b/drivers/bl702_driver/hal_drv/inc/hal_mtimer.h index d2d59fd0..b0574f70 100644 --- a/drivers/bl702_driver/hal_drv/inc/hal_mtimer.h +++ b/drivers/bl702_driver/hal_drv/inc/hal_mtimer.h @@ -25,14 +25,9 @@ #include "stdint.h" -void mtimer_init(void); -void mtimer_deinit(void); -void mtimer_start(void); -void mtimer_stop(); -void mtimer_clear_time(void); +void mtimer_set_alarm_time(uint64_t ticks, void (*interruptfun)(void)); uint64_t mtimer_get_time_ms(); uint64_t mtimer_get_time_us(); void mtimer_delay_ms(uint32_t time); void mtimer_delay_us(uint32_t time); -void mtimer_set_alarm_time(uint64_t time, void (*interruptFun)(void)); #endif \ No newline at end of file diff --git a/drivers/bl702_driver/hal_drv/inc/hal_power.h b/drivers/bl702_driver/hal_drv/inc/hal_power.h new file mode 100644 index 00000000..c4134230 --- /dev/null +++ b/drivers/bl702_driver/hal_drv/inc/hal_power.h @@ -0,0 +1,56 @@ +/** + * @file hal_pwm.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_POWER__H__ +#define __HAL_POWER__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +typedef enum +{ + CLOCK_AHB_UART0_GATE = 0x10, + CLOCK_AHB_UART1_GATE = 0x11, + CLOCK_AHB_SPI_GATE = 0x12, + CLOCK_AHB_I2C_GATE = 0x13, + CLOCK_AHB_PWM_GATE = 0x14, + CLOCK_AHB_TMR_GATE = 0x15, + CLOCK_AHB_IRR_GATE = 0x16, + CLOCK_AHB_CKS_GATE = 0x17, + CLOCK_AHB_QDEC_GATE = 0x18, + CLOCK_AHB_KYS_GATE = 0x19, + CLOCK_AHB_I2S_GATE = 0x1A, + CLOCK_AHB_USB_GATE = 0x1C, + CLOCK_AHB_CAM_GATE = 0x1D, + CLOCK_AHB_MJPEG_GATE = 0x1E, + CLOCK_AHB_ALL = 0x1F, +}Clock_Gate_Type; + +int lp_set_clock_gate(uint8_t enable , Clock_Gate_Type clockType); +void lp_set_all_gpio_hz(void); +void lp_power_off_dll(void); + +int lp_enter_wfi(void); +int lp_enter_pds(uint32_t sleep_time ,void (*preCbFun)(void),void (*postCbFun)(void)); +int lp_enter_hbn(uint32_t sleepTime); + +#endif diff --git a/drivers/bl702_driver/hal_drv/inc/hal_pwm.h b/drivers/bl702_driver/hal_drv/inc/hal_pwm.h index 876a1ae4..04f66ca5 100644 --- a/drivers/bl702_driver/hal_drv/inc/hal_pwm.h +++ b/drivers/bl702_driver/hal_drv/inc/hal_pwm.h @@ -26,6 +26,7 @@ #include "drv_device.h" #include "bl702_config.h" +#define DEIVCE_CTRL_PWM_IT_PULSE_COUNT_CONFIG 0x10 enum pwm_index_type { @@ -47,17 +48,29 @@ enum pwm_index_type PWM_MAX_INDEX }; +#define pwm_channel_start(dev) device_control(dev,DEVICE_CTRL_RESUME,NULL) +#define pwm_channel_stop(dev) device_control(dev,DEVICE_CTRL_SUSPEND,NULL) +#define pwm_channel_update(dev,cfg) device_control(dev,DEVICE_CTRL_CONFIG,cfg) +#define pwm_it_pulse_count_update(dev,count) device_control(dev,DEIVCE_CTRL_PWM_IT_PULSE_COUNT_CONFIG,(void*)count) + +enum pwm_event_type +{ + PWM_EVENT_COMPLETE, +}; + typedef struct { uint32_t frequency; - uint8_t dutyCycle; + uint8_t dutycycle; } pwm_config_t; + typedef struct pwm_device { struct device parent; uint8_t ch; uint32_t frequency; - uint8_t dutyCycle; + uint8_t dutycycle; + uint16_t it_pulse_count; } pwm_device_t; #define PWM_DEV(dev) ((pwm_device_t*)dev) diff --git a/drivers/bl702_driver/hal_drv/inc/hal_sec_aes.h b/drivers/bl702_driver/hal_drv/inc/hal_sec_aes.h new file mode 100644 index 00000000..f692cb03 --- /dev/null +++ b/drivers/bl702_driver/hal_drv/inc/hal_sec_aes.h @@ -0,0 +1,58 @@ +/** + * @file hal_sec_aes.h + * @brief + * + * Copyright 2019-2030 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_SEC_AES__H__ +#define __HAL_SEC_AES__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +typedef enum{ + SEC_ASE_CBC, + SEC_ASE_CTR, + SEC_ASE_ECB +}sec_aes_type; + +typedef enum{ + SEC_ASE_KEY_128, + SEC_ASE_KEY_256, + SEC_ASE_KEY_192 +}sec_aes_key_type; + +typedef struct sec_aes_handle_t +{ + sec_aes_type aes_type; + sec_aes_key_type key_type; +}sec_aes_handle_t; + +typedef enum{ + SEC_AES_DIR_ENCRYPT, + SEC_AES_DIR_DECRYPT +}sec_aes_dir_type; + +int sec_aes_init(sec_aes_handle_t *handle,sec_aes_type aes_tye,sec_aes_key_type key_type); +int sec_aes_setkey(sec_aes_handle_t *handle,const uint8_t *key,uint8_t key_len,const uint8_t *nonce,uint8_t dir); +int sec_aes_encrypt(sec_aes_handle_t *handle,const uint8_t *in,uint32_t len, size_t offset,uint8_t *out); +int sec_aes_decrypt(sec_aes_handle_t *handle,const uint8_t *in,uint32_t len, size_t offset,uint8_t *out); +int sec_aes_deinit(sec_aes_handle_t *handle); + +#endif \ No newline at end of file diff --git a/drivers/bl702_driver/hal_drv/inc/hal_sec_dsa.h b/drivers/bl702_driver/hal_drv/inc/hal_sec_dsa.h new file mode 100644 index 00000000..9a2cd5e5 --- /dev/null +++ b/drivers/bl702_driver/hal_drv/inc/hal_sec_dsa.h @@ -0,0 +1,59 @@ +/** + * @file hal_sec_dsa.h + * @brief + * + * Copyright 2019-2030 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_SEC_DSA__H__ +#define __HAL_SEC_DSA__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +typedef struct sec_dsa_crt_cfg_tag +{ + uint32_t *dP; + uint32_t *dQ; + uint32_t *qInv; + uint32_t *p; + uint32_t *invR_p; + uint32_t *primeN_p; + uint32_t *q; + uint32_t *invR_q; + uint32_t *primeN_q; +}sec_dsa_crt_cfg_t; + +typedef struct{ + uint32_t size; + uint32_t crtSize; + uint32_t *n; + uint32_t *e; + uint32_t *d; + sec_dsa_crt_cfg_t crtCfg; +}sec_dsa_handle_t; + +int sec_dsa_init(sec_dsa_handle_t * handle,uint32_t size); +int sec_dsa_mexp_binary(uint32_t size,const uint32_t *a,const uint32_t *b,const uint32_t *c,uint32_t *r); +int sec_dsa_mexp_mont(uint32_t size,uint32_t *a,uint32_t *b,uint32_t *c,uint32_t *invR_c,uint32_t *primeN_c,uint32_t *r); +int sec_dsa_decrypt_crt(uint32_t size,uint32_t *c,sec_dsa_crt_cfg_t *crtCfg,uint32_t *d,uint32_t *r); +int sec_dsa_sign(sec_dsa_handle_t * handle,const uint32_t *hash,uint32_t hashLenInWord,uint32_t *s); +int sec_dsa_verify(sec_dsa_handle_t * handle,const uint32_t *hash,uint32_t hashLenInWord,const uint32_t *s); + + +#endif \ No newline at end of file diff --git a/drivers/bl702_driver/hal_drv/inc/hal_sec_ecdsa.h b/drivers/bl702_driver/hal_drv/inc/hal_sec_ecdsa.h new file mode 100644 index 00000000..a0cbe4d3 --- /dev/null +++ b/drivers/bl702_driver/hal_drv/inc/hal_sec_ecdsa.h @@ -0,0 +1,57 @@ +/** + * @file hal_sec_ecdsa.h + * @brief + * + * Copyright 2019-2030 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_SEC_ECDSA__H__ +#define __HAL_SEC_ECDSA__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +typedef enum{ + ECP_SECP256R1=0, +}sec_ecp_type; + +typedef struct{ + sec_ecp_type ecpId; + uint32_t *privateKey; + uint32_t *publicKeyx; + uint32_t *publicKeyy; +}sec_ecdsa_handle_t; + +typedef struct{ + sec_ecp_type ecpId; +}sec_ecdh_handle_t; + +int sec_ecdsa_init(sec_ecdsa_handle_t * handle,sec_ecp_type id); +int sec_ecdsa_deinit(sec_ecdsa_handle_t * handle); +int sec_ecdsa_sign(sec_ecdsa_handle_t * handle,const uint32_t *random_k,const uint32_t *hash,uint32_t hashLenInWord,uint32_t *r,uint32_t *s); +int sec_ecdsa_verify(sec_ecdsa_handle_t * handle,const uint32_t *hash, uint32_t hashLen,const uint32_t *r, const uint32_t *s); +int sec_ecdsa_get_private_key(sec_ecdsa_handle_t * handle,uint32_t *private_key); +int sec_ecdsa_get_public_key(sec_ecdsa_handle_t * handle,const uint32_t *private_key,const uint32_t *pRx,const uint32_t *pRy); + +int sec_ecdh_init(sec_ecdh_handle_t * handle,sec_ecp_type id); +int sec_ecdh_deinit(sec_ecdh_handle_t * handle); +int sec_ecdh_get_encrypt_key(sec_ecdh_handle_t *handle,const uint32_t *pkX,const uint32_t *pkY,const uint32_t *private_key,const uint32_t *pRx,const uint32_t *pRy); +int sec_ecdh_get_public_key(sec_ecdh_handle_t *handle,const uint32_t *private_key,const uint32_t *pRx,const uint32_t *pRy); +int sec_ecc_get_random_value(uint32_t *randomData,uint32_t *maxRef,uint32_t size); + +#endif \ No newline at end of file diff --git a/drivers/bl702_driver/hal_drv/inc/hal_sec_hash.h b/drivers/bl702_driver/hal_drv/inc/hal_sec_hash.h new file mode 100644 index 00000000..da3095ab --- /dev/null +++ b/drivers/bl702_driver/hal_drv/inc/hal_sec_hash.h @@ -0,0 +1,55 @@ +/** + * @file hal_sec_hash.h + * @brief + * + * Copyright 2019-2030 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __HAL_SEC_HASH__H__ +#define __HAL_SEC_HASH__H__ + +#include "drv_device.h" +#include "bl702_config.h" + +enum sec_hash_index_type +{ + SEC_HASH0_INDEX, + SEC_HASH_MAX_INDEX +}; + +enum sec_hash_type +{ + SEC_HASH_SHA1, + SEC_HASH_SHA224, + SEC_HASH_SHA256, + SEC_HASH_SHA384, + SEC_HASH_SHA512, + SEC_HASH_UNKNOWN +}; + +typedef struct sec_hash_device +{ + struct device parent; + uint32_t shaBuf[64/4]; /*!< Data not processed but in this temp buffer */ + uint32_t shaPadding[64/4]; /*!< Padding data */ + uint8_t type; /*!< Sha has feed data */ +} sec_hash_device_t; + +int sec_hash_register(enum sec_hash_index_type index, const char *name, uint16_t flag); + +#endif \ No newline at end of file diff --git a/drivers/bl702_driver/hal_drv/inc/hal_spi.h b/drivers/bl702_driver/hal_drv/inc/hal_spi.h index f79a3d7f..4a71b960 100644 --- a/drivers/bl702_driver/hal_drv/inc/hal_spi.h +++ b/drivers/bl702_driver/hal_drv/inc/hal_spi.h @@ -75,6 +75,13 @@ enum spi_index_type #define SPI_TRANSFER_TPYE_24BIT 2 #define SPI_TRANSFER_TYPE_32BIT 3 +enum spi_event_type +{ + SPI_EVENT_TX_FIFO, + SPI_EVENT_RX_FIFO, + SPI_EVENT_UNKNOWN +}; + typedef struct spi_device { struct device parent; diff --git a/drivers/bl702_driver/hal_drv/inc/hal_timer.h b/drivers/bl702_driver/hal_drv/inc/hal_timer.h index c8ea6391..b8ea3489 100644 --- a/drivers/bl702_driver/hal_drv/inc/hal_timer.h +++ b/drivers/bl702_driver/hal_drv/inc/hal_timer.h @@ -26,6 +26,12 @@ #include "drv_device.h" #include "bl702_config.h" +#define DEVICE_OFLAG_INT 0x01 +#define DEVICE_OFLAG_POLL 0x02 +#define DEVICE_CTRL_TIMER_CH_START 0x80 +#define DEVICE_CTRL_TIMER_CH_STOP 0x81 +#define DEVICE_CTRL_GET_MATCH_STATUS 0x82 + enum timer_index_type { #ifdef BSP_USING_TIMER_CH0 @@ -73,6 +79,7 @@ typedef enum{ typedef struct { uint32_t timeout_val; + uint32_t comp_it; }timer_user_cfg_t; @@ -88,7 +95,7 @@ typedef struct timer_device #define TIMER_DEV(dev) ((timer_device_t*)dev) -int timer_register(enum timer_index_type index, const char *name, uint16_t flag, timer_user_cfg_t *timer_user_cfg); +int timer_register(enum timer_index_type index, const char *name, uint16_t flag); #endif \ No newline at end of file diff --git a/drivers/bl702_driver/hal_drv/inc/hal_uart.h b/drivers/bl702_driver/hal_drv/inc/hal_uart.h index 7f580bc1..19f9d534 100644 --- a/drivers/bl702_driver/hal_drv/inc/hal_uart.h +++ b/drivers/bl702_driver/hal_drv/inc/hal_uart.h @@ -36,15 +36,6 @@ enum uart_index_type #endif #ifdef BSP_USING_UART1 UART1_INDEX, -#endif -#ifdef BSP_USING_UART2 - UART2_INDEX, -#endif -#ifdef BSP_USING_UART3 - UART3_INDEX, -#endif -#ifdef BSP_USING_UART4 - UART4_INDEX, #endif UART_MAX_INDEX }; @@ -70,8 +61,8 @@ typedef enum typedef enum { UART_STOP_ONE = 0, /*!< One stop bit */ - UART_STOP_ONE_D_FIVE = 0, /*!< 1.5 stop bit */ - UART_STOP_TWO = 1 /*!< Two stop bits */ + UART_STOP_ONE_D_FIVE = 1, /*!< 1.5 stop bit */ + UART_STOP_TWO = 2 /*!< Two stop bits */ } uart_stopbits_t; /*! diff --git a/drivers/bl702_driver/hal_drv/inc/hal_usb.h b/drivers/bl702_driver/hal_drv/inc/hal_usb.h index 1b83f607..bf4dcc43 100644 --- a/drivers/bl702_driver/hal_drv/inc/hal_usb.h +++ b/drivers/bl702_driver/hal_drv/inc/hal_usb.h @@ -38,6 +38,8 @@ #define DEVICE_CTRL_USB_DC_GET_TX_FIFO_CNT 0x18 #define DEVICE_CTRL_USB_DC_GET_RX_FIFO_CNT 0x19 #define DEVICE_CTRL_USB_DC_GET_EP_FREE 0x20 +#define DEVICE_CTRL_USB_DC_SET_TX_DMA 0x21 +#define DEVICE_CTRL_USB_DC_SET_RX_DMA 0x22 enum usb_index_type { @@ -207,6 +209,8 @@ typedef struct usb_dc_device uint8_t id; usb_dc_ep_state_t in_ep[8]; /*!< IN endpoint parameters */ usb_dc_ep_state_t out_ep[8]; /*!< OUT endpoint parameters */ + void *tx_dma; + void *rx_dma; } usb_dc_device_t; int usb_dc_register(enum usb_index_type index, const char *name, uint16_t flag); diff --git a/drivers/bl702_driver/hal_drv/src/hal_adc.c b/drivers/bl702_driver/hal_drv/src/hal_adc.c index 7cf5c933..55e82c8b 100644 --- a/drivers/bl702_driver/hal_drv/src/hal_adc.c +++ b/drivers/bl702_driver/hal_drv/src/hal_adc.c @@ -22,14 +22,15 @@ */ #include "hal_adc.h" #include "hal_gpio.h" +#include "hal_clock.h" #include "bl702_glb.h" #include "bl702_dma.h" #include "bl702_adc.h" #include "adc_config.h" -adc_device_t adcx_device[ADC_MAX_INDEX] = { +static adc_device_t adcx_device[ADC_MAX_INDEX] = { #ifdef BSP_USING_ADC0 - ADC_CONFIG, + ADC0_CONFIG, #endif }; @@ -43,40 +44,17 @@ adc_device_t adcx_device[ADC_MAX_INDEX] = { int adc_open(struct device *dev, uint16_t oflag) { adc_device_t *adc_device = (adc_device_t *)dev; - adc_user_cfg_t *adc_user_cfg = ((adc_user_cfg_t *)(adc_device->parent.handle)); - ADC_CFG_Type adc_cfg; - ADC_FIFO_Cfg_Type adc_fifo_cfg; + ADC_CFG_Type adc_cfg = {0}; + ADC_FIFO_Cfg_Type adc_fifo_cfg = {0}; ADC_Disable(); ADC_Reset(); - GLB_GPIO_Func_Init(GPIO_FUN_ANALOG, (GLB_GPIO_Type *)adc_user_cfg->pinList, adc_user_cfg->num); + adc_cfg.clkDiv = adc_device->clk_div; - switch (adc_device->clk) - { - case ADC_CLK_500KHZ: - GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1); - adc_cfg.clkDiv = ADC_CLK_DIV_32; - break; - case ADC_CLK_1MHZ: - GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1); - adc_cfg.clkDiv = ADC_CLK_DIV_16; - break; - case ADC_CLK_1P3MHZ: - GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 2); - adc_cfg.clkDiv = ADC_CLK_DIV_8; - break; - case ADC_CLK_2MHZ: - GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1); - adc_cfg.clkDiv = ADC_CLK_DIV_8; - break; - default: - break; - } - adc_cfg.vref = adc_device->vref; - adc_cfg.resWidth = adc_device->resWidth; - adc_cfg.inputMode = adc_user_cfg->in_mode; + adc_cfg.resWidth = adc_device->data_width; + adc_cfg.inputMode = adc_device->differential_mode; adc_cfg.v18Sel = ADC_V18_SELECT; adc_cfg.v11Sel = ADC_V11_SELECT; @@ -88,35 +66,31 @@ int adc_open(struct device *dev, uint16_t oflag) adc_cfg.offsetCalibEn = ADC_OFFSET_CALIB_EN; adc_cfg.offsetCalibVal = ADC_OFFSER_CALIB_VAL; - if(adc_user_cfg->dma_en) + adc_fifo_cfg.dmaEn = DISABLE; + + if (oflag & DEVICE_OFLAG_STREAM_TX) + { + } + if ((oflag & DEVICE_OFLAG_INT_TX) || (oflag & DEVICE_OFLAG_INT_RX)) + { + + } + if (oflag & DEVICE_OFLAG_DMA_TX) + { + + } + if (oflag & DEVICE_OFLAG_DMA_RX) { adc_fifo_cfg.dmaEn = ENABLE; } - else - { - adc_fifo_cfg.dmaEn = DISABLE; - } - adc_fifo_cfg.fifoThreshold = ADC_FIFO_THRESHOLD_1; + + adc_fifo_cfg.fifoThreshold = adc_device->fifo_threshold; ADC_Init(&adc_cfg); - if(adc_user_cfg->num == 1) - { - ADC_Channel_Config((ADC_Chan_Type)adc_user_cfg->posChList[0],(ADC_Chan_Type)adc_user_cfg->negChList[0], adc_user_cfg->conv_mode); - } - else if(adc_user_cfg->num > 1) - { - ADC_Scan_Channel_Config((ADC_Chan_Type*)(adc_user_cfg->posChList), (ADC_Chan_Type*)(adc_user_cfg->negChList),adc_user_cfg->num,adc_user_cfg->conv_mode); - } - + ADC_FIFO_Cfg(&adc_fifo_cfg); - if((ADC_Chan_Type)adc_user_cfg->posChList[0] == ADC_CHAN_VABT_HALF) - { - ADC_Vbat_Enable(); - } - ADC_Enable(); - return 0; } /** @@ -140,7 +114,8 @@ int adc_close(struct device *dev) */ int adc_control(struct device *dev, int cmd, void *args) { - //adc_device_t *adc_device = (adc_device_t *)dev; + adc_device_t* adc_device = (adc_device_t *)dev; + adc_channel_cfg_t* adc_channel_cfg = (adc_channel_cfg_t *)args; switch (cmd) { @@ -148,8 +123,6 @@ int adc_control(struct device *dev, int cmd, void *args) break; case DEVICE_CTRL_CLR_INT /* constant-expression */: - /* code */ - /* Enable UART interrupt*/ break; case DEVICE_CTRL_GET_INT /* constant-expression */: @@ -158,13 +131,33 @@ int adc_control(struct device *dev, int cmd, void *args) case DEVICE_CTRL_CONFIG /* constant-expression */: /* code */ break; - case DEVICE_CTRL_RESUME /* constant-expression */: + case DEVICE_CTRL_ADC_CHANNEL_CONFIG /* constant-expression */: + if(adc_channel_cfg->num == 1) + ADC_Channel_Config(*adc_channel_cfg->pos_channel,*adc_channel_cfg->neg_channel,adc_device->continuous_conv_mode); + else + { + ADC_Scan_Channel_Config(adc_channel_cfg->pos_channel, adc_channel_cfg->neg_channel,adc_channel_cfg->num,adc_device->continuous_conv_mode); + } + break; + case DEVICE_CTRL_ADC_CHANNEL_START /* constant-expression */: /* code */ ADC_Start(); break; - case DEVICE_CTRL_SUSPEND /* constant-expression */: + case DEVICE_CTRL_ADC_CHANNEL_STOP /* constant-expression */: /* code */ ADC_Stop(); + break; + case DEVICE_CTRL_ADC_VBAT_ON: + ADC_Vbat_Enable(); + break; + case DEVICE_CTRL_ADC_VBAT_OFF: + ADC_Vbat_Disable(); + break; + case DEVICE_CTRL_ADC_TSEN_ON: + ADC_Tsen_Init(ADC_TSEN_MOD_INTERNAL_DIODE); + break; + case DEVICE_CTRL_ADC_TSEN_OFF: + break; default: break; @@ -205,6 +198,17 @@ int adc_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) } return 0; } + +int adc_trim_tsen(uint16_t * tsen_offset) +{ + return ADC_Trim_TSEN(tsen_offset); +} + +float adc_get_tsen(uint16_t tsen_offset) +{ + return TSEN_Get_Temp(tsen_offset); +} + /** * @brief * @@ -214,7 +218,7 @@ int adc_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) * @param adc_user_cfg * @return int */ -int adc_register(enum adc_index_type index, const char *name, uint16_t flag, adc_user_cfg_t *adc_user_cfg) +int adc_register(enum adc_index_type index, const char *name, uint16_t flag) { struct device *dev; @@ -231,7 +235,7 @@ int adc_register(enum adc_index_type index, const char *name, uint16_t flag, adc dev->status = DEVICE_UNREGISTER; dev->type = DEVICE_CLASS_ADC; - dev->handle = adc_user_cfg; + dev->handle = NULL; return device_register(dev, name, flag); } diff --git a/drivers/bl702_driver/hal_drv/src/hal_cam.c b/drivers/bl702_driver/hal_drv/src/hal_cam.c new file mode 100644 index 00000000..4846a41f --- /dev/null +++ b/drivers/bl702_driver/hal_drv/src/hal_cam.c @@ -0,0 +1,148 @@ +/** + * @file hal_cam.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "bl702_cam.h" +#include "bl702_glb.h" +#include "hal_cam.h" + +/** + * @brief + * + * @param cam_cfg + */ +void cam_init(cam_device_t *cam_cfg) +{ + CAM_CFG_Type camera_cfg = + { + .swMode = cam_cfg->software_mode, + .swIntCnt = 0, + .frameMode = cam_cfg->frame_mode, + .yuvMode = cam_cfg->yuv_format, + .waitCount = 0x40, + .linePol = CAM_LINE_ACTIVE_POLARITY_HIGH, + .framePol = CAM_FRAME_ACTIVE_POLARITY_HIGH, + .burstType = CAM_BURST_TYPE_INCR16, + .camSensorMode = CAM_SENSOR_MODE_V_AND_H, + .memStart0 = cam_cfg->cam_write_ram_addr, + .memSize0 = cam_cfg->cam_write_ram_size, + .frameSize0 = cam_cfg->cam_frame_size, + /* planar mode*/ + .memStart1 = cam_cfg->cam_write_ram_addr1, + .memSize1 = cam_cfg->cam_write_ram_size1, + .frameSize1 = cam_cfg->cam_frame_size1, + }; + CAM_Init(&camera_cfg); +} + +/** + * @brief + * + */ +void cam_start(void) +{ + CAM_Enable(); +} + +/** + * @brief + * + */ +void cam_stop(void) +{ + CAM_Disable(); +} + +/** + * @brief + * + * @param pic + * @param len + */ +uint8_t cam_get_one_frame_interleave(uint8_t **pic, uint32_t *len) +{ + CAM_Interleave_Frame_Info info; + arch_memset(&info, 0, sizeof(info)); + + CAM_Interleave_Get_Frame_Info(&info); + + if(info.validFrames == 0) + { + return ERROR; + } + + *pic = (uint8_t *)(info.curFrameAddr); + *len = info.curFrameBytes; + + return SUCCESS; +} + +uint8_t cam_get_one_frame_planar(CAM_YUV_Mode_Type yuv, uint8_t **picYY, uint32_t *lenYY, uint8_t **picUV, uint32_t *lenUV) +{ + CAM_Planar_Frame_Info info; + arch_memset(&info, 0, sizeof(info)); + + CAM_Planar_Get_Frame_Info(&info); + + if(yuv == CAM_YUV400_EVEN || yuv == CAM_YUV400_ODD) + { + if(info.validFrames0 == 0 && info.validFrames1 == 0) + { + return ERROR; + } + } + else + { + if(info.validFrames0 == 0 || info.validFrames1 == 0) + { + return ERROR; + } + } + + *picYY = (uint8_t*)(info.curFrameAddr0); + *lenYY = info.curFrameBytes0; + *picUV = (uint8_t*)(info.curFrameAddr1); + *lenUV = info.curFrameBytes1; + + return SUCCESS; +} + +void cam_drop_one_frame_interleave(void) +{ + CAM_Interleave_Pop_Frame(); +} + +void cam_drop_one_frame_planar(void) +{ + CAM_Planar_Pop_Frame(); +} + +void cam_hsync_crop(uint16_t start, uint16_t end) +{ + CAM_Hsync_Crop(start, end); +} + +void cam_vsync_crop(uint16_t start, uint16_t end) +{ + CAM_Vsync_Crop(start, end); +} + diff --git a/drivers/bl702_driver/hal_drv/src/hal_camera.c b/drivers/bl702_driver/hal_drv/src/hal_camera.c deleted file mode 100644 index f3850052..00000000 --- a/drivers/bl702_driver/hal_drv/src/hal_camera.c +++ /dev/null @@ -1,1874 +0,0 @@ -/** - * @file hal_camera.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_camera.h" -#include "bl702_i2c.h" -#include "bl702_gpio.h" -#include "bl702_glb.h" -#include "bl702_psram.h" -#include "bl702_l1c.h" -#include "bl702_timer.h" - -/** @addtogroup Image_Sensor_Driver - * @{ - */ - -/** @addtogroup IMAGE_SENSOR - * @{ - */ - -/** @defgroup IMAGE_SENSOR_Private_Macros - * @{ - */ -#define BFLB_EXTPSRAM_CLK_GPIO GLB_GPIO_PIN_27 -#define BFLB_EXTPSRAM_CS_GPIO GLB_GPIO_PIN_17 -#define BFLB_EXTPSRAM_DATA0_GPIO GLB_GPIO_PIN_28 -#define BFLB_EXTPSRAM_DATA1_GPIO GLB_GPIO_PIN_24 -#define BFLB_EXTPSRAM_DATA2_GPIO GLB_GPIO_PIN_23 -#define BFLB_EXTPSRAM_DATA3_GPIO GLB_GPIO_PIN_26 -#if (IMAGE_SENSOR_USE == IMAGE_SENSOR_BF2013) -#define I2C_CAMERA_ADDR 0x6E -#define BF2013_ID_MSB 0xFC -#define BF2013_ID_LSB 0xFD -#elif (IMAGE_SENSOR_USE == IMAGE_SENSOR_GC0308) -#define I2C_CAMERA_ADDR 0x21 -#define GC0308_ID 0x00 -#endif - -void ClkOutInit(void) -{ - uint8_t CLKPins[] = {GLB_GPIO_PIN_9}; - GLB_Set_I2S_CLK(ENABLE, GLB_I2S_OUT_REF_CLK_NONE); - PDS_Set_Audio_PLL_Freq(AUDIO_PLL_24576000_HZ); - GLB_GPIO_Func_Init(0, CLKPins, sizeof(CLKPins) / sizeof(CLKPins[0])); - GLB_Set_Chip_Out_1_CLK_Sel(GLB_CHIP_CLK_OUT_I2S_REF_CLK); -} - -CAM_CFG_Type cameraCfg = - { - .swMode = CAM_SW_MODE_AUTO, - .swIntCnt = 0, - .frameMode = CAM_INTERLEAVE_MODE, -#if (YUV_USE == 1) - .yuvMode = CAM_YUV422, -#else - .yuvMode = CAM_YUV400_ODD, -#endif - .linePol = CAM_LINE_ACTIVE_POLARITY_HIGH, - .framePol = CAM_FRAME_ACTIVE_POLARITY_HIGH, - .camSensorMode = CAM_SENSOR_MODE_V_AND_H, - .burstType = CAM_BURST_TYPE_INCR16, - .waitCount = 0x40, - .memStart0 = MJPEG_READ_ADDR, - .memSize0 = CAMERA_BUFFER_SIZE_WHEN_MJPEG, - .frameSize0 = CAMERA_FRAME_SIZE, - .memStart1 = 0, - .memSize1 = 0, - .frameSize1 = 0, -}; - -MJPEG_CFG_Type mjpegCfg = - { - .burst = MJPEG_BURST_INCR16, - .quality = 10, -#if (YUV_USE == 1) - .yuv = MJPEG_YUV422_INTERLEAVE, -#else - .yuv = MJPEG_YUV400, -#endif - .waitCount = 0x400, - .bufferMjpeg = MJPEG_WRITE_ADDR, - .sizeMjpeg = MJPEG_WRITE_SIZE, - .bufferCamYY = MJPEG_READ_ADDR, - .sizeCamYY = MJPEG_READ_SIZE, - .bufferCamUV = 0, - .sizeCamUV = 0, - .resolutionX = CAMERA_RESOLUTION_X, - .resolutionY = CAMERA_RESOLUTION_Y, - .bitOrderEnable = ENABLE, - .evenOrderEnable = ENABLE, - .swapModeEnable = DISABLE, - .overStopEnable = ENABLE, - .reflectDmy = DISABLE, - .verticalDmy = DISABLE, - .horizationalDmy = DISABLE, -}; -GLB_GPIO_Cfg_Type gpio_cfg0 = { - .gpioPin = GLB_GPIO_PIN_22, - .gpioFun = 11, - .gpioMode = GPIO_MODE_OUTPUT, - .pullType = GPIO_PULL_NONE, - .drive = 0, - .smtCtrl = 1}; -TIMER_CFG_Type timerCh0Cfg = { - TIMER_CH0, /* timer channel 0 */ - TIMER_CLKSRC_FCLK, /* timer clock source:bus clock */ - TIMER_PRELOAD_TRIG_COMP2, /* reaload on comaparator 2 */ - TIMER_COUNT_PRELOAD, /* preload when match occur */ - 0, /* clock division value */ - 230000, /* match value 0 */ - 260000, /* match value 1 */ - 14400000, /* match value 2 */ - 0, /* preload value */ -}; -void Test_H(void) -{ - GLB_GPIO_Write(gpio_cfg0.gpioPin, 1); -} -void Test_L(void) -{ - GLB_GPIO_Write(gpio_cfg0.gpioPin, 0); -} -BL_Err_Type Timer_Init(void) -{ - // TIMER_IntMask(timerCh0Cfg.timerCh, TIMER_INT_ALL, MASK); - // TIMER_Disable(timerCh0Cfg.timerCh); - // TIMER_Init(&timerCh0Cfg); - // TIMER_ClearIntStatus(timerCh0Cfg.timerCh, TIMER_COMP_ID_0); - // TIMER_ClearIntStatus(timerCh0Cfg.timerCh, TIMER_COMP_ID_1); - // TIMER_ClearIntStatus(timerCh0Cfg.timerCh, TIMER_COMP_ID_2); - // TIMER_IntMask(timerCh0Cfg.timerCh, TIMER_INT_COMP_0, UNMASK); - // Timer_Int_Callback_Install(timerCh0Cfg.timerCh, TIMER_INT_COMP_0, &Timer_Match0_Cbf); - // NVIC_ClearPendingIRQ((IRQn_Type)(timerCh0Cfg.timerCh + TIMER_CH0_IRQn)); - // NVIC_EnableIRQ((IRQn_Type)(timerCh0Cfg.timerCh + TIMER_CH0_IRQn)); - // TIMER_Enable(timerCh0Cfg.timerCh); - - GLB_GPIO_Write(gpio_cfg0.gpioPin, 0); - GLB_GPIO_Init(&gpio_cfg0); - GLB_GPIO_OUTPUT_Enable(gpio_cfg0.gpioPin); - - return SUCCESS; -} - -static const uint8_t sensorRegList[][2] = - { -#if (IMAGE_SENSOR_USE == IMAGE_SENSOR_BF2013) - {0x12, 0x80}, - {0x67, 0x00}, - {0x68, 0x00}, - //{0xb9, 0x80},//use Test pattern - //{0x69,0x20}, - {0x3a, 0x02}, - {0x09, 0x01}, - {0x15, 0x02}, - {0x12, 0x00}, - {0x1e, 0x00}, - {0x13, 0x00}, - {0x01, 0x14}, - {0x02, 0x21}, - {0x8c, 0x02}, - {0x8d, 0x64}, - {0x87, 0x18}, - {0x13, 0x07}, - //{0x11,0x80},//pclk=mclk - {0x11, 0x30}, //pclk=mclk/8 - {0x2b, 0x20}, - {0x92, 0x40}, - {0x9d, 0x99}, - {0x06, 0xe0}, - {0x29, 0x54}, - {0xeb, 0x30}, - {0xbb, 0x20}, - {0xf5, 0x21}, - {0xe1, 0x3c}, - {0x16, 0x01}, - {0xe0, 0x0b}, - {0x2f, 0xf6}, - {0x33, 0x20}, - {0x34, 0x08}, - {0x35, 0x50}, - {0x65, 0x4a}, - {0x66, 0x50}, - {0x36, 0x05}, - {0x37, 0xf6}, - {0x38, 0x46}, - {0x9b, 0xf6}, - {0x9c, 0x46}, - {0xbc, 0x01}, - {0xbd, 0xf6}, - {0xbe, 0x46}, - {0x82, 0x14}, - {0x83, 0x23}, - {0x9a, 0x23}, - {0x70, 0x6f}, - {0x72, 0x3f}, - {0x73, 0x3f}, - {0x74, 0x27}, - {0x77, 0x90}, - {0x79, 0x48}, - {0x7a, 0x1e}, - {0x7b, 0x30}, - {0x84, 0x1a}, - {0x85, 0x20}, - {0x89, 0x02}, - {0x8a, 0x64}, - {0x86, 0x30}, - {0x96, 0xa6}, - {0x97, 0x0c}, - {0x98, 0x18}, - {0x80, 0x55}, - {0x24, 0x70}, - {0x25, 0x80}, - {0x94, 0x0a}, - {0x1f, 0x20}, - {0x22, 0x20}, - {0x26, 0x20}, - {0x56, 0x40}, - {0x61, 0xd3}, - {0x79, 0x48}, - {0x3b, 0x60}, - {0x3c, 0x20}, - {0x39, 0x80}, - {0x3f, 0xb0}, - {0x39, 0x80}, - {0x40, 0x58}, - {0x41, 0x54}, - {0x42, 0x4e}, - {0x43, 0x44}, - {0x44, 0x3e}, - {0x45, 0x39}, - {0x46, 0x35}, - {0x47, 0x31}, - {0x48, 0x2e}, - {0x49, 0x2b}, - {0x4b, 0x29}, - {0x4c, 0x27}, - {0x4e, 0x23}, - {0x4f, 0x20}, - {0x50, 0x1e}, - {0x51, 0x05}, - {0x52, 0x10}, - {0x53, 0x0b}, - {0x54, 0x15}, - {0x57, 0x87}, - {0x58, 0x72}, - {0x59, 0x5f}, - {0x5a, 0x7e}, - {0x5b, 0x1f}, - {0x5c, 0x0e}, - {0x5d, 0x95}, - {0x60, 0x28}, - {0xb0, 0xe0}, - {0xb1, 0xc0}, - {0xb2, 0xb0}, - {0xb3, 0x88}, - {0x6a, 0x01}, - {0x23, 0x66}, - {0xa0, 0x03}, - {0xa1, 0x31}, - {0xa2, 0x0b}, - {0xa3, 0x26}, - {0xa4, 0x05}, - {0xa5, 0x25}, - {0xa6, 0x06}, - {0xa7, 0x80}, - {0xa8, 0x80}, - {0xa9, 0x20}, - {0xaa, 0x20}, - {0xab, 0x20}, - {0xac, 0x3c}, - {0xad, 0xf0}, - {0xc8, 0x18}, - {0xc9, 0x20}, - {0xca, 0x17}, - {0xcb, 0x1f}, - {0xaf, 0x00}, - {0xc5, 0x18}, - {0xc6, 0x00}, - {0xc7, 0x20}, - {0xae, 0x80}, - {0xcc, 0x40}, - {0xcd, 0x58}, - {0xee, 0x4c}, - {0x8e, 0x07}, - {0x8f, 0x79}, - -#elif (IMAGE_SENSOR_USE == IMAGE_SENSOR_GC0308) - {0xfe, 0x80}, - {0xfe, 0x00}, //set page0 - {0xd2, 0x10}, //close AEC - {0x22, 0x55}, //close AWB - {0x5a, 0x56}, - {0x5b, 0x40}, - {0x5c, 0x4a}, - {0x22, 0x57}, //Open AWB -#if 0 - //config for 39 FPS - {0x01 , 0x6a},//HB 106 - //{0x02 , 0x70},//VB 112 - {0x02 , 0x0c},//change VB from 112 to 12 - {0x0f , 0x00}, - {0xe2 , 0x00},//anti-flicker step [11:8] - {0xe3 , 0x96},//anti-flicker step [7:0] - {0xe4 , 0x01},//exp level 1 50.00fps or 20ms - {0xe5 , 0x2c}, - {0xe6 , 0x03},//exp level 2 16.67fps - {0xe7 , 0x84}, - {0xe8 , 0x04},//exp level 3 12.5fps - {0xe9 , 0xb0}, - {0xea , 0x09},//exp level 4 6.00fps - {0xeb , 0xc4}, -#elif 0 - //config for 33.33 FPS - {0x01, 0x6a}, //HB 106 - {0x02, 0x52}, //VB 82 - {0x0f, 0x00}, - {0xe2, 0x00}, //anti-flicker step [11:8] - {0xe3, 0x96}, //anti-flicker step [7:0] - {0xe4, 0x01}, //exp level 1 33.33fps or 30ms - {0xe5, 0x2c}, - {0xe6, 0x03}, //exp level 2 16.67fps - {0xe7, 0x84}, - {0xe8, 0x04}, //exp level 3 12.5fps - {0xe9, 0xb0}, - {0xea, 0x09}, //exp level 4 6.00fps - {0xeb, 0xc4}, -#else - //config for 25 FPS - {0x01, 0x6a}, //HB 106 - //{0x02 , 0x70},//VB 112 - {0x02, 0xe8}, //change VB from 112 to 232 - {0x0f, 0x00}, - {0xe2, 0x00}, //anti-flicker step [11:8] - {0xe3, 0x96}, //anti-flicker step [7:0] - {0xe4, 0x02}, //exp level 1 25.00fps or 40ms - {0xe5, 0x58}, - {0xe6, 0x03}, //exp level 2 16.67fps - {0xe7, 0x84}, - {0xe8, 0x04}, //exp level 3 12.5fps - {0xe9, 0xb0}, - {0xea, 0x09}, //exp level 4 6.00fps - {0xeb, 0xc4}, -#endif - {0xec, 0x00}, //select max exposure level 1 - highest fps - {0x05, 0x00}, - {0x06, 0x00}, - {0x07, 0x00}, - {0x08, 0x00}, - {0x09, 0x01}, - {0x0a, 0xe8}, - //{0x0a , 0x70},//change win_height from 488 to 368 - {0x0b, 0x02}, - {0x0c, 0x88}, //win_width 648 - {0x0d, 0x02}, - {0x0e, 0x02}, - {0x10, 0x22}, - {0x11, 0xfd}, - {0x12, 0x2a}, - {0x13, 0x00}, - //{0x14 , 0x10}, - {0x14, 0x13}, //enable mirror & flip - //-------------H_V_Switch(4)---------------// - /* - 1://normal - {0x14 , 0x10}, - 2://IMAGE_H_MIRROR - {0x14 , 0x11}, - 3://IMAGE_V_MIRROR - {0x14 , 0x12}, - 4://IMAGE_HV_MIRROR - {0x14 , 0x13},*/ - {0x15, 0x0a}, - {0x16, 0x05}, - {0x17, 0x01}, - {0x18, 0x44}, - {0x19, 0x44}, - {0x1a, 0x1e}, - {0x1b, 0x00}, - {0x1c, 0xc1}, - {0x1d, 0x08}, - {0x1e, 0x60}, - {0x1f, 0x17}, - {0x20, 0xff}, - {0x21, 0xf8}, - {0x22, 0x57}, - {0x24, 0xa0}, //Cb Y Cr Y - {0x25, 0x0f}, - //output sync_mode - //{0x26 , 0x02},//0x03 20101016 zhj - {0x26, 0x03}, //sync mode, high high - {0x2f, 0x01}, - {0x30, 0xf7}, - {0x31, 0x50}, - {0x32, 0x00}, - {0x39, 0x04}, - {0x3a, 0x18}, - {0x3b, 0x20}, - {0x3c, 0x00}, - {0x3d, 0x00}, - {0x3e, 0x00}, - {0x3f, 0x00}, - {0x50, 0x10}, - {0x53, 0x82}, - {0x54, 0x80}, - {0x55, 0x80}, - {0x56, 0x82}, - {0x8b, 0x40}, - {0x8c, 0x40}, - {0x8d, 0x40}, - {0x8e, 0x2e}, - {0x8f, 0x2e}, - {0x90, 0x2e}, - {0x91, 0x3c}, - {0x92, 0x50}, - {0x5d, 0x12}, - {0x5e, 0x1a}, - {0x5f, 0x24}, - {0x60, 0x07}, - {0x61, 0x15}, - {0x62, 0x08}, - {0x64, 0x03}, - {0x66, 0xe8}, - {0x67, 0x86}, - {0x68, 0xa2}, - {0x69, 0x18}, - {0x6a, 0x0f}, - {0x6b, 0x00}, - {0x6c, 0x5f}, - {0x6d, 0x8f}, - {0x6e, 0x55}, - {0x6f, 0x38}, - {0x70, 0x15}, - {0x71, 0x33}, - {0x72, 0xdc}, - {0x73, 0x80}, - {0x74, 0x02}, - {0x75, 0x3f}, - {0x76, 0x02}, - {0x77, 0x36}, - {0x78, 0x88}, - {0x79, 0x81}, - {0x7a, 0x81}, - {0x7b, 0x22}, - {0x7c, 0xff}, - {0x93, 0x48}, - {0x94, 0x00}, - {0x95, 0x05}, - {0x96, 0xe8}, - {0x97, 0x40}, - {0x98, 0xf0}, - {0xb1, 0x38}, - {0xb2, 0x38}, - {0xbd, 0x38}, - {0xbe, 0x36}, -#if 1 - {0xd0, 0xc9}, - {0xd1, 0x10}, - {0xd3, 0x80}, - {0xd5, 0xf2}, - {0xd6, 0x16}, -#else - //default AEC setting - {0xd0, 0xca}, - {0xd1, 0xa1}, - {0xd3, 0xa0}, - {0xd5, 0xf2}, - {0xd6, 0x18}, -#endif - {0xdb, 0x92}, - {0xdc, 0xa5}, - {0xdf, 0x23}, - {0xd9, 0x00}, - {0xda, 0x00}, - {0xe0, 0x09}, - {0xed, 0x04}, -#if 0 - //default max dgain - {0xee , 0xa0}, - {0xef , 0x40}, -#else - //increased max dgain - {0xee, 0xf0}, - {0xef, 0x60}, -#endif - {0x80, 0x03}, - {0x80, 0x03}, - {0x9F, 0x10}, - {0xA0, 0x20}, - {0xA1, 0x38}, - {0xA2, 0x4E}, - {0xA3, 0x63}, - {0xA4, 0x76}, - {0xA5, 0x87}, - {0xA6, 0xA2}, - {0xA7, 0xB8}, - {0xA8, 0xCA}, - {0xA9, 0xD8}, - {0xAA, 0xE3}, - {0xAB, 0xEB}, - {0xAC, 0xF0}, - {0xAD, 0xF8}, - {0xAE, 0xFD}, - {0xAF, 0xFF}, - /* - GC0308_GAMMA_Select, - 1://smallest gamma curve - {0x9F , 0x0B}, - {0xA0 , 0x16}, - {0xA1 , 0x29}, - {0xA2 , 0x3C}, - {0xA3 , 0x4F}, - {0xA4 , 0x5F}, - {0xA5 , 0x6F}, - {0xA6 , 0x8A}, - {0xA7 , 0x9F}, - {0xA8 , 0xB4}, - {0xA9 , 0xC6}, - {0xAA , 0xD3}, - {0xAB , 0xDD}, - {0xAC , 0xE5}, - {0xAD , 0xF1}, - {0xAE , 0xFA}, - {0xAF , 0xFF}, - 2: - {0x9F , 0x0E}, - {0xA0 , 0x1C}, - {0xA1 , 0x34}, - {0xA2 , 0x48}, - {0xA3 , 0x5A}, - {0xA4 , 0x6B}, - {0xA5 , 0x7B}, - {0xA6 , 0x95}, - {0xA7 , 0xAB}, - {0xA8 , 0xBF}, - {0xA9 , 0xCE}, - {0xAA , 0xD9}, - {0xAB , 0xE4}, - {0xAC , 0xEC}, - {0xAD , 0xF7}, - {0xAE , 0xFD}, - {0xAF , 0xFF}, - 3: - {0x9F , 0x10}, - {0xA0 , 0x20}, - {0xA1 , 0x38}, - {0xA2 , 0x4E}, - {0xA3 , 0x63}, - {0xA4 , 0x76}, - {0xA5 , 0x87}, - {0xA6 , 0xA2}, - {0xA7 , 0xB8}, - {0xA8 , 0xCA}, - {0xA9 , 0xD8}, - {0xAA , 0xE3}, - {0xAB , 0xEB}, - {0xAC , 0xF0}, - {0xAD , 0xF8}, - {0xAE , 0xFD}, - {0xAF , 0xFF}, - 4: - {0x9F , 0x14}, - {0xA0 , 0x28}, - {0xA1 , 0x44}, - {0xA2 , 0x5D}, - {0xA3 , 0x72}, - {0xA4 , 0x86}, - {0xA5 , 0x95}, - {0xA6 , 0xB1}, - {0xA7 , 0xC6}, - {0xA8 , 0xD5}, - {0xA9 , 0xE1}, - {0xAA , 0xEA}, - {0xAB , 0xF1}, - {0xAC , 0xF5}, - {0xAD , 0xFB}, - {0xAE , 0xFE}, - {0xAF , 0xFF}, - 5://largest gamma curve - {0x9F , 0x15}, - {0xA0 , 0x2A}, - {0xA1 , 0x4A}, - {0xA2 , 0x67}, - {0xA3 , 0x79}, - {0xA4 , 0x8C}, - {0xA5 , 0x9A}, - {0xA6 , 0xB3}, - {0xA7 , 0xC5}, - {0xA8 , 0xD5}, - {0xA9 , 0xDF}, - {0xAA , 0xE8}, - {0xAB , 0xEE}, - {0xAC , 0xF3}, - {0xAD , 0xFA}, - {0xAE , 0xFD}, - {0xAF , 0xFF}, - */ - //-----------GAMMA Select End--------------// - {0xc0, 0x00}, - {0xc1, 0x10}, - {0xc2, 0x1C}, - {0xc3, 0x30}, - {0xc4, 0x43}, - {0xc5, 0x54}, - {0xc6, 0x65}, - {0xc7, 0x75}, - {0xc8, 0x93}, - {0xc9, 0xB0}, - {0xca, 0xCB}, - {0xcb, 0xE6}, - {0xcc, 0xFF}, - {0xf0, 0x02}, - {0xf1, 0x01}, - {0xf2, 0x01}, - {0xf3, 0x30}, - {0xf9, 0x9f}, - {0xfa, 0x78}, - //{0xfa , 0x58},//Change measure window Y1 from 480 to 352 - //------------------------------------------------- - {0xfe, 0x01}, // set page1 - {0x00, 0xf5}, - {0x02, 0x1a}, - {0x0a, 0xa0}, - {0x0b, 0x60}, - {0x0c, 0x08}, - {0x0e, 0x4c}, - {0x0f, 0x39}, - {0x11, 0x3f}, - {0x12, 0x72}, - {0x13, 0x13}, - {0x14, 0x42}, - {0x15, 0x43}, - {0x16, 0xc2}, - {0x17, 0xa8}, - {0x18, 0x18}, - {0x19, 0x40}, - {0x1a, 0xd0}, - {0x1b, 0xf5}, - {0x70, 0x40}, - {0x71, 0x58}, - {0x72, 0x30}, - {0x73, 0x48}, - {0x74, 0x20}, - {0x75, 0x60}, - {0x77, 0x20}, - {0x78, 0x32}, - {0x30, 0x03}, - {0x31, 0x40}, - {0x32, 0xe0}, - {0x33, 0xe0}, - {0x34, 0xe0}, - {0x35, 0xb0}, - {0x36, 0xc0}, - {0x37, 0xc0}, - {0x38, 0x04}, - {0x39, 0x09}, - {0x3a, 0x12}, - {0x3b, 0x1C}, - {0x3c, 0x28}, - {0x3d, 0x31}, - {0x3e, 0x44}, - {0x3f, 0x57}, - {0x40, 0x6C}, - {0x41, 0x81}, - {0x42, 0x94}, - {0x43, 0xA7}, - {0x44, 0xB8}, - {0x45, 0xD6}, - {0x46, 0xEE}, - {0x47, 0x0d}, - {0xfe, 0x00}, //set page0 - //-----------Update the registers 2010/07/06-------------// - //Registers of Page0 - {0xfe, 0x00}, //set page0 - {0x10, 0x26}, - {0x11, 0x0d}, //fd,modified by mormo 2010/07/06 - {0x1a, 0x2a}, //1e,modified by mormo 2010/07/06 - {0x1c, 0x49}, //c1,modified by mormo 2010/07/06 - {0x1d, 0x9a}, //08,modified by mormo 2010/07/06 - {0x1e, 0x61}, //60,modified by mormo 2010/07/06 - {0x3a, 0x20}, - {0x50, 0x14}, //10,modified by mormo 2010/07/06 - {0x53, 0x80}, - {0x56, 0x80}, - {0x8b, 0x20}, //LSC - {0x8c, 0x20}, - {0x8d, 0x20}, - {0x8e, 0x14}, - {0x8f, 0x10}, - {0x90, 0x14}, - {0x94, 0x02}, - {0x95, 0x07}, - {0x96, 0xe0}, - {0xb1, 0x40}, //YCPT - {0xb2, 0x40}, - {0xb3, 0x40}, - {0xb6, 0xe0}, - //{0xd0 , 0xcb},//AECT c9,modifed by mormo 2010/07/06 - //{0xd3 , 0x48},//80,modified by mormor 2010/07/06 - {0xf2, 0x02}, - //{0xf7 , 0x12}, - //{0xf8 , 0x0a}, - //Registers - {0xfe, 0x01}, // set page1 - {0x02, 0x20}, - {0x04, 0x10}, - {0x05, 0x08}, - {0x06, 0x20}, - {0x08, 0x0a}, - {0x0e, 0x44}, - {0x0f, 0x32}, - {0x10, 0x41}, - {0x11, 0x37}, - {0x12, 0x22}, - {0x13, 0x19}, - {0x14, 0x44}, - {0x15, 0x44}, - {0x19, 0x50}, - {0x1a, 0xd8}, - {0x32, 0x10}, - {0x35, 0x00}, - {0x36, 0x80}, - {0x37, 0x00}, - //-----------Update the registers end---------// - {0xfe, 0x00}, //set page0 - {0xd2, 0x90}, -#endif -}; - -SPI_Psram_Cfg_Type apMemory1604 = { - .readIdCmd = 0x9F, - .readIdDmyClk = 0, - .burstToggleCmd = 0xC0, - .resetEnableCmd = 0x66, - .resetCmd = 0x99, - .enterQuadModeCmd = 0x35, - .exitQuadModeCmd = 0xF5, - .readRegCmd = 0xB5, - .readRegDmyClk = 1, - .writeRegCmd = 0xB1, - .readCmd = 0x03, - .readDmyClk = 0, - .fReadCmd = 0x0B, - .fReadDmyClk = 1, - .fReadQuadCmd = 0xEB, - .fReadQuadDmyClk = 3, - .writeCmd = 0x02, - .quadWriteCmd = 0x38, - .pageSize = 512, - .ctrlMode = PSRAM_SPI_CTRL_MODE, - .driveStrength = PSRAM_DRIVE_STRENGTH_50_OHMS, - .burstLength = PSRAM_BURST_LENGTH_512_BYTES, -}; - -SF_Ctrl_Cmds_Cfg cmdsCfg = { - .cmdsEn = ENABLE, - .burstToggleEn = ENABLE, - .wrapModeEn = DISABLE, - .wrapLen = SF_CTRL_WRAP_LEN_512, -}; - -SF_Ctrl_Psram_Cfg sfCtrlPsramCfg = { - .owner = SF_CTRL_OWNER_SAHB, - .padSel = SF_CTRL_PAD_SEL_DUAL_CS_SF2, - .bankSel = SF_CTRL_SEL_PSRAM, - .psramRxClkInvertSrc = ENABLE, - .psramRxClkInvertSel = ENABLE, - .psramDelaySrc = ENABLE, - .psramClkDelay = 0, -}; - -/*@} end of group IMAGE_SENSOR_Private_Variables */ - -/** @defgroup IMAGE_SENSOR_Global_Variables - * @{ - */ - -/*@} end of group IMAGE_SENSOR_Global_Variables */ - -/** @defgroup IMAGE_SENSOR_Private_Fun_Declaration - * @{ - */ -static void CAM_GPIO_Init(void); -static void I2C_GPIO_Init(void); -static BL_Err_Type CAM_Write_Byte8(uint8_t data, uint8_t cmd); -static uint8_t CAM_Read_Byte8(uint8_t cmd); -static BL_Err_Type CAM_Read_ID(void); -static BL_Err_Type CAM_Reg_Config(void); - -/*@} end of group IMAGE_SENSOR_Private_Fun_Declaration */ - -/** @defgroup IMAGE_SENSOR_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief CAMERA GPIO Initialization - * - * @param None - * - * @return None - * -*******************************************************************************/ -static void CAM_GPIO_Init(void) -{ - GLB_GPIO_Cfg_Type cfg; - - cfg.drive = 0; - cfg.smtCtrl = 1; - cfg.gpioPin = GLB_GPIO_PIN_0; - cfg.gpioFun = GPIO0_FUN_PIX_CLK; - cfg.gpioMode = GPIO_MODE_INPUT; - cfg.pullType = GPIO_PULL_NONE; - GLB_GPIO_Init(&cfg); - - cfg.drive = 0; - cfg.smtCtrl = 1; - cfg.gpioPin = GLB_GPIO_PIN_1; - cfg.gpioFun = GPIO1_FUN_FRAME_VLD; - cfg.gpioMode = GPIO_MODE_INPUT; - cfg.pullType = GPIO_PULL_NONE; - GLB_GPIO_Init(&cfg); - - cfg.drive = 0; - cfg.smtCtrl = 1; - cfg.gpioPin = GLB_GPIO_PIN_2; - cfg.gpioFun = GPIO2_FUN_LINE_VLD; - cfg.gpioMode = GPIO_MODE_INPUT; - cfg.pullType = GPIO_PULL_NONE; - GLB_GPIO_Init(&cfg); - - cfg.drive = 0; - cfg.smtCtrl = 1; - cfg.gpioPin = GLB_GPIO_PIN_3; - cfg.gpioFun = GPIO3_FUN_PIX_DAT0; - cfg.gpioMode = GPIO_MODE_INPUT; - cfg.pullType = GPIO_PULL_NONE; - GLB_GPIO_Init(&cfg); - - cfg.drive = 0; - cfg.smtCtrl = 1; - cfg.gpioPin = GLB_GPIO_PIN_4; - cfg.gpioFun = GPIO4_FUN_PIX_DAT1; - cfg.gpioMode = GPIO_MODE_INPUT; - cfg.pullType = GPIO_PULL_NONE; - GLB_GPIO_Init(&cfg); - - cfg.drive = 0; - cfg.smtCtrl = 1; - cfg.gpioPin = GLB_GPIO_PIN_5; - cfg.gpioFun = GPIO5_FUN_PIX_DAT2; - cfg.gpioMode = GPIO_MODE_INPUT; - cfg.pullType = GPIO_PULL_NONE; - GLB_GPIO_Init(&cfg); - - cfg.drive = 0; - cfg.smtCtrl = 1; - cfg.gpioPin = GLB_GPIO_PIN_6; - cfg.gpioFun = GPIO6_FUN_PIX_DAT3; - cfg.gpioMode = GPIO_MODE_INPUT; - cfg.pullType = GPIO_PULL_NONE; - GLB_GPIO_Init(&cfg); - - cfg.drive = 0; - cfg.smtCtrl = 1; - cfg.gpioPin = GLB_GPIO_PIN_12; - cfg.gpioFun = GPIO12_FUN_PIX_DAT4; - cfg.gpioMode = GPIO_MODE_INPUT; - cfg.pullType = GPIO_PULL_NONE; - GLB_GPIO_Init(&cfg); - - cfg.drive = 0; - cfg.smtCtrl = 1; - cfg.gpioPin = GLB_GPIO_PIN_29; - cfg.gpioFun = GPIO29_FUN_PIX_DAT5; - cfg.gpioMode = GPIO_MODE_INPUT; - cfg.pullType = GPIO_PULL_NONE; - GLB_GPIO_Init(&cfg); - - cfg.drive = 0; - cfg.smtCtrl = 1; - cfg.gpioPin = GLB_GPIO_PIN_30; - cfg.gpioFun = GPIO30_FUN_PIX_DAT6; - cfg.gpioMode = GPIO_MODE_INPUT; - cfg.pullType = GPIO_PULL_NONE; - GLB_GPIO_Init(&cfg); - - cfg.drive = 0; - cfg.smtCtrl = 1; - cfg.gpioPin = GLB_GPIO_PIN_31; - cfg.gpioFun = GPIO31_FUN_PIX_DAT7; - cfg.gpioMode = GPIO_MODE_INPUT; - cfg.pullType = GPIO_PULL_NONE; - GLB_GPIO_Init(&cfg); - - cfg.drive = 1; - cfg.smtCtrl = 1; - cfg.gpioPin = GLB_GPIO_PIN_10; - cfg.gpioFun = GPIO10_FUN_CAM_REF_CLK; - cfg.gpioMode = GPIO_MODE_OUTPUT; - cfg.pullType = GPIO_PULL_NONE; - //GLB_GPIO_Init(&cfg); -} - -/****************************************************************************/ /** - * @brief Dump image sensor register while is set - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Image_Sensor_Dump_Register(void) -{ - uint32_t i; - - for (i = 0; i < sizeof(sensorRegList) / sizeof(sensorRegList[0]); i++) - { - MSG("reg[%02x]: %02x\n", sensorRegList[i][0], CAM_Read_Byte8(sensorRegList[i][0])); - } -} - -/****************************************************************************/ /** - * @brief I2C GPIO Initialization - * - * @param None - * - * @return None - * -*******************************************************************************/ -static void I2C_GPIO_Init(void) -{ - uint8_t i; - GLB_GPIO_Cfg_Type cfg; - uint8_t gpiopins[2]; - uint8_t gpiofuns[2]; - uint8_t gpioMode[2]; - - cfg.gpioMode = GPIO_MODE_AF; - cfg.pullType = GPIO_PULL_UP; - cfg.drive = 1; - cfg.smtCtrl = 1; - cfg.gpioMode = GPIO_MODE_OUTPUT; - - gpiopins[0] = GLB_GPIO_PIN_16; - gpiopins[1] = GLB_GPIO_PIN_11; - gpiofuns[0] = GPIO16_FUN_I2C0_SCL; - gpiofuns[1] = GPIO11_FUN_I2C0_SDA; - gpioMode[0] = GPIO_MODE_AF; - gpioMode[1] = GPIO_MODE_AF; - - for (i = 0; i < sizeof(gpiopins) / sizeof(gpiopins[0]); i++) - { - cfg.gpioPin = gpiopins[i]; - cfg.gpioFun = gpiofuns[i]; - cfg.gpioMode = gpioMode[i]; - GLB_GPIO_Init(&cfg); - } -} - -/****************************************************************************/ /** - * @brief PSRAM GPIO Initialization - * - * @param None - * - * @return None - * -*******************************************************************************/ -static void ATTR_TCM_SECTION SF_Cfg_Init_Ext_Psram_Gpio(void) -{ - GLB_GPIO_Cfg_Type cfg; - uint8_t gpiopins[6]; - uint8_t i = 0; - - cfg.gpioMode = GPIO_MODE_AF; - cfg.pullType = GPIO_PULL_UP; - cfg.drive = 1; - cfg.smtCtrl = 1; - cfg.gpioFun = GPIO_FUN_FLASH_PSRAM; - - gpiopins[0] = BFLB_EXTPSRAM_CLK_GPIO; - gpiopins[1] = BFLB_EXTPSRAM_CS_GPIO; - gpiopins[2] = BFLB_EXTPSRAM_DATA0_GPIO; - gpiopins[3] = BFLB_EXTPSRAM_DATA1_GPIO; - gpiopins[4] = BFLB_EXTPSRAM_DATA2_GPIO; - gpiopins[5] = BFLB_EXTPSRAM_DATA3_GPIO; - - for (i = 0; i < sizeof(gpiopins); i++) - { - cfg.gpioPin = gpiopins[i]; - if (i == 0 || i == 1) - { - /*flash clk and cs is output*/ - cfg.gpioMode = GPIO_MODE_OUTPUT; - } - else - { - /*data are bidir*/ - cfg.gpioMode = GPIO_MODE_AF; - } - GLB_GPIO_Init(&cfg); - } -} - -/****************************************************************************/ /** - * @brief I2C CAMERA Write 8 bits - * - * @param data: Reg Value - * @param cmd: Reg Addr - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -static BL_Err_Type CAM_Write_Byte8(uint8_t data, uint8_t cmd) -{ - uint8_t temp = data; - I2C_Transfer_Cfg tranCfg; - - tranCfg.slaveAddr = I2C_CAMERA_ADDR; - tranCfg.stopEveryByte = DISABLE; - tranCfg.subAddrSize = 1; - tranCfg.subAddr = cmd; - tranCfg.dataSize = 1; - tranCfg.data = &temp; - return I2C_MasterSendBlocking(I2C0_ID, &tranCfg); -} - -/****************************************************************************/ /** - * @brief I2C CAMERA Read 8 bits - * - * @param cmd: Reg Addr - * - * @return Reg Value - * -*******************************************************************************/ -static uint8_t CAM_Read_Byte8(uint8_t cmd) -{ - uint8_t temp = 0; - I2C_Transfer_Cfg tranCfg; - - tranCfg.slaveAddr = I2C_CAMERA_ADDR; - tranCfg.stopEveryByte = DISABLE; - tranCfg.subAddrSize = 1; - tranCfg.subAddr = cmd; - tranCfg.dataSize = 1; - tranCfg.data = &temp; - I2C_MasterReceiveBlocking(I2C0_ID, &tranCfg); - - return temp; -} - -/****************************************************************************/ /** - * @brief CAMERA Read ID - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -static BL_Err_Type CAM_Read_ID(void) -{ - uint8_t buf[2] = {0}; -#if (IMAGE_SENSOR_USE == IMAGE_SENSOR_BF2013) - buf[0] = CAM_Read_Byte8(BF2013_ID_MSB); - bflb_platform_delay_ms(10); - buf[1] = CAM_Read_Byte8(BF2013_ID_LSB); - - if (buf[0] == 0x37 && buf[1] == 0x03) - { - return SUCCESS; - } - else - { - return ERROR; - } -#elif (IMAGE_SENSOR_USE == IMAGE_SENSOR_GC0308) - buf[0] = CAM_Read_Byte8(GC0308_ID); - - if (buf[0] == 0x9b) - { - return SUCCESS; - } - else - { - return ERROR; - } -#endif -} - -/****************************************************************************/ /** - * @brief CAMERA Reg Config - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -static BL_Err_Type CAM_Reg_Config(void) -{ - int i; - - for (i = 0; i < sizeof(sensorRegList) / sizeof(sensorRegList[0]); i++) - { - if (CAM_Write_Byte8(sensorRegList[i][1], sensorRegList[i][0]) != SUCCESS) - { - return ERROR; - } - //if(i == 0){ - bflb_platform_delay_ms(1); - //} - } - return SUCCESS; -} - -/*@} end of group IMAGE_SENSOR_Private_Functions */ - -/** @defgroup IMAGE_SENSOR_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief PSRAM Config Initialization - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Image_Sensor_PSRAM_Init(void) -{ - uint8_t psramId[8] = {0}; - - GLB_Set_SF_CLK(1, GLB_SFLASH_CLK_72M, 1); - SF_Cfg_Init_Ext_Psram_Gpio(); - - Psram_Init(&apMemory1604, &cmdsCfg, &sfCtrlPsramCfg); - Psram_ReadId(&apMemory1604, psramId); - MSG("PSRAM ID: %02X %02X %02X %02X %02X %02X %02X %02X.\r\n", - psramId[0], psramId[1], psramId[2], psramId[3], psramId[4], psramId[5], psramId[6], psramId[7]); - - Psram_Cache_Write_Set(&apMemory1604, SF_CTRL_QIO_MODE, DISABLE, ENABLE, ENABLE); - L1C_Cache_Enable_Set(0x0f); -} - -/****************************************************************************/ /** - * @brief Image sensor initialization - * - * @param mjpegEn: Enable or disable mjpeg - * @param camCfg: CAM configuration structure pointer - * @param mjpegCfg: MJPEG configuration structure pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Image_Sensor_Init(BL_Fun_Type mjpegEn, CAM_CFG_Type *camCfg, MJPEG_CFG_Type *mjpegCfg) -{ - /* Gpio init */ - CAM_GPIO_Init(); - I2C_GPIO_Init(); - - /* Set clock */ - GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_I2C); - GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_CAM); - GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_MJPEG); - GLB_Set_I2C_CLK(1, 9); - GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_DLL96M, 3); - GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_CAM); - - if (CAM_Read_ID() != SUCCESS) - { - return ERROR; - } - if (CAM_Reg_Config() != SUCCESS) - { - return ERROR; - } - CAM_Disable(); - MJPEG_Disable(); - - if (mjpegEn) - { - CAM_Init(camCfg); - MJPEG_Init(mjpegCfg); - MJPEG_Enable(); - } - else - { - CAM_Init(camCfg); - } - - CAM_Enable(); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Get one camera frame in interleave mode - * - * @param pic: Pointer of picture start address - * @param len: Length of picture - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Image_Sensor_CAM_Get_Interleave(uint8_t **pic, uint32_t *len) -{ - CAM_Interleave_Frame_Info info; - BL702_MemSet(&info, 0, sizeof(info)); - - CAM_Interleave_Get_Frame_Info(&info); - - if (info.validFrames == 0) - { - return ERROR; - } - - *pic = (uint8_t *)(info.curFrameAddr); - *len = info.curFrameBytes; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Get one camera frame in planar mode - * - * @param yuv: YUV mode - * @param picYY: Pointer of picture YY data start address(YUYV) - * @param lenYY: Length of picture YY data - * @param picUV: Pointer of picture UV data start address(YUYV) - * @param lenUV: Length of picture UV data - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Image_Sensor_CAM_Get_Planar(CAM_YUV_Mode_Type yuv, uint8_t **picYY, uint32_t *lenYY, uint8_t **picUV, uint32_t *lenUV) -{ - CAM_Planar_Frame_Info info; - BL702_MemSet(&info, 0, sizeof(info)); - - CAM_Planar_Get_Frame_Info(&info); - - if (yuv == CAM_YUV400_EVEN || yuv == CAM_YUV400_ODD) - { - if (info.validFrames0 == 0 && info.validFrames1 == 0) - { - return ERROR; - } - } - else - { - if (info.validFrames0 == 0 || info.validFrames1 == 0) - { - return ERROR; - } - } - - *picYY = (uint8_t *)(info.curFrameAddr0); - *lenYY = info.curFrameBytes0; - *picUV = (uint8_t *)(info.curFrameAddr1); - *lenUV = info.curFrameBytes1; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Get available count0 of camera frames - * - * @param None - * - * @return Frames count - * -*******************************************************************************/ -uint8_t Image_Sensor_CAM_Frame_Count0(void) -{ - return CAM_Get_Frame_Count_0(); -} - -/****************************************************************************/ /** - * @brief Get available count1 of camera frames - * - * @param None - * - * @return Frames count - * -*******************************************************************************/ -uint8_t Image_Sensor_CAM_Frame_Count1(void) -{ - return CAM_Get_Frame_Count_1(); -} - -/****************************************************************************/ /** - * @brief Pop one camera frame in interleave mode - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Image_Sensor_CAM_Release_Interleave(void) -{ - CAM_Interleave_Pop_Frame(); -} - -/****************************************************************************/ /** - * @brief Pop one camera frame in planar mode - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Image_Sensor_CAM_Release_Planar(void) -{ - CAM_Planar_Pop_Frame(); -} - -/****************************************************************************/ /** - * @brief Open camera function - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Image_Sensor_CAM_Open(void) -{ - CAM_Enable(); -} - -/****************************************************************************/ /** - * @brief Close camera function - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Image_Sensor_CAM_Close(void) -{ - CAM_Disable(); -} - -/****************************************************************************/ /** - * @brief Deinit camera module - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Image_Sensor_CAM_Deinit(void) -{ - CAM_Deinit(); -} - -/****************************************************************************/ /** - * @brief Get one mjpeg frame - * - * @param pic: Pointer of picture start address - * @param len: Length of picture - * @param q: Quantization - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Image_Sensor_MJPEG_Get(uint8_t **pic, uint32_t *len, uint8_t *q) -{ - MJPEG_Frame_Info info; - BL702_MemSet(&info, 0, sizeof(info)); - - MJPEG_Get_Frame_Info(&info); - - if (info.validFrames == 0) - { - return ERROR; - } - - *pic = (uint8_t *)(info.curFrameAddr); - *len = info.curFrameBytes; - *q = info.curFrameQ; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Get available count of mjpeg frames - * - * @param None - * - * @return Frames count - * -*******************************************************************************/ -uint8_t Image_Sensor_MJPEG_Frame_Count(void) -{ - return MJPEG_Get_Frame_Count(); -} - -/****************************************************************************/ /** - * @brief Pop one mjpeg frame - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Image_Sensor_MJPEG_Release(void) -{ - MJPEG_Pop_Frame(); -} - -/****************************************************************************/ /** - * @brief Open mjpeg function - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Image_Sensor_MJPEG_Open(void) -{ - MJPEG_Enable(); -} - -/****************************************************************************/ /** - * @brief Close mjpeg function - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Image_Sensor_MJPEG_Close(void) -{ - MJPEG_Disable(); -} - -/****************************************************************************/ /** - * @brief Deinit mjpeg module - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Image_Sensor_MJPEG_Deinit(void) -{ - MJPEG_Deinit(); -} - - - -// #include "hal_camera.h" -// #include "bl702_cam.h" -// #include "bl702_mjpeg.h" -// #include "bl702_i2c_gpio_sim.h" -// #include "bl702_glb.h" -// #include "bl702_config.h" - -// static void camera_gpio_init(camera_device_t *dev); -// /** -// * @brief -// * -// * @param dev -// * @param oflag -// * @return int -// */ -// int camera_open(struct device *dev, uint16_t oflag) -// { -// camera_device_t *camera_device = (camera_device_t *)dev; -// CAM_CFG_Type camCfg; -// uint32_t size; - -// GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_CAM); -// GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_MJPEG); -// camera_gpio_init(camera_device); -// GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_DLL96M, 3); -// GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_CAM); -// CAM_Disable(); -// MJPEG_Disable(); -// camCfg.swIntCnt = 1; -// camCfg.frameMode = camera_device->pic_format.frame_mode; -// camCfg.yuvMode = camera_device->pic_format.yuv_mode; -// camCfg.linePol = camera_device->line_pol; -// camCfg.framePol = camera_device->frame_pol; -// camCfg.camSensorMode = CAM_SENSOR_MODE_V_OR_H; -// camCfg.burstType = CAM_BURST_TYPE_INCR8; -// camCfg.waitCount = 0x40; -// size = camera_device->pic_reso_x * camera_device->pic_reso_y; -// if (camera_device->pic_format.mjpeg_enable == ENABLE) -// { -// MJPEG_CFG_Type mjpegCfg; -// camCfg.swMode = CAM_SW_MODE_AUTO; -// camCfg.memStart0 = (uint32_t)camera_device->buffer; -// camCfg.memSize0 = camera_device->pic_reso_x * 2 * 8 * 3; -// camCfg.frameSize0 = size * 2; -// camCfg.memStart1 = 0; -// camCfg.memSize1 = 0; -// camCfg.frameSize1 = 0; -// mjpegCfg.burst = MJPEG_BURST_INCR16; -// mjpegCfg.quality = camera_device->pic_format.mjpegQ; -// mjpegCfg.yuv = MJPEG_YUV422_INTERLEAVE; -// mjpegCfg.waitCount = 0x400; -// mjpegCfg.bufferMjpeg = camCfg.memStart0 + camCfg.memSize0; -// mjpegCfg.sizeMjpeg = camera_device->length - camCfg.memSize0; -// mjpegCfg.bufferCamYY = (uint32_t)camera_device->buffer; -// mjpegCfg.sizeCamYY = 3; -// mjpegCfg.bufferCamUV = 0; -// mjpegCfg.sizeCamUV = 0; -// mjpegCfg.resolutionX = camera_device->pic_reso_x; -// mjpegCfg.resolutionY = camera_device->pic_reso_y; -// mjpegCfg.bitOrderEnable = ENABLE, -// mjpegCfg.evenOrderEnable = ENABLE, -// mjpegCfg.swapModeEnable = DISABLE, -// mjpegCfg.overStopEnable = ENABLE, -// mjpegCfg.reflectDmy = DISABLE, -// mjpegCfg.verticalDmy = DISABLE, -// mjpegCfg.horizationalDmy = DISABLE, -// camera_device->picture.base1 = (uint8_t*)mjpegCfg.bufferMjpeg; -// camera_device->picture.base2 = (uint8_t *)0; -// CAM_Init(&camCfg); -// MJPEG_Init(&mjpegCfg); -// MJPEG_Enable(); -// } -// else -// { -// camCfg.swMode = CAM_SW_MODE_MANUAL; -// if (camera_device->pic_format.frame_mode == CAMERA_INTERLEAVE_MODE) -// { -// camCfg.memStart0 = (uint32_t)camera_device->buffer; -// camCfg.memSize0 = camera_device->length; -// camCfg.memStart1 = 0; -// camCfg.memSize1 = 0; -// camCfg.frameSize1 = 0; -// switch (camera_device->pic_format.yuv_mode) -// { -// case CAMERA_YUV422: -// camCfg.frameSize0 = size * 2; -// break; -// case CAMERA_YUV420_EVEN: -// camCfg.frameSize0 = size * 2 * 3 / 4; -// break; -// case CAMERA_YUV420_ODD: -// camCfg.frameSize0 = size * 2 * 3 / 4; -// break; -// case CAMERA_YUV400_EVEN: -// camCfg.frameSize0 = size; -// break; -// case CAMERA_YUV400_ODD: -// camCfg.frameSize0 = size; -// break; -// default: -// break; -// } -// camera_device->picture.base1 = (uint8_t *)camCfg.memStart0; -// camera_device->picture.base2 = (uint8_t *)0; -// } -// else -// { -// camCfg.memStart0 = (uint32_t)camera_device->buffer; -// camCfg.memSize0 = camera_device->length / 2; -// camCfg.memStart1 = (uint32_t)camera_device->buffer + camera_device->length / 2; -// camCfg.memSize1 = camera_device->length / 2; -// camCfg.frameSize1 = size; -// switch (camera_device->pic_format.yuv_mode) -// { -// case CAMERA_YUV422: -// camCfg.frameSize0 = size; -// break; -// case CAMERA_YUV420_EVEN: -// camCfg.frameSize0 = size / 2; -// break; -// case CAMERA_YUV420_ODD: -// camCfg.frameSize0 = size / 2; -// break; -// case CAMERA_YUV400_EVEN: -// camCfg.frameSize0 = 0; -// break; -// case CAMERA_YUV400_ODD: -// camCfg.frameSize0 = 0; -// break; -// default: -// break; -// } -// camera_device->picture.base1 = (uint8_t *)camCfg.memStart0; -// camera_device->picture.base2 = (uint8_t *)camCfg.memStart1; -// } -// CAM_Init(&camCfg); -// } -// CAM_Enable(); - -// return 0; -// } - -// int camera_close(struct device *dev) -// { -// CAM_Disable(); - -// return 0; -// } - -// int camera_control(struct device *dev, int cmd, void *args) -// { -// //i2c_device_t *i2c_device = (i2c_device_t *)dev; - -// switch (cmd) -// { -// case DEVICE_CTRL_SET_INT /* constant-expression */: - -// break; -// case DEVICE_CTRL_CLR_INT /* constant-expression */: -// /* code */ -// /* Enable UART interrupt*/ - -// break; -// case DEVICE_CTRL_GET_INT /* constant-expression */: -// /* code */ -// break; -// case DEVICE_CTRL_CONFIG /* constant-expression */: -// if (args == (void *)DEVICE_CTRL_CONFIG_CAM_START) -// { - -// } -// else if (args == (void *)DEVICE_CTRL_CONFIG_CAM_STOP) -// { - -// } -// break; -// case 4 /* constant-expression */: -// /* code */ -// break; -// case 5 /* constant-expression */: -// /* code */ -// break; -// default: -// break; -// } - -// return 0; -// } - -// int camera_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) -// { -// camera_device_t *camera_device = (camera_device_t *)dev; -// camera_picture_t *pic = buffer; - -// if(camera_device->pic_format.mjpeg_enable == ENABLE) -// { -// MJPEG_Frame_Info info = -// { -// .validFrames = 0, -// .curFrameAddr = 0, -// .curFrameBytes = 0, -// .curFrameQ = 0, -// .status = 0, -// }; -// MJPEG_Get_Frame_Info(&info); -// if (info.validFrames == 0) -// { -// return ERROR; -// } -// pic->addr1 = (uint8_t *)(info.curFrameAddr); -// pic->length1 = info.curFrameBytes; -// return SUCCESS; -// } -// else -// { -// if (camera_device->pic_format.frame_mode == CAMERA_INTERLEAVE_MODE) -// { -// CAM_Interleave_Frame_Info info = -// { -// .validFrames = 0, -// .curFrameAddr = 0, -// .curFrameBytes = 0, -// .status = 0, -// }; -// CAM_Interleave_Get_Frame_Info(&info); -// if (info.validFrames == 0) -// { -// return ERROR; -// } -// pic->addr1 = (uint8_t *)(info.curFrameAddr); -// pic->length1 = info.curFrameBytes; -// } -// else -// { -// CAM_Planar_Frame_Info info = -// { -// .validFrames0 = 0, -// .validFrames1 = 0, -// .curFrameAddr0 = 0, -// .curFrameAddr1 = 0, -// .curFrameBytes0 = 0, -// .curFrameBytes1 = 0, -// .status = 0, -// }; -// CAM_Planar_Get_Frame_Info(&info); -// if (camera_device->pic_format.yuv_mode == CAMERA_YUV400_EVEN || camera_device->pic_format.yuv_mode == CAMERA_YUV400_ODD) -// { -// if (info.validFrames0 == 0 && info.validFrames1 == 0) -// { -// return ERROR; -// } -// } -// else -// { -// if (info.validFrames0 == 0 || info.validFrames1 == 0) -// { -// return ERROR; -// } -// } -// pic->addr1 = (uint8_t *)(info.curFrameAddr0); -// pic->length1 = info.curFrameBytes0; -// pic->addr2 = (uint8_t *)(info.curFrameAddr1); -// pic->length2 = info.curFrameBytes1; -// return SUCCESS; -// } -// } -// return ERROR; -// } - -// #ifdef USING_DEVICE_OPS -// struct device_drv_ops cam_driver = -// { -// cam_open, -// cam_close, -// cam_control, -// cam_write, -// cam_read -// }; -// #endif - -// void camera_register(camera_device_t *device, const char *name, uint16_t flag) -// { -// struct device *dev; - -// dev = &(device->parent); -// #ifdef USING_DEVICE_OPS -// dev->api = &cam_driver; -// #else -// dev->open = camera_open; -// dev->close = camera_close; -// dev->control = camera_control; -// dev->write = NULL; -// dev->read = camera_read; -// #endif - -// dev->status = DEVICE_UNREGISTER; -// dev->type = DEVICE_CLASS_CAMERA; -// dev->handle = NULL; - -// device_register(dev, name, flag); -// } - -// static void camera_gpio_init(camera_device_t *dev) -// { -// GLB_GPIO_Cfg_Type cfg; - -// cfg.drive = 0; -// cfg.smtCtrl = 1; -// cfg.gpioPin = dev->pin.pclk; -// cfg.gpioFun = GPIO0_FUN_PIX_CLK; -// cfg.gpioMode = GPIO_MODE_INPUT; -// cfg.pullType = GPIO_PULL_NONE; -// GLB_GPIO_Init(&cfg); - -// cfg.drive = 0; -// cfg.smtCtrl = 1; -// cfg.gpioPin = dev->pin.vsync; -// cfg.gpioFun = GPIO1_FUN_FRAME_VLD; -// cfg.gpioMode = GPIO_MODE_INPUT; -// cfg.pullType = GPIO_PULL_NONE; -// GLB_GPIO_Init(&cfg); - -// cfg.drive = 0; -// cfg.smtCtrl = 1; -// cfg.gpioPin = dev->pin.hsync; -// cfg.gpioFun = GPIO2_FUN_LINE_VLD; -// cfg.gpioMode = GPIO_MODE_INPUT; -// cfg.pullType = GPIO_PULL_NONE; -// GLB_GPIO_Init(&cfg); - -// cfg.drive = 0; -// cfg.smtCtrl = 1; -// cfg.gpioPin = dev->pin.data0; -// cfg.gpioFun = GPIO3_FUN_PIX_DAT0; -// cfg.gpioMode = GPIO_MODE_INPUT; -// cfg.pullType = GPIO_PULL_NONE; -// GLB_GPIO_Init(&cfg); - -// cfg.drive = 0; -// cfg.smtCtrl = 1; -// cfg.gpioPin = dev->pin.data1; -// cfg.gpioFun = GPIO4_FUN_PIX_DAT1; -// cfg.gpioMode = GPIO_MODE_INPUT; -// cfg.pullType = GPIO_PULL_NONE; -// GLB_GPIO_Init(&cfg); - -// cfg.drive = 0; -// cfg.smtCtrl = 1; -// cfg.gpioPin = dev->pin.data2; -// cfg.gpioFun = GPIO5_FUN_PIX_DAT2; -// cfg.gpioMode = GPIO_MODE_INPUT; -// cfg.pullType = GPIO_PULL_NONE; -// GLB_GPIO_Init(&cfg); - -// cfg.drive = 0; -// cfg.smtCtrl = 1; -// cfg.gpioPin = dev->pin.data3; -// cfg.gpioFun = GPIO6_FUN_PIX_DAT3; -// cfg.gpioMode = GPIO_MODE_INPUT; -// cfg.pullType = GPIO_PULL_NONE; -// GLB_GPIO_Init(&cfg); - -// cfg.drive = 0; -// cfg.smtCtrl = 1; -// cfg.gpioPin = dev->pin.data4; -// cfg.gpioFun = GPIO12_FUN_PIX_DAT4; -// cfg.gpioMode = GPIO_MODE_INPUT; -// cfg.pullType = GPIO_PULL_NONE; -// GLB_GPIO_Init(&cfg); - -// cfg.drive = 0; -// cfg.smtCtrl = 1; -// cfg.gpioPin = dev->pin.data5; -// cfg.gpioFun = GPIO29_FUN_PIX_DAT5; -// cfg.gpioMode = GPIO_MODE_INPUT; -// cfg.pullType = GPIO_PULL_NONE; -// GLB_GPIO_Init(&cfg); - -// cfg.drive = 0; -// cfg.smtCtrl = 1; -// cfg.gpioPin = dev->pin.data6; -// cfg.gpioFun = GPIO30_FUN_PIX_DAT6; -// cfg.gpioMode = GPIO_MODE_INPUT; -// cfg.pullType = GPIO_PULL_NONE; -// GLB_GPIO_Init(&cfg); - -// cfg.drive = 0; -// cfg.smtCtrl = 1; -// cfg.gpioPin = dev->pin.data7; -// cfg.gpioFun = GPIO31_FUN_PIX_DAT7; -// cfg.gpioMode = GPIO_MODE_INPUT; -// cfg.pullType = GPIO_PULL_NONE; -// GLB_GPIO_Init(&cfg); - -// if(ENABLE == dev->pin.mclk_enable) -// { -// cfg.drive = 1; -// cfg.smtCtrl = 1; -// cfg.gpioPin = dev->pin.mclk; -// cfg.gpioFun = GPIO10_FUN_CAM_REF_CLK; -// cfg.gpioMode = GPIO_MODE_OUTPUT; -// cfg.pullType = GPIO_PULL_NONE; -// GLB_GPIO_Init(&cfg); -// } - -// } \ No newline at end of file diff --git a/drivers/bl702_driver/hal_drv/src/hal_clock.c b/drivers/bl702_driver/hal_drv/src/hal_clock.c index 1bad61f7..66feb0a0 100644 --- a/drivers/bl702_driver/hal_drv/src/hal_clock.c +++ b/drivers/bl702_driver/hal_drv/src/hal_clock.c @@ -23,6 +23,12 @@ #include "bl702_glb.h" #include "hal_clock.h" +#include "hal_mtimer.h" + +static uint32_t mtimer_get_clk_src_div(void) +{ + return ((SystemCoreClockGet()/(GLB_Get_BCLK_Div() + 1))/1000/1000-1); +} void system_clock_init(void) { @@ -31,32 +37,45 @@ void system_clock_init(void) /*set fclk/hclk and bclk clock*/ GLB_Set_System_CLK_Div(BSP_HCLK_DIV,BSP_BCLK_DIV); /* Set MTimer the same frequency as SystemCoreClock */ - GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, 7); + GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div()); +#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE + PDS_Set_Audio_PLL_Freq(BSP_AUDIO_PLL_CLOCK_SOURCE & 0x0f); +#endif } void peripheral_clock_init(void) { #if defined(BSP_USING_UART0)||defined(BSP_USING_UART1) -#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_DLL_96M +#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_96M GLB_Set_UART_CLK(ENABLE,HBN_UART_CLK_96M,BSP_UART_CLOCK_DIV); -#elif BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_DLL_FCLK +#elif BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK GLB_Set_UART_CLK(ENABLE,HBN_UART_CLK_FCLK,BSP_UART_CLOCK_DIV); +#else + #error "please select correct uart clock source" #endif #endif #if defined(BSP_USING_I2C0) +#if BSP_I2C_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK GLB_Set_I2C_CLK(ENABLE,BSP_I2C_CLOCK_DIV); +#else + #error "please select correct i2c clock source" +#endif #endif #if defined(BSP_USING_SPI0) +#if BSP_SPI_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK GLB_Set_SPI_CLK(ENABLE,BSP_SPI_CLOCK_DIV); +#else + #error "please select correct spi clock source" +#endif #endif #if defined(BSP_USING_PWM) #if BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_RC_32K -#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_DLL_BCLK +#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK -#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_DLL_XCLK +#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK #endif #endif @@ -71,18 +90,35 @@ void peripheral_clock_init(void) #endif #if defined(BSP_USING_ADC0) #if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL +#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE GLB_Set_ADC_CLK(ENABLE,GLB_ADC_CLK_AUDIO_PLL,BSP_ADC_CLOCK_DIV); -#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_DLL_XCLK +#endif +#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK GLB_Set_ADC_CLK(ENABLE,GLB_ADC_CLK_XCLK,BSP_ADC_CLOCK_DIV); +#else + #error "please select correct adc clock source" #endif #endif #if defined(BSP_USING_DAC0) #if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL +#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE GLB_Set_DAC_CLK(ENABLE,GLB_ADC_CLK_AUDIO_PLL,BSP_DAC_CLOCK_DIV); -#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_DLL_XCLK +#endif +#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK GLB_Set_DAC_CLK(ENABLE,GLB_ADC_CLK_XCLK,BSP_DAC_CLOCK_DIV); +#else + #error "please select correct dac clock source" +#endif +#endif + +#if defined(BSP_USING_CAM) +#if BSP_CAM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_96M + GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_DLL96M, BSP_CAM_CLOCK_DIV); + GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_CAM); +#else + #error "please select correct cam clock source" #endif #endif @@ -102,7 +138,20 @@ uint32_t system_clock_get(enum system_clock_type type) case SYSTEM_CLOCK_BCLK: return (SystemCoreClockGet()/((GLB_Get_HCLK_Div()+1)*(GLB_Get_BCLK_Div()+1))); case SYSTEM_CLOCK_XCLK: - return 32000000; + return 32000000; + case SYSTEM_CLOCK_AUPLL: +#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE + if(BSP_AUDIO_PLL_CLOCK_SOURCE == AUDIO_PLL_CLOCK_12288000_HZ) + return 12288000; + else if(BSP_AUDIO_PLL_CLOCK_SOURCE == AUDIO_PLL_CLOCK_11289600_HZ) + return 11289600; + else if(BSP_AUDIO_PLL_CLOCK_SOURCE == AUDIO_PLL_CLOCK_5644800_HZ) + return 5644800; + else if(BSP_AUDIO_PLL_CLOCK_SOURCE == AUDIO_PLL_CLOCK_24576000_HZ) + return 24576000; + else if(BSP_AUDIO_PLL_CLOCK_SOURCE == AUDIO_PLL_CLOCK_24000000_HZ) + return 24000000; +#endif default: break; } @@ -116,15 +165,15 @@ uint32_t peripheral_clock_get(enum peripheral_clock_type type) { case PERIPHERAL_CLOCK_UART: #if defined(BSP_USING_UART0)||defined(BSP_USING_UART1) - #if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_DLL_96M + #if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_96M return 96000000; - #elif BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_DLL_FCLK + #elif BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK return system_clock_get(SYSTEM_CLOCK_FCLK)/(GLB_Get_HCLK_Div()+1)); #endif #endif case PERIPHERAL_CLOCK_SPI: #if defined(BSP_USING_SPI0) -#if BSP_SPI_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_DLL_BCLK +#if BSP_SPI_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK tmpVal=BL_RD_REG(GLB_BASE,GLB_CLK_CFG3); div = BL_GET_REG_BITS_VAL(tmpVal,GLB_SPI_CLK_DIV); return system_clock_get(SYSTEM_CLOCK_BCLK)/(div+1); @@ -132,7 +181,7 @@ uint32_t peripheral_clock_get(enum peripheral_clock_type type) #endif case PERIPHERAL_CLOCK_I2C: #if defined(BSP_USING_I2C0) -#if BSP_I2C_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_DLL_BCLK +#if BSP_I2C_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK tmpVal=BL_RD_REG(GLB_BASE,GLB_CLK_CFG3); div = BL_GET_REG_BITS_VAL(tmpVal,GLB_I2C_CLK_DIV); return system_clock_get(SYSTEM_CLOCK_BCLK)/(div+1); @@ -141,9 +190,47 @@ uint32_t peripheral_clock_get(enum peripheral_clock_type type) case PERIPHERAL_CLOCK_I2S: return 0; case PERIPHERAL_CLOCK_ADC: - return 32000000; +#if defined(BSP_USING_ADC0) +#if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK + tmpVal=BL_RD_REG(GLB_BASE,GLB_GPADC_32M_SRC_CTRL); + div=BL_GET_REG_BITS_VAL(tmpVal,GLB_GPADC_32M_CLK_DIV); + return 32000000/div; +#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL + tmpVal=BL_RD_REG(GLB_BASE,GLB_GPADC_32M_SRC_CTRL); + div=BL_GET_REG_BITS_VAL(tmpVal,GLB_GPADC_32M_CLK_DIV); + return system_clock_get(SYSTEM_CLOCK_AUPLL)/div; +#endif +#endif + case PERIPHERAL_CLOCK_DAC: +#if defined(BSP_USING_DAC0) +#if BSP_DAC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK + tmpVal=BL_RD_REG(GLB_BASE,GLB_DIG32K_WAKEUP_CTRL); + div=BL_GET_REG_BITS_VAL(tmpVal,GLB_DIG_512K_DIV); + return 32000000/(div+1); +#elif BSP_DAC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL + tmpVal=BL_RD_REG(GLB_BASE,GLB_DIG32K_WAKEUP_CTRL); + div=BL_GET_REG_BITS_VAL(tmpVal,GLB_DIG_512K_DIV); + return system_clock_get(SYSTEM_CLOCK_AUPLL)/div; +#endif +#endif + case PERIPHERAL_CLOCK_PWM: + return system_clock_get(SYSTEM_CLOCK_BCLK); + break; + case PERIPHERAL_CLOCK_CAM: +#if defined(BSP_USING_CAM) +#if BSP_CAM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_96M + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + div = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV); + return (96000000 / (div + 1)); +#endif +#endif + break; default: + break; } + + (void)(tmpVal); + (void)(div); return 0; } \ No newline at end of file diff --git a/drivers/bl702_driver/hal_drv/src/hal_dac.c b/drivers/bl702_driver/hal_drv/src/hal_dac.c index 0f172e40..4a0a40ac 100644 --- a/drivers/bl702_driver/hal_drv/src/hal_dac.c +++ b/drivers/bl702_driver/hal_drv/src/hal_dac.c @@ -29,7 +29,7 @@ #include "bl702_glb.h" #include "dac_config.h" -dac_device_t dacx_device[] = { +static dac_device_t dacx_device[] = { #ifdef BSP_USING_DAC0 DAC_CONFIG, #endif @@ -37,8 +37,8 @@ dac_device_t dacx_device[] = { int dac_open(struct device *dev, uint16_t oflag) { - GLB_GPIP_DAC_ChanA_Cfg_Type chCfg; - GLB_GPIP_DAC_Cfg_Type dacCfg ; + GLB_GPIP_DAC_ChanA_Cfg_Type chCfg = {0}; + GLB_GPIP_DAC_Cfg_Type dacCfg = {0} ; dac_device_t *dac_device = (dac_device_t *)dev; uint8_t dac_ext_ref_pin =0; diff --git a/drivers/bl702_driver/hal_drv/src/hal_dma.c b/drivers/bl702_driver/hal_drv/src/hal_dma.c index 1d08358a..e5090e96 100644 --- a/drivers/bl702_driver/hal_drv/src/hal_dma.c +++ b/drivers/bl702_driver/hal_drv/src/hal_dma.c @@ -24,11 +24,11 @@ #include "drv_mmheap.h" #include "bl702_dma.h" -dma_control_data_t dma_ctrl_cfg; +static dma_control_data_t dma_ctrl_cfg; -void DMA0_IRQ(void); +static void DMA0_IRQ(void); -dma_device_t dmax_device[DMA_MAX_INDEX] = +static dma_device_t dmax_device[DMA_MAX_INDEX] = { #ifdef BSP_USING_DMA0_CH0 DMA0_CH0_CONFIG, @@ -66,7 +66,7 @@ int dma_open(struct device *dev, uint16_t oflag) { dma_device_t *dma_device = (dma_device_t *)dev; - DMA_LLI_Cfg_Type lliCfg; + DMA_LLI_Cfg_Type lliCfg = {0}; /* Disable all interrupt */ DMA_IntMask(dma_device->ch, DMA_INT_ALL, MASK); @@ -129,7 +129,7 @@ int dma_control(struct device *dev, int cmd, void *args) case DEVICE_CTRL_CONFIG /* constant-expression */: { dma_ctrl_param_t *cfg = (dma_ctrl_param_t *)args; - DMA_LLI_Cfg_Type lliCfg; + DMA_LLI_Cfg_Type lliCfg = {0}; lliCfg.dir = cfg->direction; lliCfg.srcPeriph = cfg->src_req; @@ -429,7 +429,7 @@ void dma_isr(dma_device_t *handle) if (handle->id == 0) { uint32_t DMAChs = DMA_BASE; - for (uint8_t i = 0; i < DMA_CH_MAX; i++) + for (uint8_t i = 0; i < DMA_MAX_INDEX; i++) { tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS); if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << handle[i].ch)) != 0) @@ -446,7 +446,7 @@ void dma_isr(dma_device_t *handle) } } - for (uint8_t i = 0; i < DMA_CH_MAX; i++) + for (uint8_t i = 0; i < DMA_MAX_INDEX; i++) { tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS); if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << handle[i].ch)) != 0) diff --git a/drivers/bl702_driver/hal_drv/src/hal_flash.c b/drivers/bl702_driver/hal_drv/src/hal_flash.c index 79e9d754..60f1fa8a 100644 --- a/drivers/bl702_driver/hal_drv/src/hal_flash.c +++ b/drivers/bl702_driver/hal_drv/src/hal_flash.c @@ -25,84 +25,123 @@ #include "bl702_glb.h" #include "hal_flash.h" + +static SPI_Flash_Cfg_Type g_boot2_flash_cfg; + /** - * @brief erase flash memory addr should be 4k aligned or will erase more than size Byte - * each block have 4K Byte + * @brief flash_init * - * @param addr flash memory block addr - * @param size erase bytes number - * @return int success or not + * @return int */ -int flash_erase(uint32_t addr, uint32_t size) +int flash_init(void) { - - SPI_Flash_Cfg_Type flashCfg; - uint32_t ret = 0; - - XIP_SFlash_Opt_Enter(); - ret = SF_Cfg_Flash_Identify(1, 1, 0, 0, &flashCfg); - XIP_SFlash_Opt_Exit(); - - if ((ret & BFLB_FLASH_ID_VALID_FLAG) == 0) - { - return -FLASH_NOT_DETECT; - } - - XIP_SFlash_Erase_With_Lock(&flashCfg, SF_CTRL_DO_MODE, addr, size - 1); + L1C_Cache_Flush(0xf); + SF_Cfg_Get_Flash_Cfg_Need_Lock(0,&g_boot2_flash_cfg); + g_boot2_flash_cfg.ioMode=g_boot2_flash_cfg.ioMode&0x0f; + L1C_Cache_Flush(0xf); return 0; } /** - * @brief read data form flash + * @brief read jedec id * - * @param addr read flash addr - * @param data read data pointer - * @param size read data size + * @param data * @return int */ -int flash_read(uint32_t addr, uint8_t *data, uint32_t size) +int flash_read_jedec_id(uint8_t *data) { - SPI_Flash_Cfg_Type flashCfg; - uint32_t ret = 0; - - XIP_SFlash_Opt_Enter(); - ret = SF_Cfg_Flash_Identify(1, 1, 0, 0, &flashCfg); - XIP_SFlash_Opt_Exit(); - - if ((ret & BFLB_FLASH_ID_VALID_FLAG) == 0) - { - return -FLASH_NOT_DETECT; - } - - XIP_SFlash_Read_With_Lock(&flashCfg, SF_CTRL_DO_MODE, addr, data, size); + uint32_t jid = 0; + XIP_SFlash_GetJedecId_Need_Lock(&g_boot2_flash_cfg,g_boot2_flash_cfg.ioMode & 0x0f,(uint8_t *)&jid); + jid &= 0xFFFFFF; + BL702_MemCpy(data, (void *)&jid, 4); return 0; } + /** - * @brief write data to flash + * @brief read xip data * - * @param addr write flash addr - * @param data write data pointer - * @param size write data size - * @return int + * @param addr + * @param data + * @param len + * @return BL_Err_Type */ -int flash_write(uint32_t addr, uint8_t *data, uint32_t size) +BL_Err_Type flash_read_xip(uint32_t addr,uint8_t *data, uint32_t len) { - SPI_Flash_Cfg_Type flashCfg; - uint32_t ret = 0; + BL702_MemCpy_Fast(data, + (uint8_t *)(BL702_FLASH_XIP_BASE+addr-SF_Ctrl_Get_Flash_Image_Offset()), + len); + return 0; +} - XIP_SFlash_Opt_Enter(); - ret = SF_Cfg_Flash_Identify(1, 1, 0, 0, &flashCfg); - XIP_SFlash_Opt_Exit(); - if ((ret & BFLB_FLASH_ID_VALID_FLAG) == 0) - { - return -FLASH_NOT_DETECT; +/** + * @brief write xip data + * + * @param addr + * @param data + * @param len + * @return BL_Err_Type + */ +BL_Err_Type flash_write_xip(uint32_t addr, uint8_t *data, uint32_t len) +{ + return XIP_SFlash_Write_With_Lock(&g_boot2_flash_cfg,g_boot2_flash_cfg.ioMode & 0x0f,addr,data,len); +} + +/** + * @brief erase xip data + * + * @param startaddr + * @param endaddr + * @return BL_Err_Type + */ +BL_Err_Type flash_erase_xip(uint32_t startaddr,uint32_t endaddr) +{ + return XIP_SFlash_Erase_With_Lock(&g_boot2_flash_cfg,g_boot2_flash_cfg.ioMode & 0x0f,startaddr,endaddr-startaddr+1); +} + + +/** + * @brief set flash cache + * + * @param cont_read + * @param cache_enable + * @param cache_way_disable + * @param flash_offset + * @return BL_Err_Type + */ +BL_Err_Type ATTR_TCM_SECTION flash_set_cache(uint8_t cont_read,uint8_t cache_enable,uint8_t cache_way_disable, uint32_t flash_offset) +{ + uint32_t tmp[1]; + BL_Err_Type stat; + + /* To make it simple, exit cont read anyway */ + SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); + + SFlash_Reset_Continue_Read(&g_boot2_flash_cfg); + if(g_boot2_flash_cfg.cReadSupport==0){ + cont_read=0; + } + + if(cont_read==1){ + stat=SFlash_Read(&g_boot2_flash_cfg, g_boot2_flash_cfg.ioMode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp)); + if(SUCCESS!=stat){ + return 0xff; + } + } + + /* Set default value */ + L1C_Cache_Enable_Set(0xf); + + + if(cache_enable){ + SF_Ctrl_Set_Flash_Image_Offset(flash_offset); + SFlash_Cache_Read_Enable(&g_boot2_flash_cfg, g_boot2_flash_cfg.ioMode & 0xf, cont_read, cache_way_disable); } - XIP_SFlash_Write_With_Lock(&flashCfg, SF_CTRL_DO_MODE, addr, data, size); return 0; -} \ No newline at end of file +} + diff --git a/drivers/bl702_driver/hal_drv/src/hal_gpio.c b/drivers/bl702_driver/hal_drv/src/hal_gpio.c index d6f7c52d..44863cd2 100644 --- a/drivers/bl702_driver/hal_drv/src/hal_gpio.c +++ b/drivers/bl702_driver/hal_drv/src/hal_gpio.c @@ -23,8 +23,21 @@ #include "bl702_glb.h" #include "bl702_gpio.h" #include "hal_gpio.h" +#include "drv_mmheap.h" + +static gpio_device_t gpio_device; + +static void GPIO_IRQ(void); + +struct gpio_int_cfg_private +{ + slist_t list; + uint32_t pin; + void (*cbfun)(uint32_t pin); +}; + +static slist_t gpio_int_head = SLIST_OBJECT_INIT(gpio_int_head); -gpio_device_t gpio_device; /** * @brief * @@ -71,7 +84,7 @@ void gpio_set_mode(uint32_t pin, uint32_t mode) gpio_cfg.gpioMode = GPIO_MODE_INPUT; - GLB_GPIO_INT0_IRQHandler_Install(); + Interrupt_Handler_Register(GPIO_INT0_IRQn,GPIO_IRQ); if (mode == GPIO_ASYNC_RISING_TRIGER_INT_MODE) { gpio_cfg.pullType = GPIO_PULL_DOWN; @@ -163,9 +176,12 @@ int gpio_read(uint32_t pin) * @param pin * @param cbFun */ -void gpio_attach_irq(uint32_t pin, void (*cbFun)(void)) +void gpio_attach_irq(uint32_t pin, void (*cbfun)(uint32_t pin)) { - GLB_GPIO_INT0_Callback_Install(pin, cbFun); + struct gpio_int_cfg_private* int_cfg = mmheap_alloc(sizeof(struct gpio_int_cfg_private)); + int_cfg->cbfun = cbfun; + int_cfg->pin = pin; + slist_add_tail(&gpio_int_head,&int_cfg->list); } /** * @brief @@ -186,6 +202,7 @@ void gpio_irq_enable(uint32_t pin, uint8_t enabled) } + void pin_register(const char *name, uint16_t flag) { struct device *dev; @@ -202,4 +219,30 @@ void pin_register(const char *name, uint16_t flag) dev->handle = NULL; device_register(dev, name, flag); +} + +static void GPIO_IRQ(void) +{ + slist_t *i; + uint32_t timeOut=0; +#define GLB_GPIO_INT0_CLEAR_TIMEOUT (32) + slist_for_each(i,&gpio_int_head) + { + struct gpio_int_cfg_private* int_cfg = slist_entry(i,struct gpio_int_cfg_private,list); + if(SET==GLB_Get_GPIO_IntStatus(int_cfg->pin)) + { + int_cfg->cbfun(int_cfg->pin); + GLB_GPIO_IntClear(int_cfg->pin,SET); + /* timeout check */ + timeOut=GLB_GPIO_INT0_CLEAR_TIMEOUT; + do{ + timeOut--; + }while((SET==GLB_Get_GPIO_IntStatus(int_cfg->pin))&&timeOut); + if(!timeOut){ + MSG("WARNING: Clear GPIO interrupt status fail.\r\n"); + } + GLB_GPIO_IntClear(int_cfg->pin,RESET); + } + } + } \ No newline at end of file diff --git a/drivers/bl702_driver/hal_drv/src/hal_i2c.c b/drivers/bl702_driver/hal_drv/src/hal_i2c.c index aef78fdc..728a6901 100644 --- a/drivers/bl702_driver/hal_drv/src/hal_i2c.c +++ b/drivers/bl702_driver/hal_drv/src/hal_i2c.c @@ -26,7 +26,7 @@ #include "bl702_i2c_gpio_sim.h" #include "bl702_glb.h" -i2c_device_t i2cx_device[I2C_MAX_INDEX] = +static i2c_device_t i2cx_device[I2C_MAX_INDEX] = { #ifdef BSP_USING_I2C0 I2C0_CONFIG, @@ -141,7 +141,7 @@ int i2c_register(enum i2c_index_type index, const char *name, uint16_t flag) int i2c_transfer(struct device *dev, i2c_msg_t msgs[], uint32_t num) { i2c_msg_t *msg; - I2C_Transfer_Cfg i2cCfg; + I2C_Transfer_Cfg i2cCfg = {0}; i2c_device_t *i2c_device = (i2c_device_t *)dev; diff --git a/drivers/bl702_driver/hal_drv/src/hal_i2s.c b/drivers/bl702_driver/hal_drv/src/hal_i2s.c index 6fa85a98..1eedd92e 100644 --- a/drivers/bl702_driver/hal_drv/src/hal_i2s.c +++ b/drivers/bl702_driver/hal_drv/src/hal_i2s.c @@ -26,7 +26,7 @@ #include "bl702_glb.h" #include "i2s_config.h" -i2s_device_t i2sx_device[I2S_MAX_INDEX] = +static i2s_device_t i2sx_device[I2S_MAX_INDEX] = { #ifdef BSP_USING_I2S0 I2S0_CONFIG, @@ -36,8 +36,8 @@ i2s_device_t i2sx_device[I2S_MAX_INDEX] = int i2s_open(struct device *dev, uint16_t oflag) { i2s_device_t *i2s_device = (i2s_device_t *)dev; - I2S_CFG_Type i2sCfg; - I2S_FifoCfg_Type fifoCfg; + I2S_CFG_Type i2sCfg = {0}; + I2S_FifoCfg_Type fifoCfg = {0}; GLB_Set_Chip_Out_0_CLK_Sel(GLB_CHIP_CLK_OUT_I2S_REF_CLK); GLB_Set_I2S_CLK(ENABLE,GLB_I2S_OUT_REF_CLK_SRC); diff --git a/drivers/bl702_driver/hal_drv/src/hal_mjpeg.c b/drivers/bl702_driver/hal_drv/src/hal_mjpeg.c new file mode 100644 index 00000000..98c1c391 --- /dev/null +++ b/drivers/bl702_driver/hal_drv/src/hal_mjpeg.c @@ -0,0 +1,123 @@ +/** + * @file hal_mjpeg.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "bl702_mjpeg.h" +#include "bl702_glb.h" +#include "hal_mjpeg.h" + +void mjpeg_init(mjpeg_device_t *mjpeg_cfg) +{ + MJPEG_CFG_Type mjpegCfg = + { + .burst = MJPEG_BURST_INCR16, + .quality = mjpeg_cfg->quality, + .yuv = mjpeg_cfg->yuv_format, + .waitCount = 0x400, + .bufferMjpeg = mjpeg_cfg->write_buffer_addr, + .sizeMjpeg = mjpeg_cfg->write_buffer_size, + .bufferCamYY = mjpeg_cfg->read_buffer_addr, + .sizeCamYY = mjpeg_cfg->read_buffer_size, + .bufferCamUV = 0, + .sizeCamUV = 0, + .resolutionX = mjpeg_cfg->resolution_x, + .resolutionY = mjpeg_cfg->resolution_y, + .bitOrderEnable = ENABLE, + .evenOrderEnable = ENABLE, + .swapModeEnable = DISABLE, + .overStopEnable = ENABLE, + .reflectDmy = DISABLE, + .verticalDmy = DISABLE, + .horizationalDmy = DISABLE, + }; + + static MJPEG_Packet_Type packetCfg = + { + .packetEnable = DISABLE, + .endToTail = DISABLE, + .frameHead = 0, + .frameTail = DISABLE, + .packetHead = 0, + .packetBody = 0, + .packetTail = 0, + }; + GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_MJPEG); + + MJPEG_Init(&mjpegCfg); + + if(mjpeg_cfg->packet_cut_mode & MJPEG_PACKET_ADD_DEFAULT) + { + packetCfg.packetEnable = ENABLE; + packetCfg.packetHead = mjpeg_cfg->packet_head_length; + packetCfg.packetBody = mjpeg_cfg->packet_body_length; + packetCfg.packetTail = mjpeg_cfg->packet_tail_length; + } + if(mjpeg_cfg->packet_cut_mode & MJPEG_PACKET_ADD_FRAME_HEAD) + { + packetCfg.frameHead = mjpeg_cfg->frame_head_length; + } + if(mjpeg_cfg->packet_cut_mode & MJPEG_PACKET_ADD_FRAME_TAIL) + { + packetCfg.frameTail = ENABLE; + } + if(mjpeg_cfg->packet_cut_mode & MJPEG_PACKET_ADD_END_TAIL) + { + packetCfg.endToTail = ENABLE; + } + + MJPEG_Packet_Config(&packetCfg); + if(mjpeg_cfg->yuv_format == MJPEG_YUV_FORMAT_YUV422_INTERLEAVE) + MJPEG_Set_YUYV_Order_Interleave(1,0,3,2); + +} + +void mjpeg_start(void) +{ + MJPEG_Enable(); +} + +void mjpeg_stop(void) +{ + MJPEG_Disable(); +} + +uint8_t mjpeg_get_one_frame(uint8_t **pic, uint32_t *len, uint8_t *q) +{ + MJPEG_Frame_Info info; + arch_memset(&info, 0, sizeof(info)); + + MJPEG_Get_Frame_Info(&info); + + if (info.validFrames == 0) + { + return ERROR; + } + *pic = (uint8_t *)(info.curFrameAddr); + *len = info.curFrameBytes; + *q = info.curFrameQ; + + return SUCCESS; +} + +void mjpeg_drop_one_frame(void) +{ + MJPEG_Pop_Frame(); +} \ No newline at end of file diff --git a/drivers/bl702_driver/hal_drv/src/hal_mtimer.c b/drivers/bl702_driver/hal_drv/src/hal_mtimer.c index 9751633f..395f1f95 100644 --- a/drivers/bl702_driver/hal_drv/src/hal_mtimer.c +++ b/drivers/bl702_driver/hal_drv/src/hal_mtimer.c @@ -22,69 +22,56 @@ */ #include "hal_mtimer.h" #include "bl702_glb.h" -/** - * @brief - * - */ -void mtimer_init(void) + +static void (*systick_callback)(void); +static uint64_t next_compare_tick = 0; +static uint64_t current_set_ticks = 0; + +static void Systick_Handler(void) { - NVIC_DisableIRQ(MTIME_IRQn); - /* Set MTimer the same frequency as SystemCoreClock */ - GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, 7); - *(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIME) = 0; -} -/** - * @brief - * - */ -void mtimer_deinit() -{ - NVIC_DisableIRQ(MTIME_IRQn); - mtimer_stop(); + *(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIMECMP) = next_compare_tick; + systick_callback(); + next_compare_tick += current_set_ticks; } + /** * @brief * * @param time * @param interruptFun */ -void mtimer_set_alarm_time(uint64_t time, void (*interruptFun)(void)) +void mtimer_set_alarm_time(uint64_t ticks, void (*interruptfun)(void)) { - uint32_t tmp; + NVIC_DisableIRQ(MTIME_IRQn); - tmp = (SystemCoreClockGet() / (GLB_Get_BCLK_Div() + 1)); - tmp = (tmp >> 3) / 1000; + uint32_t ulCurrentTimeHigh, ulCurrentTimeLow; + volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( CLIC_CTRL_ADDR + CLIC_MTIME + 4 ); + volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( CLIC_CTRL_ADDR + CLIC_MTIME ); + volatile uint32_t ulHartId = 0; - time = time * tmp; + current_set_ticks = ticks; + systick_callback = interruptfun; - *(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIMECMP) = (*(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIME) + time); + __asm volatile( "csrr %0, mhartid" : "=r"( ulHartId ) ); + do + { + ulCurrentTimeHigh = *pulTimeHigh; + ulCurrentTimeLow = *pulTimeLow; + } while( ulCurrentTimeHigh != *pulTimeHigh ); - Interrupt_Handler_Register(MTIME_IRQn, interruptFun); + next_compare_tick = ( uint64_t ) ulCurrentTimeHigh; + next_compare_tick <<= 32ULL; + next_compare_tick |= ( uint64_t ) ulCurrentTimeLow; + next_compare_tick += ( uint64_t ) current_set_ticks; + + *(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIMECMP) = next_compare_tick; + + /* Prepare the time to use after the next tick interrupt. */ + next_compare_tick += ( uint64_t ) current_set_ticks; + + Interrupt_Handler_Register(MTIME_IRQn, Systick_Handler); NVIC_EnableIRQ(MTIME_IRQn); } -/** - * @brief - * - */ -void mtimer_start() -{ - *(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIME) = 0; -} -/** - * @brief - * - */ -void mtimer_stop() -{ -} -/** - * @brief - * - */ -void mtimer_clear_time() -{ - *(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIME) = 0; -} /** * @brief @@ -103,33 +90,17 @@ uint64_t mtimer_get_time_ms() uint64_t mtimer_get_time_us() { - uint32_t tmpValLow, tmpValHigh, tmpValLow1, tmpValHigh1; - uint32_t cnt = 0, tmp; + uint32_t tmpValLow, tmpValHigh, tmpValHigh1; do { tmpValLow = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME); tmpValHigh = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME + 4); - tmpValLow1 = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME); tmpValHigh1 = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME + 4); - cnt++; - if (cnt > 4) - { - break; - } - } while (tmpValLow > tmpValLow1 || tmpValHigh > tmpValHigh1); + } while (tmpValHigh != tmpValHigh1); - tmp = (SystemCoreClockGet() / (GLB_Get_BCLK_Div() + 1)); - tmp = (tmp >> 3) / 1000 / 1000; + return (((uint64_t)tmpValHigh << 32) + tmpValLow); - if (tmpValHigh1 == 0) - { - return (uint64_t)(tmpValLow1 / tmp); - } - else - { - return (((uint64_t)tmpValHigh1 << 32) + tmpValLow1) / tmp; - } } /** * @brief diff --git a/drivers/bl702_driver/hal_drv/src/hal_power.c b/drivers/bl702_driver/hal_drv/src/hal_power.c new file mode 100644 index 00000000..27bd875a --- /dev/null +++ b/drivers/bl702_driver/hal_drv/src/hal_power.c @@ -0,0 +1,1505 @@ +/** + * @file hal_power.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "misc.h" +#include "bl702_sflash.h" +#include "bl702_sec_eng.h" +#include "bl702_ef_ctrl.h" +#include "bl702_glb.h" +#include "bl702_pds.h" +#include "bl702_clock.h" +#include "power_config.h" +#include "hal_power.h" + +/** + * @brief gating peripheral clock for power saving + * + * @param enable + * @param clockType + * @return int + */ +int lp_set_clock_gate(uint8_t enable , Clock_Gate_Type clockType){ + + if(clockType == CLOCK_AHB_ALL){ + + for (uint8_t i = CLOCK_AHB_UART0_GATE; i < CLOCK_AHB_ALL; i++) + { + GLB_AHB_Slave1_Clock_Gate(enable, i); + } + + return 0; + } + + return GLB_AHB_Slave1_Clock_Gate(enable,clockType); +} + +/** + * @brief Set the gpio hz object + * + * set all gpio to high z for power saving + * + */ +void lp_set_all_gpio_hz(void) +{ + GLB_GPIO_Cfg_Type gpio_cfg = { + .gpioPin = GLB_GPIO_PIN_14, + .gpioFun = GPIO_FUN_GPIO, + .gpioMode = GPIO_MODE_OUTPUT, + .pullType = GPIO_PULL_UP, + .drive = 0, + .smtCtrl = 1}; + for (GLB_GPIO_Type pin = GLB_GPIO_PIN_0; pin < GLB_GPIO_PIN_MAX; pin++) + { + GLB_GPIO_Init(&gpio_cfg); + GLB_GPIO_Set_HZ(gpio_cfg.gpioPin); + } +} + +void lp_power_off_dll(void){ + GLB_Power_Off_DLL(); +} + + +/** + * @brief enter cpu into mode + * + * wfi mode will suspend CPU for power saving, if any interrupt happned CPU + * will continue to run. + * + * @return int + */ +int lp_enter_wfi(void){ + + HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_1P10V); + + __WFI(); + + return 0; +} +/** @defgroup Hal_Power_Global_Variables + * + * @brief PDS level config + * @{ + */ +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel0 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 3, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 0, + .BzIsoEn = 0, + .BleIsoEn = 1, + .UsbIsoEn = 0, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 0, + .cpuRst = 0, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 0, + .BzRst = 0, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 0, + .UsbRst = 0, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel1 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 3, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 0, + .BzIsoEn = 0, + .BleIsoEn = 1, + .UsbIsoEn = 1, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 0, + .cpuRst = 0, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 0, + .BzRst = 0, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 1, + .UsbRst = 1, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel2 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 2, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 0, + .BzIsoEn = 1, + .BleIsoEn = 1, + .UsbIsoEn = 0, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 0, + .cpuRst = 0, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 1, + .BzRst = 1, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 0, + .UsbRst = 0, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel3 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 2, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 0, + .BzIsoEn = 1, + .BleIsoEn = 1, + .UsbIsoEn = 1, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 0, + .cpuRst = 0, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 1, + .BzRst = 1, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 1, + .UsbRst = 1, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel4 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 3, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 1, + .BzIsoEn = 0, + .BleIsoEn = 1, + .UsbIsoEn = 0, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 1, + .cpuRst = 1, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 0, + .BzRst = 0, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 0, + .UsbRst = 0, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel5 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 3, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 1, + .BzIsoEn = 0, + .BleIsoEn = 1, + .UsbIsoEn = 1, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 1, + .cpuRst = 1, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 0, + .BzRst = 0, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 1, + .UsbRst = 1, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel6 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 2, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 1, + .BzIsoEn = 1, + .BleIsoEn = 1, + .UsbIsoEn = 0, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 1, + .cpuRst = 1, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 1, + .BzRst = 1, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 0, + .UsbRst = 0, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel7 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 1, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 2, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 1, + .BzIsoEn = 1, + .BleIsoEn = 1, + .UsbIsoEn = 1, + .MiscIsoEn = 0, + }, + .pdsCtl4 = { + .cpuPwrOff = 1, + .cpuRst = 1, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 1, + .BzRst = 1, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 1, + .UsbRst = 1, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 0, + .MiscRst = 0, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel31 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .saveWifiState = 0, + .dcdc18Off = 1, + .bgSysOff = 1, + .gpioIePuPd = 1, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 0, + .socEnbForceOn = 0, + .pdsRstSocEn = 0, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 0, + .pdsRamLowPowerWithClkEn = 1, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsForceRamClkEn = 0, + .pdsLdoVol = 0xA, + .pdsCtlRfSel = 2, + .pdsCtlPllSel = 0, + }, + .pdsCtl2 = { + .forceCpuPwrOff = 0, + .forceBzPwrOff = 0, + .forceUsbPwrOff = 0, + .forceCpuIsoEn = 0, + .forceBzIsoEn = 0, + .forceUsbIsoEn = 0, + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceUsbPdsRst = 0, + .forceCpuMemStby = 0, + .forceBzMemStby = 0, + .forceUsbMemStby = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + .forceUsbGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceBlePwrOff = 0, + .forceBleIsoEn = 0, + .forceMiscPdsRst = 0, + .forceBlePdsRst = 0, + .forceMiscMemStby = 0, + .forceBleMemStby = 0, + .forceMiscGateClk = 0, + .forceBleGateClk = 0, + .CpuIsoEn = 1, + .BzIsoEn = 1, + .BleIsoEn = 1, + .UsbIsoEn = 1, + .MiscIsoEn = 1, + }, + .pdsCtl4 = { + .cpuPwrOff = 1, + .cpuRst = 1, + .cpuMemStby = 1, + .cpuGateClk = 1, + .BzPwrOff = 1, + .BzRst = 1, + .BzMemStby = 1, + .BzGateClk = 1, + .BlePwrOff = 1, + .BleRst = 1, + .BleMemStby = 1, + .BleGateClk = 1, + .UsbPwrOff = 1, + .UsbRst = 1, + .UsbMemStby = 1, + .UsbGateClk = 1, + .MiscPwrOff = 1, + .MiscRst = 1, + .MiscMemStby = 1, + .MiscGateClk = 1, + .MiscAnaPwrOff = 1, + .MiscDigPwrOff = 1, + } +}; +static SPI_Flash_Cfg_Type flashCfg_Gd_Q80E_Q16E = { + .resetCreadCmd = 0xff, + .resetCreadCmdSize = 3, + .mid = 0xc8, + + .deBurstWrapCmd = 0x77, + .deBurstWrapCmdDmyClk = 0x3, + .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, + .deBurstWrapData = 0xF0, + + /*reg*/ + .writeEnableCmd = 0x06, + .wrEnableIndex = 0x00, + .wrEnableBit = 0x01, + .wrEnableReadRegLen = 0x01, + + .qeIndex = 1, + .qeBit = 0x01, + .qeWriteRegLen = 0x02, + .qeReadRegLen = 0x1, + + .busyIndex = 0, + .busyBit = 0x00, + .busyReadRegLen = 0x1, + .releasePowerDown = 0xab, + + .readRegCmd[0] = 0x05, + .readRegCmd[1] = 0x35, + .writeRegCmd[0] = 0x01, + .writeRegCmd[1] = 0x01, + + .fastReadQioCmd = 0xeb, + .frQioDmyClk = 16 / 8, + .cReadSupport = 1, + .cReadMode = 0xA0, + + .burstWrapCmd = 0x77, + .burstWrapCmdDmyClk = 0x3, + .burstWrapDataMode = SF_CTRL_DATA_4_LINES, + .burstWrapData = 0x40, + /*erase*/ + .chipEraseCmd = 0xc7, + .sectorEraseCmd = 0x20, + .blk32EraseCmd = 0x52, + .blk64EraseCmd = 0xd8, + /*write*/ + .pageProgramCmd = 0x02, + .qpageProgramCmd = 0x32, + .qppAddrMode = SF_CTRL_ADDR_1_LINE, + + .ioMode = SF_CTRL_QIO_MODE, + .clkDelay = 1, + .clkInvert = 0x3f, + + .resetEnCmd = 0x66, + .resetCmd = 0x99, + .cRExit = 0xff, + .wrEnableWriteRegLen = 0x00, + + /*id*/ + .jedecIdCmd = 0x9f, + .jedecIdCmdDmyClk = 0, + .qpiJedecIdCmd = 0x9f, + .qpiJedecIdCmdDmyClk = 0x00, + .sectorSize = 4, + .pageSize = 256, + + /*read*/ + .fastReadCmd = 0x0b, + .frDmyClk = 8 / 8, + .qpiFastReadCmd = 0x0b, + .qpiFrDmyClk = 8 / 8, + .fastReadDoCmd = 0x3b, + .frDoDmyClk = 8 / 8, + .fastReadDioCmd = 0xbb, + .frDioDmyClk = 0, + .fastReadQoCmd = 0x6b, + .frQoDmyClk = 8 / 8, + + .qpiFastReadQioCmd = 0xeb, + .qpiFrQioDmyClk = 16 / 8, + .qpiPageProgramCmd = 0x02, + .writeVregEnableCmd = 0x50, + + /* qpi mode */ + .enterQpi = 0x38, + .exitQpi = 0xff, + + /*AC*/ + .timeEsector = 300, + .timeE32k = 1200, + .timeE64k = 1200, + .timePagePgm = 5, + .timeCe = 20 * 1000, + .pdDelay = 20, + .qeData = 0, +}; +static void (*glb_preCbFun)(void); +static void (*glb_postCbFun)(void); +/*@} end of group Hal_Power_Global_Variables */ + +/****************************************************************************//** + * @brief PDS update flash_ctrl setting + * + * @param fastClock: fast clock + * + * @return None + * +*******************************************************************************/ +static ATTR_TCM_SECTION void PDS_Update_Flash_Ctrl_Setting(uint8_t fastClock) +{ + if(fastClock){ + GLB_Set_SF_CLK(1, GLB_SFLASH_CLK_96M, 0); + }else{ + GLB_Set_SF_CLK(1, GLB_SFLASH_CLK_XCLK, 0); + } + SF_Ctrl_Set_Clock_Delay(fastClock); +} + +/****************************************************************************//** + * @brief PDS power on flash pad gpio + * + * @param flashPinCfg: flash pin config + * + * @return None + * +*******************************************************************************/ +static ATTR_TCM_SECTION void PDS_Power_On_Flash_Pad(uint8_t flashPinCfg) +{ + switch(flashPinCfg){ + case 0: + HBN_Set_Pad_23_28_Pullnone(); + break; + case 1: + break; + case 2: + break; + case 3: + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_23,PDS_PAD_CFG_PULL_NONE); + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_24,PDS_PAD_CFG_PULL_NONE); + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_25,PDS_PAD_CFG_PULL_NONE); + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_26,PDS_PAD_CFG_PULL_NONE); + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_27,PDS_PAD_CFG_PULL_NONE); + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_28,PDS_PAD_CFG_PULL_NONE); + break; + default : + break; + } + + /* Init flash gpio */ + SF_Cfg_Init_Flash_Gpio(flashPinCfg,1); +} + +/****************************************************************************//** + * @brief PDS power on flash + * + * @param cfg: PDS app config + * + * @return None + * +*******************************************************************************/ +static ATTR_TCM_SECTION void PDS_Power_On_Flash(PDS_APP_CFG_Type *cfg) +{ + /* Init flash gpio */ + //SF_Cfg_Init_Flash_Gpio(0,1); + + SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); + + /* Restore flash */ + SFlash_Restore_From_Powerdown(cfg->flashCfg,cfg->flashContRead); +} + +/****************************************************************************//** + * @brief power down sleep mode test function + * + * @param cfg: PDS app config + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION PDS_Mode_Enter(PDS_APP_CFG_Type *cfg) +{ + PDS_DEFAULT_LV_CFG_Type *pPdsCfg = NULL; + uint32_t tmpVal=0,tmpVal2=0; + + if(cfg->useXtal32k){ + HBN_32K_Sel(HBN_32K_XTAL); + }else{ + HBN_32K_Sel(HBN_32K_RC); + HBN_Power_Off_Xtal_32K(); + } + + /* turn_off_sec_ring */ + SEC_Eng_Turn_Off_Sec_Ring(); /* E_ITEM_04 */ + + /* disable sec_eng to reduce current which enabled by bflb_platform_init(0) */ + Sec_Eng_Trng_Disable(); + + /* pre callback */ + if(cfg->preCbFun){ + cfg->preCbFun(); + } + + /* always disable HBN pin pull up/down for reduce PDS0/1/2/3/7 current, 0x4000F014[16]=0 */ + HBN_Hw_Pu_Pd_Cfg(DISABLE); + + /* mask/unmask HBN pin wakeup, 0x4000F014[4:3] */ + HBN_Pin_WakeUp_Mask(~(cfg->pdsAonGpioWakeupSrc)); + HBN_Aon_Pad_IeSmt_Cfg(cfg->pdsAonGpioWakeupSrc); + if(cfg->pdsAonGpioWakeupSrc!=0){ + HBN_GPIO_INT_Enable(cfg->pdsAonGpioTrigType); + } + + /* always disable and mask aon_pad_GPIO9, mask/unmask and ie_enable/ie_disable */ + tmpVal=BL_RD_REG(HBN_BASE,HBN_IRQ_MODE); + tmpVal2=BL_GET_REG_BITS_VAL(tmpVal,HBN_PIN_WAKEUP_MASK); + tmpVal2|=(1<<0); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_PIN_WAKEUP_MASK,tmpVal2); + tmpVal2=BL_GET_REG_BITS_VAL(tmpVal,HBN_REG_AON_PAD_IE_SMT); + tmpVal2&=~(1<<0); + tmpVal=BL_SET_REG_BITS_VAL(tmpVal,HBN_REG_AON_PAD_IE_SMT,tmpVal2); + BL_WR_REG(HBN_BASE,HBN_IRQ_MODE,tmpVal); + + /* To make it simple and safe*/ + __disable_irq(); + + if(cfg->powerDownFlash){ + HBN_Power_Down_Flash(cfg->flashCfg); + GLB_Select_External_Flash(); + } + + HBN_Set_Ldo11_All_Vout(cfg->ldoLevel); + + if(cfg->turnOffXtal32m){ + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M); + AON_Power_Off_XTAL(); + } + + if(cfg->turnOffDll){ + GLB_Power_Off_DLL(); + } + + /* power off PLL to reduce current */ + if(cfg->turnoffPLL){ + GLB_Set_System_CLK(GLB_DLL_XTAL_NONE,GLB_SYS_CLK_RC32M); + PDS_Update_Flash_Ctrl_Setting(0); + PDS_Power_Off_PLL(); + } + + /* pds0-pds7 : ldo11rt_iload_sel=3 */ + /* pds31 : ldo11rt_iload_sel=1 */ + if((cfg->pdsLevel>=0)&&(cfg->pdsLevel<=7)){ + HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_25_250UA); + }else if(cfg->pdsLevel==31){ + HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_10_100UA); + }else{ + /* pdsLevel error */ + } + + switch(cfg->pdsLevel){ + case 0: + pPdsCfg = &pdsCfgLevel0; + break; + case 1: + pPdsCfg = &pdsCfgLevel1; + break; + case 2: + pPdsCfg = &pdsCfgLevel2; + break; + case 3: + pPdsCfg = &pdsCfgLevel3; + break; + case 4: + pPdsCfg = &pdsCfgLevel4; + break; + case 5: + pPdsCfg = &pdsCfgLevel5; + break; + case 6: + pPdsCfg = &pdsCfgLevel6; + break; + case 7: + pPdsCfg = &pdsCfgLevel7; + break; + case 31: + pPdsCfg = &pdsCfgLevel31; + break; + default : + /* pdsLevel error */ + while(1){ + BL702_Delay_MS(500); + } + break; + } + + if(cfg->turnOffFlashPad){ + switch(cfg->flashPinCfg){ + case 0: + /* turn_off_ext_flash_pin, GPIO23 - GPIO28 */ + for(uint32_t pin=23;pin<=28;pin++){ + GLB_GPIO_Set_HZ(pin); + } + HBN_Set_Pad_23_28_Pullup(); + break; + case 1: + /* turn_off_internal_flash_pin, GPIO23 - GPIO28 */ + for(uint32_t pin=23;pin<=28;pin++){ + GLB_GPIO_Set_HZ(pin); + } + break; + case 2: + /* turn_off_internal_flash_pin, GPIO23 - GPIO28 */ + for(uint32_t pin=23;pin<=28;pin++){ + GLB_GPIO_Set_HZ(pin); + } + break; + case 3: + /* turn_off_ext_flash_pin, GPIO17 - GPIO22 */ + for(uint32_t pin=17;pin<=22;pin++){ + GLB_GPIO_Set_HZ(pin); + } + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_23,PDS_PAD_CFG_PULL_UP); + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_24,PDS_PAD_CFG_PULL_UP); + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_25,PDS_PAD_CFG_PULL_UP); + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_26,PDS_PAD_CFG_PULL_UP); + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_27,PDS_PAD_CFG_PULL_UP); + PDS_Set_Pad_Config(PDS_PAD_PIN_GPIO_28,PDS_PAD_CFG_PULL_UP); + break; + default : + break; + } + pPdsCfg->pdsCtl.puFlash = 1; /* power switch setting, set 1 for internal flash, has no effect on ext flash */ + } + + if(cfg->pdsHoldGpio){ + pPdsCfg->pdsCtl.gpioIePuPd = 1; + }else{ + pPdsCfg->pdsCtl.gpioIePuPd = 0; + } + + pPdsCfg->pdsCtl.pdsLdoVol = cfg->ldoLevel; + pPdsCfg->pdsCtl.pdsLdoVselEn = 1; + + if(!(cfg->turnOffRF)){ + pPdsCfg->pdsCtl.pdsCtlRfSel = 0; + } + + /* config ldo11soc_sstart_delay_aon =2 , cr_pds_pd_ldo11=0 to speedup ldo11soc_rdy_aon */ + AON_Set_LDO11_SOC_Sstart_Delay(0x2); + + PDS_Default_Level_Config(pPdsCfg,cfg->sleepTime); + __WFI(); /* if(.wfiMask==0){CPU won't power down until PDS module had seen __wfi} */ + + /* Wake up from PDS */ + /* post callback, mainly for GPIO or peripherals on/off */ + if(cfg->postCbFun){ + cfg->postCbFun(); + } + + if(cfg->turnoffPLL){ + GLB_Set_System_CLK(cfg->xtalType,GLB_SYS_CLK_DLL144M); + PDS_Update_Flash_Ctrl_Setting(1); + } + + if(cfg->turnOffFlashPad){ + PDS_Power_On_Flash_Pad(cfg->flashPinCfg); + } + + if(cfg->powerDownFlash){ + PDS_Power_On_Flash(cfg); /* call GLB_Select_Internal_Flash() in this API */ + } + + /* always turn_on_sec_ring, may cost more current */ + SEC_Eng_Turn_On_Sec_Ring(); /* E_ITEM_04 */ + + /* always enable sec_eng, may cost more current */ + Sec_Eng_Trng_Enable(); + + HBN_Aon_Pad_IeSmt_Cfg(ENABLE); + + __enable_irq(); +} + +/** + * @brief callback function before entry into pds + * + */ +static void ATTR_TCM_SECTION PDS_Pre_CallBack(void) +{ + GLB_GPIO_Cfg_Type gpioCfg = { + .gpioPin = GLB_GPIO_PIN_0, + .gpioFun = GPIO_FUN_GPIO, + .gpioMode = GPIO_MODE_INPUT, + .pullType = GPIO_PULL_NONE, + .drive = 0, + .smtCtrl = 0, + }; + + /* turn off gpio except for CCI, GPIO0 - GPIO22 */ + for (GLB_GPIO_Type pin = GLB_GPIO_PIN_0; pin < GLB_GPIO_PIN_MAX; pin++) + { + + GLB_CCI_Use_IO_0_1_2_7(DISABLE); + GLB_CCI_Use_Jtag_Pin(DISABLE); + + /* flash pin GPIO17~GPIO22 */ + if ((pin >= GLB_GPIO_PIN_17) && (pin <= GLB_GPIO_PIN_22)) + { + continue; + } + /* flash pin GPIO23~GPIO28 */ + if ((pin >= GLB_GPIO_PIN_23) && (pin <= GLB_GPIO_PIN_28)) + { + continue; + } + /* DBG_TX pin */ + if (pin == GLB_GPIO_PIN_14) + { + continue; + } + gpioCfg.gpioPin = pin; + GLB_GPIO_Init(&gpioCfg); + GLB_GPIO_Set_HZ(gpioCfg.gpioPin); + } + + if(glb_preCbFun != NULL) + glb_preCbFun(); +} + +/** + * @brief callback function after wake up form pds if cpu do not reset + * + */ +static void ATTR_TCM_SECTION PDS_Post_CallBack(void) +{ + HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_1P00V); + + if(glb_postCbFun != NULL) + glb_postCbFun(); +} +/** + * @brief enter cpu into pds mode + * + * pds(power down sleep) mode will set CPU into sleep mode. + * cpu's behavior after wakeup depend on psd level + * + * see flow table if cpu off , cpu will reset after wakeup + * + * PD_CORE PD_CORE_MISC_DIG PD_CORE_MISC_ANA PD_CORE_CPU PD_BZ PD_USB + * PDS0 ON ON ON ON ON ON + * PDS1 ON ON ON ON ON OFF + * PDS2 ON ON ON ON OFF ON + * PDS3 ON ON ON ON OFF OFF + * PDS4 ON ON ON OFF ON ON + * PDS5 ON ON ON OFF ON OFF + * PDS6 ON ON ON OFF OFF ON + * PDS7 ON ON ON OFF OFF OFF + * PDS31 ON OFF OFF OFF OFF OFF + * + * + * now default pds level is pds31 + * @return int + */ +int lp_enter_pds(uint32_t sleep_time ,void (*preCbFun)(void),void (*postCbFun)(void)) +{ + + PDS_APP_CFG_Type pdsCfg = { + .pdsLevel = 31, /*!< PDS level */ + .turnOffXtal32m = DEFAULT_LP_PDS_TURN_OFF_XTAL_32M, /*!< Wheather turn off XTAL32M */ + .turnOffDll = DEFAULT_LP_PDS_TURN_OFF_DLL, /*!< Wheather turn off DLL */ + .turnOffRF = DEFAULT_LP_PDS_TURN_OFF_RF, /*!< Wheather turn off RF */ + .useXtal32k = DEFAULT_LP_PDS_USE_XTAL_32K, /*!< Wheather use xtal 32K as 32K clock source,otherwise use rc32k */ + .pdsAonGpioWakeupSrc = DEFAULT_LP_PDS_AON_GPIO_WAKE_UP_SRC, /*!< PDS level 0-7,31 mode aon GPIO Wakeup source(HBN wakeup pin) */ + .pdsAonGpioTrigType = DEFAULT_LP_PDS_AON_GPIO_TRIG_TYPE, /*!< PDS level 0-7,31 mode aon GPIO Triger type(HBN wakeup pin) */ + .powerDownFlash = DEFAULT_LP_PDS_FLASH_POWER_DOWN, /*!< Whether power down flash */ + .pdsHoldGpio = DEFAULT_LP_PDS_HOLD_GPIO, /*!< Whether pds hold gpio level */ + .turnOffFlashPad = DEFAULT_LP_PDS_TURN_OFF_FLASH_PAD, /*!< Whether turn off ext flash pad(GPIO17-GPIO22, GPIO23-GPIO28) */ + .flashPinCfg = 0, + .turnoffPLL=1, /*!< Whether trun off PLL */ /*!< 0 ext flash 23-28, 1 internal flash 23-28, 2 internal flash 23-28, 3 ext flash 17-22 */ + .xtalType = DEAULT_LP_XTAL_TYPE, /*!< XTal type, used when user choose turn off PLL, PDS will turn on when exit PDS mode */ + .flashContRead = 0, /*!< Whether enable flash continue read */ + .sleepTime = 10 * 32768, /*!< PDS sleep time */ + .flashCfg = &flashCfg_Gd_Q80E_Q16E, /*!< Flash config pointer, used when power down flash */ + .ldoLevel = DEFAULT_LP_LDO_LEVEL, /*!< LDO level */ + .preCbFun = PDS_Pre_CallBack, /*!< Pre callback function */ + .postCbFun = PDS_Post_CallBack, /*!< Post callback function */ + }; + + BL702_Delay_MS(2000); + + glb_preCbFun = preCbFun; + glb_postCbFun = postCbFun; + + pdsCfg.sleepTime = sleep_time; + + HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_1P00V); + + PDS_WAKEUP_IRQHandler_Install(); + + /* enable PDS interrupt to wakeup CPU (PDS1:CPU not powerdown, CPU __WFI) */ + NVIC_EnableIRQ(PDS_WAKEUP_IRQn); + + /* clear and mask PDS int */ + PDS_IntMask(PDS_INT_WAKEUP, UNMASK); + PDS_IntMask(PDS_INT_RF_DONE, MASK); + PDS_IntMask(PDS_INT_PLL_DONE, MASK); + PDS_IntClear(); + + BL702_Delay_MS(100); + + PDS_Mode_Enter(&pdsCfg); + + while(1) + { + //MSG("pds wakeup and running.\r\n"); + BL702_Delay_MS(1000); + } + + return 0; +} + +/****************************************************************************//** + * @brief Make buf word + * + * @param data: Data + * + * @return Word data + * +*******************************************************************************/ +static uint32_t put_word_buf(uint8_t data) +{ + return (data<<24)+(data<<16)+(data<<8)+data; +} + +/****************************************************************************//** + * @brief HBN Check RAM Data + * + * @param accessDelay: delay time for access + * + * @return None + * +*******************************************************************************/ +static void HBN_Check_RAM(uint32_t accessDelay) +{ + uint32_t i; + uint8_t hbnWakeup=0; + uint32_t *hbnVal=(uint32_t *)HBN_RAM_BASE; + uint32_t *hbnCount=(uint32_t *)(HBN_RAM_BASE+HBN_RAM_SIZE-4); + + MSG("HBN wakeup Case.Check reset to check case success\r\n"); + if(HBN_STATUS_WAKEUP_FLAG==HBN_Get_Status_Flag()){ + MSG("System wakeup from HBN\r\n"); + hbnWakeup=1; + MSG("HBN RTC Wakeup, HBN RAM Buff: %d\r\n", *hbnCount); + + for(i=0; iclkDiv = 1200; - pwmCfg->period = 60000/freq; - pwmCfg->threshold2 = 600*duty/freq; - }else if(freq <= 140){ - pwmCfg->clkDiv = 16; - pwmCfg->period = 4500000/freq; - pwmCfg->threshold2 = 45000*duty/freq; - }else if(freq <= 275){ - pwmCfg->clkDiv = 8; - pwmCfg->period = 9000000/freq; - pwmCfg->threshold2 = 90000*duty/freq; - }else if(freq <=550){ - pwmCfg->clkDiv = 4; - pwmCfg->period = 18000000/freq; - pwmCfg->threshold2 = 180000*duty/freq; - }else if(freq <=1100){ - pwmCfg->clkDiv = 2; - pwmCfg->period = 36000000/freq; - pwmCfg->threshold2 = 360000*duty/freq; - }else{ - pwmCfg->clkDiv = 1; - pwmCfg->period = 72000000/freq; - pwmCfg->threshold2 = 720000*duty/freq; - } - break; - case KHZ: - if(freq <= 2){ - pwmCfg->clkDiv = 2; - pwmCfg->period = 36000/freq; - pwmCfg->threshold2 = 360*duty/freq; - }else{ - pwmCfg->clkDiv = 1; - pwmCfg->period = 72000/freq; - pwmCfg->threshold2 = 720*duty/freq; - } - break; - case MHZ: - pwmCfg->clkDiv = 1; - pwmCfg->period = 72/freq; - pwmCfg->threshold2 = 72*duty/freq/100; - break; - default: - break; - } + pwmCfg.clkDiv = 1200; + pwmCfg.period = 60000/frequence; + pwmCfg.threshold2 = 600*dutycycle/frequence; + } + else if(frequence <= 140) + { + pwmCfg.clkDiv = 16; + pwmCfg.period = 4500000/frequence; + pwmCfg.threshold2 = 45000*dutycycle/frequence; + } + else if(frequence <= 275) + { + pwmCfg.clkDiv = 8; + pwmCfg.period = 9000000/frequence; + pwmCfg.threshold2 = 90000*dutycycle/frequence; + } + else if(frequence <= 550) + { + pwmCfg.clkDiv = 4; + pwmCfg.period = 18000000/frequence; + pwmCfg.threshold2 = 180000*dutycycle/frequence; + } + else if(frequence <= 1100) + { + pwmCfg.clkDiv = 2; + pwmCfg.period = 36000000/frequence; + pwmCfg.threshold2 = 360000*dutycycle/frequence; + } + else + { + pwmCfg.clkDiv = 1; + pwmCfg.period = 72000000/frequence; + pwmCfg.threshold2 = 720000*dutycycle/frequence; + } - PWM_Channel_Set_Div(pwm_device->ch ,pwmCfg->clkDiv); - PWM_Channel_Update(pwm_device->ch ,pwmCfg->period,0,pwmCfg->threshold2); + PWM_Channel_Set_Div(ch,pwmCfg.clkDiv); + PWM_Channel_Update(ch,pwmCfg.period,0,pwmCfg.threshold2); } int pwm_open(struct device *dev, uint16_t oflag) { - PWM_CH_CFG_Type pwmCfg = { - 0, /* PWM channel */ - PWM_CLK_BCLK, /* PWM Clock */ - PWM_STOP_GRACEFUL, /* PWM Stop Mode */ - PWM_POL_NORMAL, /* PWM mode type */ - 1, /* PWM clkDiv num */ - 100, /* PWM period set */ - 0, /* PWM threshold1 num */ - 50, /* PWM threshold2 num */ - 0, /* PWM interrupt pulse count */ - }; pwm_device_t *pwm_device = (pwm_device_t *)dev; + PWM_CH_CFG_Type pwmCfg = {0}; + + PWM_Channel_Disable(pwm_device->ch); + PWM_IntMask(pwm_device->ch,PWM_INT_ALL,MASK); + NVIC_DisableIRQ(PWM_IRQn); + pwmCfg.ch = pwm_device->ch; /* todo clk init at clock tree now clk fix set as bclk*/ pwmCfg.clk = PWM_CLK_BCLK; - pwmCfg.stopMode = PWM_STOP_MODE_SEL; pwmCfg.pol = PWM_POL_SEL; - - if(pwm_device->frequency < 1000){ - pwm_set(dev,&pwmCfg,pwm_device->frequency,HZ,pwm_device->dutyCycle); - }else if(pwm_device->frequency < 999999){ - pwm_set(dev,&pwmCfg,pwm_device->frequency /1000,KHZ,pwm_device->dutyCycle); - }else{ - pwm_set(dev,&pwmCfg,pwm_device->frequency /1000000,MHZ,pwm_device->dutyCycle); - } - PWM_Channel_Init(&pwmCfg); - PWM_Channel_Enable(pwm_device->ch); + pwm_channel_config(pwm_device->ch,pwm_device->frequency,pwm_device->dutycycle); + + if (oflag & DEVICE_OFLAG_INT_TX) + { + pwmCfg.intPulseCnt = pwm_device->it_pulse_count; + Interrupt_Handler_Register(PWM_IRQn,PWM_IRQ); + PWM_IntMask(pwm_device->ch,PWM_INT_PULSE_CNT,UNMASK); + NVIC_EnableIRQ(PWM_IRQn); + } + return 0; } int pwm_close(struct device *dev) @@ -155,17 +132,10 @@ int pwm_control(struct device *dev, int cmd, void *args) { pwm_device_t *pwm_device = (pwm_device_t *)dev; pwm_config_t *pwm_config = (pwm_config_t *)args; - PWM_CH_CFG_Type pwmCfg; switch (cmd) { case DEVICE_CTRL_CONFIG/* constant-expression */: - if(pwm_device->frequency < 1000){ - pwm_set(dev,&pwmCfg,pwm_config->frequency,HZ,pwm_config->dutyCycle); - }else if(pwm_device->frequency < 999999){ - pwm_set(dev,&pwmCfg,pwm_config->frequency /1000,KHZ,pwm_config->dutyCycle); - }else{ - pwm_set(dev,&pwmCfg,pwm_config->frequency /1000000,MHZ,pwm_config->dutyCycle); - } + pwm_channel_config(pwm_device->ch,pwm_config->frequency,pwm_config->dutycycle); break; case DEVICE_CTRL_RESUME /* constant-expression */: PWM_Channel_Enable(pwm_device->ch); @@ -173,6 +143,25 @@ int pwm_control(struct device *dev, int cmd, void *args) case DEVICE_CTRL_SUSPEND /* constant-expression */: PWM_Channel_Disable(pwm_device->ch); break; + case DEIVCE_CTRL_PWM_IT_PULSE_COUNT_CONFIG: + { + /* Config interrupt pulse count */ + uint32_t pwm_ch_addr = PWM_BASE+PWM_CHANNEL_OFFSET+(pwm_device->ch)*0x20; + uint32_t tmpVal = BL_RD_REG(pwm_ch_addr, PWM_INTERRUPT); + BL_WR_REG(pwm_ch_addr, PWM_INTERRUPT, BL_SET_REG_BITS_VAL(tmpVal, PWM_INT_PERIOD_CNT, (uint32_t)args)); + + if((uint32_t)args) + { + PWM_IntMask(pwm_device->ch,PWM_INT_PULSE_CNT,UNMASK); + NVIC_EnableIRQ(PWM_IRQn); + } + else + { + PWM_IntMask(pwm_device->ch,PWM_INT_PULSE_CNT,MASK); + NVIC_DisableIRQ(PWM_IRQn); + } + break; + } default: break; } @@ -202,3 +191,44 @@ int pwm_register(enum pwm_index_type index, const char *name, uint16_t flag) return device_register(dev, name, flag); } + +static void pwm_isr(pwm_device_t *handle) +{ + uint32_t i; + uint32_t tmpVal; + uint32_t timeoutCnt = 160*1000; + /* Get channel register */ + uint32_t PWMx = PWM_BASE; + + for (i = 0; i < PWM_MAX_INDEX; i++) { + tmpVal = BL_RD_REG(PWMx, PWM_INT_CONFIG); + if ((BL_GET_REG_BITS_VAL(tmpVal, PWM_INTERRUPT_STS) & (1 << handle[i].ch)) != 0) { + /* Clear interrupt */ + tmpVal |= (1 << (handle[i].ch + PWM_INT_CLEAR_POS)); + BL_WR_REG(PWMx, PWM_INT_CONFIG, tmpVal); + /* FIXME: we need set pwm_int_clear to 0 by software and + before this,we must make sure pwm_interrupt_sts is 0*/ + do{ + tmpVal = BL_RD_REG(PWMx, PWM_INT_CONFIG); + timeoutCnt--; + if(timeoutCnt == 0){ + break; + } + }while(BL_GET_REG_BITS_VAL(tmpVal,PWM_INTERRUPT_STS)&(1 << handle[i].ch)); + + tmpVal &= (~(1 << (handle[i].ch + PWM_INT_CLEAR_POS))); + BL_WR_REG(PWMx, PWM_INT_CONFIG, tmpVal); + + if (handle[i].parent.callback) + { + handle[i].parent.callback(&handle[i].parent, NULL, 0, PWM_EVENT_COMPLETE); + } + + } + } +} + +static void PWM_IRQ(void) +{ + pwm_isr(&pwmx_device[0]); +} \ No newline at end of file diff --git a/drivers/bl702_driver/hal_drv/src/hal_sec_aes.c b/drivers/bl702_driver/hal_drv/src/hal_sec_aes.c new file mode 100644 index 00000000..eba28382 --- /dev/null +++ b/drivers/bl702_driver/hal_drv/src/hal_sec_aes.c @@ -0,0 +1,117 @@ +/** + * @file hal_sec_aes.c + * @brief + * + * Copyright 2019-2030 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_sec_aes.h" +#include "bl702_sec_eng.h" + +static SEC_Eng_AES_Ctx aesCtx; + +int sec_aes_init(sec_aes_handle_t *handle,sec_aes_type aes_tye,sec_aes_key_type key_type) +{ + handle->aes_type=aes_tye; + handle->key_type=key_type; + + return 0; +} + +static SEC_ENG_AES_Key_Type sec_aes_get_key_type(sec_aes_handle_t *handle) +{ + SEC_ENG_AES_Key_Type type=0; + + switch(handle->key_type) + { + case SEC_ASE_KEY_128: + type=SEC_ENG_AES_KEY_128BITS; + break; + case SEC_ASE_KEY_256: + type=SEC_ENG_AES_KEY_256BITS; + break; + case SEC_ASE_KEY_192: + type=SEC_ENG_AES_KEY_192BITS; + break; + default: + return SEC_ENG_AES_KEY_128BITS; + } + return type; +} + +int sec_aes_setkey(sec_aes_handle_t *handle,const uint8_t *key,uint8_t key_len,const uint8_t *nonce,uint8_t dir) +{ + SEC_ENG_AES_Key_Type type=sec_aes_get_key_type(handle); + + switch(handle->aes_type) + { + case SEC_ASE_CBC: + Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID0); + Sec_Eng_AES_Init(&aesCtx,SEC_ENG_AES_ID0,SEC_ENG_AES_CBC,type, + SEC_AES_DIR_ENCRYPT==dir?SEC_ENG_AES_ENCRYPTION:SEC_ENG_AES_DECRYPTION); + break; + case SEC_ASE_CTR: + Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID0); + Sec_Eng_AES_Init(&aesCtx,SEC_ENG_AES_ID0,SEC_ENG_AES_CTR,type, + SEC_AES_DIR_ENCRYPT==dir?SEC_ENG_AES_ENCRYPTION:SEC_ENG_AES_DECRYPTION); + break; + case SEC_ASE_ECB: + break; + default: + return -1; + } + + /* if key len is 0, means key is from efuse and *key value is key_sel value */ + if(key_len==0){ + Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID0,SEC_ENG_AES_KEY_HW,key,nonce); + }else{ + Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID0,SEC_ENG_AES_KEY_SW,key,nonce); + } + + return 0; +} + +int sec_aes_encrypt(sec_aes_handle_t *handle,const uint8_t *in,uint32_t len, size_t offset,uint8_t *out) +{ + + if(SUCCESS!=Sec_Eng_AES_Crypt(&aesCtx,SEC_ENG_AES_ID0,in, len,out)){ + return -1; + } + + return 0; +} + + +int sec_aes_decrypt(sec_aes_handle_t *handle,const uint8_t *in,uint32_t len,size_t offset,uint8_t *out) +{ + + if(SUCCESS!=Sec_Eng_AES_Crypt(&aesCtx,SEC_ENG_AES_ID0,in, len,out)){ + return -1; + } + + return 0; +} + +int sec_aes_deinit(sec_aes_handle_t *handle) +{ + Sec_Eng_AES_Finish(SEC_ENG_AES_ID0); + + memset(handle,0,sizeof(sec_aes_handle_t)); + + return 0; +} diff --git a/drivers/bl702_driver/hal_drv/src/hal_sec_dsa.c b/drivers/bl702_driver/hal_drv/src/hal_sec_dsa.c new file mode 100644 index 00000000..3f5ee111 --- /dev/null +++ b/drivers/bl702_driver/hal_drv/src/hal_sec_dsa.c @@ -0,0 +1,368 @@ +/** + * @file hal_sec_dsa.c + * @brief + * + * Copyright 2019-2030 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_sec_dsa.h" +#include "bl702_sec_eng.h" + +//#define DSA_DBG 1 +//#define DSA_DBG_DETAIL 1 +void bflb_platform_dump(uint8_t *data, uint32_t len); + +#if (defined(DSA_DBG)||defined(DSA_DBG_DETAIL)) +uint32_t pka_tmp[64]={0}; +#endif + +/* +n=p*q; +F(n)=(p-1)*(q-1) +e*d%F(n)=1[e is public key and d is private key] +dP=d%(p-1) +dQ=d%(q-1) +m1=c^(dP)%p +m2=c^(dQ)%q +h=qInv*(m1-m2)%p +m=m2+h*q +m=c^d +*/ +static SEC_ENG_PKA_REG_SIZE_Type sec_dsa_get_reg_size(uint32_t size) +{ + switch(size){ + case 64: + return SEC_ENG_PKA_REG_SIZE_8; + case 128: + return SEC_ENG_PKA_REG_SIZE_16; + case 256: + return SEC_ENG_PKA_REG_SIZE_32; + case 512: + return SEC_ENG_PKA_REG_SIZE_64; + case 768: + return SEC_ENG_PKA_REG_SIZE_96; + case 1024: + return SEC_ENG_PKA_REG_SIZE_128; + case 1536: + return SEC_ENG_PKA_REG_SIZE_192; + case 2048: + return SEC_ENG_PKA_REG_SIZE_256; + case 3072: + return SEC_ENG_PKA_REG_SIZE_384; + case 4096: + return SEC_ENG_PKA_REG_SIZE_512; + default: + return SEC_ENG_PKA_REG_SIZE_32; + } + return SEC_ENG_PKA_REG_SIZE_32; +} + +/* c code: +number = 1 +base = a +while b: + if b & 1: + number = number * base % c + b >>= 1 + base = base * base % c +return number +*/ +int sec_dsa_mexp_binary(uint32_t size,const uint32_t *a,const uint32_t *b,const uint32_t *c,uint32_t *r) +{ + uint32_t i,j,k; + uint32_t tmp; + uint32_t isOne=0; + uint8_t *p=(uint8_t *)b; + SEC_ENG_PKA_REG_SIZE_Type nregType=sec_dsa_get_reg_size(size); + SEC_ENG_PKA_REG_SIZE_Type lregType=sec_dsa_get_reg_size(size*2); + uint32_t dataSize=(size>>3)>>2; +#if 1 + uint8_t oneBuf[128] ALIGN4 ={0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01}; +#endif + /* 0:c + * 4:a + * 5:number + * 6&7:temp + */ + + /* base = a */ + Sec_Eng_PKA_Write_Data(nregType,4,(uint32_t *)a,dataSize,0); + + /* number = 1 */ + Sec_Eng_PKA_Write_Data(nregType,5,(uint32_t *)oneBuf,sizeof(oneBuf)/4,0); + //Sec_Eng_PKA_Write_Immediate(nregType,5,0x01,1); +#ifdef DSA_DBG + Sec_Eng_PKA_Read_Data(nregType,5,(uint32_t *)pka_tmp,dataSize); + MSG("number:\r\n"); + bflb_platform_dump(pka_tmp,dataSize*4); +#endif + + Sec_Eng_PKA_Write_Data(nregType,0,(uint32_t *)c,dataSize,0); + + Sec_Eng_PKA_CREG(nregType,6,dataSize,1); + Sec_Eng_PKA_CREG(nregType,7,dataSize,1); +#ifdef DSA_DBG + Sec_Eng_PKA_Read_Data(nregType,4,(uint32_t *)pka_tmp,dataSize); + MSG("base:\r\n"); + bflb_platform_dump(pka_tmp,dataSize*4); +#endif + /* Remove zeros bytes*/ + k=0; + while(p[k]==0&&k<(size>>3)){ + k++; + } + i=(size>>3)-1; + for(;i>=k;i--){ + tmp=p[i]; + j=0; + for(j=0;j<8;j++){ + isOne=tmp&(1<>3)>>2; + + /* 0:c + * 1:NPrime_c + * 2:invR_c + * 4:a(mont domain) + * 5:b + * 6:a^b%c(mont domain) + * 7:a^b%c(gf domain) + * 10&11:2^size for GF2Mont*/ + Sec_Eng_PKA_Write_Data(nregType,0,(uint32_t *)c,dataSize,0); + Sec_Eng_PKA_Write_Data(nregType,1,(uint32_t *)primeN_c,dataSize,1); + Sec_Eng_PKA_Write_Data(nregType,2,(uint32_t *)invR_c,dataSize,1); + + /* change a into mont domain*/ + Sec_Eng_PKA_Write_Data(nregType,4,(uint32_t *)a,dataSize,0); + Sec_Eng_PKA_CREG(nregType,10,dataSize,1); + Sec_Eng_PKA_CREG(nregType,11,dataSize,1); + Sec_Eng_PKA_GF2Mont(nregType,4,nregType,4,size,lregType,5,nregType,0); +#ifdef DSA_DBG + Sec_Eng_PKA_Read_Data(nregType,4,(uint32_t *)pka_tmp,dataSize); + MSG("GF2Mont Result of a:\r\n"); + bflb_platform_dump(pka_tmp,dataSize/*dataSize*4*/); +#endif + + Sec_Eng_PKA_Write_Data(nregType,5,(uint32_t *)b,dataSize,0); + /* a^b%c*/ + Sec_Eng_PKA_MEXP(nregType,6,nregType,4,nregType,5,nregType,0,1); + + /* change result into gf domain*/ + Sec_Eng_PKA_CREG(nregType,10,dataSize,1); + Sec_Eng_PKA_CREG(nregType,11,dataSize,1); + /*index 2 is invertR*/ + Sec_Eng_PKA_Mont2GF(nregType,7, nregType,6, nregType, 2,lregType,5,nregType,0); + Sec_Eng_PKA_Read_Data(nregType,7,(uint32_t *)r,dataSize); +#ifdef DSA_DBG + MSG("r:\r\n"); + bflb_platform_dump(r,dataSize/*dataSize*4*/); +#endif + return 0; +} + +/** + * dP=d%(p-1) + * dQ=d%(q-1) + * qInv=qp^(1-1):qInv*q%p=1 + * invR_p*r%p=1(r is 1024/2048/256) + * invR_q*r%q=1(r is 1024/2048/256) + */ +int sec_dsa_decrypt_crt(uint32_t size,uint32_t *c,sec_dsa_crt_cfg_t* crtCfg,uint32_t *d,uint32_t *r) +{ + /* + * m1 = pow(c, dP, p) + * m2 = pow(c, dQ, q) + * h = (qInv * (m1 - m2)) % p + * m = m2 + h * q + * */ + SEC_ENG_PKA_REG_SIZE_Type nregType=sec_dsa_get_reg_size(size); + SEC_ENG_PKA_REG_SIZE_Type lregType=sec_dsa_get_reg_size(size*2); + uint32_t dataSize=(size>>3)>>2; +#if 0 + uint8_t m1[64]={0x11,0xdd,0x19,0x7e,0x69,0x1a,0x40,0x0a,0x28,0xfc,0x3b,0x31,0x47,0xa2,0x6c,0x14, + 0x4e,0xf6,0xb0,0xe6,0xcd,0x89,0x0b,0x4f,0x02,0xe4,0x86,0xe2,0xe5,0xbe,0xe1,0xaf, + 0x91,0xd1,0x7b,0x59,0x8d,0xdc,0xb3,0x57,0x18,0xcb,0x80,0x05,0x1c,0xb5,0xa4,0x07, + 0xde,0x31,0x94,0xa4,0x2f,0x45,0xc7,0x95,0x75,0x0f,0x91,0xf0,0x37,0x91,0x85,0xa5}; + uint8_t m2[64]={0x63,0x89,0xa3,0xbb,0x64,0x63,0x87,0x4f,0x38,0xbd,0x9e,0x0e,0x93,0x29,0x58,0xee, + 0xf8,0xe2,0x20,0x2d,0xe5,0x38,0x0a,0x7f,0x18,0x38,0x2f,0xa3,0xf5,0x48,0xf8,0xfd, + 0xe5,0x78,0x4a,0x10,0x62,0x01,0x09,0x29,0xe3,0xe3,0x9f,0xad,0x9b,0xbe,0x20,0xd2, + 0x68,0x90,0x57,0x97,0xfc,0x78,0xd5,0xdb,0x07,0x5b,0xfe,0x21,0x0a,0x2d,0x7f,0xc1}; +#else + uint32_t m1[32]; + uint32_t m2[32]; +#endif + /* + * 4:m1 + * 5:m2 + * 6:qInv + * 7:p + * 8:q + * 9:h + * 10&11:qInv*(m1-m2) + */ + sec_dsa_mexp_mont(size,c,crtCfg->dP,crtCfg->p,crtCfg->invR_p,crtCfg->primeN_p,m1); + sec_dsa_mexp_mont(size,c,crtCfg->dQ,crtCfg->q,crtCfg->invR_q,crtCfg->primeN_q,m2); + + Sec_Eng_PKA_Write_Data(nregType,4,(uint32_t *)m1,dataSize,0); + Sec_Eng_PKA_Write_Data(nregType,5,(uint32_t *)m2,dataSize,0); + Sec_Eng_PKA_Write_Data(nregType,6,(uint32_t *)crtCfg->qInv,dataSize,0); + Sec_Eng_PKA_Write_Data(nregType,7,(uint32_t *)crtCfg->p,dataSize,0); + Sec_Eng_PKA_Write_Data(nregType,8,(uint32_t *)crtCfg->q,dataSize,0); + + /*(m1 - m2)%p*/ + Sec_Eng_PKA_MSUB(nregType,4,nregType,4,nregType,5,nregType,7,1); +#ifdef DSA_DBG + Sec_Eng_PKA_Read_Data(nregType,4,(uint32_t *)pka_tmp,dataSize); + MSG("m1 - m2:\r\n"); + bflb_platform_dump(pka_tmp,dataSize/*dataSize*4*/); +#endif + /* (qInv * (m1 - m2)) % p*/ + Sec_Eng_PKA_CREG(nregType,10,dataSize,1); + Sec_Eng_PKA_CREG(nregType,11,dataSize,1); + Sec_Eng_PKA_LMUL(lregType,5,nregType,6,nregType,4,1); +#ifdef DSA_DBG + Sec_Eng_PKA_Read_Data(lregType,5,(uint32_t *)pka_tmp,dataSize*2); + MSG("qInv * (m1 - m2):\r\n"); + bflb_platform_dump(pka_tmp,dataSize/*dataSize*4*2*/); +#endif + Sec_Eng_PKA_MREM(nregType,9,lregType,5,nregType,7,1); +#ifdef DSA_DBG + Sec_Eng_PKA_Read_Data(nregType,9,(uint32_t *)pka_tmp,dataSize); + MSG("h:\r\n"); + bflb_platform_dump(pka_tmp,dataSize*4); +#endif + + /* h*q */ + Sec_Eng_PKA_CREG(nregType,10,dataSize,1); + Sec_Eng_PKA_CREG(nregType,11,dataSize,1); + Sec_Eng_PKA_LMUL(lregType,5,nregType,9,nregType,8,1); +#ifdef DSA_DBG + Sec_Eng_PKA_Read_Data(lregType,5,(uint32_t *)pka_tmp,dataSize*2); + MSG("h*q:\r\n"); + bflb_platform_dump(pka_tmp,dataSize/*dataSize*4*2*/); +#endif + /* m2 + h*q*/ + Sec_Eng_PKA_LADD(lregType,5,lregType,5,nregType,5,1); + + Sec_Eng_PKA_Read_Data(lregType,5,(uint32_t *)r,dataSize*2); +#ifdef DSA_DBG + MSG("r:\r\n"); + bflb_platform_dump(r,dataSize*4*2); +#endif + return 0; +} + +int sec_dsa_init(sec_dsa_handle_t * handle,uint32_t size) +{ + Sec_Eng_PKA_Reset(); + Sec_Eng_PKA_BigEndian_Enable(); + + memset(handle,0,sizeof(sec_dsa_handle_t)); + handle->size=size; + handle->crtSize=(size>>1); + + return 0; +} + +int sec_dsa_sign(sec_dsa_handle_t * handle,const uint32_t *hash,uint32_t hashLenInWord,uint32_t *s) +{ + uint32_t dsa_tmp[64]={0}; + + Sec_Eng_PKA_Reset(); + Sec_Eng_PKA_BigEndian_Enable(); + + memcpy(dsa_tmp+((handle->crtSize>>3)>>2)-hashLenInWord,hash,hashLenInWord*4); + + + if(0==sec_dsa_decrypt_crt(handle->crtSize,dsa_tmp,&handle->crtCfg,handle->d,s)){ + return 0; + }else{ + return -1; + } +} + +/** + */ +int sec_dsa_verify(sec_dsa_handle_t * handle,const uint32_t *hash,uint32_t hashLenInWord,const uint32_t *s) +{ + uint32_t dsa_tmp[64]; + uint8_t i=0; + uint8_t resultOffset=0; + + Sec_Eng_PKA_Reset(); + Sec_Eng_PKA_BigEndian_Enable(); + + if(0==sec_dsa_mexp_binary(handle->size,s,handle->e,handle->n,dsa_tmp)){ + resultOffset=(handle->size>>5)-hashLenInWord; + for(i=0;i cout = 1 + //cout = 1 if Y1 < Bar_1p1 + Sec_Eng_PKA_LCMP(res+1,3,3,3,19); + //cout=1 if Y1 > Bar_1m1 + Sec_Eng_PKA_LCMP(res+2,3,20,3,3); + //cout =1 if Z1 = 0 + Sec_Eng_PKA_LCMP(res+3,3,4,3,8); + *pka_p1_eq_inf = res[0]&res[1]&res[2]&res[3]; + + //cout = 1 if X2 = 0 + Sec_Eng_PKA_LCMP(res,3,5,3,8); + // cout = 1 if Y2 < Bar_1p1 + Sec_Eng_PKA_LCMP(res+1,3,6,3,19); + //cout = 1 if Y2 > Bar_1m1 + Sec_Eng_PKA_LCMP(res+2,3,20,3,6); + //cout = 1 if Z2 = 0 + Sec_Eng_PKA_LCMP(res+3,3,7,3,8); + *pka_p2_eq_inf = res[0]&res[1]&res[2]&res[3]; +} + +static void sec_ecdsa_copy_x2_to_x1(uint8_t id) +{ + //X2->X1 + Sec_Eng_PKA_Move_Data(3,2,3,5,0); + //Y2->Y1 + Sec_Eng_PKA_Move_Data(3,3,3,6,0); + //Z2->Z1 + Sec_Eng_PKA_Move_Data(3,4,3,7,1);//Caution!!! wait movdat ready to execute next command +} + +static void sec_ecdsa_point_add(uint8_t id) +{ + /* index 2:BAR_Zero_x + * index 3:BAR_Zero_y + * index 4:BAR_Zero_z + * index 5:BAR_G_x + * index 6:BAR_G_y + * index 7:BAR_G_z + * index 8:1 + * index 9:2 + * index 10:3 + * index 11:4 + * index 12:8 + * index 19:1P1 + * index 20:1m1*/ + + //U1 = Y2*Z1 + //PKA_MMUL(0,3,13,3, 6,3, 4,3,0);//d_reg_type,d_reg_idx,s0_reg_type,s0_reg_idx,s1_reg_type,s1_reg_idx,s2_reg_type,s2_reg_idx + Sec_Eng_PKA_MMUL(3,13,3,6,3,4,3,0,0); + + //U2 = Y1*Z2 + //PKA_MMUL(0,3,14,3, 3,3, 7,3,0); + Sec_Eng_PKA_MMUL(3,14,3,3,3,7,3,0,0); + + //V1 = X2*Z1 + //PKA_MMUL(0,3,15,3, 5,3, 4,3,0); + Sec_Eng_PKA_MMUL(3,15,3,5,3,4,3,0,0); + + //V2 = X1*Z2 + //PKA_MMUL(0,3,16,3, 2,3, 7,3,0); + Sec_Eng_PKA_MMUL(3,16,3,2,3,7,3,0,0); + + //U = U1-U2 + //PKA_MSUB(0,3,13,3,13,3,14,3,0); + Sec_Eng_PKA_MSUB(3,13,3,13,3,14,3,0,0); + + //V = V1-V2 + //PKA_MSUB(0,3,15,3,15,3,16,3,0); + Sec_Eng_PKA_MSUB(3,15,3,15,3,16,3,0,0); + + //W = Z1*Z2 + //PKA_MMUL(0,3, 2,3, 4,3, 7,3,0); + Sec_Eng_PKA_MMUL(3,2,3,4,3,7,3,0,0); + + //V^2 + //PKA_MMUL(0,3, 3,3,15,3,15,3,0); + Sec_Eng_PKA_MMUL(3,3,3,15,3,15,3,0,0); + + //V^3 + //PKA_MMUL(0,3, 4,3, 3,3,15,3,0); + Sec_Eng_PKA_MMUL(3,4,3,3,3,15,3,0,0); + + //U^2 + //PKA_MMUL(0,3,17,3,13,3,13,3,0); + Sec_Eng_PKA_MMUL(3,17,3,13,3,13,3,0,0); + + //U^2*W + //PKA_MMUL(0,3,17,3,17,3, 2,3,0); + Sec_Eng_PKA_MMUL(3,17,3,17,3,2,3,0,0); + + //U^2*W-V^3 + //PKA_MSUB(0,3,17,3,17,3, 4,3,0); + Sec_Eng_PKA_MSUB(3,17,3,17,3,4,3,0,0); + + //2*V^2 + //PKA_MMUL(0,3,18,3, 9,3, 3,3,0); + Sec_Eng_PKA_MMUL(3,18,3,9,3,3,3,0,0); + + //2*V^2*V2 + //PKA_MMUL(0,3,18,3,18,3,16,3,0); + Sec_Eng_PKA_MMUL(3,18,3,18,3,16,3,0,0); + + //A = U^2*W-V^3-2*V^2*V2 + //PKA_MSUB(0,3,18,3,17,3,18,3,0); + Sec_Eng_PKA_MSUB(3,18,3,17,3,18,3,0,0); + + //V^2*V2 + //PKA_MMUL(0,3, 3,3, 3,3,16,3,0); + Sec_Eng_PKA_MMUL(3,3,3,3,3,16,3,0,0); + + //V^3*U2 + //PKA_MMUL(0,3,14,3, 4,3,14,3,0); + Sec_Eng_PKA_MMUL(3,14,3,4,3,14,3,0,0); + + //Z3 = V^3*W + //PKA_MMUL(0,3, 4,3, 4,3, 2,3,0); + Sec_Eng_PKA_MMUL(3,4,3,4,3,2,3,0,0); + + //X3 = V*A + //PKA_MMUL(0,3, 2,3,15,3,18,3,0); + Sec_Eng_PKA_MMUL(3,2,3,15,3,18,3,0,0); + + //V^2*V2-A + //PKA_MSUB(0,3, 3,3, 3,3,18,3,0); + Sec_Eng_PKA_MSUB(3,3,3,3,3,18,3,0,0); + + //U*(V^2*V2-A) + //PKA_MMUL(0,3, 3,3,13,3, 3,3,0); + Sec_Eng_PKA_MMUL(3,3,3,13,3,3,3,0,0); + + //Y3 = U*(V^2*V2-A)-V^3*U2 + //PKA_MSUB(1,3, 3,3, 3,3,14,3,0); + Sec_Eng_PKA_MSUB(3,3,3,3,3,14,3,0,1); + +} + +static void sec_ecdsa_point_double(uint8_t id) +{ + /* index 2:BAR_Zero_x + * index 3:BAR_Zero_y + * index 4:BAR_Zero_z + * index 5:BAR_G_x + * index 6:BAR_G_y + * index 7:BAR_G_z + * index 8:1 + * index 9:2 + * index 10:3 + * index 11:4 + * index 12:8 + * index 19:1P1 + * index 20:1m1*/ + + //X1^2 + //PKA_MMUL(0,3,13,3, 5,3, 5,3,0);//d_reg_type,d_reg_idx,s0_reg_type,s0_reg_idx,s1_reg_type,s1_reg_idx,s2_reg_type,s2_reg_idx + Sec_Eng_PKA_MMUL(3,13,3,5,3,5,3,0,0); + + //Z1^2 + //PKA_MMUL(0,3,14,3, 7,3, 7,3,0); + Sec_Eng_PKA_MMUL(3,14,3,7,3,7,3,0,0); + + //X1^2-Z1^2 + //PKA_MSUB(0,3,13,3,13,3,14,3,0); + Sec_Eng_PKA_MSUB(3,13,3,13,3,14,3,0,0); + + //W = 3*(X1^2-Z1^2) + //PKA_MMUL(0,3,13,3,10,3,13,3,0); + Sec_Eng_PKA_MMUL(3,13,3,10,3,13,3,0,0); + + //S = Y1*Z1 + //PKA_MMUL(0,3,14,3, 6,3, 7,3,0); + Sec_Eng_PKA_MMUL(3,14,3,6,3,7,3,0,0); + + //X1*Y1 + //PKA_MMUL(0,3,15,3, 5,3, 6,3,0); + Sec_Eng_PKA_MMUL(3,15,3,5,3,6,3,0,0); + + //W^2 + //PKA_MMUL(0,3, 7,3,13,3,13,3,0); + Sec_Eng_PKA_MMUL(3,7,3,13,3,13,3,0,0); + + //B = X1*Y1*S + //PKA_MMUL(0,3,15,3,15,3,14,3,0); + Sec_Eng_PKA_MMUL(3,15,3,15,3,14,3,0,0); + + //8*B + //PKA_MMUL(0,3, 5,3,12,3,15,3,0); + Sec_Eng_PKA_MMUL(3,5,3,12,3,15,3,0,0); + + //H = W^2-8*B + //PKA_MSUB(0,3, 7,3, 7,3, 5,3,0); + Sec_Eng_PKA_MSUB(3,7,3,7,3,5,3,0,0); + + //2*H + //PKA_MMUL(0,3, 5,3, 9,3, 7,3,0); + Sec_Eng_PKA_MMUL(3, 5,3,9,3,7,3,0,0); + + //X2 = 2*H*S + //PKA_MMUL(0,3, 5,3, 5,3,14,3,0); + Sec_Eng_PKA_MMUL(3, 5,3,5,3,14,3,0,0); + + //4*B + //PKA_MMUL(0,3,15,3,11,3,15,3,0); + Sec_Eng_PKA_MMUL(3,15,3,11,3,15,3,0,0); + + //S^2 + //PKA_MMUL(0,3,16,3,14,3,14,3,0); + Sec_Eng_PKA_MMUL(3,16,3,14,3,14,3,0,0); + + //4*B-H + //PKA_MSUB(0,3,15,3,15,3, 7,3,0); + Sec_Eng_PKA_MSUB(3,15,3,15,3,7,3,0,0); + + //Y1^2 + //PKA_MMUL(0,3, 6,3, 6,3, 6,3,0); + Sec_Eng_PKA_MMUL(3,6,3,6,3,6,3,0,0); + + //W*(4*B-H) + //PKA_MMUL(0,3,15,3,15,3,13,3,0); + Sec_Eng_PKA_MMUL(3,15,3,15,3,13,3,0,0); + + //8*Y1^2 + //PKA_MMUL(0,3, 6,3,12,3, 6,3,0); + Sec_Eng_PKA_MMUL(3,6,3,12,3,6,3,0,0); + + //8*Y1^2*S^2 + //PKA_MMUL(0,3, 6,3, 6,3,16,3,0); + Sec_Eng_PKA_MMUL(3,6,3,6,3,16,3,0,0); + + //Y2 = W*(4*B-H)-8*Y1^2*S^2 + //PKA_MSUB(0,3, 6,3,15,3, 6,3,0); + Sec_Eng_PKA_MSUB(3,6,3,15,3,6,3,0,0); + + //S^3 + //PKA_MMUL(0,3, 7,3,14,3,16,3,0); + Sec_Eng_PKA_MMUL(3,7,3,14,3,16,3,0,0); + + //Z2 = 8*S^3 + //PKA_MMUL(1,3, 7,3,12,3, 7,3,0); + Sec_Eng_PKA_MMUL(3,7,3,12,3,7,3,0,1); + +} +#ifdef ECDSA_DBG_DETAIL +static void sec_ecdsa_dump_temp_result() +{ + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,2,(uint32_t *)pka_tmp,ECP_SECP256R1_SIZE/4); + MSG("2=\r\n"); + bflb_platform_dump(pka_tmp,ECP_SECP256R1_SIZE); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,3,(uint32_t *)pka_tmp,ECP_SECP256R1_SIZE/4); + MSG("3=\r\n"); + bflb_platform_dump(pka_tmp,ECP_SECP256R1_SIZE); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,4,(uint32_t *)pka_tmp,ECP_SECP256R1_SIZE/4); + MSG("4=\r\n"); + bflb_platform_dump(pka_tmp,ECP_SECP256R1_SIZE); + + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,5,(uint32_t *)pka_tmp,ECP_SECP256R1_SIZE/4); + MSG("5=\r\n"); + bflb_platform_dump(pka_tmp,ECP_SECP256R1_SIZE); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,6,(uint32_t *)pka_tmp,ECP_SECP256R1_SIZE/4); + MSG("6=\r\n"); + bflb_platform_dump(pka_tmp,ECP_SECP256R1_SIZE); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,7,(uint32_t *)pka_tmp,ECP_SECP256R1_SIZE/4); + MSG("7=\r\n"); + bflb_platform_dump(pka_tmp,ECP_SECP256R1_SIZE); +} +#endif +static int sec_ecdsa_verify_point_mul(uint8_t id,const uint32_t *m ) +{ + uint32_t i,j,k; + uint32_t tmp; + uint32_t isOne=0; + uint8_t *p=(uint8_t *)m; + uint8_t pka_p1_eq_inf,pka_p2_eq_inf; + + /* Remove zeros bytes*/ + k=0; + while(p[k]==0&&k<31){ + k++; + } + i=31; + for(;i>=k;i--){ + tmp=p[i]; + j=0; + for(j=0;j<8;j++){ + isOne=tmp&(1< j ) return( -1 ); + if( j > i ) return( 1 ); + + for( ; i b[i] ) return( 1 ); + if( a[i] < b[i] ) return( -1 ); + } + + return 0; +} + +int sec_ecdsa_init(sec_ecdsa_handle_t * handle,sec_ecp_type id) +{ + + Sec_Eng_PKA_Reset(); + Sec_Eng_PKA_BigEndian_Enable(); + Sec_Eng_Trng_Enable(); + + handle->ecpId=id; + + return 0; +} + +int sec_ecdsa_deinit(sec_ecdsa_handle_t * handle) +{ + Sec_Eng_PKA_Reset(); + + return 0; +} + +int sec_ecdsa_verify(sec_ecdsa_handle_t * handle,const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *r, const uint32_t *s) +{ + uint32_t bar_u1_x[8]; + uint32_t bar_u1_y[8]; + uint32_t bar_u1_z[8]; + uint32_t bar_u2_x[8]; + uint32_t bar_u2_y[8]; + uint32_t bar_u2_z[8]; + uint32_t pka_u1[8]={0}; + uint32_t pka_u2[8]={0}; + uint32_t i=0; + + /* Pointer check */ + if(hash==NULL || handle->publicKeyx==NULL || handle->publicKeyy==NULL || r==NULL ||s==NULL){ + return -1; + } + + + Sec_Eng_PKA_Reset(); + Sec_Eng_PKA_BigEndian_Enable(); + + /*Step 0: make sure r and s are in range 1..n-1*/ + + /* r and s should not be 0*/ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_S_REG_INDEX,(uint32_t *)r,ECP_SECP256R1_SIZE/4,0); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,8,(uint32_t *)secp256r1_1,ECP_SECP256R1_SIZE/4,0); + //cout = 1 if r = 0 + Sec_Eng_PKA_LCMP((uint8_t*)&i,ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_S_REG_INDEX,ECP_SECP256R1_REG_TYPE,8);//s0 < s1 => cout = 1 + if(i==1){ + return -1; + } + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_S_REG_INDEX,(uint32_t *)s,ECP_SECP256R1_SIZE/4,0); + //cout = 1 if r = 0 + Sec_Eng_PKA_LCMP((uint8_t*)&i,ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_S_REG_INDEX,ECP_SECP256R1_REG_TYPE,8);//s0 < s1 => cout = 1 + if(i==1){ + return -1; + } + + sec_ecc_basic_parameter_init(handle->ecpId); + + /* r and s should not be 0*/ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_S_REG_INDEX,(uint32_t *)r,ECP_SECP256R1_SIZE/4,0); + //cout = 1 if r < N + Sec_Eng_PKA_LCMP((uint8_t*)&i,ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_S_REG_INDEX,ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_N_REG_INDEX); + if(i!=1){ + return -1; + } + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_S_REG_INDEX,(uint32_t *)s,ECP_SECP256R1_SIZE/4,0); + //cout = 1 if r < N + Sec_Eng_PKA_LCMP((uint8_t*)&i,ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_S_REG_INDEX,ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_N_REG_INDEX); + if(i!=1){ + return -1; + } + + /* u1 = e / s mod n, u2 = r / s mod n + * R = u1 G + u2 Q*/ + + /* Step1: Get S^-1*/ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_S_REG_INDEX,(uint32_t *)s,ECP_SECP256R1_SIZE/4,0); + /* Change s to Mont domain */ + /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE,2*ECP_SECP256R1_LT_REG_INDEX-1,ECP_SECP256R1_SIZE/4,1); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE,2*ECP_SECP256R1_LT_REG_INDEX,ECP_SECP256R1_SIZE/4,1); + Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_S_REG_INDEX,ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_S_REG_INDEX,256, + ECP_SECP256R1_LT_REG_TYPE,ECP_SECP256R1_LT_REG_INDEX,ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_N_REG_INDEX); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_S_REG_INDEX,(uint32_t *)pka_tmp,ECP_SECP256R1_SIZE/4); + MSG("GF2Mont Result of s:\r\n"); + bflb_platform_dump(pka_tmp,ECP_SECP256R1_SIZE); +#endif + + /* Get S^-1 in Mont domain */ + Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_BAR_S_REG_INDEX,ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_S_REG_INDEX, + ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_N_REG_INDEX,1); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_BAR_S_REG_INDEX,(uint32_t *)pka_tmp,ECP_SECP256R1_SIZE/4); + MSG("s^-1 in Mont:\r\n"); + bflb_platform_dump(pka_tmp,ECP_SECP256R1_SIZE); +#endif + + /* Change S^-1 into GF domain,now ECP_SECP256R1_S_REG_INDEX store s^-1*/ + /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_BAR_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_INVR_N_REG_INDEX, + ECP_SECP256R1_LT_REG_TYPE,ECP_SECP256R1_LT_REG_INDEX,ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_N_REG_INDEX); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_S_REG_INDEX,(uint32_t *)pka_tmp,ECP_SECP256R1_SIZE/4); + MSG("S^-1:\r\n"); + bflb_platform_dump(pka_tmp,ECP_SECP256R1_SIZE); +#endif + + /* Step2: Get u1*/ + //u1=hash(e)*s^-1; + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_HASH_REG_INDEX,(uint32_t *)hash,ECP_SECP256R1_SIZE/4,0); + Sec_Eng_PKA_LMUL(ECP_SECP256R1_LT_REG_TYPE,ECP_SECP256R1_LT_REG_INDEX,ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_HASH_REG_INDEX, + ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_S_REG_INDEX,0); + Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_U1_REG_INDEX,ECP_SECP256R1_LT_REG_TYPE,ECP_SECP256R1_LT_REG_INDEX, + ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_N_REG_INDEX,1); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_U1_REG_INDEX,(uint32_t *)pka_u1,ECP_SECP256R1_SIZE/4); +#ifdef ECDSA_DBG + MSG("u1:\r\n"); + bflb_platform_dump(pka_u1,ECP_SECP256R1_SIZE); +#endif + + /* Step3: Get u2*/ + //u2=r*s^-1; + // use hash and u1 temp register + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_HASH_REG_INDEX,(uint32_t *)r,ECP_SECP256R1_SIZE/4,0); + Sec_Eng_PKA_LMUL(ECP_SECP256R1_LT_REG_TYPE,ECP_SECP256R1_LT_REG_INDEX,ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_HASH_REG_INDEX, + ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_S_REG_INDEX,0); + Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_U1_REG_INDEX,ECP_SECP256R1_LT_REG_TYPE,ECP_SECP256R1_LT_REG_INDEX, + ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_N_REG_INDEX,1); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_U1_REG_INDEX,(uint32_t *)pka_u2,ECP_SECP256R1_SIZE/4); +#ifdef ECDSA_DBG + MSG("u2:\r\n"); + bflb_platform_dump(pka_u2,ECP_SECP256R1_SIZE); +#endif + + /* Step4: Get u1*G*/ + + //Clear D[7] + //PKA_CREG(1,4, 7,0); + Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE,7,ECP_SECP256R1_SIZE/4,1); + + sec_ecc_point_mul_init(handle->ecpId); + + //X1 + //PKA_CTREG(3, 2,8,bar_Zero_x); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,2,(uint32_t *)secp256r1_Zerox,ECP_SECP256R1_SIZE/4,0); + //Y1 + //PKA_CTREG(3, 3,8,bar_Zero_y); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,3,(uint32_t *)secp256r1_Zeroy,ECP_SECP256R1_SIZE/4,0); + //Z1 + //PKA_CTREG(3, 4,8,bar_Zero_z); + //PKA_MOVDAT(1,3, 4,3, 2); + Sec_Eng_PKA_Move_Data(3,4,3,2,1); + + //X2 + //PKA_CTREG(3, 5,8,bar_G_x); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,5,(uint32_t *)secp256r1_Gx,ECP_SECP256R1_SIZE/4,0); + //Y2 + //PKA_CTREG(3, 6,8,bar_G_y); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,6,(uint32_t *)secp256r1_Gy,ECP_SECP256R1_SIZE/4,0); + //Z2 + //PKA_CTREG(3, 7,8,bar_G_z); + //PKA_MOVDAT(1,3, 7,3, 3); + Sec_Eng_PKA_Move_Data(3,7,3,3,1); + + sec_ecdsa_verify_point_mul(handle->ecpId,pka_u1); + //get bar_u1_x + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,2,(uint32_t *)bar_u1_x,ECP_SECP256R1_SIZE/4); +#ifdef ECDSA_DBG + MSG("bar_u1_x\r\n"); + bflb_platform_dump(bar_u1_x,ECP_SECP256R1_SIZE); +#endif + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,3,(uint32_t *)bar_u1_y,ECP_SECP256R1_SIZE/4); +#ifdef ECDSA_DBG + MSG("bar_u1_y\r\n"); + bflb_platform_dump(bar_u1_y,ECP_SECP256R1_SIZE); +#endif + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,4,(uint32_t *)bar_u1_z,ECP_SECP256R1_SIZE/4); +#ifdef ECDSA_DBG + MSG("bar_u1_z\r\n"); + bflb_platform_dump(bar_u1_z,ECP_SECP256R1_SIZE); +#endif + + /* Step4: Get u2*Q*/ + //X1 + //PKA_CTREG(3, 2,8,bar_Zero_x); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,2,(uint32_t *)secp256r1_Zerox,ECP_SECP256R1_SIZE/4,0); + //Y1 + //PKA_CTREG(3, 3,8,bar_Zero_y); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,3,(uint32_t *)secp256r1_Zeroy,ECP_SECP256R1_SIZE/4,0); + //Z1 + //PKA_CTREG(3, 4,8,bar_Zero_z); + //PKA_MOVDAT(1,3, 4,3, 2); + Sec_Eng_PKA_Move_Data(3,4,3,2,1); + + //PUB_x + //PKA_CTREG(3, 5,8,PUB_x); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,5,(uint32_t *)handle->publicKeyx,ECP_SECP256R1_SIZE/4,0); + //bar_pub_x + //PKA_GF2MONT(3, 5,3, 5); + /* Change s to Mont domain,remember to clear temp register and index 0 is P256*/ + /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE,2*ECP_SECP256R1_LT_REG_INDEX-1,ECP_SECP256R1_SIZE/4,1); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE,2*ECP_SECP256R1_LT_REG_INDEX,ECP_SECP256R1_SIZE/4,1); + Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE,5,ECP_SECP256R1_REG_TYPE,5,256, + ECP_SECP256R1_LT_REG_TYPE,ECP_SECP256R1_LT_REG_INDEX,ECP_SECP256R1_REG_TYPE,0); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,5,(uint32_t *)pka_tmp,ECP_SECP256R1_SIZE/4); + MSG("PK.x in Mont:\r\n"); + bflb_platform_dump(pka_tmp,ECP_SECP256R1_SIZE); +#endif + + //PUB_y + //PKA_CTREG(3, 6,8,PUB_y); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,6,(uint32_t *)handle->publicKeyy,ECP_SECP256R1_SIZE/4,0); + //bar_pub_y + //PKA_GF2MONT(3, 6,3, 6); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE,2*ECP_SECP256R1_LT_REG_INDEX-1,ECP_SECP256R1_SIZE/4,1); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE,2*ECP_SECP256R1_LT_REG_INDEX,ECP_SECP256R1_SIZE/4,1); + Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE,6,ECP_SECP256R1_REG_TYPE,6,256, + ECP_SECP256R1_LT_REG_TYPE,ECP_SECP256R1_LT_REG_INDEX,ECP_SECP256R1_REG_TYPE,0); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,6,(uint32_t *)pka_tmp,ECP_SECP256R1_SIZE/4); + MSG("PK.y in Mont:\r\n"); + bflb_platform_dump(pka_tmp,ECP_SECP256R1_SIZE); +#endif + + //bar_pub_z + //PKA_CTREG(3, 7,8,PUB_z); + //PKA_MOVDAT(1,3, 7,3, 3); + Sec_Eng_PKA_Move_Data(3,7,3,3,1); + + /* Clear temp register since it's used in point-mul*/ + Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE,7,ECP_SECP256R1_SIZE/4,1); + + sec_ecdsa_verify_point_mul(handle->ecpId,pka_u2); + //get bar_u1_x + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,2,(uint32_t *)bar_u2_x,ECP_SECP256R1_SIZE/4); +#ifdef ECDSA_DBG + MSG("bar_u2_x\r\n"); + bflb_platform_dump(bar_u2_x,ECP_SECP256R1_SIZE); +#endif + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,3,(uint32_t *)bar_u2_y,ECP_SECP256R1_SIZE/4); +#ifdef ECDSA_DBG + MSG("bar_u2_y\r\n"); + bflb_platform_dump(bar_u2_y,ECP_SECP256R1_SIZE); +#endif + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,4,(uint32_t *)bar_u2_z,ECP_SECP256R1_SIZE/4); +#ifdef ECDSA_DBG + MSG("bar_u2_z\r\n"); + bflb_platform_dump(bar_u2_z,ECP_SECP256R1_SIZE); +#endif + + /* Step5: Get u1*G+u2*Q*/ + //move bar_u2_x + //PKA_MOVDAT(0,3, 5,3, 2); + Sec_Eng_PKA_Move_Data(3,5,3,2,0); + //move bar_u2_y + //PKA_MOVDAT(0,3, 6,3, 3); + Sec_Eng_PKA_Move_Data(3,6,3,3,0); + //move bar_u2_z + //PKA_MOVDAT(1,3, 7,3, 4); + Sec_Eng_PKA_Move_Data(3,7,3,4,1); + + //bar_u1_x + //PKA_CTREG(3, 2,8,bar_u1_x); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,2,(uint32_t *)bar_u1_x,ECP_SECP256R1_SIZE/4,0); + //bar_u1_y + //PKA_CTREG(3, 3,8,bar_u1_y); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,3,(uint32_t *)bar_u1_y,ECP_SECP256R1_SIZE/4,0); + //bar_u1_z + //PKA_CTREG(3, 4,8,bar_u1_z); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,4,(uint32_t *)bar_u1_z,ECP_SECP256R1_SIZE/4,0); + + //R = u1 * G + u2 * PUB + //PKA_POINT_ADDITION(); + sec_ecdsa_point_add(handle->ecpId); + + /* Step6 Get R.x(R=u1G+u2P)*/ + //R.z ^ -1 + //PKA_MINV(0,3, 5,3, 4,3, 0); + Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE,5,ECP_SECP256R1_REG_TYPE,4,ECP_SECP256R1_REG_TYPE,0,1); + //inv_r + //PKA_CTREG(3, 6,8,inv_r); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,6,(uint32_t *)secp256r1InvR_P,ECP_SECP256R1_SIZE/4,0); + //R.z ^ -1 + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE,2*ECP_SECP256R1_LT_REG_INDEX-1,ECP_SECP256R1_SIZE/4,1); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE,2*ECP_SECP256R1_LT_REG_INDEX,ECP_SECP256R1_SIZE/4,1); + //PKA_MONT2GF(3, 5,3, 5,3, 6); + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE,5, ECP_SECP256R1_REG_TYPE,5, ECP_SECP256R1_REG_TYPE, 6, + ECP_SECP256R1_LT_REG_TYPE,ECP_SECP256R1_LT_REG_INDEX,ECP_SECP256R1_REG_TYPE,0); + + //R.x (Montgomery to GF) + //PKA_MONT2GF(3, 6,3, 2,3, 6); + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE,6, ECP_SECP256R1_REG_TYPE,2, ECP_SECP256R1_REG_TYPE, 6, + ECP_SECP256R1_LT_REG_TYPE,ECP_SECP256R1_LT_REG_INDEX,ECP_SECP256R1_REG_TYPE,0); + + //R.x (GF to Affine domain) + //PKA_MONT2GF(3, 2,3, 5,3, 6); + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE,2, ECP_SECP256R1_REG_TYPE,5, ECP_SECP256R1_REG_TYPE, 6, + ECP_SECP256R1_LT_REG_TYPE,ECP_SECP256R1_LT_REG_INDEX,ECP_SECP256R1_REG_TYPE,0); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,2,(uint32_t *)bar_u2_x,ECP_SECP256R1_SIZE/4); +#ifdef ECDSA_DBG + MSG("R.x=\r\n"); + bflb_platform_dump(bar_u2_x,ECP_SECP256R1_SIZE); +#endif + + /* Step7 check R.x=r*/ + /* Check Result */ + for(i=0;i<8;i++){ + if(bar_u2_x[i]!=r[i]){ + return -1; + } + } +#ifdef ECDSA_DBG + MSG("Verify success\r\n"); +#endif + return 0; +} + +int sec_ecdsa_sign(sec_ecdsa_handle_t * handle,const uint32_t *random_k,const uint32_t *hash,uint32_t hashLenInWord,uint32_t *r,uint32_t *s) +{ + uint32_t k[8]; + uint32_t Rx[8]; + uint32_t Ry[8]; + uint32_t KInvert[8]; + uint32_t maxTry1=100; + + /* Pointer check */ + if(handle->privateKey==NULL||hash==NULL||r==NULL||s==NULL){ + return -1; + } + + Sec_Eng_PKA_Reset(); + Sec_Eng_PKA_BigEndian_Enable(); + Sec_Eng_Trng_Enable(); + + while(maxTry1--){ + /* step 1 ,get random k*/ + if(random_k==NULL){ + if(sec_ecc_get_random_value(k,(uint32_t *)secp256r1N,32)<0){ + return -1; + } + }else{ + memcpy(k,random_k,32); + } +#ifdef ECDSA_DBG + MSG("Random k:\r\n"); + bflb_platform_dump(k,ECP_SECP256R1_SIZE); +#endif + /*step 2, calc R=kG*/ + if(sec_ecdsa_get_public_key(handle,k,Rx,Ry)<0){ + return -1; + } + if(sec_ecc_is_zero((uint8_t *)Rx,32)){ + continue; + } + memcpy(r,Rx,32); +#ifdef ECDSA_DBG + MSG("r:\r\n"); + bflb_platform_dump(r,ECP_SECP256R1_SIZE); +#endif + sec_ecc_basic_parameter_init(handle->ecpId); + /* step 3,get k^-1*/ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,5,(uint32_t *)k,ECP_SECP256R1_SIZE/4,0); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_N_REG_INDEX,(uint32_t *)secp256r1N,ECP_SECP256R1_SIZE/4,0); + /* Change k to Mont domain */ + /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE,2*ECP_SECP256R1_LT_REG_INDEX-1,ECP_SECP256R1_SIZE/4,1); + Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE,2*ECP_SECP256R1_LT_REG_INDEX,ECP_SECP256R1_SIZE/4,1); + Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE,5,ECP_SECP256R1_REG_TYPE,5,256, + ECP_SECP256R1_LT_REG_TYPE,ECP_SECP256R1_LT_REG_INDEX,ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_N_REG_INDEX); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,5,(uint32_t *)pka_tmp,ECP_SECP256R1_SIZE/4); + MSG("GF2Mont Result of k:\r\n"); + bflb_platform_dump(pka_tmp,ECP_SECP256R1_SIZE); +#endif + + /* Get k^-1 in Mont domain */ + Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE,6,ECP_SECP256R1_REG_TYPE,5, + ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_N_REG_INDEX,1); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,6,(uint32_t *)KInvert,ECP_SECP256R1_SIZE/4); + MSG("k^-1 in Mont:\r\n"); + bflb_platform_dump(KInvert,ECP_SECP256R1_SIZE); +#endif + + /* Change k^-1 into GF domain,now ECP_SECP256R1_S_REG_INDEX store k^-1*/ + /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ + Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE,5, ECP_SECP256R1_REG_TYPE,6, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_INVR_N_REG_INDEX, + ECP_SECP256R1_LT_REG_TYPE,ECP_SECP256R1_LT_REG_INDEX,ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_N_REG_INDEX); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,5,(uint32_t *)KInvert,ECP_SECP256R1_SIZE/4); +#ifdef ECDSA_DBG + MSG("k^-1:\r\n"); + bflb_platform_dump(KInvert,ECP_SECP256R1_SIZE); +#endif + + /* Step 4,r*d ((e + r * d) / k) */ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,4,(uint32_t *)handle->privateKey,ECP_SECP256R1_SIZE/4,0); + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,5,(uint32_t *)r,ECP_SECP256R1_SIZE/4,0); + Sec_Eng_PKA_LMUL(ECP_SECP256R1_SLT_REG_TYPE,ECP_SECP256R1_SLT_REG_INDEX,ECP_SECP256R1_REG_TYPE,4, + ECP_SECP256R1_REG_TYPE,5,1); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_SLT_REG_TYPE,ECP_SECP256R1_SLT_REG_INDEX,(uint32_t *)pka_tmp,ECP_SECP256R1_SIZE/2); + MSG("r*d:\r\n"); + bflb_platform_dump(pka_tmp,ECP_SECP256R1_SIZE*2); +#endif + + /* Step 5,e+r*d ((e + r * d) / k) */ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,5,(uint32_t *)hash,ECP_SECP256R1_SIZE/4,0); + Sec_Eng_PKA_LADD(ECP_SECP256R1_SLT_REG_TYPE,ECP_SECP256R1_SLT_REG_INDEX,ECP_SECP256R1_SLT_REG_TYPE,ECP_SECP256R1_SLT_REG_INDEX, + ECP_SECP256R1_REG_TYPE,5,1); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_SLT_REG_TYPE,ECP_SECP256R1_SLT_REG_INDEX,(uint32_t *)pka_tmp,ECP_SECP256R1_SIZE/2); + MSG("e+r*d:\r\n"); + bflb_platform_dump(pka_tmp,ECP_SECP256R1_SIZE*2); +#endif + + /* Step 6,(e+r*d)*k^-1 ((e + r * d) / k) */ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,5,(uint32_t *)KInvert,ECP_SECP256R1_SIZE/4,0); + Sec_Eng_PKA_LMUL(ECP_SECP256R1_SLT_REG_TYPE,ECP_SECP256R1_SLT_REG_INDEX,ECP_SECP256R1_SLT_REG_TYPE,ECP_SECP256R1_SLT_REG_INDEX, + ECP_SECP256R1_REG_TYPE,5,1); +#ifdef ECDSA_DBG + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_SLT_REG_TYPE,ECP_SECP256R1_SLT_REG_INDEX,(uint32_t *)pka_tmp,ECP_SECP256R1_SIZE/2); + MSG("(e+r*d)*k^-1:\r\n"); + bflb_platform_dump(pka_tmp,ECP_SECP256R1_SIZE*2); +#endif + /*N write only this time,add following operation will not change this register*/ + Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_N_REG_INDEX,(uint32_t *)secp256r1N,ECP_SECP256R1_SIZE/4,0); + Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE,4,ECP_SECP256R1_SLT_REG_TYPE,ECP_SECP256R1_SLT_REG_INDEX, + ECP_SECP256R1_REG_TYPE,ECP_SECP256R1_N_REG_INDEX,1); + Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE,4,(uint32_t *)s,ECP_SECP256R1_SIZE/4); +#ifdef ECDSA_DBG + MSG("s:\r\n"); + bflb_platform_dump(s,ECP_SECP256R1_SIZE); +#endif + /* Check s zero*/ + if(sec_ecc_is_zero((uint8_t *)s,32)){ + continue; + } + return 0; + } + return -1; +} + +int sec_ecdsa_get_private_key(sec_ecdsa_handle_t * handle,uint32_t *private_key) +{ + if(sec_ecc_get_random_value(private_key,(uint32_t *)secp256r1N,32)<0){ + return -1; + } + return 0; +} + +int sec_ecdsa_get_public_key(sec_ecdsa_handle_t * handle,const uint32_t *private_key,const uint32_t *pRx,const uint32_t *pRy) +{ + return sec_ecdh_get_scalar_point(handle->ecpId,NULL,NULL,private_key,pRx,pRy); +} + +int sec_ecc_get_random_value(uint32_t *randomData,uint32_t *maxRef,uint32_t size) +{ + uint32_t maxTry=100; + int32_t ret=0; + + while(maxTry--){ + ret=Sec_Eng_Trng_Get_Random((uint8_t *)randomData,size); + if(ret<0){ + return -1; + } + if(maxRef!=NULL){ + if(sec_ecc_cmp((uint8_t *)maxRef,(uint8_t *)randomData,size)>0){ + return 0; + } + }else{ + return 0; + } + } + return -1; +} + +int sec_ecdh_init(sec_ecdh_handle_t * handle,sec_ecp_type id) +{ + Sec_Eng_PKA_Reset(); + Sec_Eng_PKA_BigEndian_Enable(); + Sec_Eng_Trng_Enable(); + + handle->ecpId=id; + + return 0; +} + +int sec_ecdh_deinit(sec_ecdh_handle_t * handle) +{ + Sec_Eng_PKA_Reset(); + + return 0; +} + +int sec_ecdh_get_encrypt_key(sec_ecdh_handle_t * handle,const uint32_t *pkX,const uint32_t *pkY,const uint32_t *private_key,const uint32_t *pRx,const uint32_t *pRy) +{ + return sec_ecdh_get_scalar_point(handle->ecpId,pkX,pkY,private_key,pRx,pRy); +} + +int sec_ecdh_get_public_key(sec_ecdh_handle_t * handle,const uint32_t *private_key,const uint32_t *pRx,const uint32_t *pRy) +{ + return sec_ecdh_get_scalar_point(handle->ecpId,NULL,NULL,private_key,pRx,pRy); +} + diff --git a/drivers/bl702_driver/hal_drv/src/hal_sec_hash.c b/drivers/bl702_driver/hal_drv/src/hal_sec_hash.c new file mode 100644 index 00000000..05f35919 --- /dev/null +++ b/drivers/bl702_driver/hal_drv/src/hal_sec_hash.c @@ -0,0 +1,243 @@ +/** + * @file hal_sec_hash.c + * @brief + * + * Copyright 2019-2030 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "hal_sec_hash.h" +#include "bl702_sec_eng.h" + +void SEC_SHA_IRQHandler(void); + +static sec_hash_device_t sec_hashx_device[SEC_HASH_MAX_INDEX] = +{ + 0 +}; +static SEC_Eng_SHA256_Ctx shaCtx; +/** + * @brief + * + * @param dev + * @param oflag + * @return int + */ +int sec_hash_open(struct device *dev, uint16_t oflag) +{ + sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev; + int ret=0; + + switch(sec_hash_device->type) + { + case SEC_HASH_SHA1 : + ret=-1; + break; + case SEC_HASH_SHA224: + Sec_Eng_SHA256_Init(&shaCtx,SEC_ENG_SHA_ID0,SEC_ENG_SHA224,sec_hash_device->shaBuf,sec_hash_device->shaPadding); + Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0); + break; + case SEC_HASH_SHA256 : + Sec_Eng_SHA256_Init(&shaCtx,SEC_ENG_SHA_ID0,SEC_ENG_SHA256,sec_hash_device->shaBuf,sec_hash_device->shaPadding); + Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0); + break; + case SEC_HASH_SHA384: + case SEC_HASH_SHA512: + ret=-1; + break; + default: + ret=-1; + break; + } + return ret; +} +/** + * @brief + * + * @param dev + * @return int + */ +int sec_hash_close(struct device *dev) +{ + sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev; + memset(sec_hash_device,0,sizeof(sec_hash_device_t)); + + return 0; +} +/** + * @brief + * + * @param dev + * @param cmd + * @param args + * @return int + */ +int sec_hash_control(struct device *dev, int cmd, void *args) +{ + + return 0; +} + +/** + * @brief + * + * @param dev + * @param pos + * @param buffer + * @param size + * @return int + */ +int sec_hash_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) +{ + sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev; + int ret = 0; + + switch(sec_hash_device->type) + { + case SEC_HASH_SHA1 : + ret=-1; + break; + case SEC_HASH_SHA224: + Sec_Eng_SHA256_Update(&shaCtx,SEC_ENG_SHA_ID0,(uint8_t*)buffer, size); + break; + case SEC_HASH_SHA256 : + Sec_Eng_SHA256_Update(&shaCtx,SEC_ENG_SHA_ID0,(uint8_t*)buffer, size); + break; + case SEC_HASH_SHA384: + case SEC_HASH_SHA512: + ret=-1; + break; + default: + ret=-1; + break; + } + return ret; +} + +/** + * @brief + * + * @param dev + * @param pos + * @param buffer + * @param size + * @return int + */ +int sec_hash_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) +{ + sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev; + int ret = 0; + + switch(sec_hash_device->type) + { + case SEC_HASH_SHA1 : + ret=-1; + break; + case SEC_HASH_SHA224: + Sec_Eng_SHA256_Finish(&shaCtx,SEC_ENG_SHA_ID0,(uint8_t *)buffer); + ret=28; + break; + case SEC_HASH_SHA256 : + Sec_Eng_SHA256_Finish(&shaCtx,SEC_ENG_SHA_ID0,(uint8_t *)buffer); + ret=32; + break; + case SEC_HASH_SHA384: + case SEC_HASH_SHA512: + ret=-1; + break; + default: + ret=-1; + break; + } + return ret; +} + +/** + * @brief + * + * @param index + * @param type + * @param name + * @param flag + * @return int + */ +static int sec_hash_sha_register(enum sec_hash_index_type index, enum sec_hash_type type,const char *name, uint16_t flag) +{ + struct device *dev; + + if(SEC_HASH_MAX_INDEX == 0) + return -DEVICE_EINVAL; + + dev = &(sec_hashx_device[index].parent); + sec_hashx_device[index].type=type; + + dev->open = sec_hash_open; + dev->close = sec_hash_close; + dev->control = sec_hash_control; + dev->write = sec_hash_write; + dev->read = sec_hash_read; + + dev->status = DEVICE_UNREGISTER; + dev->type = DEVICE_CLASS_SEC_HASH; + dev->handle = NULL; + + return device_register(dev, name, flag); +} + +/** + * @brief + * + * @param index + * @param name + * @param flag + * @return int + */ +int sec_hash_sha256_register(enum sec_hash_index_type index, const char *name, uint16_t flag) +{ + return sec_hash_sha_register(index,SEC_HASH_SHA256, name, flag); +} + +/** + * @brief + * + * @param index + * @param name + * @param flag + * @return int + */ +int sec_hash_sha224_register(enum sec_hash_index_type index, const char *name, uint16_t flag) +{ + return sec_hash_sha_register(index,SEC_HASH_SHA224, name, flag); +} + +/** + * @brief + * + * @param handle + */ +void sec_hash_isr(sec_hash_device_t *handle) +{ +} + +/** + * @brief + * + */ +void SEC_SHA_IRQ(void) +{ + sec_hash_isr(&sec_hashx_device[0]); +} \ No newline at end of file diff --git a/drivers/bl702_driver/hal_drv/src/hal_spi.c b/drivers/bl702_driver/hal_drv/src/hal_spi.c index 6247a260..1fd60365 100644 --- a/drivers/bl702_driver/hal_drv/src/hal_spi.c +++ b/drivers/bl702_driver/hal_drv/src/hal_spi.c @@ -28,10 +28,10 @@ #include "spi_config.h" #ifdef BSP_USING_SPI0 -void SPI0_IRQ(void); +static void SPI0_IRQ(void); #endif -spi_device_t spix_device[SPI_MAX_INDEX] = +static spi_device_t spix_device[SPI_MAX_INDEX] = { #ifdef BSP_USING_SPI0 SPI0_CONFIG, @@ -47,8 +47,8 @@ spi_device_t spix_device[SPI_MAX_INDEX] = int spi_open(struct device *dev, uint16_t oflag) { spi_device_t *spi_device = (spi_device_t *)dev; - SPI_CFG_Type spiCfg; - SPI_FifoCfg_Type fifoCfg; + SPI_CFG_Type spiCfg = {0}; + SPI_FifoCfg_Type fifoCfg = {0}; #if SPI_SWAP_ENABLE GLB_Swap_SPI_0_MOSI_With_MISO(ENABLE); #endif diff --git a/drivers/bl702_driver/hal_drv/src/hal_timer.c b/drivers/bl702_driver/hal_drv/src/hal_timer.c index 814434ff..30d14d5b 100644 --- a/drivers/bl702_driver/hal_drv/src/hal_timer.c +++ b/drivers/bl702_driver/hal_drv/src/hal_timer.c @@ -31,7 +31,7 @@ void TIMER_CH0_IRQ(void); void TIMER_CH1_IRQ(void); -timer_device_t timerx_device[TIMER_MAX_INDEX] = +static timer_device_t timerx_device[TIMER_MAX_INDEX] = { #ifdef BSP_USING_TIMER_CH0 TIMER_CH0_CONFIG, @@ -51,7 +51,7 @@ timer_device_t timerx_device[TIMER_MAX_INDEX] = int timer_open(struct device *dev, uint16_t oflag) { timer_device_t *timer_device = (timer_device_t *)dev; - TIMER_CFG_Type timer_cfg; + TIMER_CFG_Type timer_cfg = {0}; timer_cfg.timerCh = timer_device->ch; timer_cfg.clkSrc = TIMER_CLK_SRC; @@ -77,12 +77,14 @@ int timer_open(struct device *dev, uint16_t oflag) TIMER_ClearIntStatus(timer_device->ch,TIMER_COMP_ID_2); #ifdef BSP_USING_TIMER_CH0 - if( timer_device->ch == TIMER_CH0) - Interrupt_Handler_Register(TIMER_CH0_IRQn, TIMER_CH0_IRQ); + if(oflag == DEVICE_OFLAG_INT) + if( timer_device->ch == TIMER_CH0) + Interrupt_Handler_Register(TIMER_CH0_IRQn, TIMER_CH0_IRQ); #endif #ifdef BSP_USING_TIMER_CH1 - if( timer_device->ch == TIMER_CH1) - Interrupt_Handler_Register(TIMER_CH1_IRQn, TIMER_CH1_IRQ); + if(oflag == DEVICE_OFLAG_INT) + if( timer_device->ch == TIMER_CH1) + Interrupt_Handler_Register(TIMER_CH1_IRQn, TIMER_CH1_IRQ); #endif return 0; @@ -116,15 +118,6 @@ int timer_control(struct device *dev, int cmd, void *args) { case DEVICE_CTRL_SET_INT /* constant-expression */: { - uint32_t offset = __builtin_ctz((uint32_t)args); - while((0 <= offset) && (offset < 4)) - { - if((uint32_t)args & (1 << offset)) - { - TIMER_IntMask(timer_device->ch, offset, UNMASK); - } - offset ++; - } if(timer_device->ch == TIMER_CH0) { NVIC_ClearPendingIRQ(TIMER_CH0_IRQn); @@ -135,20 +128,13 @@ int timer_control(struct device *dev, int cmd, void *args) NVIC_ClearPendingIRQ(TIMER_CH1_IRQn); NVIC_EnableIRQ(TIMER_CH1_IRQn); } - break; } case DEVICE_CTRL_CLR_INT /* constant-expression */: { - uint32_t offset = __builtin_ctz((uint32_t)args); - while((0 <= offset) && (offset < 4)) - { - if ((uint32_t)args & (1 << offset)) - { - TIMER_IntMask(timer_device->ch, offset, MASK); - } - offset ++; - } + timer_user_cfg_t *timer_user_cfg = ((timer_user_cfg_t *)(args)); + uint32_t offset = __builtin_ctz((uint32_t)timer_user_cfg->comp_it); + if(timer_device->ch == TIMER_CH0) { NVIC_DisableIRQ(TIMER_CH0_IRQn); @@ -157,7 +143,15 @@ int timer_control(struct device *dev, int cmd, void *args) { NVIC_DisableIRQ(TIMER_CH1_IRQn); } - + while((0 <= offset) && (offset < 4)) + { + if ((uint32_t)timer_user_cfg->comp_it & (1 << offset)) + { + TIMER_SetCompValue(timer_device->ch,offset,TIMER_MAX_VALUE); + TIMER_IntMask(timer_device->ch, offset, MASK); + } + offset ++; + } break; } case DEVICE_CTRL_GET_INT /* constant-expression */: @@ -168,24 +162,26 @@ int timer_control(struct device *dev, int cmd, void *args) break; case DEVICE_CTRL_RESUME /* constant-expression */: { - uint32_t offset = __builtin_ctz((uint32_t)args); - timer_user_cfg_t *timer_user_cfg = ((timer_user_cfg_t *)(timer_device->parent.handle)); - uint32_t timeout = (timer_user_cfg->timeout_val * 144 * 1000); + /* Enable timer */ + TIMER_Enable(timer_device->ch); + break; + } + case DEVICE_CTRL_SUSPEND /* constant-expression */: + { + TIMER_Disable(timer_device->ch); + break; + } + case DEVICE_CTRL_TIMER_CH_START: + { + timer_user_cfg_t *timer_user_cfg = ((timer_user_cfg_t *)(args)); + + uint32_t offset = __builtin_ctz((uint32_t)timer_user_cfg->comp_it); + uint32_t timeout = (timer_user_cfg->timeout_val * 144); TIMER_SetPreloadValue(timer_device->ch, 0); - if(timer_device->ch == TIMER_CH0) - { - NVIC_ClearPendingIRQ(TIMER_CH0_IRQn); - NVIC_EnableIRQ(TIMER_CH0_IRQn); - } - else if(timer_device->ch == TIMER_CH1) - { - NVIC_ClearPendingIRQ(TIMER_CH1_IRQn); - NVIC_EnableIRQ(TIMER_CH1_IRQn); - } while((0 <= offset) && (offset < 4)) { - if((uint32_t)args & (1 << offset)) + if((uint32_t)timer_user_cfg->comp_it & (1 << offset)) { TIMER_SetCompValue(timer_device->ch,offset,timeout); TIMER_IntMask(timer_device->ch, offset, UNMASK); @@ -196,10 +192,10 @@ int timer_control(struct device *dev, int cmd, void *args) TIMER_Enable(timer_device->ch); break; } - case DEVICE_CTRL_SUSPEND /* constant-expression */: + case DEVICE_CTRL_TIMER_CH_STOP: { - TIMER_Disable(timer_device->ch); - uint32_t offset = __builtin_ctz((uint32_t)args); + timer_user_cfg_t *timer_user_cfg = ((timer_user_cfg_t *)(args)); + uint32_t offset = __builtin_ctz((uint32_t)timer_user_cfg->comp_it); if(timer_device->ch == TIMER_CH0) { @@ -211,18 +207,25 @@ int timer_control(struct device *dev, int cmd, void *args) } while((0 <= offset) && (offset < 4)) { - if ((uint32_t)args & (1 << offset)) + if ((uint32_t)timer_user_cfg->comp_it & (1 << offset)) { TIMER_SetCompValue(timer_device->ch,offset,TIMER_MAX_VALUE); TIMER_IntMask(timer_device->ch, offset, MASK); } offset ++; } + TIMER_Disable(timer_device->ch); break; } case DEVICE_CTRL_GET_CONFIG: return TIMER_GetCounterValue(timer_device->ch); break; + case DEVICE_CTRL_GET_MATCH_STATUS: + { + uint32_t tmpval = (uint32_t)args; + return TIMER_GetMatchStatus(timer_device->ch, tmpval); + break; + } default: break; } @@ -250,7 +253,7 @@ int timer_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) * @return int */ -int timer_register(enum timer_index_type index, const char *name, uint16_t flag, timer_user_cfg_t *timer_user_cfg) +int timer_register(enum timer_index_type index, const char *name, uint16_t flag) { struct device *dev; @@ -267,7 +270,7 @@ int timer_register(enum timer_index_type index, const char *name, uint16_t flag, dev->status = DEVICE_UNREGISTER; dev->type = DEVICE_CLASS_TIMER; - dev->handle = timer_user_cfg; + dev->handle = NULL; return device_register(dev, name, flag); } diff --git a/drivers/bl702_driver/hal_drv/src/hal_uart.c b/drivers/bl702_driver/hal_drv/src/hal_uart.c index b3e24c03..da715aac 100644 --- a/drivers/bl702_driver/hal_drv/src/hal_uart.c +++ b/drivers/bl702_driver/hal_drv/src/hal_uart.c @@ -29,13 +29,13 @@ #include "uart_config.h" #ifdef BSP_USING_UART0 -void UART0_IRQ(void); +static void UART0_IRQ(void); #endif #ifdef BSP_USING_UART1 -void UART1_IRQ(void); +static void UART1_IRQ(void); #endif -uart_device_t uartx_device[UART_MAX_INDEX] = +static uart_device_t uartx_device[UART_MAX_INDEX] = { #ifdef BSP_USING_UART0 UART0_CONFIG, @@ -54,8 +54,8 @@ uart_device_t uartx_device[UART_MAX_INDEX] = int uart_open(struct device *dev, uint16_t oflag) { uart_device_t *uart_device = (uart_device_t *)dev; - UART_FifoCfg_Type fifoCfg; - UART_CFG_Type uart_cfg; + UART_FifoCfg_Type fifoCfg = {0}; + UART_CFG_Type uart_cfg = {0}; /* disable all interrupt */ UART_IntMask(uart_device->id, UART_INT_ALL, MASK); @@ -184,6 +184,12 @@ int uart_control(struct device *dev, int cmd, void *args) case DEVICE_CTRL_GET_INT /* constant-expression */: /* code */ break; + case DEVICE_CTRL_RESUME /* constant-expression */: + UART_Enable(uart_device->id, UART_TXRX); + break; + case DEVICE_CTRL_SUSPEND /* constant-expression */: + UART_Disable(uart_device->id, UART_TXRX); + break; case DEVICE_CTRL_CONFIG /* constant-expression */: { uart_param_cfg_t* cfg = (uart_param_cfg_t *)args; @@ -305,7 +311,7 @@ int uart_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t si * @param size * @return int */ -int uart_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) +int ATTR_TCM_SECTION uart_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) { uart_device_t *uart_device = (uart_device_t *)dev; if (dev->oflag & DEVICE_OFLAG_DMA_RX) @@ -361,7 +367,7 @@ int uart_register(enum uart_index_type index, const char *name, uint16_t flag) * * @param handle */ -void uart_isr(uart_device_t *handle) +void ATTR_TCM_SECTION uart_isr(uart_device_t *handle) { uint32_t tmpVal = 0; uint32_t maskVal = 0; @@ -442,7 +448,7 @@ void uart_isr(uart_device_t *handle) * @brief * */ -void UART0_IRQ(void) +void ATTR_TCM_SECTION UART0_IRQ(void) { uart_isr(&uartx_device[UART0_INDEX]); } diff --git a/drivers/bl702_driver/hal_drv/src/hal_usb.c b/drivers/bl702_driver/hal_drv/src/hal_usb.c index 4b8338af..a75278fd 100644 --- a/drivers/bl702_driver/hal_drv/src/hal_usb.c +++ b/drivers/bl702_driver/hal_drv/src/hal_usb.c @@ -21,6 +21,7 @@ * */ #include "hal_usb.h" +#include "hal_dma.h" #include "hal_mtimer.h" #include "bl702_usb.h" #include "bl702_glb.h" @@ -36,6 +37,24 @@ usb_dc_device_t usb_fs_device; +static dma_lli_ctrl_t usb_lli_list = +{ + .src_addr = 0, + .dst_addr = 0, + .nextlli = 0, + .cfg.bits.fix_cnt = 0, + .cfg.bits.dst_min_mode = 0, + .cfg.bits.dst_add_mode = 0, + .cfg.bits.SI = 0, + .cfg.bits.DI = 0, + .cfg.bits.SWidth = DMA_TRANSFER_WIDTH_8BIT, + .cfg.bits.DWidth = DMA_TRANSFER_WIDTH_8BIT, + .cfg.bits.SBSize = 0, + .cfg.bits.DBSize = 0, + .cfg.bits.I = 0, + .cfg.bits.TransferSize = 0 +}; + static void usb_set_power_up(void) { uint32_t tmpVal = 0; @@ -192,7 +211,7 @@ static void usb_xcvr_config(BL_Fun_Type NewState) */ int usb_open(struct device *dev, uint16_t oflag) { - USB_Config_Type usbCfg; + USB_Config_Type usbCfg = {0}; usb_set_power_off(); mtimer_delay_ms(10); @@ -305,6 +324,7 @@ int usb_close(struct device *dev) */ int usb_control(struct device *dev, int cmd, void *args) { + struct usb_dc_device *usb_device = (struct usb_dc_device *)dev; switch (cmd) { case DEVICE_CTRL_SET_INT /* constant-expression */: @@ -379,6 +399,18 @@ int usb_control(struct device *dev, int cmd, void *args) return USB_Get_EPx_RX_FIFO_CNT(((uint32_t)args) & 0x7f); case DEVICE_CTRL_USB_DC_GET_EP_FREE: return USB_Is_EPx_RDY_Free(((uint32_t)args) & 0x7f); + case DEVICE_CTRL_ATTACH_TX_DMA /* constant-expression */: + usb_device->tx_dma = (struct device *)args; + break; + case DEVICE_CTRL_ATTACH_RX_DMA /* constant-expression */: + usb_device->rx_dma = (struct device *)args; + break; + case DEVICE_CTRL_USB_DC_SET_TX_DMA /* constant-expression */: + USB_Set_EPx_TX_DMA_Interface_Config(((uint32_t)args) & 0x7f,ENABLE); + break; + case DEVICE_CTRL_USB_DC_SET_RX_DMA /* constant-expression */: + USB_Set_EPx_RX_DMA_Interface_Config(((uint32_t)args) & 0x7f,ENABLE); + break; default: break; } @@ -387,66 +419,56 @@ int usb_control(struct device *dev, int cmd, void *args) int usb_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) { - uint8_t ret = 0; - uint8_t *p = (uint8_t*)buffer; + struct usb_dc_device *usb_device = (struct usb_dc_device *)dev; + uint8_t ep_idx = USB_EP_GET_IDX(pos); - while(size) + if(usb_device->in_ep[ep_idx].ep_cfg.ep_type == USBD_EP_TYPE_ISOC) { - if(USB_Is_EPx_RDY_Free(pos & 0x7f)) - { - uint8_t len = USB_Get_EPx_TX_FIFO_CNT(pos & 0x7f); - if(len) - { - if(len < size) - { - ret = usb_dc_ep_write(dev,pos,p,len,NULL); - size -= len; - p += len; - } - else - { - ret = usb_dc_ep_write(dev,pos,p,size,NULL); - p += size; - size = 0; - } + uint32_t usb_ep_addr = USB_BASE + 0x308 + ep_idx * 0x10; - } - } + dma_channel_stop(usb_device->tx_dma); + usb_lli_list.src_addr = (uint32_t)buffer; + usb_lli_list.dst_addr = usb_ep_addr; + usb_lli_list.cfg.bits.TransferSize = size; + usb_lli_list.cfg.bits.DI = 0; + usb_lli_list.cfg.bits.SI = 1; + usb_lli_list.cfg.bits.SBSize = DMA_BURST_16BYTE; + usb_lli_list.cfg.bits.DBSize = DMA_BURST_1BYTE; + device_control(usb_device->tx_dma,DMA_CHANNEL_UPDATE,(void*)((uint32_t)&usb_lli_list)); + dma_channel_start(usb_device->tx_dma); } - if(!(size%64)) + else { - ret = usb_dc_ep_write(dev,pos,NULL,0,NULL); + } - return ret; + return 0; } int usb_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) { - uint32_t total_rx_len = 0; - uint8_t ret = 0; - uint8_t *p = (uint8_t*)buffer; + struct usb_dc_device *usb_device = (struct usb_dc_device *)dev; + uint8_t ep_idx = USB_EP_GET_IDX(pos); - while(total_rx_len < size) + if(usb_device->out_ep[ep_idx].ep_cfg.ep_type == USBD_EP_TYPE_ISOC) { - if(USB_Is_EPx_RDY_Free(pos)) - { - uint8_t len = USB_Get_EPx_RX_FIFO_CNT(pos); - if(len) - { - ret = usb_dc_ep_read(dev,pos,p,len,NULL); - ret = usb_dc_ep_read(dev,pos,NULL,0,NULL); - total_rx_len += len; - p += len; - } - else - { - ret = usb_dc_ep_read(dev,pos,NULL,0,NULL); - } - } + uint32_t usb_ep_addr = USB_BASE + 0x308 + ep_idx * 0x1c; + + dma_channel_stop(usb_device->tx_dma); + usb_lli_list.src_addr = usb_ep_addr; + usb_lli_list.dst_addr = (uint32_t)buffer; + usb_lli_list.cfg.bits.TransferSize = size; + usb_lli_list.cfg.bits.DI = 1; + usb_lli_list.cfg.bits.SI = 0; + usb_lli_list.cfg.bits.SBSize = DMA_BURST_1BYTE; + usb_lli_list.cfg.bits.DBSize = DMA_BURST_16BYTE; + device_control(usb_device->rx_dma,DMA_CHANNEL_UPDATE,(void*)((uint32_t)&usb_lli_list)); + dma_channel_start(usb_device->rx_dma); } - - return ret; - + else + { + + } + return 0; } /** @@ -675,7 +697,7 @@ int usb_dc_ep_write(struct device *dev, const uint8_t ep, const uint8_t *data, u do { uint32_t avail_space = USB_Get_EPx_TX_FIFO_CNT(ep_idx); - if (avail_space == usb_fs_device.in_ep[ep_idx].ep_cfg.ep_mps) + if (avail_space >= usb_fs_device.in_ep[ep_idx].ep_cfg.ep_mps) { break; } @@ -755,7 +777,7 @@ int usb_dc_ep_read(struct device *dev, const uint8_t ep, uint8_t *data, uint32_t USB_DC_LOG_ERR("Not enabled endpoint\r\n"); return -1; } - + /*common process for other ep out*/ if(ep_idx) { while (!USB_Is_EPx_RDY_Free(ep_idx)) @@ -768,6 +790,19 @@ int usb_dc_ep_read(struct device *dev, const uint8_t ep, uint8_t *data, uint32_t } } } + /*special process for ep0 out*/ + else if(read_bytes && data_len && (ep_idx == 0)) + { + while(((BL_RD_WORD(0x4000D800) & (1 << 28)) >> 28)) + { + timeout--; + if (!timeout) + { + USB_DC_LOG_ERR("ep%d wait free timeout\r\n", ep); + return -USB_DC_EP_TIMEOUT_ERR; + } + } + } /* Allow to read 0 bytes */ if (!data_len) diff --git a/drivers/bl702_driver/regs/bl702.h b/drivers/bl702_driver/regs/bl702.h index 36c4381a..46a29bca 100644 --- a/drivers/bl702_driver/regs/bl702.h +++ b/drivers/bl702_driver/regs/bl702.h @@ -10,39 +10,7 @@ /** * @brief Configuration of the Processor and Core Peripherals */ -/** - * @brief Memory access macro - */ -#define BL_RD_WORD(addr) (*((volatile uint32_t*)(addr))) -#define BL_WR_WORD(addr,val) ((*(volatile uint32_t*)(addr))=(val)) -#define BL_RD_SHORT(addr) (*((volatile uint16_t*)(addr))) -#define BL_WR_SHORT(addr,val) ((*(volatile uint16_t*)(addr))=(val)) -#define BL_RD_BYTE(addr) (*((volatile uint8_t*)(addr))) -#define BL_WR_BYTE(addr,val) ((*(volatile uint8_t*)(addr))=(val)) -#define BL_RDWD_FRM_BYTEP(p) ((p[3]<<24)|(p[2]<<16)|(p[1]<<8)|(p[0])) -#define BL_WRWD_TO_BYTEP(p,val) {p[0]=val&0xff;p[1]=(val>>8)&0xff;p[2]=(val>>16)&0xff;p[3]=(val>>24)&0xff;} -/** - * @brief Register access macro - */ -#define BL_RD_REG16(addr,regname) BL_RD_SHORT(addr+regname##_OFFSET) -#define BL_WR_REG16(addr,regname,val) BL_WR_SHORT(addr+regname##_OFFSET,val) -#define BL_RD_REG(addr,regname) BL_RD_WORD(addr+regname##_OFFSET) -#define BL_WR_REG(addr,regname,val) BL_WR_WORD(addr+regname##_OFFSET,val) -#define BL_SET_REG_BIT(val,bitname) ( (val) |(1U<> bitname##_POS ) -#define BL_SET_REG_BITS_VAL(val,bitname,bitval) ( ((val)&bitname##_UMSK) | ((uint32_t)(bitval)< sizeof(tmpBuf)){ + cnt = sizeof(tmpBuf); + } + for(i = 0; i < cnt; i ++){ + data[readLen + i] = tmpBuf[i]; + } + readLen += cnt; + } + + return 0; +} + /****************************************************************************//** * @brief TRNG Interrupt Read Trigger * diff --git a/drivers/bl702_driver/std_drv/src/bl702_uart.c b/drivers/bl702_driver/std_drv/src/bl702_uart.c index 0d7e4dd3..683596d3 100644 --- a/drivers/bl702_driver/std_drv/src/bl702_uart.c +++ b/drivers/bl702_driver/std_drv/src/bl702_uart.c @@ -972,7 +972,7 @@ BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId, uint8_t* data,uint32_t len) * @return The length of the received buffer * *******************************************************************************/ -uint32_t UART_ReceiveData(UART_ID_Type uartId,uint8_t* data,uint32_t maxLen) +uint32_t ATTR_TCM_SECTION UART_ReceiveData(UART_ID_Type uartId,uint8_t* data,uint32_t maxLen) { uint32_t rxLen = 0; uint32_t UARTx = uartAddr[uartId]; @@ -1039,7 +1039,7 @@ uint8_t UART_GetTxFifoCount(UART_ID_Type uartId) * @return Rx fifo occupied count value * *******************************************************************************/ -uint8_t UART_GetRxFifoCount(UART_ID_Type uartId) +uint8_t ATTR_TCM_SECTION UART_GetRxFifoCount(UART_ID_Type uartId) { uint32_t UARTx = uartAddr[uartId];