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[update] update lhal, soc and demos

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This commit is contained in:
jzlv 2022-11-05 10:44:08 +08:00
parent d44726c783
commit c70a3cd8f0
80 changed files with 2206 additions and 323 deletions
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8
examples/peripherals/pwm_v1/pwm_all_channels/main.c
View file

@ -9,12 +9,12 @@ int main(void)
board_init();
board_pwm_gpio_init();
pwm = bflb_device_get_by_name("pwm");
pwm = bflb_device_get_by_name("pwm0");
/* period = .PBCLK / .clk_div / .period = 80MHz / 80 / 1000 = 1KHz */
/* period = .XCLK / .clk_div / .period = 32MHz / 32 / 1000 = 1KHz */
struct bflb_pwm_v1_channel_config_s cfg = {
.clk_source = BFLB_SYSTEM_PBCLK,
.clk_div = 80,
.clk_source = BFLB_SYSTEM_XCLK,
.clk_div = 32,
.period = 1000,
};

8
examples/peripherals/pwm_v1/pwm_basic/main.c
View file

@ -9,12 +9,12 @@ int main(void)
board_init();
board_pwm_gpio_init();
pwm = bflb_device_get_by_name("pwm");
pwm = bflb_device_get_by_name("pwm0");
/* period = .PBCLK / .clk_div / .period = 80MHz / 80 / 1000 = 1KHz */
/* period = .XCLK / .clk_div / .period = 32MHz / 32 / 1000 = 1KHz */
struct bflb_pwm_v1_channel_config_s cfg = {
.clk_source = BFLB_SYSTEM_PBCLK,
.clk_div = 80,
.clk_source = BFLB_SYSTEM_XCLK,
.clk_div = 32,
.period = 1000,
};

10
examples/peripherals/pwm_v1/pwm_int/main.c
View file

@ -42,16 +42,16 @@ int main(void)
board_init();
board_pwm_gpio_init();
pwm = bflb_device_get_by_name("pwm");
pwm = bflb_device_get_by_name("pwm0");
/* period = .PBCLK / .clk_div / .period = 80MHz / 80 / 1000 = 1kHz */
/* period = .XCLK / .clk_div / .period = 32MHz / 32 / 1000 = 1KHz */
struct bflb_pwm_v1_channel_config_s cfg = {
.clk_source = BFLB_SYSTEM_PBCLK,
.clk_div = 80,
.clk_source = BFLB_SYSTEM_XCLK,
.clk_div = 32,
.period = 1000,
};
for (uint8_t i = 0; i <= PWM_V1_CH_MAX; i++) {
for (uint8_t i = 0; i < PWM_V1_CH_MAX; i++) {
bflb_pwm_v1_channel_init(pwm, i, &cfg);
bflb_pwm_v1_channel_set_threshold(pwm, i, 100, 500 + i * 100); /* duty = ((500 + i *100)-100)/1000 */