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[refactor][dma] rename DMA_BURST_xBYTE with DMA_BURST_INCRx

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This commit is contained in:
jzlv 2022-04-26 12:58:47 +08:00
parent c65ae0f8f2
commit d0092f878a
42 changed files with 270 additions and 394 deletions
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11
drivers/bl602_driver/hal_drv/inc/hal_dma.h
View file

@ -77,10 +77,10 @@ enum dma_index_type {
#define DMA_TRANSFER_WIDTH_16BIT 1
#define DMA_TRANSFER_WIDTH_32BIT 2
#define DMA_BURST_1BYTE 0
#define DMA_BURST_4BYTE 1
#define DMA_BURST_8BYTE 2
#define DMA_BURST_16BYTE 3
#define DMA_BURST_INCR1 0
#define DMA_BURST_INCR4 1
#define DMA_BURST_INCR8 2
#define DMA_BURST_INCR16 3
#define DMA_ADDR_UART0_TDR (0x4000A000 + 0x88)
#define DMA_ADDR_UART0_RDR (0x4000A000 + 0x8C)
@ -162,7 +162,8 @@ typedef struct dma_device {
uint8_t dst_burst_size;
uint8_t src_width;
uint8_t dst_width;
dma_lli_ctrl_t *lli_cfg;
uint8_t intr; /* private param */
dma_lli_ctrl_t *lli_cfg;/* private param*/
} dma_device_t;
#define DMA_DEV(dev) ((dma_device_t *)dev)

89
drivers/bl602_driver/hal_drv/src/hal_dma.c
View file

@ -81,13 +81,13 @@ int dma_open(struct device *dev, uint16_t oflag)
/* Disable all interrupt */
DMA_IntMask(dma_device->ch, DMA_INT_ALL, MASK);
/* Enable uart interrupt*/
CPU_Interrupt_Disable(DMA_ALL_IRQn);
DMA_Disable();
DMA_Channel_Disable(dma_device->ch);
dma_device->intr = 0;
chCfg.ch = dma_device->ch;
chCfg.dir = dma_device->direction;
chCfg.srcPeriph = dma_device->src_req;
@ -103,7 +103,7 @@ int dma_open(struct device *dev, uint16_t oflag)
DMA_Enable();
Interrupt_Handler_Register(DMA_ALL_IRQn, DMA0_IRQ);
/* Enable uart interrupt*/
/* Enable dma interrupt*/
CPU_Interrupt_Enable(DMA_ALL_IRQn);
return 0;
}
@ -124,14 +124,14 @@ int dma_control(struct device *dev, int cmd, void *args)
/* Dma interrupt configuration */
DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, UNMASK);
DMA_IntMask(dma_device->ch, DMA_INT_ERR, UNMASK);
dma_device->intr = 1;
break;
case DEVICE_CTRL_CLR_INT:
/* Dma interrupt configuration */
DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, MASK);
DMA_IntMask(dma_device->ch, DMA_INT_ERR, MASK);
dma_device->intr = 0;
break;
case DEVICE_CTRL_GET_INT:
@ -186,6 +186,7 @@ int dma_close(struct device *dev)
DMA_Channel_Disable(dma_device->ch);
DMA_Channel_Init(&chCfg);
dma_device->intr = 0;
return 0;
}
@ -211,64 +212,6 @@ int dma_register(enum dma_index_type index, const char *name)
return device_register(dev, name);
}
static BL_Err_Type dma_scan_unregister_device(uint8_t *allocate_index)
{
struct device *dev;
dlist_t *node;
uint8_t dma_index = 0;
uint32_t dma_handle[DMA_MAX_INDEX];
for (dma_index = 0; dma_index < DMA_MAX_INDEX; dma_index++) {
dma_handle[dma_index] = 0xff;
}
/* get registered dma handle list*/
dlist_for_each(node, device_get_list_header())
{
dev = dlist_entry(node, struct device, list);
if (dev->type == DEVICE_CLASS_DMA) {
dma_handle[(((uint32_t)dev - (uint32_t)dmax_device) / sizeof(dma_device_t)) % DMA_MAX_INDEX] = SET;
}
}
for (dma_index = 0; dma_index < DMA_MAX_INDEX; dma_index++) {
if (dma_handle[dma_index] == 0xff) {
*allocate_index = dma_index;
return SUCCESS;
}
}
return ERROR;
}
int dma_allocate_register(const char *name)
{
struct device *dev;
uint8_t index;
if (DMA_MAX_INDEX == 0) {
return -DEVICE_EINVAL;
}
if (dma_scan_unregister_device(&index) == ERROR) {
return -DEVICE_ENOSPACE;
}
dev = &(dmax_device[index].parent);
dev->open = dma_open;
dev->close = dma_close;
dev->control = dma_control;
// dev->write = dma_write;
// dev->read = dma_read;
dev->type = DEVICE_CLASS_DMA;
dev->handle = NULL;
return device_register(dev, name);
}
/**
* @brief
*
@ -280,11 +223,13 @@ int dma_allocate_register(const char *name)
*/
int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size)
{
#ifdef BSP_USING_DMA
uint32_t malloc_count;
uint32_t remain_len;
uint32_t actual_transfer_len = 0;
uint32_t actual_transfer_offset = 0;
dma_control_data_t dma_ctrl_cfg;
bool intr = false;
dma_device_t *dma_device = (dma_device_t *)dev;
@ -321,6 +266,7 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
}
dma_ctrl_cfg = (dma_control_data_t)(BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL));
intr = dma_device->intr;
malloc_count = actual_transfer_len / 4095;
remain_len = actual_transfer_len % 4095;
@ -329,23 +275,17 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
malloc_count++;
}
if (dma_device->lli_cfg) {
free(dma_device->lli_cfg);
dma_device->lli_cfg = (dma_lli_ctrl_t *)malloc(sizeof(dma_lli_ctrl_t) * malloc_count);
} else {
dma_device->lli_cfg = (dma_lli_ctrl_t *)malloc(sizeof(dma_lli_ctrl_t) * malloc_count);
}
dma_device->lli_cfg = (dma_lli_ctrl_t *)realloc(dma_device->lli_cfg, sizeof(dma_lli_ctrl_t) * malloc_count);
if (dma_device->lli_cfg) {
dma_ctrl_cfg.bits.TransferSize = 4095;
dma_ctrl_cfg.bits.I = 0;
/*transfer_size will be integer multiple of 4095*n or 4095*2*n or 4095*4*n,(n>0) */
for (uint32_t i = 0; i < malloc_count; i++) {
dma_device->lli_cfg[i].src_addr = src_addr;
dma_device->lli_cfg[i].dst_addr = dst_addr;
dma_device->lli_cfg[i].nextlli = 0;
dma_ctrl_cfg.bits.TransferSize = 4095;
dma_ctrl_cfg.bits.I = 0;
if (dma_ctrl_cfg.bits.SI) {
src_addr += actual_transfer_offset;
}
@ -358,7 +298,7 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
if (remain_len) {
dma_ctrl_cfg.bits.TransferSize = remain_len;
}
dma_ctrl_cfg.bits.I = 1;
dma_ctrl_cfg.bits.I = intr;
if (dma_device->transfer_mode == DMA_LLI_CYCLE_MODE) {
dma_device->lli_cfg[i].nextlli = (uint32_t)&dma_device->lli_cfg[0];
@ -369,7 +309,7 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
dma_device->lli_cfg[i - 1].nextlli = (uint32_t)&dma_device->lli_cfg[i];
}
memcpy(&dma_device->lli_cfg[i].cfg, &dma_ctrl_cfg, sizeof(dma_control_data_t));
dma_device->lli_cfg[i].cfg = dma_ctrl_cfg;
}
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_SRCADDR, dma_device->lli_cfg[0].src_addr);
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_DSTADDR, dma_device->lli_cfg[0].dst_addr);
@ -378,9 +318,10 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
} else {
return -2;
}
#endif
return 0;
}
/**
* @brief
*

12
drivers/bl702_driver/hal_drv/inc/hal_dma.h
View file

@ -81,10 +81,10 @@ enum dma_index_type {
#define DMA_TRANSFER_WIDTH_16BIT 1
#define DMA_TRANSFER_WIDTH_32BIT 2
#define DMA_BURST_1BYTE 0
#define DMA_BURST_4BYTE 1
#define DMA_BURST_8BYTE 2
#define DMA_BURST_16BYTE 3
#define DMA_BURST_INCR1 0
#define DMA_BURST_INCR4 1
#define DMA_BURST_INCR8 2
#define DMA_BURST_INCR16 3
#define DMA_ADDR_UART0_TDR (0x4000A000 + 0x88)
#define DMA_ADDR_UART0_RDR (0x4000A000 + 0x8C)
@ -174,13 +174,13 @@ typedef struct dma_device {
uint8_t dst_burst_size;
uint8_t src_width;
uint8_t dst_width;
dma_lli_ctrl_t *lli_cfg;
uint8_t intr; /* private param */
dma_lli_ctrl_t *lli_cfg;/* private param*/
} dma_device_t;
#define DMA_DEV(dev) ((dma_device_t *)dev)
int dma_register(enum dma_index_type index, const char *name);
int dma_allocate_register(const char *name);
int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size);
#ifdef __cplusplus

81
drivers/bl702_driver/hal_drv/src/hal_dma.c
View file

@ -81,13 +81,13 @@ int dma_open(struct device *dev, uint16_t oflag)
/* Disable all interrupt */
DMA_IntMask(dma_device->ch, DMA_INT_ALL, MASK);
/* Enable uart interrupt*/
CPU_Interrupt_Disable(DMA_ALL_IRQn);
DMA_Disable();
DMA_Channel_Disable(dma_device->ch);
dma_device->intr = 0;
chCfg.ch = dma_device->ch;
chCfg.dir = dma_device->direction;
chCfg.srcPeriph = dma_device->src_req;
@ -103,7 +103,7 @@ int dma_open(struct device *dev, uint16_t oflag)
DMA_Enable();
Interrupt_Handler_Register(DMA_ALL_IRQn, DMA0_IRQ);
/* Enable uart interrupt*/
/* Enable dma interrupt*/
CPU_Interrupt_Enable(DMA_ALL_IRQn);
return 0;
}
@ -124,14 +124,14 @@ int dma_control(struct device *dev, int cmd, void *args)
/* Dma interrupt configuration */
DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, UNMASK);
DMA_IntMask(dma_device->ch, DMA_INT_ERR, UNMASK);
dma_device->intr = 1;
break;
case DEVICE_CTRL_CLR_INT:
/* Dma interrupt configuration */
DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, MASK);
DMA_IntMask(dma_device->ch, DMA_INT_ERR, MASK);
dma_device->intr = 0;
break;
case DEVICE_CTRL_GET_INT:
@ -185,6 +185,7 @@ int dma_close(struct device *dev)
DMA_Channel_Disable(dma_device->ch);
DMA_Channel_Init(&chCfg);
dma_device->intr = 0;
return 0;
}
@ -210,65 +211,6 @@ int dma_register(enum dma_index_type index, const char *name)
return device_register(dev, name);
}
static BL_Err_Type dma_scan_unregister_device(uint8_t *allocate_index)
{
struct device *dev;
dlist_t *node;
uint8_t dma_index = 0;
uint32_t dma_handle[DMA_MAX_INDEX];
for (dma_index = 0; dma_index < DMA_MAX_INDEX; dma_index++) {
dma_handle[dma_index] = 0xff;
}
/* get registered dma handle list*/
dlist_for_each(node, device_get_list_header())
{
dev = dlist_entry(node, struct device, list);
if (dev->type == DEVICE_CLASS_DMA) {
dma_handle[(((uint32_t)dev - (uint32_t)dmax_device) / sizeof(dma_device_t)) % DMA_MAX_INDEX] = SET;
}
}
for (dma_index = 0; dma_index < DMA_MAX_INDEX; dma_index++) {
if (dma_handle[dma_index] == 0xff) {
*allocate_index = dma_index;
return SUCCESS;
}
}
return ERROR;
}
int dma_allocate_register(const char *name)
{
struct device *dev;
uint8_t index;
if (DMA_MAX_INDEX == 0) {
return -DEVICE_EINVAL;
}
if (dma_scan_unregister_device(&index) == ERROR) {
return -DEVICE_ENOSPACE;
}
dev = &(dmax_device[index].parent);
dev->open = dma_open;
dev->close = dma_close;
dev->control = dma_control;
// dev->write = dma_write;
// dev->read = dma_read;
dev->status = DEVICE_UNREGISTER;
dev->type = DEVICE_CLASS_DMA;
dev->handle = NULL;
return device_register(dev, name);
}
/**
* @brief
*
@ -280,14 +222,13 @@ int dma_allocate_register(const char *name)
*/
int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size)
{
#if defined(BSP_USING_DMA0_CH0) || defined(BSP_USING_DMA0_CH1) || defined(BSP_USING_DMA0_CH2) || defined(BSP_USING_DMA0_CH3) || \
defined(BSP_USING_DMA0_CH4) || defined(BSP_USING_DMA0_CH5) || defined(BSP_USING_DMA0_CH6) || defined(BSP_USING_DMA0_CH7)
#ifdef BSP_USING_DMA
uint32_t malloc_count;
uint32_t remain_len;
uint32_t actual_transfer_len = 0;
uint32_t actual_transfer_offset = 0;
dma_control_data_t dma_ctrl_cfg;
bool intr = false;
dma_device_t *dma_device = (dma_device_t *)dev;
@ -324,6 +265,7 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
}
dma_ctrl_cfg = (dma_control_data_t)(BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL));
intr = dma_device->intr;
malloc_count = actual_transfer_len / 4095;
remain_len = actual_transfer_len % 4095;
@ -335,15 +277,14 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
dma_device->lli_cfg = (dma_lli_ctrl_t *)realloc(dma_device->lli_cfg, sizeof(dma_lli_ctrl_t) * malloc_count);
if (dma_device->lli_cfg) {
dma_ctrl_cfg.bits.TransferSize = 4095;
dma_ctrl_cfg.bits.I = 0;
/*transfer_size will be integer multiple of 4095*n or 4095*2*n or 4095*4*n,(n>0) */
for (uint32_t i = 0; i < malloc_count; i++) {
dma_device->lli_cfg[i].src_addr = src_addr;
dma_device->lli_cfg[i].dst_addr = dst_addr;
dma_device->lli_cfg[i].nextlli = 0;
dma_ctrl_cfg.bits.TransferSize = 4095;
dma_ctrl_cfg.bits.I = 0;
if (dma_ctrl_cfg.bits.SI) {
src_addr += actual_transfer_offset;
}
@ -356,7 +297,7 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
if (remain_len) {
dma_ctrl_cfg.bits.TransferSize = remain_len;
}
dma_ctrl_cfg.bits.I = 0;
dma_ctrl_cfg.bits.I = intr;
if (dma_device->transfer_mode == DMA_LLI_CYCLE_MODE) {
dma_device->lli_cfg[i].nextlli = (uint32_t)&dma_device->lli_cfg[0];

8
drivers/bl702_driver/hal_drv/src/hal_usb.c
View file

@ -408,8 +408,8 @@ int usb_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t siz
usb_lli_list.cfg.bits.TransferSize = size;
usb_lli_list.cfg.bits.DI = 0;
usb_lli_list.cfg.bits.SI = 1;
usb_lli_list.cfg.bits.SBSize = DMA_BURST_16BYTE;
usb_lli_list.cfg.bits.DBSize = DMA_BURST_1BYTE;
usb_lli_list.cfg.bits.SBSize = DMA_BURST_INCR16;
usb_lli_list.cfg.bits.DBSize = DMA_BURST_INCR1;
dma_channel_update(usb_device->tx_dma, (void *)((uint32_t)&usb_lli_list));
dma_channel_start(usb_device->tx_dma);
return 0;
@ -433,8 +433,8 @@ int usb_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
usb_lli_list.cfg.bits.TransferSize = size;
usb_lli_list.cfg.bits.DI = 1;
usb_lli_list.cfg.bits.SI = 0;
usb_lli_list.cfg.bits.SBSize = DMA_BURST_1BYTE;
usb_lli_list.cfg.bits.DBSize = DMA_BURST_16BYTE;
usb_lli_list.cfg.bits.SBSize = DMA_BURST_INCR1;
usb_lli_list.cfg.bits.DBSize = DMA_BURST_INCR16;
dma_channel_update(usb_device->rx_dma, (void *)((uint32_t)&usb_lli_list));
dma_channel_start(usb_device->rx_dma);
return 0;