diff --git a/README.md b/README.md index b05e1d8c..639b4d52 100644 --- a/README.md +++ b/README.md @@ -15,7 +15,7 @@ Note2：due to the non-generic peripherals, the code style and interface name in | CHIP | v1.4.5 | latest | |:-------------:|:--------:|:-------:| -|BL602/BL604 | √ | × | +|BL602/BL604 | √ | √ | |BL702/BL704/BL706 | √ | √ | |BL616 | × | √ | |BL808 | × | √ | @@ -47,7 +47,7 @@ Note：**√** means supported ；**×** means not supported；**○** means sup | SEC_TRNG | ○ | √ | √ | √ | | SPI | ○ | √ | √ | ○ | | TIMER | ○ | √ | √ | √ | -| UART | ○ | √ | √ | √ | +| UART | √ | √ | √ | √ | | USB_v1 | - | √ | - | - | | USB_v2 | - | - | √ | √ | diff --git a/README_zh.md b/README_zh.md index dd603ba0..1ce10747 100644 --- a/README_zh.md +++ b/README_zh.md @@ -15,7 +15,7 @@ | 芯片 | v1.4.5 | latest | |:-------------:|:--------:|:-------:| -|BL602/BL604 | √ | × | +|BL602/BL604 | √ | √ | |BL702/BL704/BL706 | √ | √ | |BL616 | × | √ | |BL808 | × | √ | @@ -47,7 +47,7 @@ | SEC_TRNG | ○ | √ | √ | √ | | SPI | ○ | √ | √ | ○ | | TIMER | ○ | √ | √ | √ | -| UART | ○ | √ | √ | √ | +| UART | √ | √ | √ | √ | | USB_v1 | - | √ | - | - | | USB_v2 | - | - | √ | √ | diff --git a/bsp/board/bl602dk/CMakeLists.txt b/bsp/board/bl602dk/CMakeLists.txt new file mode 100644 index 00000000..c1e0ab49 --- /dev/null +++ b/bsp/board/bl602dk/CMakeLists.txt @@ -0,0 +1,3 @@ +sdk_add_include_directories(.) + +sdk_set_linker_script(bl602_flash.ld) \ No newline at end of file diff --git a/bsp/board/bl602dk/bl602_flash.ld b/bsp/board/bl602dk/bl602_flash.ld new file mode 100644 index 00000000..b51a8de3 --- /dev/null +++ b/bsp/board/bl602dk/bl602_flash.ld @@ -0,0 +1,232 @@ +/**************************************************************************************** +* @file map.txt +* +* @brief This file is the map file (gnuarm or armgcc). +* +* Copyright (C) BouffaloLab 2018 +* +**************************************************************************************** +*/ + +/* configure the CPU type */ +OUTPUT_ARCH( "riscv" ) +/* link with the standard c library */ +/*INPUT(-lc)*/ +/* link with the standard GCC library */ +/*INPUT(-lgcc)*/ +/* configure the entry point */ +ENTRY(__start) + +StackSize = 0x0400; /* 1KB */ +HeapSize = 0x1000; /* 4KB */ + +MEMORY +{ + xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 1024K + itcm_memory (rx) : ORIGIN = 0x22010000, LENGTH = 16K + dtcm_memory (rx) : ORIGIN = 0x42014000, LENGTH = 48K + ram_memory (!rx) : ORIGIN = 0x42020000, LENGTH = 176K +} + +SECTIONS +{ + PROVIDE(__metal_chicken_bit = 0); + + .text : + { + . = ALIGN(4); + __text_code_start__ = .; + + KEEP (*(SORT_NONE(.init))) + + *(.text) + *(.text.*) + + /* section information for shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /*put .rodata**/ + *(EXCLUDE_FILE( *bl602_glb*.o* \ + *bl602_pds*.o* \ + *bl602_common*.o* \ + *bl602_sf_cfg*.o* \ + *bl602_sf_cfg_ext*.o* \ + *bl602_sf_ctrl*.o* \ + *bl602_sflash*.o* \ + *bl602_sflash_ext*.o* \ + *bl602_xip_sflash*.o* \ + *bl602_xip_sflash_ext*.o* \ + *bl602_ef_ctrl*.o*) .rodata*) + *(.rodata) + *(.rodata.*) + + *(.srodata) + *(.srodata.*) + + . = ALIGN(4); + __text_code_end__ = .; + + } > xip_memory + + . = ALIGN(4); + __itcm_load_addr = .; + + .itcm_region : AT (__itcm_load_addr) + { + . = ALIGN(4); + __tcm_code_start__ = .; + + *(.tcm_code.*) + *(.tcm_const.*) + *(.sclock_rlt_code.*) + *(.sclock_rlt_const.*) + + *bl602_glb*.o*(.rodata*) + *bl602_pds*.o*(.rodata*) + *bl602_common*.o*(.rodata*) + *bl602_sf_cfg*.o*(.rodata*) + *bl602_sf_cfg_ext*.o*(.rodata*) + *bl602_sf_ctrl*.o*(.rodata*) + *bl602_sflash*.o*(.rodata*) + *bl602_sflash_ext*.o*(.rodata*) + *bl602_xip_sflash*.o*(.rodata*) + *bl602_xip_sflash_ext*.o*(.rodata*) + *bl602_ef_ctrl*.o*(.rodata*) + + . = ALIGN(4); + __tcm_code_end__ = .; + } > itcm_memory + + __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); + + .dtcm_region : AT (__dtcm_load_addr) + { + . = ALIGN(4); + __tcm_data_start__ = .; + + *(.tcm_data) + + . = ALIGN(4); + __tcm_data_end__ = .; + } > dtcm_memory + + + /* .heap_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of heap sections, and assign + * values to heap symbols later */ + .heap_dummy (NOLOAD): + { + . = ALIGN(0x4); + . = . + HeapSize; + . = ALIGN(0x4); + } > dtcm_memory + + _HeapBase = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory) - StackSize - HeapSize; + _HeapSize = HeapSize; + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(_HeapBase >= __tcm_data_end__, "region RAM overflowed with stack") + + /*************************************************************************/ + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + . = ALIGN(0x4); + . = . + StackSize; + . = ALIGN(0x4); + } > dtcm_memory + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); + PROVIDE( __freertos_irq_stack_top = __StackTop); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") + /*************************************************************************/ + + __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); + + .system_ram_data_region : AT (__system_ram_load_addr) + { + . = ALIGN(4); + __system_ram_data_start__ = .; + + *(.system_ram) + + . = ALIGN(4); + __system_ram_data_end__ = .; + } > ram_memory + + __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); + + /* Data section */ + RAM_DATA : AT (__ram_load_addr) + { + . = ALIGN(4); + __ram_data_start__ = .; + + PROVIDE( __global_pointer$ = . + 0x800 ); + + *(.data) + *(.data.*) + *(.sdata) + *(.sdata.*) + *(.sdata2) + *(.sdata2.*) + + . = ALIGN(4); + __ram_data_end__ = .; + } > ram_memory + + .bss (NOLOAD) : + { + . = ALIGN(4); + __bss_start__ = .; + + *(.bss*) + *(.sbss*) + *(COMMON) + + . = ALIGN(4); + __bss_end__ = .; + } > ram_memory + + .noinit_data (NOLOAD) : + { + . = ALIGN(4); + __noinit_data_start__ = .; + + *(.noinit_data*) + + . = ALIGN(4); + __noinit_data_end__ = .; + } > ram_memory + + .heap (NOLOAD): + { + . = ALIGN(4); + __HeapBase = .; + + /*__end__ = .;*/ + /*end = __end__;*/ + KEEP(*(.heap*)) + + . = ALIGN(4); + __HeapLimit = .; + } > ram_memory + __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); + +} + diff --git a/bsp/board/bl602dk/board.c b/bsp/board/bl602dk/board.c new file mode 100644 index 00000000..2ff843ed --- /dev/null +++ b/bsp/board/bl602dk/board.c @@ -0,0 +1,168 @@ +#include "bflb_uart.h" +#include "bflb_irq.h" +#include "bflb_gpio.h" +#include "bflb_clock.h" +#include "bflb_rtc.h" +#include "mmheap.h" +#include "board.h" +#include "bl602_glb.h" + +extern uint32_t __HeapBase; +extern uint32_t __HeapLimit; + +struct heap_info mmheap_root; + +static struct bflb_device_s *uart0; + +static struct heap_region system_mmheap[] = { + { NULL, 0 }, + { NULL, 0 }, /* Terminates the array. */ +}; + +static void system_clock_init(void) +{ + GLB_Set_System_CLK(GLB_PLL_XTAL_40M, GLB_SYS_CLK_PLL192M); + GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, 95); +} + +static void peripheral_clock_init(void) +{ + PERIPHERAL_CLOCK_ADC_DAC_ENABLE(); + PERIPHERAL_CLOCK_SEC_ENABLE(); + PERIPHERAL_CLOCK_DMA0_ENABLE(); + PERIPHERAL_CLOCK_UART0_ENABLE(); + PERIPHERAL_CLOCK_UART1_ENABLE(); + PERIPHERAL_CLOCK_SPI0_ENABLE(); + PERIPHERAL_CLOCK_I2C0_ENABLE(); + PERIPHERAL_CLOCK_PWM0_ENABLE(); + PERIPHERAL_CLOCK_TIMER0_1_WDG_ENABLE(); + + GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_160M, 0); + GLB_Set_SPI_CLK(ENABLE, 0); + GLB_Set_I2C_CLK(ENABLE, 0); + + GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 0); + GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_XCLK, 0x3E); +} + +void bl_show_log(void) +{ + printf("\r\n"); + printf(" ____ __ __ _ _ _ \r\n"); + printf(" | _ \\ / _|/ _| | | | | | | \r\n"); + printf(" | |_) | ___ _ _| |_| |_ __ _| | ___ | | __ _| |__ \r\n"); + printf(" | _ < / _ \\| | | | _| _/ _` | |/ _ \\| |/ _` | '_ \\ \r\n"); + printf(" | |_) | (_) | |_| | | | || (_| | | (_) | | (_| | |_) |\r\n"); + printf(" |____/ \\___/ \\__,_|_| |_| \\__,_|_|\\___/|_|\\__,_|_.__/ \r\n"); + printf("\r\n"); + printf("Build:%s,%s\r\n", __TIME__, __DATE__); + printf("Copyright (c) 2022 Bouffalolab team\r\n"); +} + +extern void bflb_uart_set_console(struct bflb_device_s *dev); + +static void console_init() +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + bflb_gpio_uart_init(gpio, GPIO_PIN_16, GPIO_UART_FUNC_UART0_TX); + bflb_gpio_uart_init(gpio, GPIO_PIN_7, GPIO_UART_FUNC_UART0_RX); + + struct bflb_uart_config_s cfg; + cfg.baudrate = 2000000; + cfg.data_bits = UART_DATA_BITS_8; + cfg.stop_bits = UART_STOP_BITS_1; + cfg.parity = UART_PARITY_NONE; + cfg.flow_ctrl = 0; + cfg.tx_fifo_threshold = 15; + cfg.rx_fifo_threshold = 15; + + uart0 = bflb_device_get_by_name("uart0"); + + bflb_uart_init(uart0, &cfg); + bflb_uart_set_console(uart0); +} + +void board_init(void) +{ + bflb_irq_initialize(); + system_clock_init(); + peripheral_clock_init(); + + system_mmheap[0].addr = (uint8_t *)&__HeapBase; + system_mmheap[0].mem_size = ((size_t)&__HeapLimit - (size_t)&__HeapBase); + + if (system_mmheap[0].mem_size > 0) { + mmheap_init(&mmheap_root, system_mmheap); + } + + console_init(); + + bl_show_log(); + + printf("dynamic memory init success,heap size = %d Kbyte \r\n", system_mmheap[0].mem_size / 1024); +} + +void board_uart1_gpio_init() +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + // bflb_gpio_uart_init(gpio, GPIO_PIN_18, GPIO_UART_FUNC_UART1_TX); + // bflb_gpio_uart_init(gpio, GPIO_PIN_19, GPIO_UART_FUNC_UART1_RX); +} + +void board_i2c0_gpio_init() +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + // /* I2C0_SDA */ + // bflb_gpio_init(gpio, GPIO_PIN_11, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + // /* I2C0_SCL */ + // bflb_gpio_init(gpio, GPIO_PIN_16, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); +} + +void board_spi0_gpio_init() +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + // bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + // bflb_gpio_init(gpio, GPIO_PIN_19, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + // bflb_gpio_init(gpio, GPIO_PIN_20, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); +} + +void board_pwm_gpio_init() +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + // bflb_gpio_init(gpio, GPIO_PIN_0, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + // bflb_gpio_init(gpio, GPIO_PIN_1, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + // bflb_gpio_init(gpio, GPIO_PIN_2, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + // bflb_gpio_init(gpio, GPIO_PIN_3, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + // bflb_gpio_init(gpio, GPIO_PIN_4, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); +} + +void board_adc_gpio_init() +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + // bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + // bflb_gpio_init(gpio, GPIO_PIN_19, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + // bflb_gpio_init(gpio, GPIO_PIN_20, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); +} + +void board_dac_gpio_init() +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + /* DAC_CHA */ + // bflb_gpio_init(gpio, GPIO_PIN_11, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + // /* DAC_CHB */ + // bflb_gpio_init(gpio, GPIO_PIN_17, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); +} \ No newline at end of file diff --git a/bsp/board/bl602dk/board.h b/bsp/board/bl602dk/board.h new file mode 100644 index 00000000..7b527d98 --- /dev/null +++ b/bsp/board/bl602dk/board.h @@ -0,0 +1,13 @@ +#ifndef _BOARD_H +#define _BOARD_H + +void board_init(void); + +void board_uart1_gpio_init(); +void board_i2c0_gpio_init(); +void board_spi0_gpio_init(); +void board_adc_gpio_init(); +void board_dac_gpio_init(); +void board_emac_gpio_init(); +void board_pwm_gpio_init(); +#endif \ No newline at end of file diff --git a/drivers/lhal/CMakeLists.txt b/drivers/lhal/CMakeLists.txt index 477b20bc..4f2e3aae 100644 --- a/drivers/lhal/CMakeLists.txt +++ b/drivers/lhal/CMakeLists.txt @@ -5,7 +5,9 @@ sdk_library_add_sources(src/bflb_common.c) sdk_library_add_sources(src/bflb_adc.c) sdk_library_add_sources(src/bflb_dac.c) sdk_library_add_sources(src/bflb_dma.c) +if((NOT ("${CHIP}" STREQUAL "bl602"))) sdk_library_add_sources(src/bflb_emac.c) +endif() sdk_library_add_sources(src/bflb_gpio.c) sdk_library_add_sources(src/bflb_i2c.c) sdk_library_add_sources(src/bflb_ir.c) diff --git a/drivers/lhal/config/bl602/bl602_irq.h b/drivers/lhal/config/bl602/bl602_irq.h new file mode 100644 index 00000000..9a72f12b --- /dev/null +++ b/drivers/lhal/config/bl602/bl602_irq.h @@ -0,0 +1,84 @@ +#ifndef __BL602_IRQ_H +#define __BL602_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define BL602_IRQ_NUM_BASE 16 + +#define BL602_IRQ_MSOFT 3 +#define BL602_IRQ_MTIME 7 +#define BL602_IRQ_MEXT 11 +#define BL602_IRQ_CLIC_SOFT_PEND 12 + +#define BL602_IRQ_BMX_MCU_BUS_ERR (BL602_IRQ_NUM_BASE + 0) +#define BL602_IRQ_BMX_MCU_TO (BL602_IRQ_NUM_BASE + 1) +#define BL602_IRQ_L1C_BMX_ERR (BL602_IRQ_NUM_BASE + 2) +#define BL602_IRQ_L1C_BMX_TO (BL602_IRQ_NUM_BASE + 3) +#define BL602_IRQ_SEC_BMX_ERR (BL602_IRQ_NUM_BASE + 4) +#define BL602_IRQ_RF_TOP_INT0 (BL602_IRQ_NUM_BASE + 5) +#define BL602_IRQ_RF_TOP_INT1 (BL602_IRQ_NUM_BASE + 6) +#define BL602_IRQ_SDIO (BL602_IRQ_NUM_BASE + 7) +#define BL602_IRQ_DMA_BMX_ERR (BL602_IRQ_NUM_BASE + 8) +#define BL602_IRQ_SEC_GMAC (BL602_IRQ_NUM_BASE + 9) +#define BL602_IRQ_SEC_CDET (BL602_IRQ_NUM_BASE + 10) +#define BL602_IRQ_SEC_PKA (BL602_IRQ_NUM_BASE + 11) +#define BL602_IRQ_SEC_TRNG (BL602_IRQ_NUM_BASE + 12) +#define BL602_IRQ_SEC_AES (BL602_IRQ_NUM_BASE + 13) +#define BL602_IRQ_SEC_SHA (BL602_IRQ_NUM_BASE + 14) +#define BL602_IRQ_DMA0_ALL (BL602_IRQ_NUM_BASE + 15) +#define BL602_IRQ_RESERVED0 (BL602_IRQ_NUM_BASE + 16) +#define BL602_IRQ_RESERVED1 (BL602_IRQ_NUM_BASE + 17) +#define BL602_IRQ_RESERVED2 (BL602_IRQ_NUM_BASE + 18) +#define BL602_IRQ_IRTX (BL602_IRQ_NUM_BASE + 19) +#define BL602_IRQ_IRRX (BL602_IRQ_NUM_BASE + 20) +#define BL602_IRQ_RESERVED3 (BL602_IRQ_NUM_BASE + 21) +#define BL602_IRQ_RESERVED4 (BL602_IRQ_NUM_BASE + 22) +#define BL602_IRQ_SF_CTRL (BL602_IRQ_NUM_BASE + 23) +#define BL602_IRQ_RESERVED5 (BL602_IRQ_NUM_BASE + 24) +#define BL602_IRQ_GPADC_DMA (BL602_IRQ_NUM_BASE + 25) +#define BL602_IRQ_EFUSE (BL602_IRQ_NUM_BASE + 26) +#define BL602_IRQ_SPI0 (BL602_IRQ_NUM_BASE + 27) +#define BL602_IRQ_RESERVED6 (BL602_IRQ_NUM_BASE + 28) +#define BL602_IRQ_UART0 (BL602_IRQ_NUM_BASE + 29) +#define BL602_IRQ_UART1 (BL602_IRQ_NUM_BASE + 30) +#define BL602_IRQ_RESERVED7 (BL602_IRQ_NUM_BASE + 31) +#define BL602_IRQ_I2C0 (BL602_IRQ_NUM_BASE + 32) +#define BL602_IRQ_RESERVED8 (BL602_IRQ_NUM_BASE + 33) +#define BL602_IRQ_PWM (BL602_IRQ_NUM_BASE + 34) +#define BL602_IRQ_RESERVED9 (BL602_IRQ_NUM_BASE + 35) +#define BL602_IRQ_TIMER0 (BL602_IRQ_NUM_BASE + 36) +#define BL602_IRQ_TIMER1 (BL602_IRQ_NUM_BASE + 37) +#define BL602_IRQ_WDT (BL602_IRQ_NUM_BASE + 38) +#define BL602_IRQ_RESERVED10 (BL602_IRQ_NUM_BASE + 39) +#define BL602_IRQ_RESERVED11 (BL602_IRQ_NUM_BASE + 40) +#define BL602_IRQ_RESERVED12 (BL602_IRQ_NUM_BASE + 41) +#define BL602_IRQ_RESERVED13 (BL602_IRQ_NUM_BASE + 42) +#define BL602_IRQ_RESERVED14 (BL602_IRQ_NUM_BASE + 43) +#define BL602_IRQ_GPIO_INT0 (BL602_IRQ_NUM_BASE + 44) +#define BL602_IRQ_RESERVED15 (BL602_IRQ_NUM_BASE + 45) +#define BL602_IRQ_RESERVED16 (BL602_IRQ_NUM_BASE + 46) +#define BL602_IRQ_RESERVED17 (BL602_IRQ_NUM_BASE + 47) +#define BL602_IRQ_RESERVED18 (BL602_IRQ_NUM_BASE + 48) +#define BL602_IRQ_RESERVED19 (BL602_IRQ_NUM_BASE + 49) +#define BL602_IRQ_PDS_WAKEUP (BL602_IRQ_NUM_BASE + 50) +#define BL602_IRQ_HBN_OUT0 (BL602_IRQ_NUM_BASE + 51) +#define BL602_IRQ_HBN_OUT1 (BL602_IRQ_NUM_BASE + 52) +#define BL602_IRQ_BOR (BL602_IRQ_NUM_BASE + 53) +#define BL602_IRQ_WIFI (BL602_IRQ_NUM_BASE + 54) +#define BL616_IRQ_BZ_PHY_INT (BL602_IRQ_NUM_BASE + 55) +#define BL602_IRQ_BLE (BL602_IRQ_NUM_BASE + 56) +#define BL602_IRQ_MAC_INT_TIMER (BL602_IRQ_NUM_BASE + 57) +#define BL602_IRQ_MAC_INT_MISC (BL602_IRQ_NUM_BASE + 58) +#define BL602_IRQ_MAC_INT_RX_TRIGGER (BL602_IRQ_NUM_BASE + 59) +#define BL602_IRQ_MAC_INT_TX_TRIGGER (BL602_IRQ_NUM_BASE + 60) +#define BL602_IRQ_MAC_INT_GEN (BL602_IRQ_NUM_BASE + 61) +#define BL602_IRQ_MAC_INT_PROT_TRIGGER (BL602_IRQ_NUM_BASE + 62) +#define BL602_IRQ_WIFI_IPC (BL602_IRQ_NUM_BASE + 63) + +#endif diff --git a/drivers/lhal/config/bl602/bl602_memorymap.h b/drivers/lhal/config/bl602/bl602_memorymap.h new file mode 100644 index 00000000..4e846b55 --- /dev/null +++ b/drivers/lhal/config/bl602/bl602_memorymap.h @@ -0,0 +1,67 @@ +#ifndef __BL702_MEMORYMAP_H +#define __BL702_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +#define BL602_FLASH_XIP_BASE 0x23000000 +#define BL602_FLASH_XIP_END (0x23000000 + 16 * 1024 * 1024) +#define BL602_FLASH_XIP_REMAP0_BASE 0x33000000 +#define BL602_FLASH_XIP_REMAP0_END (0x33000000 + 16 * 1024 * 1024) +#define BL602_FLASH_XIP_REMAP1_BASE 0x43000000 +#define BL602_FLASH_XIP_REMAP1_END (0x43000000 + 16 * 1024 * 1024) +#define BL602_FLASH_XIP_REMAP2_BASE 0x53000000 +#define BL602_FLASH_XIP_REMAP2_END (0x53000000 + 16 * 1024 * 1024) + +#define BL602_WRAM_BASE 0x42020000 +#define BL602_WRAM_END (0x42020000 + 176 * 1024) +#define BL602_WRAM_REMAP0_BASE 0x22020000 +#define BL602_WRAM_REMAP0_END (0x22020000 + 176 * 1024) +#define BL602_WRAM_REMAP1_BASE 0x32020000 +#define BL602_WRAM_REMAP1_END (0x32020000 + 176 * 1024) +#define BL602_WRAM_REMAP2_BASE 0x52020000 +#define BL602_WRAM_REMAP2_END (0x52020000 + 176 * 1024) + +#define BL602_TCM_BASE 0x22008000 +#define BL602_TCM_END (0x22008000 + (96 + 176) * 1024) +#define BL602_TCM_REMAP0_BASE 0x32008000 +#define BL602_TCM_REMAP0_END (0x32008000 + (96 + 176) * 1024) +#define BL602_TCM_REMAP1_BASE 0x42008000 +#define BL602_TCM_REMAP1_END (0x42008000 + (96 + 176) * 1024) +#define BL602_TCM_REMAP2_BASE 0x52008000 +#define BL602_TCM_REMAP2_END (0x52008000 + (96 + 176) * 1024) +/*@} end of group Memory_Map_Section */ + +/* BL602 peripherals base address */ +#define GLB_BASE ((uint32_t)0x40000000) +#define RF_BASE ((uint32_t)0x40001000) +#define GPIP_BASE ((uint32_t)0x40002000) /*!< AUX module base address */ +#define SEC_DBG_BASE ((uint32_t)0x40003000) /*!< Security Debug module base address */ +#define SEC_ENG_BASE ((uint32_t)0x40004000) /*!< Security Engine module base address */ +#define TZC_SEC_BASE ((uint32_t)0x40005000) /*!< Trustzone control security base address */ +#define TZC_NSEC_BASE ((uint32_t)0x40006000) /*!< Trustzone control none-security base address */ +#define EF_DATA_BASE ((uint32_t)0x40007000) +#define EF_CTRL_BASE ((uint32_t)0x40007000) +#define CCI_BASE ((uint32_t)0x40008000) +#define L1C_BASE ((uint32_t)0x40009000) /*!< L1 cache config base address */ +#define UART0_BASE ((uint32_t)0x4000A000) +#define UART1_BASE ((uint32_t)0x4000A100) +#define SPI_BASE ((uint32_t)0x4000A200) +#define I2C_BASE ((uint32_t)0x4000A300) +#define PWM_BASE ((uint32_t)0x4000A400) +#define TIMER_BASE ((uint32_t)0x4000A500) +#define IR_BASE ((uint32_t)0x4000A600) +#define SF_CTRL_BASE ((uint32_t)0x4000B000) +#define SF_CTRL_BUF_BASE ((uint32_t)0x4000B700) +#define DMA_BASE ((uint32_t)0x4000C000) +#define SDU_BASE ((uint32_t)0x4000D000) +#define PDS_BASE ((uint32_t)0x4000E000) /*!< Power down sleep module base address */ +#define HBN_BASE ((uint32_t)0x4000F000) /*!< Hibernate module base address */ +#define AON_BASE ((uint32_t)0x4000F000) /*!< Always on module base address */ +#define HBN_RAM_BASE ((uint32_t)0x40010000) + +#endif \ No newline at end of file diff --git a/drivers/lhal/config/bl602/device_table.c b/drivers/lhal/config/bl602/device_table.c new file mode 100644 index 00000000..cd9c382d --- /dev/null +++ b/drivers/lhal/config/bl602/device_table.c @@ -0,0 +1,183 @@ +#include "bflb_core.h" +#include "bl602_irq.h" +#include "bl602_memorymap.h" + +#define DMA_CHANNEL_OFFSET 0x100 + +struct bflb_device_s bl602_device_table[] = { + { .name = "adc", + .reg_base = AON_BASE, + .irq_num = BL602_IRQ_GPADC_DMA, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_ADC, + .user_data = NULL }, + { .name = "dac", + .reg_base = GLB_BASE, + .irq_num = 0xff, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_DAC, + .user_data = NULL }, + { .name = "gpio", + .reg_base = GLB_BASE, + .irq_num = BL602_IRQ_GPIO_INT0, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_GPIO, + .user_data = NULL }, + { .name = "uart0", + .reg_base = UART0_BASE, + .irq_num = BL602_IRQ_UART0, + .idx = 0, + .dev_type = BFLB_DEVICE_TYPE_UART, + .user_data = NULL }, + { .name = "uart1", + .reg_base = UART1_BASE, + .irq_num = BL602_IRQ_UART1, + .idx = 1, + .dev_type = BFLB_DEVICE_TYPE_UART, + .user_data = NULL }, + { .name = "spi0", + .reg_base = SPI_BASE, + .irq_num = BL602_IRQ_SPI0, + .idx = 0, + .dev_type = BFLB_DEVICE_TYPE_SPI, + .user_data = NULL }, + { .name = "pwm", + .reg_base = PWM_BASE, + .irq_num = BL602_IRQ_PWM, + .idx = 0, + .dev_type = BFLB_DEVICE_TYPE_PWM, + .user_data = NULL }, + { .name = "dma0_ch0", + .reg_base = DMA_BASE + 1 * DMA_CHANNEL_OFFSET, + .irq_num = BL602_IRQ_DMA0_ALL, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_DMA, + .user_data = NULL }, + { .name = "dma0_ch1", + .reg_base = DMA_BASE + 2 * DMA_CHANNEL_OFFSET, + .irq_num = BL602_IRQ_DMA0_ALL, + .idx = 0, + .sub_idx = 1, + .dev_type = BFLB_DEVICE_TYPE_DMA, + .user_data = NULL }, + { .name = "dma0_ch2", + .reg_base = DMA_BASE + 3 * DMA_CHANNEL_OFFSET, + .irq_num = BL602_IRQ_DMA0_ALL, + .idx = 0, + .sub_idx = 2, + .dev_type = BFLB_DEVICE_TYPE_DMA, + .user_data = NULL }, + { .name = "dma0_ch3", + .reg_base = DMA_BASE + 4 * DMA_CHANNEL_OFFSET, + .irq_num = BL602_IRQ_DMA0_ALL, + .idx = 0, + .sub_idx = 3, + .dev_type = BFLB_DEVICE_TYPE_DMA, + .user_data = NULL }, + { .name = "dma0_ch4", + .reg_base = DMA_BASE + 5 * DMA_CHANNEL_OFFSET, + .irq_num = BL602_IRQ_DMA0_ALL, + .idx = 0, + .sub_idx = 4, + .dev_type = BFLB_DEVICE_TYPE_DMA, + .user_data = NULL }, + { .name = "dma0_ch5", + .reg_base = DMA_BASE + 6 * DMA_CHANNEL_OFFSET, + .irq_num = BL602_IRQ_DMA0_ALL, + .idx = 0, + .sub_idx = 5, + .dev_type = BFLB_DEVICE_TYPE_DMA, + .user_data = NULL }, + { .name = "dma0_ch6", + .reg_base = DMA_BASE + 7 * DMA_CHANNEL_OFFSET, + .irq_num = BL602_IRQ_DMA0_ALL, + .idx = 0, + .sub_idx = 6, + .dev_type = BFLB_DEVICE_TYPE_DMA, + .user_data = NULL }, + { .name = "dma0_ch7", + .reg_base = DMA_BASE + 8 * DMA_CHANNEL_OFFSET, + .irq_num = BL602_IRQ_DMA0_ALL, + .idx = 0, + .sub_idx = 7, + .dev_type = BFLB_DEVICE_TYPE_DMA, + .user_data = NULL }, + { .name = "i2c0", + .reg_base = I2C_BASE, + .irq_num = BL602_IRQ_I2C0, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_I2C, + .user_data = NULL }, + { .name = "timer0", + .reg_base = TIMER_BASE, + .irq_num = BL602_IRQ_TIMER0, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_TIMER, + .user_data = NULL }, + { .name = "timer1", + .reg_base = TIMER_BASE, + .irq_num = BL602_IRQ_TIMER1, + .idx = 1, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_TIMER, + .user_data = NULL }, + { .name = "rtc", + .reg_base = HBN_BASE, + .irq_num = BL602_IRQ_HBN_OUT0, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_RTC, + .user_data = NULL }, + { .name = "aes", + .reg_base = SEC_ENG_BASE, + .irq_num = 0xff, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_AES, + .user_data = NULL }, + { .name = "sha", + .reg_base = SEC_ENG_BASE, + .irq_num = 0xff, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_SHA, + .user_data = NULL }, + { .name = "trng", + .reg_base = SEC_ENG_BASE, + .irq_num = 0xff, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_TRNG, + .user_data = NULL }, +}; + +struct bflb_device_s *bflb_device_get_by_name(const char *name) +{ + for (uint8_t i = 0; i < sizeof(bl602_device_table) / sizeof(bl602_device_table[0]); i++) { + if (strcmp(bl602_device_table[i].name, name) == 0) { + return &bl602_device_table[i]; + } + } + return NULL; +} + +struct bflb_device_s *bflb_device_get_by_id(uint8_t type, uint8_t idx) +{ + for (uint8_t i = 0; i < sizeof(bl602_device_table) / sizeof(bl602_device_table[0]); i++) { + if ((bl602_device_table[i].dev_type == type) && (bl602_device_table[i].idx = idx)) { + return &bl602_device_table[i]; + } + } + return NULL; +} + +void bflb_device_set_userdata(struct bflb_device_s *device, void *user_data) +{ + device->user_data = user_data; +} \ No newline at end of file diff --git a/drivers/lhal/include/arch/risc-v/t-head/rv_pmp.h b/drivers/lhal/include/arch/risc-v/t-head/rv_pmp.h index 238eacc3..8b1318f7 100644 --- a/drivers/lhal/include/arch/risc-v/t-head/rv_pmp.h +++ b/drivers/lhal/include/arch/risc-v/t-head/rv_pmp.h @@ -1,6 +1,8 @@ #ifndef _RV_PMP_H_ #define _RV_PMP_H_ +#include "stdint.h" + #define RV_PMP_ENTRY (8) #define ENTRY_FLAG_PERM_R (1 << 0) diff --git a/drivers/lhal/include/bflb_clock.h b/drivers/lhal/include/bflb_clock.h index 50f5fe17..55bdef12 100644 --- a/drivers/lhal/include/bflb_clock.h +++ b/drivers/lhal/include/bflb_clock.h @@ -10,7 +10,7 @@ #define BFLB_SYSTEM_32K_CLK 4 #define BFLB_SYSTEM_1K_CLK 5 -#if defined(BL702) +#if defined(BL702) || defined(BL602) #define BFLB_GLB_CGEN1_BASE (0x40000000 + 0x24) #elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628) #define BFLB_GLB_CGEN1_BASE (0x20000000 + 0x584) diff --git a/drivers/lhal/include/bflb_gpio.h b/drivers/lhal/include/bflb_gpio.h index 0a904be0..31c9dfae 100644 --- a/drivers/lhal/include/bflb_gpio.h +++ b/drivers/lhal/include/bflb_gpio.h @@ -69,7 +69,13 @@ /* cfgset list */ #define GPIO_FUNC_SHIFT (0) /* Bits 0-4: GPIO function */ #define GPIO_FUNC_MASK (0x1f << GPIO_FUNC_SHIFT) -#if defined(BL702) +#if defined(BL602) +#define GPIO_FUNC_SDIO (1 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_SPI0 (4 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_I2C0 (6 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_PWM0 (8 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_JTAG (14 << GPIO_FUNC_SHIFT) +#elif defined(BL702) #define GPIO_FUNC_I2S (3 << GPIO_FUNC_SHIFT) #define GPIO_FUNC_SPI0 (4 << GPIO_FUNC_SHIFT) #define GPIO_FUNC_I2C0 (6 << GPIO_FUNC_SHIFT) @@ -89,6 +95,7 @@ #define GPIO_FUNC_SDU (12 << GPIO_FUNC_SHIFT) #define GPIO_FUNC_PWM0 (16 << GPIO_FUNC_SHIFT) #define GPIO_FUNC_JTAG (26 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_CLKOUT (31 << GPIO_FUNC_SHIFT) #elif defined(BL606P) || defined(BL808) #define GPIO_FUNC_SDH (0 << GPIO_FUNC_SHIFT) #define GPIO_FUNC_SPI0 (1 << GPIO_FUNC_SHIFT) diff --git a/drivers/lhal/include/hardware/adc_reg.h b/drivers/lhal/include/hardware/adc_reg.h index c752be81..3eee688f 100644 --- a/drivers/lhal/include/hardware/adc_reg.h +++ b/drivers/lhal/include/hardware/adc_reg.h @@ -127,7 +127,7 @@ #if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628) #define AON_GPADC_SEN_SEL_MASK (0x7 << AON_GPADC_SEN_SEL_SHIFT) #define AON_GPADC_SEN_TEST_EN (1 << 31U) -#elif defined(BL702) +#elif defined(BL702) || defined(BL602) #define AON_GPADC_SEN_SEL_MASK (0x3 << AON_GPADC_SEN_SEL_SHIFT) #define AON_GPADC_SEN_TEST_EN (1 << 30U) #endif diff --git a/drivers/lhal/include/hardware/dac_reg.h b/drivers/lhal/include/hardware/dac_reg.h index 3eed8fba..74bc696c 100644 --- a/drivers/lhal/include/hardware/dac_reg.h +++ b/drivers/lhal/include/hardware/dac_reg.h @@ -129,7 +129,7 @@ #define GLB_GPDAC_B_OUTMUX_MASK (0x7 << GLB_GPDAC_B_OUTMUX_SHIFT) /* 0x314 : gpdac_data */ -#if defined(BL702) || defined(BL606P) || defined(BL808) +#if defined(BL702) || defined(BL602) || defined(BL606P) || defined(BL808) #define GLB_GPDAC_B_DATA_SHIFT (0U) #define GLB_GPDAC_B_DATA_MASK (0x3ff << GLB_GPDAC_B_DATA_SHIFT) #define GLB_GPDAC_A_DATA_SHIFT (16U) diff --git a/drivers/lhal/include/hardware/gpio_reg.h b/drivers/lhal/include/hardware/gpio_reg.h index 872622eb..c4130f0d 100644 --- a/drivers/lhal/include/hardware/gpio_reg.h +++ b/drivers/lhal/include/hardware/gpio_reg.h @@ -1495,7 +1495,7 @@ #define GLB_GPIO_TX_DATA_TO_FIFO_SHIFT (0U) #define GLB_GPIO_TX_DATA_TO_FIFO_MASK (0xffff<> GPIO_DRV_SHIFT; -#if defined(BL702) +#if defined(BL702) || defined(BL602) uint32_t regval; uint8_t is_odd = 0; - regval = getreg32(dev->reg_base + GLB_GPIO_CFGCTL34_OFFSET + ((pin >> 5) << 2)); + regval = getreg32(reg_base + GLB_GPIO_CFGCTL34_OFFSET + ((pin >> 5) << 2)); regval &= ~(1 << (pin & 0x1f)); - putreg32(regval, dev->reg_base + GLB_GPIO_CFGCTL34_OFFSET + ((pin >> 5) << 2)); + putreg32(regval, reg_base + GLB_GPIO_CFGCTL34_OFFSET + ((pin >> 5) << 2)); is_odd = (pin % 2); @@ -30,7 +30,7 @@ void bflb_gpio_init(struct bflb_device_s *dev, uint8_t pin, uint32_t cfgset) cfg = getreg32(cfg_address); cfg &= ~(0xffff << (16 * is_odd)); - regval = getreg32(dev->reg_base + GLB_GPIO_CFGCTL34_OFFSET + ((pin >> 5) << 2)); + regval = getreg32(reg_base + GLB_GPIO_CFGCTL34_OFFSET + ((pin >> 5) << 2)); if (mode == GPIO_INPUT) { cfg |= (1 << (is_odd * 16 + 0)); regval &= ~(1 << (pin & 0x1f)); @@ -44,13 +44,15 @@ void bflb_gpio_init(struct bflb_device_s *dev, uint8_t pin, uint32_t cfgset) } else if (mode == GPIO_ALTERNATE) { cfg |= (1 << (is_odd * 16 + 0)); regval &= ~(1 << (pin & 0x1f)); + } else { } - putreg32(regval, dev->reg_base + GLB_GPIO_CFGCTL34_OFFSET + ((pin >> 5) << 2)); + putreg32(regval, reg_base + GLB_GPIO_CFGCTL34_OFFSET + ((pin >> 5) << 2)); if (cfgset & GPIO_PULLUP) { cfg |= (1 << (is_odd * 16 + 4)); } else if (cfgset & GPIO_PULLDOWN) { cfg |= (1 << (is_odd * 16 + 5)); + } else { } if (cfgset & GPIO_SMT_EN) { @@ -74,12 +76,14 @@ void bflb_gpio_init(struct bflb_device_s *dev, uint8_t pin, uint32_t cfgset) function = 10; } else if (mode == GPIO_ALTERNATE) { cfg |= GLB_REG_GPIO_0_IE; + } else { } if (cfgset & GPIO_PULLUP) { cfg |= GLB_REG_GPIO_0_PU; } else if (cfgset & GPIO_PULLDOWN) { cfg |= GLB_REG_GPIO_0_PD; + } else { } if (cfgset & GPIO_SMT_EN) { @@ -102,7 +106,7 @@ void bflb_gpio_deinit(struct bflb_device_s *dev, uint8_t pin) void bflb_gpio_set(struct bflb_device_s *dev, uint8_t pin) { -#if defined(BL702) +#if defined(BL702) || defined(BL602) putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET); #elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628) putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFG138_OFFSET + ((pin >> 5) << 2)); @@ -111,7 +115,7 @@ void bflb_gpio_set(struct bflb_device_s *dev, uint8_t pin) void bflb_gpio_reset(struct bflb_device_s *dev, uint8_t pin) { -#if defined(BL702) +#if defined(BL702) || defined(BL602) putreg32(0 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET); #elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628) putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFG140_OFFSET + ((pin >> 5) << 2)); @@ -120,7 +124,7 @@ void bflb_gpio_reset(struct bflb_device_s *dev, uint8_t pin) bool bflb_gpio_read(struct bflb_device_s *dev, uint8_t pin) { -#if defined(BL702) +#if defined(BL702) || defined(BL602) return (getreg32(dev->reg_base + GLB_GPIO_CFGCTL30_OFFSET) & (1 << pin)); #elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628) return (getreg32(dev->reg_base + GLB_GPIO_CFG0_OFFSET + (pin << 2)) & GLB_REG_GPIO_0_I); @@ -140,7 +144,7 @@ void bflb_gpio_int_init(struct bflb_device_s *dev, uint8_t pin, uint8_t trig_mod bflb_gpio_int_mask(dev, pin, true); bflb_gpio_int_clear(dev, pin); -#if defined(BL702) +#if defined(BL702) || defined(BL602) cfg_address = reg_base + GLB_GPIO_INT_MODE_SET1_OFFSET + ((pin / 10) << 2); regval = getreg32(cfg_address); regval &= ~(0x07 << ((pin % 10) * 3)); @@ -161,7 +165,7 @@ void bflb_gpio_int_mask(struct bflb_device_s *dev, uint8_t pin, bool mask) uint32_t regval; reg_base = dev->reg_base; -#if defined(BL702) +#if defined(BL702) || defined(BL602) cfg_address = reg_base + GLB_GPIO_INT_MASK1_OFFSET; regval = getreg32(cfg_address); @@ -185,7 +189,7 @@ void bflb_gpio_int_mask(struct bflb_device_s *dev, uint8_t pin, bool mask) bool bflb_gpio_get_intstatus(struct bflb_device_s *dev, uint8_t pin) { -#if defined(BL702) +#if defined(BL702) || defined(BL602) return (getreg32(dev->reg_base + GLB_GPIO_INT_STAT1_OFFSET) & (1 << pin)); #elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628) return (getreg32(dev->reg_base + GLB_GPIO_CFG0_OFFSET + (pin << 2)) & GLB_GPIO_0_INT_STAT); @@ -199,7 +203,7 @@ void bflb_gpio_int_clear(struct bflb_device_s *dev, uint8_t pin) uint32_t regval; reg_base = dev->reg_base; -#if defined(BL702) +#if defined(BL702) || defined(BL602) cfg_address = reg_base + GLB_GPIO_INT_CLR1_OFFSET; regval = getreg32(cfg_address); @@ -226,7 +230,7 @@ void bflb_gpio_uart_init(struct bflb_device_s *dev, uint8_t pin, uint8_t uart_fu uint8_t sig_pos; reg_base = dev->reg_base; -#if defined(BL702) +#if defined(BL702) || defined(BL602) #define GLB_UART_SIG_SEL_0_OFFSET (0xC0) regval = getreg32(reg_base + GLB_UART_SIG_SEL_0_OFFSET); diff --git a/drivers/lhal/src/bflb_uart.c b/drivers/lhal/src/bflb_uart.c index 0f8c747f..23e2ec92 100644 --- a/drivers/lhal/src/bflb_uart.c +++ b/drivers/lhal/src/bflb_uart.c @@ -71,7 +71,17 @@ void bflb_uart_init(struct bflb_device_s *dev, const struct bflb_uart_config_s * /* Write back */ putreg32(tx_cfg, reg_base + UART_UTX_CONFIG_OFFSET); putreg32(rx_cfg, reg_base + UART_URX_CONFIG_OFFSET); - +#if defined(BL602) + if (config->flow_ctrl & UART_FLOWCTRL_RTS) { + regval = getreg32(reg_base + UART_URX_CONFIG_OFFSET); + regval |= UART_CR_URX_RTS_SW_MODE; + putreg32(regval, reg_base + UART_URX_CONFIG_OFFSET); + } else { + regval = getreg32(reg_base + UART_URX_CONFIG_OFFSET); + regval &= ~UART_CR_URX_RTS_SW_MODE; + putreg32(regval, reg_base + UART_URX_CONFIG_OFFSET); + } +#else if (config->flow_ctrl & UART_FLOWCTRL_RTS) { regval = getreg32(reg_base + UART_SW_MODE_OFFSET); regval |= UART_CR_URX_RTS_SW_MODE; @@ -81,7 +91,7 @@ void bflb_uart_init(struct bflb_device_s *dev, const struct bflb_uart_config_s * regval &= ~UART_CR_URX_RTS_SW_MODE; putreg32(regval, reg_base + UART_SW_MODE_OFFSET); } - +#endif regval = getreg32(reg_base + UART_DATA_CONFIG_OFFSET); regval &= ~UART_CR_UART_BIT_INV; putreg32(regval, reg_base + UART_DATA_CONFIG_OFFSET); @@ -257,12 +267,16 @@ void bflb_uart_errint_mask(struct bflb_device_s *dev, bool mask) int_mask |= UART_CR_URX_PCE_MASK; int_mask |= UART_CR_UTX_FER_MASK; int_mask |= UART_CR_URX_FER_MASK; +#if !defined(BL602) int_mask |= UART_CR_URX_LSE_MASK; +#endif } else { int_mask &= ~UART_CR_URX_PCE_MASK; int_mask &= ~UART_CR_UTX_FER_MASK; int_mask &= ~UART_CR_URX_FER_MASK; +#if !defined(BL602) int_mask &= ~UART_CR_URX_LSE_MASK; +#endif } putreg32(int_mask, reg_base + UART_INT_MASK_OFFSET); } @@ -373,6 +387,8 @@ void bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) break; case UART_CMD_SET_RTS_VALUE: +#if defined(BL602) +#else /* Set rx rts output software control value */ tmp = getreg32(reg_base + UART_SW_MODE_OFFSET); tmp &= ~UART_CR_URX_RTS_SW_VAL; @@ -380,6 +396,7 @@ void bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) tmp |= UART_CR_URX_RTS_SW_VAL; } putreg32(tmp, reg_base + UART_SW_MODE_OFFSET); +#endif break; case UART_CMD_GET_TX_FIFO_CNT: @@ -421,7 +438,7 @@ void bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) *((uint32_t *)arg + 1) = (tmp & UART_STS_URX_ABR_PRD_0X55_MASK) >> UART_STS_URX_ABR_PRD_0X55_SHIFT; } break; - +#if !defined(BL602) case UART_CMD_SET_BREAK_VALUE: /* Set lin mode break value */ tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET); @@ -453,7 +470,7 @@ void bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET); break; - +#endif case UART_CMD_SET_TX_RX_EN: /* Set tx and rx enable */ tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET); diff --git a/drivers/soc/bl602/CMakeLists.txt b/drivers/soc/bl602/CMakeLists.txt new file mode 100644 index 00000000..a7cdbe0a --- /dev/null +++ b/drivers/soc/bl602/CMakeLists.txt @@ -0,0 +1,31 @@ +sdk_generate_library() + +sdk_library_add_sources(startup/start.S) +sdk_library_add_sources(startup/start_load.c) +sdk_library_add_sources(startup/system_bl602.c) +sdk_library_add_sources(startup/interrupt.c) + +sdk_library_add_sources(bl602_std/src/bl602_clock.c) +sdk_library_add_sources(bl602_std/src/bl602_glb.c) +sdk_library_add_sources(bl602_std/src/bl602_hbn.c) +sdk_library_add_sources(bl602_std/src/bl602_romapi.c) +# sdk_library_add_sources(bl602_std/src/bl602_pds.c) +# sdk_library_add_sources(bl602_std/src/bl602_common.c) +# sdk_library_add_sources(bl602_std/src/bl602_l1c.c) +# sdk_library_add_sources(bl602_std/src/bl602_aon.c) +sdk_library_add_sources(port/bl602_clock.c) + +sdk_add_include_directories( +bl602_std/include +bl602_std/include/hardware +) + +SET(MCPU "riscv-e24") +SET(MARCH "rv32imafc") +SET(MABI "ilp32f") + +sdk_add_compile_definitions(-DARCH_RISCV) +sdk_add_compile_options(-march=${MARCH} -mabi=${MABI}) +sdk_add_link_options(-march=${MARCH} -mabi=${MABI}) + +sdk_add_compile_definitions(-DCONFIG_IRQ_NUM=80) \ No newline at end of file diff --git a/drivers/soc/bl602/bl602_std/include/bl602_aon.h b/drivers/soc/bl602/bl602_std/include/bl602_aon.h new file mode 100644 index 00000000..7762aefb --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/bl602_aon.h @@ -0,0 +1,108 @@ +/** + ****************************************************************************** + * @file bl602_aon.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_AON_H__ +#define __BL602_AON_H__ + +#include "aon_reg.h" +#include "glb_reg.h" +#include "hbn_reg.h" +#include "pds_reg.h" +#include "bl602_ef_ctrl.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup AON + * @{ + */ + +/** @defgroup AON_Public_Types + * @{ + */ + +/*@} end of group AON_Public_Types */ + +/** @defgroup AON_Public_Constants + * @{ + */ + +/*@} end of group AON_Public_Constants */ + +/** @defgroup AON_Public_Macros + * @{ + */ + +/*@} end of group AON_Public_Macros */ + +/** @defgroup AON_Public_Functions + * @{ + */ +/*----------*/ +BL_Err_Type AON_Power_On_MBG(void); +BL_Err_Type AON_Power_Off_MBG(void); +/*----------*/ +BL_Err_Type AON_Power_On_XTAL(void); +BL_Err_Type AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut); +uint8_t AON_Get_Xtal_CapCode(void); +BL_Err_Type AON_Power_Off_XTAL(void); +/*----------*/ +BL_Err_Type AON_Power_On_BG(void); +BL_Err_Type AON_Power_Off_BG(void); +/*----------*/ +BL_Err_Type AON_Power_On_LDO11_SOC(void); +BL_Err_Type AON_Power_Off_LDO11_SOC(void); +/*----------*/ +BL_Err_Type AON_Power_On_LDO15_RF(void); +BL_Err_Type AON_Power_Off_LDO15_RF(void); +/*----------*/ +BL_Err_Type AON_Power_On_SFReg(void); +BL_Err_Type AON_Power_Off_SFReg(void); +/*----------*/ +BL_Err_Type AON_LowPower_Enter_PDS0(void); +BL_Err_Type AON_LowPower_Exit_PDS0(void); +/*----------*/ +BL_Err_Type AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay); +/*----------*/; + +/*@} end of group AON_Public_Functions */ + +/*@} end of group AON */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_AON_H__ */ diff --git a/drivers/soc/bl602/bl602_std/include/bl602_clock.h b/drivers/soc/bl602/bl602_std/include/bl602_clock.h new file mode 100644 index 00000000..07e2f93e --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/bl602_clock.h @@ -0,0 +1,128 @@ +/** + ****************************************************************************** + * @file bl602_clock.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_CLOCK_H__ +#define __BL602_CLOCK_H__ + +#include "glb_reg.h" +#include "bl602_hbn.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup CLOCK + * @{ + */ + +/** @defgroup CLOCK_Public_Types + * @{ + */ + +/** + * @brief System clock type definition + */ +typedef enum { + BL_SYSTEM_CLOCK_ROOT, /*!< ROOT clock */ + BL_SYSTEM_CLOCK_FCLK, /*!< Fast clock/CPU clock */ + BL_SYSTEM_CLOCK_BCLK, /*!< BUS clock */ + BL_SYSTEM_CLOCK_F32K, /*!< F32K clock */ + BL_SYSTEM_CLOCK_XCLK, /*!< XCLK:RC32M or XTAL */ + BL_SYSTEM_CLOCK_XTAL, /*!< XTAL clock */ + BL_SYSTEM_CLOCK_MAX, /*!< MAX type of system clock */ +} BL_System_Clock_Type; + +typedef enum { + BL_PERIPHERAL_CLOCK_UART0, /*!< UART0 clock */ + BL_PERIPHERAL_CLOCK_UART1, /*!< UART1 clock */ + BL_PERIPHERAL_CLOCK_SPI0, /*!< SPI0 clock */ + BL_PERIPHERAL_CLOCK_I2C0, /*!< I2C0 clock */ + BL_PERIPHERAL_CLOCK_GPADC, /*!< GPADC clock */ + BL_PERIPHERAL_CLOCK_GPDAC, /*!< GPDAC clock */ + BL_PERIPHERAL_CLOCK_PWM, /*!< PWM clock */ + BL_PERIPHERAL_CLOCK_IR, /*!< IR clock */ + BL_PERIPHERAL_CLOCK_FLASH, /*!< FLASH clock */ + BL_PERIPHERAL_CLOCK_MAX, +} BL_Peripheral_Type; + +/** + * @brief SOC clock config type + */ +typedef struct +{ + uint16_t systemClock[BL_SYSTEM_CLOCK_MAX]; /*!< System lock value */ + uint16_t peripheralClock[BL_AHB_SLAVE1_MAX]; /*!< Pewripherals clock value */ + uint32_t i2sClock; /*!< I2S clock */ +} Clock_Cfg_Type; + +/*@} end of group CLOCK_Public_Types */ + +/** @defgroup CLOCK_Public_Constants + * @{ + */ + +/** @defgroup BL_SYSTEM_CLOCK_TYPE + * @{ + */ +#define IS_BL_SYSTEM_CLOCK_TYPE(type) (((type) == BL_SYSTEM_CLOCK_ROOT) || \ + ((type) == BL_SYSTEM_CLOCK_FCLK) || \ + ((type) == BL_SYSTEM_CLOCK_BCLK) || \ + ((type) == BL_SYSTEM_CLOCK_F32K) || \ + ((type) == BL_SYSTEM_CLOCK_XCLK) || \ + ((type) == BL_SYSTEM_CLOCK_XTAL) || \ + ((type) == BL_SYSTEM_CLOCK_MAX)) + +/*@} end of group CLOCK_Public_Constants */ + +/** @defgroup CLOCK_Public_Macros + * @{ + */ + +/*@} end of group CLOCK_Public_Macros */ + +/** @defgroup CLOCK_Public_Functions + * @{ + */ +uint32_t Clock_System_Clock_Get(BL_System_Clock_Type type); +uint32_t Clock_Peripheral_Clock_Get(BL_Peripheral_Type type); + +/*@} end of group CLOCK_Public_Functions */ + +/*@} end of group CLOCK */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_CLOCK_H__ */ diff --git a/drivers/soc/bl602/bl602_std/include/bl602_common.h b/drivers/soc/bl602/bl602_std/include/bl602_common.h new file mode 100644 index 00000000..9f831e20 --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/bl602_common.h @@ -0,0 +1,210 @@ +#ifndef __BL602_COMMON_H__ +#define __BL602_COMMON_H__ + +#include "bl602.h" +#include "bflb_core.h" + +/** + * @brief Memory access macro + */ +#define BL_RD_WORD(addr) (*((volatile uint32_t *)(uintptr_t)(addr))) +#define BL_WR_WORD(addr, val) ((*(volatile uint32_t *)(uintptr_t)(addr)) = (val)) +#define BL_RD_SHORT(addr) (*((volatile uint16_t *)(uintptr_t)(addr))) +#define BL_WR_SHORT(addr, val) ((*(volatile uint16_t *)(uintptr_t)(addr)) = (val)) +#define BL_RD_BYTE(addr) (*((volatile uint8_t *)(uintptr_t)(addr))) +#define BL_WR_BYTE(addr, val) ((*(volatile uint8_t *)(uintptr_t)(addr)) = (val)) +#define BL_RDWD_FRM_BYTEP(p) ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0])) + +#define BL_WRWD_TO_BYTEP(p, val) \ + { \ + p[0] = val & 0xff; \ + p[1] = (val >> 8) & 0xff; \ + p[2] = (val >> 16) & 0xff; \ + p[3] = (val >> 24) & 0xff; \ + } +/** + * @brief Register access macro + */ +#define BL_RD_REG16(addr, regname) BL_RD_SHORT(addr + regname##_OFFSET) +#define BL_WR_REG16(addr, regname, val) BL_WR_SHORT(addr + regname##_OFFSET, val) +#define BL_RD_REG(addr, regname) BL_RD_WORD(addr + regname##_OFFSET) +#define BL_WR_REG(addr, regname, val) BL_WR_WORD(addr + regname##_OFFSET, val) +#define BL_SET_REG_BIT(val, bitname) ((val) | (1U << bitname##_POS)) +#define BL_CLR_REG_BIT(val, bitname) ((val)&bitname##_UMSK) +#define BL_GET_REG_BITS_VAL(val, bitname) (((val)&bitname##_MSK) >> bitname##_POS) +#define BL_SET_REG_BITS_VAL(val, bitname, bitval) (((val)&bitname##_UMSK) | ((uint32_t)(bitval) << bitname##_POS)) +#define BL_IS_REG_BIT_SET(val, bitname) (((val) & (1U << (bitname##_POS))) != 0) +#define BL_DRV_DUMMY \ + { \ + __ASM volatile("nop"); \ + __ASM volatile("nop"); \ + __ASM volatile("nop"); \ + __ASM volatile("nop"); \ + } + +/** @defgroup COMMON_Public_Types + * @{ + */ +#ifdef BIT +#undef BIT +#define BIT(n) (1UL << (n)) +#else +#define BIT(n) (1UL << (n)) +#endif + +/** + * @brief Null Type definition + */ +#ifndef NULL +#define NULL 0 +#endif + +/** + * @brief Error type definition + */ +typedef enum { + SUCCESS = 0, + ERROR = 1, + TIMEOUT = 2, + INVALID = 3, /* invalid arguments */ + NORESC = 4 /* no resource or resource temperary unavailable */ +} BL_Err_Type; + +/** + * @brief Functional type definition + */ +typedef enum { + DISABLE = 0, + ENABLE = 1, +} BL_Fun_Type; + +/** + * @brief Status type definition + */ +typedef enum { + RESET = 0, + SET = 1, +} BL_Sts_Type; + +/** + * @brief Mask type definition + */ +typedef enum { + UNMASK = 0, + MASK = 1 +} BL_Mask_Type; + +/** + * @brief Logical status Type definition + */ +typedef enum { + LOGIC_LO = 0, + LOGIC_HI = !LOGIC_LO +} LogicalStatus; + +/** + * @brief Active status Type definition + */ +typedef enum { + DEACTIVE = 0, + ACTIVE = !DEACTIVE +} ActiveStatus; + +/** + * @brief Interrupt callback function type + */ +typedef void(intCallback_Type)(void); +typedef void (*pFunc)(void); + +#ifdef DEBUG +void check_failed(uint8_t *file, uint32_t line); +#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__)) +#else +#define CHECK_PARAM(expr) ((void)0) +#endif /* DEBUG */ + +#ifndef __NOP +#define __NOP() __ASM volatile("nop") /* This implementation generates debug information */ +#endif +#ifndef __WFI +#define __WFI() __ASM volatile("wfi") /* This implementation generates debug information */ +#endif +#ifndef __WFE +#define __WFE() __ASM volatile("wfe") /* This implementation generates debug information */ +#endif +#ifndef __SEV +#define __SEV() __ASM volatile("sev") /* This implementation generates debug information */ +#endif +#ifndef __set_MSP +#define __set_MSP(msp) __ASM volatile("add sp, x0, %0" ::"r"(msp)) +#endif + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ + //return __builtin_bswap32(value); + uint32_t res = 0; + + res = (value << 24) | (value >> 24); + res &= 0xFF0000FF; /* only for sure */ + res |= ((value >> 8) & 0x0000FF00) | ((value << 8) & 0x00FF0000); + + return res; +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + return __builtin_bswap16(value); +} + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by setting the IE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile("csrs mstatus, 8"); +} + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by clearing the IE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile("csrc mstatus, 8"); +} + +/** @defgroup COMMON_Public_Constants + * @{ + */ + +/** @defgroup DRIVER_INT_PERIPH + * @{ + */ +#define IS_INT_PERIPH(INT_PERIPH) ((INT_PERIPH) < IRQn_LAST) + +/*@} end of group DRIVER_INT_PERIPH */ + +/** @defgroup DRIVER_INT_MASK + * @{ + */ +#define IS_BL_MASK_TYPE(type) (((type) == MASK) || ((type) == UNMASK)) + +/*@} end of group COMMON_Public_Constants */ + +/*@} end of group DRIVER_Public_Macro */ +#define BL602_MemCpy arch_memcpy +#define BL602_MemSet arch_memset +#define BL602_MemCmp arch_memcmp +#define BL602_MemCpy4 arch_memcpy4 +#define BL602_MemCpy_Fast arch_memcpy_fast +#define BL602_MemSet4 arch_memset4 + +#define arch_delay_us BL602_Delay_US +#define arch_delay_ms BL602_Delay_MS + +void BL602_Delay_US(uint32_t cnt); +void BL602_Delay_MS(uint32_t cnt); +#endif diff --git a/drivers/soc/bl602/bl602_std/include/bl602_ef_ctrl.h b/drivers/soc/bl602/bl602_std/include/bl602_ef_ctrl.h new file mode 100644 index 00000000..5e8d1fd6 --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/bl602_ef_ctrl.h @@ -0,0 +1,352 @@ +/** + ****************************************************************************** + * @file bl602_ef_ctrl.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_EF_CTRL_H__ +#define __BL602_EF_CTRL_H__ + +#include "ef_ctrl_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup EF_CTRL + * @{ + */ + +/** @defgroup EF_CTRL_Public_Types + * @{ + */ + +/** + * @brief Efuse Ctrl key slot type definition + */ +typedef enum { + EF_CTRL_KEY_SLOT0, /*!< key slot 0 */ + EF_CTRL_KEY_SLOT1, /*!< key slot 1 */ + EF_CTRL_KEY_SLOT2, /*!< key slot 2 */ + EF_CTRL_KEY_SLOT3, /*!< key slot 3 */ + EF_CTRL_KEY_SLOT4, /*!< key slot 4 */ + EF_CTRL_KEY_SLOT5, /*!< key slot 5 */ + EF_CTRL_KEY_MAX, /*!< */ +} EF_Ctrl_Key_Type; + +/** + * @brief Efuse Ctrl sign type definition + */ +typedef enum { + EF_CTRL_SIGN_NONE, /*!< no sign */ + EF_CTRL_SIGN_RSA, /*!< use RSA to sign */ + EF_CTRL_SIGN_ECC, /*!< use ECC to sign */ +} EF_Ctrl_Sign_Type; + +/** + * @brief Efuse Ctrl flash AES type definition + */ +typedef enum { + EF_CTRL_SF_AES_NONE, /*!< No AES */ + EF_CTRL_SF_AES_128, /*!< AES 128 */ + EF_CTRL_SF_AES_192, /*!< AES 192 */ + EF_CTRL_SF_AES_256, /*!< AES 256 */ +} EF_Ctrl_SF_AES_Type; + +/** + * @brief Efuse Ctrl Dbg type definition + */ +typedef enum { + EF_CTRL_DBG_OPEN = 0, /*!< Open debug */ + EF_CTRL_DBG_PASSWORD, /*!< Open debug with password */ + EF_CTRL_DBG_CLOSE = 4, /*!< Close debug */ +} EF_Ctrl_Dbg_Mode_Type; + +/** + * @brief Efuse Ctrl clock type definition + */ +typedef enum { + EF_CTRL_EF_CLK, /*!< Select efuse clock */ + EF_CTRL_SAHB_CLK, /*!< Select SAHB clock */ +} EF_Ctrl_CLK_Type; + +/** + * @brief Efuse Ctrl clock type definition + */ +typedef enum { + EF_CTRL_PARA_DFT, /*!< Select default cyc parameter */ + EF_CTRL_PARA_MANUAL, /*!< Select manual cyc parameter */ +} EF_Ctrl_CYC_PARA_Type; + +/** + * @brief Efuse Ctrl clock type definition + */ +typedef enum { + EF_CTRL_OP_MODE_AUTO, /*!< Select efuse program auto mode */ + EF_CTRL_OP_MODE_MANUAL, /*!< Select efuse program manual mode */ +} EF_Ctrl_OP_MODE_Type; + +/** + * @brief Efuse Ctrl secure configuration structure type definition + */ +typedef struct +{ + EF_Ctrl_Dbg_Mode_Type ef_dbg_mode; /*!< Efuse debug mode */ + uint8_t ef_dbg_jtag_0_dis; /*!< Jtag debug disable config value */ + uint8_t ef_sboot_en; /*!< Secure boot enable config value */ + uint8_t ef_no_hd_boot_en; /*!< No header boot enable */ +} EF_Ctrl_Sec_Param_Type; + +/** + * @brief Efuse analog RC32M trim type definition + */ +typedef struct +{ + uint32_t trimRc32mCodeFrExt : 8; /*!< Efuse analog trim:trim_rc32m_code_fr_ext */ + uint32_t trimRc32mCodeFrExtParity : 1; /*!< Efuse analog trim:trim_rc32m_ext_code_en_parity */ + uint32_t trimRc32mExtCodeEn : 1; /*!< Efuse analog trim:trim_rc32m_ext_code_en */ + uint32_t reserved : 22; /*!< Efuse analog trim:reserved */ +} Efuse_Ana_RC32M_Trim_Type; + +/** + * @brief Efuse analog RC32K trim type definition + */ +typedef struct +{ + uint32_t trimRc32kCodeFrExt : 10; /*!< Efuse analog trim:trim_rc32k_code_fr_ext */ + uint32_t trimRc32kCodeFrExtParity : 1; /*!< Efuse analog trim:trim_rc32k_code_fr_ext_parity */ + uint32_t trimRc32kExtCodeEn : 1; /*!< Efuse analog trim:trim_rc32k_ext_code_en */ + uint32_t reserved : 20; /*!< Efuse analog trim:reserved */ +} Efuse_Ana_RC32K_Trim_Type; + +/** + * @brief Efuse analog TSEN trim type definition + */ +typedef struct +{ + uint32_t tsenRefcodeCorner : 12; /*!< TSEN refcode */ + uint32_t tsenRefcodeCornerParity : 1; /*!< TSEN refcode parity */ + uint32_t tsenRefcodeCornerEn : 1; /*!< TSEN refcode enable */ + uint32_t tsenRefcodeCornerVersion : 1; /*!< TSEN refcode version */ + uint32_t reserved : 17; /*!< TSEN analog trim:reserved */ +} Efuse_TSEN_Refcode_Corner_Type; + +/** + * @brief Efuse analog ADC Gain trim type definition + */ +typedef struct +{ + uint32_t adcGainCoeff : 12; /*!< ADC gain coeff */ + uint32_t adcGainCoeffParity : 1; /*!< ADC gain coeff parity */ + uint32_t adcGainCoeffEn : 1; /*!< ADC gain coeff enable */ + uint32_t reserved : 18; /*!< ADC gain coeff:reserved */ +} Efuse_ADC_Gain_Coeff_Type; + +/** + * @brief Efuse analog device info type definition + */ +typedef struct +{ + uint32_t rsvd : 19; /*!< Reserved */ + uint32_t chip_ver : 3; /*!< chip revision */ + uint32_t customerID : 2; /*!< Efuse customer ID information */ + uint32_t rsvd_info : 3; /*!< Efuse device info extension: 1:BL602C, 2:BL602L, 3:BL602E */ + uint32_t memoryInfo : 2; /*!< Efuse memory info 0:no memory, 1:1MB flash, 2:2MB flash */ + uint32_t coreInfo : 1; /*!< Efuse reserved */ + uint32_t mcuInfo : 1; /*!< Efuse mcu info 0:wifi, 1:mcu */ + uint32_t pinInfo : 1; /*!< Efuse pin info 0:QFN32, 1:QFN40 */ +} Efuse_Device_Info_Type; + +/** + * @brief Efuse Capcode type definition + */ +typedef struct +{ + uint32_t capCode : 6; /*!< Cap code value */ + uint32_t parity : 1; /*!< Parity of capcode */ + uint32_t en : 1; /*!< Enable status */ + uint32_t rsvd : 24; /*!< Reserved */ +} Efuse_Capcode_Info_Type; + +/** + * @brief Efuse Ldo11 Vout Sel Trim definition + */ +typedef struct { + uint32_t sel_value : 4; /*!< value trim */ + uint32_t parity : 1; /*!< Parity of capcode */ + uint32_t en : 1; /*!< Enable status */ + uint32_t rsvd : 26; /*!< Reserved */ +} Efuse_Ldo11VoutSelTrim_Info_Type; + +/** + * @brief Efuse Tx Power definition + */ +typedef struct { + uint32_t txpower : 5; /*!< txpower value */ + uint32_t parity : 1; /*!< Parity of capcode */ + uint32_t en : 1; /*!< Enable status */ + uint32_t rsvd : 25; /*!< Reserved */ +} Efuse_TxPower_Info_Type; + +/*@} end of group EF_CTRL_Public_Types */ + +/** @defgroup EF_CTRL_Public_Constants + * @{ + */ + +/** @defgroup EF_CTRL_KEY_TYPE + * @{ + */ +#define IS_EF_CTRL_KEY_TYPE(type) (((type) == EF_CTRL_KEY_SLOT0) || \ + ((type) == EF_CTRL_KEY_SLOT1) || \ + ((type) == EF_CTRL_KEY_SLOT2) || \ + ((type) == EF_CTRL_KEY_SLOT3) || \ + ((type) == EF_CTRL_KEY_SLOT4) || \ + ((type) == EF_CTRL_KEY_SLOT5) || \ + ((type) == EF_CTRL_KEY_MAX)) + +/** @defgroup EF_CTRL_SIGN_TYPE + * @{ + */ +#define IS_EF_CTRL_SIGN_TYPE(type) (((type) == EF_CTRL_SIGN_NONE) || \ + ((type) == EF_CTRL_SIGN_RSA) || \ + ((type) == EF_CTRL_SIGN_ECC)) + +/** @defgroup EF_CTRL_SF_AES_TYPE + * @{ + */ +#define IS_EF_CTRL_SF_AES_TYPE(type) (((type) == EF_CTRL_SF_AES_NONE) || \ + ((type) == EF_CTRL_SF_AES_128) || \ + ((type) == EF_CTRL_SF_AES_192) || \ + ((type) == EF_CTRL_SF_AES_256)) + +/** @defgroup EF_CTRL_DBG_MODE_TYPE + * @{ + */ +#define IS_EF_CTRL_DBG_MODE_TYPE(type) (((type) == EF_CTRL_DBG_OPEN) || \ + ((type) == EF_CTRL_DBG_PASSWORD) || \ + ((type) == EF_CTRL_DBG_CLOSE)) + +/** @defgroup EF_CTRL_CLK_TYPE + * @{ + */ +#define IS_EF_CTRL_CLK_TYPE(type) (((type) == EF_CTRL_EF_CLK) || \ + ((type) == EF_CTRL_SAHB_CLK)) + +/** @defgroup EF_CTRL_CYC_PARA_TYPE + * @{ + */ +#define IS_EF_CTRL_CYC_PARA_TYPE(type) (((type) == EF_CTRL_PARA_DFT) || \ + ((type) == EF_CTRL_PARA_MANUAL)) + +/** @defgroup EF_CTRL_OP_MODE_TYPE + * @{ + */ +#define IS_EF_CTRL_OP_MODE_TYPE(type) (((type) == EF_CTRL_OP_MODE_AUTO) || \ + ((type) == EF_CTRL_OP_MODE_MANUAL)) + +/*@} end of group EF_CTRL_Public_Constants */ + +/** @defgroup EF_CTRL_Public_Macros + * @{ + */ +#define EF_CTRL_EFUSE_R0_SIZE 128 + +/*@} end of group EF_CTRL_Public_Macros */ + +/** @defgroup EF_CTRL_Public_Functions + * @{ + */ +void EF_Ctrl_Load_Efuse_R0(void); +void EF_Ctrl_Program_Efuse_0(void); +BL_Sts_Type EF_Ctrl_Busy(void); +BL_Sts_Type EF_Ctrl_AutoLoad_Done(void); +void EF_Ctrl_Write_Dbg_Pwd(uint32_t passWdLow, uint32_t passWdHigh, uint8_t program); +void EF_Ctrl_Read_Dbg_Pwd(uint32_t *passWdLow, uint32_t *passWdHigh); +void EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program); +void EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program); +void EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg, uint8_t program); +void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg); +void EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1], uint8_t program); +void EF_Ctrl_Read_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1]); +void EF_Ctrl_Read_CPU_Cfg(uint8_t *apDisabled, uint8_t *npDisabled, uint8_t *npCpuType); +uint8_t EF_Ctrl_Get_Trim_Enable(void); +uint8_t EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len); +void EF_Ctrl_Write_Ana_Trim(uint32_t index, uint32_t trim, uint8_t program); +void EF_Ctrl_Read_Ana_Trim(uint32_t index, uint32_t *trim); +void EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim); +void EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim); +void EF_Ctrl_Read_TSEN_Trim(Efuse_TSEN_Refcode_Corner_Type *trim); +void EF_Ctrl_Read_ADC_Gain_Trim(Efuse_ADC_Gain_Coeff_Type *trim); +void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage, uint8_t program); +void EF_Ctrl_Read_Sw_Usage(uint32_t index, uint32_t *usage); +void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program); +void EF_Ctrl_Write_MAC_Address(uint8_t mac[6], uint8_t program); +BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[6]); +BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]); +void EF_Ctrl_Writelock_MAC_Address(uint8_t program); +BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t id[8]); +void EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo); +void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program); +void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len); +void EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program); +void EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program); +void EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len); +void EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len); +void EF_Ctrl_Program_Direct(uint32_t index, uint32_t *data, uint32_t len); +void EF_Ctrl_Read_Direct(uint32_t index, uint32_t *data, uint32_t len); +void EF_Ctrl_Clear(uint32_t index, uint32_t len); +void EF_Ctrl_Crc_Enable(void); +BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void); +void EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue); +BL_Err_Type EF_Ctrl_Crc_Result(void); +void EF_Ctrl_Sw_AHB_Clk_0(void); +uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload); +BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t program); +BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t reload); +uint8_t EF_Ctrl_Is_CapCode_Slot_Empty(uint8_t slot, uint8_t reload); +BL_Err_Type EF_Ctrl_Write_CapCode_Opt(uint8_t slot, uint8_t code, uint8_t program); +BL_Err_Type EF_Ctrl_Read_CapCode_Opt(uint8_t slot, uint8_t *code, uint8_t reload); +uint8_t EF_Ctrl_Is_PowerOffset_Slot_Empty(uint8_t slot, uint8_t reload); +BL_Err_Type EF_Ctrl_Write_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[3], uint8_t program); +BL_Err_Type EF_Ctrl_Read_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[3], uint8_t reload); +void EF_Ctrl_Write_R0(uint32_t index, uint32_t *data, uint32_t len); +void EF_Ctrl_Read_R0(uint32_t index, uint32_t *data, uint32_t len); + +/*@} end of group EF_CTRL_Public_Functions */ + +/*@} end of group EF_CTRL */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_EF_CTRL_H__ */ diff --git a/drivers/soc/bl602/bl602_std/include/bl602_glb.h b/drivers/soc/bl602/bl602_std/include/bl602_glb.h new file mode 100644 index 00000000..aac7a407 --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/bl602_glb.h @@ -0,0 +1,667 @@ +/** + ****************************************************************************** + * @file bl602_glb.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_GLB_H__ +#define __BL602_GLB_H__ + +#include "glb_reg.h" +#include "pds_reg.h" +#include "bl602_gpio.h" +// #include "bl602_l1c.h" +#include "bl602_hbn.h" +#include "bl602_sf_ctrl.h" +#include "bl602_sf_cfg.h" +#include "bl602_aon.h" +#include "bl602_ef_ctrl.h" +#include "bl602_pds.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup GLB + * @{ + */ + +/** @defgroup GLB_Public_Types + * @{ + */ + +/** + * @brief GLB root clock type definition + */ +typedef enum { + GLB_ROOT_CLK_RC32M, /*!< root clock select RC32M */ + GLB_ROOT_CLK_XTAL, /*!< root clock select XTAL */ + GLB_ROOT_CLK_PLL, /*!< root clock select PLL others */ +} GLB_ROOT_CLK_Type; + +/** + * @brief GLB system clock type definition + */ +typedef enum { + GLB_SYS_CLK_RC32M, /*!< use RC32M as system clock frequency */ + GLB_SYS_CLK_XTAL, /*!< use XTAL as system clock */ + GLB_SYS_CLK_PLL48M, /*!< use PLL output 48M as system clock */ + GLB_SYS_CLK_PLL120M, /*!< use PLL output 120M as system clock */ + GLB_SYS_CLK_PLL160M, /*!< use PLL output 160M as system clock */ + GLB_SYS_CLK_PLL192M, /*!< use PLL output 192M as system clock */ +} GLB_SYS_CLK_Type; + +/** + * @brief GLB DMA clock ID type definition + */ +typedef enum { + GLB_DMA_CLK_DMA0_CH0, /*!< DMA clock ID:channel 0 */ + GLB_DMA_CLK_DMA0_CH1, /*!< DMA clock ID:channel 1 */ + GLB_DMA_CLK_DMA0_CH2, /*!< DMA clock ID:channel 2 */ + GLB_DMA_CLK_DMA0_CH3, /*!< DMA clock ID:channel 3 */ +} GLB_DMA_CLK_ID_Type; + +/** + * @brief GLB clock source type definition + */ +typedef enum { + GLB_IR_CLK_SRC_XCLK, /*!< IR clock source select XCLK */ +} GLB_IR_CLK_SRC_Type; + +/** + * @brief GLB flash clock type definition + */ +typedef enum { + GLB_SFLASH_CLK_120M, /*!< Select 120M as flash clock */ + GLB_SFLASH_CLK_XTAL, /*!< Select XTAL as flash clock */ + GLB_SFLASH_CLK_48M, /*!< Select 48M as flash clock */ + GLB_SFLASH_CLK_80M, /*!< Select 80M as flash clock */ + GLB_SFLASH_CLK_BCLK, /*!< Select BCLK as flash clock */ + GLB_SFLASH_CLK_96M, /*!< Select 96M as flash clock */ +} GLB_SFLASH_CLK_Type; + +/** + * @brief GLB SPI pad action type definition + */ +typedef enum { + GLB_SPI_PAD_ACT_AS_SLAVE, /*!< SPI pad act as slave */ + GLB_SPI_PAD_ACT_AS_MASTER, /*!< SPI pad act as master */ +} GLB_SPI_PAD_ACT_AS_Type; + +/** + * @brief GLB PKA clock type definition + */ +typedef enum { + GLB_PKA_CLK_HCLK, /*!< Select HCLK as PKA clock */ + GLB_PKA_CLK_PLL120M, /*!< Select PLL 120M as PKA clock */ +} GLB_PKA_CLK_Type; + +/** + * @brief BMX arb mode type definition + */ +typedef enum { + BMX_ARB_FIX, /*!< 0->fix */ + BMX_ARB_ROUND_ROBIN, /*!< 2->round-robin */ + BMX_ARB_RANDOM, /*!< 3->random */ +} BMX_ARB_Type; + +/** + * @brief BMX configuration structure type definition + */ +typedef struct +{ + uint8_t timeoutEn; /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */ + BL_Fun_Type errEn; /*!< Bus error response enable */ + BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */ +} BMX_Cfg_Type; + +/** + * @brief BMX bus err type definition + */ +typedef enum { + BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */ + BMX_BUS_ERR_ADDR_DECODE, /*!< Bus addr decode error */ +} BMX_BUS_ERR_Type; + +/** + * @brief BMX bus err interrupt type definition + */ +typedef enum { + BMX_ERR_INT_ERR, /*!< BMX bus err interrupt */ + BMX_ERR_INT_ALL, /*!< BMX bus err interrupt max num */ +} BMX_ERR_INT_Type; + +/** + * @brief BMX time out interrupt type definition + */ +typedef enum { + BMX_TO_INT_TIMEOUT, /*!< BMX timeout interrupt */ + BMX_TO_INT_ALL, /*!< BMX timeout interrupt max num */ +} BMX_TO_INT_Type; + +/** + * @brief GLB EM type definition + */ +typedef enum { + GLB_EM_0KB = 0x0, /*!< 0x0 --> 0KB */ + GLB_EM_8KB = 0x3, /*!< 0x3 --> 8KB */ + GLB_EM_16KB = 0xF, /*!< 0xF --> 16KB */ +} GLB_EM_Type; + +/** + * @brief GLB RTC clock type definition + */ +typedef enum { + GLB_MTIMER_CLK_BCLK, /*!< BUS clock */ + GLB_MTIMER_CLK_32K, /*!< 32KHz */ +} GLB_MTIMER_CLK_Type; + +/** + * @brief GLB ADC clock type definition + */ +typedef enum { + GLB_ADC_CLK_96M, /*!< use 96M as ADC clock */ + GLB_ADC_CLK_XCLK, /*!< use XCLK as ADC clock */ +} GLB_ADC_CLK_Type; + +/** + * @brief GLB DAC clock type definition + */ +typedef enum { + GLB_DAC_CLK_32M, /*!< use 32M as DAC clock */ + GLB_DAC_CLK_XCLK, /*!< use XCLK as DAC clock */ +} GLB_DAC_CLK_Type; + +/** + * @brief GLB DIG clock source select type definition + */ +typedef enum { + GLB_DIG_CLK_PLL_32M, /*!< select PLL 32M as DIG clock source */ + GLB_DIG_CLK_XCLK, /*!< select XCLK as DIG clock source */ +} GLB_DIG_CLK_Type; + +/** + * @brief GLB 512K clock out select type definition + */ +typedef enum { + GLB_512K_CLK_OUT_512K, /*!< select 512K clock out */ + GLB_512K_CLK_OUT_256K, /*!< select 256K clock out */ + GLB_512K_CLK_OUT_128K, /*!< select 128K clock out */ +} GLB_512K_CLK_OUT_Type; + +/** + * @brief GLB BT bandwidth type definition + */ +typedef enum { + GLB_BT_BANDWIDTH_1M, /*!< BT bandwidth 1MHz */ + GLB_BT_BANDWIDTH_2M, /*!< BT bandwidth 2MHz */ +} GLB_BT_BANDWIDTH_Type; + +/** + * @brief GLB UART signal type definition + */ +typedef enum { + GLB_UART_SIG_0, /*!< UART signal 0 */ + GLB_UART_SIG_1, /*!< UART signal 1 */ + GLB_UART_SIG_2, /*!< UART signal 2 */ + GLB_UART_SIG_3, /*!< UART signal 3 */ + GLB_UART_SIG_4, /*!< UART signal 4 */ + GLB_UART_SIG_5, /*!< UART signal 5 */ + GLB_UART_SIG_6, /*!< UART signal 6 */ + GLB_UART_SIG_7, /*!< UART signal 7 */ +} GLB_UART_SIG_Type; + +/** + * @brief GLB UART signal function type definition + */ +typedef enum { + GLB_UART_SIG_FUN_UART0_RTS, /*!< UART funtion: UART 0 RTS */ + GLB_UART_SIG_FUN_UART0_CTS, /*!< UART funtion: UART 0 CTS */ + GLB_UART_SIG_FUN_UART0_TXD, /*!< UART funtion: UART 0 TXD */ + GLB_UART_SIG_FUN_UART0_RXD, /*!< UART funtion: UART 0 RXD */ + GLB_UART_SIG_FUN_UART1_RTS, /*!< UART funtion: UART 1 RTS */ + GLB_UART_SIG_FUN_UART1_CTS, /*!< UART funtion: UART 1 CTS */ + GLB_UART_SIG_FUN_UART1_TXD, /*!< UART funtion: UART 1 TXD */ + GLB_UART_SIG_FUN_UART1_RXD, /*!< UART funtion: UART 1 RXD */ +} GLB_UART_SIG_FUN_Type; + +/** + * @brief GLB GPIO real mode type definition + */ +typedef enum { + GLB_GPIO_REAL_MODE_REG, /*!< GPIO real function is reg_gpio_x_func_sel */ + GLB_GPIO_REAL_MODE_SDIO = 0x1, /*!< GPIO real function is SDIO */ + GLB_GPIO_REAL_MODE_RF = 0xC, /*!< GPIO real function is RF */ + GLB_GPIO_REAL_MODE_JTAG = 0xE, /*!< GPIO real function is JTAG */ + GLB_GPIO_REAL_MODE_CCI = 0xF, /*!< GPIO real function is CCI */ +} GLB_GPIO_REAL_MODE_Type; + +/** + * @brief GLB GPIO interrupt trigger mode type definition + */ +typedef enum { + GLB_GPIO_INT_TRIG_NEG_PULSE, /*!< GPIO negedge pulse trigger interrupt */ + GLB_GPIO_INT_TRIG_POS_PULSE, /*!< GPIO posedge pulse trigger interrupt */ + GLB_GPIO_INT_TRIG_NEG_LEVEL, /*!< GPIO negedge level trigger interrupt (32k 3T) */ + GLB_GPIO_INT_TRIG_POS_LEVEL, /*!< GPIO posedge level trigger interrupt (32k 3T) */ +} GLB_GPIO_INT_TRIG_Type; + +/** + * @brief GLB GPIO interrupt control mode type definition + */ +typedef enum { + GLB_GPIO_INT_CONTROL_SYNC, /*!< GPIO interrupt sync mode */ + GLB_GPIO_INT_CONTROL_ASYNC, /*!< GPIO interrupt async mode */ +} GLB_GPIO_INT_CONTROL_Type; + +/** + * @brief PLL XTAL type definition + */ +typedef enum { + GLB_PLL_XTAL_NONE, /*!< XTAL is none */ + GLB_PLL_XTAL_24M, /*!< XTAL is 24M */ + GLB_PLL_XTAL_32M, /*!< XTAL is 32M */ + GLB_PLL_XTAL_38P4M, /*!< XTAL is 38.4M */ + GLB_PLL_XTAL_40M, /*!< XTAL is 40M */ + GLB_PLL_XTAL_26M, /*!< XTAL is 26M */ + GLB_PLL_XTAL_RC32M, /*!< XTAL is RC32M */ +} GLB_PLL_XTAL_Type; + +/** + * @brief PLL output clock type definition + */ +typedef enum { + GLB_PLL_CLK_480M, /*!< PLL output clock:480M */ + GLB_PLL_CLK_240M, /*!< PLL output clock:240M */ + GLB_PLL_CLK_192M, /*!< PLL output clock:192M */ + GLB_PLL_CLK_160M, /*!< PLL output clock:160M */ + GLB_PLL_CLK_120M, /*!< PLL output clock:120M */ + GLB_PLL_CLK_96M, /*!< PLL output clock:96M */ + GLB_PLL_CLK_80M, /*!< PLL output clock:80M */ + GLB_PLL_CLK_48M, /*!< PLL output clock:48M */ + GLB_PLL_CLK_32M, /*!< PLL output clock:32M */ +} GLB_PLL_CLK_Type; + +/** + * @brief PLL configuration structure type definition + */ +typedef struct +{ + uint8_t clkpllIcp1u; /*!< int mode:0, frac mode:1 */ + uint8_t clkpllIcp5u; /*!< int mode:2, frac mode:0 */ + uint8_t clkpllIntFracSw; /*!< 0:int mode, 1:frac mode */ + uint8_t clkpllC3; /*!< int:3, frac:2 */ + uint8_t clkpllCz; /*!< int:1, frac:2 */ + uint8_t clkpllRz; /*!< int:1, frac:5 */ + uint8_t clkpllR4; /*!< int:2, frac:2 */ + uint8_t clkpllR4Short; /*!< int:1, frac:0 */ + uint8_t clkpllRefdivRatio; /*!< ref divider ratio */ + uint8_t clkpllPostdiv; /*!< >=8 and should be even number */ + uint32_t clkpllSdmin; /*!< sdmin */ + uint8_t clkpllSelFbClk; /*!< 0:mod1, 1:mod2, 2:mod3 */ + uint8_t clkpllSelSampleClk; /*!< 0:[16,63)mod3, 1:[32:127)mod4, 2:[64,255)mod5 */ +} GLB_PLL_Cfg_Type; + +/*@} end of group GLB_Public_Types */ + +/** @defgroup GLB_Public_Constants + * @{ + */ + +/** @defgroup GLB_ROOT_CLK_TYPE + * @{ + */ +#define IS_GLB_ROOT_CLK_TYPE(type) (((type) == GLB_ROOT_CLK_RC32M) || \ + ((type) == GLB_ROOT_CLK_XTAL) || \ + ((type) == GLB_ROOT_CLK_PLL)) + +/** @defgroup GLB_SYS_CLK_TYPE + * @{ + */ +#define IS_GLB_SYS_CLK_TYPE(type) (((type) == GLB_SYS_CLK_RC32M) || \ + ((type) == GLB_SYS_CLK_XTAL) || \ + ((type) == GLB_SYS_CLK_PLL48M) || \ + ((type) == GLB_SYS_CLK_PLL120M) || \ + ((type) == GLB_SYS_CLK_PLL160M) || \ + ((type) == GLB_SYS_CLK_PLL192M)) + +/** @defgroup GLB_DMA_CLK_ID_TYPE + * @{ + */ +#define IS_GLB_DMA_CLK_ID_TYPE(type) (((type) == GLB_DMA_CLK_DMA0_CH0) || \ + ((type) == GLB_DMA_CLK_DMA0_CH1) || \ + ((type) == GLB_DMA_CLK_DMA0_CH2) || \ + ((type) == GLB_DMA_CLK_DMA0_CH3)) + +/** @defgroup GLB_IR_CLK_SRC_TYPE + * @{ + */ +#define IS_GLB_IR_CLK_SRC_TYPE(type) (((type) == GLB_IR_CLK_SRC_XCLK)) + +/** @defgroup GLB_SFLASH_CLK_TYPE + * @{ + */ +#define IS_GLB_SFLASH_CLK_TYPE(type) (((type) == GLB_SFLASH_CLK_120M) || \ + ((type) == GLB_SFLASH_CLK_XTAL) || \ + ((type) == GLB_SFLASH_CLK_48M) || \ + ((type) == GLB_SFLASH_CLK_80M) || \ + ((type) == GLB_SFLASH_CLK_BCLK) || \ + ((type) == GLB_SFLASH_CLK_96M)) + +/** @defgroup GLB_SPI_PAD_ACT_AS_TYPE + * @{ + */ +#define IS_GLB_SPI_PAD_ACT_AS_TYPE(type) (((type) == GLB_SPI_PAD_ACT_AS_SLAVE) || \ + ((type) == GLB_SPI_PAD_ACT_AS_MASTER)) + +/** @defgroup GLB_PKA_CLK_TYPE + * @{ + */ +#define IS_GLB_PKA_CLK_TYPE(type) (((type) == GLB_PKA_CLK_HCLK) || \ + ((type) == GLB_PKA_CLK_PLL120M)) + +/** @defgroup BMX_ARB_TYPE + * @{ + */ +#define IS_BMX_ARB_TYPE(type) (((type) == BMX_ARB_FIX) || \ + ((type) == BMX_ARB_ROUND_ROBIN) || \ + ((type) == BMX_ARB_RANDOM)) + +/** @defgroup BMX_BUS_ERR_TYPE + * @{ + */ +#define IS_BMX_BUS_ERR_TYPE(type) (((type) == BMX_BUS_ERR_TRUSTZONE_DECODE) || \ + ((type) == BMX_BUS_ERR_ADDR_DECODE)) + +/** @defgroup BMX_ERR_INT_TYPE + * @{ + */ +#define IS_BMX_ERR_INT_TYPE(type) (((type) == BMX_ERR_INT_ERR) || \ + ((type) == BMX_ERR_INT_ALL)) + +/** @defgroup BMX_TO_INT_TYPE + * @{ + */ +#define IS_BMX_TO_INT_TYPE(type) (((type) == BMX_TO_INT_TIMEOUT) || \ + ((type) == BMX_TO_INT_ALL)) + +/** @defgroup GLB_EM_TYPE + * @{ + */ +#define IS_GLB_EM_TYPE(type) (((type) == GLB_EM_0KB) || \ + ((type) == GLB_EM_8KB) || \ + ((type) == GLB_EM_16KB)) + +/** @defgroup GLB_MTIMER_CLK_TYPE + * @{ + */ +#define IS_GLB_MTIMER_CLK_TYPE(type) (((type) == GLB_MTIMER_CLK_BCLK) || \ + ((type) == GLB_MTIMER_CLK_32K)) + +/** @defgroup GLB_ADC_CLK_TYPE + * @{ + */ +#define IS_GLB_ADC_CLK_TYPE(type) (((type) == GLB_ADC_CLK_96M) || \ + ((type) == GLB_ADC_CLK_XCLK)) + +/** @defgroup GLB_DAC_CLK_TYPE + * @{ + */ +#define IS_GLB_DAC_CLK_TYPE(type) (((type) == GLB_DAC_CLK_32M) || \ + ((type) == GLB_DAC_CLK_XCLK)) + +/** @defgroup GLB_DIG_CLK_TYPE + * @{ + */ +#define IS_GLB_DIG_CLK_TYPE(type) (((type) == GLB_DIG_CLK_PLL_32M) || \ + ((type) == GLB_DIG_CLK_XCLK)) + +/** @defgroup GLB_512K_CLK_OUT_TYPE + * @{ + */ +#define IS_GLB_512K_CLK_OUT_TYPE(type) (((type) == GLB_512K_CLK_OUT_512K) || \ + ((type) == GLB_512K_CLK_OUT_256K) || \ + ((type) == GLB_512K_CLK_OUT_128K)) + +/** @defgroup GLB_BT_BANDWIDTH_TYPE + * @{ + */ +#define IS_GLB_BT_BANDWIDTH_TYPE(type) (((type) == GLB_BT_BANDWIDTH_1M) || \ + ((type) == GLB_BT_BANDWIDTH_2M)) + +/** @defgroup GLB_UART_SIG_TYPE + * @{ + */ +#define IS_GLB_UART_SIG_TYPE(type) (((type) == GLB_UART_SIG_0) || \ + ((type) == GLB_UART_SIG_1) || \ + ((type) == GLB_UART_SIG_2) || \ + ((type) == GLB_UART_SIG_3) || \ + ((type) == GLB_UART_SIG_4) || \ + ((type) == GLB_UART_SIG_5) || \ + ((type) == GLB_UART_SIG_6) || \ + ((type) == GLB_UART_SIG_7)) + +/** @defgroup GLB_UART_SIG_FUN_TYPE + * @{ + */ +#define IS_GLB_UART_SIG_FUN_TYPE(type) (((type) == GLB_UART_SIG_FUN_UART0_RTS) || \ + ((type) == GLB_UART_SIG_FUN_UART0_CTS) || \ + ((type) == GLB_UART_SIG_FUN_UART0_TXD) || \ + ((type) == GLB_UART_SIG_FUN_UART0_RXD) || \ + ((type) == GLB_UART_SIG_FUN_UART1_RTS) || \ + ((type) == GLB_UART_SIG_FUN_UART1_CTS) || \ + ((type) == GLB_UART_SIG_FUN_UART1_TXD) || \ + ((type) == GLB_UART_SIG_FUN_UART1_RXD)) + +/** @defgroup GLB_GPIO_REAL_MODE_TYPE + * @{ + */ +#define IS_GLB_GPIO_REAL_MODE_TYPE(type) (((type) == GLB_GPIO_REAL_MODE_REG) || \ + ((type) == GLB_GPIO_REAL_MODE_SDIO) || \ + ((type) == GLB_GPIO_REAL_MODE_RF) || \ + ((type) == GLB_GPIO_REAL_MODE_JTAG) || \ + ((type) == GLB_GPIO_REAL_MODE_CCI)) + +/** @defgroup GLB_GPIO_INT_TRIG_TYPE + * @{ + */ +#define IS_GLB_GPIO_INT_TRIG_TYPE(type) (((type) == GLB_GPIO_INT_TRIG_NEG_PULSE) || \ + ((type) == GLB_GPIO_INT_TRIG_POS_PULSE) || \ + ((type) == GLB_GPIO_INT_TRIG_NEG_LEVEL) || \ + ((type) == GLB_GPIO_INT_TRIG_POS_LEVEL)) + +/** @defgroup GLB_GPIO_INT_CONTROL_TYPE + * @{ + */ +#define IS_GLB_GPIO_INT_CONTROL_TYPE(type) (((type) == GLB_GPIO_INT_CONTROL_SYNC) || \ + ((type) == GLB_GPIO_INT_CONTROL_ASYNC)) + +/** @defgroup GLB_PLL_XTAL_TYPE + * @{ + */ +#define IS_GLB_PLL_XTAL_TYPE(type) (((type) == GLB_PLL_XTAL_NONE) || \ + ((type) == GLB_PLL_XTAL_24M) || \ + ((type) == GLB_PLL_XTAL_32M) || \ + ((type) == GLB_PLL_XTAL_38P4M) || \ + ((type) == GLB_PLL_XTAL_40M) || \ + ((type) == GLB_PLL_XTAL_26M) || \ + ((type) == GLB_PLL_XTAL_RC32M)) + +/** @defgroup GLB_PLL_CLK_TYPE + * @{ + */ +#define IS_GLB_PLL_CLK_TYPE(type) (((type) == GLB_PLL_CLK_480M) || \ + ((type) == GLB_PLL_CLK_240M) || \ + ((type) == GLB_PLL_CLK_192M) || \ + ((type) == GLB_PLL_CLK_160M) || \ + ((type) == GLB_PLL_CLK_120M) || \ + ((type) == GLB_PLL_CLK_96M) || \ + ((type) == GLB_PLL_CLK_80M) || \ + ((type) == GLB_PLL_CLK_48M) || \ + ((type) == GLB_PLL_CLK_32M)) + +/*@} end of group GLB_Public_Constants */ + +/** @defgroup GLB_Public_Macros + * @{ + */ +#define UART_SIG_SWAP_GPIO0_GPIO7 0x01 /* GPIO0-7 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */ +#define UART_SIG_SWAP_GPIO8_GPIO15 0x02 /* GPIO8-15 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */ +#define UART_SIG_SWAP_GPIO16_GPIO22 0x04 /* GPIO16-22 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */ +#define UART_SIG_SWAP_NONE 0x00 /* GPIO0-22 uart_sig[0:7] <- uart_sig[4:7], uart_sig[0:3] */ +#define JTAG_SIG_SWAP_GPIO0_GPIO3 0x01 /* GPIO0-3 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO4_GPIO7 0x02 /* GPIO4-7 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO8_GPIO11 0x04 /* GPIO8-11 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO12_GPIO15 0x08 /* GPIO12-15 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO16_GPIO19 0x10 /* GPIO16-19 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO20_GPIO22 0x20 /* GPIO20-22 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_NONE 0x00 /* GPIO0-22 E21_TMS/E21_TDI/E21_TCK/E21_TDO <- E21_TCK/E21_TDO/E21_TMS/E21_TDI */ + +/*@} end of group GLB_Public_Macros */ + +/** @defgroup GLB_Public_Functions + * @{ + */ +/*----------*/ +#ifndef BFLB_USE_HAL_DRIVER +void BMX_ERR_IRQHandler(void); +void BMX_TO_IRQHandler(void); +void GPIO_INT0_IRQHandler(void); +#endif +/*----------*/ +GLB_ROOT_CLK_Type GLB_Get_Root_CLK_Sel(void); +BL_Err_Type GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv); +uint8_t GLB_Get_BCLK_Div(void); +uint8_t GLB_Get_HCLK_Div(void); +BL_Err_Type Update_SystemCoreClockWith_XTAL(GLB_PLL_XTAL_Type xtalType); +BL_Err_Type GLB_Set_System_CLK(GLB_PLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq); +BL_Err_Type System_Core_Clock_Update_From_RC32M(void); +/*----------*/ +BL_Err_Type GLB_Set_BLE_CLK(uint8_t enable); +BL_Err_Type GLB_Set_WiFi_Core_CLK(uint8_t clkDiv); +BL_Err_Type GLB_Set_WiFi_Encrypt_CLK(uint8_t clkDiv); +BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk); +BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div); +BL_Err_Type GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div); +BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div); +BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, uint8_t div); +BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, uint8_t div); +/*----------*/ +BL_Err_Type GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel); +BL_Err_Type GLB_SW_System_Reset(void); +BL_Err_Type GLB_SW_CPU_Reset(void); +BL_Err_Type GLB_SW_POR_Reset(void); +BL_Err_Type GLB_AHB_Slave1_Reset(BL_AHB_Slave1_Type slave1); +BL_Err_Type GLB_AHB_Slave1_Clock_Gate(uint8_t enable, BL_AHB_Slave1_Type slave1); +/*----------*/ +BL_Err_Type GLB_BMX_Init(BMX_Cfg_Type *BmxCfg); +BL_Err_Type GLB_BMX_Addr_Monitor_Enable(void); +BL_Err_Type GLB_BMX_Addr_Monitor_Disable(void); +BL_Err_Type GLB_BMX_BusErrResponse_Enable(void); +BL_Err_Type GLB_BMX_BusErrResponse_Disable(void); +BL_Sts_Type GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType); +uint32_t GLB_BMX_Get_Err_Addr(void); +BL_Err_Type BMX_ERR_INT_Callback_Install(BMX_ERR_INT_Type intType, intCallback_Type *cbFun); +BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun); +/*----------*/ +BL_Err_Type GLB_Set_OCRAM_Idle(void); +BL_Err_Type GLB_Set_SRAM_RET(uint32_t value); +uint32_t GLB_Get_SRAM_RET(void); +BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value); +uint32_t GLB_Get_SRAM_SLP(void); +BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value); +uint32_t GLB_Get_SRAM_PARM(void); +/*----------*/ +BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType); +/*----------*/ +BL_Err_Type GLB_UART_Sig_Swap_Set(uint8_t swapSel); +BL_Err_Type GLB_JTAG_Sig_Swap_Set(uint8_t swapSel); +BL_Err_Type GLB_Swap_SPI_0_MOSI_With_MISO(BL_Fun_Type newState); +BL_Err_Type GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod); +BL_Err_Type GLB_Select_Internal_Flash(void); +BL_Err_Type GLB_Select_External_Flash(void); +BL_Err_Type GLB_Deswap_Flash_Pin(void); +BL_Err_Type GLB_Swap_Flash_Pin(void); +/*----------*/ +BL_Err_Type GLB_Set_MTimer_CLK(uint8_t enable, GLB_MTIMER_CLK_Type clkSel, uint32_t div); +/*----------*/ +BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div); +BL_Err_Type GLB_Set_DAC_CLK(uint8_t enable, GLB_DAC_CLK_Type clkSel, uint8_t div); +/*----------*/ +BL_Err_Type GLB_Platform_Wakeup_Enable(void); +BL_Err_Type GLB_Platform_Wakeup_Disable(void); +/*----------*/ +BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel); +BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensation, uint8_t div); +BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensation, uint16_t div); +/*----------*/ +BL_Err_Type GLB_Set_BT_Coex_Signal(uint8_t enable, GLB_BT_BANDWIDTH_Type bandWidth, + uint8_t pti, uint8_t channel); +/*----------*/ +BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun); +/*----------*/ +BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio); +BL_Err_Type GLB_IR_LED_Driver_Enable(void); +BL_Err_Type GLB_IR_LED_Driver_Disable(void); +BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias); +/*----------*/ +BL_Err_Type GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg); +BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt); +BL_Err_Type GLB_GPIO_INPUT_Enable(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_Set_PullUp(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_Set_PullDown(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin); +uint8_t GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin); +GLB_GPIO_REAL_MODE_Type GLB_GPIO_Get_Real_Fun(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val); +uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask); +BL_Err_Type GLB_GPIO_IntClear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear); +BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_Set_GPIO_IntMod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod, + GLB_GPIO_INT_TRIG_Type intTrgMod); +GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_IntCtlMod(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void); +BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun); + +/*@} end of group GLB_Public_Functions */ + +/*@} end of group GLB */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_GLB_H__ */ diff --git a/drivers/soc/bl602/bl602_std/include/bl602_gpio.h b/drivers/soc/bl602/bl602_std/include/bl602_gpio.h new file mode 100644 index 00000000..7cc1446c --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/bl602_gpio.h @@ -0,0 +1,444 @@ +/** + + ****************************************************************************** + + * @file bl602_gpio.h + + * @version V1.2 + + * @date 2019-12-14 + + * @brief This file is the description of.IP register + + ****************************************************************************** + + * @attention + + * + + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ + * + + * Redistribution and use in source and binary forms, with or without modification, + + * are permitted provided that the following conditions are met: + + * 1. Redistributions of source code must retain the above copyright notice, + + * this list of conditions and the following disclaimer. + + * 2. Redistributions in binary form must reproduce the above copyright notice, + + * this list of conditions and the following disclaimer in the documentation + + * and/or other materials provided with the distribution. + + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + + * may be used to endorse or promote products derived from this software + + * without specific prior written permission. + + * + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + * + + ****************************************************************************** + + */ + +#ifndef __BL602_GPIO_H__ +#define __BL602_GPIO_H__ + +typedef enum { + GLB_GPIO_PIN_0 = 0, + GLB_GPIO_PIN_1, + GLB_GPIO_PIN_2, + GLB_GPIO_PIN_3, + GLB_GPIO_PIN_4, + GLB_GPIO_PIN_5, + GLB_GPIO_PIN_6, + GLB_GPIO_PIN_7, + GLB_GPIO_PIN_8, + GLB_GPIO_PIN_9, + GLB_GPIO_PIN_10, + GLB_GPIO_PIN_11, + GLB_GPIO_PIN_12, + GLB_GPIO_PIN_13, + GLB_GPIO_PIN_14, + GLB_GPIO_PIN_15, + GLB_GPIO_PIN_16, + GLB_GPIO_PIN_17, + GLB_GPIO_PIN_18, + GLB_GPIO_PIN_19, + GLB_GPIO_PIN_20, + GLB_GPIO_PIN_21, + GLB_GPIO_PIN_22, + GLB_GPIO_PIN_MAX, +} GLB_GPIO_Type; + +#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */ +#define GPIO_MODE_AF ((uint32_t)0x00000002U) /*!< Alternate function */ +#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog function */ +#define GPIO_PULL_UP ((uint32_t)0x00000000U) /*!< GPIO pull up */ +#define GPIO_PULL_DOWN ((uint32_t)0x00000001U) /*!< GPIO pull down */ +#define GPIO_PULL_NONE ((uint32_t)0x00000002U) /*!< GPIO no pull up or down */ + +typedef enum { + GPIO_FUN_SDIO = 1, + GPIO_FUN_FLASH = 2, + GPIO_FUN_SPI = 4, + GPIO_FUN_I2C = 6, + GPIO_FUN_UART = 7, + GPIO_FUN_PWM = 8, + GPIO_FUN_EXT_PA = 9, + GPIO_FUN_ANALOG = 10, + GPIO_FUN_SWGPIO = 11, + GPIO_FUN_GPIO = 11, + GPIO_FUN_JTAG = 14, + GPIO_FUN_UART0_RTS = 0x70, + GPIO_FUN_UART0_CTS = 0x71, + GPIO_FUN_UART0_TX = 0x72, + GPIO_FUN_UART0_RX = 0x73, + GPIO_FUN_UART1_RTS = 0x74, + GPIO_FUN_UART1_CTS = 0x75, + GPIO_FUN_UART1_TX = 0x76, + GPIO_FUN_UART1_RX = 0x77, + GPIO_FUN_GPIO_OUTPUT = 0x80, + GPIO_FUN_GPIO_INPUT = 0x81, + GPIO_FUN_UNUSED = 255, +} GLB_GPIO_FUNC_Type; + +typedef struct +{ + uint8_t gpioPin; + uint8_t gpioFun; + uint8_t gpioMode; + uint8_t pullType; + uint8_t drive; + uint8_t smtCtrl; +} GLB_GPIO_Cfg_Type; + +/* GPIO0 function definition */ +#define GPIO0_FUN_SDIO_CLK 1 +#define GPIO0_FUN_SF_D1 2 +#define GPIO0_FUN_UNUSED3 3 +#define GPIO0_FUN_SPI_MOSI_SPI_MISO 4 +#define GPIO0_FUN_UNUSED5 5 +#define GPIO0_FUN_I2C_SCL 6 +#define GPIO0_FUN_UART_SIG0 7 +#define GPIO0_FUN_PWM_CH0 8 +#define GPIO0_FUN_FEM_GPIO_0 9 +#define GPIO0_FUN_ATEST_IN 10 +#define GPIO0_FUN_SWGPIO_0 11 +#define GPIO0_FUN_E21_TMS 14 +/* GPIO1 function definition */ +#define GPIO1_FUN_SDIO_CMD 1 +#define GPIO1_FUN_SF_D2 2 +#define GPIO1_FUN_UNUSED3 3 +#define GPIO1_FUN_SPI_MISO_SPI_MOSI 4 +#define GPIO1_FUN_UNUSED5 5 +#define GPIO1_FUN_I2C_SDA 6 +#define GPIO1_FUN_UART_SIG1 7 +#define GPIO1_FUN_PWM_CH1 8 +#define GPIO1_FUN_FEM_GPIO_1 9 +#define GPIO1_FUN_ATEST_IP 10 +#define GPIO1_FUN_SWGPIO_1 11 +#define GPIO1_FUN_E21_TDI 14 +/* GPIO2 function definition */ +#define GPIO2_FUN_SDIO_DAT0 1 +#define GPIO2_FUN_SF_D3 2 +#define GPIO2_FUN_UNUSED3 3 +#define GPIO2_FUN_SPI_SS 4 +#define GPIO2_FUN_UNUSED5 5 +#define GPIO2_FUN_I2C_SCL 6 +#define GPIO2_FUN_UART_SIG2 7 +#define GPIO2_FUN_PWM_CH2 8 +#define GPIO2_FUN_FEM_GPIO_2 9 +#define GPIO2_FUN_ATEST_QN 10 +#define GPIO2_FUN_SWGPIO_2 11 +#define GPIO2_FUN_E21_TCK 14 +/* GPIO3 function definition */ +#define GPIO3_FUN_SDIO_DAT1 1 +#define GPIO3_FUN_UNUSED2 2 +#define GPIO3_FUN_UNUSED3 3 +#define GPIO3_FUN_SPI_SCLK 4 +#define GPIO3_FUN_UNUSED5 5 +#define GPIO3_FUN_I2C_SDA 6 +#define GPIO3_FUN_UART_SIG3 7 +#define GPIO3_FUN_PWM_CH3 8 +#define GPIO3_FUN_FEM_GPIO_3 9 +#define GPIO3_FUN_ATEST_QP 10 +#define GPIO3_FUN_SWGPIO_3 11 +#define GPIO3_FUN_E21_TDO 14 +/* GPIO4 function definition */ +#define GPIO4_FUN_SDIO_DAT2 1 +#define GPIO4_FUN_UNUSED2 2 +#define GPIO4_FUN_UNUSED3 3 +#define GPIO4_FUN_SPI_MOSI_SPI_MISO 4 +#define GPIO4_FUN_UNUSED5 5 +#define GPIO4_FUN_I2C_SCL 6 +#define GPIO4_FUN_UART_SIG4 7 +#define GPIO4_FUN_PWM_CH4 8 +#define GPIO4_FUN_FEM_GPIO_0 9 +#define GPIO4_FUN_GPIP_CH1 10 +#define GPIO4_FUN_SWGPIO_4 11 +#define GPIO4_FUN_E21_TMS 14 +/* GPIO5 function definition */ +#define GPIO5_FUN_SDIO_DAT3 1 +#define GPIO5_FUN_UNUSED2 2 +#define GPIO5_FUN_UNUSED3 3 +#define GPIO5_FUN_SPI_MISO_SPI_MOSI 4 +#define GPIO5_FUN_UNUSED5 5 +#define GPIO5_FUN_I2C_SDA 6 +#define GPIO5_FUN_UART_SIG5 7 +#define GPIO5_FUN_PWM_CH0 8 +#define GPIO5_FUN_FEM_GPIO_1 9 +#define GPIO5_FUN_GPIP_CH4 10 +#define GPIO5_FUN_SWGPIO_5 11 +#define GPIO5_FUN_E21_TDI 14 +/* GPIO6 function definition */ +#define GPIO6_FUN_UNUSED1 1 +#define GPIO6_FUN_UNUSED2 2 +#define GPIO6_FUN_UNUSED3 3 +#define GPIO6_FUN_SPI_SS 4 +#define GPIO6_FUN_UNUSED5 5 +#define GPIO6_FUN_I2C_SCL 6 +#define GPIO6_FUN_UART_SIG6 7 +#define GPIO6_FUN_PWM_CH1 8 +#define GPIO6_FUN_FEM_GPIO_2 9 +#define GPIO6_FUN_GPIP_CH5 10 +#define GPIO6_FUN_SWGPIO_6 11 +#define GPIO6_FUN_E21_TCK 14 +/* GPIO7 function definition */ +#define GPIO7_FUN_UNUSED1 1 +#define GPIO7_FUN_UNUSED2 2 +#define GPIO7_FUN_UNUSED3 3 +#define GPIO7_FUN_SPI_SCLK 4 +#define GPIO7_FUN_UNUSED5 5 +#define GPIO7_FUN_I2C_SDA 6 +#define GPIO7_FUN_UART_SIG7 7 +#define GPIO7_FUN_PWM_CH2 8 +#define GPIO7_FUN_FEM_GPIO_3 9 +#define GPIO7_FUN_UNUSED10 10 +#define GPIO7_FUN_SWGPIO_7 11 +#define GPIO7_FUN_E21_TDO 14 +/* GPIO8 function definition */ +#define GPIO8_FUN_UNUSED1 1 +#define GPIO8_FUN_UNUSED2 2 +#define GPIO8_FUN_UNUSED3 3 +#define GPIO8_FUN_SPI_MOSI_SPI_MISO 4 +#define GPIO8_FUN_UNUSED5 5 +#define GPIO8_FUN_I2C_SCL 6 +#define GPIO8_FUN_UART_SIG0 7 +#define GPIO8_FUN_PWM_CH3 8 +#define GPIO8_FUN_FEM_GPIO_0 9 +#define GPIO8_FUN_UNUSED10 10 +#define GPIO8_FUN_SWGPIO_8 11 +#define GPIO8_FUN_E21_TMS 14 +/* GPIO9 function definition */ +#define GPIO9_FUN_UNUSED1 1 +#define GPIO9_FUN_UNUSED2 2 +#define GPIO9_FUN_UNUSED3 3 +#define GPIO9_FUN_SPI_MISO_SPI_MOSI 4 +#define GPIO9_FUN_UNUSED5 5 +#define GPIO9_FUN_I2C_SDA 6 +#define GPIO9_FUN_UART_SIG1 7 +#define GPIO9_FUN_PWM_CH4 8 +#define GPIO9_FUN_FEM_GPIO_1 9 +#define GPIO9_FUN_GPIP_CH6_GPIP_CH7 10 +#define GPIO9_FUN_SWGPIO_9 11 +#define GPIO9_FUN_E21_TDI 14 +/* GPIO10 function definition */ +#define GPIO10_FUN_UNUSED1 1 +#define GPIO10_FUN_UNUSED2 2 +#define GPIO10_FUN_UNUSED3 3 +#define GPIO10_FUN_SPI_SS 4 +#define GPIO10_FUN_UNUSED5 5 +#define GPIO10_FUN_I2C_SCL 6 +#define GPIO10_FUN_UART_SIG2 7 +#define GPIO10_FUN_PWM_CH0 8 +#define GPIO10_FUN_FEM_GPIO_2 9 +#define GPIO10_FUN_MICBIAS_GPIP_CH8_GPIP_CH9 10 +#define GPIO10_FUN_SWGPIO_10 11 +#define GPIO10_FUN_E21_TCK 14 +/* GPIO11 function definition */ +#define GPIO11_FUN_UNUSED1 1 +#define GPIO11_FUN_UNUSED2 2 +#define GPIO11_FUN_UNUSED3 3 +#define GPIO11_FUN_SPI_SCLK 4 +#define GPIO11_FUN_UNUSED5 5 +#define GPIO11_FUN_I2C_SDA 6 +#define GPIO11_FUN_UART_SIG3 7 +#define GPIO11_FUN_PWM_CH1 8 +#define GPIO11_FUN_FEM_GPIO_3 9 +#define GPIO11_FUN_IRLED_OUT_GPIP_CH10 10 +#define GPIO11_FUN_SWGPIO_11 11 +#define GPIO11_FUN_E21_TDO 14 +/* GPIO12 function definition */ +#define GPIO12_FUN_UNUSED1 1 +#define GPIO12_FUN_UNUSED2 2 +#define GPIO12_FUN_UNUSED3 3 +#define GPIO12_FUN_SPI_MOSI_SPI_MISO 4 +#define GPIO12_FUN_UNUSED5 5 +#define GPIO12_FUN_I2C_SCL 6 +#define GPIO12_FUN_UART_SIG4 7 +#define GPIO12_FUN_PWM_CH2 8 +#define GPIO12_FUN_FEM_GPIO_0 9 +#define GPIO12_FUN_GPIP_CH0_GPADC_VREF_EXT 10 +#define GPIO12_FUN_SWGPIO_12 11 +#define GPIO12_FUN_E21_TMS 14 +/* GPIO13 function definition */ +#define GPIO13_FUN_UNUSED1 1 +#define GPIO13_FUN_UNUSED2 2 +#define GPIO13_FUN_UNUSED3 3 +#define GPIO13_FUN_SPI_MISO_SPI_MOSI 4 +#define GPIO13_FUN_UNUSED5 5 +#define GPIO13_FUN_I2C_SDA 6 +#define GPIO13_FUN_UART_SIG5 7 +#define GPIO13_FUN_PWM_CH3 8 +#define GPIO13_FUN_FEM_GPIO_1 9 +#define GPIO13_FUN_GPIP_CH3 10 +#define GPIO13_FUN_SWGPIO_13 11 +#define GPIO13_FUN_E21_TDI 14 +/* GPIO14 function definition */ +#define GPIO14_FUN_UNUSED1 1 +#define GPIO14_FUN_UNUSED2 2 +#define GPIO14_FUN_UNUSED3 3 +#define GPIO14_FUN_SPI_SS 4 +#define GPIO14_FUN_UNUSED5 5 +#define GPIO14_FUN_I2C_SCL 6 +#define GPIO14_FUN_UART_SIG6 7 +#define GPIO14_FUN_PWM_CH4 8 +#define GPIO14_FUN_FEM_GPIO_2 9 +#define GPIO14_FUN_GPIP_CH2 10 +#define GPIO14_FUN_SWGPIO_14 11 +#define GPIO14_FUN_E21_TCK 14 +/* GPIO15 function definition */ +#define GPIO15_FUN_UNUSED1 1 +#define GPIO15_FUN_UNUSED2 2 +#define GPIO15_FUN_UNUSED3 3 +#define GPIO15_FUN_SPI_SCLK 4 +#define GPIO15_FUN_UNUSED5 5 +#define GPIO15_FUN_I2C_SDA 6 +#define GPIO15_FUN_UART_SIG7 7 +#define GPIO15_FUN_PWM_CH0 8 +#define GPIO15_FUN_FEM_GPIO_3 9 +#define GPIO15_FUN_PSW_IRRCV_OUT_GPIP_CH11 10 +#define GPIO15_FUN_SWGPIO_15 11 +#define GPIO15_FUN_E21_TDO 14 +/* GPIO16 function definition */ +#define GPIO16_FUN_UNUSED1 1 +#define GPIO16_FUN_UNUSED2 2 +#define GPIO16_FUN_UNUSED3 3 +#define GPIO16_FUN_SPI_MOSI_SPI_MISO 4 +#define GPIO16_FUN_UNUSED5 5 +#define GPIO16_FUN_I2C_SCL 6 +#define GPIO16_FUN_UART_SIG0 7 +#define GPIO16_FUN_PWM_CH1 8 +#define GPIO16_FUN_FEM_GPIO_0 9 +#define GPIO16_FUN_UNUSED10 10 +#define GPIO16_FUN_SWGPIO_16 11 +#define GPIO16_FUN_E21_TMS 14 +/* GPIO17 function definition */ +#define GPIO17_FUN_UNUSED1 1 +#define GPIO17_FUN_SF_D3 2 +#define GPIO17_FUN_UNUSED3 3 +#define GPIO17_FUN_SPI_MISO_SPI_MOSI 4 +#define GPIO17_FUN_UNUSED5 5 +#define GPIO17_FUN_I2C_SDA 6 +#define GPIO17_FUN_UART_SIG1 7 +#define GPIO17_FUN_PWM_CH2 8 +#define GPIO17_FUN_FEM_GPIO_1 9 +#define GPIO17_FUN_PMIP_DC_TP_OUT 10 +#define GPIO17_FUN_SWGPIO_17 11 +#define GPIO17_FUN_E21_TDI 14 +/* GPIO18 function definition */ +#define GPIO18_FUN_UNUSED1 1 +#define GPIO18_FUN_SF_D2 2 +#define GPIO18_FUN_UNUSED3 3 +#define GPIO18_FUN_SPI_SS 4 +#define GPIO18_FUN_UNUSED5 5 +#define GPIO18_FUN_I2C_SCL 6 +#define GPIO18_FUN_UART_SIG2 7 +#define GPIO18_FUN_PWM_CH3 8 +#define GPIO18_FUN_FEM_GPIO_2 9 +#define GPIO18_FUN_UNUSED10 10 +#define GPIO18_FUN_SWGPIO_18 11 +#define GPIO18_FUN_E21_TCK 14 +/* GPIO19 function definition */ +#define GPIO19_FUN_UNUSED1 1 +#define GPIO19_FUN_SF_D1 2 +#define GPIO19_FUN_UNUSED3 3 +#define GPIO19_FUN_SPI_SCLK 4 +#define GPIO19_FUN_UNUSED5 5 +#define GPIO19_FUN_I2C_SDA 6 +#define GPIO19_FUN_UART_SIG3 7 +#define GPIO19_FUN_PWM_CH4 8 +#define GPIO19_FUN_FEM_GPIO_3 9 +#define GPIO19_FUN_UNUSED10 10 +#define GPIO19_FUN_SWGPIO_19 11 +#define GPIO19_FUN_E21_TDO 14 +/* GPIO20 function definition */ +#define GPIO20_FUN_UNUSED1 1 +#define GPIO20_FUN_SF_D0 2 +#define GPIO20_FUN_UNUSED3 3 +#define GPIO20_FUN_SPI_MOSI_SPI_MISO 4 +#define GPIO20_FUN_UNUSED5 5 +#define GPIO20_FUN_I2C_SCL 6 +#define GPIO20_FUN_UART_SIG4 7 +#define GPIO20_FUN_PWM_CH0 8 +#define GPIO20_FUN_FEM_GPIO_0 9 +#define GPIO20_FUN_UNUSED10 10 +#define GPIO20_FUN_SWGPIO_20 11 +#define GPIO20_FUN_E21_TMS 14 +/* GPIO21 function definition */ +#define GPIO21_FUN_UNUSED1 1 +#define GPIO21_FUN_SF_CS 2 +#define GPIO21_FUN_UNUSED3 3 +#define GPIO21_FUN_SPI_MISO_SPI_MOSI 4 +#define GPIO21_FUN_UNUSED5 5 +#define GPIO21_FUN_I2C_SDA 6 +#define GPIO21_FUN_UART_SIG5 7 +#define GPIO21_FUN_PWM_CH1 8 +#define GPIO21_FUN_FEM_GPIO_1 9 +#define GPIO21_FUN_UNUSED10 10 +#define GPIO21_FUN_SWGPIO_21 11 +#define GPIO21_FUN_E21_TDI 14 +/* GPIO22 function definition */ +#define GPIO22_FUN_UNUSED1 1 +#define GPIO22_FUN_SF_CLK_OUT 2 +#define GPIO22_FUN_UNUSED3 3 +#define GPIO22_FUN_SPI_SS 4 +#define GPIO22_FUN_UNUSED5 5 +#define GPIO22_FUN_I2C_SCL 6 +#define GPIO22_FUN_UART_SIG6 7 +#define GPIO22_FUN_PWM_CH2 8 +#define GPIO22_FUN_FEM_GPIO_2 9 +#define GPIO22_FUN_UNUSED10 10 +#define GPIO22_FUN_SWGPIO_22 11 +#define GPIO22_FUN_E21_TCK 14 + +#endif /*__BL602_GPIO_H__ */ diff --git a/drivers/soc/bl602/bl602_std/include/bl602_hbn.h b/drivers/soc/bl602/bl602_std/include/bl602_hbn.h new file mode 100644 index 00000000..8b31dad4 --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/bl602_hbn.h @@ -0,0 +1,497 @@ +/** + ****************************************************************************** + * @file bl602_hbn.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_HBN_H__ +#define __BL602_HBN_H__ + +#include "hbn_reg.h" +#include "bl602_aon.h" +#include "bl602_sflash.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup HBN + * @{ + */ + +/** @defgroup HBN_Public_Types + * @{ + */ + +/** + * @brief HBN PIR interrupt configuration type definition + */ +typedef struct +{ + BL_Fun_Type lowIntEn; /*!< Low will trigger interrupt */ + BL_Fun_Type highIntEn; /*!< High will trigger interrupt */ +} HBN_PIR_INT_CFG_Type; + +/** + * @brief HBN PIR low pass filter type definition + */ +typedef enum { + HBN_PIR_LPF_DIV1, /*!< HBN PIR lpf div 1 */ + HBN_PIR_LPF_DIV2, /*!< HBN PIR lpf div 2 */ +} HBN_PIR_LPF_Type; + +/** + * @brief HBN PIR high pass filter type definition + */ +typedef enum { + HBN_PIR_HPF_METHOD0, /*!< HBN PIR hpf calc method 0, 1-z^-1 */ + HBN_PIR_HPF_METHOD1, /*!< HBN PIR hpf calc method 1, 1-z^-2 */ + HBN_PIR_HPF_METHOD2, /*!< HBN PIR hpf calc method 2, 1-z^-3 */ +} HBN_PIR_HPF_Type; + +/** + * @brief HBN BOR threshold type definition + */ +typedef enum { + HBN_BOR_THRES_2P0V, /*!< BOR threshold 2.0V */ + HBN_BOR_THRES_2P4V, /*!< BOR threshold 2.4V */ +} HBN_BOR_THRES_Type; + +/** + * @brief HBN BOR mode type definition + */ +typedef enum { + HBN_BOR_MODE_POR_INDEPENDENT, /*!< POR is independent of BOR */ + HBN_BOR_MODE_POR_RELEVANT, /*!< POR is relevant to BOR */ +} HBN_BOR_MODE_Type; + +/** + * @brief HBN 32K clock type definition + */ +typedef enum { + HBN_32K_RC = 0, /*!< HBN use rc 32k */ + HBN_32K_XTAL, /*!< HBN use xtal 32k */ + HBN_32K_DIG = 3, /*!< HBN use dig 32k */ +} HBN_32K_CLK_Type; + +/** + * @brief HBN xclk clock type definition + */ +typedef enum { + HBN_XCLK_CLK_RC32M, /*!< use RC32M as xclk clock */ + HBN_XCLK_CLK_XTAL, /*!< use XTAL as xclk clock */ +} HBN_XCLK_CLK_Type; + +/** + * @brief HBN root clock type definition + */ +typedef enum { + HBN_ROOT_CLK_RC32M, /*!< use RC32M as root clock */ + HBN_ROOT_CLK_XTAL, /*!< use XTAL as root clock */ + HBN_ROOT_CLK_PLL, /*!< use PLL as root clock */ +} HBN_ROOT_CLK_Type; + +/** + * @brief HBN UART clock type definition + */ +typedef enum { + HBN_UART_CLK_FCLK = 0, /*!< Select FCLK as UART clock */ + HBN_UART_CLK_160M, /*!< Select 160M as UART clock */ +} HBN_UART_CLK_Type; + +/** + * @brief HBN RTC interrupt delay type definition + */ +typedef enum { + HBN_RTC_INT_DELAY_32T = 0, /*!< HBN RTC interrupt delay 32T */ + HBN_RTC_INT_DELAY_0T = 1, /*!< HBN RTC interrupt delay 0T */ +} HBN_RTC_INT_Delay_Type; + +/** + * @brief HBN interrupt type definition + */ +typedef enum { + HBN_INT_GPIO7 = 0, /*!< HBN interrupt type: GPIO7 */ + HBN_INT_GPIO8 = 1, /*!< HBN interrupt type: GPIO8 */ + HBN_INT_RTC = 16, /*!< HBN interrupt type: RTC */ + HBN_INT_PIR = 17, /*!< HBN interrupt type: PIR */ + HBN_INT_BOR = 18, /*!< HBN interrupt type: BOR */ + HBN_INT_ACOMP0 = 20, /*!< HBN interrupt type: ACOMP0 */ + HBN_INT_ACOMP1 = 22, /*!< HBN interrupt type: ACOMP1 */ +} HBN_INT_Type; + +/** + * @brief HBN acomp interrupt type definition + */ +typedef enum { + HBN_ACOMP_INT_EDGE_POSEDGE = 0, /*!< HBN acomp interrupt edge posedge */ + HBN_ACOMP_INT_EDGE_NEGEDGE = 1, /*!< HBN acomp interrupt edge negedge */ +} HBN_ACOMP_INT_EDGE_Type; + +/** + * @brief HBN GPIO interrupt trigger type definition + */ +typedef enum { + HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE, /*!< HBN GPIO INT trigger type: sync falling edge trigger */ + HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE, /*!< HBN GPIO INT trigger type: sync rising edge trigger */ + HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL, /*!< HBN GPIO INT trigger type: sync low level trigger */ + HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL, /*!< HBN GPIO INT trigger type: sync high level trigger */ + HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE, /*!< HBN GPIO INT trigger type: async falling edge trigger */ + HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE, /*!< HBN GPIO INT trigger type: async rising edge trigger */ + HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL, /*!< HBN GPIO INT trigger type: async low level trigger */ + HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL, /*!< HBN GPIO INT trigger type: async high level trigger */ +} HBN_GPIO_INT_Trigger_Type; + +/** + * @brief HBN OUT0 interrupt type definition + */ +typedef enum { + HBN_OUT0_INT_GPIO7 = 0, /*!< HBN out 0 interrupt type: GPIO7 */ + HBN_OUT0_INT_GPIO8, /*!< HBN out 0 interrupt type: GPIO8 */ + HBN_OUT0_INT_RTC, /*!< HBN out 0 interrupt type: RTC */ +} HBN_OUT0_INT_Type; + +/** + * @brief HBN OUT0 interrupt type definition + */ +typedef enum { + HBN_OUT1_INT_PIR, /*!< HBN out 1 interrupt type: PIR */ + HBN_OUT1_INT_BOR, /*!< HBN out 1 interrupt type: BOR */ + HBN_OUT1_INT_ACOMP0, /*!< HBN out 1 interrupt type: ACOMP0 */ + HBN_OUT1_INT_ACOMP1, /*!< HBN out 1 interrupt type: ACOMP1 */ +} HBN_OUT1_INT_Type; + +/** + * @brief HBN LDO level type definition + */ +typedef enum { + HBN_LDO_LEVEL_0P60V = 0, /*!< HBN LDO voltage 0.60V */ + HBN_LDO_LEVEL_0P65V = 1, /*!< HBN LDO voltage 0.65V */ + HBN_LDO_LEVEL_0P70V = 2, /*!< HBN LDO voltage 0.70V */ + HBN_LDO_LEVEL_0P75V = 3, /*!< HBN LDO voltage 0.75V */ + HBN_LDO_LEVEL_0P80V = 4, /*!< HBN LDO voltage 0.80V */ + HBN_LDO_LEVEL_0P85V = 5, /*!< HBN LDO voltage 0.85V */ + HBN_LDO_LEVEL_0P90V = 6, /*!< HBN LDO voltage 0.90V */ + HBN_LDO_LEVEL_0P95V = 7, /*!< HBN LDO voltage 0.95V */ + HBN_LDO_LEVEL_1P00V = 8, /*!< HBN LDO voltage 1.00V */ + HBN_LDO_LEVEL_1P05V = 9, /*!< HBN LDO voltage 1.05V */ + HBN_LDO_LEVEL_1P10V = 10, /*!< HBN LDO voltage 1.10V */ + HBN_LDO_LEVEL_1P15V = 11, /*!< HBN LDO voltage 1.15V */ + HBN_LDO_LEVEL_1P20V = 12, /*!< HBN LDO voltage 1.20V */ + HBN_LDO_LEVEL_1P25V = 13, /*!< HBN LDO voltage 1.25V */ + HBN_LDO_LEVEL_1P30V = 14, /*!< HBN LDO voltage 1.30V */ + HBN_LDO_LEVEL_1P35V = 15, /*!< HBN LDO voltage 1.35V */ +} HBN_LDO_LEVEL_Type; + +/** + * @brief HBN level type definition + */ +typedef enum { + HBN_LEVEL_0, /*!< HBN pd_core */ + HBN_LEVEL_1, /*!< HBN pd_aon_hbncore + pd_core */ + HBN_LEVEL_2, /*!< HBN pd_aon_hbnrtc + pd_aon_hbncore + pd_core */ + HBN_LEVEL_3, /*!< HBN pd_aon_hbnrtc + pd_aon_hbncore + pd_core */ +} HBN_LEVEL_Type; + +/** + * @brief HBN BOR configuration type definition + */ +typedef struct +{ + uint8_t enableBor; /*!< Enable BOR or not */ + uint8_t enableBorInt; /*!< Enable BOR interrupt or not */ + uint8_t borThreshold; /*!< BOR threshold */ + uint8_t enablePorInBor; /*!< Enable POR when BOR occure or not */ +} HBN_BOR_CFG_Type; + +/** + * @brief HBN APP configuration type definition + */ +typedef struct +{ + uint8_t useXtal32k; /*!< Whether use xtal 32K as 32K clock source,otherwise use rc32k */ + uint32_t sleepTime; /*!< HBN sleep time */ + uint8_t gpioWakeupSrc; /*!< GPIO Wakeup source */ + HBN_GPIO_INT_Trigger_Type gpioTrigType; /*!< GPIO Triger type */ + SPI_Flash_Cfg_Type *flashCfg; /*!< Flash config pointer, used when power down flash */ + HBN_LEVEL_Type hbnLevel; /*!< HBN level */ + HBN_LDO_LEVEL_Type ldoLevel; /*!< LDO level */ +} HBN_APP_CFG_Type; + +/*@} end of group HBN_Public_Types */ + +/** @defgroup HBN_Public_Constants + * @{ + */ + +/** @defgroup HBN_PIR_LPF_TYPE + * @{ + */ +#define IS_HBN_PIR_LPF_TYPE(type) (((type) == HBN_PIR_LPF_DIV1) || \ + ((type) == HBN_PIR_LPF_DIV2)) + +/** @defgroup HBN_PIR_HPF_TYPE + * @{ + */ +#define IS_HBN_PIR_HPF_TYPE(type) (((type) == HBN_PIR_HPF_METHOD0) || \ + ((type) == HBN_PIR_HPF_METHOD1) || \ + ((type) == HBN_PIR_HPF_METHOD2)) + +/** @defgroup HBN_BOR_THRES_TYPE + * @{ + */ +#define IS_HBN_BOR_THRES_TYPE(type) (((type) == HBN_BOR_THRES_2P0V) || \ + ((type) == HBN_BOR_THRES_2P4V)) + +/** @defgroup HBN_BOR_MODE_TYPE + * @{ + */ +#define IS_HBN_BOR_MODE_TYPE(type) (((type) == HBN_BOR_MODE_POR_INDEPENDENT) || \ + ((type) == HBN_BOR_MODE_POR_RELEVANT)) + +/** @defgroup HBN_32K_CLK_TYPE + * @{ + */ +#define IS_HBN_32K_CLK_TYPE(type) (((type) == HBN_32K_RC) || \ + ((type) == HBN_32K_XTAL) || \ + ((type) == HBN_32K_DIG)) + +/** @defgroup HBN_XCLK_CLK_TYPE + * @{ + */ +#define IS_HBN_XCLK_CLK_TYPE(type) (((type) == HBN_XCLK_CLK_RC32M) || \ + ((type) == HBN_XCLK_CLK_XTAL)) + +/** @defgroup HBN_ROOT_CLK_TYPE + * @{ + */ +#define IS_HBN_ROOT_CLK_TYPE(type) (((type) == HBN_ROOT_CLK_RC32M) || \ + ((type) == HBN_ROOT_CLK_XTAL) || \ + ((type) == HBN_ROOT_CLK_PLL)) + +/** @defgroup HBN_UART_CLK_TYPE + * @{ + */ +#define IS_HBN_UART_CLK_TYPE(type) (((type) == HBN_UART_CLK_FCLK) || \ + ((type) == HBN_UART_CLK_160M)) + +/** @defgroup HBN_RTC_INT_DELAY_TYPE + * @{ + */ +#define IS_HBN_RTC_INT_DELAY_TYPE(type) (((type) == HBN_RTC_INT_DELAY_32T) || \ + ((type) == HBN_RTC_INT_DELAY_0T)) + +/** @defgroup HBN_INT_TYPE + * @{ + */ +#define IS_HBN_INT_TYPE(type) (((type) == HBN_INT_GPIO7) || \ + ((type) == HBN_INT_GPIO8) || \ + ((type) == HBN_INT_RTC) || \ + ((type) == HBN_INT_PIR) || \ + ((type) == HBN_INT_BOR) || \ + ((type) == HBN_INT_ACOMP0) || \ + ((type) == HBN_INT_ACOMP1)) + +/** @defgroup HBN_ACOMP_INT_EDGE_TYPE + * @{ + */ +#define IS_HBN_ACOMP_INT_EDGE_TYPE(type) (((type) == HBN_ACOMP_INT_EDGE_POSEDGE) || \ + ((type) == HBN_ACOMP_INT_EDGE_NEGEDGE)) + +/** @defgroup HBN_GPIO_INT_TRIGGER_TYPE + * @{ + */ +#define IS_HBN_GPIO_INT_TRIGGER_TYPE(type) (((type) == HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) || \ + ((type) == HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) || \ + ((type) == HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) || \ + ((type) == HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) || \ + ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \ + ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) || \ + ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) || \ + ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL)) + +/** @defgroup HBN_OUT0_INT_TYPE + * @{ + */ +#define IS_HBN_OUT0_INT_TYPE(type) (((type) == HBN_OUT0_INT_GPIO7) || \ + ((type) == HBN_OUT0_INT_GPIO8) || \ + ((type) == HBN_OUT0_INT_RTC)) + +/** @defgroup HBN_OUT1_INT_TYPE + * @{ + */ +#define IS_HBN_OUT1_INT_TYPE(type) (((type) == HBN_OUT1_INT_PIR) || \ + ((type) == HBN_OUT1_INT_BOR) || \ + ((type) == HBN_OUT1_INT_ACOMP0) || \ + ((type) == HBN_OUT1_INT_ACOMP1)) + +/** @defgroup HBN_LDO_LEVEL_TYPE + * @{ + */ +#define IS_HBN_LDO_LEVEL_TYPE(type) (((type) == HBN_LDO_LEVEL_0P60V) || \ + ((type) == HBN_LDO_LEVEL_0P65V) || \ + ((type) == HBN_LDO_LEVEL_0P70V) || \ + ((type) == HBN_LDO_LEVEL_0P75V) || \ + ((type) == HBN_LDO_LEVEL_0P80V) || \ + ((type) == HBN_LDO_LEVEL_0P85V) || \ + ((type) == HBN_LDO_LEVEL_0P90V) || \ + ((type) == HBN_LDO_LEVEL_0P95V) || \ + ((type) == HBN_LDO_LEVEL_1P00V) || \ + ((type) == HBN_LDO_LEVEL_1P05V) || \ + ((type) == HBN_LDO_LEVEL_1P10V) || \ + ((type) == HBN_LDO_LEVEL_1P15V) || \ + ((type) == HBN_LDO_LEVEL_1P20V) || \ + ((type) == HBN_LDO_LEVEL_1P25V) || \ + ((type) == HBN_LDO_LEVEL_1P30V) || \ + ((type) == HBN_LDO_LEVEL_1P35V)) + +/** @defgroup HBN_LEVEL_TYPE + * @{ + */ +#define IS_HBN_LEVEL_TYPE(type) (((type) == HBN_LEVEL_0) || \ + ((type) == HBN_LEVEL_1) || \ + ((type) == HBN_LEVEL_2) || \ + ((type) == HBN_LEVEL_3)) + +/*@} end of group HBN_Public_Constants */ + +/** @defgroup HBN_Public_Macros + * @{ + */ +#define HBN_RAM_SIZE (4 * 1024) +#define HBN_RTC_COMP_BIT0_39 0x01 +#define HBN_RTC_COMP_BIT0_23 0x02 +#define HBN_RTC_COMP_BIT13_39 0x04 +#define HBN_STATUS_ENTER_FLAG 0x4e424845 +#define HBN_STATUS_WAKEUP_FLAG 0x4e424857 +#define HBN_WAKEUP_GPIO_NONE 0x00 +#define HBN_WAKEUP_GPIO_7 0x01 +#define HBN_WAKEUP_GPIO_8 0x02 +#define HBN_WAKEUP_GPIO_ALL 0x03 + +/*@} end of group HBN_Public_Macros */ + +/** @defgroup HBN_Public_Functions + * @{ + */ +/*----------*/ +#ifndef BFLB_USE_HAL_DRIVER +void HBN_OUT0_IRQHandler(void); +void HBN_OUT1_IRQHandler(void); +#endif +/*----------*/ +void HBN_Mode_Enter_Ext(HBN_APP_CFG_Type *cfg); +void HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg); +void HBN_Enable_Ext(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel); +BL_Err_Type HBN_Reset(void); +BL_Err_Type HBN_App_Reset(uint8_t npXtalType, uint8_t bclkDiv, uint8_t apXtalType, uint8_t fclkDiv); +BL_Err_Type HBN_Disable(void); +/*----------*/ +BL_Err_Type HBN_PIR_Enable(void); +BL_Err_Type HBN_PIR_Disable(void); +BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg); +BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf); +BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf); +BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold); +uint16_t HBN_Get_PIR_Threshold(void); +BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval); +uint16_t HBN_Get_PIR_Interval(void); +/*----------*/ +BL_Sts_Type HBN_Get_BOR_OUT_State(void); +BL_Err_Type HBN_Set_BOR_Config(uint8_t enable, HBN_BOR_THRES_Type threshold, HBN_BOR_MODE_Type mode); +/*----------*/ +BL_Err_Type HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel); +BL_Err_Type HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel); +BL_Err_Type HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel); +BL_Err_Type HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel); +/*----------*/ +BL_Err_Type HBN_32K_Sel(HBN_32K_CLK_Type clkType); +BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel); +BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk); +HBN_ROOT_CLK_Type HBN_Get_Root_CLK_Sel(void); +BL_Err_Type HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk); +/*----------*/ +BL_Err_Type HBN_Set_HRAM_slp(void); +BL_Err_Type HBN_Set_HRAM_Ret(void); +/*----------*/ +uint32_t HBN_Get_Status_Flag(void); +BL_Err_Type HBN_Set_Status_Flag(uint32_t flag); +uint32_t HBN_Get_Wakeup_Addr(void); +BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr); +/*----------*/ +BL_Err_Type HBN_Clear_RTC_Counter(void); +BL_Err_Type HBN_Enable_RTC_Counter(void); +BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode); +BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh); +BL_Err_Type HBN_Clear_RTC_INT(void); +/*----------*/ +BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType); +BL_Err_Type HBN_GPIO_INT_Disable(void); +BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType); +uint8_t HBN_Get_Pin_Wakeup_Mode(void); +BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType); +BL_Err_Type HBN_Hw_Pu_Pd_Cfg(uint8_t enable); +BL_Err_Type HBN_Aon_Pad_IeSmt_Cfg(uint8_t padCfg); +BL_Err_Type HBN_Pin_WakeUp_Mask(uint8_t maskVal); +/*----------*/ +BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge); +BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge); +BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge); +BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge); +/*----------*/ +BL_Err_Type HBN_Enable_BOR_IRQ(void); +BL_Err_Type HBN_Disable_BOR_IRQ(void); +/*----------*/ +BL_Err_Type HBN_Out0_IRQHandler_Install(void); +BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType, intCallback_Type *cbFun); +BL_Err_Type HBN_Out1_IRQHandler_Install(void); +BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType, intCallback_Type *cbFun); +/*----------*/ +BL_Err_Type HBN_GPIO7_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type iesmtEn, + BL_Fun_Type dlyEn, uint8_t dlySec); +/*----------*/ +BL_Err_Type HBN_Power_On_Xtal_32K(void); +BL_Err_Type HBN_Power_Off_Xtal_32K(void); +BL_Err_Type HBN_Power_On_RC32K(void); +BL_Err_Type HBN_Power_Off_RC32K(void); +BL_Err_Type HBN_Trim_RC32K(void); +BL_Err_Type HBN_Set_Embedded_Flash_Pullup(uint8_t enable); +BL_Err_Type HBN_Set_BOR_Cfg(HBN_BOR_CFG_Type *cfg); + +/*@} end of group HBN_Public_Functions */ + +/*@} end of group HBN */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_HBN_H__ */ diff --git a/drivers/soc/bl602/bl602_std/include/bl602_pds.h b/drivers/soc/bl602/bl602_std/include/bl602_pds.h new file mode 100644 index 00000000..f6b8ccd0 --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/bl602_pds.h @@ -0,0 +1,502 @@ +/** + ****************************************************************************** + * @file bl602_pds.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_PDS_H__ +#define __BL602_PDS_H__ + +#include "pds_reg.h" +#include "bl602_ef_ctrl.h" +#include "bl602_aon.h" +#include "bl602_hbn.h" +#include "bl602_sflash.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup PDS + * @{ + */ + +/** @defgroup PDS_Public_Types + * @{ + */ + +/** + * @brief PDS LDO level type definition + */ +typedef enum { + PDS_LDO_LEVEL_0P60V = 0, /*!< PDS LDO voltage 0.60V */ + PDS_LDO_LEVEL_0P65V = 1, /*!< PDS LDO voltage 0.65V */ + PDS_LDO_LEVEL_0P70V = 2, /*!< PDS LDO voltage 0.70V */ + PDS_LDO_LEVEL_0P75V = 3, /*!< PDS LDO voltage 0.75V */ + PDS_LDO_LEVEL_0P80V = 4, /*!< PDS LDO voltage 0.80V */ + PDS_LDO_LEVEL_0P85V = 5, /*!< PDS LDO voltage 0.85V */ + PDS_LDO_LEVEL_0P90V = 6, /*!< PDS LDO voltage 0.90V */ + PDS_LDO_LEVEL_0P95V = 7, /*!< PDS LDO voltage 0.95V */ + PDS_LDO_LEVEL_1P00V = 8, /*!< PDS LDO voltage 1.00V */ + PDS_LDO_LEVEL_1P05V = 9, /*!< PDS LDO voltage 1.05V */ + PDS_LDO_LEVEL_1P10V = 10, /*!< PDS LDO voltage 1.10V */ + PDS_LDO_LEVEL_1P15V = 11, /*!< PDS LDO voltage 1.15V */ + PDS_LDO_LEVEL_1P20V = 12, /*!< PDS LDO voltage 1.20V */ + PDS_LDO_LEVEL_1P25V = 13, /*!< PDS LDO voltage 1.25V */ + PDS_LDO_LEVEL_1P30V = 14, /*!< PDS LDO voltage 1.30V */ + PDS_LDO_LEVEL_1P35V = 15, /*!< PDS LDO voltage 1.35V */ +} PDS_LDO_LEVEL_Type; + +/** + * @brief PDS configuration type definition + */ +typedef struct +{ + uint32_t pdsStart : 1; /*!< [0]PDS Start */ + uint32_t sleepForever : 1; /*!< [1]PDS sleep forever */ + uint32_t xtalForceOff : 1; /*!< [2]Power off xtal force */ + uint32_t saveWiFiState : 1; /*!< [3]Save WIFI State Before Enter PDS */ + uint32_t dcdc18Off : 1; /*!< [4]power down dcdc18 during PDS */ + uint32_t bgSysOff : 1; /*!< [5]power down bg_sys during PDS */ + uint32_t rsv6_7 : 2; /*!< [7:6]reserve */ + uint32_t clkOff : 1; /*!< [8]gate clock during PDS (each pwr domain has its own control) */ + uint32_t memStby : 1; /*!< [9]mem_stby during PDS (each power domain can has its own control) */ + uint32_t rsv10 : 1; /*!< [10]reserve */ + uint32_t isolation : 1; /*!< [11]Isolation during PDS (each power domain can has its own control) */ + uint32_t waitXtalRdy : 1; /*!< [12]wait XTAL Ready during before PDS Interrupt */ + uint32_t pdsPwrOff : 1; /*!< [13]Power off during PDS (each power domain can has its own control) */ + uint32_t xtalOff : 1; /*!< [14]xtal power down during PDS */ + uint32_t socEnbForceOn : 1; /*!< [15]pds_soc_enb always active */ + uint32_t pdsRstSocEn : 1; /*!< [16]pds_rst controlled by PDS */ + uint32_t pdsRC32mOn : 1; /*!< [17]RC32M always on or RC32M on/off controlled by PDS state */ + uint32_t pdsLdoVselEn : 1; /*!< [18]PDS "SLEEP" control LDO voltage enable */ + uint32_t rsv19_20 : 2; /*!< [20:19]reserve */ + uint32_t wfiMask : 1; /*!< [21]pds start condition mask np_wfi */ + uint32_t ldo11Off : 1; /*!< [22]power down ldo11 during PDS */ + uint32_t rsv23 : 1; /*!< [23]reserve */ + uint32_t pdsLdoVol : 4; /*!< [27:24]LDO voltage value in PDS mode */ + uint32_t pdsCtlRfSel : 2; /*!< [29:28]select the way RF controlled by PDS */ + uint32_t pdsCtlPllSel : 2; /*!< [31:30]select the way PLL controlled by PDS */ +} PDS_CTL_Type; + +/** + * @brief PDS force configuration type definition + */ +typedef struct +{ + uint32_t cpuPwrOff : 1; /*!< [0] */ + uint32_t cpuRst : 1; /*!< [1] */ + uint32_t cpuMemStby : 1; /*!< [2] */ + uint32_t cpuGateClk : 1; /*!< [3] */ + uint32_t rsv4_11 : 8; /*!< [11:4]reserve */ + uint32_t WbPwrOff : 1; /*!< [12] */ + uint32_t WbRst : 1; /*!< [13] */ + uint32_t WbMemStby : 1; /*!< [14] */ + uint32_t WbGateClk : 1; /*!< [15] */ + uint32_t rsv16_23 : 8; /*!< [23:16]reserve */ + uint32_t MiscPwrOff : 1; /*!< [24] */ + uint32_t MiscRst : 1; /*!< [25] */ + uint32_t MiscMemStby : 1; /*!< [26] */ + uint32_t MiscGateClk : 1; /*!< [27] */ + uint32_t rsv28_31 : 4; /*!< [31:28]reserve */ +} PDS_CTL4_Type; + +/** + * @brief PDS interrupt type definition + */ +typedef enum { + PDS_INT_WAKEUP = 0, /*!< PDS wakeup interrupt(assert bit while wakeup, include PDS_Timer/...) */ + PDS_INT_HBN_GPIO_IRRX_BLE_WIFI = 1, /*!< PDS in interrupt source HBN_Wakeup_Source/All_GPIO_Wakeup/IRRX/BLE_Wakeup_Eveent/WIFI_Wakeup_Event */ + PDS_INT_RF_DONE = 2, /*!< PDS RF done interrupt */ + PDS_INT_PLL_DONE = 3, /*!< PDS PLL done interrupt */ + PDS_INT_MAX = 4, /*!< PDS int max number */ +} PDS_INT_Type; + +/** + * @brief PDS force configuration type definition + */ +typedef struct +{ + uint32_t forceCpuPwrOff : 1; /*!< [0]manual force NP power off */ + uint32_t rsv1 : 1; /*!< [1]reserve */ + uint32_t forceWbPwrOff : 1; /*!< [2]manual force WB power off */ + uint32_t rsv3 : 1; /*!< [3]reserve */ + uint32_t forceCpuIsoPwrOff : 1; /*!< [4]manual force NP isolation */ + uint32_t rsv5 : 1; /*!< [5]reserve */ + uint32_t forceWbIsoPwrOff : 1; /*!< [6]manual force WB isolation */ + uint32_t rsv7 : 1; /*!< [7]reserve */ + uint32_t forceCpuPdsRst : 1; /*!< [8]manual force NP pds reset */ + uint32_t rsv9 : 1; /*!< [9]reserve */ + uint32_t forceWbPdsRst : 1; /*!< [10]manual force WB pds reset */ + uint32_t rsv11 : 1; /*!< [11]reserve */ + uint32_t forceCpuMemStby : 1; /*!< [12]manual force NP memory sleep */ + uint32_t rsv13 : 1; /*!< [13]reserve */ + uint32_t forceWbMemStby : 1; /*!< [14]manual force WB memory sleep */ + uint32_t rsv15 : 1; /*!< [15]reserve */ + uint32_t forceCpuGateClk : 1; /*!< [16]manual force NP clock gated */ + uint32_t rsv17 : 1; /*!< [17]reserve */ + uint32_t forceWbGateClk : 1; /*!< [18]manual force WB clock gated */ + uint32_t rsv19_31 : 12; /*!< [31:19]reserve */ +} PDS_CTL2_Type; + +/** + * @brief PDS force configuration type definition + */ +typedef struct +{ + uint32_t rsv0 : 1; /*!< [0]reserve */ + uint32_t forceMiscPwrOff : 1; /*!< [1]manual force MISC pwr_off */ + uint32_t rsv2_3 : 2; /*!< [3:2]reserve */ + uint32_t forceMiscIsoEn : 1; /*!< [4]manual force MISC iso_en */ + uint32_t rsv5_6 : 2; /*!< [6:5]reserve */ + uint32_t forceMiscPdsRst : 1; /*!< [7]manual force MISC pds_rst */ + uint32_t rsv8_9 : 2; /*!< [9:8]reserve */ + uint32_t forceMiscMemStby : 1; /*!< [10]manual force MISC mem_stby */ + uint32_t rsv11_12 : 2; /*!< [12:11]reserve */ + uint32_t forceMiscGateClk : 1; /*!< [13]manual force MISC gate_clk */ + uint32_t rsv14_23 : 10; /*!< [23:14]reserve */ + uint32_t CpuIsoEn : 1; /*!< [24]make NP isolated at PDS Sleep state */ + uint32_t rsv25_26 : 2; /*!< [26:25]reserve */ + uint32_t WbIsoEn : 1; /*!< [27]make WB isolated at PDS Sleep state */ + uint32_t rsv28_29 : 2; /*!< [29:28]reserve */ + uint32_t MiscIsoEn : 1; /*!< [30]make misc isolated at PDS Sleep state */ + uint32_t rsv31 : 1; /*!< [31]reserve */ +} PDS_CTL3_Type; + +/** + * @brief PDS default level configuration type definition + */ +typedef struct +{ + PDS_CTL_Type pdsCtl; /*!< PDS_CTL configuration */ + PDS_CTL2_Type pdsCtl2; /*!< PDS_CTL2 configuration */ + PDS_CTL3_Type pdsCtl3; /*!< PDS_CTL3 configuration */ + PDS_CTL4_Type pdsCtl4; /*!< PDS_CTL4 configuration */ +} PDS_DEFAULT_LV_CFG_Type; + +/** + * @brief PDS PLL status type definition + */ +typedef enum { + PDS_PLL_STS_OFF = 0, /*!< 2'b00 */ + PDS_PLL_STS_SFREG = 1, /*!< 2'b01 */ + PDS_PLL_STS_PU = 2, /*!< 2'b10 */ + PDS_PLL_STS_RDY = 3, /*!< 2'b11 */ +} PDS_PLL_STS_Type; + +/** + * @brief PDS RF status type definition + */ +typedef enum { + PDS_RF_STS_OFF = 0, /*!< 4'b0000 */ + PDS_RF_STS_PU_MBG = 1, /*!< 4'b0001 */ + PDS_RF_STS_PU_LDO15RF = 3, /*!< 4'b0011 */ + PDS_RF_STS_PU_SFREG = 7, /*!< 4'b0111 */ + PDS_RF_STS_WB_EN_AON = 15, /*!< 4'b1111 */ +} PDS_RF_STS_Type; + +/** + * @brief PDS status type definition + */ +typedef enum { + PDS_STS_IDLE = 0, /*!< 4'b0000 */ + PDS_STS_ECG = 8, /*!< 4'b1000 */ + PDS_STS_ERST = 12, /*!< 4'b1100 */ + PDS_STS_EISO = 15, /*!< 4'b1111 */ + PDS_STS_POFF = 7, /*!< 4'b0111 */ + PDS_STS_PRE_BGON = 3, /*!< 4'b0011 */ + PDS_STS_PRE_BGON1 = 1, /*!< 4'b0001 */ + PDS_STS_BGON = 5, /*!< 4'b0101 */ + PDS_STS_CLK_SW_32M = 4, /*!< 4'b0100 */ + PDS_STS_PON_DCDC = 6, /*!< 4'b0110 */ + PDS_STS_PON_LDO11_MISC = 14, /*!< 4'b1110 */ + PDS_STS_PON = 10, /*!< 4'b1010 */ + PDS_STS_DISO = 2, /*!< 4'b0010 */ + PDS_STS_DCG = 13, /*!< 4'b1101 */ + PDS_STS_DRST = 11, /*!< 4'b1011 */ + PDS_STS_WAIT_EFUSE = 9, /*!< 4'b1001 */ +} PDS_STS_Type; + +/** + * @brief PDS RAM configuration type definition + */ +typedef struct +{ + uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_RET : 1; /*!< [0] 0~16KB cpu_ram RET */ + uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_RET : 1; /*!< [1] 16~32KB cpu_ram RET */ + uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_RET : 1; /*!< [2] 32~48KB cpu_ram RET */ + uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_RET : 1; /*!< [3] 48~64KB cpu_ram RET */ + uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_SLP : 1; /*!< [4] 0~16KB cpu_ram SLP */ + uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_SLP : 1; /*!< [5] 16~32KB cpu_ram SLP */ + uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_SLP : 1; /*!< [6] 32~48KB cpu_ram SLP */ + uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_SLP : 1; /*!< [7] 48~64KB cpu_ram SLP */ + uint32_t PDS_RAM_CFG_RSV : 24; /*!< [31:8]reserve */ +} PDS_RAM_CFG_Type; + +/** + * @brief PLL XTAL type definition + */ +typedef enum { + PDS_PLL_XTAL_NONE, /*!< XTAL is none */ + PDS_PLL_XTAL_24M, /*!< XTAL is 24M */ + PDS_PLL_XTAL_32M, /*!< XTAL is 32M */ + PDS_PLL_XTAL_38P4M, /*!< XTAL is 38.4M */ + PDS_PLL_XTAL_40M, /*!< XTAL is 40M */ + PDS_PLL_XTAL_26M, /*!< XTAL is 26M */ + PDS_PLL_XTAL_RC32M, /*!< XTAL is RC32M */ +} PDS_PLL_XTAL_Type; + +/** + * @brief PLL output clock type definition + */ +typedef enum { + PDS_PLL_CLK_480M, /*!< PLL output clock:480M */ + PDS_PLL_CLK_240M, /*!< PLL output clock:240M */ + PDS_PLL_CLK_192M, /*!< PLL output clock:192M */ + PDS_PLL_CLK_160M, /*!< PLL output clock:160M */ + PDS_PLL_CLK_120M, /*!< PLL output clock:120M */ + PDS_PLL_CLK_96M, /*!< PLL output clock:96M */ + PDS_PLL_CLK_80M, /*!< PLL output clock:80M */ + PDS_PLL_CLK_48M, /*!< PLL output clock:48M */ + PDS_PLL_CLK_32M, /*!< PLL output clock:32M */ +} PDS_PLL_CLK_Type; + +/** + * @brief PDS level 0/1/2/3 mode HBN GPIO interrupt trigger type definition + */ +typedef enum { + PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync falling edge trigger */ + PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync rising edge trigger */ + PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync low level trigger */ + PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync high level trigger */ + PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async falling edge trigger */ + PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async rising edge trigger */ + PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async low level trigger */ + PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async high level trigger */ +} PDS_AON_GPIO_INT_Trigger_Type; + +/** + * @brief PDS APP configuration type definition + */ +typedef struct +{ + uint8_t pdsLevel; /*!< PDS level */ + uint8_t turnOffRF; /*!< Wheather turn off RF */ + uint8_t useXtal32k; /*!< Wheather use xtal 32K as 32K clock source,otherwise use rc32k */ + uint8_t pdsAonGpioWakeupSrc; /*!< PDS level 0/1/2/3 mode always on GPIO Wakeup source(HBN wakeup pin) */ + PDS_AON_GPIO_INT_Trigger_Type pdsAonGpioTrigType; /*!< PDS level 0/1/2/3 mode always on GPIO Triger type(HBN wakeup pin) */ + uint8_t powerDownFlash; /*!< Whether power down flash */ + uint8_t turnOffFlashPad; /*!< Whether turn off embedded flash pad */ + uint8_t ocramRetetion; /*!< Whether OCRAM Retention */ + uint8_t turnoffPLL; /*!< Whether trun off PLL */ + uint8_t xtalType; /*!< XTal type, used when user choose turn off PLL, PDS will turn on when exit PDS mode */ + uint8_t flashContRead; /*!< Whether enable flash continue read */ + uint32_t sleepTime; /*!< PDS sleep time */ + SPI_Flash_Cfg_Type *flashCfg; /*!< Flash config pointer, used when power down flash */ + PDS_LDO_LEVEL_Type ldoLevel; /*!< LDO level */ + void (*preCbFun)(void); /*!< Pre callback function */ + void (*postCbFun)(void); /*!< Post callback function */ +} PDS_APP_CFG_Type; + +/*@} end of group PDS_Public_Types */ + +/** @defgroup PDS_Public_Constants + * @{ + */ + +/** @defgroup PDS_LDO_LEVEL_TYPE + * @{ + */ +#define IS_PDS_LDO_LEVEL_TYPE(type) (((type) == PDS_LDO_LEVEL_0P60V) || \ + ((type) == PDS_LDO_LEVEL_0P65V) || \ + ((type) == PDS_LDO_LEVEL_0P70V) || \ + ((type) == PDS_LDO_LEVEL_0P75V) || \ + ((type) == PDS_LDO_LEVEL_0P80V) || \ + ((type) == PDS_LDO_LEVEL_0P85V) || \ + ((type) == PDS_LDO_LEVEL_0P90V) || \ + ((type) == PDS_LDO_LEVEL_0P95V) || \ + ((type) == PDS_LDO_LEVEL_1P00V) || \ + ((type) == PDS_LDO_LEVEL_1P05V) || \ + ((type) == PDS_LDO_LEVEL_1P10V) || \ + ((type) == PDS_LDO_LEVEL_1P15V) || \ + ((type) == PDS_LDO_LEVEL_1P20V) || \ + ((type) == PDS_LDO_LEVEL_1P25V) || \ + ((type) == PDS_LDO_LEVEL_1P30V) || \ + ((type) == PDS_LDO_LEVEL_1P35V)) + +/** @defgroup PDS_INT_TYPE + * @{ + */ +#define IS_PDS_INT_TYPE(type) (((type) == PDS_INT_WAKEUP) || \ + ((type) == PDS_INT_HBN_GPIO_IRRX_BLE_WIFI) || \ + ((type) == PDS_INT_RF_DONE) || \ + ((type) == PDS_INT_PLL_DONE) || \ + ((type) == PDS_INT_MAX)) + +/** @defgroup PDS_PLL_STS_TYPE + * @{ + */ +#define IS_PDS_PLL_STS_TYPE(type) (((type) == PDS_PLL_STS_OFF) || \ + ((type) == PDS_PLL_STS_SFREG) || \ + ((type) == PDS_PLL_STS_PU) || \ + ((type) == PDS_PLL_STS_RDY)) + +/** @defgroup PDS_RF_STS_TYPE + * @{ + */ +#define IS_PDS_RF_STS_TYPE(type) (((type) == PDS_RF_STS_OFF) || \ + ((type) == PDS_RF_STS_PU_MBG) || \ + ((type) == PDS_RF_STS_PU_LDO15RF) || \ + ((type) == PDS_RF_STS_PU_SFREG) || \ + ((type) == PDS_RF_STS_WB_EN_AON)) + +/** @defgroup PDS_STS_TYPE + * @{ + */ +#define IS_PDS_STS_TYPE(type) (((type) == PDS_STS_IDLE) || \ + ((type) == PDS_STS_ECG) || \ + ((type) == PDS_STS_ERST) || \ + ((type) == PDS_STS_EISO) || \ + ((type) == PDS_STS_POFF) || \ + ((type) == PDS_STS_PRE_BGON) || \ + ((type) == PDS_STS_PRE_BGON1) || \ + ((type) == PDS_STS_BGON) || \ + ((type) == PDS_STS_CLK_SW_32M) || \ + ((type) == PDS_STS_PON_DCDC) || \ + ((type) == PDS_STS_PON_LDO11_MISC) || \ + ((type) == PDS_STS_PON) || \ + ((type) == PDS_STS_DISO) || \ + ((type) == PDS_STS_DCG) || \ + ((type) == PDS_STS_DRST) || \ + ((type) == PDS_STS_WAIT_EFUSE)) + +/** @defgroup PDS_PLL_XTAL_TYPE + * @{ + */ +#define IS_PDS_PLL_XTAL_TYPE(type) (((type) == PDS_PLL_XTAL_NONE) || \ + ((type) == PDS_PLL_XTAL_24M) || \ + ((type) == PDS_PLL_XTAL_32M) || \ + ((type) == PDS_PLL_XTAL_38P4M) || \ + ((type) == PDS_PLL_XTAL_40M) || \ + ((type) == PDS_PLL_XTAL_26M) || \ + ((type) == PDS_PLL_XTAL_RC32M)) + +/** @defgroup PDS_PLL_CLK_TYPE + * @{ + */ +#define IS_PDS_PLL_CLK_TYPE(type) (((type) == PDS_PLL_CLK_480M) || \ + ((type) == PDS_PLL_CLK_240M) || \ + ((type) == PDS_PLL_CLK_192M) || \ + ((type) == PDS_PLL_CLK_160M) || \ + ((type) == PDS_PLL_CLK_120M) || \ + ((type) == PDS_PLL_CLK_96M) || \ + ((type) == PDS_PLL_CLK_80M) || \ + ((type) == PDS_PLL_CLK_48M) || \ + ((type) == PDS_PLL_CLK_32M)) + +/** @defgroup PDS_AON_GPIO_INT_TRIGGER_TYPE + * @{ + */ +#define IS_PDS_AON_GPIO_INT_TRIGGER_TYPE(type) (((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) || \ + ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL)) + +/*@} end of group PDS_Public_Constants */ + +/** @defgroup PDS_Public_Macros + * @{ + */ +#define PDS_LDO_MIN_PU_CNT (25) /* LDO need 25 cycles to power up */ +#define PDS_WARMUP_LATENCY_CNT (38) /* LDO hw warmup compensation latency cycles */ +#define PDS_FORCE_PWR_OFF_OFFSET (0) +#define PDS_FORCE_ISO_EN_OFFSET (4) +#define PDS_FORCE_PDS_RST_OFFSET (8) +#define PDS_FORCE_MEM_STBY_OFFSET (12) +#define PDS_FORCE_GATE_CLK_OFFSET (16) +#define PDS_INT_MASK_BIT_OFFSET (8) +#define PDS_AON_WAKEUP_GPIO_NONE (0x00) +#define PDS_AON_WAKEUP_GPIO_7 (0x01) +#define PDS_AON_WAKEUP_GPIO_8 (0x02) +#define PDS_AON_WAKEUP_GPIO_ALL (0x03) + +/*@} end of group PDS_Public_Macros */ + +/** @defgroup PDS_Public_Functions + * @{ + */ +/*----------*/ +#ifndef BFLB_USE_HAL_DRIVER +void PDS_WAKEUP_IRQHandler(void); +#endif +/*----------*/ +BL_Err_Type PDS_Reset(void); +BL_Err_Type PDS_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt); +BL_Err_Type PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3); +BL_Err_Type PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg); +/*----------*/ +BL_Err_Type PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, + PDS_RAM_CFG_Type *ramCfg, uint32_t pdsSleepCnt); +/*----------*/ +BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask); +BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType); +BL_Err_Type PDS_IntClear(void); +PDS_PLL_STS_Type PDS_Get_PdsPllStstus(void); +PDS_RF_STS_Type PDS_Get_PdsRfStstus(void); +PDS_STS_Type PDS_Get_PdsStstus(void); +BL_Err_Type PDS_WAKEUP_IRQHandler_Install(void); +BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun); +/*----------*/ +BL_Err_Type PDS_Trim_RC32M(void); +BL_Err_Type PDS_Select_RC32M_As_PLL_Ref(void); +BL_Err_Type PDS_Select_XTAL_As_PLL_Ref(void); +BL_Err_Type PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType); +BL_Err_Type PDS_Fix_Xtal_Settig(void); +BL_Err_Type PDS_Enable_PLL_All_Clks(void); +BL_Err_Type PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk); +BL_Err_Type PDS_Disable_PLL_All_Clks(void); +BL_Err_Type PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk); +BL_Err_Type PDS_Power_Off_PLL(void); +/*----------*/; + +/*@} end of group PDS_Public_Functions */ + +/*@} end of group PDS */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_PDS_H__ */ diff --git a/drivers/soc/bl602/bl602_std/include/bl602_romdriver.h b/drivers/soc/bl602/bl602_std/include/bl602_romdriver.h new file mode 100644 index 00000000..1d58acb2 --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/bl602_romdriver.h @@ -0,0 +1,798 @@ +/** + ****************************************************************************** + * @file bl602_romdriver.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_ROMDRIVER_H__ +#define __BL602_ROMDRIVER_H__ + +#include "bl602_common.h" +#include "bl602_aon.h" +#include "bl602_glb.h" +#include "bl602_hbn.h" +#include "bl602_xip_sflash.h" +#include "bl602_sflash.h" +#include "bl602_sf_ctrl.h" +// #include "bl602_sec_eng.h" +// #include "softcrc.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup ROMDRIVER + * @{ + */ + +/** @defgroup ROMDRIVER_Public_Types + * @{ + */ + +#define ROMAPI_INDEX_SECT_SIZE (0x800) +#define ROMAPI_INDEX_MAX (ROMAPI_INDEX_SECT_SIZE / 4 - 1) + +typedef enum { + ROM_API_INDEX_VERSION = 0, + ROM_API_INDEX_RSVD_0, + ROM_API_INDEX_RSVD_1, + ROM_API_INDEX_RSVD_LAST, + + ROM_API_INDEX_AON_Power_On_MBG, + ROM_API_INDEX_AON_Power_Off_MBG, + ROM_API_INDEX_AON_Power_On_XTAL, + ROM_API_INDEX_AON_Set_Xtal_CapCode, + ROM_API_INDEX_AON_Get_Xtal_CapCode, + ROM_API_INDEX_AON_Power_Off_XTAL, + ROM_API_INDEX_AON_Power_On_BG, + ROM_API_INDEX_AON_Power_Off_BG, + ROM_API_INDEX_AON_Power_On_LDO11_SOC, + ROM_API_INDEX_AON_Power_Off_LDO11_SOC, + ROM_API_INDEX_AON_Power_On_LDO15_RF, + ROM_API_INDEX_AON_Power_Off_LDO15_RF, + ROM_API_INDEX_AON_Power_On_SFReg, + ROM_API_INDEX_AON_Power_Off_SFReg, + ROM_API_INDEX_AON_LowPower_Enter_PDS0, + ROM_API_INDEX_AON_LowPower_Exit_PDS0, + + ROM_API_INDEX_ASM_Delay_Us, + + ROM_API_INDEX_BL602_Delay_US, + ROM_API_INDEX_BL602_Delay_MS, + ROM_API_INDEX_BL602_MemCpy, + ROM_API_INDEX_BL602_MemCpy4, + ROM_API_INDEX_BL602_MemCpy_Fast, + ROM_API_INDEX_BL602_MemSet, + ROM_API_INDEX_BL602_MemSet4, + ROM_API_INDEX_BL602_MemCmp, + + ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0, + ROM_API_INDEX_EF_Ctrl_Program_Efuse_0, + ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0, + ROM_API_INDEX_EF_Ctrl_Busy, + ROM_API_INDEX_EF_Ctrl_AutoLoad_Done, + ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity, + ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim, + ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim, + ROM_API_INDEX_EF_Ctrl_Clear, + + ROM_API_INDEX_GLB_Get_Root_CLK_Sel, + ROM_API_INDEX_GLB_Set_System_CLK_Div, + ROM_API_INDEX_GLB_Get_BCLK_Div, + ROM_API_INDEX_GLB_Get_HCLK_Div, + + ROM_API_INDEX_Update_SystemCoreClockWith_XTAL, + + ROM_API_INDEX_GLB_Set_System_CLK, + + ROM_API_INDEX_System_Core_Clock_Update_From_RC32M, + + ROM_API_INDEX_GLB_Set_SF_CLK, + ROM_API_INDEX_GLB_Set_PKA_CLK_Sel, + ROM_API_INDEX_GLB_SW_System_Reset, + ROM_API_INDEX_GLB_SW_CPU_Reset, + ROM_API_INDEX_GLB_SW_POR_Reset, + ROM_API_INDEX_GLB_Select_Internal_Flash, + ROM_API_INDEX_GLB_Select_External_Flash, + ROM_API_INDEX_GLB_Deswap_Flash_Pin, + ROM_API_INDEX_GLB_Swap_Flash_Pin, + ROM_API_INDEX_GLB_GPIO_Init, + ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable, + ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable, + ROM_API_INDEX_GLB_GPIO_Set_HZ, + ROM_API_INDEX_GLB_GPIO_Get_Fun, + + ROM_API_INDEX_HBN_Mode_Enter, + ROM_API_INDEX_HBN_Power_Down_Flash, + ROM_API_INDEX_HBN_Enable, + ROM_API_INDEX_HBN_Reset, + ROM_API_INDEX_HBN_Set_Ldo11_Aon_Vout, + ROM_API_INDEX_HBN_Set_Ldo11_Rt_Vout, + ROM_API_INDEX_HBN_Set_Ldo11_Soc_Vout, + ROM_API_INDEX_HBN_32K_Sel, + ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel, + ROM_API_INDEX_HBN_Power_On_Xtal_32K, + ROM_API_INDEX_HBN_Power_Off_Xtal_32K, + ROM_API_INDEX_HBN_Power_On_RC32K, + ROM_API_INDEX_HBN_Power_Off_RC32K, + ROM_API_INDEX_HBN_Trim_RC32K, + ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg, + ROM_API_INDEX_HBN_Pin_WakeUp_Mask, + ROM_API_INDEX_HBN_GPIO7_Dbg_Pull_Cfg, + ROM_API_INDEX_HBN_Set_Embedded_Flash_Pullup, + + ROM_API_INDEX_L1C_Set_Wrap, + ROM_API_INDEX_L1C_Set_Way_Disable, + ROM_API_INDEX_L1C_IROM_2T_Access_Set, + + ROM_API_INDEX_PDS_Reset, + ROM_API_INDEX_PDS_Enable, + ROM_API_INDEX_PDS_Force_Config, + ROM_API_INDEX_PDS_RAM_Config, + ROM_API_INDEX_PDS_Default_Level_Config, + ROM_API_INDEX_PDS_Trim_RC32M, + ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref, + ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref, + ROM_API_INDEX_PDS_Power_On_PLL, + ROM_API_INDEX_PDS_Enable_PLL_All_Clks, + ROM_API_INDEX_PDS_Disable_PLL_All_Clks, + ROM_API_INDEX_PDS_Enable_PLL_Clk, + ROM_API_INDEX_PDS_Disable_PLL_Clk, + ROM_API_INDEX_PDS_Power_Off_PLL, + + ROM_API_INDEX_SEC_Eng_Turn_On_Sec_Ring, + ROM_API_INDEX_SEC_Eng_Turn_Off_Sec_Ring, + + ROM_API_INDEX_SFlash_Init, + ROM_API_INDEX_SFlash_SetSPIMode, + ROM_API_INDEX_SFlash_Read_Reg, + ROM_API_INDEX_SFlash_Write_Reg, + ROM_API_INDEX_SFlash_Busy, + ROM_API_INDEX_SFlash_Write_Enable, + ROM_API_INDEX_SFlash_Qspi_Enable, + ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable, + ROM_API_INDEX_SFlash_Chip_Erase, + ROM_API_INDEX_SFlash_Sector_Erase, + ROM_API_INDEX_SFlash_Blk32_Erase, + ROM_API_INDEX_SFlash_Blk64_Erase, + ROM_API_INDEX_SFlash_Erase, + ROM_API_INDEX_SFlash_Program, + ROM_API_INDEX_SFlash_GetUniqueId, + ROM_API_INDEX_SFlash_GetJedecId, + ROM_API_INDEX_SFlash_GetDeviceId, + ROM_API_INDEX_SFlash_Powerdown, + ROM_API_INDEX_SFlash_Releae_Powerdown, + ROM_API_INDEX_SFlash_SetBurstWrap, + ROM_API_INDEX_SFlash_DisableBurstWrap, + ROM_API_INDEX_SFlash_Software_Reset, + ROM_API_INDEX_SFlash_Reset_Continue_Read, + ROM_API_INDEX_SFlash_Set_IDbus_Cfg, + ROM_API_INDEX_SFlash_IDbus_Read_Enable, + ROM_API_INDEX_SFlash_Cache_Enable_Set, + ROM_API_INDEX_SFlash_Cache_Flush, + ROM_API_INDEX_SFlash_Cache_Read_Enable, + ROM_API_INDEX_SFlash_Cache_Hit_Count_Get, + ROM_API_INDEX_SFlash_Cache_Miss_Count_Get, + ROM_API_INDEX_SFlash_Cache_Read_Disable, + ROM_API_INDEX_SFlash_Read, + ROM_API_INDEX_SFlash_Read_Reg_With_Cmd, + ROM_API_INDEX_SFlash_Write_Reg_With_Cmd, + ROM_API_INDEX_SFlash_Restore_From_Powerdown, + + ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio, + ROM_API_INDEX_SF_Cfg_Init_Internal_Flash_Gpio, + ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio, + ROM_API_INDEX_SF_Cfg_Restore_GPIO17_Fun, + ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock, + ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio, + ROM_API_INDEX_SF_Cfg_Flash_Identify, + ROM_API_INDEX_SF_Ctrl_Enable, + ROM_API_INDEX_SF_Ctrl_Select_Pad, + ROM_API_INDEX_SF_Ctrl_Set_Owner, + ROM_API_INDEX_SF_Ctrl_Disable, + ROM_API_INDEX_SF_Ctrl_AES_Enable_BE, + ROM_API_INDEX_SF_Ctrl_AES_Enable_LE, + ROM_API_INDEX_SF_Ctrl_AES_Set_Region, + ROM_API_INDEX_SF_Ctrl_AES_Set_Key, + ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE, + ROM_API_INDEX_SF_Ctrl_AES_Set_IV, + ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE, + ROM_API_INDEX_SF_Ctrl_AES_Enable, + ROM_API_INDEX_SF_Ctrl_AES_Disable, + ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset, + ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset, + ROM_API_INDEX_SF_Ctrl_Select_Clock, + ROM_API_INDEX_SF_Ctrl_SendCmd, + ROM_API_INDEX_SF_Ctrl_Icache_Set, + ROM_API_INDEX_SF_Ctrl_Icache2_Set, + ROM_API_INDEX_SF_Ctrl_GetBusyState, + ROM_API_INDEX_SF_Ctrl_Is_AES_Enable, + ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay, + ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay, + + ROM_API_INDEX_XIP_SFlash_State_Save, + ROM_API_INDEX_XIP_SFlash_State_Restore, + ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock, + ROM_API_INDEX_XIP_SFlash_Write_Need_Lock, + ROM_API_INDEX_XIP_SFlash_Read_Need_Lock, + ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock, + ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock, + ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock, + ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock, + ROM_API_INDEX_XIP_SFlash_Read_With_Lock, + ROM_API_INDEX_XIP_SFlash_Write_With_Lock, + ROM_API_INDEX_XIP_SFlash_Erase_With_Lock, + ROM_API_INDEX_XIP_SFlash_Opt_Enter, + ROM_API_INDEX_XIP_SFlash_Opt_Exit, + + ROM_API_INDEX_BFLB_Soft_CRC32, + + ROM_API_INDEX_FUNC_EMPTY_START, + + ROM_API_INDEX_FUNC_EMPTY_END = ROMAPI_INDEX_MAX + +} ROM_API_INDEX_e; + +/*@} end of group ROMDRIVER_Public_Types */ + +/** @defgroup ROMDRIVER_Public_Constants + * @{ + */ + +/*@} end of group ROMDRIVER_Public_Constants */ + +/** @defgroup ROMDRIVER_Public_Macros + * @{ + */ + +#define ROM_APITABLE ((uint32_t *)0x21010800) + +#define RomDriver_AON_Power_On_MBG \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_MBG]) + +#define RomDriver_AON_Power_Off_MBG \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_MBG]) + +#define RomDriver_AON_Power_On_XTAL \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_XTAL]) + +#define RomDriver_AON_Set_Xtal_CapCode \ + ((BL_Err_Type(*)(uint8_t capIn, uint8_t capOut))ROM_APITABLE[ROM_API_INDEX_AON_Set_Xtal_CapCode]) + +#define RomDriver_AON_Get_Xtal_CapCode \ + ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Get_Xtal_CapCode]) + +#define RomDriver_AON_Power_Off_XTAL \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_XTAL]) + +#define RomDriver_AON_Power_On_BG \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_BG]) + +#define RomDriver_AON_Power_Off_BG \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_BG]) + +#define RomDriver_AON_Power_On_LDO11_SOC \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_LDO11_SOC]) + +#define RomDriver_AON_Power_Off_LDO11_SOC \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_LDO11_SOC]) + +#define RomDriver_AON_Power_On_LDO15_RF \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_LDO15_RF]) + +#define RomDriver_AON_Power_Off_LDO15_RF \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_LDO15_RF]) + +#define RomDriver_AON_Power_On_SFReg \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_SFReg]) + +#define RomDriver_AON_Power_Off_SFReg \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_SFReg]) + +#define RomDriver_AON_LowPower_Enter_PDS0 \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_LowPower_Enter_PDS0]) + +#define RomDriver_AON_LowPower_Exit_PDS0 \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_LowPower_Exit_PDS0]) + +#define RomDriver_ASM_Delay_Us \ + ((void (*)(uint32_t core, uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_ASM_Delay_Us]) + +#define RomDriver_BL602_Delay_US \ + ((void (*)(uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_BL602_Delay_US]) + +#define RomDriver_BL602_Delay_MS \ + ((void (*)(uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_BL602_Delay_MS]) + +#define RomDriver_BL602_MemCpy \ + ((void *(*)(void *dst, const void *src, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemCpy]) + +#define RomDriver_BL602_MemCpy4 \ + ((uint32_t * (*)(uint32_t * dst, const uint32_t *src, uint32_t n)) ROM_APITABLE[ROM_API_INDEX_BL602_MemCpy4]) + +#define RomDriver_BL602_MemCpy_Fast \ + ((void *(*)(void *pdst, const void *psrc, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemCpy_Fast]) + +#define RomDriver_BL602_MemSet \ + ((void *(*)(void *s, uint8_t c, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemSet]) + +#define RomDriver_BL602_MemSet4 \ + ((uint32_t * (*)(uint32_t * dst, const uint32_t val, uint32_t n)) ROM_APITABLE[ROM_API_INDEX_BL602_MemSet4]) + +#define RomDriver_BL602_MemCmp \ + ((int (*)(const void *s1, const void *s2, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemCmp]) + +#define RomDriver_EF_Ctrl_Sw_AHB_Clk_0 \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0]) + +#define RomDriver_EF_Ctrl_Program_Efuse_0 \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Program_Efuse_0]) + +#define RomDriver_EF_Ctrl_Load_Efuse_R0 \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0]) + +#define RomDriver_EF_Ctrl_Busy \ + ((BL_Sts_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Busy]) + +#define RomDriver_EF_Ctrl_AutoLoad_Done \ + ((BL_Sts_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_AutoLoad_Done]) + +#define RomDriver_EF_Ctrl_Get_Trim_Parity \ + ((uint8_t(*)(uint32_t val, uint8_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity]) + +#define RomDriver_EF_Ctrl_Read_RC32M_Trim \ + ((void (*)(Efuse_Ana_RC32M_Trim_Type * trim)) ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim]) + +#define RomDriver_EF_Ctrl_Read_RC32K_Trim \ + ((void (*)(Efuse_Ana_RC32K_Trim_Type * trim)) ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim]) + +#define RomDriver_EF_Ctrl_Clear \ + ((void (*)(uint32_t index, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Clear]) + +#define RomDriver_GLB_Get_Root_CLK_Sel \ + ((GLB_ROOT_CLK_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_Root_CLK_Sel]) + +#define RomDriver_GLB_Set_System_CLK_Div \ + ((BL_Err_Type(*)(uint8_t hclkDiv, uint8_t bclkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Set_System_CLK_Div]) + +#define RomDriver_GLB_Get_BCLK_Div \ + ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_BCLK_Div]) + +#define RomDriver_GLB_Get_HCLK_Div \ + ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_HCLK_Div]) + +#define RomDriver_Update_SystemCoreClockWith_XTAL \ + ((BL_Err_Type(*)(GLB_PLL_XTAL_Type xtalType))ROM_APITABLE[ROM_API_INDEX_Update_SystemCoreClockWith_XTAL]) + +#define RomDriver_GLB_Set_System_CLK \ + ((BL_Err_Type(*)(GLB_PLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq))ROM_APITABLE[ROM_API_INDEX_GLB_Set_System_CLK]) + +#define RomDriver_System_Core_Clock_Update_From_RC32M \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_System_Core_Clock_Update_From_RC32M]) + +#define RomDriver_GLB_Set_SF_CLK \ + ((BL_Err_Type(*)(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SF_CLK]) + +#define RomDriver_GLB_Set_PKA_CLK_Sel \ + ((BL_Err_Type(*)(GLB_PKA_CLK_Type clkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_PKA_CLK_Sel]) + +#define RomDriver_GLB_SW_System_Reset \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_System_Reset]) + +#define RomDriver_GLB_SW_CPU_Reset \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_CPU_Reset]) + +#define RomDriver_GLB_SW_POR_Reset \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_POR_Reset]) + +#define RomDriver_GLB_Select_Internal_Flash \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Select_Internal_Flash]) + +#define RomDriver_GLB_Select_External_Flash \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Select_External_Flash]) + +#define RomDriver_GLB_Deswap_Flash_Pin \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Deswap_Flash_Pin]) + +#define RomDriver_GLB_Swap_Flash_Pin \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Swap_Flash_Pin]) + +#define RomDriver_GLB_GPIO_Init \ + ((BL_Err_Type(*)(GLB_GPIO_Cfg_Type * cfg)) ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Init]) + +#define RomDriver_GLB_GPIO_OUTPUT_Enable \ + ((BL_Err_Type(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable]) + +#define RomDriver_GLB_GPIO_OUTPUT_Disable \ + ((BL_Err_Type(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable]) + +#define RomDriver_GLB_GPIO_Set_HZ \ + ((BL_Err_Type(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Set_HZ]) + +#define RomDriver_GLB_GPIO_Get_Fun \ + ((uint8_t(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Get_Fun]) + +#define RomDriver_HBN_Mode_Enter \ + ((void (*)(HBN_APP_CFG_Type * cfg)) ROM_APITABLE[ROM_API_INDEX_HBN_Mode_Enter]) + +#define RomDriver_HBN_Power_Down_Flash \ + ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_HBN_Power_Down_Flash]) + +#define RomDriver_HBN_Enable \ + ((void (*)(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Enable]) + +#define RomDriver_HBN_Reset \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Reset]) + +#define RomDriver_HBN_Set_Ldo11_Aon_Vout \ + ((BL_Err_Type(*)(HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_Aon_Vout]) + +#define RomDriver_HBN_Set_Ldo11_Rt_Vout \ + ((BL_Err_Type(*)(HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_Rt_Vout]) + +#define RomDriver_HBN_Set_Ldo11_Soc_Vout \ + ((BL_Err_Type(*)(HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_Soc_Vout]) + +#define RomDriver_HBN_32K_Sel \ + ((BL_Err_Type(*)(HBN_32K_CLK_Type clkType))ROM_APITABLE[ROM_API_INDEX_HBN_32K_Sel]) + +#define RomDriver_HBN_Set_ROOT_CLK_Sel \ + ((BL_Err_Type(*)(HBN_ROOT_CLK_Type rootClk))ROM_APITABLE[ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel]) + +#define RomDriver_HBN_Power_On_Xtal_32K \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_On_Xtal_32K]) + +#define RomDriver_HBN_Power_Off_Xtal_32K \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Off_Xtal_32K]) + +#define RomDriver_HBN_Power_On_RC32K \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_On_RC32K]) + +#define RomDriver_HBN_Power_Off_RC32K \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Off_RC32K]) + +#define RomDriver_HBN_Trim_RC32K \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Trim_RC32K]) + +#define RomDriver_HBN_Hw_Pu_Pd_Cfg \ + ((BL_Err_Type(*)(uint8_t enable))ROM_APITABLE[ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg]) + +#define RomDriver_HBN_Pin_WakeUp_Mask \ + ((BL_Err_Type(*)(uint8_t maskVal))ROM_APITABLE[ROM_API_INDEX_HBN_Pin_WakeUp_Mask]) + +#define RomDriver_HBN_GPIO7_Dbg_Pull_Cfg \ + ((BL_Err_Type(*)(BL_Fun_Type pupdEn, BL_Fun_Type iesmtEn, BL_Fun_Type dlyEn, uint8_t dlySec))ROM_APITABLE[ROM_API_INDEX_HBN_GPIO7_Dbg_Pull_Cfg]) + +#define RomDriver_HBN_Set_Embedded_Flash_Pullup \ + ((BL_Err_Type(*)(uint8_t enable))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Embedded_Flash_Pullup]) + +#define RomDriver_L1C_Set_Wrap \ + ((BL_Err_Type(*)(BL_Fun_Type wrap))ROM_APITABLE[ROM_API_INDEX_L1C_Set_Wrap]) + +#define RomDriver_L1C_Set_Way_Disable \ + ((BL_Err_Type(*)(uint8_t disableVal))ROM_APITABLE[ROM_API_INDEX_L1C_Set_Way_Disable]) + +#define RomDriver_L1C_IROM_2T_Access_Set \ + ((BL_Err_Type(*)(uint8_t enable))ROM_APITABLE[ROM_API_INDEX_L1C_IROM_2T_Access_Set]) + +#define RomDriver_PDS_Reset \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Reset]) + +#define RomDriver_PDS_Enable \ + ((BL_Err_Type(*)(PDS_CTL_Type * cfg, PDS_CTL4_Type * cfg4, uint32_t pdsSleepCnt)) ROM_APITABLE[ROM_API_INDEX_PDS_Enable]) + +#define RomDriver_PDS_Force_Config \ + ((BL_Err_Type(*)(PDS_CTL2_Type * cfg2, PDS_CTL3_Type * cfg3)) ROM_APITABLE[ROM_API_INDEX_PDS_Force_Config]) + +#define RomDriver_PDS_RAM_Config \ + ((BL_Err_Type(*)(PDS_RAM_CFG_Type * ramCfg)) ROM_APITABLE[ROM_API_INDEX_PDS_RAM_Config]) + +#define RomDriver_PDS_Default_Level_Config \ + ((BL_Err_Type(*)(PDS_DEFAULT_LV_CFG_Type * defaultLvCfg, PDS_RAM_CFG_Type * ramCfg, uint32_t pdsSleepCnt)) ROM_APITABLE[ROM_API_INDEX_PDS_Default_Level_Config]) + +#define RomDriver_PDS_Trim_RC32M \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Trim_RC32M]) + +#define RomDriver_PDS_Select_RC32M_As_PLL_Ref \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref]) + +#define RomDriver_PDS_Select_XTAL_As_PLL_Ref \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref]) + +#define RomDriver_PDS_Power_On_PLL \ + ((BL_Err_Type(*)(PDS_PLL_XTAL_Type xtalType))ROM_APITABLE[ROM_API_INDEX_PDS_Power_On_PLL]) + +#define RomDriver_PDS_Enable_PLL_All_Clks \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Enable_PLL_All_Clks]) + +#define RomDriver_PDS_Disable_PLL_All_Clks \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Disable_PLL_All_Clks]) + +#define RomDriver_PDS_Enable_PLL_Clk \ + ((BL_Err_Type(*)(PDS_PLL_CLK_Type pllClk))ROM_APITABLE[ROM_API_INDEX_PDS_Enable_PLL_Clk]) + +#define RomDriver_PDS_Disable_PLL_Clk \ + ((BL_Err_Type(*)(PDS_PLL_CLK_Type pllClk))ROM_APITABLE[ROM_API_INDEX_PDS_Disable_PLL_Clk]) + +#define RomDriver_PDS_Power_Off_PLL \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Power_Off_PLL]) + +#define RomDriver_SEC_Eng_Turn_On_Sec_Ring \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SEC_Eng_Turn_On_Sec_Ring]) + +#define RomDriver_SEC_Eng_Turn_Off_Sec_Ring \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SEC_Eng_Turn_Off_Sec_Ring]) + +#define RomDriver_SFlash_Init \ + ((void (*)(const SF_Ctrl_Cfg_Type *pSfCtrlCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Init]) + +#define RomDriver_SFlash_SetSPIMode \ + ((BL_Err_Type(*)(SF_Ctrl_Mode_Type mode))ROM_APITABLE[ROM_API_INDEX_SFlash_SetSPIMode]) + +#define RomDriver_SFlash_Read_Reg \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg]) + +#define RomDriver_SFlash_Write_Reg \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg]) + +#define RomDriver_SFlash_Busy \ + ((BL_Sts_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Busy]) + +#define RomDriver_SFlash_Write_Enable \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Enable]) + +#define RomDriver_SFlash_Qspi_Enable \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Enable]) + +#define RomDriver_SFlash_Volatile_Reg_Write_Enable \ + ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable]) + +#define RomDriver_SFlash_Chip_Erase \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Chip_Erase]) + +#define RomDriver_SFlash_Sector_Erase \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t secNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Sector_Erase]) + +#define RomDriver_SFlash_Blk32_Erase \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk32_Erase]) + +#define RomDriver_SFlash_Blk64_Erase \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk64_Erase]) + +#define RomDriver_SFlash_Erase \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_SFlash_Erase]) + +#define RomDriver_SFlash_Program \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Program]) + +#define RomDriver_SFlash_GetUniqueId \ + ((void (*)(uint8_t * data, uint8_t idLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetUniqueId]) + +#define RomDriver_SFlash_GetJedecId \ + ((void (*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetJedecId]) + +#define RomDriver_SFlash_GetDeviceId \ + ((void (*)(uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetDeviceId]) + +#define RomDriver_SFlash_Powerdown \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Powerdown]) + +#define RomDriver_SFlash_Releae_Powerdown \ + ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Releae_Powerdown]) + +#define RomDriver_SFlash_SetBurstWrap \ + ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_SetBurstWrap]) + +#define RomDriver_SFlash_DisableBurstWrap \ + ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_DisableBurstWrap]) + +#define RomDriver_SFlash_Software_Reset \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Software_Reset]) + +#define RomDriver_SFlash_Reset_Continue_Read \ + ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Reset_Continue_Read]) + +#define RomDriver_SFlash_Set_IDbus_Cfg \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Set_IDbus_Cfg]) + +#define RomDriver_SFlash_IDbus_Read_Enable \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead)) ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Enable]) + +#define RomDriver_SFlash_Cache_Enable_Set \ + ((BL_Err_Type(*)(uint8_t wayDisable))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Enable_Set]) + +#define RomDriver_SFlash_Cache_Flush \ + ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Flush]) + +#define RomDriver_SFlash_Cache_Read_Enable \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint8_t wayDisable)) ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Enable]) + +#define RomDriver_SFlash_Cache_Hit_Count_Get \ + ((void (*)(uint32_t * hitCountLow, uint32_t * hitCountHigh)) ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Hit_Count_Get]) + +#define RomDriver_SFlash_Cache_Miss_Count_Get \ + ((uint32_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Miss_Count_Get]) + +#define RomDriver_SFlash_Cache_Read_Disable \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Disable]) + +#define RomDriver_SFlash_Read \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read]) + +#define RomDriver_SFlash_Read_Reg_With_Cmd \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t readRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd]) + +#define RomDriver_SFlash_Write_Reg_With_Cmd \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t writeRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd]) + +#define RomDriver_SFlash_Restore_From_Powerdown \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint8_t flashContRead)) ROM_APITABLE[ROM_API_INDEX_SFlash_Restore_From_Powerdown]) + +#define RomDriver_SF_Cfg_Init_Ext_Flash_Gpio \ + ((void (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio]) + +#define RomDriver_SF_Cfg_Init_Internal_Flash_Gpio \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Internal_Flash_Gpio]) + +#define RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio \ + ((void (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio]) + +#define RomDriver_SF_Cfg_Restore_GPIO17_Fun \ + ((void (*)(uint8_t fun))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Restore_GPIO17_Fun]) + +#define RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock \ + ((BL_Err_Type(*)(uint32_t flashID, SPI_Flash_Cfg_Type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock]) + +#define RomDriver_SF_Cfg_Init_Flash_Gpio \ + ((void (*)(uint8_t flashPinCfg, uint8_t restoreDefault))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio]) + +#define RomDriver_SF_Cfg_Flash_Identify \ + ((uint32_t(*)(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify]) + +#define RomDriver_SF_Ctrl_Enable \ + ((void (*)(const SF_Ctrl_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Enable]) + +#define RomDriver_SF_Ctrl_Select_Pad \ + ((void (*)(SF_Ctrl_Pad_Sel sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Pad]) + +#define RomDriver_SF_Ctrl_Set_Owner \ + ((void (*)(SF_Ctrl_Owner_Type owner))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Owner]) + +#define RomDriver_SF_Ctrl_Disable \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Disable]) + +#define RomDriver_SF_Ctrl_AES_Enable_BE \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable_BE]) + +#define RomDriver_SF_Ctrl_AES_Enable_LE \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable_LE]) + +#define RomDriver_SF_Ctrl_AES_Set_Region \ + ((void (*)(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Region]) + +#define RomDriver_SF_Ctrl_AES_Set_Key \ + ((void (*)(uint8_t region, uint8_t * key, SF_Ctrl_AES_Key_Type keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key]) + +#define RomDriver_SF_Ctrl_AES_Set_Key_BE \ + ((void (*)(uint8_t region, uint8_t * key, SF_Ctrl_AES_Key_Type keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE]) + +#define RomDriver_SF_Ctrl_AES_Set_IV \ + ((void (*)(uint8_t region, uint8_t * iv, uint32_t addrOffset)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV]) + +#define RomDriver_SF_Ctrl_AES_Set_IV_BE \ + ((void (*)(uint8_t region, uint8_t * iv, uint32_t addrOffset)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE]) + +#define RomDriver_SF_Ctrl_AES_Enable \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable]) + +#define RomDriver_SF_Ctrl_AES_Disable \ + ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Disable]) + +#define RomDriver_SF_Ctrl_Set_Flash_Image_Offset \ + ((void (*)(uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset]) + +#define RomDriver_SF_Ctrl_Get_Flash_Image_Offset \ + ((uint32_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset]) + +#define RomDriver_SF_Ctrl_Select_Clock \ + ((void (*)(SF_Ctrl_Sahb_Type sahbType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Clock]) + +#define RomDriver_SF_Ctrl_SendCmd \ + ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_SendCmd]) + +#define RomDriver_SF_Ctrl_Icache_Set \ + ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Icache_Set]) + +#define RomDriver_SF_Ctrl_Icache2_Set \ + ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Icache2_Set]) + +#define RomDriver_SF_Ctrl_GetBusyState \ + ((BL_Sts_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_GetBusyState]) + +#define RomDriver_SF_Ctrl_Is_AES_Enable \ + ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_AES_Enable]) + +#define RomDriver_SF_Ctrl_Get_Clock_Delay \ + ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay]) + +#define RomDriver_SF_Ctrl_Set_Clock_Delay \ + ((void (*)(uint8_t delay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay]) + +#define RomDriver_XIP_SFlash_State_Save \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t * offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Save]) + +#define RomDriver_XIP_SFlash_State_Restore \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Restore]) + +#define RomDriver_XIP_SFlash_Erase_Need_Lock \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock]) + +#define RomDriver_XIP_SFlash_Write_Need_Lock \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock]) + +#define RomDriver_XIP_SFlash_Read_Need_Lock \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock]) + +#define RomDriver_XIP_SFlash_GetJedecId_Need_Lock \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock]) + +#define RomDriver_XIP_SFlash_GetDeviceId_Need_Lock \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock]) + +#define RomDriver_XIP_SFlash_GetUniqueId_Need_Lock \ + ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint8_t * data, uint8_t idLen)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock]) + +#define RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock \ + ((BL_Err_Type(*)(uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock]) + +#define RomDriver_XIP_SFlash_Opt_Enter \ + ((void (*)(uint8_t * aesEnable)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Opt_Enter]) + +#define RomDriver_XIP_SFlash_Opt_Exit \ + ((void (*)(uint8_t aesEnable))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Opt_Exit]) + +#define RomDriver_BFLB_Soft_CRC32 \ + ((uint32_t(*)(void *dataIn, uint32_t len))ROM_APITABLE[ROM_API_INDEX_BFLB_Soft_CRC32]) + +/*@} end of group ROMDRIVER_Public_Macros */ + +/** @defgroup ROMDRIVER_Public_Functions + * @{ + */ + +/*@} end of group ROMDRIVER_Public_Functions */ + +/*@} end of group ROMDRIVER */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_ROMDRIVER_H__ */ diff --git a/drivers/soc/bl602/bl602_std/include/bl602_sdu.h b/drivers/soc/bl602/bl602_std/include/bl602_sdu.h new file mode 100644 index 00000000..25fb979a --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/bl602_sdu.h @@ -0,0 +1,184 @@ +#ifndef __BL602_SDU_H__ +#define __BL602_SDU_H__ + +#include "bl602.h" +#include "bl602_common.h" + +#define NUM_FUNC 1 +#define FUNC_WIFI 0 + +// SDIO I/O Enable +#define BL_SDIO_IO_ENABLE SDU_BASE + 0x00000002 +//CCCR (Fn0) Registers + +// SDIO Device Sleep +#define BL_SDIO_DEV_SLEEP SDU_BASE + 0x00000092 + +// Start Address of CCR +#define BL_SDIO_CCR_BASE SDU_BASE + 0x00000100 +// Address offset of CCR between two functions +#define BL_SDIO_CCR_FUNC_OFFSET 0x00000100 + +// Address for sdio block size information +#define SDIO_FN1_BLK_SIZE_0 (SDU_BASE + 0x00000028) +#define SDIO_FN1_BLK_SIZE_1 (SDU_BASE + 0x00000029) +#define SDIO_FN1_BLK_SIZE_1_MASK 0x01 + +#define BL_FUNC_SCRATCH_BASE SDU_BASE + 0x00000160 + +typedef struct +{ + uint8_t HostToCardEvent; // 0x100/200 + uint8_t HostIntCause; // 0x101/201 + uint8_t HostIntMask; // 0x102/202 + uint8_t HostIntStatus; // 0x103/203 + uint16_t RdBitMap; // 0x104/204 + uint16_t WrBitMap; // 0x106/206 + uint16_t RdLen[16]; // 0x108/208 + uint8_t HostTransferStatus; // 0x128/228 + uint8_t reserved1[0x130 - 0x128 - 1]; + uint8_t CardToHostEvent; // 0x130/230 + uint8_t reserved2[3]; + uint8_t CardIntMask; // 0x134/234 + uint8_t reserved3[3]; + uint8_t CardIntStatus; // 0x138/238 + uint8_t reserved4[3]; + uint8_t CardIntMode; // 0x13C/23C + uint8_t reserved5[3]; + uint32_t SqReadBase; // 0x140/240 + uint32_t SqWriteBase; // 0x144/244 + uint8_t RdIdx; // 0x148/248 + uint8_t WrIdx; // 0x149/249 + uint8_t DnldQueueWrPtr; // 0x14A/24A + uint8_t UpldQueueWrPtr; // 0x14B/24B + uint8_t DnldQueue[8]; // 0x14C/24C + uint8_t UpldQueue[8]; // 0x154/254 + uint8_t ChipRev; // 0x15C //RO + uint8_t reserved6; // 0x15D //NOT_DEFINE + uint8_t IPRev0; // 0x15E //RO + uint8_t IPRev1; // 0x15F //RO + uint8_t reserved7[4]; // 0x160/260 + uint16_t Scratch2; // 0x164/264 + uint16_t Scratch1; // 0x166/266 + uint8_t Ocr0; // 0x168/268 + uint8_t Ocr1; // 0x169/269 + uint8_t Ocr2; // 0x16A/26A + uint8_t Config; // 0x16B/26B + uint32_t Config2; // 0x16C/26C + uint32_t Debug; // 0x170/270 + uint32_t DmaAddr; // 0x174/274 + uint8_t IoPort[3]; // 0x178/278 +} __attribute__((packed)) HidSdio_RegMap_t, *pHidSdio_RegMap_t; + +// Common I/O Area Registers (CIA) Offset +// +// Bit Def. Host To Card Interrupt Event (Offset 0x100/200) +#define SDIO_HCR_CONFIG_HostPwrUp (1 << 1) + +// Bit Def. Host Transfer Status (Offset 0x128/228) +#define SDIO_CCR_HOST_INT_DnLdReStart (1 << 0) +#define SDIO_CCR_HOST_INT_UpLdReStart (1 << 1) +#define SDIO_CCR_HOST_INT_DnLdCRC_err (1 << 2) + +// Bit Def. Card To Host Interrupt Event (Offset 0x130/230) +#define SDIO_CCR_CS_DnLdRdy (1 << 0) +#define SDIO_CCR_CS_UpLdRdy (1 << 1) +#define SDIO_CCR_CS_ReadCISRdy (1 << 2) +#define SDIO_CCR_CS_IORdy (1 << 3) + +// Bit Def. Card Interrupt Mask (Offset 0x134/234) +#define SDIO_CCR_CIM_DnLdOvr (1 << 0) +#define SDIO_CCR_CIM_UpLdOvr (1 << 1) +#define SDIO_CCR_CIM_Abort (1 << 2) +#define SDIO_CCR_CIM_PwrDn (1 << 3) +#define SDIO_CCR_CIM_PwrUp (1 << 4) + +#define SDIO_CCR_CIM_MASK 0x0007 + +// Bit Def. Card Interrupt Status (Offset 0x138/238) +#define SDIO_CCR_CIC_DnLdOvr (1 << 0) +#define SDIO_CCR_CIC_UpLdOvr (1 << 1) +#define SDIO_CCR_CIC_Abort (1 << 2) +#define SDIO_CCR_CIC_PwrDn (1 << 3) +#define SDIO_CCR_CIC_PwrUp (1 << 4) + +#define SDIO_CCR_CIC_MASK 0x001F + +// Bit Def. Card Interrupt RSR (Offset 0x13C/23C) +#define SDIO_CCR_CIO_DnLdOvr (1 << 0) +#define SDIO_CCR_CIO_UpLdOvr (1 << 1) +#define SDIO_CCR_CIO_Abort (1 << 2) +#define SDIO_CCR_CIO_PwrDn (1 << 3) +#define SDIO_CCR_CIO_PwrUp (1 << 4) +#define SDIO_CCR_CIO_MASK 0x001F + +//Config2 register mask +#define CONFIG2_MSK 0x00000C00 + +//CardIntMode register mask + +#define CARD_INT_MODE_MSK 0x00000003 +#define HOST_INT_MSK 0x00000002 + +//============================================================================= +// PUBLIC MACROS +//============================================================================= + +#define BL_REGS8(x) (*(volatile unsigned char *)(x)) +#define BL_REGS16(x) (*(volatile unsigned short *)(x)) +#define BL_REGS32(x) (*(volatile unsigned long *)(x)) + +#define BL_READ_REGS8(reg, val) ((val) = BL_REGS8(reg)) +#define BL_READ_REGS16(reg, val) ((val) = BL_REGS16(reg)) +#define BL_READ_REGS32(reg, val) ((val) = BL_REGS32(reg)) +#define BL_READ_BYTE(reg, val) ((val) = BL_REGS8(reg)) +#define BL_READ_HWORD(reg, val) ((val) = BL_REGS16(reg)) /*half word; */ +#define BL_READ_WORD(reg, val) ((val) = BL_REGS32(reg)) /*32 bits */ + +#define BL_WRITE_REGS8(reg, val) (BL_REGS8(reg) = (val)) +#define BL_WRITE_REGS16(reg, val) (BL_REGS16(reg) = (val)) +#define BL_WRITE_REGS32(reg, val) (BL_REGS32(reg) = (val)) +#define BL_WRITE_BYTE(reg, val) (BL_REGS8(reg) = (val)) +#define BL_WRITE_HWORD(reg, val) (BL_REGS16(reg) = (val)) /*half word; */ +#define BL_WRITE_WORD(reg, val) (BL_REGS32(reg) = (val)) /*32 bits */ +// Write uint32 to a low 16-bit register and a high 16-bit register +#define WRITE2REGS(lo, hi, u32) \ + BL_WRITE_HWORD(lo, (uint16_t)((u32)&0xffff)); \ + BL_WRITE_HWORD(hi, (uint16_t)(((u32) >> 16) & 0xffff)) + +#define BL_REGS8_SETBITS(reg, val) (BL_REGS8(reg) |= (uint8)(val)) +#define BL_REGS16_SETBITS(reg, val) (BL_REGS16(reg) |= (uint16)(val)) +#define BL_REGS32_SETBITS(reg, val) (BL_REGS32(reg) |= (val)) +#define BL_REGS8_CLRBITS(reg, val) (BL_REGS8(reg) = (uint8)(BL_REGS8(reg) & ~(val))) +#define BL_REGS16_CLRBITS(reg, val) (BL_REGS16(reg) = (uint16)(BL_REGS16(reg) & ~(val))) +#define BL_REGS32_CLRBITS(reg, val) (BL_REGS32(reg) = (BL_REGS32(reg) & ~(val))) + +//============================================================================= +// ENUM TYPE DEFINITION +//============================================================================= + +/******************************************************************/ +/*! + * \enum SDIO_CMD_TYPE + * + *******************************************************************/ +typedef enum { + IOCTL_GET_CONFIG = 0, /*!< Get configuration info */ + + /* HID IOCTLs*/ + IOCTL_HID_GET_BLOCK_SIZE, /*!< Get Block size */ + +} SDIO_CMD_TYPE; + +//============================================================================= +// FUNCTION DECLARATION +//============================================================================= +extern void sdio_GEN_CARD2HOST_INT(uint32_t port_id, uint16_t value); +extern uint32_t sdio_ioctl(uint32_t port_id, SDIO_CMD_TYPE cmd, void *arg); + +//============================================================================= +// Variable DECLARATION +//============================================================================= +extern volatile pHidSdio_RegMap_t SdioFuncReg[]; +extern uint8_t flag_mport[]; +#endif /* __BL602_SDU_H__ */ diff --git a/drivers/soc/bl602/bl602_std/include/bl602_sf_cfg.h b/drivers/soc/bl602/bl602_std/include/bl602_sf_cfg.h new file mode 100644 index 00000000..cb2cd503 --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/bl602_sf_cfg.h @@ -0,0 +1,112 @@ +/** + ****************************************************************************** + * @file bl602_sf_cfg.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_SF_CFG_H__ +#define __BL602_SF_CFG_H__ + +#include "string.h" +#include "bl602_sflash.h" +#include "bl602_sf_ctrl.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CFG + * @{ + */ + +/** @defgroup SF_CFG_Public_Types + * @{ + */ + +/*@} end of group SF_CFG_Public_Types */ + +/** @defgroup SF_CFG_Public_Constants + * @{ + */ + +/*@} end of group SF_CFG_Public_Constants */ + +/** @defgroup SF_CFG_Public_Macros + * @{ + */ +/*Flash option 0*/ +/*Flash CLK*/ +#define BFLB_EXTFLASH_CLK0_GPIO GLB_GPIO_PIN_22 +/*FLASH CS*/ +#define BFLB_EXTFLASH_CS0_GPIO GLB_GPIO_PIN_21 +/*FLASH DATA*/ +#define BFLB_EXTFLASH_DATA00_GPIO GLB_GPIO_PIN_20 +#define BFLB_EXTFLASH_DATA10_GPIO GLB_GPIO_PIN_19 +#define BFLB_EXTFLASH_DATA20_GPIO GLB_GPIO_PIN_18 +#define BFLB_EXTFLASH_DATA30_GPIO GLB_GPIO_PIN_17 +/*Flash option 1*/ +/*Flash CLK*/ +#define BFLB_EXTFLASH_CLK1_GPIO GLB_GPIO_PIN_22 +/*FLASH CS*/ +#define BFLB_EXTFLASH_CS1_GPIO GLB_GPIO_PIN_21 +/*FLASH DATA*/ +#define BFLB_EXTFLASH_DATA01_GPIO GLB_GPIO_PIN_20 +#define BFLB_EXTFLASH_DATA11_GPIO GLB_GPIO_PIN_0 +#define BFLB_EXTFLASH_DATA21_GPIO GLB_GPIO_PIN_1 +#define BFLB_EXTFLASH_DATA31_GPIO GLB_GPIO_PIN_2 +#define BFLB_FLASH_CFG_DESWAP 1 +#define BFLB_FLASH_CFG_EXT0_17_22 2 +#define BFLB_FLASH_CFG_EXT1_0_2_20_22 3 +#define BFLB_FLASH_ID_VALID_FLAG 0x80000000 +#define BFLB_FLASH_ID_VALID_MASK 0x7FFFFFFF + +/*@} end of group SF_CFG_Public_Macros */ + +/** @defgroup SF_CFG_Public_Functions + * @{ + */ +BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg); +void SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg, uint8_t restoreDefault); +void SF_Cfg_Restore_GPIO17_Fun(uint8_t fun); +uint32_t SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, + SPI_Flash_Cfg_Type *pFlashCfg); +void SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin); +void SF_Cfg_Init_Internal_Flash_Gpio(void); +void SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin); + +/*@} end of group SF_CFG_Public_Functions */ + +/*@} end of group SF_CFG */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_SF_CFG_H__ */ diff --git a/drivers/soc/bl602/bl602_std/include/bl602_sf_cfg_ext.h b/drivers/soc/bl602/bl602_std/include/bl602_sf_cfg_ext.h new file mode 100644 index 00000000..f3fbdfcb --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/bl602_sf_cfg_ext.h @@ -0,0 +1,82 @@ +/** + ****************************************************************************** + * @file bl602_sf_cfg_ext.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_SF_CFG_EXT_H__ +#define __BL602_SF_CFG_EXT_H__ + +#include "string.h" +#include "bl602_sflash.h" +#include "bl602_sf_ctrl.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CFG_EXT + * @{ + */ + +/** @defgroup SF_CFG_EXT_Public_Types + * @{ + */ + +/*@} end of group SF_CFG_EXT_Public_Types */ + +/** @defgroup SF_CFG_EXT_Public_Constants + * @{ + */ + +/*@} end of group SF_CFG_EXT_Public_Constants */ + +/** @defgroup SF_CFG_EXT_Public_Macros + * @{ + */ + +/*@} end of group SF_CFG_EXT_Public_Macros */ + +/** @defgroup SF_CFG_EXT_Public_Functions + * @{ + */ +BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg); +uint32_t SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, + uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg); + +/*@} end of group SF_CFG_EXT_Public_Functions */ + +/*@} end of group SF_CFG_EXT */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_SF_CFG_EXT_H__ */ diff --git a/drivers/soc/bl602/bl602_std/include/bl602_sf_ctrl.h b/drivers/soc/bl602/bl602_std/include/bl602_sf_ctrl.h new file mode 100644 index 00000000..b5b882ea --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/bl602_sf_ctrl.h @@ -0,0 +1,327 @@ +/** + ****************************************************************************** + * @file bl602_sf_ctrl.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_SF_CTRL_H__ +#define __BL602_SF_CTRL_H__ + +#include "sf_ctrl_reg.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CTRL + * @{ + */ + +/** @defgroup SF_CTRL_Public_Types + * @{ + */ + +/** + * @brief Serial flash pad select type definition + */ +typedef enum { + SF_CTRL_EMBEDDED_SEL, /*!< Embedded flash select */ + SF_CTRL_EXTERNAL_17TO22_SEL, /*!< External flash select gpio 17-22 */ + SF_CTRL_EXTERNAL_0TO2_20TO22_SEL, /*!< External flash select gpio 0-2 and 20-22 */ +} SF_Ctrl_Pad_Sel; + +/** + * @brief Serial flash controller owner type definition + */ +typedef enum { + SF_CTRL_OWNER_SAHB, /*!< System AHB bus control serial flash controller */ + SF_CTRL_OWNER_IAHB, /*!< I-Code AHB bus control serial flash controller */ +} SF_Ctrl_Owner_Type; + +/** + * @brief Serial flash controller select clock type definition + */ +typedef enum { + SF_CTRL_SAHB_CLOCK, /*!< Serial flash controller select default sahb clock */ + SF_CTRL_FLASH_CLOCK, /*!< Serial flash controller select flash clock */ +} SF_Ctrl_Sahb_Type; + +/** + * @brief Serial flash controller owner type definition + */ +typedef enum { + HIGH_SPEED_MODE_CLOCK, /*!< Serial flash controller high speed mode clk_ahb>clk_sf */ + REMOVE_CLOCK_CONSTRAIN, /*!< Serial flash controller remove clock constrain */ +} SF_Ctrl_Ahb2sif_Type; + +/** + * @brief Read and write type definition + */ +typedef enum { + SF_CTRL_READ, /*!< Serail flash read command flag */ + SF_CTRL_WRITE, /*!< Serail flash write command flag */ +} SF_Ctrl_RW_Type; + +/** + * @brief Serail flash interface IO type definition + */ +typedef enum { + SF_CTRL_NIO_MODE, /*!< Normal IO mode define */ + SF_CTRL_DO_MODE, /*!< Dual Output mode define */ + SF_CTRL_QO_MODE, /*!< Quad Output mode define */ + SF_CTRL_DIO_MODE, /*!< Dual IO mode define */ + SF_CTRL_QIO_MODE, /*!< Quad IO mode define */ +} SF_Ctrl_IO_Type; + +/** + * @brief Serail flash controller interface mode type definition + */ +typedef enum { + SF_CTRL_SPI_MODE, /*!< SPI mode define */ + SF_CTRL_QPI_MODE, /*!< QPI mode define */ +} SF_Ctrl_Mode_Type; + +/** + * @brief Serail flash controller command mode type definition + */ +typedef enum { + SF_CTRL_CMD_1_LINE, /*!< Command in one line mode */ + SF_CTRL_CMD_4_LINES, /*!< Command in four lines mode */ +} SF_Ctrl_Cmd_Mode_Type; + +/** + * @brief Serail flash controller address mode type definition + */ +typedef enum { + SF_CTRL_ADDR_1_LINE, /*!< Address in one line mode */ + SF_CTRL_ADDR_2_LINES, /*!< Address in two lines mode */ + SF_CTRL_ADDR_4_LINES, /*!< Address in four lines mode */ +} SF_Ctrl_Addr_Mode_Type; + +/** + * @brief Serail flash controller dummy mode type definition + */ +typedef enum { + SF_CTRL_DUMMY_1_LINE, /*!< Dummy in one line mode */ + SF_CTRL_DUMMY_2_LINES, /*!< Dummy in two lines mode */ + SF_CTRL_DUMMY_4_LINES, /*!< Dummy in four lines mode */ +} SF_Ctrl_Dmy_Mode_Type; + +/** + * @brief Serail flash controller data mode type definition + */ +typedef enum { + SF_CTRL_DATA_1_LINE, /*!< Data in one line mode */ + SF_CTRL_DATA_2_LINES, /*!< Data in two lines mode */ + SF_CTRL_DATA_4_LINES, /*!< Data in four lines mode */ +} SF_Ctrl_Data_Mode_Type; + +/** + * @brief Serail flash controller AES type definition + */ +typedef enum { + SF_CTRL_AES_128BITS, /*!< Serail flash AES key 128 bits length */ + SF_CTRL_AES_256BITS, /*!< Serail flash AES key 256 bits length */ + SF_CTRL_AES_192BITS, /*!< Serail flash AES key 192 bits length */ + SF_CTRL_AES_128BITS_DOUBLE_KEY, /*!< Serail flash AES key 128 bits length double key */ +} SF_Ctrl_AES_Key_Type; + +/** + * @brief Serail flash controller configuration structure type definition + */ +typedef struct +{ + SF_Ctrl_Owner_Type owner; /*!< Sflash interface bus owner */ + SF_Ctrl_Sahb_Type sahbClock; /*!< Sflash clock sahb sram select */ + SF_Ctrl_Ahb2sif_Type ahb2sifMode; /*!< Sflash ahb2sif mode */ + uint8_t clkDelay; /*!< Clock count for read due to pad delay */ + uint8_t clkInvert; /*!< Clock invert */ + uint8_t rxClkInvert; /*!< RX clock invert */ + uint8_t doDelay; /*!< Data out delay */ + uint8_t diDelay; /*!< Data in delay */ + uint8_t oeDelay; /*!< Output enable delay */ +} SF_Ctrl_Cfg_Type; + +/** + * @brief Serail flash command configuration structure type definition + */ +typedef struct +{ + uint8_t rwFlag; /*!< Read write flag */ + SF_Ctrl_Cmd_Mode_Type cmdMode; /*!< Command mode */ + SF_Ctrl_Addr_Mode_Type addrMode; /*!< Address mode */ + uint8_t addrSize; /*!< Address size */ + uint8_t dummyClks; /*!< Dummy clocks */ + SF_Ctrl_Dmy_Mode_Type dummyMode; /*!< Dummy mode */ + SF_Ctrl_Data_Mode_Type dataMode; /*!< Data mode */ + uint8_t rsv[1]; /*!< */ + uint32_t nbData; /*!< Transfer number of bytes */ + uint32_t cmdBuf[2]; /*!< Command buffer */ +} SF_Ctrl_Cmd_Cfg_Type; + +/*@} end of group SF_CTRL_Public_Types */ + +/** @defgroup SF_CTRL_Public_Constants + * @{ + */ + +/** @defgroup SF_CTRL_PAD_SEL + * @{ + */ +#define IS_SF_CTRL_PAD_SEL(type) (((type) == SF_CTRL_EMBEDDED_SEL) || \ + ((type) == SF_CTRL_EXTERNAL_17TO22_SEL) || \ + ((type) == SF_CTRL_EXTERNAL_0TO2_20TO22_SEL)) + +/** @defgroup SF_CTRL_OWNER_TYPE + * @{ + */ +#define IS_SF_CTRL_OWNER_TYPE(type) (((type) == SF_CTRL_OWNER_SAHB) || \ + ((type) == SF_CTRL_OWNER_IAHB)) + +/** @defgroup SF_CTRL_SAHB_TYPE + * @{ + */ +#define IS_SF_CTRL_SAHB_TYPE(type) (((type) == SF_CTRL_SAHB_CLOCK) || \ + ((type) == SF_CTRL_FLASH_CLOCK)) + +/** @defgroup SF_CTRL_AHB2SIF_TYPE + * @{ + */ +#define IS_SF_CTRL_AHB2SIF_TYPE(type) (((type) == HIGH_SPEED_MODE_CLOCK) || \ + ((type) == REMOVE_CLOCK_CONSTRAIN)) + +/** @defgroup SF_CTRL_RW_TYPE + * @{ + */ +#define IS_SF_CTRL_RW_TYPE(type) (((type) == SF_CTRL_READ) || \ + ((type) == SF_CTRL_WRITE)) + +/** @defgroup SF_CTRL_IO_TYPE + * @{ + */ +#define IS_SF_CTRL_IO_TYPE(type) (((type) == SF_CTRL_NIO_MODE) || \ + ((type) == SF_CTRL_DO_MODE) || \ + ((type) == SF_CTRL_QO_MODE) || \ + ((type) == SF_CTRL_DIO_MODE) || \ + ((type) == SF_CTRL_QIO_MODE)) + +/** @defgroup SF_CTRL_MODE_TYPE + * @{ + */ +#define IS_SF_CTRL_MODE_TYPE(type) (((type) == SF_CTRL_SPI_MODE) || \ + ((type) == SF_CTRL_QPI_MODE)) + +/** @defgroup SF_CTRL_CMD_MODE_TYPE + * @{ + */ +#define IS_SF_CTRL_CMD_MODE_TYPE(type) (((type) == SF_CTRL_CMD_1_LINE) || \ + ((type) == SF_CTRL_CMD_4_LINES)) + +/** @defgroup SF_CTRL_ADDR_MODE_TYPE + * @{ + */ +#define IS_SF_CTRL_ADDR_MODE_TYPE(type) (((type) == SF_CTRL_ADDR_1_LINE) || \ + ((type) == SF_CTRL_ADDR_2_LINES) || \ + ((type) == SF_CTRL_ADDR_4_LINES)) + +/** @defgroup SF_CTRL_DMY_MODE_TYPE + * @{ + */ +#define IS_SF_CTRL_DMY_MODE_TYPE(type) (((type) == SF_CTRL_DUMMY_1_LINE) || \ + ((type) == SF_CTRL_DUMMY_2_LINES) || \ + ((type) == SF_CTRL_DUMMY_4_LINES)) + +/** @defgroup SF_CTRL_DATA_MODE_TYPE + * @{ + */ +#define IS_SF_CTRL_DATA_MODE_TYPE(type) (((type) == SF_CTRL_DATA_1_LINE) || \ + ((type) == SF_CTRL_DATA_2_LINES) || \ + ((type) == SF_CTRL_DATA_4_LINES)) + +/** @defgroup SF_CTRL_AES_KEY_TYPE + * @{ + */ +#define IS_SF_CTRL_AES_KEY_TYPE(type) (((type) == SF_CTRL_AES_128BITS) || \ + ((type) == SF_CTRL_AES_256BITS) || \ + ((type) == SF_CTRL_AES_192BITS) || \ + ((type) == SF_CTRL_AES_128BITS_DOUBLE_KEY)) + +/*@} end of group SF_CTRL_Public_Constants */ + +/** @defgroup SF_CTRL_Public_Macros + * @{ + */ +#define SF_CTRL_NO_ADDRESS 0xFFFFFFFF +#define FLASH_CTRL_BUF_SIZE 256 + +/*@} end of group SF_CTRL_Public_Macros */ + +/** @defgroup SF_CTRL_Public_Functions + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +void SF_Ctrl_IRQHandler(void); +#endif +void SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg); +void SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner); +void SF_Ctrl_Disable(void); +void SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Sel sel); +void SF_Ctrl_AES_Enable_BE(void); +void SF_Ctrl_AES_Enable_LE(void); +void SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, + uint32_t endAddr, + uint8_t locked); +void SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); +void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); +void SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset); +void SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset); +void SF_Ctrl_AES_Enable(void); +void SF_Ctrl_AES_Disable(void); +void SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset); +uint32_t SF_Ctrl_Get_Flash_Image_Offset(void); +void SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType); +void SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg); +void SF_Ctrl_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid); +void SF_Ctrl_Icache2_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid); +BL_Sts_Type SF_Ctrl_GetBusyState(void); +uint8_t SF_Ctrl_Is_AES_Enable(void); +uint8_t SF_Ctrl_Get_Clock_Delay(void); +void SF_Ctrl_Set_Clock_Delay(uint8_t delay); + +/*@} end of group SF_CTRL_Public_Functions */ + +/*@} end of group SF_CTRL */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_SF_CTRL_H__ */ diff --git a/drivers/soc/bl602/bl602_std/include/bl602_sflash.h b/drivers/soc/bl602/bl602_std/include/bl602_sflash.h new file mode 100644 index 00000000..ec5bd82d --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/bl602_sflash.h @@ -0,0 +1,199 @@ +/** + ****************************************************************************** + * @file bl602_sflah.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_SFLAH_H__ +#define __BL602_SFLAH_H__ + +#include "bl602_common.h" +#include "bl602_sf_ctrl.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SFLAH + * @{ + */ + +/** @defgroup SFLAH_Public_Types + * @{ + */ + +/** + * @brief Serial flash configuration structure type definition + */ +typedef struct +{ + uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ + uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ + uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ + uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ + uint8_t resetEnCmd; /*!< Flash enable reset command */ + uint8_t resetCmd; /*!< Flash reset command */ + uint8_t resetCreadCmd; /*!< Flash reset continuous read command */ + uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */ + uint8_t jedecIdCmd; /*!< JEDEC ID command */ + uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */ + uint8_t qpiJedecIdCmd; /*!< QPI JEDEC ID comamnd */ + uint8_t qpiJedecIdCmdDmyClk; /*!< QPI JEDEC ID command dummy clock */ + uint8_t sectorSize; /*!< *1024bytes */ + uint8_t mid; /*!< Manufacturer ID */ + uint16_t pageSize; /*!< Page size */ + uint8_t chipEraseCmd; /*!< Chip erase cmd */ + uint8_t sectorEraseCmd; /*!< Sector erase command */ + uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */ + uint8_t blk64EraseCmd; /*!< Block 64K erase command */ + uint8_t writeEnableCmd; /*!< Need before every erase or program */ + uint8_t pageProgramCmd; /*!< Page program cmd */ + uint8_t qpageProgramCmd; /*!< QIO page program cmd */ + uint8_t qppAddrMode; /*!< QIO page program address mode */ + uint8_t fastReadCmd; /*!< Fast read command */ + uint8_t frDmyClk; /*!< Fast read command dummy clock */ + uint8_t qpiFastReadCmd; /*!< QPI fast read command */ + uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */ + uint8_t fastReadDoCmd; /*!< Fast read dual output command */ + uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */ + uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */ + uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */ + uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */ + uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */ + uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */ + uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */ + uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */ + uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */ + uint8_t qpiPageProgramCmd; /*!< QPI program command */ + uint8_t writeVregEnableCmd; /*!< Enable write reg */ + uint8_t wrEnableIndex; /*!< Write enable register index */ + uint8_t qeIndex; /*!< Quad mode enable register index */ + uint8_t busyIndex; /*!< Busy status register index */ + uint8_t wrEnableBit; /*!< Write enable bit pos */ + uint8_t qeBit; /*!< Quad enable bit pos */ + uint8_t busyBit; /*!< Busy status bit pos */ + uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */ + uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */ + uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */ + uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */ + uint8_t releasePowerDown; /*!< Release power down command */ + uint8_t busyReadRegLen; /*!< Register length of contain busy status */ + uint8_t readRegCmd[4]; /*!< Read register command buffer */ + uint8_t writeRegCmd[4]; /*!< Write register command buffer */ + uint8_t enterQpi; /*!< Enter qpi command */ + uint8_t exitQpi; /*!< Exit qpi command */ + uint8_t cReadMode; /*!< Config data for continuous read mode */ + uint8_t cRExit; /*!< Config data for exit continuous read mode */ + uint8_t burstWrapCmd; /*!< Enable burst wrap command */ + uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */ + uint8_t burstWrapDataMode; /*!< Data and address mode for this command */ + uint8_t burstWrapData; /*!< Data to enable burst wrap */ + uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */ + uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */ + uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */ + uint8_t deBurstWrapData; /*!< Data to disable burst wrap */ + uint16_t timeEsector; /*!< 4K erase time */ + uint16_t timeE32k; /*!< 32K erase time */ + uint16_t timeE64k; /*!< 64K erase time */ + uint16_t timePagePgm; /*!< Page program time */ + uint16_t timeCe; /*!< Chip erase time in ms */ + uint8_t pdDelay; /*!< Release power down command delay time for wake up */ + uint8_t qeData; /*!< QE set data */ +} __attribute__((packed)) SPI_Flash_Cfg_Type; + +/*@} end of group SFLAH_Public_Types */ + +/** @defgroup SFLAH_Public_Constants + * @{ + */ + +/*@} end of group SFLAH_Public_Constants */ + +/** @defgroup SFLAH_Public_Macros + * @{ + */ +#define BFLB_SPIFLASH_BLK32K_SIZE (32 * 1024) +#define BFLB_SPIFLASH_BLK64K_SIZE (64 * 1024) +#define BFLB_SPIFLASH_CMD_INVALID 0xff + +/*@} end of group SFLAH_Public_Macros */ + +/** @defgroup SFLAH_Public_Functions + * @{ + */ +void SFlash_Init(const SF_Ctrl_Cfg_Type *sfCtrlCfg); +BL_Err_Type SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode); +BL_Err_Type SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen); +BL_Err_Type SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen); +BL_Sts_Type SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg); +void SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum); +BL_Err_Type SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum); +BL_Err_Type SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum); +BL_Err_Type SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr); +BL_Err_Type SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len); +void SFlash_GetUniqueId(uint8_t *data, uint8_t idLen); +void SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data); +void SFlash_GetDeviceId(uint8_t *data); +void SFlash_Powerdown(void); +void SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg); +void SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg); +void SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg); +void SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg); +BL_Err_Type SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, + uint32_t len); +BL_Err_Type SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead); +BL_Err_Type SFlash_Cache_Enable_Set(uint8_t wayDisable); +BL_Err_Type SFlash_Cache_Flush(void); +BL_Err_Type SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, + uint8_t wayDisable); +void SFlash_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh); +uint32_t SFlash_Cache_Miss_Count_Get(void); +void SFlash_Cache_Read_Disable(void); +BL_Err_Type SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, + uint32_t len); +BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, + uint8_t regLen); +BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, + uint8_t regLen); + +/*@} end of group SFLAH_Public_Functions */ + +/*@} end of group SFLAH */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_SFLAH_H__ */ diff --git a/drivers/soc/bl602/bl602_std/include/bl602_sflash_ext.h b/drivers/soc/bl602/bl602_std/include/bl602_sflash_ext.h new file mode 100644 index 00000000..817e9260 --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/bl602_sflash_ext.h @@ -0,0 +1,101 @@ +/** + ****************************************************************************** + * @file bl602_sflah_ext.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_SFLAH_EXT_H__ +#define __BL602_SFLAH_EXT_H__ + +#include "bl602_sflash.h" +#include "bl602_common.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup SFLAH_EXT + * @{ + */ + +/** @defgroup SFLAH_EXT_Public_Types + * @{ + */ + +/** + * @brief Serial flash security register configuration + */ +typedef struct +{ + uint8_t eraseCmd; /*!< Erase security register command */ + uint8_t programCmd; /*!< Program security register command */ + uint8_t readCmd; /*!< Read security register command */ + uint8_t enterSecOptCmd; /*!< Enter security register option mode command */ + uint8_t exitSecOptCmd; /*!< Exit security register option mode command */ + uint8_t blockNum; /*!< Security register block number */ + uint8_t *data; /*!< Data pointer to be program/read */ + uint32_t addr; /*!< Start address to be program/read */ + uint32_t len; /*!< Data length to be program/read */ +} SFlash_Sec_Reg_Cfg; + +/*@} end of group SFLAH_EXT_Public_Types */ + +/** @defgroup SFLAH_EXT_Public_Constants + * @{ + */ + +/*@} end of group SFLAH_EXT_Public_Constants */ + +/** @defgroup SFLAH_EXT_Public_Macros + * @{ + */ + +/*@} end of group SFLAH_EXT_Public_Macros */ + +/** @defgroup SFLAH_EXT_Public_Functions + * @{ + */ +BL_Err_Type SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead); +BL_Err_Type SFlash_RCV_Enable(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos); +BL_Err_Type SFlash_Erase_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg); +BL_Err_Type SFlash_Program_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, + SFlash_Sec_Reg_Cfg *pSecRegCfg); +BL_Err_Type SFlash_Read_Security_Register(SFlash_Sec_Reg_Cfg *pSecRegCfg); +BL_Err_Type SFlash_Clear_Status_Register(SPI_Flash_Cfg_Type *pFlashCfg); + +/*@} end of group SFLAH_EXT_Public_Functions */ + +/*@} end of group SFLAH_EXT */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_SFLAH_EXT_H__ */ diff --git a/drivers/soc/bl602/bl602_std/include/bl602_xip_sflash.h b/drivers/soc/bl602/bl602_std/include/bl602_xip_sflash.h new file mode 100644 index 00000000..aa3d2b56 --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/bl602_xip_sflash.h @@ -0,0 +1,90 @@ +/** + ****************************************************************************** + * @file bl602_xip_sflash.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_XIP_SFLASH_H__ +#define __BL602_XIP_SFLASH_H__ + +#include "bl602_common.h" +#include "bl602_sflash.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup XIP_SFLASH + * @{ + */ + +/** @defgroup XIP_SFLASH_Public_Types + * @{ + */ + +/*@} end of group XIP_SFLASH_Public_Types */ + +/** @defgroup XIP_SFLASH_Public_Constants + * @{ + */ + +/*@} end of group XIP_SFLASH_Public_Constants */ + +/** @defgroup XIP_SFLASH_Public_Macros + * @{ + */ + +/*@} end of group XIP_SFLASH_Public_Macros */ + +/** @defgroup XIP_SFLASH_Public_Functions + * @{ + */ +BL_Err_Type XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset); +BL_Err_Type XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset); +BL_Err_Type XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, uint32_t endaddr); +BL_Err_Type XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, + uint32_t len); +BL_Err_Type XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len); +BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data); +BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data); +BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen); +BL_Err_Type XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len); +void XIP_SFlash_Opt_Enter(uint8_t *aesEnable); +void XIP_SFlash_Opt_Exit(uint8_t aesEnable); + +/*@} end of group XIP_SFLASH_Public_Functions */ + +/*@} end of group XIP_SFLASH */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_XIP_SFLASH_H__ */ diff --git a/drivers/soc/bl602/bl602_std/include/bl602_xip_sflash_ext.h b/drivers/soc/bl602/bl602_std/include/bl602_xip_sflash_ext.h new file mode 100644 index 00000000..d73bf5c5 --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/bl602_xip_sflash_ext.h @@ -0,0 +1,95 @@ +/** + ****************************************************************************** + * @file bl602_xip_sflash_ext.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL602_XIP_SFLASH_EXT_H__ +#define __BL602_XIP_SFLASH_EXT_H__ + +#include "bl602_common.h" +#include "bl602_sflash.h" +#include "bl602_sflash_ext.h" +#include "bl602_xip_sflash.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup XIP_SFLASH_EXT + * @{ + */ + +/** @defgroup XIP_SFLASH_EXT_Public_Types + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Public_Types */ + +/** @defgroup XIP_SFLASH_EXT_Public_Constants + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Public_Constants */ + +/** @defgroup XIP_SFLASH_EXT_Public_Macros + * @{ + */ + +/*@} end of group XIP_SFLASH_EXT_Public_Macros */ + +/** @defgroup XIP_SFLASH_EXT_Public_Functions + * @{ + */ +BL_Err_Type XIP_SFlash_State_Restore_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t offset); +BL_Err_Type XIP_SFlash_Erase_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t startaddr, + uint32_t endaddr); +BL_Err_Type XIP_SFlash_Write_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr,uint8_t *data, + uint32_t len); +BL_Err_Type XIP_SFlash_Read_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr,uint8_t *data, + uint32_t len); +BL_Err_Type XIP_SFlash_Clear_Status_Register_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg); +BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data); +BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data); +BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data, + uint8_t idLen); +BL_Err_Type XIP_SFlash_RCV_Enable_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, + uint8_t bitPos); +BL_Err_Type XIP_SFlash_Init(SPI_Flash_Cfg_Type *pFlashCfg); + +/*@} end of group XIP_SFLASH_EXT_Public_Functions */ + +/*@} end of group XIP_SFLASH_EXT */ + +/*@} end of group BL602_Peripheral_Driver */ + +#endif /* __BL602_XIP_SFLASH_EXT_H__ */ diff --git a/drivers/soc/bl602/bl602_std/include/hardware/aon_reg.h b/drivers/soc/bl602/bl602_std/include/hardware/aon_reg.h new file mode 100644 index 00000000..993e0604 --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/hardware/aon_reg.h @@ -0,0 +1,1560 @@ +/** + ****************************************************************************** + * @file aon_reg.h + * @version V1.2 + * @date 2020-04-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __AON_REG_H__ +#define __AON_REG_H__ + +#include "bl602.h" + +/* 0x800 : aon */ +#define AON_OFFSET (0x800) +#define AON_RESV AON_RESV +#define AON_RESV_POS (0U) +#define AON_RESV_LEN (8U) +#define AON_RESV_MSK (((1U << AON_RESV_LEN) - 1) << AON_RESV_POS) +#define AON_RESV_UMSK (~(((1U << AON_RESV_LEN) - 1) << AON_RESV_POS)) +#define AON_PU_AON_DC_TBUF AON_PU_AON_DC_TBUF +#define AON_PU_AON_DC_TBUF_POS (12U) +#define AON_PU_AON_DC_TBUF_LEN (1U) +#define AON_PU_AON_DC_TBUF_MSK (((1U << AON_PU_AON_DC_TBUF_LEN) - 1) << AON_PU_AON_DC_TBUF_POS) +#define AON_PU_AON_DC_TBUF_UMSK (~(((1U << AON_PU_AON_DC_TBUF_LEN) - 1) << AON_PU_AON_DC_TBUF_POS)) +#define AON_LDO11_RT_PULLDOWN AON_LDO11_RT_PULLDOWN +#define AON_LDO11_RT_PULLDOWN_POS (20U) +#define AON_LDO11_RT_PULLDOWN_LEN (1U) +#define AON_LDO11_RT_PULLDOWN_MSK (((1U << AON_LDO11_RT_PULLDOWN_LEN) - 1) << AON_LDO11_RT_PULLDOWN_POS) +#define AON_LDO11_RT_PULLDOWN_UMSK (~(((1U << AON_LDO11_RT_PULLDOWN_LEN) - 1) << AON_LDO11_RT_PULLDOWN_POS)) +#define AON_LDO11_RT_PULLDOWN_SEL AON_LDO11_RT_PULLDOWN_SEL +#define AON_LDO11_RT_PULLDOWN_SEL_POS (21U) +#define AON_LDO11_RT_PULLDOWN_SEL_LEN (1U) +#define AON_LDO11_RT_PULLDOWN_SEL_MSK (((1U << AON_LDO11_RT_PULLDOWN_SEL_LEN) - 1) << AON_LDO11_RT_PULLDOWN_SEL_POS) +#define AON_LDO11_RT_PULLDOWN_SEL_UMSK (~(((1U << AON_LDO11_RT_PULLDOWN_SEL_LEN) - 1) << AON_LDO11_RT_PULLDOWN_SEL_POS)) +#define AON_SW_PU_LDO11_RT AON_SW_PU_LDO11_RT +#define AON_SW_PU_LDO11_RT_POS (22U) +#define AON_SW_PU_LDO11_RT_LEN (1U) +#define AON_SW_PU_LDO11_RT_MSK (((1U << AON_SW_PU_LDO11_RT_LEN) - 1) << AON_SW_PU_LDO11_RT_POS) +#define AON_SW_PU_LDO11_RT_UMSK (~(((1U << AON_SW_PU_LDO11_RT_LEN) - 1) << AON_SW_PU_LDO11_RT_POS)) + +/* 0x804 : aon_common */ +#define AON_COMMON_OFFSET (0x804) +#define AON_TMUX_AON AON_TMUX_AON +#define AON_TMUX_AON_POS (0U) +#define AON_TMUX_AON_LEN (3U) +#define AON_TMUX_AON_MSK (((1U << AON_TMUX_AON_LEN) - 1) << AON_TMUX_AON_POS) +#define AON_TMUX_AON_UMSK (~(((1U << AON_TMUX_AON_LEN) - 1) << AON_TMUX_AON_POS)) +#define AON_TEN_AON AON_TEN_AON +#define AON_TEN_AON_POS (4U) +#define AON_TEN_AON_LEN (1U) +#define AON_TEN_AON_MSK (((1U << AON_TEN_AON_LEN) - 1) << AON_TEN_AON_POS) +#define AON_TEN_AON_UMSK (~(((1U << AON_TEN_AON_LEN) - 1) << AON_TEN_AON_POS)) +#define AON_DTEN_XTAL32K AON_DTEN_XTAL32K +#define AON_DTEN_XTAL32K_POS (5U) +#define AON_DTEN_XTAL32K_LEN (1U) +#define AON_DTEN_XTAL32K_MSK (((1U << AON_DTEN_XTAL32K_LEN) - 1) << AON_DTEN_XTAL32K_POS) +#define AON_DTEN_XTAL32K_UMSK (~(((1U << AON_DTEN_XTAL32K_LEN) - 1) << AON_DTEN_XTAL32K_POS)) +#define AON_TEN_XTAL32K AON_TEN_XTAL32K +#define AON_TEN_XTAL32K_POS (6U) +#define AON_TEN_XTAL32K_LEN (1U) +#define AON_TEN_XTAL32K_MSK (((1U << AON_TEN_XTAL32K_LEN) - 1) << AON_TEN_XTAL32K_POS) +#define AON_TEN_XTAL32K_UMSK (~(((1U << AON_TEN_XTAL32K_LEN) - 1) << AON_TEN_XTAL32K_POS)) +#define AON_TEN_VDDCORE_AON AON_TEN_VDDCORE_AON +#define AON_TEN_VDDCORE_AON_POS (8U) +#define AON_TEN_VDDCORE_AON_LEN (1U) +#define AON_TEN_VDDCORE_AON_MSK (((1U << AON_TEN_VDDCORE_AON_LEN) - 1) << AON_TEN_VDDCORE_AON_POS) +#define AON_TEN_VDDCORE_AON_UMSK (~(((1U << AON_TEN_VDDCORE_AON_LEN) - 1) << AON_TEN_VDDCORE_AON_POS)) +#define AON_TEN_LDO11SOC_AON AON_TEN_LDO11SOC_AON +#define AON_TEN_LDO11SOC_AON_POS (9U) +#define AON_TEN_LDO11SOC_AON_LEN (1U) +#define AON_TEN_LDO11SOC_AON_MSK (((1U << AON_TEN_LDO11SOC_AON_LEN) - 1) << AON_TEN_LDO11SOC_AON_POS) +#define AON_TEN_LDO11SOC_AON_UMSK (~(((1U << AON_TEN_LDO11SOC_AON_LEN) - 1) << AON_TEN_LDO11SOC_AON_POS)) +#define AON_TEN_DCDC18_0_AON AON_TEN_DCDC18_0_AON +#define AON_TEN_DCDC18_0_AON_POS (10U) +#define AON_TEN_DCDC18_0_AON_LEN (1U) +#define AON_TEN_DCDC18_0_AON_MSK (((1U << AON_TEN_DCDC18_0_AON_LEN) - 1) << AON_TEN_DCDC18_0_AON_POS) +#define AON_TEN_DCDC18_0_AON_UMSK (~(((1U << AON_TEN_DCDC18_0_AON_LEN) - 1) << AON_TEN_DCDC18_0_AON_POS)) +#define AON_TEN_DCDC18_1_AON AON_TEN_DCDC18_1_AON +#define AON_TEN_DCDC18_1_AON_POS (11U) +#define AON_TEN_DCDC18_1_AON_LEN (1U) +#define AON_TEN_DCDC18_1_AON_MSK (((1U << AON_TEN_DCDC18_1_AON_LEN) - 1) << AON_TEN_DCDC18_1_AON_POS) +#define AON_TEN_DCDC18_1_AON_UMSK (~(((1U << AON_TEN_DCDC18_1_AON_LEN) - 1) << AON_TEN_DCDC18_1_AON_POS)) +#define AON_TEN_BG_SYS_AON AON_TEN_BG_SYS_AON +#define AON_TEN_BG_SYS_AON_POS (12U) +#define AON_TEN_BG_SYS_AON_LEN (1U) +#define AON_TEN_BG_SYS_AON_MSK (((1U << AON_TEN_BG_SYS_AON_LEN) - 1) << AON_TEN_BG_SYS_AON_POS) +#define AON_TEN_BG_SYS_AON_UMSK (~(((1U << AON_TEN_BG_SYS_AON_LEN) - 1) << AON_TEN_BG_SYS_AON_POS)) +#define AON_TEN_LDO15RF_AON AON_TEN_LDO15RF_AON +#define AON_TEN_LDO15RF_AON_POS (16U) +#define AON_TEN_LDO15RF_AON_LEN (1U) +#define AON_TEN_LDO15RF_AON_MSK (((1U << AON_TEN_LDO15RF_AON_LEN) - 1) << AON_TEN_LDO15RF_AON_POS) +#define AON_TEN_LDO15RF_AON_UMSK (~(((1U << AON_TEN_LDO15RF_AON_LEN) - 1) << AON_TEN_LDO15RF_AON_POS)) +#define AON_TEN_XTAL_AON AON_TEN_XTAL_AON +#define AON_TEN_XTAL_AON_POS (17U) +#define AON_TEN_XTAL_AON_LEN (1U) +#define AON_TEN_XTAL_AON_MSK (((1U << AON_TEN_XTAL_AON_LEN) - 1) << AON_TEN_XTAL_AON_POS) +#define AON_TEN_XTAL_AON_UMSK (~(((1U << AON_TEN_XTAL_AON_LEN) - 1) << AON_TEN_XTAL_AON_POS)) +#define AON_DTEN_XTAL_AON AON_DTEN_XTAL_AON +#define AON_DTEN_XTAL_AON_POS (18U) +#define AON_DTEN_XTAL_AON_LEN (1U) +#define AON_DTEN_XTAL_AON_MSK (((1U << AON_DTEN_XTAL_AON_LEN) - 1) << AON_DTEN_XTAL_AON_POS) +#define AON_DTEN_XTAL_AON_UMSK (~(((1U << AON_DTEN_XTAL_AON_LEN) - 1) << AON_DTEN_XTAL_AON_POS)) +#define AON_TEN_MBG_AON AON_TEN_MBG_AON +#define AON_TEN_MBG_AON_POS (19U) +#define AON_TEN_MBG_AON_LEN (1U) +#define AON_TEN_MBG_AON_MSK (((1U << AON_TEN_MBG_AON_LEN) - 1) << AON_TEN_MBG_AON_POS) +#define AON_TEN_MBG_AON_UMSK (~(((1U << AON_TEN_MBG_AON_LEN) - 1) << AON_TEN_MBG_AON_POS)) +#define AON_TEN_CIP_MISC_AON AON_TEN_CIP_MISC_AON +#define AON_TEN_CIP_MISC_AON_POS (20U) +#define AON_TEN_CIP_MISC_AON_LEN (1U) +#define AON_TEN_CIP_MISC_AON_MSK (((1U << AON_TEN_CIP_MISC_AON_LEN) - 1) << AON_TEN_CIP_MISC_AON_POS) +#define AON_TEN_CIP_MISC_AON_UMSK (~(((1U << AON_TEN_CIP_MISC_AON_LEN) - 1) << AON_TEN_CIP_MISC_AON_POS)) + +/* 0x808 : aon_misc */ +#define AON_MISC_OFFSET (0x808) +#define AON_SW_SOC_EN_AON AON_SW_SOC_EN_AON +#define AON_SW_SOC_EN_AON_POS (0U) +#define AON_SW_SOC_EN_AON_LEN (1U) +#define AON_SW_SOC_EN_AON_MSK (((1U << AON_SW_SOC_EN_AON_LEN) - 1) << AON_SW_SOC_EN_AON_POS) +#define AON_SW_SOC_EN_AON_UMSK (~(((1U << AON_SW_SOC_EN_AON_LEN) - 1) << AON_SW_SOC_EN_AON_POS)) +#define AON_SW_WB_EN_AON AON_SW_WB_EN_AON +#define AON_SW_WB_EN_AON_POS (1U) +#define AON_SW_WB_EN_AON_LEN (1U) +#define AON_SW_WB_EN_AON_MSK (((1U << AON_SW_WB_EN_AON_LEN) - 1) << AON_SW_WB_EN_AON_POS) +#define AON_SW_WB_EN_AON_UMSK (~(((1U << AON_SW_WB_EN_AON_LEN) - 1) << AON_SW_WB_EN_AON_POS)) + +/* 0x810 : bg_sys_top */ +#define AON_BG_SYS_TOP_OFFSET (0x810) +#define AON_PMIP_RESV AON_PMIP_RESV +#define AON_PMIP_RESV_POS (0U) +#define AON_PMIP_RESV_LEN (8U) +#define AON_PMIP_RESV_MSK (((1U << AON_PMIP_RESV_LEN) - 1) << AON_PMIP_RESV_POS) +#define AON_PMIP_RESV_UMSK (~(((1U << AON_PMIP_RESV_LEN) - 1) << AON_PMIP_RESV_POS)) +#define AON_PU_BG_SYS_AON AON_PU_BG_SYS_AON +#define AON_PU_BG_SYS_AON_POS (8U) +#define AON_PU_BG_SYS_AON_LEN (1U) +#define AON_PU_BG_SYS_AON_MSK (((1U << AON_PU_BG_SYS_AON_LEN) - 1) << AON_PU_BG_SYS_AON_POS) +#define AON_PU_BG_SYS_AON_UMSK (~(((1U << AON_PU_BG_SYS_AON_LEN) - 1) << AON_PU_BG_SYS_AON_POS)) +#define AON_BG_SYS_START_CTRL_AON AON_BG_SYS_START_CTRL_AON +#define AON_BG_SYS_START_CTRL_AON_POS (12U) +#define AON_BG_SYS_START_CTRL_AON_LEN (1U) +#define AON_BG_SYS_START_CTRL_AON_MSK (((1U << AON_BG_SYS_START_CTRL_AON_LEN) - 1) << AON_BG_SYS_START_CTRL_AON_POS) +#define AON_BG_SYS_START_CTRL_AON_UMSK (~(((1U << AON_BG_SYS_START_CTRL_AON_LEN) - 1) << AON_BG_SYS_START_CTRL_AON_POS)) + +/* 0x814 : dcdc18_top_0 */ +#define AON_DCDC18_TOP_0_OFFSET (0x814) +#define AON_DCDC18_VOUT_SEL_AON AON_DCDC18_VOUT_SEL_AON +#define AON_DCDC18_VOUT_SEL_AON_POS (1U) +#define AON_DCDC18_VOUT_SEL_AON_LEN (5U) +#define AON_DCDC18_VOUT_SEL_AON_MSK (((1U << AON_DCDC18_VOUT_SEL_AON_LEN) - 1) << AON_DCDC18_VOUT_SEL_AON_POS) +#define AON_DCDC18_VOUT_SEL_AON_UMSK (~(((1U << AON_DCDC18_VOUT_SEL_AON_LEN) - 1) << AON_DCDC18_VOUT_SEL_AON_POS)) +#define AON_DCDC18_VPFM_AON AON_DCDC18_VPFM_AON +#define AON_DCDC18_VPFM_AON_POS (8U) +#define AON_DCDC18_VPFM_AON_LEN (4U) +#define AON_DCDC18_VPFM_AON_MSK (((1U << AON_DCDC18_VPFM_AON_LEN) - 1) << AON_DCDC18_VPFM_AON_POS) +#define AON_DCDC18_VPFM_AON_UMSK (~(((1U << AON_DCDC18_VPFM_AON_LEN) - 1) << AON_DCDC18_VPFM_AON_POS)) +#define AON_DCDC18_OSC_2M_MODE_AON AON_DCDC18_OSC_2M_MODE_AON +#define AON_DCDC18_OSC_2M_MODE_AON_POS (12U) +#define AON_DCDC18_OSC_2M_MODE_AON_LEN (1U) +#define AON_DCDC18_OSC_2M_MODE_AON_MSK (((1U << AON_DCDC18_OSC_2M_MODE_AON_LEN) - 1) << AON_DCDC18_OSC_2M_MODE_AON_POS) +#define AON_DCDC18_OSC_2M_MODE_AON_UMSK (~(((1U << AON_DCDC18_OSC_2M_MODE_AON_LEN) - 1) << AON_DCDC18_OSC_2M_MODE_AON_POS)) +#define AON_DCDC18_OSC_FREQ_TRIM_AON AON_DCDC18_OSC_FREQ_TRIM_AON +#define AON_DCDC18_OSC_FREQ_TRIM_AON_POS (16U) +#define AON_DCDC18_OSC_FREQ_TRIM_AON_LEN (4U) +#define AON_DCDC18_OSC_FREQ_TRIM_AON_MSK (((1U << AON_DCDC18_OSC_FREQ_TRIM_AON_LEN) - 1) << AON_DCDC18_OSC_FREQ_TRIM_AON_POS) +#define AON_DCDC18_OSC_FREQ_TRIM_AON_UMSK (~(((1U << AON_DCDC18_OSC_FREQ_TRIM_AON_LEN) - 1) << AON_DCDC18_OSC_FREQ_TRIM_AON_POS)) +#define AON_DCDC18_SLOPE_CURR_SEL_AON AON_DCDC18_SLOPE_CURR_SEL_AON +#define AON_DCDC18_SLOPE_CURR_SEL_AON_POS (20U) +#define AON_DCDC18_SLOPE_CURR_SEL_AON_LEN (5U) +#define AON_DCDC18_SLOPE_CURR_SEL_AON_MSK (((1U << AON_DCDC18_SLOPE_CURR_SEL_AON_LEN) - 1) << AON_DCDC18_SLOPE_CURR_SEL_AON_POS) +#define AON_DCDC18_SLOPE_CURR_SEL_AON_UMSK (~(((1U << AON_DCDC18_SLOPE_CURR_SEL_AON_LEN) - 1) << AON_DCDC18_SLOPE_CURR_SEL_AON_POS)) +#define AON_DCDC18_STOP_OSC_AON AON_DCDC18_STOP_OSC_AON +#define AON_DCDC18_STOP_OSC_AON_POS (25U) +#define AON_DCDC18_STOP_OSC_AON_LEN (1U) +#define AON_DCDC18_STOP_OSC_AON_MSK (((1U << AON_DCDC18_STOP_OSC_AON_LEN) - 1) << AON_DCDC18_STOP_OSC_AON_POS) +#define AON_DCDC18_STOP_OSC_AON_UMSK (~(((1U << AON_DCDC18_STOP_OSC_AON_LEN) - 1) << AON_DCDC18_STOP_OSC_AON_POS)) +#define AON_DCDC18_SLOW_OSC_AON AON_DCDC18_SLOW_OSC_AON +#define AON_DCDC18_SLOW_OSC_AON_POS (26U) +#define AON_DCDC18_SLOW_OSC_AON_LEN (1U) +#define AON_DCDC18_SLOW_OSC_AON_MSK (((1U << AON_DCDC18_SLOW_OSC_AON_LEN) - 1) << AON_DCDC18_SLOW_OSC_AON_POS) +#define AON_DCDC18_SLOW_OSC_AON_UMSK (~(((1U << AON_DCDC18_SLOW_OSC_AON_LEN) - 1) << AON_DCDC18_SLOW_OSC_AON_POS)) +#define AON_DCDC18_OSC_INHIBIT_T2_AON AON_DCDC18_OSC_INHIBIT_T2_AON +#define AON_DCDC18_OSC_INHIBIT_T2_AON_POS (27U) +#define AON_DCDC18_OSC_INHIBIT_T2_AON_LEN (1U) +#define AON_DCDC18_OSC_INHIBIT_T2_AON_MSK (((1U << AON_DCDC18_OSC_INHIBIT_T2_AON_LEN) - 1) << AON_DCDC18_OSC_INHIBIT_T2_AON_POS) +#define AON_DCDC18_OSC_INHIBIT_T2_AON_UMSK (~(((1U << AON_DCDC18_OSC_INHIBIT_T2_AON_LEN) - 1) << AON_DCDC18_OSC_INHIBIT_T2_AON_POS)) +#define AON_DCDC18_SSTART_TIME_AON AON_DCDC18_SSTART_TIME_AON +#define AON_DCDC18_SSTART_TIME_AON_POS (28U) +#define AON_DCDC18_SSTART_TIME_AON_LEN (2U) +#define AON_DCDC18_SSTART_TIME_AON_MSK (((1U << AON_DCDC18_SSTART_TIME_AON_LEN) - 1) << AON_DCDC18_SSTART_TIME_AON_POS) +#define AON_DCDC18_SSTART_TIME_AON_UMSK (~(((1U << AON_DCDC18_SSTART_TIME_AON_LEN) - 1) << AON_DCDC18_SSTART_TIME_AON_POS)) +#define AON_DCDC18_RDY_AON AON_DCDC18_RDY_AON +#define AON_DCDC18_RDY_AON_POS (31U) +#define AON_DCDC18_RDY_AON_LEN (1U) +#define AON_DCDC18_RDY_AON_MSK (((1U << AON_DCDC18_RDY_AON_LEN) - 1) << AON_DCDC18_RDY_AON_POS) +#define AON_DCDC18_RDY_AON_UMSK (~(((1U << AON_DCDC18_RDY_AON_LEN) - 1) << AON_DCDC18_RDY_AON_POS)) + +/* 0x818 : dcdc18_top_1 */ +#define AON_DCDC18_TOP_1_OFFSET (0x818) +#define AON_DCDC18_FORCE_CS_ZVS_AON AON_DCDC18_FORCE_CS_ZVS_AON +#define AON_DCDC18_FORCE_CS_ZVS_AON_POS (0U) +#define AON_DCDC18_FORCE_CS_ZVS_AON_LEN (1U) +#define AON_DCDC18_FORCE_CS_ZVS_AON_MSK (((1U << AON_DCDC18_FORCE_CS_ZVS_AON_LEN) - 1) << AON_DCDC18_FORCE_CS_ZVS_AON_POS) +#define AON_DCDC18_FORCE_CS_ZVS_AON_UMSK (~(((1U << AON_DCDC18_FORCE_CS_ZVS_AON_LEN) - 1) << AON_DCDC18_FORCE_CS_ZVS_AON_POS)) +#define AON_DCDC18_CS_DELAY_AON AON_DCDC18_CS_DELAY_AON +#define AON_DCDC18_CS_DELAY_AON_POS (1U) +#define AON_DCDC18_CS_DELAY_AON_LEN (3U) +#define AON_DCDC18_CS_DELAY_AON_MSK (((1U << AON_DCDC18_CS_DELAY_AON_LEN) - 1) << AON_DCDC18_CS_DELAY_AON_POS) +#define AON_DCDC18_CS_DELAY_AON_UMSK (~(((1U << AON_DCDC18_CS_DELAY_AON_LEN) - 1) << AON_DCDC18_CS_DELAY_AON_POS)) +#define AON_DCDC18_ZVS_TD_OPT_AON AON_DCDC18_ZVS_TD_OPT_AON +#define AON_DCDC18_ZVS_TD_OPT_AON_POS (4U) +#define AON_DCDC18_ZVS_TD_OPT_AON_LEN (3U) +#define AON_DCDC18_ZVS_TD_OPT_AON_MSK (((1U << AON_DCDC18_ZVS_TD_OPT_AON_LEN) - 1) << AON_DCDC18_ZVS_TD_OPT_AON_POS) +#define AON_DCDC18_ZVS_TD_OPT_AON_UMSK (~(((1U << AON_DCDC18_ZVS_TD_OPT_AON_LEN) - 1) << AON_DCDC18_ZVS_TD_OPT_AON_POS)) +#define AON_DCDC18_NONOVERLAP_TD_AON AON_DCDC18_NONOVERLAP_TD_AON +#define AON_DCDC18_NONOVERLAP_TD_AON_POS (8U) +#define AON_DCDC18_NONOVERLAP_TD_AON_LEN (5U) +#define AON_DCDC18_NONOVERLAP_TD_AON_MSK (((1U << AON_DCDC18_NONOVERLAP_TD_AON_LEN) - 1) << AON_DCDC18_NONOVERLAP_TD_AON_POS) +#define AON_DCDC18_NONOVERLAP_TD_AON_UMSK (~(((1U << AON_DCDC18_NONOVERLAP_TD_AON_LEN) - 1) << AON_DCDC18_NONOVERLAP_TD_AON_POS)) +#define AON_DCDC18_RC_SEL_AON AON_DCDC18_RC_SEL_AON +#define AON_DCDC18_RC_SEL_AON_POS (16U) +#define AON_DCDC18_RC_SEL_AON_LEN (4U) +#define AON_DCDC18_RC_SEL_AON_MSK (((1U << AON_DCDC18_RC_SEL_AON_LEN) - 1) << AON_DCDC18_RC_SEL_AON_POS) +#define AON_DCDC18_RC_SEL_AON_UMSK (~(((1U << AON_DCDC18_RC_SEL_AON_LEN) - 1) << AON_DCDC18_RC_SEL_AON_POS)) +#define AON_DCDC18_CHF_SEL_AON AON_DCDC18_CHF_SEL_AON +#define AON_DCDC18_CHF_SEL_AON_POS (20U) +#define AON_DCDC18_CHF_SEL_AON_LEN (4U) +#define AON_DCDC18_CHF_SEL_AON_MSK (((1U << AON_DCDC18_CHF_SEL_AON_LEN) - 1) << AON_DCDC18_CHF_SEL_AON_POS) +#define AON_DCDC18_CHF_SEL_AON_UMSK (~(((1U << AON_DCDC18_CHF_SEL_AON_LEN) - 1) << AON_DCDC18_CHF_SEL_AON_POS)) +#define AON_DCDC18_CFB_SEL_AON AON_DCDC18_CFB_SEL_AON +#define AON_DCDC18_CFB_SEL_AON_POS (24U) +#define AON_DCDC18_CFB_SEL_AON_LEN (4U) +#define AON_DCDC18_CFB_SEL_AON_MSK (((1U << AON_DCDC18_CFB_SEL_AON_LEN) - 1) << AON_DCDC18_CFB_SEL_AON_POS) +#define AON_DCDC18_CFB_SEL_AON_UMSK (~(((1U << AON_DCDC18_CFB_SEL_AON_LEN) - 1) << AON_DCDC18_CFB_SEL_AON_POS)) +#define AON_DCDC18_EN_ANTIRING_AON AON_DCDC18_EN_ANTIRING_AON +#define AON_DCDC18_EN_ANTIRING_AON_POS (28U) +#define AON_DCDC18_EN_ANTIRING_AON_LEN (1U) +#define AON_DCDC18_EN_ANTIRING_AON_MSK (((1U << AON_DCDC18_EN_ANTIRING_AON_LEN) - 1) << AON_DCDC18_EN_ANTIRING_AON_POS) +#define AON_DCDC18_EN_ANTIRING_AON_UMSK (~(((1U << AON_DCDC18_EN_ANTIRING_AON_LEN) - 1) << AON_DCDC18_EN_ANTIRING_AON_POS)) +#define AON_DCDC18_PULLDOWN_AON AON_DCDC18_PULLDOWN_AON +#define AON_DCDC18_PULLDOWN_AON_POS (29U) +#define AON_DCDC18_PULLDOWN_AON_LEN (1U) +#define AON_DCDC18_PULLDOWN_AON_MSK (((1U << AON_DCDC18_PULLDOWN_AON_LEN) - 1) << AON_DCDC18_PULLDOWN_AON_POS) +#define AON_DCDC18_PULLDOWN_AON_UMSK (~(((1U << AON_DCDC18_PULLDOWN_AON_LEN) - 1) << AON_DCDC18_PULLDOWN_AON_POS)) + +/* 0x81C : ldo11soc_and_dctest */ +#define AON_LDO11SOC_AND_DCTEST_OFFSET (0x81C) +#define AON_PU_LDO11SOC_AON AON_PU_LDO11SOC_AON +#define AON_PU_LDO11SOC_AON_POS (0U) +#define AON_PU_LDO11SOC_AON_LEN (1U) +#define AON_PU_LDO11SOC_AON_MSK (((1U << AON_PU_LDO11SOC_AON_LEN) - 1) << AON_PU_LDO11SOC_AON_POS) +#define AON_PU_LDO11SOC_AON_UMSK (~(((1U << AON_PU_LDO11SOC_AON_LEN) - 1) << AON_PU_LDO11SOC_AON_POS)) +#define AON_LDO11SOC_SSTART_SEL_AON AON_LDO11SOC_SSTART_SEL_AON +#define AON_LDO11SOC_SSTART_SEL_AON_POS (4U) +#define AON_LDO11SOC_SSTART_SEL_AON_LEN (1U) +#define AON_LDO11SOC_SSTART_SEL_AON_MSK (((1U << AON_LDO11SOC_SSTART_SEL_AON_LEN) - 1) << AON_LDO11SOC_SSTART_SEL_AON_POS) +#define AON_LDO11SOC_SSTART_SEL_AON_UMSK (~(((1U << AON_LDO11SOC_SSTART_SEL_AON_LEN) - 1) << AON_LDO11SOC_SSTART_SEL_AON_POS)) +#define AON_LDO11SOC_SSTART_DELAY_AON AON_LDO11SOC_SSTART_DELAY_AON +#define AON_LDO11SOC_SSTART_DELAY_AON_POS (8U) +#define AON_LDO11SOC_SSTART_DELAY_AON_LEN (2U) +#define AON_LDO11SOC_SSTART_DELAY_AON_MSK (((1U << AON_LDO11SOC_SSTART_DELAY_AON_LEN) - 1) << AON_LDO11SOC_SSTART_DELAY_AON_POS) +#define AON_LDO11SOC_SSTART_DELAY_AON_UMSK (~(((1U << AON_LDO11SOC_SSTART_DELAY_AON_LEN) - 1) << AON_LDO11SOC_SSTART_DELAY_AON_POS)) +#define AON_LDO11SOC_PULLDOWN_AON AON_LDO11SOC_PULLDOWN_AON +#define AON_LDO11SOC_PULLDOWN_AON_POS (10U) +#define AON_LDO11SOC_PULLDOWN_AON_LEN (1U) +#define AON_LDO11SOC_PULLDOWN_AON_MSK (((1U << AON_LDO11SOC_PULLDOWN_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_AON_POS) +#define AON_LDO11SOC_PULLDOWN_AON_UMSK (~(((1U << AON_LDO11SOC_PULLDOWN_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_AON_POS)) +#define AON_LDO11SOC_PULLDOWN_SEL_AON AON_LDO11SOC_PULLDOWN_SEL_AON +#define AON_LDO11SOC_PULLDOWN_SEL_AON_POS (11U) +#define AON_LDO11SOC_PULLDOWN_SEL_AON_LEN (1U) +#define AON_LDO11SOC_PULLDOWN_SEL_AON_MSK (((1U << AON_LDO11SOC_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_SEL_AON_POS) +#define AON_LDO11SOC_PULLDOWN_SEL_AON_UMSK (~(((1U << AON_LDO11SOC_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_SEL_AON_POS)) +#define AON_LDO11SOC_VTH_SEL_AON AON_LDO11SOC_VTH_SEL_AON +#define AON_LDO11SOC_VTH_SEL_AON_POS (12U) +#define AON_LDO11SOC_VTH_SEL_AON_LEN (2U) +#define AON_LDO11SOC_VTH_SEL_AON_MSK (((1U << AON_LDO11SOC_VTH_SEL_AON_LEN) - 1) << AON_LDO11SOC_VTH_SEL_AON_POS) +#define AON_LDO11SOC_VTH_SEL_AON_UMSK (~(((1U << AON_LDO11SOC_VTH_SEL_AON_LEN) - 1) << AON_LDO11SOC_VTH_SEL_AON_POS)) +#define AON_LDO11SOC_CC_AON AON_LDO11SOC_CC_AON +#define AON_LDO11SOC_CC_AON_POS (24U) +#define AON_LDO11SOC_CC_AON_LEN (2U) +#define AON_LDO11SOC_CC_AON_MSK (((1U << AON_LDO11SOC_CC_AON_LEN) - 1) << AON_LDO11SOC_CC_AON_POS) +#define AON_LDO11SOC_CC_AON_UMSK (~(((1U << AON_LDO11SOC_CC_AON_LEN) - 1) << AON_LDO11SOC_CC_AON_POS)) +#define AON_LDO11SOC_RDY_AON AON_LDO11SOC_RDY_AON +#define AON_LDO11SOC_RDY_AON_POS (28U) +#define AON_LDO11SOC_RDY_AON_LEN (1U) +#define AON_LDO11SOC_RDY_AON_MSK (((1U << AON_LDO11SOC_RDY_AON_LEN) - 1) << AON_LDO11SOC_RDY_AON_POS) +#define AON_LDO11SOC_RDY_AON_UMSK (~(((1U << AON_LDO11SOC_RDY_AON_LEN) - 1) << AON_LDO11SOC_RDY_AON_POS)) +#define AON_LDO11SOC_POWER_GOOD_AON AON_LDO11SOC_POWER_GOOD_AON +#define AON_LDO11SOC_POWER_GOOD_AON_POS (29U) +#define AON_LDO11SOC_POWER_GOOD_AON_LEN (1U) +#define AON_LDO11SOC_POWER_GOOD_AON_MSK (((1U << AON_LDO11SOC_POWER_GOOD_AON_LEN) - 1) << AON_LDO11SOC_POWER_GOOD_AON_POS) +#define AON_LDO11SOC_POWER_GOOD_AON_UMSK (~(((1U << AON_LDO11SOC_POWER_GOOD_AON_LEN) - 1) << AON_LDO11SOC_POWER_GOOD_AON_POS)) +#define AON_PU_VDDCORE_MISC_AON AON_PU_VDDCORE_MISC_AON +#define AON_PU_VDDCORE_MISC_AON_POS (30U) +#define AON_PU_VDDCORE_MISC_AON_LEN (1U) +#define AON_PU_VDDCORE_MISC_AON_MSK (((1U << AON_PU_VDDCORE_MISC_AON_LEN) - 1) << AON_PU_VDDCORE_MISC_AON_POS) +#define AON_PU_VDDCORE_MISC_AON_UMSK (~(((1U << AON_PU_VDDCORE_MISC_AON_LEN) - 1) << AON_PU_VDDCORE_MISC_AON_POS)) +#define AON_PMIP_DC_TP_OUT_EN_AON AON_PMIP_DC_TP_OUT_EN_AON +#define AON_PMIP_DC_TP_OUT_EN_AON_POS (31U) +#define AON_PMIP_DC_TP_OUT_EN_AON_LEN (1U) +#define AON_PMIP_DC_TP_OUT_EN_AON_MSK (((1U << AON_PMIP_DC_TP_OUT_EN_AON_LEN) - 1) << AON_PMIP_DC_TP_OUT_EN_AON_POS) +#define AON_PMIP_DC_TP_OUT_EN_AON_UMSK (~(((1U << AON_PMIP_DC_TP_OUT_EN_AON_LEN) - 1) << AON_PMIP_DC_TP_OUT_EN_AON_POS)) + +/* 0x820 : psw_irrcv */ +#define AON_PSW_IRRCV_OFFSET (0x820) +#define AON_PU_IR_PSW_AON AON_PU_IR_PSW_AON +#define AON_PU_IR_PSW_AON_POS (0U) +#define AON_PU_IR_PSW_AON_LEN (1U) +#define AON_PU_IR_PSW_AON_MSK (((1U << AON_PU_IR_PSW_AON_LEN) - 1) << AON_PU_IR_PSW_AON_POS) +#define AON_PU_IR_PSW_AON_UMSK (~(((1U << AON_PU_IR_PSW_AON_LEN) - 1) << AON_PU_IR_PSW_AON_POS)) + +/* 0x880 : rf_top_aon */ +#define AON_RF_TOP_AON_OFFSET (0x880) +#define AON_PU_MBG_AON AON_PU_MBG_AON +#define AON_PU_MBG_AON_POS (0U) +#define AON_PU_MBG_AON_LEN (1U) +#define AON_PU_MBG_AON_MSK (((1U << AON_PU_MBG_AON_LEN) - 1) << AON_PU_MBG_AON_POS) +#define AON_PU_MBG_AON_UMSK (~(((1U << AON_PU_MBG_AON_LEN) - 1) << AON_PU_MBG_AON_POS)) +#define AON_PU_LDO15RF_AON AON_PU_LDO15RF_AON +#define AON_PU_LDO15RF_AON_POS (1U) +#define AON_PU_LDO15RF_AON_LEN (1U) +#define AON_PU_LDO15RF_AON_MSK (((1U << AON_PU_LDO15RF_AON_LEN) - 1) << AON_PU_LDO15RF_AON_POS) +#define AON_PU_LDO15RF_AON_UMSK (~(((1U << AON_PU_LDO15RF_AON_LEN) - 1) << AON_PU_LDO15RF_AON_POS)) +#define AON_PU_SFREG_AON AON_PU_SFREG_AON +#define AON_PU_SFREG_AON_POS (2U) +#define AON_PU_SFREG_AON_LEN (1U) +#define AON_PU_SFREG_AON_MSK (((1U << AON_PU_SFREG_AON_LEN) - 1) << AON_PU_SFREG_AON_POS) +#define AON_PU_SFREG_AON_UMSK (~(((1U << AON_PU_SFREG_AON_LEN) - 1) << AON_PU_SFREG_AON_POS)) +#define AON_PU_XTAL_BUF_AON AON_PU_XTAL_BUF_AON +#define AON_PU_XTAL_BUF_AON_POS (4U) +#define AON_PU_XTAL_BUF_AON_LEN (1U) +#define AON_PU_XTAL_BUF_AON_MSK (((1U << AON_PU_XTAL_BUF_AON_LEN) - 1) << AON_PU_XTAL_BUF_AON_POS) +#define AON_PU_XTAL_BUF_AON_UMSK (~(((1U << AON_PU_XTAL_BUF_AON_LEN) - 1) << AON_PU_XTAL_BUF_AON_POS)) +#define AON_PU_XTAL_AON AON_PU_XTAL_AON +#define AON_PU_XTAL_AON_POS (5U) +#define AON_PU_XTAL_AON_LEN (1U) +#define AON_PU_XTAL_AON_MSK (((1U << AON_PU_XTAL_AON_LEN) - 1) << AON_PU_XTAL_AON_POS) +#define AON_PU_XTAL_AON_UMSK (~(((1U << AON_PU_XTAL_AON_LEN) - 1) << AON_PU_XTAL_AON_POS)) +#define AON_LDO15RF_SSTART_SEL_AON AON_LDO15RF_SSTART_SEL_AON +#define AON_LDO15RF_SSTART_SEL_AON_POS (8U) +#define AON_LDO15RF_SSTART_SEL_AON_LEN (1U) +#define AON_LDO15RF_SSTART_SEL_AON_MSK (((1U << AON_LDO15RF_SSTART_SEL_AON_LEN) - 1) << AON_LDO15RF_SSTART_SEL_AON_POS) +#define AON_LDO15RF_SSTART_SEL_AON_UMSK (~(((1U << AON_LDO15RF_SSTART_SEL_AON_LEN) - 1) << AON_LDO15RF_SSTART_SEL_AON_POS)) +#define AON_LDO15RF_SSTART_DELAY_AON AON_LDO15RF_SSTART_DELAY_AON +#define AON_LDO15RF_SSTART_DELAY_AON_POS (9U) +#define AON_LDO15RF_SSTART_DELAY_AON_LEN (2U) +#define AON_LDO15RF_SSTART_DELAY_AON_MSK (((1U << AON_LDO15RF_SSTART_DELAY_AON_LEN) - 1) << AON_LDO15RF_SSTART_DELAY_AON_POS) +#define AON_LDO15RF_SSTART_DELAY_AON_UMSK (~(((1U << AON_LDO15RF_SSTART_DELAY_AON_LEN) - 1) << AON_LDO15RF_SSTART_DELAY_AON_POS)) +#define AON_LDO15RF_PULLDOWN_AON AON_LDO15RF_PULLDOWN_AON +#define AON_LDO15RF_PULLDOWN_AON_POS (12U) +#define AON_LDO15RF_PULLDOWN_AON_LEN (1U) +#define AON_LDO15RF_PULLDOWN_AON_MSK (((1U << AON_LDO15RF_PULLDOWN_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_AON_POS) +#define AON_LDO15RF_PULLDOWN_AON_UMSK (~(((1U << AON_LDO15RF_PULLDOWN_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_AON_POS)) +#define AON_LDO15RF_PULLDOWN_SEL_AON AON_LDO15RF_PULLDOWN_SEL_AON +#define AON_LDO15RF_PULLDOWN_SEL_AON_POS (13U) +#define AON_LDO15RF_PULLDOWN_SEL_AON_LEN (1U) +#define AON_LDO15RF_PULLDOWN_SEL_AON_MSK (((1U << AON_LDO15RF_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_SEL_AON_POS) +#define AON_LDO15RF_PULLDOWN_SEL_AON_UMSK (~(((1U << AON_LDO15RF_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_SEL_AON_POS)) +#define AON_LDO15RF_VOUT_SEL_AON AON_LDO15RF_VOUT_SEL_AON +#define AON_LDO15RF_VOUT_SEL_AON_POS (16U) +#define AON_LDO15RF_VOUT_SEL_AON_LEN (3U) +#define AON_LDO15RF_VOUT_SEL_AON_MSK (((1U << AON_LDO15RF_VOUT_SEL_AON_LEN) - 1) << AON_LDO15RF_VOUT_SEL_AON_POS) +#define AON_LDO15RF_VOUT_SEL_AON_UMSK (~(((1U << AON_LDO15RF_VOUT_SEL_AON_LEN) - 1) << AON_LDO15RF_VOUT_SEL_AON_POS)) +#define AON_LDO15RF_CC_AON AON_LDO15RF_CC_AON +#define AON_LDO15RF_CC_AON_POS (24U) +#define AON_LDO15RF_CC_AON_LEN (2U) +#define AON_LDO15RF_CC_AON_MSK (((1U << AON_LDO15RF_CC_AON_LEN) - 1) << AON_LDO15RF_CC_AON_POS) +#define AON_LDO15RF_CC_AON_UMSK (~(((1U << AON_LDO15RF_CC_AON_LEN) - 1) << AON_LDO15RF_CC_AON_POS)) +#define AON_LDO15RF_BYPASS_AON AON_LDO15RF_BYPASS_AON +#define AON_LDO15RF_BYPASS_AON_POS (28U) +#define AON_LDO15RF_BYPASS_AON_LEN (1U) +#define AON_LDO15RF_BYPASS_AON_MSK (((1U << AON_LDO15RF_BYPASS_AON_LEN) - 1) << AON_LDO15RF_BYPASS_AON_POS) +#define AON_LDO15RF_BYPASS_AON_UMSK (~(((1U << AON_LDO15RF_BYPASS_AON_LEN) - 1) << AON_LDO15RF_BYPASS_AON_POS)) + +/* 0x884 : xtal_cfg */ +#define AON_XTAL_CFG_OFFSET (0x884) +#define AON_XTAL_BK_AON AON_XTAL_BK_AON +#define AON_XTAL_BK_AON_POS (0U) +#define AON_XTAL_BK_AON_LEN (2U) +#define AON_XTAL_BK_AON_MSK (((1U << AON_XTAL_BK_AON_LEN) - 1) << AON_XTAL_BK_AON_POS) +#define AON_XTAL_BK_AON_UMSK (~(((1U << AON_XTAL_BK_AON_LEN) - 1) << AON_XTAL_BK_AON_POS)) +#define AON_XTAL_CAPCODE_EXTRA_AON AON_XTAL_CAPCODE_EXTRA_AON +#define AON_XTAL_CAPCODE_EXTRA_AON_POS (2U) +#define AON_XTAL_CAPCODE_EXTRA_AON_LEN (1U) +#define AON_XTAL_CAPCODE_EXTRA_AON_MSK (((1U << AON_XTAL_CAPCODE_EXTRA_AON_LEN) - 1) << AON_XTAL_CAPCODE_EXTRA_AON_POS) +#define AON_XTAL_CAPCODE_EXTRA_AON_UMSK (~(((1U << AON_XTAL_CAPCODE_EXTRA_AON_LEN) - 1) << AON_XTAL_CAPCODE_EXTRA_AON_POS)) +#define AON_XTAL_EXT_SEL_AON AON_XTAL_EXT_SEL_AON +#define AON_XTAL_EXT_SEL_AON_POS (3U) +#define AON_XTAL_EXT_SEL_AON_LEN (1U) +#define AON_XTAL_EXT_SEL_AON_MSK (((1U << AON_XTAL_EXT_SEL_AON_LEN) - 1) << AON_XTAL_EXT_SEL_AON_POS) +#define AON_XTAL_EXT_SEL_AON_UMSK (~(((1U << AON_XTAL_EXT_SEL_AON_LEN) - 1) << AON_XTAL_EXT_SEL_AON_POS)) +#define AON_XTAL_BUF_EN_AON AON_XTAL_BUF_EN_AON +#define AON_XTAL_BUF_EN_AON_POS (4U) +#define AON_XTAL_BUF_EN_AON_LEN (4U) +#define AON_XTAL_BUF_EN_AON_MSK (((1U << AON_XTAL_BUF_EN_AON_LEN) - 1) << AON_XTAL_BUF_EN_AON_POS) +#define AON_XTAL_BUF_EN_AON_UMSK (~(((1U << AON_XTAL_BUF_EN_AON_LEN) - 1) << AON_XTAL_BUF_EN_AON_POS)) +#define AON_XTAL_BUF_HP_AON AON_XTAL_BUF_HP_AON +#define AON_XTAL_BUF_HP_AON_POS (8U) +#define AON_XTAL_BUF_HP_AON_LEN (4U) +#define AON_XTAL_BUF_HP_AON_MSK (((1U << AON_XTAL_BUF_HP_AON_LEN) - 1) << AON_XTAL_BUF_HP_AON_POS) +#define AON_XTAL_BUF_HP_AON_UMSK (~(((1U << AON_XTAL_BUF_HP_AON_LEN) - 1) << AON_XTAL_BUF_HP_AON_POS)) +#define AON_XTAL_FAST_STARTUP_AON AON_XTAL_FAST_STARTUP_AON +#define AON_XTAL_FAST_STARTUP_AON_POS (12U) +#define AON_XTAL_FAST_STARTUP_AON_LEN (1U) +#define AON_XTAL_FAST_STARTUP_AON_MSK (((1U << AON_XTAL_FAST_STARTUP_AON_LEN) - 1) << AON_XTAL_FAST_STARTUP_AON_POS) +#define AON_XTAL_FAST_STARTUP_AON_UMSK (~(((1U << AON_XTAL_FAST_STARTUP_AON_LEN) - 1) << AON_XTAL_FAST_STARTUP_AON_POS)) +#define AON_XTAL_SLEEP_AON AON_XTAL_SLEEP_AON +#define AON_XTAL_SLEEP_AON_POS (13U) +#define AON_XTAL_SLEEP_AON_LEN (1U) +#define AON_XTAL_SLEEP_AON_MSK (((1U << AON_XTAL_SLEEP_AON_LEN) - 1) << AON_XTAL_SLEEP_AON_POS) +#define AON_XTAL_SLEEP_AON_UMSK (~(((1U << AON_XTAL_SLEEP_AON_LEN) - 1) << AON_XTAL_SLEEP_AON_POS)) +#define AON_XTAL_AMP_CTRL_AON AON_XTAL_AMP_CTRL_AON +#define AON_XTAL_AMP_CTRL_AON_POS (14U) +#define AON_XTAL_AMP_CTRL_AON_LEN (2U) +#define AON_XTAL_AMP_CTRL_AON_MSK (((1U << AON_XTAL_AMP_CTRL_AON_LEN) - 1) << AON_XTAL_AMP_CTRL_AON_POS) +#define AON_XTAL_AMP_CTRL_AON_UMSK (~(((1U << AON_XTAL_AMP_CTRL_AON_LEN) - 1) << AON_XTAL_AMP_CTRL_AON_POS)) +#define AON_XTAL_CAPCODE_OUT_AON AON_XTAL_CAPCODE_OUT_AON +#define AON_XTAL_CAPCODE_OUT_AON_POS (16U) +#define AON_XTAL_CAPCODE_OUT_AON_LEN (6U) +#define AON_XTAL_CAPCODE_OUT_AON_MSK (((1U << AON_XTAL_CAPCODE_OUT_AON_LEN) - 1) << AON_XTAL_CAPCODE_OUT_AON_POS) +#define AON_XTAL_CAPCODE_OUT_AON_UMSK (~(((1U << AON_XTAL_CAPCODE_OUT_AON_LEN) - 1) << AON_XTAL_CAPCODE_OUT_AON_POS)) +#define AON_XTAL_CAPCODE_IN_AON AON_XTAL_CAPCODE_IN_AON +#define AON_XTAL_CAPCODE_IN_AON_POS (22U) +#define AON_XTAL_CAPCODE_IN_AON_LEN (6U) +#define AON_XTAL_CAPCODE_IN_AON_MSK (((1U << AON_XTAL_CAPCODE_IN_AON_LEN) - 1) << AON_XTAL_CAPCODE_IN_AON_POS) +#define AON_XTAL_CAPCODE_IN_AON_UMSK (~(((1U << AON_XTAL_CAPCODE_IN_AON_LEN) - 1) << AON_XTAL_CAPCODE_IN_AON_POS)) +#define AON_XTAL_GM_BOOST_AON AON_XTAL_GM_BOOST_AON +#define AON_XTAL_GM_BOOST_AON_POS (28U) +#define AON_XTAL_GM_BOOST_AON_LEN (2U) +#define AON_XTAL_GM_BOOST_AON_MSK (((1U << AON_XTAL_GM_BOOST_AON_LEN) - 1) << AON_XTAL_GM_BOOST_AON_POS) +#define AON_XTAL_GM_BOOST_AON_UMSK (~(((1U << AON_XTAL_GM_BOOST_AON_LEN) - 1) << AON_XTAL_GM_BOOST_AON_POS)) +#define AON_XTAL_RDY_SEL_AON AON_XTAL_RDY_SEL_AON +#define AON_XTAL_RDY_SEL_AON_POS (30U) +#define AON_XTAL_RDY_SEL_AON_LEN (2U) +#define AON_XTAL_RDY_SEL_AON_MSK (((1U << AON_XTAL_RDY_SEL_AON_LEN) - 1) << AON_XTAL_RDY_SEL_AON_POS) +#define AON_XTAL_RDY_SEL_AON_UMSK (~(((1U << AON_XTAL_RDY_SEL_AON_LEN) - 1) << AON_XTAL_RDY_SEL_AON_POS)) + +/* 0x888 : tsen */ +#define AON_TSEN_OFFSET (0x888) +#define AON_TSEN_REFCODE_CORNER AON_TSEN_REFCODE_CORNER +#define AON_TSEN_REFCODE_CORNER_POS (0U) +#define AON_TSEN_REFCODE_CORNER_LEN (12U) +#define AON_TSEN_REFCODE_CORNER_MSK (((1U << AON_TSEN_REFCODE_CORNER_LEN) - 1) << AON_TSEN_REFCODE_CORNER_POS) +#define AON_TSEN_REFCODE_CORNER_UMSK (~(((1U << AON_TSEN_REFCODE_CORNER_LEN) - 1) << AON_TSEN_REFCODE_CORNER_POS)) +#define AON_TSEN_REFCODE_RFCAL AON_TSEN_REFCODE_RFCAL +#define AON_TSEN_REFCODE_RFCAL_POS (16U) +#define AON_TSEN_REFCODE_RFCAL_LEN (12U) +#define AON_TSEN_REFCODE_RFCAL_MSK (((1U << AON_TSEN_REFCODE_RFCAL_LEN) - 1) << AON_TSEN_REFCODE_RFCAL_POS) +#define AON_TSEN_REFCODE_RFCAL_UMSK (~(((1U << AON_TSEN_REFCODE_RFCAL_LEN) - 1) << AON_TSEN_REFCODE_RFCAL_POS)) +#define AON_XTAL_RDY AON_XTAL_RDY +#define AON_XTAL_RDY_POS (28U) +#define AON_XTAL_RDY_LEN (1U) +#define AON_XTAL_RDY_MSK (((1U << AON_XTAL_RDY_LEN) - 1) << AON_XTAL_RDY_POS) +#define AON_XTAL_RDY_UMSK (~(((1U << AON_XTAL_RDY_LEN) - 1) << AON_XTAL_RDY_POS)) +#define AON_XTAL_INN_CFG_EN_AON AON_XTAL_INN_CFG_EN_AON +#define AON_XTAL_INN_CFG_EN_AON_POS (29U) +#define AON_XTAL_INN_CFG_EN_AON_LEN (1U) +#define AON_XTAL_INN_CFG_EN_AON_MSK (((1U << AON_XTAL_INN_CFG_EN_AON_LEN) - 1) << AON_XTAL_INN_CFG_EN_AON_POS) +#define AON_XTAL_INN_CFG_EN_AON_UMSK (~(((1U << AON_XTAL_INN_CFG_EN_AON_LEN) - 1) << AON_XTAL_INN_CFG_EN_AON_POS)) +#define AON_XTAL_RDY_INT_SEL_AON AON_XTAL_RDY_INT_SEL_AON +#define AON_XTAL_RDY_INT_SEL_AON_POS (30U) +#define AON_XTAL_RDY_INT_SEL_AON_LEN (2U) +#define AON_XTAL_RDY_INT_SEL_AON_MSK (((1U << AON_XTAL_RDY_INT_SEL_AON_LEN) - 1) << AON_XTAL_RDY_INT_SEL_AON_POS) +#define AON_XTAL_RDY_INT_SEL_AON_UMSK (~(((1U << AON_XTAL_RDY_INT_SEL_AON_LEN) - 1) << AON_XTAL_RDY_INT_SEL_AON_POS)) + +/* 0x900 : acomp0_ctrl */ +#define AON_ACOMP0_CTRL_OFFSET (0x900) +#define AON_ACOMP0_EN AON_ACOMP0_EN +#define AON_ACOMP0_EN_POS (0U) +#define AON_ACOMP0_EN_LEN (1U) +#define AON_ACOMP0_EN_MSK (((1U << AON_ACOMP0_EN_LEN) - 1) << AON_ACOMP0_EN_POS) +#define AON_ACOMP0_EN_UMSK (~(((1U << AON_ACOMP0_EN_LEN) - 1) << AON_ACOMP0_EN_POS)) +#define AON_ACOMP0_HYST_SELN AON_ACOMP0_HYST_SELN +#define AON_ACOMP0_HYST_SELN_POS (4U) +#define AON_ACOMP0_HYST_SELN_LEN (3U) +#define AON_ACOMP0_HYST_SELN_MSK (((1U << AON_ACOMP0_HYST_SELN_LEN) - 1) << AON_ACOMP0_HYST_SELN_POS) +#define AON_ACOMP0_HYST_SELN_UMSK (~(((1U << AON_ACOMP0_HYST_SELN_LEN) - 1) << AON_ACOMP0_HYST_SELN_POS)) +#define AON_ACOMP0_HYST_SELP AON_ACOMP0_HYST_SELP +#define AON_ACOMP0_HYST_SELP_POS (7U) +#define AON_ACOMP0_HYST_SELP_LEN (3U) +#define AON_ACOMP0_HYST_SELP_MSK (((1U << AON_ACOMP0_HYST_SELP_LEN) - 1) << AON_ACOMP0_HYST_SELP_POS) +#define AON_ACOMP0_HYST_SELP_UMSK (~(((1U << AON_ACOMP0_HYST_SELP_LEN) - 1) << AON_ACOMP0_HYST_SELP_POS)) +#define AON_ACOMP0_BIAS_PROG AON_ACOMP0_BIAS_PROG +#define AON_ACOMP0_BIAS_PROG_POS (10U) +#define AON_ACOMP0_BIAS_PROG_LEN (2U) +#define AON_ACOMP0_BIAS_PROG_MSK (((1U << AON_ACOMP0_BIAS_PROG_LEN) - 1) << AON_ACOMP0_BIAS_PROG_POS) +#define AON_ACOMP0_BIAS_PROG_UMSK (~(((1U << AON_ACOMP0_BIAS_PROG_LEN) - 1) << AON_ACOMP0_BIAS_PROG_POS)) +#define AON_ACOMP0_LEVEL_SEL AON_ACOMP0_LEVEL_SEL +#define AON_ACOMP0_LEVEL_SEL_POS (12U) +#define AON_ACOMP0_LEVEL_SEL_LEN (6U) +#define AON_ACOMP0_LEVEL_SEL_MSK (((1U << AON_ACOMP0_LEVEL_SEL_LEN) - 1) << AON_ACOMP0_LEVEL_SEL_POS) +#define AON_ACOMP0_LEVEL_SEL_UMSK (~(((1U << AON_ACOMP0_LEVEL_SEL_LEN) - 1) << AON_ACOMP0_LEVEL_SEL_POS)) +#define AON_ACOMP0_NEG_SEL AON_ACOMP0_NEG_SEL +#define AON_ACOMP0_NEG_SEL_POS (18U) +#define AON_ACOMP0_NEG_SEL_LEN (4U) +#define AON_ACOMP0_NEG_SEL_MSK (((1U << AON_ACOMP0_NEG_SEL_LEN) - 1) << AON_ACOMP0_NEG_SEL_POS) +#define AON_ACOMP0_NEG_SEL_UMSK (~(((1U << AON_ACOMP0_NEG_SEL_LEN) - 1) << AON_ACOMP0_NEG_SEL_POS)) +#define AON_ACOMP0_POS_SEL AON_ACOMP0_POS_SEL +#define AON_ACOMP0_POS_SEL_POS (22U) +#define AON_ACOMP0_POS_SEL_LEN (4U) +#define AON_ACOMP0_POS_SEL_MSK (((1U << AON_ACOMP0_POS_SEL_LEN) - 1) << AON_ACOMP0_POS_SEL_POS) +#define AON_ACOMP0_POS_SEL_UMSK (~(((1U << AON_ACOMP0_POS_SEL_LEN) - 1) << AON_ACOMP0_POS_SEL_POS)) +#define AON_ACOMP0_MUXEN AON_ACOMP0_MUXEN +#define AON_ACOMP0_MUXEN_POS (26U) +#define AON_ACOMP0_MUXEN_LEN (1U) +#define AON_ACOMP0_MUXEN_MSK (((1U << AON_ACOMP0_MUXEN_LEN) - 1) << AON_ACOMP0_MUXEN_POS) +#define AON_ACOMP0_MUXEN_UMSK (~(((1U << AON_ACOMP0_MUXEN_LEN) - 1) << AON_ACOMP0_MUXEN_POS)) + +/* 0x904 : acomp1_ctrl */ +#define AON_ACOMP1_CTRL_OFFSET (0x904) +#define AON_ACOMP1_EN AON_ACOMP1_EN +#define AON_ACOMP1_EN_POS (0U) +#define AON_ACOMP1_EN_LEN (1U) +#define AON_ACOMP1_EN_MSK (((1U << AON_ACOMP1_EN_LEN) - 1) << AON_ACOMP1_EN_POS) +#define AON_ACOMP1_EN_UMSK (~(((1U << AON_ACOMP1_EN_LEN) - 1) << AON_ACOMP1_EN_POS)) +#define AON_ACOMP1_HYST_SELN AON_ACOMP1_HYST_SELN +#define AON_ACOMP1_HYST_SELN_POS (4U) +#define AON_ACOMP1_HYST_SELN_LEN (3U) +#define AON_ACOMP1_HYST_SELN_MSK (((1U << AON_ACOMP1_HYST_SELN_LEN) - 1) << AON_ACOMP1_HYST_SELN_POS) +#define AON_ACOMP1_HYST_SELN_UMSK (~(((1U << AON_ACOMP1_HYST_SELN_LEN) - 1) << AON_ACOMP1_HYST_SELN_POS)) +#define AON_ACOMP1_HYST_SELP AON_ACOMP1_HYST_SELP +#define AON_ACOMP1_HYST_SELP_POS (7U) +#define AON_ACOMP1_HYST_SELP_LEN (3U) +#define AON_ACOMP1_HYST_SELP_MSK (((1U << AON_ACOMP1_HYST_SELP_LEN) - 1) << AON_ACOMP1_HYST_SELP_POS) +#define AON_ACOMP1_HYST_SELP_UMSK (~(((1U << AON_ACOMP1_HYST_SELP_LEN) - 1) << AON_ACOMP1_HYST_SELP_POS)) +#define AON_ACOMP1_BIAS_PROG AON_ACOMP1_BIAS_PROG +#define AON_ACOMP1_BIAS_PROG_POS (10U) +#define AON_ACOMP1_BIAS_PROG_LEN (2U) +#define AON_ACOMP1_BIAS_PROG_MSK (((1U << AON_ACOMP1_BIAS_PROG_LEN) - 1) << AON_ACOMP1_BIAS_PROG_POS) +#define AON_ACOMP1_BIAS_PROG_UMSK (~(((1U << AON_ACOMP1_BIAS_PROG_LEN) - 1) << AON_ACOMP1_BIAS_PROG_POS)) +#define AON_ACOMP1_LEVEL_SEL AON_ACOMP1_LEVEL_SEL +#define AON_ACOMP1_LEVEL_SEL_POS (12U) +#define AON_ACOMP1_LEVEL_SEL_LEN (6U) +#define AON_ACOMP1_LEVEL_SEL_MSK (((1U << AON_ACOMP1_LEVEL_SEL_LEN) - 1) << AON_ACOMP1_LEVEL_SEL_POS) +#define AON_ACOMP1_LEVEL_SEL_UMSK (~(((1U << AON_ACOMP1_LEVEL_SEL_LEN) - 1) << AON_ACOMP1_LEVEL_SEL_POS)) +#define AON_ACOMP1_NEG_SEL AON_ACOMP1_NEG_SEL +#define AON_ACOMP1_NEG_SEL_POS (18U) +#define AON_ACOMP1_NEG_SEL_LEN (4U) +#define AON_ACOMP1_NEG_SEL_MSK (((1U << AON_ACOMP1_NEG_SEL_LEN) - 1) << AON_ACOMP1_NEG_SEL_POS) +#define AON_ACOMP1_NEG_SEL_UMSK (~(((1U << AON_ACOMP1_NEG_SEL_LEN) - 1) << AON_ACOMP1_NEG_SEL_POS)) +#define AON_ACOMP1_POS_SEL AON_ACOMP1_POS_SEL +#define AON_ACOMP1_POS_SEL_POS (22U) +#define AON_ACOMP1_POS_SEL_LEN (4U) +#define AON_ACOMP1_POS_SEL_MSK (((1U << AON_ACOMP1_POS_SEL_LEN) - 1) << AON_ACOMP1_POS_SEL_POS) +#define AON_ACOMP1_POS_SEL_UMSK (~(((1U << AON_ACOMP1_POS_SEL_LEN) - 1) << AON_ACOMP1_POS_SEL_POS)) +#define AON_ACOMP1_MUXEN AON_ACOMP1_MUXEN +#define AON_ACOMP1_MUXEN_POS (26U) +#define AON_ACOMP1_MUXEN_LEN (1U) +#define AON_ACOMP1_MUXEN_MSK (((1U << AON_ACOMP1_MUXEN_LEN) - 1) << AON_ACOMP1_MUXEN_POS) +#define AON_ACOMP1_MUXEN_UMSK (~(((1U << AON_ACOMP1_MUXEN_LEN) - 1) << AON_ACOMP1_MUXEN_POS)) + +/* 0x908 : acomp_ctrl */ +#define AON_ACOMP_CTRL_OFFSET (0x908) +#define AON_ACOMP1_RSTN_ANA AON_ACOMP1_RSTN_ANA +#define AON_ACOMP1_RSTN_ANA_POS (0U) +#define AON_ACOMP1_RSTN_ANA_LEN (1U) +#define AON_ACOMP1_RSTN_ANA_MSK (((1U << AON_ACOMP1_RSTN_ANA_LEN) - 1) << AON_ACOMP1_RSTN_ANA_POS) +#define AON_ACOMP1_RSTN_ANA_UMSK (~(((1U << AON_ACOMP1_RSTN_ANA_LEN) - 1) << AON_ACOMP1_RSTN_ANA_POS)) +#define AON_ACOMP0_RSTN_ANA AON_ACOMP0_RSTN_ANA +#define AON_ACOMP0_RSTN_ANA_POS (1U) +#define AON_ACOMP0_RSTN_ANA_LEN (1U) +#define AON_ACOMP0_RSTN_ANA_MSK (((1U << AON_ACOMP0_RSTN_ANA_LEN) - 1) << AON_ACOMP0_RSTN_ANA_POS) +#define AON_ACOMP0_RSTN_ANA_UMSK (~(((1U << AON_ACOMP0_RSTN_ANA_LEN) - 1) << AON_ACOMP0_RSTN_ANA_POS)) +#define AON_ACOMP1_TEST_EN AON_ACOMP1_TEST_EN +#define AON_ACOMP1_TEST_EN_POS (8U) +#define AON_ACOMP1_TEST_EN_LEN (1U) +#define AON_ACOMP1_TEST_EN_MSK (((1U << AON_ACOMP1_TEST_EN_LEN) - 1) << AON_ACOMP1_TEST_EN_POS) +#define AON_ACOMP1_TEST_EN_UMSK (~(((1U << AON_ACOMP1_TEST_EN_LEN) - 1) << AON_ACOMP1_TEST_EN_POS)) +#define AON_ACOMP0_TEST_EN AON_ACOMP0_TEST_EN +#define AON_ACOMP0_TEST_EN_POS (9U) +#define AON_ACOMP0_TEST_EN_LEN (1U) +#define AON_ACOMP0_TEST_EN_MSK (((1U << AON_ACOMP0_TEST_EN_LEN) - 1) << AON_ACOMP0_TEST_EN_POS) +#define AON_ACOMP0_TEST_EN_UMSK (~(((1U << AON_ACOMP0_TEST_EN_LEN) - 1) << AON_ACOMP0_TEST_EN_POS)) +#define AON_ACOMP1_TEST_SEL AON_ACOMP1_TEST_SEL +#define AON_ACOMP1_TEST_SEL_POS (10U) +#define AON_ACOMP1_TEST_SEL_LEN (2U) +#define AON_ACOMP1_TEST_SEL_MSK (((1U << AON_ACOMP1_TEST_SEL_LEN) - 1) << AON_ACOMP1_TEST_SEL_POS) +#define AON_ACOMP1_TEST_SEL_UMSK (~(((1U << AON_ACOMP1_TEST_SEL_LEN) - 1) << AON_ACOMP1_TEST_SEL_POS)) +#define AON_ACOMP0_TEST_SEL AON_ACOMP0_TEST_SEL +#define AON_ACOMP0_TEST_SEL_POS (12U) +#define AON_ACOMP0_TEST_SEL_LEN (2U) +#define AON_ACOMP0_TEST_SEL_MSK (((1U << AON_ACOMP0_TEST_SEL_LEN) - 1) << AON_ACOMP0_TEST_SEL_POS) +#define AON_ACOMP0_TEST_SEL_UMSK (~(((1U << AON_ACOMP0_TEST_SEL_LEN) - 1) << AON_ACOMP0_TEST_SEL_POS)) +#define AON_ACOMP1_OUT_RAW AON_ACOMP1_OUT_RAW +#define AON_ACOMP1_OUT_RAW_POS (17U) +#define AON_ACOMP1_OUT_RAW_LEN (1U) +#define AON_ACOMP1_OUT_RAW_MSK (((1U << AON_ACOMP1_OUT_RAW_LEN) - 1) << AON_ACOMP1_OUT_RAW_POS) +#define AON_ACOMP1_OUT_RAW_UMSK (~(((1U << AON_ACOMP1_OUT_RAW_LEN) - 1) << AON_ACOMP1_OUT_RAW_POS)) +#define AON_ACOMP0_OUT_RAW AON_ACOMP0_OUT_RAW +#define AON_ACOMP0_OUT_RAW_POS (19U) +#define AON_ACOMP0_OUT_RAW_LEN (1U) +#define AON_ACOMP0_OUT_RAW_MSK (((1U << AON_ACOMP0_OUT_RAW_LEN) - 1) << AON_ACOMP0_OUT_RAW_POS) +#define AON_ACOMP0_OUT_RAW_UMSK (~(((1U << AON_ACOMP0_OUT_RAW_LEN) - 1) << AON_ACOMP0_OUT_RAW_POS)) +#define AON_ACOMP_RESERVED AON_ACOMP_RESERVED +#define AON_ACOMP_RESERVED_POS (24U) +#define AON_ACOMP_RESERVED_LEN (8U) +#define AON_ACOMP_RESERVED_MSK (((1U << AON_ACOMP_RESERVED_LEN) - 1) << AON_ACOMP_RESERVED_POS) +#define AON_ACOMP_RESERVED_UMSK (~(((1U << AON_ACOMP_RESERVED_LEN) - 1) << AON_ACOMP_RESERVED_POS)) + +/* 0x90C : gpadc_reg_cmd */ +#define AON_GPADC_REG_CMD_OFFSET (0x90C) +#define AON_GPADC_GLOBAL_EN AON_GPADC_GLOBAL_EN +#define AON_GPADC_GLOBAL_EN_POS (0U) +#define AON_GPADC_GLOBAL_EN_LEN (1U) +#define AON_GPADC_GLOBAL_EN_MSK (((1U << AON_GPADC_GLOBAL_EN_LEN) - 1) << AON_GPADC_GLOBAL_EN_POS) +#define AON_GPADC_GLOBAL_EN_UMSK (~(((1U << AON_GPADC_GLOBAL_EN_LEN) - 1) << AON_GPADC_GLOBAL_EN_POS)) +#define AON_GPADC_CONV_START AON_GPADC_CONV_START +#define AON_GPADC_CONV_START_POS (1U) +#define AON_GPADC_CONV_START_LEN (1U) +#define AON_GPADC_CONV_START_MSK (((1U << AON_GPADC_CONV_START_LEN) - 1) << AON_GPADC_CONV_START_POS) +#define AON_GPADC_CONV_START_UMSK (~(((1U << AON_GPADC_CONV_START_LEN) - 1) << AON_GPADC_CONV_START_POS)) +#define AON_GPADC_SOFT_RST AON_GPADC_SOFT_RST +#define AON_GPADC_SOFT_RST_POS (2U) +#define AON_GPADC_SOFT_RST_LEN (1U) +#define AON_GPADC_SOFT_RST_MSK (((1U << AON_GPADC_SOFT_RST_LEN) - 1) << AON_GPADC_SOFT_RST_POS) +#define AON_GPADC_SOFT_RST_UMSK (~(((1U << AON_GPADC_SOFT_RST_LEN) - 1) << AON_GPADC_SOFT_RST_POS)) +#define AON_GPADC_NEG_SEL AON_GPADC_NEG_SEL +#define AON_GPADC_NEG_SEL_POS (3U) +#define AON_GPADC_NEG_SEL_LEN (5U) +#define AON_GPADC_NEG_SEL_MSK (((1U << AON_GPADC_NEG_SEL_LEN) - 1) << AON_GPADC_NEG_SEL_POS) +#define AON_GPADC_NEG_SEL_UMSK (~(((1U << AON_GPADC_NEG_SEL_LEN) - 1) << AON_GPADC_NEG_SEL_POS)) +#define AON_GPADC_POS_SEL AON_GPADC_POS_SEL +#define AON_GPADC_POS_SEL_POS (8U) +#define AON_GPADC_POS_SEL_LEN (5U) +#define AON_GPADC_POS_SEL_MSK (((1U << AON_GPADC_POS_SEL_LEN) - 1) << AON_GPADC_POS_SEL_POS) +#define AON_GPADC_POS_SEL_UMSK (~(((1U << AON_GPADC_POS_SEL_LEN) - 1) << AON_GPADC_POS_SEL_POS)) +#define AON_GPADC_NEG_GND AON_GPADC_NEG_GND +#define AON_GPADC_NEG_GND_POS (13U) +#define AON_GPADC_NEG_GND_LEN (1U) +#define AON_GPADC_NEG_GND_MSK (((1U << AON_GPADC_NEG_GND_LEN) - 1) << AON_GPADC_NEG_GND_POS) +#define AON_GPADC_NEG_GND_UMSK (~(((1U << AON_GPADC_NEG_GND_LEN) - 1) << AON_GPADC_NEG_GND_POS)) +#define AON_GPADC_MICBIAS_EN AON_GPADC_MICBIAS_EN +#define AON_GPADC_MICBIAS_EN_POS (14U) +#define AON_GPADC_MICBIAS_EN_LEN (1U) +#define AON_GPADC_MICBIAS_EN_MSK (((1U << AON_GPADC_MICBIAS_EN_LEN) - 1) << AON_GPADC_MICBIAS_EN_POS) +#define AON_GPADC_MICBIAS_EN_UMSK (~(((1U << AON_GPADC_MICBIAS_EN_LEN) - 1) << AON_GPADC_MICBIAS_EN_POS)) +#define AON_GPADC_MICPGA_EN AON_GPADC_MICPGA_EN +#define AON_GPADC_MICPGA_EN_POS (15U) +#define AON_GPADC_MICPGA_EN_LEN (1U) +#define AON_GPADC_MICPGA_EN_MSK (((1U << AON_GPADC_MICPGA_EN_LEN) - 1) << AON_GPADC_MICPGA_EN_POS) +#define AON_GPADC_MICPGA_EN_UMSK (~(((1U << AON_GPADC_MICPGA_EN_LEN) - 1) << AON_GPADC_MICPGA_EN_POS)) +#define AON_GPADC_BYP_MICBOOST AON_GPADC_BYP_MICBOOST +#define AON_GPADC_BYP_MICBOOST_POS (16U) +#define AON_GPADC_BYP_MICBOOST_LEN (1U) +#define AON_GPADC_BYP_MICBOOST_MSK (((1U << AON_GPADC_BYP_MICBOOST_LEN) - 1) << AON_GPADC_BYP_MICBOOST_POS) +#define AON_GPADC_BYP_MICBOOST_UMSK (~(((1U << AON_GPADC_BYP_MICBOOST_LEN) - 1) << AON_GPADC_BYP_MICBOOST_POS)) +#define AON_GPADC_DWA_EN AON_GPADC_DWA_EN +#define AON_GPADC_DWA_EN_POS (18U) +#define AON_GPADC_DWA_EN_LEN (1U) +#define AON_GPADC_DWA_EN_MSK (((1U << AON_GPADC_DWA_EN_LEN) - 1) << AON_GPADC_DWA_EN_POS) +#define AON_GPADC_DWA_EN_UMSK (~(((1U << AON_GPADC_DWA_EN_LEN) - 1) << AON_GPADC_DWA_EN_POS)) +#define AON_GPADC_MIC2_DIFF AON_GPADC_MIC2_DIFF +#define AON_GPADC_MIC2_DIFF_POS (19U) +#define AON_GPADC_MIC2_DIFF_LEN (1U) +#define AON_GPADC_MIC2_DIFF_MSK (((1U << AON_GPADC_MIC2_DIFF_LEN) - 1) << AON_GPADC_MIC2_DIFF_POS) +#define AON_GPADC_MIC2_DIFF_UMSK (~(((1U << AON_GPADC_MIC2_DIFF_LEN) - 1) << AON_GPADC_MIC2_DIFF_POS)) +#define AON_GPADC_MIC1_DIFF AON_GPADC_MIC1_DIFF +#define AON_GPADC_MIC1_DIFF_POS (20U) +#define AON_GPADC_MIC1_DIFF_LEN (1U) +#define AON_GPADC_MIC1_DIFF_MSK (((1U << AON_GPADC_MIC1_DIFF_LEN) - 1) << AON_GPADC_MIC1_DIFF_POS) +#define AON_GPADC_MIC1_DIFF_UMSK (~(((1U << AON_GPADC_MIC1_DIFF_LEN) - 1) << AON_GPADC_MIC1_DIFF_POS)) +#define AON_GPADC_MIC_PGA2_GAIN AON_GPADC_MIC_PGA2_GAIN +#define AON_GPADC_MIC_PGA2_GAIN_POS (21U) +#define AON_GPADC_MIC_PGA2_GAIN_LEN (2U) +#define AON_GPADC_MIC_PGA2_GAIN_MSK (((1U << AON_GPADC_MIC_PGA2_GAIN_LEN) - 1) << AON_GPADC_MIC_PGA2_GAIN_POS) +#define AON_GPADC_MIC_PGA2_GAIN_UMSK (~(((1U << AON_GPADC_MIC_PGA2_GAIN_LEN) - 1) << AON_GPADC_MIC_PGA2_GAIN_POS)) +#define AON_GPADC_MICBOOST_32DB_EN AON_GPADC_MICBOOST_32DB_EN +#define AON_GPADC_MICBOOST_32DB_EN_POS (23U) +#define AON_GPADC_MICBOOST_32DB_EN_LEN (1U) +#define AON_GPADC_MICBOOST_32DB_EN_MSK (((1U << AON_GPADC_MICBOOST_32DB_EN_LEN) - 1) << AON_GPADC_MICBOOST_32DB_EN_POS) +#define AON_GPADC_MICBOOST_32DB_EN_UMSK (~(((1U << AON_GPADC_MICBOOST_32DB_EN_LEN) - 1) << AON_GPADC_MICBOOST_32DB_EN_POS)) +#define AON_GPADC_CHIP_SEN_PU AON_GPADC_CHIP_SEN_PU +#define AON_GPADC_CHIP_SEN_PU_POS (27U) +#define AON_GPADC_CHIP_SEN_PU_LEN (1U) +#define AON_GPADC_CHIP_SEN_PU_MSK (((1U << AON_GPADC_CHIP_SEN_PU_LEN) - 1) << AON_GPADC_CHIP_SEN_PU_POS) +#define AON_GPADC_CHIP_SEN_PU_UMSK (~(((1U << AON_GPADC_CHIP_SEN_PU_LEN) - 1) << AON_GPADC_CHIP_SEN_PU_POS)) +#define AON_GPADC_SEN_SEL AON_GPADC_SEN_SEL +#define AON_GPADC_SEN_SEL_POS (28U) +#define AON_GPADC_SEN_SEL_LEN (2U) +#define AON_GPADC_SEN_SEL_MSK (((1U << AON_GPADC_SEN_SEL_LEN) - 1) << AON_GPADC_SEN_SEL_POS) +#define AON_GPADC_SEN_SEL_UMSK (~(((1U << AON_GPADC_SEN_SEL_LEN) - 1) << AON_GPADC_SEN_SEL_POS)) +#define AON_GPADC_SEN_TEST_EN AON_GPADC_SEN_TEST_EN +#define AON_GPADC_SEN_TEST_EN_POS (30U) +#define AON_GPADC_SEN_TEST_EN_LEN (1U) +#define AON_GPADC_SEN_TEST_EN_MSK (((1U << AON_GPADC_SEN_TEST_EN_LEN) - 1) << AON_GPADC_SEN_TEST_EN_POS) +#define AON_GPADC_SEN_TEST_EN_UMSK (~(((1U << AON_GPADC_SEN_TEST_EN_LEN) - 1) << AON_GPADC_SEN_TEST_EN_POS)) + +/* 0x910 : gpadc_reg_config1 */ +#define AON_GPADC_REG_CONFIG1_OFFSET (0x910) +#define AON_GPADC_CAL_OS_EN AON_GPADC_CAL_OS_EN +#define AON_GPADC_CAL_OS_EN_POS (0U) +#define AON_GPADC_CAL_OS_EN_LEN (1U) +#define AON_GPADC_CAL_OS_EN_MSK (((1U << AON_GPADC_CAL_OS_EN_LEN) - 1) << AON_GPADC_CAL_OS_EN_POS) +#define AON_GPADC_CAL_OS_EN_UMSK (~(((1U << AON_GPADC_CAL_OS_EN_LEN) - 1) << AON_GPADC_CAL_OS_EN_POS)) +#define AON_GPADC_CONT_CONV_EN AON_GPADC_CONT_CONV_EN +#define AON_GPADC_CONT_CONV_EN_POS (1U) +#define AON_GPADC_CONT_CONV_EN_LEN (1U) +#define AON_GPADC_CONT_CONV_EN_MSK (((1U << AON_GPADC_CONT_CONV_EN_LEN) - 1) << AON_GPADC_CONT_CONV_EN_POS) +#define AON_GPADC_CONT_CONV_EN_UMSK (~(((1U << AON_GPADC_CONT_CONV_EN_LEN) - 1) << AON_GPADC_CONT_CONV_EN_POS)) +#define AON_GPADC_RES_SEL AON_GPADC_RES_SEL +#define AON_GPADC_RES_SEL_POS (2U) +#define AON_GPADC_RES_SEL_LEN (3U) +#define AON_GPADC_RES_SEL_MSK (((1U << AON_GPADC_RES_SEL_LEN) - 1) << AON_GPADC_RES_SEL_POS) +#define AON_GPADC_RES_SEL_UMSK (~(((1U << AON_GPADC_RES_SEL_LEN) - 1) << AON_GPADC_RES_SEL_POS)) +#define AON_GPADC_CLK_ANA_INV AON_GPADC_CLK_ANA_INV +#define AON_GPADC_CLK_ANA_INV_POS (17U) +#define AON_GPADC_CLK_ANA_INV_LEN (1U) +#define AON_GPADC_CLK_ANA_INV_MSK (((1U << AON_GPADC_CLK_ANA_INV_LEN) - 1) << AON_GPADC_CLK_ANA_INV_POS) +#define AON_GPADC_CLK_ANA_INV_UMSK (~(((1U << AON_GPADC_CLK_ANA_INV_LEN) - 1) << AON_GPADC_CLK_ANA_INV_POS)) +#define AON_GPADC_CLK_DIV_RATIO AON_GPADC_CLK_DIV_RATIO +#define AON_GPADC_CLK_DIV_RATIO_POS (18U) +#define AON_GPADC_CLK_DIV_RATIO_LEN (3U) +#define AON_GPADC_CLK_DIV_RATIO_MSK (((1U << AON_GPADC_CLK_DIV_RATIO_LEN) - 1) << AON_GPADC_CLK_DIV_RATIO_POS) +#define AON_GPADC_CLK_DIV_RATIO_UMSK (~(((1U << AON_GPADC_CLK_DIV_RATIO_LEN) - 1) << AON_GPADC_CLK_DIV_RATIO_POS)) +#define AON_GPADC_SCAN_LENGTH AON_GPADC_SCAN_LENGTH +#define AON_GPADC_SCAN_LENGTH_POS (21U) +#define AON_GPADC_SCAN_LENGTH_LEN (4U) +#define AON_GPADC_SCAN_LENGTH_MSK (((1U << AON_GPADC_SCAN_LENGTH_LEN) - 1) << AON_GPADC_SCAN_LENGTH_POS) +#define AON_GPADC_SCAN_LENGTH_UMSK (~(((1U << AON_GPADC_SCAN_LENGTH_LEN) - 1) << AON_GPADC_SCAN_LENGTH_POS)) +#define AON_GPADC_SCAN_EN AON_GPADC_SCAN_EN +#define AON_GPADC_SCAN_EN_POS (25U) +#define AON_GPADC_SCAN_EN_LEN (1U) +#define AON_GPADC_SCAN_EN_MSK (((1U << AON_GPADC_SCAN_EN_LEN) - 1) << AON_GPADC_SCAN_EN_POS) +#define AON_GPADC_SCAN_EN_UMSK (~(((1U << AON_GPADC_SCAN_EN_LEN) - 1) << AON_GPADC_SCAN_EN_POS)) +#define AON_GPADC_DITHER_EN AON_GPADC_DITHER_EN +#define AON_GPADC_DITHER_EN_POS (26U) +#define AON_GPADC_DITHER_EN_LEN (1U) +#define AON_GPADC_DITHER_EN_MSK (((1U << AON_GPADC_DITHER_EN_LEN) - 1) << AON_GPADC_DITHER_EN_POS) +#define AON_GPADC_DITHER_EN_UMSK (~(((1U << AON_GPADC_DITHER_EN_LEN) - 1) << AON_GPADC_DITHER_EN_POS)) +#define AON_GPADC_V11_SEL AON_GPADC_V11_SEL +#define AON_GPADC_V11_SEL_POS (27U) +#define AON_GPADC_V11_SEL_LEN (2U) +#define AON_GPADC_V11_SEL_MSK (((1U << AON_GPADC_V11_SEL_LEN) - 1) << AON_GPADC_V11_SEL_POS) +#define AON_GPADC_V11_SEL_UMSK (~(((1U << AON_GPADC_V11_SEL_LEN) - 1) << AON_GPADC_V11_SEL_POS)) +#define AON_GPADC_V18_SEL AON_GPADC_V18_SEL +#define AON_GPADC_V18_SEL_POS (29U) +#define AON_GPADC_V18_SEL_LEN (2U) +#define AON_GPADC_V18_SEL_MSK (((1U << AON_GPADC_V18_SEL_LEN) - 1) << AON_GPADC_V18_SEL_POS) +#define AON_GPADC_V18_SEL_UMSK (~(((1U << AON_GPADC_V18_SEL_LEN) - 1) << AON_GPADC_V18_SEL_POS)) + +/* 0x914 : gpadc_reg_config2 */ +#define AON_GPADC_REG_CONFIG2_OFFSET (0x914) +#define AON_GPADC_DIFF_MODE AON_GPADC_DIFF_MODE +#define AON_GPADC_DIFF_MODE_POS (2U) +#define AON_GPADC_DIFF_MODE_LEN (1U) +#define AON_GPADC_DIFF_MODE_MSK (((1U << AON_GPADC_DIFF_MODE_LEN) - 1) << AON_GPADC_DIFF_MODE_POS) +#define AON_GPADC_DIFF_MODE_UMSK (~(((1U << AON_GPADC_DIFF_MODE_LEN) - 1) << AON_GPADC_DIFF_MODE_POS)) +#define AON_GPADC_VREF_SEL AON_GPADC_VREF_SEL +#define AON_GPADC_VREF_SEL_POS (3U) +#define AON_GPADC_VREF_SEL_LEN (1U) +#define AON_GPADC_VREF_SEL_MSK (((1U << AON_GPADC_VREF_SEL_LEN) - 1) << AON_GPADC_VREF_SEL_POS) +#define AON_GPADC_VREF_SEL_UMSK (~(((1U << AON_GPADC_VREF_SEL_LEN) - 1) << AON_GPADC_VREF_SEL_POS)) +#define AON_GPADC_VBAT_EN AON_GPADC_VBAT_EN +#define AON_GPADC_VBAT_EN_POS (4U) +#define AON_GPADC_VBAT_EN_LEN (1U) +#define AON_GPADC_VBAT_EN_MSK (((1U << AON_GPADC_VBAT_EN_LEN) - 1) << AON_GPADC_VBAT_EN_POS) +#define AON_GPADC_VBAT_EN_UMSK (~(((1U << AON_GPADC_VBAT_EN_LEN) - 1) << AON_GPADC_VBAT_EN_POS)) +#define AON_GPADC_TSEXT_SEL AON_GPADC_TSEXT_SEL +#define AON_GPADC_TSEXT_SEL_POS (5U) +#define AON_GPADC_TSEXT_SEL_LEN (1U) +#define AON_GPADC_TSEXT_SEL_MSK (((1U << AON_GPADC_TSEXT_SEL_LEN) - 1) << AON_GPADC_TSEXT_SEL_POS) +#define AON_GPADC_TSEXT_SEL_UMSK (~(((1U << AON_GPADC_TSEXT_SEL_LEN) - 1) << AON_GPADC_TSEXT_SEL_POS)) +#define AON_GPADC_TS_EN AON_GPADC_TS_EN +#define AON_GPADC_TS_EN_POS (6U) +#define AON_GPADC_TS_EN_LEN (1U) +#define AON_GPADC_TS_EN_MSK (((1U << AON_GPADC_TS_EN_LEN) - 1) << AON_GPADC_TS_EN_POS) +#define AON_GPADC_TS_EN_UMSK (~(((1U << AON_GPADC_TS_EN_LEN) - 1) << AON_GPADC_TS_EN_POS)) +#define AON_GPADC_PGA_VCM AON_GPADC_PGA_VCM +#define AON_GPADC_PGA_VCM_POS (7U) +#define AON_GPADC_PGA_VCM_LEN (2U) +#define AON_GPADC_PGA_VCM_MSK (((1U << AON_GPADC_PGA_VCM_LEN) - 1) << AON_GPADC_PGA_VCM_POS) +#define AON_GPADC_PGA_VCM_UMSK (~(((1U << AON_GPADC_PGA_VCM_LEN) - 1) << AON_GPADC_PGA_VCM_POS)) +#define AON_GPADC_PGA_OS_CAL AON_GPADC_PGA_OS_CAL +#define AON_GPADC_PGA_OS_CAL_POS (9U) +#define AON_GPADC_PGA_OS_CAL_LEN (4U) +#define AON_GPADC_PGA_OS_CAL_MSK (((1U << AON_GPADC_PGA_OS_CAL_LEN) - 1) << AON_GPADC_PGA_OS_CAL_POS) +#define AON_GPADC_PGA_OS_CAL_UMSK (~(((1U << AON_GPADC_PGA_OS_CAL_LEN) - 1) << AON_GPADC_PGA_OS_CAL_POS)) +#define AON_GPADC_PGA_EN AON_GPADC_PGA_EN +#define AON_GPADC_PGA_EN_POS (13U) +#define AON_GPADC_PGA_EN_LEN (1U) +#define AON_GPADC_PGA_EN_MSK (((1U << AON_GPADC_PGA_EN_LEN) - 1) << AON_GPADC_PGA_EN_POS) +#define AON_GPADC_PGA_EN_UMSK (~(((1U << AON_GPADC_PGA_EN_LEN) - 1) << AON_GPADC_PGA_EN_POS)) +#define AON_GPADC_PGA_VCMI_EN AON_GPADC_PGA_VCMI_EN +#define AON_GPADC_PGA_VCMI_EN_POS (14U) +#define AON_GPADC_PGA_VCMI_EN_LEN (1U) +#define AON_GPADC_PGA_VCMI_EN_MSK (((1U << AON_GPADC_PGA_VCMI_EN_LEN) - 1) << AON_GPADC_PGA_VCMI_EN_POS) +#define AON_GPADC_PGA_VCMI_EN_UMSK (~(((1U << AON_GPADC_PGA_VCMI_EN_LEN) - 1) << AON_GPADC_PGA_VCMI_EN_POS)) +#define AON_GPADC_CHOP_MODE AON_GPADC_CHOP_MODE +#define AON_GPADC_CHOP_MODE_POS (15U) +#define AON_GPADC_CHOP_MODE_LEN (2U) +#define AON_GPADC_CHOP_MODE_MSK (((1U << AON_GPADC_CHOP_MODE_LEN) - 1) << AON_GPADC_CHOP_MODE_POS) +#define AON_GPADC_CHOP_MODE_UMSK (~(((1U << AON_GPADC_CHOP_MODE_LEN) - 1) << AON_GPADC_CHOP_MODE_POS)) +#define AON_GPADC_BIAS_SEL AON_GPADC_BIAS_SEL +#define AON_GPADC_BIAS_SEL_POS (17U) +#define AON_GPADC_BIAS_SEL_LEN (1U) +#define AON_GPADC_BIAS_SEL_MSK (((1U << AON_GPADC_BIAS_SEL_LEN) - 1) << AON_GPADC_BIAS_SEL_POS) +#define AON_GPADC_BIAS_SEL_UMSK (~(((1U << AON_GPADC_BIAS_SEL_LEN) - 1) << AON_GPADC_BIAS_SEL_POS)) +#define AON_GPADC_TEST_EN AON_GPADC_TEST_EN +#define AON_GPADC_TEST_EN_POS (18U) +#define AON_GPADC_TEST_EN_LEN (1U) +#define AON_GPADC_TEST_EN_MSK (((1U << AON_GPADC_TEST_EN_LEN) - 1) << AON_GPADC_TEST_EN_POS) +#define AON_GPADC_TEST_EN_UMSK (~(((1U << AON_GPADC_TEST_EN_LEN) - 1) << AON_GPADC_TEST_EN_POS)) +#define AON_GPADC_TEST_SEL AON_GPADC_TEST_SEL +#define AON_GPADC_TEST_SEL_POS (19U) +#define AON_GPADC_TEST_SEL_LEN (3U) +#define AON_GPADC_TEST_SEL_MSK (((1U << AON_GPADC_TEST_SEL_LEN) - 1) << AON_GPADC_TEST_SEL_POS) +#define AON_GPADC_TEST_SEL_UMSK (~(((1U << AON_GPADC_TEST_SEL_LEN) - 1) << AON_GPADC_TEST_SEL_POS)) +#define AON_GPADC_PGA2_GAIN AON_GPADC_PGA2_GAIN +#define AON_GPADC_PGA2_GAIN_POS (22U) +#define AON_GPADC_PGA2_GAIN_LEN (3U) +#define AON_GPADC_PGA2_GAIN_MSK (((1U << AON_GPADC_PGA2_GAIN_LEN) - 1) << AON_GPADC_PGA2_GAIN_POS) +#define AON_GPADC_PGA2_GAIN_UMSK (~(((1U << AON_GPADC_PGA2_GAIN_LEN) - 1) << AON_GPADC_PGA2_GAIN_POS)) +#define AON_GPADC_PGA1_GAIN AON_GPADC_PGA1_GAIN +#define AON_GPADC_PGA1_GAIN_POS (25U) +#define AON_GPADC_PGA1_GAIN_LEN (3U) +#define AON_GPADC_PGA1_GAIN_MSK (((1U << AON_GPADC_PGA1_GAIN_LEN) - 1) << AON_GPADC_PGA1_GAIN_POS) +#define AON_GPADC_PGA1_GAIN_UMSK (~(((1U << AON_GPADC_PGA1_GAIN_LEN) - 1) << AON_GPADC_PGA1_GAIN_POS)) +#define AON_GPADC_DLY_SEL AON_GPADC_DLY_SEL +#define AON_GPADC_DLY_SEL_POS (28U) +#define AON_GPADC_DLY_SEL_LEN (3U) +#define AON_GPADC_DLY_SEL_MSK (((1U << AON_GPADC_DLY_SEL_LEN) - 1) << AON_GPADC_DLY_SEL_POS) +#define AON_GPADC_DLY_SEL_UMSK (~(((1U << AON_GPADC_DLY_SEL_LEN) - 1) << AON_GPADC_DLY_SEL_POS)) +#define AON_GPADC_TSVBE_LOW AON_GPADC_TSVBE_LOW +#define AON_GPADC_TSVBE_LOW_POS (31U) +#define AON_GPADC_TSVBE_LOW_LEN (1U) +#define AON_GPADC_TSVBE_LOW_MSK (((1U << AON_GPADC_TSVBE_LOW_LEN) - 1) << AON_GPADC_TSVBE_LOW_POS) +#define AON_GPADC_TSVBE_LOW_UMSK (~(((1U << AON_GPADC_TSVBE_LOW_LEN) - 1) << AON_GPADC_TSVBE_LOW_POS)) + +/* 0x918 : adc converation sequence 1 */ +#define AON_GPADC_REG_SCN_POS1_OFFSET (0x918) +#define AON_GPADC_SCAN_POS_0 AON_GPADC_SCAN_POS_0 +#define AON_GPADC_SCAN_POS_0_POS (0U) +#define AON_GPADC_SCAN_POS_0_LEN (5U) +#define AON_GPADC_SCAN_POS_0_MSK (((1U << AON_GPADC_SCAN_POS_0_LEN) - 1) << AON_GPADC_SCAN_POS_0_POS) +#define AON_GPADC_SCAN_POS_0_UMSK (~(((1U << AON_GPADC_SCAN_POS_0_LEN) - 1) << AON_GPADC_SCAN_POS_0_POS)) +#define AON_GPADC_SCAN_POS_1 AON_GPADC_SCAN_POS_1 +#define AON_GPADC_SCAN_POS_1_POS (5U) +#define AON_GPADC_SCAN_POS_1_LEN (5U) +#define AON_GPADC_SCAN_POS_1_MSK (((1U << AON_GPADC_SCAN_POS_1_LEN) - 1) << AON_GPADC_SCAN_POS_1_POS) +#define AON_GPADC_SCAN_POS_1_UMSK (~(((1U << AON_GPADC_SCAN_POS_1_LEN) - 1) << AON_GPADC_SCAN_POS_1_POS)) +#define AON_GPADC_SCAN_POS_2 AON_GPADC_SCAN_POS_2 +#define AON_GPADC_SCAN_POS_2_POS (10U) +#define AON_GPADC_SCAN_POS_2_LEN (5U) +#define AON_GPADC_SCAN_POS_2_MSK (((1U << AON_GPADC_SCAN_POS_2_LEN) - 1) << AON_GPADC_SCAN_POS_2_POS) +#define AON_GPADC_SCAN_POS_2_UMSK (~(((1U << AON_GPADC_SCAN_POS_2_LEN) - 1) << AON_GPADC_SCAN_POS_2_POS)) +#define AON_GPADC_SCAN_POS_3 AON_GPADC_SCAN_POS_3 +#define AON_GPADC_SCAN_POS_3_POS (15U) +#define AON_GPADC_SCAN_POS_3_LEN (5U) +#define AON_GPADC_SCAN_POS_3_MSK (((1U << AON_GPADC_SCAN_POS_3_LEN) - 1) << AON_GPADC_SCAN_POS_3_POS) +#define AON_GPADC_SCAN_POS_3_UMSK (~(((1U << AON_GPADC_SCAN_POS_3_LEN) - 1) << AON_GPADC_SCAN_POS_3_POS)) +#define AON_GPADC_SCAN_POS_4 AON_GPADC_SCAN_POS_4 +#define AON_GPADC_SCAN_POS_4_POS (20U) +#define AON_GPADC_SCAN_POS_4_LEN (5U) +#define AON_GPADC_SCAN_POS_4_MSK (((1U << AON_GPADC_SCAN_POS_4_LEN) - 1) << AON_GPADC_SCAN_POS_4_POS) +#define AON_GPADC_SCAN_POS_4_UMSK (~(((1U << AON_GPADC_SCAN_POS_4_LEN) - 1) << AON_GPADC_SCAN_POS_4_POS)) +#define AON_GPADC_SCAN_POS_5 AON_GPADC_SCAN_POS_5 +#define AON_GPADC_SCAN_POS_5_POS (25U) +#define AON_GPADC_SCAN_POS_5_LEN (5U) +#define AON_GPADC_SCAN_POS_5_MSK (((1U << AON_GPADC_SCAN_POS_5_LEN) - 1) << AON_GPADC_SCAN_POS_5_POS) +#define AON_GPADC_SCAN_POS_5_UMSK (~(((1U << AON_GPADC_SCAN_POS_5_LEN) - 1) << AON_GPADC_SCAN_POS_5_POS)) + +/* 0x91C : adc converation sequence 2 */ +#define AON_GPADC_REG_SCN_POS2_OFFSET (0x91C) +#define AON_GPADC_SCAN_POS_6 AON_GPADC_SCAN_POS_6 +#define AON_GPADC_SCAN_POS_6_POS (0U) +#define AON_GPADC_SCAN_POS_6_LEN (5U) +#define AON_GPADC_SCAN_POS_6_MSK (((1U << AON_GPADC_SCAN_POS_6_LEN) - 1) << AON_GPADC_SCAN_POS_6_POS) +#define AON_GPADC_SCAN_POS_6_UMSK (~(((1U << AON_GPADC_SCAN_POS_6_LEN) - 1) << AON_GPADC_SCAN_POS_6_POS)) +#define AON_GPADC_SCAN_POS_7 AON_GPADC_SCAN_POS_7 +#define AON_GPADC_SCAN_POS_7_POS (5U) +#define AON_GPADC_SCAN_POS_7_LEN (5U) +#define AON_GPADC_SCAN_POS_7_MSK (((1U << AON_GPADC_SCAN_POS_7_LEN) - 1) << AON_GPADC_SCAN_POS_7_POS) +#define AON_GPADC_SCAN_POS_7_UMSK (~(((1U << AON_GPADC_SCAN_POS_7_LEN) - 1) << AON_GPADC_SCAN_POS_7_POS)) +#define AON_GPADC_SCAN_POS_8 AON_GPADC_SCAN_POS_8 +#define AON_GPADC_SCAN_POS_8_POS (10U) +#define AON_GPADC_SCAN_POS_8_LEN (5U) +#define AON_GPADC_SCAN_POS_8_MSK (((1U << AON_GPADC_SCAN_POS_8_LEN) - 1) << AON_GPADC_SCAN_POS_8_POS) +#define AON_GPADC_SCAN_POS_8_UMSK (~(((1U << AON_GPADC_SCAN_POS_8_LEN) - 1) << AON_GPADC_SCAN_POS_8_POS)) +#define AON_GPADC_SCAN_POS_9 AON_GPADC_SCAN_POS_9 +#define AON_GPADC_SCAN_POS_9_POS (15U) +#define AON_GPADC_SCAN_POS_9_LEN (5U) +#define AON_GPADC_SCAN_POS_9_MSK (((1U << AON_GPADC_SCAN_POS_9_LEN) - 1) << AON_GPADC_SCAN_POS_9_POS) +#define AON_GPADC_SCAN_POS_9_UMSK (~(((1U << AON_GPADC_SCAN_POS_9_LEN) - 1) << AON_GPADC_SCAN_POS_9_POS)) +#define AON_GPADC_SCAN_POS_10 AON_GPADC_SCAN_POS_10 +#define AON_GPADC_SCAN_POS_10_POS (20U) +#define AON_GPADC_SCAN_POS_10_LEN (5U) +#define AON_GPADC_SCAN_POS_10_MSK (((1U << AON_GPADC_SCAN_POS_10_LEN) - 1) << AON_GPADC_SCAN_POS_10_POS) +#define AON_GPADC_SCAN_POS_10_UMSK (~(((1U << AON_GPADC_SCAN_POS_10_LEN) - 1) << AON_GPADC_SCAN_POS_10_POS)) +#define AON_GPADC_SCAN_POS_11 AON_GPADC_SCAN_POS_11 +#define AON_GPADC_SCAN_POS_11_POS (25U) +#define AON_GPADC_SCAN_POS_11_LEN (5U) +#define AON_GPADC_SCAN_POS_11_MSK (((1U << AON_GPADC_SCAN_POS_11_LEN) - 1) << AON_GPADC_SCAN_POS_11_POS) +#define AON_GPADC_SCAN_POS_11_UMSK (~(((1U << AON_GPADC_SCAN_POS_11_LEN) - 1) << AON_GPADC_SCAN_POS_11_POS)) + +/* 0x920 : adc converation sequence 3 */ +#define AON_GPADC_REG_SCN_NEG1_OFFSET (0x920) +#define AON_GPADC_SCAN_NEG_0 AON_GPADC_SCAN_NEG_0 +#define AON_GPADC_SCAN_NEG_0_POS (0U) +#define AON_GPADC_SCAN_NEG_0_LEN (5U) +#define AON_GPADC_SCAN_NEG_0_MSK (((1U << AON_GPADC_SCAN_NEG_0_LEN) - 1) << AON_GPADC_SCAN_NEG_0_POS) +#define AON_GPADC_SCAN_NEG_0_UMSK (~(((1U << AON_GPADC_SCAN_NEG_0_LEN) - 1) << AON_GPADC_SCAN_NEG_0_POS)) +#define AON_GPADC_SCAN_NEG_1 AON_GPADC_SCAN_NEG_1 +#define AON_GPADC_SCAN_NEG_1_POS (5U) +#define AON_GPADC_SCAN_NEG_1_LEN (5U) +#define AON_GPADC_SCAN_NEG_1_MSK (((1U << AON_GPADC_SCAN_NEG_1_LEN) - 1) << AON_GPADC_SCAN_NEG_1_POS) +#define AON_GPADC_SCAN_NEG_1_UMSK (~(((1U << AON_GPADC_SCAN_NEG_1_LEN) - 1) << AON_GPADC_SCAN_NEG_1_POS)) +#define AON_GPADC_SCAN_NEG_2 AON_GPADC_SCAN_NEG_2 +#define AON_GPADC_SCAN_NEG_2_POS (10U) +#define AON_GPADC_SCAN_NEG_2_LEN (5U) +#define AON_GPADC_SCAN_NEG_2_MSK (((1U << AON_GPADC_SCAN_NEG_2_LEN) - 1) << AON_GPADC_SCAN_NEG_2_POS) +#define AON_GPADC_SCAN_NEG_2_UMSK (~(((1U << AON_GPADC_SCAN_NEG_2_LEN) - 1) << AON_GPADC_SCAN_NEG_2_POS)) +#define AON_GPADC_SCAN_NEG_3 AON_GPADC_SCAN_NEG_3 +#define AON_GPADC_SCAN_NEG_3_POS (15U) +#define AON_GPADC_SCAN_NEG_3_LEN (5U) +#define AON_GPADC_SCAN_NEG_3_MSK (((1U << AON_GPADC_SCAN_NEG_3_LEN) - 1) << AON_GPADC_SCAN_NEG_3_POS) +#define AON_GPADC_SCAN_NEG_3_UMSK (~(((1U << AON_GPADC_SCAN_NEG_3_LEN) - 1) << AON_GPADC_SCAN_NEG_3_POS)) +#define AON_GPADC_SCAN_NEG_4 AON_GPADC_SCAN_NEG_4 +#define AON_GPADC_SCAN_NEG_4_POS (20U) +#define AON_GPADC_SCAN_NEG_4_LEN (5U) +#define AON_GPADC_SCAN_NEG_4_MSK (((1U << AON_GPADC_SCAN_NEG_4_LEN) - 1) << AON_GPADC_SCAN_NEG_4_POS) +#define AON_GPADC_SCAN_NEG_4_UMSK (~(((1U << AON_GPADC_SCAN_NEG_4_LEN) - 1) << AON_GPADC_SCAN_NEG_4_POS)) +#define AON_GPADC_SCAN_NEG_5 AON_GPADC_SCAN_NEG_5 +#define AON_GPADC_SCAN_NEG_5_POS (25U) +#define AON_GPADC_SCAN_NEG_5_LEN (5U) +#define AON_GPADC_SCAN_NEG_5_MSK (((1U << AON_GPADC_SCAN_NEG_5_LEN) - 1) << AON_GPADC_SCAN_NEG_5_POS) +#define AON_GPADC_SCAN_NEG_5_UMSK (~(((1U << AON_GPADC_SCAN_NEG_5_LEN) - 1) << AON_GPADC_SCAN_NEG_5_POS)) + +/* 0x924 : adc converation sequence 4 */ +#define AON_GPADC_REG_SCN_NEG2_OFFSET (0x924) +#define AON_GPADC_SCAN_NEG_6 AON_GPADC_SCAN_NEG_6 +#define AON_GPADC_SCAN_NEG_6_POS (0U) +#define AON_GPADC_SCAN_NEG_6_LEN (5U) +#define AON_GPADC_SCAN_NEG_6_MSK (((1U << AON_GPADC_SCAN_NEG_6_LEN) - 1) << AON_GPADC_SCAN_NEG_6_POS) +#define AON_GPADC_SCAN_NEG_6_UMSK (~(((1U << AON_GPADC_SCAN_NEG_6_LEN) - 1) << AON_GPADC_SCAN_NEG_6_POS)) +#define AON_GPADC_SCAN_NEG_7 AON_GPADC_SCAN_NEG_7 +#define AON_GPADC_SCAN_NEG_7_POS (5U) +#define AON_GPADC_SCAN_NEG_7_LEN (5U) +#define AON_GPADC_SCAN_NEG_7_MSK (((1U << AON_GPADC_SCAN_NEG_7_LEN) - 1) << AON_GPADC_SCAN_NEG_7_POS) +#define AON_GPADC_SCAN_NEG_7_UMSK (~(((1U << AON_GPADC_SCAN_NEG_7_LEN) - 1) << AON_GPADC_SCAN_NEG_7_POS)) +#define AON_GPADC_SCAN_NEG_8 AON_GPADC_SCAN_NEG_8 +#define AON_GPADC_SCAN_NEG_8_POS (10U) +#define AON_GPADC_SCAN_NEG_8_LEN (5U) +#define AON_GPADC_SCAN_NEG_8_MSK (((1U << AON_GPADC_SCAN_NEG_8_LEN) - 1) << AON_GPADC_SCAN_NEG_8_POS) +#define AON_GPADC_SCAN_NEG_8_UMSK (~(((1U << AON_GPADC_SCAN_NEG_8_LEN) - 1) << AON_GPADC_SCAN_NEG_8_POS)) +#define AON_GPADC_SCAN_NEG_9 AON_GPADC_SCAN_NEG_9 +#define AON_GPADC_SCAN_NEG_9_POS (15U) +#define AON_GPADC_SCAN_NEG_9_LEN (5U) +#define AON_GPADC_SCAN_NEG_9_MSK (((1U << AON_GPADC_SCAN_NEG_9_LEN) - 1) << AON_GPADC_SCAN_NEG_9_POS) +#define AON_GPADC_SCAN_NEG_9_UMSK (~(((1U << AON_GPADC_SCAN_NEG_9_LEN) - 1) << AON_GPADC_SCAN_NEG_9_POS)) +#define AON_GPADC_SCAN_NEG_10 AON_GPADC_SCAN_NEG_10 +#define AON_GPADC_SCAN_NEG_10_POS (20U) +#define AON_GPADC_SCAN_NEG_10_LEN (5U) +#define AON_GPADC_SCAN_NEG_10_MSK (((1U << AON_GPADC_SCAN_NEG_10_LEN) - 1) << AON_GPADC_SCAN_NEG_10_POS) +#define AON_GPADC_SCAN_NEG_10_UMSK (~(((1U << AON_GPADC_SCAN_NEG_10_LEN) - 1) << AON_GPADC_SCAN_NEG_10_POS)) +#define AON_GPADC_SCAN_NEG_11 AON_GPADC_SCAN_NEG_11 +#define AON_GPADC_SCAN_NEG_11_POS (25U) +#define AON_GPADC_SCAN_NEG_11_LEN (5U) +#define AON_GPADC_SCAN_NEG_11_MSK (((1U << AON_GPADC_SCAN_NEG_11_LEN) - 1) << AON_GPADC_SCAN_NEG_11_POS) +#define AON_GPADC_SCAN_NEG_11_UMSK (~(((1U << AON_GPADC_SCAN_NEG_11_LEN) - 1) << AON_GPADC_SCAN_NEG_11_POS)) + +/* 0x928 : gpadc_reg_status */ +#define AON_GPADC_REG_STATUS_OFFSET (0x928) +#define AON_GPADC_DATA_RDY AON_GPADC_DATA_RDY +#define AON_GPADC_DATA_RDY_POS (0U) +#define AON_GPADC_DATA_RDY_LEN (1U) +#define AON_GPADC_DATA_RDY_MSK (((1U << AON_GPADC_DATA_RDY_LEN) - 1) << AON_GPADC_DATA_RDY_POS) +#define AON_GPADC_DATA_RDY_UMSK (~(((1U << AON_GPADC_DATA_RDY_LEN) - 1) << AON_GPADC_DATA_RDY_POS)) +#define AON_GPADC_RESERVED AON_GPADC_RESERVED +#define AON_GPADC_RESERVED_POS (16U) +#define AON_GPADC_RESERVED_LEN (16U) +#define AON_GPADC_RESERVED_MSK (((1U << AON_GPADC_RESERVED_LEN) - 1) << AON_GPADC_RESERVED_POS) +#define AON_GPADC_RESERVED_UMSK (~(((1U << AON_GPADC_RESERVED_LEN) - 1) << AON_GPADC_RESERVED_POS)) + +/* 0x92C : gpadc_reg_isr */ +#define AON_GPADC_REG_ISR_OFFSET (0x92C) +#define AON_GPADC_NEG_SATUR AON_GPADC_NEG_SATUR +#define AON_GPADC_NEG_SATUR_POS (0U) +#define AON_GPADC_NEG_SATUR_LEN (1U) +#define AON_GPADC_NEG_SATUR_MSK (((1U << AON_GPADC_NEG_SATUR_LEN) - 1) << AON_GPADC_NEG_SATUR_POS) +#define AON_GPADC_NEG_SATUR_UMSK (~(((1U << AON_GPADC_NEG_SATUR_LEN) - 1) << AON_GPADC_NEG_SATUR_POS)) +#define AON_GPADC_POS_SATUR AON_GPADC_POS_SATUR +#define AON_GPADC_POS_SATUR_POS (1U) +#define AON_GPADC_POS_SATUR_LEN (1U) +#define AON_GPADC_POS_SATUR_MSK (((1U << AON_GPADC_POS_SATUR_LEN) - 1) << AON_GPADC_POS_SATUR_POS) +#define AON_GPADC_POS_SATUR_UMSK (~(((1U << AON_GPADC_POS_SATUR_LEN) - 1) << AON_GPADC_POS_SATUR_POS)) +#define AON_GPADC_NEG_SATUR_CLR AON_GPADC_NEG_SATUR_CLR +#define AON_GPADC_NEG_SATUR_CLR_POS (4U) +#define AON_GPADC_NEG_SATUR_CLR_LEN (1U) +#define AON_GPADC_NEG_SATUR_CLR_MSK (((1U << AON_GPADC_NEG_SATUR_CLR_LEN) - 1) << AON_GPADC_NEG_SATUR_CLR_POS) +#define AON_GPADC_NEG_SATUR_CLR_UMSK (~(((1U << AON_GPADC_NEG_SATUR_CLR_LEN) - 1) << AON_GPADC_NEG_SATUR_CLR_POS)) +#define AON_GPADC_POS_SATUR_CLR AON_GPADC_POS_SATUR_CLR +#define AON_GPADC_POS_SATUR_CLR_POS (5U) +#define AON_GPADC_POS_SATUR_CLR_LEN (1U) +#define AON_GPADC_POS_SATUR_CLR_MSK (((1U << AON_GPADC_POS_SATUR_CLR_LEN) - 1) << AON_GPADC_POS_SATUR_CLR_POS) +#define AON_GPADC_POS_SATUR_CLR_UMSK (~(((1U << AON_GPADC_POS_SATUR_CLR_LEN) - 1) << AON_GPADC_POS_SATUR_CLR_POS)) +#define AON_GPADC_NEG_SATUR_MASK AON_GPADC_NEG_SATUR_MASK +#define AON_GPADC_NEG_SATUR_MASK_POS (8U) +#define AON_GPADC_NEG_SATUR_MASK_LEN (1U) +#define AON_GPADC_NEG_SATUR_MASK_MSK (((1U << AON_GPADC_NEG_SATUR_MASK_LEN) - 1) << AON_GPADC_NEG_SATUR_MASK_POS) +#define AON_GPADC_NEG_SATUR_MASK_UMSK (~(((1U << AON_GPADC_NEG_SATUR_MASK_LEN) - 1) << AON_GPADC_NEG_SATUR_MASK_POS)) +#define AON_GPADC_POS_SATUR_MASK AON_GPADC_POS_SATUR_MASK +#define AON_GPADC_POS_SATUR_MASK_POS (9U) +#define AON_GPADC_POS_SATUR_MASK_LEN (1U) +#define AON_GPADC_POS_SATUR_MASK_MSK (((1U << AON_GPADC_POS_SATUR_MASK_LEN) - 1) << AON_GPADC_POS_SATUR_MASK_POS) +#define AON_GPADC_POS_SATUR_MASK_UMSK (~(((1U << AON_GPADC_POS_SATUR_MASK_LEN) - 1) << AON_GPADC_POS_SATUR_MASK_POS)) + +/* 0x930 : gpadc_reg_result */ +#define AON_GPADC_REG_RESULT_OFFSET (0x930) +#define AON_GPADC_DATA_OUT AON_GPADC_DATA_OUT +#define AON_GPADC_DATA_OUT_POS (0U) +#define AON_GPADC_DATA_OUT_LEN (26U) +#define AON_GPADC_DATA_OUT_MSK (((1U << AON_GPADC_DATA_OUT_LEN) - 1) << AON_GPADC_DATA_OUT_POS) +#define AON_GPADC_DATA_OUT_UMSK (~(((1U << AON_GPADC_DATA_OUT_LEN) - 1) << AON_GPADC_DATA_OUT_POS)) + +/* 0x934 : gpadc_reg_raw_result */ +#define AON_GPADC_REG_RAW_RESULT_OFFSET (0x934) +#define AON_GPADC_RAW_DATA AON_GPADC_RAW_DATA +#define AON_GPADC_RAW_DATA_POS (0U) +#define AON_GPADC_RAW_DATA_LEN (12U) +#define AON_GPADC_RAW_DATA_MSK (((1U << AON_GPADC_RAW_DATA_LEN) - 1) << AON_GPADC_RAW_DATA_POS) +#define AON_GPADC_RAW_DATA_UMSK (~(((1U << AON_GPADC_RAW_DATA_LEN) - 1) << AON_GPADC_RAW_DATA_POS)) + +/* 0x938 : gpadc_reg_define */ +#define AON_GPADC_REG_DEFINE_OFFSET (0x938) +#define AON_GPADC_OS_CAL_DATA AON_GPADC_OS_CAL_DATA +#define AON_GPADC_OS_CAL_DATA_POS (0U) +#define AON_GPADC_OS_CAL_DATA_LEN (16U) +#define AON_GPADC_OS_CAL_DATA_MSK (((1U << AON_GPADC_OS_CAL_DATA_LEN) - 1) << AON_GPADC_OS_CAL_DATA_POS) +#define AON_GPADC_OS_CAL_DATA_UMSK (~(((1U << AON_GPADC_OS_CAL_DATA_LEN) - 1) << AON_GPADC_OS_CAL_DATA_POS)) + +/* 0x93C : hbncore_resv0 */ +#define AON_HBNCORE_RESV0_OFFSET (0x93C) +#define AON_HBNCORE_RESV0_DATA AON_HBNCORE_RESV0_DATA +#define AON_HBNCORE_RESV0_DATA_POS (0U) +#define AON_HBNCORE_RESV0_DATA_LEN (32U) +#define AON_HBNCORE_RESV0_DATA_MSK (((1U << AON_HBNCORE_RESV0_DATA_LEN) - 1) << AON_HBNCORE_RESV0_DATA_POS) +#define AON_HBNCORE_RESV0_DATA_UMSK (~(((1U << AON_HBNCORE_RESV0_DATA_LEN) - 1) << AON_HBNCORE_RESV0_DATA_POS)) + +/* 0x940 : hbncore_resv1 */ +#define AON_HBNCORE_RESV1_OFFSET (0x940) +#define AON_HBNCORE_RESV1_DATA AON_HBNCORE_RESV1_DATA +#define AON_HBNCORE_RESV1_DATA_POS (0U) +#define AON_HBNCORE_RESV1_DATA_LEN (32U) +#define AON_HBNCORE_RESV1_DATA_MSK (((1U << AON_HBNCORE_RESV1_DATA_LEN) - 1) << AON_HBNCORE_RESV1_DATA_POS) +#define AON_HBNCORE_RESV1_DATA_UMSK (~(((1U << AON_HBNCORE_RESV1_DATA_LEN) - 1) << AON_HBNCORE_RESV1_DATA_POS)) + +struct aon_reg { + /* 0x0 reserved */ + uint8_t RESERVED0x0[2048]; + + /* 0x800 : aon */ + union { + struct + { + uint32_t aon_resv : 8; /* [ 7: 0], r/w, 0x0 */ + uint32_t reserved_8_11 : 4; /* [11: 8], rsvd, 0x0 */ + uint32_t pu_aon_dc_tbuf : 1; /* [ 12], r/w, 0x0 */ + uint32_t reserved_13_19 : 7; /* [19:13], rsvd, 0x0 */ + uint32_t ldo11_rt_pulldown : 1; /* [ 20], r/w, 0x0 */ + uint32_t ldo11_rt_pulldown_sel : 1; /* [ 21], r/w, 0x0 */ + uint32_t sw_pu_ldo11_rt : 1; /* [ 22], r/w, 0x1 */ + uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } aon; + + /* 0x804 : aon_common */ + union { + struct + { + uint32_t tmux_aon : 3; /* [ 2: 0], r/w, 0x0 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t ten_aon : 1; /* [ 4], r/w, 0x0 */ + uint32_t dten_xtal32k : 1; /* [ 5], r/w, 0x0 */ + uint32_t ten_xtal32k : 1; /* [ 6], r/w, 0x0 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t ten_vddcore_aon : 1; /* [ 8], r/w, 0x0 */ + uint32_t ten_ldo11soc_aon : 1; /* [ 9], r/w, 0x0 */ + uint32_t ten_dcdc18_0_aon : 1; /* [ 10], r/w, 0x0 */ + uint32_t ten_dcdc18_1_aon : 1; /* [ 11], r/w, 0x0 */ + uint32_t ten_bg_sys_aon : 1; /* [ 12], r/w, 0x0 */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t ten_ldo15rf_aon : 1; /* [ 16], r/w, 0x0 */ + uint32_t ten_xtal_aon : 1; /* [ 17], r/w, 0x0 */ + uint32_t dten_xtal_aon : 1; /* [ 18], r/w, 0x0 */ + uint32_t ten_mbg_aon : 1; /* [ 19], r/w, 0x0 */ + uint32_t ten_cip_misc_aon : 1; /* [ 20], r/w, 0x0 */ + uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } aon_common; + + /* 0x808 : aon_misc */ + union { + struct + { + uint32_t sw_soc_en_aon : 1; /* [ 0], r/w, 0x1 */ + uint32_t sw_wb_en_aon : 1; /* [ 1], r/w, 0x1 */ + uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } aon_misc; + + /* 0x80c reserved */ + uint8_t RESERVED0x80c[4]; + + /* 0x810 : bg_sys_top */ + union { + struct + { + uint32_t pmip_resv : 8; /* [ 7: 0], r/w, 0x0 */ + uint32_t pu_bg_sys_aon : 1; /* [ 8], r/w, 0x1 */ + uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */ + uint32_t bg_sys_start_ctrl_aon : 1; /* [ 12], r/w, 0x1 */ + uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } bg_sys_top; + + /* 0x814 : dcdc18_top_0 */ + union { + struct + { + uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ + uint32_t dcdc18_vout_sel_aon : 5; /* [ 5: 1], r/w, 0x1b */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t dcdc18_vpfm_aon : 4; /* [11: 8], r/w, 0x7 */ + uint32_t dcdc18_osc_2m_mode_aon : 1; /* [ 12], r/w, 0x0 */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t dcdc18_osc_freq_trim_aon : 4; /* [19:16], r/w, 0x8 */ + uint32_t dcdc18_slope_curr_sel_aon : 5; /* [24:20], r/w, 0x5 */ + uint32_t dcdc18_stop_osc_aon : 1; /* [ 25], r/w, 0x1 */ + uint32_t dcdc18_slow_osc_aon : 1; /* [ 26], r/w, 0x0 */ + uint32_t dcdc18_osc_inhibit_t2_aon : 1; /* [ 27], r/w, 0x1 */ + uint32_t dcdc18_sstart_time_aon : 2; /* [29:28], r/w, 0x0 */ + uint32_t reserved_30 : 1; /* [ 30], rsvd, 0x0 */ + uint32_t dcdc18_rdy_aon : 1; /* [ 31], r, 0x1 */ + } BF; + uint32_t WORD; + } dcdc18_top_0; + + /* 0x818 : dcdc18_top_1 */ + union { + struct + { + uint32_t dcdc18_force_cs_zvs_aon : 1; /* [ 0], r/w, 0x0 */ + uint32_t dcdc18_cs_delay_aon : 3; /* [ 3: 1], r/w, 0x4 */ + uint32_t dcdc18_zvs_td_opt_aon : 3; /* [ 6: 4], r/w, 0x4 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t dcdc18_nonoverlap_td_aon : 5; /* [12: 8], r/w, 0x0 */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t dcdc18_rc_sel_aon : 4; /* [19:16], r/w, 0x8 */ + uint32_t dcdc18_chf_sel_aon : 4; /* [23:20], r/w, 0x1 */ + uint32_t dcdc18_cfb_sel_aon : 4; /* [27:24], r/w, 0x8 */ + uint32_t dcdc18_en_antiring_aon : 1; /* [ 28], r/w, 0x1 */ + uint32_t dcdc18_pulldown_aon : 1; /* [ 29], r/w, 0x0 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } dcdc18_top_1; + + /* 0x81C : ldo11soc_and_dctest */ + union { + struct + { + uint32_t pu_ldo11soc_aon : 1; /* [ 0], r/w, 0x1 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t ldo11soc_sstart_sel_aon : 1; /* [ 4], r/w, 0x1 */ + uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ + uint32_t ldo11soc_sstart_delay_aon : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t ldo11soc_pulldown_aon : 1; /* [ 10], r/w, 0x0 */ + uint32_t ldo11soc_pulldown_sel_aon : 1; /* [ 11], r/w, 0x1 */ + uint32_t ldo11soc_vth_sel_aon : 2; /* [13:12], r/w, 0x1 */ + uint32_t reserved_14_23 : 10; /* [23:14], rsvd, 0x0 */ + uint32_t ldo11soc_cc_aon : 2; /* [25:24], r/w, 0x0 */ + uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */ + uint32_t ldo11soc_rdy_aon : 1; /* [ 28], r, 0x1 */ + uint32_t ldo11soc_power_good_aon : 1; /* [ 29], r, 0x1 */ + uint32_t pu_vddcore_misc_aon : 1; /* [ 30], r/w, 0x1 */ + uint32_t pmip_dc_tp_out_en_aon : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ldo11soc_and_dctest; + + /* 0x820 : psw_irrcv */ + union { + struct + { + uint32_t pu_ir_psw_aon : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } psw_irrcv; + + /* 0x824 reserved */ + uint8_t RESERVED0x824[92]; + + /* 0x880 : rf_top_aon */ + union { + struct + { + uint32_t pu_mbg_aon : 1; /* [ 0], r/w, 0x1 */ + uint32_t pu_ldo15rf_aon : 1; /* [ 1], r/w, 0x1 */ + uint32_t pu_sfreg_aon : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t pu_xtal_buf_aon : 1; /* [ 4], r/w, 0x1 */ + uint32_t pu_xtal_aon : 1; /* [ 5], r/w, 0x1 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t ldo15rf_sstart_sel_aon : 1; /* [ 8], r/w, 0x1 */ + uint32_t ldo15rf_sstart_delay_aon : 2; /* [10: 9], r/w, 0x0 */ + uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ + uint32_t ldo15rf_pulldown_aon : 1; /* [ 12], r/w, 0x0 */ + uint32_t ldo15rf_pulldown_sel_aon : 1; /* [ 13], r/w, 0x0 */ + uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ + uint32_t ldo15rf_vout_sel_aon : 3; /* [18:16], r/w, 0x2 */ + uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */ + uint32_t ldo15rf_cc_aon : 2; /* [25:24], r/w, 0x0 */ + uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */ + uint32_t ldo15rf_bypass_aon : 1; /* [ 28], r/w, 0x0 */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } rf_top_aon; + + /* 0x884 : xtal_cfg */ + union { + struct + { + uint32_t xtal_bk_aon : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t xtal_capcode_extra_aon : 1; /* [ 2], r/w, 0x0 */ + uint32_t xtal_ext_sel_aon : 1; /* [ 3], r/w, 0x0 */ + uint32_t xtal_buf_en_aon : 4; /* [ 7: 4], r/w, 0xf */ + uint32_t xtal_buf_hp_aon : 4; /* [11: 8], r/w, 0x0 */ + uint32_t xtal_fast_startup_aon : 1; /* [ 12], r/w, 0x1 */ + uint32_t xtal_sleep_aon : 1; /* [ 13], r/w, 0x1 */ + uint32_t xtal_amp_ctrl_aon : 2; /* [15:14], r/w, 0x3 */ + uint32_t xtal_capcode_out_aon : 6; /* [21:16], r/w, 0x10 */ + uint32_t xtal_capcode_in_aon : 6; /* [27:22], r/w, 0x10 */ + uint32_t xtal_gm_boost_aon : 2; /* [29:28], r/w, 0x3 */ + uint32_t xtal_rdy_sel_aon : 2; /* [31:30], r/w, 0x2 */ + } BF; + uint32_t WORD; + } xtal_cfg; + + /* 0x888 : tsen */ + union { + struct + { + uint32_t tsen_refcode_corner : 12; /* [11: 0], r/w, 0x8ff */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t tsen_refcode_rfcal : 12; /* [27:16], r/w, 0x8ff */ + uint32_t xtal_rdy : 1; /* [ 28], r, 0x1 */ + uint32_t xtal_inn_cfg_en_aon : 1; /* [ 29], r/w, 0x1 */ + uint32_t xtal_rdy_int_sel_aon : 2; /* [31:30], r/w, 0x1 */ + } BF; + uint32_t WORD; + } tsen; + + /* 0x88c reserved */ + uint8_t RESERVED0x88c[116]; + + /* 0x900 : acomp0_ctrl */ + union { + struct + { + uint32_t acomp0_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t acomp0_hyst_seln : 3; /* [ 6: 4], r/w, 0x0 */ + uint32_t acomp0_hyst_selp : 3; /* [ 9: 7], r/w, 0x0 */ + uint32_t acomp0_bias_prog : 2; /* [11:10], r/w, 0x0 */ + uint32_t acomp0_level_sel : 6; /* [17:12], r/w, 0x0 */ + uint32_t acomp0_neg_sel : 4; /* [21:18], r/w, 0x0 */ + uint32_t acomp0_pos_sel : 4; /* [25:22], r/w, 0x0 */ + uint32_t acomp0_muxen : 1; /* [ 26], r/w, 0x0 */ + uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } acomp0_ctrl; + + /* 0x904 : acomp1_ctrl */ + union { + struct + { + uint32_t acomp1_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t acomp1_hyst_seln : 3; /* [ 6: 4], r/w, 0x0 */ + uint32_t acomp1_hyst_selp : 3; /* [ 9: 7], r/w, 0x0 */ + uint32_t acomp1_bias_prog : 2; /* [11:10], r/w, 0x0 */ + uint32_t acomp1_level_sel : 6; /* [17:12], r/w, 0x0 */ + uint32_t acomp1_neg_sel : 4; /* [21:18], r/w, 0x0 */ + uint32_t acomp1_pos_sel : 4; /* [25:22], r/w, 0x0 */ + uint32_t acomp1_muxen : 1; /* [ 26], r/w, 0x0 */ + uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } acomp1_ctrl; + + /* 0x908 : acomp_ctrl */ + union { + struct + { + uint32_t acomp1_rstn_ana : 1; /* [ 0], r/w, 0x1 */ + uint32_t acomp0_rstn_ana : 1; /* [ 1], r/w, 0x1 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t acomp1_test_en : 1; /* [ 8], r/w, 0x0 */ + uint32_t acomp0_test_en : 1; /* [ 9], r/w, 0x0 */ + uint32_t acomp1_test_sel : 2; /* [11:10], r/w, 0x0 */ + uint32_t acomp0_test_sel : 2; /* [13:12], r/w, 0x0 */ + uint32_t reserved_14_16 : 3; /* [16:14], rsvd, 0x0 */ + uint32_t acomp1_out_raw : 1; /* [ 17], r, 0x0 */ + uint32_t reserved_18 : 1; /* [ 18], rsvd, 0x0 */ + uint32_t acomp0_out_raw : 1; /* [ 19], r, 0x0 */ + uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */ + uint32_t acomp_reserved : 8; /* [31:24], r/w, 0x0 */ + } BF; + uint32_t WORD; + } acomp_ctrl; + + /* 0x90C : gpadc_reg_cmd */ + union { + struct + { + uint32_t gpadc_global_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t gpadc_conv_start : 1; /* [ 1], r/w, 0x0 */ + uint32_t gpadc_soft_rst : 1; /* [ 2], r/w, 0x0 */ + uint32_t gpadc_neg_sel : 5; /* [ 7: 3], r/w, 0xf */ + uint32_t gpadc_pos_sel : 5; /* [12: 8], r/w, 0xf */ + uint32_t gpadc_neg_gnd : 1; /* [ 13], r/w, 0x0 */ + uint32_t gpadc_micbias_en : 1; /* [ 14], r/w, 0x0 */ + uint32_t gpadc_micpga_en : 1; /* [ 15], r/w, 0x0 */ + uint32_t gpadc_byp_micboost : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */ + uint32_t gpadc_dwa_en : 1; /* [ 18], r/w, 0x0 */ + uint32_t gpadc_mic2_diff : 1; /* [ 19], r/w, 0x0 */ + uint32_t gpadc_mic1_diff : 1; /* [ 20], r/w, 0x0 */ + uint32_t gpadc_mic_pga2_gain : 2; /* [22:21], r/w, 0x0 */ + uint32_t gpadc_micboost_32db_en : 1; /* [ 23], r/w, 0x0 */ + uint32_t reserved_24_26 : 3; /* [26:24], rsvd, 0x0 */ + uint32_t gpadc_chip_sen_pu : 1; /* [ 27], r/w, 0x0 */ + uint32_t gpadc_sen_sel : 2; /* [29:28], r/w, 0x0 */ + uint32_t gpadc_sen_test_en : 1; /* [ 30], r/w, 0x0 */ + uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_cmd; + + /* 0x910 : gpadc_reg_config1 */ + union { + struct + { + uint32_t gpadc_cal_os_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t gpadc_cont_conv_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t gpadc_res_sel : 3; /* [ 4: 2], r/w, 0x0 */ + uint32_t reserved_5_16 : 12; /* [16: 5], rsvd, 0x0 */ + uint32_t gpadc_clk_ana_inv : 1; /* [ 17], r/w, 0x0 */ + uint32_t gpadc_clk_div_ratio : 3; /* [20:18], r/w, 0x3 */ + uint32_t gpadc_scan_length : 4; /* [24:21], r/w, 0x0 */ + uint32_t gpadc_scan_en : 1; /* [ 25], r/w, 0x0 */ + uint32_t gpadc_dither_en : 1; /* [ 26], r/w, 0x0 */ + uint32_t gpadc_v11_sel : 2; /* [28:27], r/w, 0x0 */ + uint32_t gpadc_v18_sel : 2; /* [30:29], r/w, 0x0 */ + uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_config1; + + /* 0x914 : gpadc_reg_config2 */ + union { + struct + { + uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ + uint32_t gpadc_diff_mode : 1; /* [ 2], r/w, 0x0 */ + uint32_t gpadc_vref_sel : 1; /* [ 3], r/w, 0x0 */ + uint32_t gpadc_vbat_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t gpadc_tsext_sel : 1; /* [ 5], r/w, 0x0 */ + uint32_t gpadc_ts_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t gpadc_pga_vcm : 2; /* [ 8: 7], r/w, 0x2 */ + uint32_t gpadc_pga_os_cal : 4; /* [12: 9], r/w, 0x8 */ + uint32_t gpadc_pga_en : 1; /* [ 13], r/w, 0x0 */ + uint32_t gpadc_pga_vcmi_en : 1; /* [ 14], r/w, 0x0 */ + uint32_t gpadc_chop_mode : 2; /* [16:15], r/w, 0x3 */ + uint32_t gpadc_bias_sel : 1; /* [ 17], r/w, 0x0 */ + uint32_t gpadc_test_en : 1; /* [ 18], r/w, 0x0 */ + uint32_t gpadc_test_sel : 3; /* [21:19], r/w, 0x0 */ + uint32_t gpadc_pga2_gain : 3; /* [24:22], r/w, 0x0 */ + uint32_t gpadc_pga1_gain : 3; /* [27:25], r/w, 0x0 */ + uint32_t gpadc_dly_sel : 3; /* [30:28], r/w, 0x0 */ + uint32_t gpadc_tsvbe_low : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_config2; + + /* 0x918 : adc converation sequence 1 */ + union { + struct + { + uint32_t gpadc_scan_pos_0 : 5; /* [ 4: 0], r/w, 0xf */ + uint32_t gpadc_scan_pos_1 : 5; /* [ 9: 5], r/w, 0xf */ + uint32_t gpadc_scan_pos_2 : 5; /* [14:10], r/w, 0xf */ + uint32_t gpadc_scan_pos_3 : 5; /* [19:15], r/w, 0xf */ + uint32_t gpadc_scan_pos_4 : 5; /* [24:20], r/w, 0xf */ + uint32_t gpadc_scan_pos_5 : 5; /* [29:25], r/w, 0xf */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_scn_pos1; + + /* 0x91C : adc converation sequence 2 */ + union { + struct + { + uint32_t gpadc_scan_pos_6 : 5; /* [ 4: 0], r/w, 0xf */ + uint32_t gpadc_scan_pos_7 : 5; /* [ 9: 5], r/w, 0xf */ + uint32_t gpadc_scan_pos_8 : 5; /* [14:10], r/w, 0xf */ + uint32_t gpadc_scan_pos_9 : 5; /* [19:15], r/w, 0xf */ + uint32_t gpadc_scan_pos_10 : 5; /* [24:20], r/w, 0xf */ + uint32_t gpadc_scan_pos_11 : 5; /* [29:25], r/w, 0xf */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_scn_pos2; + + /* 0x920 : adc converation sequence 3 */ + union { + struct + { + uint32_t gpadc_scan_neg_0 : 5; /* [ 4: 0], r/w, 0xf */ + uint32_t gpadc_scan_neg_1 : 5; /* [ 9: 5], r/w, 0xf */ + uint32_t gpadc_scan_neg_2 : 5; /* [14:10], r/w, 0xf */ + uint32_t gpadc_scan_neg_3 : 5; /* [19:15], r/w, 0xf */ + uint32_t gpadc_scan_neg_4 : 5; /* [24:20], r/w, 0xf */ + uint32_t gpadc_scan_neg_5 : 5; /* [29:25], r/w, 0xf */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_scn_neg1; + + /* 0x924 : adc converation sequence 4 */ + union { + struct + { + uint32_t gpadc_scan_neg_6 : 5; /* [ 4: 0], r/w, 0xf */ + uint32_t gpadc_scan_neg_7 : 5; /* [ 9: 5], r/w, 0xf */ + uint32_t gpadc_scan_neg_8 : 5; /* [14:10], r/w, 0xf */ + uint32_t gpadc_scan_neg_9 : 5; /* [19:15], r/w, 0xf */ + uint32_t gpadc_scan_neg_10 : 5; /* [24:20], r/w, 0xf */ + uint32_t gpadc_scan_neg_11 : 5; /* [29:25], r/w, 0xf */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_scn_neg2; + + /* 0x928 : gpadc_reg_status */ + union { + struct + { + uint32_t gpadc_data_rdy : 1; /* [ 0], r, 0x0 */ + uint32_t reserved_1_15 : 15; /* [15: 1], rsvd, 0x0 */ + uint32_t gpadc_reserved : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_status; + + /* 0x92C : gpadc_reg_isr */ + union { + struct + { + uint32_t gpadc_neg_satur : 1; /* [ 0], r, 0x0 */ + uint32_t gpadc_pos_satur : 1; /* [ 1], r, 0x0 */ + uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ + uint32_t gpadc_neg_satur_clr : 1; /* [ 4], r/w, 0x0 */ + uint32_t gpadc_pos_satur_clr : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t gpadc_neg_satur_mask : 1; /* [ 8], r/w, 0x0 */ + uint32_t gpadc_pos_satur_mask : 1; /* [ 9], r/w, 0x0 */ + uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_isr; + + /* 0x930 : gpadc_reg_result */ + union { + struct + { + uint32_t gpadc_data_out : 26; /* [25: 0], r, 0x1ef0000 */ + uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_result; + + /* 0x934 : gpadc_reg_raw_result */ + union { + struct + { + uint32_t gpadc_raw_data : 12; /* [11: 0], r, 0x0 */ + uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_raw_result; + + /* 0x938 : gpadc_reg_define */ + union { + struct + { + uint32_t gpadc_os_cal_data : 16; /* [15: 0], r/w, 0x0 */ + uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpadc_reg_define; + + /* 0x93C : hbncore_resv0 */ + union { + struct + { + uint32_t hbncore_resv0_data : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } hbncore_resv0; + + /* 0x940 : hbncore_resv1 */ + union { + struct + { + uint32_t hbncore_resv1_data : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } hbncore_resv1; +}; + +typedef volatile struct aon_reg aon_reg_t; + +#endif /* __AON_REG_H__ */ diff --git a/drivers/soc/bl602/bl602_std/include/hardware/bl602.h b/drivers/soc/bl602/bl602_std/include/hardware/bl602.h new file mode 100644 index 00000000..db35c118 --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/hardware/bl602.h @@ -0,0 +1,250 @@ +#ifndef __BL602_H__ +#define __BL602_H__ + +/** @addtogroup Configuration_section_for_RISCV + * @{ + */ + +/** + * @brief Configuration of the Processor and Core Peripherals + */ +#define SystemCoreClockSet(val) BL_WR_WORD(0x4000F108, val) +#define SystemCoreClockGet(val) BL_RD_WORD(0x4000F108) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +#ifdef ARCH_ARM +#define IRQ_NUM_BASE 0 +#endif + +#ifdef ARCH_RISCV +#define IRQ_NUM_BASE 16 +#endif +/** + * @brief BL602 Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum { +#ifdef ARCH_ARM + /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +#endif +#ifdef ARCH_RISCV + MSOFT_IRQn = 3, /*!< 3 RISCV machine software Interrupt */ + MTIME_IRQn = 7, /*!< 7 RISCV machine time Interrupt */ + MEXT_IRQn = 11, /*!< 11 RISCV external Interrupt */ + CLIC_SOFT_PEND_IRQn = 12, /*!< 12 RISCV CLIC software pending Interrupt */ +#endif + /****** BL602 specific Interrupt Numbers **********************************************************************/ + BMX_ERR_IRQn = IRQ_NUM_BASE + 0, /*!< BMX Error Interrupt */ + BMX_TO_IRQn = IRQ_NUM_BASE + 1, /*!< BMX Timeout Interrupt */ + L1C_BMX_ERR_IRQn = IRQ_NUM_BASE + 2, /*!< L1C BMX Error Interrupt */ + L1C_BMX_TO_IRQn = IRQ_NUM_BASE + 3, /*!< L1C BMX Timeout Interrupt */ + SEC_BMX_ERR_IRQn = IRQ_NUM_BASE + 4, /*!< SEC BMX Error Interrupt */ + RF_TOP_INT0_IRQn = IRQ_NUM_BASE + 5, /*!< RF_TOP_INT0 Interrupt */ + RF_TOP_INT1_IRQn = IRQ_NUM_BASE + 6, /*!< RF_TOP_INT1 Interrupt */ + SDIO_IRQn = IRQ_NUM_BASE + 7, /*!< SDIO Interrupt */ + DMA_BMX_ERR_IRQn = IRQ_NUM_BASE + 8, /*!< DMA BMX Error Interrupt */ + SEC_GMAC_IRQn = IRQ_NUM_BASE + 9, /*!< SEC_ENG_GMAC_INT Interrupt */ + SEC_CDET_IRQn = IRQ_NUM_BASE + 10, /*!< SEC_ENG_CDET_INT Interrupt */ + SEC_PKA_IRQn = IRQ_NUM_BASE + 11, /*!< SEC_ENG_PKA_INT Interrupt */ + SEC_TRNG_IRQn = IRQ_NUM_BASE + 12, /*!< SEC_ENG_TRNG_INT Interrupt */ + SEC_AES_IRQn = IRQ_NUM_BASE + 13, /*!< SEC_ENG_AES_INT Interrupt */ + SEC_SHA_IRQn = IRQ_NUM_BASE + 14, /*!< SEC_ENG_SHA_INT Interrupt */ + DMA_ALL_IRQn = IRQ_NUM_BASE + 15, /*!< DMA ALL Interrupt */ + RESERVED0 = IRQ_NUM_BASE + 16, /*!< RESERVED Interrupt */ + RESERVED1 = IRQ_NUM_BASE + 17, /*!< RESERVED Interrupt */ + RESERVED2 = IRQ_NUM_BASE + 18, /*!< RESERVED Interrupt */ + IRTX_IRQn = IRQ_NUM_BASE + 19, /*!< IR TX Interrupt */ + IRRX_IRQn = IRQ_NUM_BASE + 20, /*!< IR RX Interrupt */ + RESERVED3 = IRQ_NUM_BASE + 21, /*!< RESERVED Interrupt */ + RESERVED4 = IRQ_NUM_BASE + 22, /*!< RESERVED Interrupt */ + SF_CTRL_IRQn = IRQ_NUM_BASE + 23, /*!< SF_CTRL Interrupt */ + RESERVED5 = IRQ_NUM_BASE + 24, /*!< RESERVED Interrupt */ + GPADC_DMA_IRQn = IRQ_NUM_BASE + 25, /*!< GPADC_DMA Interrupt */ + EFUSE_IRQn = IRQ_NUM_BASE + 26, /*!< Efuse Interrupt */ + SPI_IRQn = IRQ_NUM_BASE + 27, /*!< SPI Interrupt */ + RESERVED6 = IRQ_NUM_BASE + 28, /*!< RESERVED Interrupt */ + UART0_IRQn = IRQ_NUM_BASE + 29, /*!< UART Interrupt */ + UART1_IRQn = IRQ_NUM_BASE + 30, /*!< UART1 Interrupt */ + RESERVED7 = IRQ_NUM_BASE + 31, /*!< RESERVED Interrupt */ + I2C_IRQn = IRQ_NUM_BASE + 32, /*!< I2C Interrupt */ + RESERVED8 = IRQ_NUM_BASE + 33, /*!< RESERVED Interrupt */ + PWM_IRQn = IRQ_NUM_BASE + 34, /*!< PWM Interrupt */ + RESERVED9 = IRQ_NUM_BASE + 35, /*!< RESERVED Interrupt */ + TIMER_CH0_IRQn = IRQ_NUM_BASE + 36, /*!< Timer Channel 0 Interrupt */ + TIMER_CH1_IRQn = IRQ_NUM_BASE + 37, /*!< Timer Channel 1 Interrupt */ + TIMER_WDT_IRQn = IRQ_NUM_BASE + 38, /*!< Timer Watch Dog Interrupt */ + RESERVED10 = IRQ_NUM_BASE + 39, /*!< RESERVED Interrupt */ + RESERVED11 = IRQ_NUM_BASE + 40, /*!< RESERVED Interrupt */ + RESERVED12 = IRQ_NUM_BASE + 41, /*!< RESERVED Interrupt */ + RESERVED13 = IRQ_NUM_BASE + 42, /*!< RESERVED Interrupt */ + RESERVED14 = IRQ_NUM_BASE + 43, /*!< RESERVED Interrupt */ + GPIO_INT0_IRQn = IRQ_NUM_BASE + 44, /*!< RESERVED Interrupt */ + RESERVED16 = IRQ_NUM_BASE + 45, /*!< RESERVED Interrupt */ + RESERVED17 = IRQ_NUM_BASE + 46, /*!< RESERVED Interrupt */ + RESERVED18 = IRQ_NUM_BASE + 47, /*!< RESERVED Interrupt */ + RESERVED19 = IRQ_NUM_BASE + 48, /*!< RESERVED Interrupt */ + RESERVED20 = IRQ_NUM_BASE + 49, /*!< RESERVED Interrupt */ + PDS_WAKEUP_IRQn = IRQ_NUM_BASE + 50, /*!< PDS Wakeup Interrupt */ + HBN_OUT0_IRQn = IRQ_NUM_BASE + 51, /*!< Hibernate out 0 Interrupt */ + HBN_OUT1_IRQn = IRQ_NUM_BASE + 52, /*!< Hibernate out 1 Interrupt */ + BOR_IRQn = IRQ_NUM_BASE + 53, /*!< BOR Interrupt */ + WIFI_IRQn = IRQ_NUM_BASE + 54, /*!< WIFI To CPU Interrupt */ + BZ_PHY_IRQn = IRQ_NUM_BASE + 55, /*!< RESERVED Interrupt */ + BLE_IRQn = IRQ_NUM_BASE + 56, /*!< RESERVED Interrupt */ + MAC_TXRX_TIMER_IRQn = IRQ_NUM_BASE + 57, /*!< mac_int_tx_rx_timer Interrupt */ + MAC_TXRX_MISC_IRQn = IRQ_NUM_BASE + 58, /*!< mac_int_tx_rx_misc Interrupt */ + MAC_RX_TRG_IRQn = IRQ_NUM_BASE + 59, /*!< mac_int_rx_trigger Interrupt */ + MAC_TX_TRG_IRQn = IRQ_NUM_BASE + 60, /*!< mac_int_tx_trigger Interrupt */ + MAC_GEN_IRQn = IRQ_NUM_BASE + 61, /*!< mac_int_gen Interrupt */ + MAC_PORT_TRG_IRQn = IRQ_NUM_BASE + 62, /*!< mac_int_port_trigger Interrupt */ + WIFI_IPC_PUBLIC_IRQn = IRQ_NUM_BASE + 63, /*!< wifi IPC public Interrupt */ + IRQn_LAST, +} IRQn_Type; + +/** + * @brief BL602 Memory Map Definitions + */ +#define BL602_FLASH_XIP_BASE 0x23000000 +#define BL602_FLASH_XIP_END (0x23000000 + 16 * 1024 * 1024) +#define BL602_FLASH_XIP_REMAP0_BASE 0x33000000 +#define BL602_FLASH_XIP_REMAP0_END (0x33000000 + 16 * 1024 * 1024) +#define BL602_FLASH_XIP_REMAP1_BASE 0x43000000 +#define BL602_FLASH_XIP_REMAP1_END (0x43000000 + 16 * 1024 * 1024) +#define BL602_FLASH_XIP_REMAP2_BASE 0x53000000 +#define BL602_FLASH_XIP_REMAP2_END (0x53000000 + 16 * 1024 * 1024) + +#define BL602_WRAM_BASE 0x42020000 +#define BL602_WRAM_END (0x42020000 + 176 * 1024) +#define BL602_WRAM_REMAP0_BASE 0x22020000 +#define BL602_WRAM_REMAP0_END (0x22020000 + 176 * 1024) +#define BL602_WRAM_REMAP1_BASE 0x32020000 +#define BL602_WRAM_REMAP1_END (0x32020000 + 176 * 1024) +#define BL602_WRAM_REMAP2_BASE 0x52020000 +#define BL602_WRAM_REMAP2_END (0x52020000 + 176 * 1024) + +#define BL602_TCM_BASE 0x22008000 +#define BL602_TCM_END (0x22008000 + (96 + 176) * 1024) +#define BL602_TCM_REMAP0_BASE 0x32008000 +#define BL602_TCM_REMAP0_END (0x32008000 + (96 + 176) * 1024) +#define BL602_TCM_REMAP1_BASE 0x42008000 +#define BL602_TCM_REMAP1_END (0x42008000 + (96 + 176) * 1024) +#define BL602_TCM_REMAP2_BASE 0x52008000 +#define BL602_TCM_REMAP2_END (0x52008000 + (96 + 176) * 1024) +/*@} end of group Memory_Map_Section */ + +/* BL602 peripherals base address */ +#define GLB_BASE ((uint32_t)0x40000000) +#define RF_BASE ((uint32_t)0x40001000) +#define GPIP_BASE ((uint32_t)0x40002000) /*!< AUX module base address */ +#define SEC_DBG_BASE ((uint32_t)0x40003000) /*!< Security Debug module base address */ +#define SEC_ENG_BASE ((uint32_t)0x40004000) /*!< Security Engine module base address */ +#define TZC_SEC_BASE ((uint32_t)0x40005000) /*!< Trustzone control security base address */ +#define TZC_NSEC_BASE ((uint32_t)0x40006000) /*!< Trustzone control none-security base address */ +#define EF_DATA_BASE ((uint32_t)0x40007000) +#define EF_CTRL_BASE ((uint32_t)0x40007000) +#define CCI_BASE ((uint32_t)0x40008000) +#define L1C_BASE ((uint32_t)0x40009000) /*!< L1 cache config base address */ +#define UART0_BASE ((uint32_t)0x4000A000) +#define UART1_BASE ((uint32_t)0x4000A100) +#define SPI_BASE ((uint32_t)0x4000A200) +#define I2C_BASE ((uint32_t)0x4000A300) +#define PWM_BASE ((uint32_t)0x4000A400) +#define TIMER_BASE ((uint32_t)0x4000A500) +#define IR_BASE ((uint32_t)0x4000A600) +#define SF_CTRL_BASE ((uint32_t)0x4000B000) +#define SF_CTRL_BUF_BASE ((uint32_t)0x4000B700) +#define DMA_BASE ((uint32_t)0x4000C000) +#define SDU_BASE ((uint32_t)0x4000D000) +#define PDS_BASE ((uint32_t)0x4000E000) /*!< Power down sleep module base address */ +#define HBN_BASE ((uint32_t)0x4000F000) /*!< Hibernate module base address */ +#define AON_BASE ((uint32_t)0x4000F000) /*!< Always on module base address */ +#define HBN_RAM_BASE ((uint32_t)0x40010000) + +typedef enum { + BL_AHB_SLAVE1_GLB = 0x00, + BL_AHB_SLAVE1_RF = 0x01, + BL_AHB_SLAVE1_GPIP_PHY_AGC = 0x02, + BL_AHB_SLAVE1_SEC_DBG = 0x03, + BL_AHB_SLAVE1_SEC = 0x04, + BL_AHB_SLAVE1_TZ1 = 0x05, + BL_AHB_SLAVE1_TZ2 = 0x06, + BL_AHB_SLAVE1_EFUSE = 0x07, + BL_AHB_SLAVE1_CCI = 0x08, + BL_AHB_SLAVE1_L1C = 0x09, + BL_AHB_SLAVE1_RSVD0A = 0x0A, + BL_AHB_SLAVE1_SFC = 0x0B, + BL_AHB_SLAVE1_DMA = 0x0C, + BL_AHB_SLAVE1_SDU = 0x0D, + BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM = 0x0E, + BL_AHB_SLAVE1_RSVD0F = 0x0F, + BL_AHB_SLAVE1_UART0 = 0x10, + BL_AHB_SLAVE1_UART1 = 0x11, + BL_AHB_SLAVE1_SPI = 0x12, + BL_AHB_SLAVE1_I2C = 0x13, + BL_AHB_SLAVE1_PWM = 0x14, + BL_AHB_SLAVE1_TMR = 0x15, + BL_AHB_SLAVE1_IRR = 0x16, + BL_AHB_SLAVE1_CKS = 0x17, + BL_AHB_SLAVE1_MAX = 0x18, +} BL_AHB_Slave1_Type; + +typedef enum { + BL_AHB_SEC_ENG_AES0 = 0, + BL_AHB_SEC_ENG_AES1, + BL_AHB_SEC_ENG_SHA0, + BL_AHB_SEC_ENG_SHA1, +} BL_AHB_Sec_Eng_Type; + +typedef enum { + BL_AHB_DMA0_CH0 = 0, + BL_AHB_DMA0_CH1, + BL_AHB_DMA0_CH2, + BL_AHB_DMA0_CH3, + BL_AHB_DMA0_CH4, +} BL_AHB_DMA0_CHNL_Type; + +typedef enum { + BL_CORE_MASTER_IBUS_CPU = 0, + BL_CORE_MASTER_DBUS_CPU, + BL_CORE_MASTER_BUS_S2F, + BL_CORE_MASTER_MAX, +} BL_Core_Master_Type; + +typedef enum { + BL_CORE_SLAVE0_DTCM_CPU = 0, + BL_CORE_SLAVE0_MAX, +} BL_Core_Slave0_Type; + +typedef enum { + BL_CORE_SLAVE1_XIP_CPU = 0, + BL_CORE_SLAVE1_ITCM_CPU, + BL_CORE_SLAVE1_ROM, + BL_CORE_SLAVE1_MAX, +} BL_Core_Slave1_Type; + +typedef enum { + BL_CORE_SLAVE2_F2S = 0, + BL_CORE_SLAVE2_MAX, +} BL_Core_Slave2_Type; + +/** + * @} + */ +#include + +#endif diff --git a/drivers/soc/bl602/bl602_std/include/hardware/ef_ctrl_reg.h b/drivers/soc/bl602/bl602_std/include/hardware/ef_ctrl_reg.h new file mode 100644 index 00000000..772c9030 --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/hardware/ef_ctrl_reg.h @@ -0,0 +1,812 @@ +/** + ****************************************************************************** + * @file ef_ctrl_reg.h + * @version V1.2 + * @date 2019-11-22 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __EF_CTRL_REG_H__ +#define __EF_CTRL_REG_H__ + +#include "bl602.h" + +/* 0x800 : ef_if_ctrl_0 */ +#define EF_CTRL_EF_IF_CTRL_0_OFFSET (0x800) +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS (0U) +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN (1U) +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_MSK (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS) +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_UMSK (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS)) +#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE EF_CTRL_EF_IF_0_AUTOLOAD_DONE +#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS (1U) +#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN (1U) +#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_MSK (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS) +#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_UMSK (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS)) +#define EF_CTRL_EF_IF_0_BUSY EF_CTRL_EF_IF_0_BUSY +#define EF_CTRL_EF_IF_0_BUSY_POS (2U) +#define EF_CTRL_EF_IF_0_BUSY_LEN (1U) +#define EF_CTRL_EF_IF_0_BUSY_MSK (((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS) +#define EF_CTRL_EF_IF_0_BUSY_UMSK (~(((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS)) +#define EF_CTRL_EF_IF_0_RW EF_CTRL_EF_IF_0_RW +#define EF_CTRL_EF_IF_0_RW_POS (3U) +#define EF_CTRL_EF_IF_0_RW_LEN (1U) +#define EF_CTRL_EF_IF_0_RW_MSK (((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS) +#define EF_CTRL_EF_IF_0_RW_UMSK (~(((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS)) +#define EF_CTRL_EF_IF_0_TRIG EF_CTRL_EF_IF_0_TRIG +#define EF_CTRL_EF_IF_0_TRIG_POS (4U) +#define EF_CTRL_EF_IF_0_TRIG_LEN (1U) +#define EF_CTRL_EF_IF_0_TRIG_MSK (((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS) +#define EF_CTRL_EF_IF_0_TRIG_UMSK (~(((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS)) +#define EF_CTRL_EF_IF_0_MANUAL_EN EF_CTRL_EF_IF_0_MANUAL_EN +#define EF_CTRL_EF_IF_0_MANUAL_EN_POS (5U) +#define EF_CTRL_EF_IF_0_MANUAL_EN_LEN (1U) +#define EF_CTRL_EF_IF_0_MANUAL_EN_MSK (((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS) +#define EF_CTRL_EF_IF_0_MANUAL_EN_UMSK (~(((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS)) +#define EF_CTRL_EF_IF_0_CYC_MODIFY EF_CTRL_EF_IF_0_CYC_MODIFY +#define EF_CTRL_EF_IF_0_CYC_MODIFY_POS (6U) +#define EF_CTRL_EF_IF_0_CYC_MODIFY_LEN (1U) +#define EF_CTRL_EF_IF_0_CYC_MODIFY_MSK (((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) +#define EF_CTRL_EF_IF_0_CYC_MODIFY_UMSK (~(((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)) +#define EF_CTRL_EF_CLK_SAHB_DATA_SEL EF_CTRL_EF_CLK_SAHB_DATA_SEL +#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS (7U) +#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN (1U) +#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_MSK (((1U << EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) +#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_UMSK (~(((1U << EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS)) +#define EF_CTRL_EF_IF_PROT_CODE_CTRL EF_CTRL_EF_IF_PROT_CODE_CTRL +#define EF_CTRL_EF_IF_PROT_CODE_CTRL_POS (8U) +#define EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN (8U) +#define EF_CTRL_EF_IF_PROT_CODE_CTRL_MSK (((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS) +#define EF_CTRL_EF_IF_PROT_CODE_CTRL_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS)) +#define EF_CTRL_EF_IF_POR_DIG EF_CTRL_EF_IF_POR_DIG +#define EF_CTRL_EF_IF_POR_DIG_POS (16U) +#define EF_CTRL_EF_IF_POR_DIG_LEN (1U) +#define EF_CTRL_EF_IF_POR_DIG_MSK (((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS) +#define EF_CTRL_EF_IF_POR_DIG_UMSK (~(((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS)) +#define EF_CTRL_EF_CLK_SAHB_DATA_GATE EF_CTRL_EF_CLK_SAHB_DATA_GATE +#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS (17U) +#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN (1U) +#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_MSK (((1U << EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS) +#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_UMSK (~(((1U << EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS)) +#define EF_CTRL_EF_IF_AUTO_RD_EN EF_CTRL_EF_IF_AUTO_RD_EN +#define EF_CTRL_EF_IF_AUTO_RD_EN_POS (18U) +#define EF_CTRL_EF_IF_AUTO_RD_EN_LEN (1U) +#define EF_CTRL_EF_IF_AUTO_RD_EN_MSK (((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS) +#define EF_CTRL_EF_IF_AUTO_RD_EN_UMSK (~(((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS)) +#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK EF_CTRL_EF_IF_CYC_MODIFY_LOCK +#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS (19U) +#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN (1U) +#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_MSK (((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS) +#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS)) +#define EF_CTRL_EF_IF_0_INT EF_CTRL_EF_IF_0_INT +#define EF_CTRL_EF_IF_0_INT_POS (20U) +#define EF_CTRL_EF_IF_0_INT_LEN (1U) +#define EF_CTRL_EF_IF_0_INT_MSK (((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS) +#define EF_CTRL_EF_IF_0_INT_UMSK (~(((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS)) +#define EF_CTRL_EF_IF_0_INT_CLR EF_CTRL_EF_IF_0_INT_CLR +#define EF_CTRL_EF_IF_0_INT_CLR_POS (21U) +#define EF_CTRL_EF_IF_0_INT_CLR_LEN (1U) +#define EF_CTRL_EF_IF_0_INT_CLR_MSK (((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS) +#define EF_CTRL_EF_IF_0_INT_CLR_UMSK (~(((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS)) +#define EF_CTRL_EF_IF_0_INT_SET EF_CTRL_EF_IF_0_INT_SET +#define EF_CTRL_EF_IF_0_INT_SET_POS (22U) +#define EF_CTRL_EF_IF_0_INT_SET_LEN (1U) +#define EF_CTRL_EF_IF_0_INT_SET_MSK (((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS) +#define EF_CTRL_EF_IF_0_INT_SET_UMSK (~(((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS)) +#define EF_CTRL_EF_IF_PROT_CODE_CYC EF_CTRL_EF_IF_PROT_CODE_CYC +#define EF_CTRL_EF_IF_PROT_CODE_CYC_POS (24U) +#define EF_CTRL_EF_IF_PROT_CODE_CYC_LEN (8U) +#define EF_CTRL_EF_IF_PROT_CODE_CYC_MSK (((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS) +#define EF_CTRL_EF_IF_PROT_CODE_CYC_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS)) + +/* 0x804 : ef_if_cyc_0 */ +#define EF_CTRL_EF_IF_CYC_0_OFFSET (0x804) +#define EF_CTRL_EF_IF_CYC_RD_DMY EF_CTRL_EF_IF_CYC_RD_DMY +#define EF_CTRL_EF_IF_CYC_RD_DMY_POS (0U) +#define EF_CTRL_EF_IF_CYC_RD_DMY_LEN (6U) +#define EF_CTRL_EF_IF_CYC_RD_DMY_MSK (((1U << EF_CTRL_EF_IF_CYC_RD_DMY_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DMY_POS) +#define EF_CTRL_EF_IF_CYC_RD_DMY_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_RD_DMY_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DMY_POS)) +#define EF_CTRL_EF_IF_CYC_RD_DAT EF_CTRL_EF_IF_CYC_RD_DAT +#define EF_CTRL_EF_IF_CYC_RD_DAT_POS (6U) +#define EF_CTRL_EF_IF_CYC_RD_DAT_LEN (6U) +#define EF_CTRL_EF_IF_CYC_RD_DAT_MSK (((1U << EF_CTRL_EF_IF_CYC_RD_DAT_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DAT_POS) +#define EF_CTRL_EF_IF_CYC_RD_DAT_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_RD_DAT_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DAT_POS)) +#define EF_CTRL_EF_IF_CYC_RD_ADR EF_CTRL_EF_IF_CYC_RD_ADR +#define EF_CTRL_EF_IF_CYC_RD_ADR_POS (12U) +#define EF_CTRL_EF_IF_CYC_RD_ADR_LEN (6U) +#define EF_CTRL_EF_IF_CYC_RD_ADR_MSK (((1U << EF_CTRL_EF_IF_CYC_RD_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_ADR_POS) +#define EF_CTRL_EF_IF_CYC_RD_ADR_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_RD_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_ADR_POS)) +#define EF_CTRL_EF_IF_CYC_CS EF_CTRL_EF_IF_CYC_CS +#define EF_CTRL_EF_IF_CYC_CS_POS (18U) +#define EF_CTRL_EF_IF_CYC_CS_LEN (6U) +#define EF_CTRL_EF_IF_CYC_CS_MSK (((1U << EF_CTRL_EF_IF_CYC_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_CS_POS) +#define EF_CTRL_EF_IF_CYC_CS_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_CS_POS)) +#define EF_CTRL_EF_IF_CYC_PD_CS_S EF_CTRL_EF_IF_CYC_PD_CS_S +#define EF_CTRL_EF_IF_CYC_PD_CS_S_POS (24U) +#define EF_CTRL_EF_IF_CYC_PD_CS_S_LEN (8U) +#define EF_CTRL_EF_IF_CYC_PD_CS_S_MSK (((1U << EF_CTRL_EF_IF_CYC_PD_CS_S_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_S_POS) +#define EF_CTRL_EF_IF_CYC_PD_CS_S_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PD_CS_S_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_S_POS)) + +/* 0x808 : ef_if_cyc_1 */ +#define EF_CTRL_EF_IF_CYC_1_OFFSET (0x808) +#define EF_CTRL_EF_IF_CYC_PI EF_CTRL_EF_IF_CYC_PI +#define EF_CTRL_EF_IF_CYC_PI_POS (0U) +#define EF_CTRL_EF_IF_CYC_PI_LEN (6U) +#define EF_CTRL_EF_IF_CYC_PI_MSK (((1U << EF_CTRL_EF_IF_CYC_PI_LEN) - 1) << EF_CTRL_EF_IF_CYC_PI_POS) +#define EF_CTRL_EF_IF_CYC_PI_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PI_LEN) - 1) << EF_CTRL_EF_IF_CYC_PI_POS)) +#define EF_CTRL_EF_IF_CYC_PP EF_CTRL_EF_IF_CYC_PP +#define EF_CTRL_EF_IF_CYC_PP_POS (6U) +#define EF_CTRL_EF_IF_CYC_PP_LEN (8U) +#define EF_CTRL_EF_IF_CYC_PP_MSK (((1U << EF_CTRL_EF_IF_CYC_PP_LEN) - 1) << EF_CTRL_EF_IF_CYC_PP_POS) +#define EF_CTRL_EF_IF_CYC_PP_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PP_LEN) - 1) << EF_CTRL_EF_IF_CYC_PP_POS)) +#define EF_CTRL_EF_IF_CYC_WR_ADR EF_CTRL_EF_IF_CYC_WR_ADR +#define EF_CTRL_EF_IF_CYC_WR_ADR_POS (14U) +#define EF_CTRL_EF_IF_CYC_WR_ADR_LEN (6U) +#define EF_CTRL_EF_IF_CYC_WR_ADR_MSK (((1U << EF_CTRL_EF_IF_CYC_WR_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_WR_ADR_POS) +#define EF_CTRL_EF_IF_CYC_WR_ADR_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_WR_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_WR_ADR_POS)) +#define EF_CTRL_EF_IF_CYC_PS_CS EF_CTRL_EF_IF_CYC_PS_CS +#define EF_CTRL_EF_IF_CYC_PS_CS_POS (20U) +#define EF_CTRL_EF_IF_CYC_PS_CS_LEN (6U) +#define EF_CTRL_EF_IF_CYC_PS_CS_MSK (((1U << EF_CTRL_EF_IF_CYC_PS_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_PS_CS_POS) +#define EF_CTRL_EF_IF_CYC_PS_CS_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PS_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_PS_CS_POS)) +#define EF_CTRL_EF_IF_CYC_PD_CS_H EF_CTRL_EF_IF_CYC_PD_CS_H +#define EF_CTRL_EF_IF_CYC_PD_CS_H_POS (26U) +#define EF_CTRL_EF_IF_CYC_PD_CS_H_LEN (6U) +#define EF_CTRL_EF_IF_CYC_PD_CS_H_MSK (((1U << EF_CTRL_EF_IF_CYC_PD_CS_H_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_H_POS) +#define EF_CTRL_EF_IF_CYC_PD_CS_H_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PD_CS_H_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_H_POS)) + +/* 0x80C : ef_if_0_manual */ +#define EF_CTRL_EF_IF_0_MANUAL_OFFSET (0x80C) +#define EF_CTRL_EF_IF_A EF_CTRL_EF_IF_A +#define EF_CTRL_EF_IF_A_POS (0U) +#define EF_CTRL_EF_IF_A_LEN (10U) +#define EF_CTRL_EF_IF_A_MSK (((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS) +#define EF_CTRL_EF_IF_A_UMSK (~(((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS)) +#define EF_CTRL_EF_IF_PD EF_CTRL_EF_IF_PD +#define EF_CTRL_EF_IF_PD_POS (10U) +#define EF_CTRL_EF_IF_PD_LEN (1U) +#define EF_CTRL_EF_IF_PD_MSK (((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS) +#define EF_CTRL_EF_IF_PD_UMSK (~(((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS)) +#define EF_CTRL_EF_IF_PS EF_CTRL_EF_IF_PS +#define EF_CTRL_EF_IF_PS_POS (11U) +#define EF_CTRL_EF_IF_PS_LEN (1U) +#define EF_CTRL_EF_IF_PS_MSK (((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS) +#define EF_CTRL_EF_IF_PS_UMSK (~(((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS)) +#define EF_CTRL_EF_IF_STROBE EF_CTRL_EF_IF_STROBE +#define EF_CTRL_EF_IF_STROBE_POS (12U) +#define EF_CTRL_EF_IF_STROBE_LEN (1U) +#define EF_CTRL_EF_IF_STROBE_MSK (((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS) +#define EF_CTRL_EF_IF_STROBE_UMSK (~(((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS)) +#define EF_CTRL_EF_IF_PGENB EF_CTRL_EF_IF_PGENB +#define EF_CTRL_EF_IF_PGENB_POS (13U) +#define EF_CTRL_EF_IF_PGENB_LEN (1U) +#define EF_CTRL_EF_IF_PGENB_MSK (((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS) +#define EF_CTRL_EF_IF_PGENB_UMSK (~(((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS)) +#define EF_CTRL_EF_IF_LOAD EF_CTRL_EF_IF_LOAD +#define EF_CTRL_EF_IF_LOAD_POS (14U) +#define EF_CTRL_EF_IF_LOAD_LEN (1U) +#define EF_CTRL_EF_IF_LOAD_MSK (((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS) +#define EF_CTRL_EF_IF_LOAD_UMSK (~(((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS)) +#define EF_CTRL_EF_IF_CSB EF_CTRL_EF_IF_CSB +#define EF_CTRL_EF_IF_CSB_POS (15U) +#define EF_CTRL_EF_IF_CSB_LEN (1U) +#define EF_CTRL_EF_IF_CSB_MSK (((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS) +#define EF_CTRL_EF_IF_CSB_UMSK (~(((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS)) +#define EF_CTRL_EF_IF_0_Q EF_CTRL_EF_IF_0_Q +#define EF_CTRL_EF_IF_0_Q_POS (16U) +#define EF_CTRL_EF_IF_0_Q_LEN (8U) +#define EF_CTRL_EF_IF_0_Q_MSK (((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS) +#define EF_CTRL_EF_IF_0_Q_UMSK (~(((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS)) +#define EF_CTRL_EF_IF_PROT_CODE_MANUAL EF_CTRL_EF_IF_PROT_CODE_MANUAL +#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS (24U) +#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN (8U) +#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_MSK (((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS) +#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS)) + +/* 0x810 : ef_if_0_status */ +#define EF_CTRL_EF_IF_0_STATUS_OFFSET (0x810) +#define EF_CTRL_EF_IF_0_STATUS EF_CTRL_EF_IF_0_STATUS +#define EF_CTRL_EF_IF_0_STATUS_POS (0U) +#define EF_CTRL_EF_IF_0_STATUS_LEN (32U) +#define EF_CTRL_EF_IF_0_STATUS_MSK (((1U << EF_CTRL_EF_IF_0_STATUS_LEN) - 1) << EF_CTRL_EF_IF_0_STATUS_POS) +#define EF_CTRL_EF_IF_0_STATUS_UMSK (~(((1U << EF_CTRL_EF_IF_0_STATUS_LEN) - 1) << EF_CTRL_EF_IF_0_STATUS_POS)) + +/* 0x814 : ef_if_cfg_0 */ +#define EF_CTRL_EF_IF_CFG_0_OFFSET (0x814) +#define EF_CTRL_EF_IF_SF_AES_MODE EF_CTRL_EF_IF_SF_AES_MODE +#define EF_CTRL_EF_IF_SF_AES_MODE_POS (0U) +#define EF_CTRL_EF_IF_SF_AES_MODE_LEN (2U) +#define EF_CTRL_EF_IF_SF_AES_MODE_MSK (((1U << EF_CTRL_EF_IF_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_IF_SF_AES_MODE_POS) +#define EF_CTRL_EF_IF_SF_AES_MODE_UMSK (~(((1U << EF_CTRL_EF_IF_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_IF_SF_AES_MODE_POS)) +#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE EF_CTRL_EF_IF_SBOOT_SIGN_MODE +#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS (2U) +#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN (2U) +#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_MSK (((1U << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS) +#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS)) +#define EF_CTRL_EF_IF_SBOOT_EN EF_CTRL_EF_IF_SBOOT_EN +#define EF_CTRL_EF_IF_SBOOT_EN_POS (4U) +#define EF_CTRL_EF_IF_SBOOT_EN_LEN (2U) +#define EF_CTRL_EF_IF_SBOOT_EN_MSK (((1U << EF_CTRL_EF_IF_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_EN_POS) +#define EF_CTRL_EF_IF_SBOOT_EN_UMSK (~(((1U << EF_CTRL_EF_IF_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_EN_POS)) +#define EF_CTRL_EF_IF_CPU1_ENC_EN EF_CTRL_EF_IF_CPU1_ENC_EN +#define EF_CTRL_EF_IF_CPU1_ENC_EN_POS (6U) +#define EF_CTRL_EF_IF_CPU1_ENC_EN_LEN (1U) +#define EF_CTRL_EF_IF_CPU1_ENC_EN_MSK (((1U << EF_CTRL_EF_IF_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU1_ENC_EN_POS) +#define EF_CTRL_EF_IF_CPU1_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_IF_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU1_ENC_EN_POS)) +#define EF_CTRL_EF_IF_CPU0_ENC_EN EF_CTRL_EF_IF_CPU0_ENC_EN +#define EF_CTRL_EF_IF_CPU0_ENC_EN_POS (7U) +#define EF_CTRL_EF_IF_CPU0_ENC_EN_LEN (1U) +#define EF_CTRL_EF_IF_CPU0_ENC_EN_MSK (((1U << EF_CTRL_EF_IF_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU0_ENC_EN_POS) +#define EF_CTRL_EF_IF_CPU0_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_IF_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU0_ENC_EN_POS)) +#define EF_CTRL_EF_IF_BOOT_SEL EF_CTRL_EF_IF_BOOT_SEL +#define EF_CTRL_EF_IF_BOOT_SEL_POS (8U) +#define EF_CTRL_EF_IF_BOOT_SEL_LEN (4U) +#define EF_CTRL_EF_IF_BOOT_SEL_MSK (((1U << EF_CTRL_EF_IF_BOOT_SEL_LEN) - 1) << EF_CTRL_EF_IF_BOOT_SEL_POS) +#define EF_CTRL_EF_IF_BOOT_SEL_UMSK (~(((1U << EF_CTRL_EF_IF_BOOT_SEL_LEN) - 1) << EF_CTRL_EF_IF_BOOT_SEL_POS)) +#define EF_CTRL_EF_IF_SW_USAGE_1 EF_CTRL_EF_IF_SW_USAGE_1 +#define EF_CTRL_EF_IF_SW_USAGE_1_POS (12U) +#define EF_CTRL_EF_IF_SW_USAGE_1_LEN (2U) +#define EF_CTRL_EF_IF_SW_USAGE_1_MSK (((1U << EF_CTRL_EF_IF_SW_USAGE_1_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_1_POS) +#define EF_CTRL_EF_IF_SW_USAGE_1_UMSK (~(((1U << EF_CTRL_EF_IF_SW_USAGE_1_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_1_POS)) +#define EF_CTRL_EF_IF_SDU_DIS EF_CTRL_EF_IF_SDU_DIS +#define EF_CTRL_EF_IF_SDU_DIS_POS (14U) +#define EF_CTRL_EF_IF_SDU_DIS_LEN (1U) +#define EF_CTRL_EF_IF_SDU_DIS_MSK (((1U << EF_CTRL_EF_IF_SDU_DIS_LEN) - 1) << EF_CTRL_EF_IF_SDU_DIS_POS) +#define EF_CTRL_EF_IF_SDU_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_SDU_DIS_LEN) - 1) << EF_CTRL_EF_IF_SDU_DIS_POS)) +#define EF_CTRL_EF_IF_BLE_DIS EF_CTRL_EF_IF_BLE_DIS +#define EF_CTRL_EF_IF_BLE_DIS_POS (15U) +#define EF_CTRL_EF_IF_BLE_DIS_LEN (1U) +#define EF_CTRL_EF_IF_BLE_DIS_MSK (((1U << EF_CTRL_EF_IF_BLE_DIS_LEN) - 1) << EF_CTRL_EF_IF_BLE_DIS_POS) +#define EF_CTRL_EF_IF_BLE_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_BLE_DIS_LEN) - 1) << EF_CTRL_EF_IF_BLE_DIS_POS)) +#define EF_CTRL_EF_IF_WIFI_DIS EF_CTRL_EF_IF_WIFI_DIS +#define EF_CTRL_EF_IF_WIFI_DIS_POS (16U) +#define EF_CTRL_EF_IF_WIFI_DIS_LEN (1U) +#define EF_CTRL_EF_IF_WIFI_DIS_MSK (((1U << EF_CTRL_EF_IF_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_IF_WIFI_DIS_POS) +#define EF_CTRL_EF_IF_WIFI_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_IF_WIFI_DIS_POS)) +#define EF_CTRL_EF_IF_0_KEY_ENC_EN EF_CTRL_EF_IF_0_KEY_ENC_EN +#define EF_CTRL_EF_IF_0_KEY_ENC_EN_POS (17U) +#define EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN (1U) +#define EF_CTRL_EF_IF_0_KEY_ENC_EN_MSK (((1U << EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_0_KEY_ENC_EN_POS) +#define EF_CTRL_EF_IF_0_KEY_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_0_KEY_ENC_EN_POS)) +#define EF_CTRL_EF_IF_CAM_DIS EF_CTRL_EF_IF_CAM_DIS +#define EF_CTRL_EF_IF_CAM_DIS_POS (18U) +#define EF_CTRL_EF_IF_CAM_DIS_LEN (1U) +#define EF_CTRL_EF_IF_CAM_DIS_MSK (((1U << EF_CTRL_EF_IF_CAM_DIS_LEN) - 1) << EF_CTRL_EF_IF_CAM_DIS_POS) +#define EF_CTRL_EF_IF_CAM_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CAM_DIS_LEN) - 1) << EF_CTRL_EF_IF_CAM_DIS_POS)) +#define EF_CTRL_EF_IF_SF_DIS EF_CTRL_EF_IF_SF_DIS +#define EF_CTRL_EF_IF_SF_DIS_POS (19U) +#define EF_CTRL_EF_IF_SF_DIS_LEN (1U) +#define EF_CTRL_EF_IF_SF_DIS_MSK (((1U << EF_CTRL_EF_IF_SF_DIS_LEN) - 1) << EF_CTRL_EF_IF_SF_DIS_POS) +#define EF_CTRL_EF_IF_SF_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_SF_DIS_LEN) - 1) << EF_CTRL_EF_IF_SF_DIS_POS)) +#define EF_CTRL_EF_IF_CPU1_DIS EF_CTRL_EF_IF_CPU1_DIS +#define EF_CTRL_EF_IF_CPU1_DIS_POS (20U) +#define EF_CTRL_EF_IF_CPU1_DIS_LEN (1U) +#define EF_CTRL_EF_IF_CPU1_DIS_MSK (((1U << EF_CTRL_EF_IF_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU1_DIS_POS) +#define EF_CTRL_EF_IF_CPU1_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU1_DIS_POS)) +#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS EF_CTRL_EF_IF_CPU_RST_DBG_DIS +#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS (21U) +#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_MSK (((1U << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS) +#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS)) +#define EF_CTRL_EF_IF_SE_DBG_DIS EF_CTRL_EF_IF_SE_DBG_DIS +#define EF_CTRL_EF_IF_SE_DBG_DIS_POS (22U) +#define EF_CTRL_EF_IF_SE_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_IF_SE_DBG_DIS_MSK (((1U << EF_CTRL_EF_IF_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_SE_DBG_DIS_POS) +#define EF_CTRL_EF_IF_SE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_SE_DBG_DIS_POS)) +#define EF_CTRL_EF_IF_EFUSE_DBG_DIS EF_CTRL_EF_IF_EFUSE_DBG_DIS +#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS (23U) +#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_MSK (((1U << EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS) +#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS)) +#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS EF_CTRL_EF_IF_DBG_JTAG_1_DIS +#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS (24U) +#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN (2U) +#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_MSK (((1U << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS) +#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS)) +#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS EF_CTRL_EF_IF_DBG_JTAG_0_DIS +#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS (26U) +#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN (2U) +#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_MSK (((1U << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS) +#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS)) +#define EF_CTRL_EF_IF_DBG_MODE EF_CTRL_EF_IF_DBG_MODE +#define EF_CTRL_EF_IF_DBG_MODE_POS (28U) +#define EF_CTRL_EF_IF_DBG_MODE_LEN (4U) +#define EF_CTRL_EF_IF_DBG_MODE_MSK (((1U << EF_CTRL_EF_IF_DBG_MODE_LEN) - 1) << EF_CTRL_EF_IF_DBG_MODE_POS) +#define EF_CTRL_EF_IF_DBG_MODE_UMSK (~(((1U << EF_CTRL_EF_IF_DBG_MODE_LEN) - 1) << EF_CTRL_EF_IF_DBG_MODE_POS)) + +/* 0x818 : ef_sw_cfg_0 */ +#define EF_CTRL_EF_SW_CFG_0_OFFSET (0x818) +#define EF_CTRL_EF_SW_SF_AES_MODE EF_CTRL_EF_SW_SF_AES_MODE +#define EF_CTRL_EF_SW_SF_AES_MODE_POS (0U) +#define EF_CTRL_EF_SW_SF_AES_MODE_LEN (2U) +#define EF_CTRL_EF_SW_SF_AES_MODE_MSK (((1U << EF_CTRL_EF_SW_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_SW_SF_AES_MODE_POS) +#define EF_CTRL_EF_SW_SF_AES_MODE_UMSK (~(((1U << EF_CTRL_EF_SW_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_SW_SF_AES_MODE_POS)) +#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE EF_CTRL_EF_SW_SBOOT_SIGN_MODE +#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS (2U) +#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN (2U) +#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_MSK (((1U << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS) +#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS)) +#define EF_CTRL_EF_SW_SBOOT_EN EF_CTRL_EF_SW_SBOOT_EN +#define EF_CTRL_EF_SW_SBOOT_EN_POS (4U) +#define EF_CTRL_EF_SW_SBOOT_EN_LEN (2U) +#define EF_CTRL_EF_SW_SBOOT_EN_MSK (((1U << EF_CTRL_EF_SW_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_EN_POS) +#define EF_CTRL_EF_SW_SBOOT_EN_UMSK (~(((1U << EF_CTRL_EF_SW_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_EN_POS)) +#define EF_CTRL_EF_SW_CPU1_ENC_EN EF_CTRL_EF_SW_CPU1_ENC_EN +#define EF_CTRL_EF_SW_CPU1_ENC_EN_POS (6U) +#define EF_CTRL_EF_SW_CPU1_ENC_EN_LEN (1U) +#define EF_CTRL_EF_SW_CPU1_ENC_EN_MSK (((1U << EF_CTRL_EF_SW_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU1_ENC_EN_POS) +#define EF_CTRL_EF_SW_CPU1_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_SW_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU1_ENC_EN_POS)) +#define EF_CTRL_EF_SW_CPU0_ENC_EN EF_CTRL_EF_SW_CPU0_ENC_EN +#define EF_CTRL_EF_SW_CPU0_ENC_EN_POS (7U) +#define EF_CTRL_EF_SW_CPU0_ENC_EN_LEN (1U) +#define EF_CTRL_EF_SW_CPU0_ENC_EN_MSK (((1U << EF_CTRL_EF_SW_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU0_ENC_EN_POS) +#define EF_CTRL_EF_SW_CPU0_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_SW_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU0_ENC_EN_POS)) +#define EF_CTRL_EF_SW_SW_USAGE_1 EF_CTRL_EF_SW_SW_USAGE_1 +#define EF_CTRL_EF_SW_SW_USAGE_1_POS (12U) +#define EF_CTRL_EF_SW_SW_USAGE_1_LEN (2U) +#define EF_CTRL_EF_SW_SW_USAGE_1_MSK (((1U << EF_CTRL_EF_SW_SW_USAGE_1_LEN) - 1) << EF_CTRL_EF_SW_SW_USAGE_1_POS) +#define EF_CTRL_EF_SW_SW_USAGE_1_UMSK (~(((1U << EF_CTRL_EF_SW_SW_USAGE_1_LEN) - 1) << EF_CTRL_EF_SW_SW_USAGE_1_POS)) +#define EF_CTRL_EF_SW_SDU_DIS EF_CTRL_EF_SW_SDU_DIS +#define EF_CTRL_EF_SW_SDU_DIS_POS (14U) +#define EF_CTRL_EF_SW_SDU_DIS_LEN (1U) +#define EF_CTRL_EF_SW_SDU_DIS_MSK (((1U << EF_CTRL_EF_SW_SDU_DIS_LEN) - 1) << EF_CTRL_EF_SW_SDU_DIS_POS) +#define EF_CTRL_EF_SW_SDU_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_SDU_DIS_LEN) - 1) << EF_CTRL_EF_SW_SDU_DIS_POS)) +#define EF_CTRL_EF_SW_BLE_DIS EF_CTRL_EF_SW_BLE_DIS +#define EF_CTRL_EF_SW_BLE_DIS_POS (15U) +#define EF_CTRL_EF_SW_BLE_DIS_LEN (1U) +#define EF_CTRL_EF_SW_BLE_DIS_MSK (((1U << EF_CTRL_EF_SW_BLE_DIS_LEN) - 1) << EF_CTRL_EF_SW_BLE_DIS_POS) +#define EF_CTRL_EF_SW_BLE_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_BLE_DIS_LEN) - 1) << EF_CTRL_EF_SW_BLE_DIS_POS)) +#define EF_CTRL_EF_SW_WIFI_DIS EF_CTRL_EF_SW_WIFI_DIS +#define EF_CTRL_EF_SW_WIFI_DIS_POS (16U) +#define EF_CTRL_EF_SW_WIFI_DIS_LEN (1U) +#define EF_CTRL_EF_SW_WIFI_DIS_MSK (((1U << EF_CTRL_EF_SW_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_SW_WIFI_DIS_POS) +#define EF_CTRL_EF_SW_WIFI_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_SW_WIFI_DIS_POS)) +#define EF_CTRL_EF_SW_0_KEY_ENC_EN EF_CTRL_EF_SW_0_KEY_ENC_EN +#define EF_CTRL_EF_SW_0_KEY_ENC_EN_POS (17U) +#define EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN (1U) +#define EF_CTRL_EF_SW_0_KEY_ENC_EN_MSK (((1U << EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_0_KEY_ENC_EN_POS) +#define EF_CTRL_EF_SW_0_KEY_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_0_KEY_ENC_EN_POS)) +#define EF_CTRL_EF_SW_CAM_DIS EF_CTRL_EF_SW_CAM_DIS +#define EF_CTRL_EF_SW_CAM_DIS_POS (18U) +#define EF_CTRL_EF_SW_CAM_DIS_LEN (1U) +#define EF_CTRL_EF_SW_CAM_DIS_MSK (((1U << EF_CTRL_EF_SW_CAM_DIS_LEN) - 1) << EF_CTRL_EF_SW_CAM_DIS_POS) +#define EF_CTRL_EF_SW_CAM_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CAM_DIS_LEN) - 1) << EF_CTRL_EF_SW_CAM_DIS_POS)) +#define EF_CTRL_EF_SW_SF_DIS EF_CTRL_EF_SW_SF_DIS +#define EF_CTRL_EF_SW_SF_DIS_POS (19U) +#define EF_CTRL_EF_SW_SF_DIS_LEN (1U) +#define EF_CTRL_EF_SW_SF_DIS_MSK (((1U << EF_CTRL_EF_SW_SF_DIS_LEN) - 1) << EF_CTRL_EF_SW_SF_DIS_POS) +#define EF_CTRL_EF_SW_SF_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_SF_DIS_LEN) - 1) << EF_CTRL_EF_SW_SF_DIS_POS)) +#define EF_CTRL_EF_SW_CPU1_DIS EF_CTRL_EF_SW_CPU1_DIS +#define EF_CTRL_EF_SW_CPU1_DIS_POS (20U) +#define EF_CTRL_EF_SW_CPU1_DIS_LEN (1U) +#define EF_CTRL_EF_SW_CPU1_DIS_MSK (((1U << EF_CTRL_EF_SW_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU1_DIS_POS) +#define EF_CTRL_EF_SW_CPU1_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU1_DIS_POS)) +#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS EF_CTRL_EF_SW_CPU_RST_DBG_DIS +#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS (21U) +#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_MSK (((1U << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS) +#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS)) +#define EF_CTRL_EF_SW_SE_DBG_DIS EF_CTRL_EF_SW_SE_DBG_DIS +#define EF_CTRL_EF_SW_SE_DBG_DIS_POS (22U) +#define EF_CTRL_EF_SW_SE_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_SW_SE_DBG_DIS_MSK (((1U << EF_CTRL_EF_SW_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_SE_DBG_DIS_POS) +#define EF_CTRL_EF_SW_SE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_SE_DBG_DIS_POS)) +#define EF_CTRL_EF_SW_EFUSE_DBG_DIS EF_CTRL_EF_SW_EFUSE_DBG_DIS +#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS (23U) +#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_MSK (((1U << EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS) +#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS)) +#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS EF_CTRL_EF_SW_DBG_JTAG_1_DIS +#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS (24U) +#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN (2U) +#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_MSK (((1U << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS) +#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS)) +#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS EF_CTRL_EF_SW_DBG_JTAG_0_DIS +#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS (26U) +#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN (2U) +#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_MSK (((1U << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS) +#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS)) +#define EF_CTRL_EF_SW_DBG_MODE EF_CTRL_EF_SW_DBG_MODE +#define EF_CTRL_EF_SW_DBG_MODE_POS (28U) +#define EF_CTRL_EF_SW_DBG_MODE_LEN (4U) +#define EF_CTRL_EF_SW_DBG_MODE_MSK (((1U << EF_CTRL_EF_SW_DBG_MODE_LEN) - 1) << EF_CTRL_EF_SW_DBG_MODE_POS) +#define EF_CTRL_EF_SW_DBG_MODE_UMSK (~(((1U << EF_CTRL_EF_SW_DBG_MODE_LEN) - 1) << EF_CTRL_EF_SW_DBG_MODE_POS)) + +/* 0x81C : ef_reserved */ +#define EF_CTRL_EF_RESERVED_OFFSET (0x81C) +#define EF_CTRL_EF_RESERVED EF_CTRL_EF_RESERVED +#define EF_CTRL_EF_RESERVED_POS (0U) +#define EF_CTRL_EF_RESERVED_LEN (32U) +#define EF_CTRL_EF_RESERVED_MSK (((1U << EF_CTRL_EF_RESERVED_LEN) - 1) << EF_CTRL_EF_RESERVED_POS) +#define EF_CTRL_EF_RESERVED_UMSK (~(((1U << EF_CTRL_EF_RESERVED_LEN) - 1) << EF_CTRL_EF_RESERVED_POS)) + +/* 0x820 : ef_if_ana_trim_0 */ +#define EF_CTRL_EF_IF_ANA_TRIM_0_OFFSET (0x820) +#define EF_CTRL_EF_IF_ANA_TRIM_0 EF_CTRL_EF_IF_ANA_TRIM_0 +#define EF_CTRL_EF_IF_ANA_TRIM_0_POS (0U) +#define EF_CTRL_EF_IF_ANA_TRIM_0_LEN (32U) +#define EF_CTRL_EF_IF_ANA_TRIM_0_MSK (((1U << EF_CTRL_EF_IF_ANA_TRIM_0_LEN) - 1) << EF_CTRL_EF_IF_ANA_TRIM_0_POS) +#define EF_CTRL_EF_IF_ANA_TRIM_0_UMSK (~(((1U << EF_CTRL_EF_IF_ANA_TRIM_0_LEN) - 1) << EF_CTRL_EF_IF_ANA_TRIM_0_POS)) + +/* 0x824 : ef_if_sw_usage_0 */ +#define EF_CTRL_EF_IF_SW_USAGE_0_OFFSET (0x824) +#define EF_CTRL_EF_IF_SW_USAGE_0 EF_CTRL_EF_IF_SW_USAGE_0 +#define EF_CTRL_EF_IF_SW_USAGE_0_POS (0U) +#define EF_CTRL_EF_IF_SW_USAGE_0_LEN (32U) +#define EF_CTRL_EF_IF_SW_USAGE_0_MSK (((1U << EF_CTRL_EF_IF_SW_USAGE_0_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_0_POS) +#define EF_CTRL_EF_IF_SW_USAGE_0_UMSK (~(((1U << EF_CTRL_EF_IF_SW_USAGE_0_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_0_POS)) + +/* 0xA00 : ef_crc_ctrl_0 */ +#define EF_CTRL_EF_CRC_CTRL_0_OFFSET (0xA00) +#define EF_CTRL_EF_CRC_BUSY EF_CTRL_EF_CRC_BUSY +#define EF_CTRL_EF_CRC_BUSY_POS (0U) +#define EF_CTRL_EF_CRC_BUSY_LEN (1U) +#define EF_CTRL_EF_CRC_BUSY_MSK (((1U << EF_CTRL_EF_CRC_BUSY_LEN) - 1) << EF_CTRL_EF_CRC_BUSY_POS) +#define EF_CTRL_EF_CRC_BUSY_UMSK (~(((1U << EF_CTRL_EF_CRC_BUSY_LEN) - 1) << EF_CTRL_EF_CRC_BUSY_POS)) +#define EF_CTRL_EF_CRC_TRIG EF_CTRL_EF_CRC_TRIG +#define EF_CTRL_EF_CRC_TRIG_POS (1U) +#define EF_CTRL_EF_CRC_TRIG_LEN (1U) +#define EF_CTRL_EF_CRC_TRIG_MSK (((1U << EF_CTRL_EF_CRC_TRIG_LEN) - 1) << EF_CTRL_EF_CRC_TRIG_POS) +#define EF_CTRL_EF_CRC_TRIG_UMSK (~(((1U << EF_CTRL_EF_CRC_TRIG_LEN) - 1) << EF_CTRL_EF_CRC_TRIG_POS)) +#define EF_CTRL_EF_CRC_EN EF_CTRL_EF_CRC_EN +#define EF_CTRL_EF_CRC_EN_POS (2U) +#define EF_CTRL_EF_CRC_EN_LEN (1U) +#define EF_CTRL_EF_CRC_EN_MSK (((1U << EF_CTRL_EF_CRC_EN_LEN) - 1) << EF_CTRL_EF_CRC_EN_POS) +#define EF_CTRL_EF_CRC_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_EN_LEN) - 1) << EF_CTRL_EF_CRC_EN_POS)) +#define EF_CTRL_EF_CRC_MODE EF_CTRL_EF_CRC_MODE +#define EF_CTRL_EF_CRC_MODE_POS (3U) +#define EF_CTRL_EF_CRC_MODE_LEN (1U) +#define EF_CTRL_EF_CRC_MODE_MSK (((1U << EF_CTRL_EF_CRC_MODE_LEN) - 1) << EF_CTRL_EF_CRC_MODE_POS) +#define EF_CTRL_EF_CRC_MODE_UMSK (~(((1U << EF_CTRL_EF_CRC_MODE_LEN) - 1) << EF_CTRL_EF_CRC_MODE_POS)) +#define EF_CTRL_EF_CRC_ERROR EF_CTRL_EF_CRC_ERROR +#define EF_CTRL_EF_CRC_ERROR_POS (4U) +#define EF_CTRL_EF_CRC_ERROR_LEN (1U) +#define EF_CTRL_EF_CRC_ERROR_MSK (((1U << EF_CTRL_EF_CRC_ERROR_LEN) - 1) << EF_CTRL_EF_CRC_ERROR_POS) +#define EF_CTRL_EF_CRC_ERROR_UMSK (~(((1U << EF_CTRL_EF_CRC_ERROR_LEN) - 1) << EF_CTRL_EF_CRC_ERROR_POS)) +#define EF_CTRL_EF_CRC_DOUT_INV_EN EF_CTRL_EF_CRC_DOUT_INV_EN +#define EF_CTRL_EF_CRC_DOUT_INV_EN_POS (5U) +#define EF_CTRL_EF_CRC_DOUT_INV_EN_LEN (1U) +#define EF_CTRL_EF_CRC_DOUT_INV_EN_MSK (((1U << EF_CTRL_EF_CRC_DOUT_INV_EN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_INV_EN_POS) +#define EF_CTRL_EF_CRC_DOUT_INV_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_INV_EN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_INV_EN_POS)) +#define EF_CTRL_EF_CRC_DOUT_ENDIAN EF_CTRL_EF_CRC_DOUT_ENDIAN +#define EF_CTRL_EF_CRC_DOUT_ENDIAN_POS (6U) +#define EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN (1U) +#define EF_CTRL_EF_CRC_DOUT_ENDIAN_MSK (((1U << EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_ENDIAN_POS) +#define EF_CTRL_EF_CRC_DOUT_ENDIAN_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_ENDIAN_POS)) +#define EF_CTRL_EF_CRC_DIN_ENDIAN EF_CTRL_EF_CRC_DIN_ENDIAN +#define EF_CTRL_EF_CRC_DIN_ENDIAN_POS (7U) +#define EF_CTRL_EF_CRC_DIN_ENDIAN_LEN (1U) +#define EF_CTRL_EF_CRC_DIN_ENDIAN_MSK (((1U << EF_CTRL_EF_CRC_DIN_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DIN_ENDIAN_POS) +#define EF_CTRL_EF_CRC_DIN_ENDIAN_UMSK (~(((1U << EF_CTRL_EF_CRC_DIN_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DIN_ENDIAN_POS)) +#define EF_CTRL_EF_CRC_INT EF_CTRL_EF_CRC_INT +#define EF_CTRL_EF_CRC_INT_POS (8U) +#define EF_CTRL_EF_CRC_INT_LEN (1U) +#define EF_CTRL_EF_CRC_INT_MSK (((1U << EF_CTRL_EF_CRC_INT_LEN) - 1) << EF_CTRL_EF_CRC_INT_POS) +#define EF_CTRL_EF_CRC_INT_UMSK (~(((1U << EF_CTRL_EF_CRC_INT_LEN) - 1) << EF_CTRL_EF_CRC_INT_POS)) +#define EF_CTRL_EF_CRC_INT_CLR EF_CTRL_EF_CRC_INT_CLR +#define EF_CTRL_EF_CRC_INT_CLR_POS (9U) +#define EF_CTRL_EF_CRC_INT_CLR_LEN (1U) +#define EF_CTRL_EF_CRC_INT_CLR_MSK (((1U << EF_CTRL_EF_CRC_INT_CLR_LEN) - 1) << EF_CTRL_EF_CRC_INT_CLR_POS) +#define EF_CTRL_EF_CRC_INT_CLR_UMSK (~(((1U << EF_CTRL_EF_CRC_INT_CLR_LEN) - 1) << EF_CTRL_EF_CRC_INT_CLR_POS)) +#define EF_CTRL_EF_CRC_INT_SET EF_CTRL_EF_CRC_INT_SET +#define EF_CTRL_EF_CRC_INT_SET_POS (10U) +#define EF_CTRL_EF_CRC_INT_SET_LEN (1U) +#define EF_CTRL_EF_CRC_INT_SET_MSK (((1U << EF_CTRL_EF_CRC_INT_SET_LEN) - 1) << EF_CTRL_EF_CRC_INT_SET_POS) +#define EF_CTRL_EF_CRC_INT_SET_UMSK (~(((1U << EF_CTRL_EF_CRC_INT_SET_LEN) - 1) << EF_CTRL_EF_CRC_INT_SET_POS)) +#define EF_CTRL_EF_CRC_LOCK EF_CTRL_EF_CRC_LOCK +#define EF_CTRL_EF_CRC_LOCK_POS (11U) +#define EF_CTRL_EF_CRC_LOCK_LEN (1U) +#define EF_CTRL_EF_CRC_LOCK_MSK (((1U << EF_CTRL_EF_CRC_LOCK_LEN) - 1) << EF_CTRL_EF_CRC_LOCK_POS) +#define EF_CTRL_EF_CRC_LOCK_UMSK (~(((1U << EF_CTRL_EF_CRC_LOCK_LEN) - 1) << EF_CTRL_EF_CRC_LOCK_POS)) +#define EF_CTRL_EF_CRC_SLP_N EF_CTRL_EF_CRC_SLP_N +#define EF_CTRL_EF_CRC_SLP_N_POS (16U) +#define EF_CTRL_EF_CRC_SLP_N_LEN (16U) +#define EF_CTRL_EF_CRC_SLP_N_MSK (((1U << EF_CTRL_EF_CRC_SLP_N_LEN) - 1) << EF_CTRL_EF_CRC_SLP_N_POS) +#define EF_CTRL_EF_CRC_SLP_N_UMSK (~(((1U << EF_CTRL_EF_CRC_SLP_N_LEN) - 1) << EF_CTRL_EF_CRC_SLP_N_POS)) + +/* 0xA04 : ef_crc_ctrl_1 */ +#define EF_CTRL_EF_CRC_CTRL_1_OFFSET (0xA04) +#define EF_CTRL_EF_CRC_DATA_0_EN EF_CTRL_EF_CRC_DATA_0_EN +#define EF_CTRL_EF_CRC_DATA_0_EN_POS (0U) +#define EF_CTRL_EF_CRC_DATA_0_EN_LEN (32U) +#define EF_CTRL_EF_CRC_DATA_0_EN_MSK (((1U << EF_CTRL_EF_CRC_DATA_0_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_0_EN_POS) +#define EF_CTRL_EF_CRC_DATA_0_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DATA_0_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_0_EN_POS)) + +/* 0xA08 : ef_crc_ctrl_2 */ +#define EF_CTRL_EF_CRC_CTRL_2_OFFSET (0xA08) +#define EF_CTRL_EF_CRC_DATA_1_EN EF_CTRL_EF_CRC_DATA_1_EN +#define EF_CTRL_EF_CRC_DATA_1_EN_POS (0U) +#define EF_CTRL_EF_CRC_DATA_1_EN_LEN (32U) +#define EF_CTRL_EF_CRC_DATA_1_EN_MSK (((1U << EF_CTRL_EF_CRC_DATA_1_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_1_EN_POS) +#define EF_CTRL_EF_CRC_DATA_1_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DATA_1_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_1_EN_POS)) + +/* 0xA0C : ef_crc_ctrl_3 */ +#define EF_CTRL_EF_CRC_CTRL_3_OFFSET (0xA0C) +#define EF_CTRL_EF_CRC_IV EF_CTRL_EF_CRC_IV +#define EF_CTRL_EF_CRC_IV_POS (0U) +#define EF_CTRL_EF_CRC_IV_LEN (32U) +#define EF_CTRL_EF_CRC_IV_MSK (((1U << EF_CTRL_EF_CRC_IV_LEN) - 1) << EF_CTRL_EF_CRC_IV_POS) +#define EF_CTRL_EF_CRC_IV_UMSK (~(((1U << EF_CTRL_EF_CRC_IV_LEN) - 1) << EF_CTRL_EF_CRC_IV_POS)) + +/* 0xA10 : ef_crc_ctrl_4 */ +#define EF_CTRL_EF_CRC_CTRL_4_OFFSET (0xA10) +#define EF_CTRL_EF_CRC_GOLDEN EF_CTRL_EF_CRC_GOLDEN +#define EF_CTRL_EF_CRC_GOLDEN_POS (0U) +#define EF_CTRL_EF_CRC_GOLDEN_LEN (32U) +#define EF_CTRL_EF_CRC_GOLDEN_MSK (((1U << EF_CTRL_EF_CRC_GOLDEN_LEN) - 1) << EF_CTRL_EF_CRC_GOLDEN_POS) +#define EF_CTRL_EF_CRC_GOLDEN_UMSK (~(((1U << EF_CTRL_EF_CRC_GOLDEN_LEN) - 1) << EF_CTRL_EF_CRC_GOLDEN_POS)) + +/* 0xA14 : ef_crc_ctrl_5 */ +#define EF_CTRL_EF_CRC_CTRL_5_OFFSET (0xA14) +#define EF_CTRL_EF_CRC_DOUT EF_CTRL_EF_CRC_DOUT +#define EF_CTRL_EF_CRC_DOUT_POS (0U) +#define EF_CTRL_EF_CRC_DOUT_LEN (32U) +#define EF_CTRL_EF_CRC_DOUT_MSK (((1U << EF_CTRL_EF_CRC_DOUT_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_POS) +#define EF_CTRL_EF_CRC_DOUT_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_POS)) + +struct ef_ctrl_reg { + /* 0x0 reserved */ + uint8_t RESERVED0x0[2048]; + + /* 0x800 : ef_if_ctrl_0 */ + union { + struct + { + uint32_t ef_if_0_autoload_p1_done : 1; /* [ 0], r, 0x1 */ + uint32_t ef_if_0_autoload_done : 1; /* [ 1], r, 0x1 */ + uint32_t ef_if_0_busy : 1; /* [ 2], r, 0x0 */ + uint32_t ef_if_0_rw : 1; /* [ 3], r/w, 0x0 */ + uint32_t ef_if_0_trig : 1; /* [ 4], r/w, 0x0 */ + uint32_t ef_if_0_manual_en : 1; /* [ 5], r/w, 0x0 */ + uint32_t ef_if_0_cyc_modify : 1; /* [ 6], r/w, 0x0 */ + uint32_t ef_clk_sahb_data_sel : 1; /* [ 7], r/w, 0x0 */ + uint32_t ef_if_prot_code_ctrl : 8; /* [15: 8], r/w, 0x0 */ + uint32_t ef_if_por_dig : 1; /* [ 16], r/w, 0x0 */ + uint32_t ef_clk_sahb_data_gate : 1; /* [ 17], r/w, 0x0 */ + uint32_t ef_if_auto_rd_en : 1; /* [ 18], r/w, 0x1 */ + uint32_t ef_if_cyc_modify_lock : 1; /* [ 19], r/w, 0x0 */ + uint32_t ef_if_0_int : 1; /* [ 20], r, 0x0 */ + uint32_t ef_if_0_int_clr : 1; /* [ 21], r/w, 0x1 */ + uint32_t ef_if_0_int_set : 1; /* [ 22], r/w, 0x0 */ + uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ + uint32_t ef_if_prot_code_cyc : 8; /* [31:24], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_ctrl_0; + + /* 0x804 : ef_if_cyc_0 */ + union { + struct + { + uint32_t ef_if_cyc_rd_dmy : 6; /* [ 5: 0], r/w, 0x0 */ + uint32_t ef_if_cyc_rd_dat : 6; /* [11: 6], r/w, 0x1 */ + uint32_t ef_if_cyc_rd_adr : 6; /* [17:12], r/w, 0x0 */ + uint32_t ef_if_cyc_cs : 6; /* [23:18], r/w, 0x0 */ + uint32_t ef_if_cyc_pd_cs_s : 8; /* [31:24], r/w, 0x16 */ + } BF; + uint32_t WORD; + } ef_if_cyc_0; + + /* 0x808 : ef_if_cyc_1 */ + union { + struct + { + uint32_t ef_if_cyc_pi : 6; /* [ 5: 0], r/w, 0x9 */ + uint32_t ef_if_cyc_pp : 8; /* [13: 6], r/w, 0x98 */ + uint32_t ef_if_cyc_wr_adr : 6; /* [19:14], r/w, 0x1 */ + uint32_t ef_if_cyc_ps_cs : 6; /* [25:20], r/w, 0x2 */ + uint32_t ef_if_cyc_pd_cs_h : 6; /* [31:26], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_cyc_1; + + /* 0x80C : ef_if_0_manual */ + union { + struct + { + uint32_t ef_if_a : 10; /* [ 9: 0], r/w, 0x0 */ + uint32_t ef_if_pd : 1; /* [ 10], r/w, 0x1 */ + uint32_t ef_if_ps : 1; /* [ 11], r/w, 0x0 */ + uint32_t ef_if_strobe : 1; /* [ 12], r/w, 0x0 */ + uint32_t ef_if_pgenb : 1; /* [ 13], r/w, 0x1 */ + uint32_t ef_if_load : 1; /* [ 14], r/w, 0x1 */ + uint32_t ef_if_csb : 1; /* [ 15], r/w, 0x1 */ + uint32_t ef_if_0_q : 8; /* [23:16], r, 0x0 */ + uint32_t ef_if_prot_code_manual : 8; /* [31:24], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_0_manual; + + /* 0x810 : ef_if_0_status */ + union { + struct + { + uint32_t ef_if_0_status : 32; /* [31: 0], r, 0xe400 */ + } BF; + uint32_t WORD; + } ef_if_0_status; + + /* 0x814 : ef_if_cfg_0 */ + union { + struct + { + uint32_t ef_if_sf_aes_mode : 2; /* [ 1: 0], r, 0x0 */ + uint32_t ef_if_sboot_sign_mode : 2; /* [ 3: 2], r, 0x0 */ + uint32_t ef_if_sboot_en : 2; /* [ 5: 4], r, 0x0 */ + uint32_t ef_if_cpu1_enc_en : 1; /* [ 6], r, 0x0 */ + uint32_t ef_if_cpu0_enc_en : 1; /* [ 7], r, 0x0 */ + uint32_t ef_if_boot_sel : 4; /* [11: 8], r, 0x0 */ + uint32_t ef_if_sw_usage_1 : 2; /* [13:12], r, 0x0 */ + uint32_t ef_if_sdu_dis : 1; /* [ 14], r, 0x0 */ + uint32_t ef_if_ble_dis : 1; /* [ 15], r, 0x0 */ + uint32_t ef_if_wifi_dis : 1; /* [ 16], r, 0x0 */ + uint32_t ef_if_0_key_enc_en : 1; /* [ 17], r, 0x0 */ + uint32_t ef_if_cam_dis : 1; /* [ 18], r, 0x0 */ + uint32_t ef_if_sf_dis : 1; /* [ 19], r, 0x0 */ + uint32_t ef_if_cpu1_dis : 1; /* [ 20], r, 0x0 */ + uint32_t ef_if_cpu_rst_dbg_dis : 1; /* [ 21], r, 0x0 */ + uint32_t ef_if_se_dbg_dis : 1; /* [ 22], r, 0x0 */ + uint32_t ef_if_efuse_dbg_dis : 1; /* [ 23], r, 0x0 */ + uint32_t ef_if_dbg_jtag_1_dis : 2; /* [25:24], r, 0x0 */ + uint32_t ef_if_dbg_jtag_0_dis : 2; /* [27:26], r, 0x0 */ + uint32_t ef_if_dbg_mode : 4; /* [31:28], r, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_cfg_0; + + /* 0x818 : ef_sw_cfg_0 */ + union { + struct + { + uint32_t ef_sw_sf_aes_mode : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t ef_sw_sboot_sign_mode : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t ef_sw_sboot_en : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t ef_sw_cpu1_enc_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t ef_sw_cpu0_enc_en : 1; /* [ 7], r/w, 0x0 */ + uint32_t reserved_8_11 : 4; /* [11: 8], rsvd, 0x0 */ + uint32_t ef_sw_sw_usage_1 : 2; /* [13:12], r/w, 0x0 */ + uint32_t ef_sw_sdu_dis : 1; /* [ 14], r/w, 0x0 */ + uint32_t ef_sw_ble_dis : 1; /* [ 15], r/w, 0x0 */ + uint32_t ef_sw_wifi_dis : 1; /* [ 16], r/w, 0x0 */ + uint32_t ef_sw_0_key_enc_en : 1; /* [ 17], r/w, 0x0 */ + uint32_t ef_sw_cam_dis : 1; /* [ 18], r/w, 0x0 */ + uint32_t ef_sw_sf_dis : 1; /* [ 19], r/w, 0x0 */ + uint32_t ef_sw_cpu1_dis : 1; /* [ 20], r/w, 0x0 */ + uint32_t ef_sw_cpu_rst_dbg_dis : 1; /* [ 21], r/w, 0x0 */ + uint32_t ef_sw_se_dbg_dis : 1; /* [ 22], r/w, 0x0 */ + uint32_t ef_sw_efuse_dbg_dis : 1; /* [ 23], r/w, 0x0 */ + uint32_t ef_sw_dbg_jtag_1_dis : 2; /* [25:24], r/w, 0x0 */ + uint32_t ef_sw_dbg_jtag_0_dis : 2; /* [27:26], r/w, 0x0 */ + uint32_t ef_sw_dbg_mode : 4; /* [31:28], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_sw_cfg_0; + + /* 0x81C : ef_reserved */ + union { + struct + { + uint32_t ef_reserved : 32; /* [31: 0], r/w, 0xffff */ + } BF; + uint32_t WORD; + } ef_reserved; + + /* 0x820 : ef_if_ana_trim_0 */ + union { + struct + { + uint32_t ef_if_ana_trim_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_ana_trim_0; + + /* 0x824 : ef_if_sw_usage_0 */ + union { + struct + { + uint32_t ef_if_sw_usage_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_sw_usage_0; + + /* 0x828 reserved */ + uint8_t RESERVED0x828[472]; + + /* 0xA00 : ef_crc_ctrl_0 */ + union { + struct + { + uint32_t ef_crc_busy : 1; /* [ 0], r, 0x0 */ + uint32_t ef_crc_trig : 1; /* [ 1], r/w, 0x0 */ + uint32_t ef_crc_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t ef_crc_mode : 1; /* [ 3], r/w, 0x0 */ + uint32_t ef_crc_error : 1; /* [ 4], r, 0x0 */ + uint32_t ef_crc_dout_inv_en : 1; /* [ 5], r/w, 0x1 */ + uint32_t ef_crc_dout_endian : 1; /* [ 6], r/w, 0x0 */ + uint32_t ef_crc_din_endian : 1; /* [ 7], r/w, 0x0 */ + uint32_t ef_crc_int : 1; /* [ 8], r, 0x0 */ + uint32_t ef_crc_int_clr : 1; /* [ 9], r/w, 0x1 */ + uint32_t ef_crc_int_set : 1; /* [ 10], r/w, 0x0 */ + uint32_t ef_crc_lock : 1; /* [ 11], r/w, 0x0 */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t ef_crc_slp_n : 16; /* [31:16], r/w, 0xff */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_0; + + /* 0xA04 : ef_crc_ctrl_1 */ + union { + struct + { + uint32_t ef_crc_data_0_en : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_1; + + /* 0xA08 : ef_crc_ctrl_2 */ + union { + struct + { + uint32_t ef_crc_data_1_en : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_2; + + /* 0xA0C : ef_crc_ctrl_3 */ + union { + struct + { + uint32_t ef_crc_iv : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_3; + + /* 0xA10 : ef_crc_ctrl_4 */ + union { + struct + { + uint32_t ef_crc_golden : 32; /* [31: 0], r/w, 0xc2a8fa9dL */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_4; + + /* 0xA14 : ef_crc_ctrl_5 */ + union { + struct + { + uint32_t ef_crc_dout : 32; /* [31: 0], r, 0xffffffffL */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_5; +}; + +typedef volatile struct ef_ctrl_reg ef_ctrl_reg_t; + +#endif /* __EF_CTRL_REG_H__ */ diff --git a/drivers/soc/bl602/bl602_std/include/hardware/ef_data_0_reg.h b/drivers/soc/bl602/bl602_std/include/hardware/ef_data_0_reg.h new file mode 100644 index 00000000..2322c740 --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/hardware/ef_data_0_reg.h @@ -0,0 +1,762 @@ +/** + ****************************************************************************** + * @file ef_data_0_reg.h + * @version V1.2 + * @date 2019-11-22 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __EF_DATA_0_REG_H__ +#define __EF_DATA_0_REG_H__ + +#include "bl602.h" + +/* 0x0 : ef_cfg_0 */ +#define EF_DATA_0_EF_CFG_0_OFFSET (0x0) +#define EF_DATA_0_EF_SF_AES_MODE EF_DATA_0_EF_SF_AES_MODE +#define EF_DATA_0_EF_SF_AES_MODE_POS (0U) +#define EF_DATA_0_EF_SF_AES_MODE_LEN (2U) +#define EF_DATA_0_EF_SF_AES_MODE_MSK (((1U << EF_DATA_0_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_0_EF_SF_AES_MODE_POS) +#define EF_DATA_0_EF_SF_AES_MODE_UMSK (~(((1U << EF_DATA_0_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_0_EF_SF_AES_MODE_POS)) +#define EF_DATA_0_EF_SBOOT_SIGN_MODE EF_DATA_0_EF_SBOOT_SIGN_MODE +#define EF_DATA_0_EF_SBOOT_SIGN_MODE_POS (2U) +#define EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN (2U) +#define EF_DATA_0_EF_SBOOT_SIGN_MODE_MSK (((1U << EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_0_EF_SBOOT_SIGN_MODE_POS) +#define EF_DATA_0_EF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_0_EF_SBOOT_SIGN_MODE_POS)) +#define EF_DATA_0_EF_SBOOT_EN EF_DATA_0_EF_SBOOT_EN +#define EF_DATA_0_EF_SBOOT_EN_POS (4U) +#define EF_DATA_0_EF_SBOOT_EN_LEN (2U) +#define EF_DATA_0_EF_SBOOT_EN_MSK (((1U << EF_DATA_0_EF_SBOOT_EN_LEN) - 1) << EF_DATA_0_EF_SBOOT_EN_POS) +#define EF_DATA_0_EF_SBOOT_EN_UMSK (~(((1U << EF_DATA_0_EF_SBOOT_EN_LEN) - 1) << EF_DATA_0_EF_SBOOT_EN_POS)) +#define EF_DATA_0_EF_CPU0_ENC_EN EF_DATA_0_EF_CPU0_ENC_EN +#define EF_DATA_0_EF_CPU0_ENC_EN_POS (7U) +#define EF_DATA_0_EF_CPU0_ENC_EN_LEN (1U) +#define EF_DATA_0_EF_CPU0_ENC_EN_MSK (((1U << EF_DATA_0_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_0_EF_CPU0_ENC_EN_POS) +#define EF_DATA_0_EF_CPU0_ENC_EN_UMSK (~(((1U << EF_DATA_0_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_0_EF_CPU0_ENC_EN_POS)) +#define EF_DATA_0_EF_TRIM_EN EF_DATA_0_EF_TRIM_EN +#define EF_DATA_0_EF_TRIM_EN_POS (12U) +#define EF_DATA_0_EF_TRIM_EN_LEN (1U) +#define EF_DATA_0_EF_TRIM_EN_MSK (((1U << EF_DATA_0_EF_TRIM_EN_LEN) - 1) << EF_DATA_0_EF_TRIM_EN_POS) +#define EF_DATA_0_EF_TRIM_EN_UMSK (~(((1U << EF_DATA_0_EF_TRIM_EN_LEN) - 1) << EF_DATA_0_EF_TRIM_EN_POS)) +#define EF_DATA_0_EF_NO_HD_BOOT_EN EF_DATA_0_EF_NO_HD_BOOT_EN +#define EF_DATA_0_EF_NO_HD_BOOT_EN_POS (13U) +#define EF_DATA_0_EF_NO_HD_BOOT_EN_LEN (1U) +#define EF_DATA_0_EF_NO_HD_BOOT_EN_MSK (((1U << EF_DATA_0_EF_NO_HD_BOOT_EN_LEN) - 1) << EF_DATA_0_EF_NO_HD_BOOT_EN_POS) +#define EF_DATA_0_EF_NO_HD_BOOT_EN_UMSK (~(((1U << EF_DATA_0_EF_NO_HD_BOOT_EN_LEN) - 1) << EF_DATA_0_EF_NO_HD_BOOT_EN_POS)) +#define EF_DATA_0_EF_0_KEY_ENC_EN EF_DATA_0_EF_0_KEY_ENC_EN +#define EF_DATA_0_EF_0_KEY_ENC_EN_POS (17U) +#define EF_DATA_0_EF_0_KEY_ENC_EN_LEN (1U) +#define EF_DATA_0_EF_0_KEY_ENC_EN_MSK (((1U << EF_DATA_0_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_0_EF_0_KEY_ENC_EN_POS) +#define EF_DATA_0_EF_0_KEY_ENC_EN_UMSK (~(((1U << EF_DATA_0_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_0_EF_0_KEY_ENC_EN_POS)) +#define EF_DATA_0_EF_DBG_JTAG_0_DIS EF_DATA_0_EF_DBG_JTAG_0_DIS +#define EF_DATA_0_EF_DBG_JTAG_0_DIS_POS (26U) +#define EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN (2U) +#define EF_DATA_0_EF_DBG_JTAG_0_DIS_MSK (((1U << EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_0_DIS_POS) +#define EF_DATA_0_EF_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_0_DIS_POS)) +#define EF_DATA_0_EF_DBG_MODE EF_DATA_0_EF_DBG_MODE +#define EF_DATA_0_EF_DBG_MODE_POS (28U) +#define EF_DATA_0_EF_DBG_MODE_LEN (4U) +#define EF_DATA_0_EF_DBG_MODE_MSK (((1U << EF_DATA_0_EF_DBG_MODE_LEN) - 1) << EF_DATA_0_EF_DBG_MODE_POS) +#define EF_DATA_0_EF_DBG_MODE_UMSK (~(((1U << EF_DATA_0_EF_DBG_MODE_LEN) - 1) << EF_DATA_0_EF_DBG_MODE_POS)) + +/* 0x4 : ef_dbg_pwd_low */ +#define EF_DATA_0_EF_DBG_PWD_LOW_OFFSET (0x4) +#define EF_DATA_0_EF_DBG_PWD_LOW EF_DATA_0_EF_DBG_PWD_LOW +#define EF_DATA_0_EF_DBG_PWD_LOW_POS (0U) +#define EF_DATA_0_EF_DBG_PWD_LOW_LEN (32U) +#define EF_DATA_0_EF_DBG_PWD_LOW_MSK (((1U << EF_DATA_0_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_LOW_POS) +#define EF_DATA_0_EF_DBG_PWD_LOW_UMSK (~(((1U << EF_DATA_0_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_LOW_POS)) + +/* 0x8 : ef_dbg_pwd_high */ +#define EF_DATA_0_EF_DBG_PWD_HIGH_OFFSET (0x8) +#define EF_DATA_0_EF_DBG_PWD_HIGH EF_DATA_0_EF_DBG_PWD_HIGH +#define EF_DATA_0_EF_DBG_PWD_HIGH_POS (0U) +#define EF_DATA_0_EF_DBG_PWD_HIGH_LEN (32U) +#define EF_DATA_0_EF_DBG_PWD_HIGH_MSK (((1U << EF_DATA_0_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_HIGH_POS) +#define EF_DATA_0_EF_DBG_PWD_HIGH_UMSK (~(((1U << EF_DATA_0_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_HIGH_POS)) + +/* 0xC : ef_ana_trim_0 */ +#define EF_DATA_0_EF_ANA_TRIM_0_OFFSET (0xC) +#define EF_DATA_0_EF_ANA_TRIM_0 EF_DATA_0_EF_ANA_TRIM_0 +#define EF_DATA_0_EF_ANA_TRIM_0_POS (0U) +#define EF_DATA_0_EF_ANA_TRIM_0_LEN (32U) +#define EF_DATA_0_EF_ANA_TRIM_0_MSK (((1U << EF_DATA_0_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_0_POS) +#define EF_DATA_0_EF_ANA_TRIM_0_UMSK (~(((1U << EF_DATA_0_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_0_POS)) + +/* 0x10 : ef_sw_usage_0 */ +#define EF_DATA_0_EF_SW_USAGE_0_OFFSET (0x10) +#define EF_DATA_0_EF_SW_USAGE_0 EF_DATA_0_EF_SW_USAGE_0 +#define EF_DATA_0_EF_SW_USAGE_0_POS (0U) +#define EF_DATA_0_EF_SW_USAGE_0_LEN (32U) +#define EF_DATA_0_EF_SW_USAGE_0_MSK (((1U << EF_DATA_0_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_0_POS) +#define EF_DATA_0_EF_SW_USAGE_0_UMSK (~(((1U << EF_DATA_0_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_0_POS)) + +/* 0x14 : ef_wifi_mac_low */ +#define EF_DATA_0_EF_WIFI_MAC_LOW_OFFSET (0x14) +#define EF_DATA_0_EF_WIFI_MAC_LOW EF_DATA_0_EF_WIFI_MAC_LOW +#define EF_DATA_0_EF_WIFI_MAC_LOW_POS (0U) +#define EF_DATA_0_EF_WIFI_MAC_LOW_LEN (32U) +#define EF_DATA_0_EF_WIFI_MAC_LOW_MSK (((1U << EF_DATA_0_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_LOW_POS) +#define EF_DATA_0_EF_WIFI_MAC_LOW_UMSK (~(((1U << EF_DATA_0_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_LOW_POS)) + +/* 0x18 : ef_wifi_mac_high */ +#define EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET (0x18) +#define EF_DATA_0_EF_WIFI_MAC_HIGH EF_DATA_0_EF_WIFI_MAC_HIGH +#define EF_DATA_0_EF_WIFI_MAC_HIGH_POS (0U) +#define EF_DATA_0_EF_WIFI_MAC_HIGH_LEN (32U) +#define EF_DATA_0_EF_WIFI_MAC_HIGH_MSK (((1U << EF_DATA_0_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_HIGH_POS) +#define EF_DATA_0_EF_WIFI_MAC_HIGH_UMSK (~(((1U << EF_DATA_0_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_HIGH_POS)) + +/* 0x1C : ef_key_slot_0_w0 */ +#define EF_DATA_0_EF_KEY_SLOT_0_W0_OFFSET (0x1C) +#define EF_DATA_0_EF_KEY_SLOT_0_W0 EF_DATA_0_EF_KEY_SLOT_0_W0 +#define EF_DATA_0_EF_KEY_SLOT_0_W0_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_0_W0_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_0_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W0_POS) +#define EF_DATA_0_EF_KEY_SLOT_0_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W0_POS)) + +/* 0x20 : ef_key_slot_0_w1 */ +#define EF_DATA_0_EF_KEY_SLOT_0_W1_OFFSET (0x20) +#define EF_DATA_0_EF_KEY_SLOT_0_W1 EF_DATA_0_EF_KEY_SLOT_0_W1 +#define EF_DATA_0_EF_KEY_SLOT_0_W1_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_0_W1_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_0_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W1_POS) +#define EF_DATA_0_EF_KEY_SLOT_0_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W1_POS)) + +/* 0x24 : ef_key_slot_0_w2 */ +#define EF_DATA_0_EF_KEY_SLOT_0_W2_OFFSET (0x24) +#define EF_DATA_0_EF_KEY_SLOT_0_W2 EF_DATA_0_EF_KEY_SLOT_0_W2 +#define EF_DATA_0_EF_KEY_SLOT_0_W2_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_0_W2_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_0_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W2_POS) +#define EF_DATA_0_EF_KEY_SLOT_0_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W2_POS)) + +/* 0x28 : ef_key_slot_0_w3 */ +#define EF_DATA_0_EF_KEY_SLOT_0_W3_OFFSET (0x28) +#define EF_DATA_0_EF_KEY_SLOT_0_W3 EF_DATA_0_EF_KEY_SLOT_0_W3 +#define EF_DATA_0_EF_KEY_SLOT_0_W3_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_0_W3_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_0_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W3_POS) +#define EF_DATA_0_EF_KEY_SLOT_0_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W3_POS)) + +/* 0x2C : ef_key_slot_1_w0 */ +#define EF_DATA_0_EF_KEY_SLOT_1_W0_OFFSET (0x2C) +#define EF_DATA_0_EF_KEY_SLOT_1_W0 EF_DATA_0_EF_KEY_SLOT_1_W0 +#define EF_DATA_0_EF_KEY_SLOT_1_W0_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_1_W0_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_1_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W0_POS) +#define EF_DATA_0_EF_KEY_SLOT_1_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W0_POS)) + +/* 0x30 : ef_key_slot_1_w1 */ +#define EF_DATA_0_EF_KEY_SLOT_1_W1_OFFSET (0x30) +#define EF_DATA_0_EF_KEY_SLOT_1_W1 EF_DATA_0_EF_KEY_SLOT_1_W1 +#define EF_DATA_0_EF_KEY_SLOT_1_W1_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_1_W1_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_1_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W1_POS) +#define EF_DATA_0_EF_KEY_SLOT_1_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W1_POS)) + +/* 0x34 : ef_key_slot_1_w2 */ +#define EF_DATA_0_EF_KEY_SLOT_1_W2_OFFSET (0x34) +#define EF_DATA_0_EF_KEY_SLOT_1_W2 EF_DATA_0_EF_KEY_SLOT_1_W2 +#define EF_DATA_0_EF_KEY_SLOT_1_W2_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_1_W2_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_1_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W2_POS) +#define EF_DATA_0_EF_KEY_SLOT_1_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W2_POS)) + +/* 0x38 : ef_key_slot_1_w3 */ +#define EF_DATA_0_EF_KEY_SLOT_1_W3_OFFSET (0x38) +#define EF_DATA_0_EF_KEY_SLOT_1_W3 EF_DATA_0_EF_KEY_SLOT_1_W3 +#define EF_DATA_0_EF_KEY_SLOT_1_W3_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_1_W3_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_1_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W3_POS) +#define EF_DATA_0_EF_KEY_SLOT_1_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W3_POS)) + +/* 0x3C : ef_key_slot_2_w0 */ +#define EF_DATA_0_EF_KEY_SLOT_2_W0_OFFSET (0x3C) +#define EF_DATA_0_EF_KEY_SLOT_2_W0 EF_DATA_0_EF_KEY_SLOT_2_W0 +#define EF_DATA_0_EF_KEY_SLOT_2_W0_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_2_W0_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_2_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W0_POS) +#define EF_DATA_0_EF_KEY_SLOT_2_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W0_POS)) + +/* 0x40 : ef_key_slot_2_w1 */ +#define EF_DATA_0_EF_KEY_SLOT_2_W1_OFFSET (0x40) +#define EF_DATA_0_EF_KEY_SLOT_2_W1 EF_DATA_0_EF_KEY_SLOT_2_W1 +#define EF_DATA_0_EF_KEY_SLOT_2_W1_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_2_W1_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_2_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W1_POS) +#define EF_DATA_0_EF_KEY_SLOT_2_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W1_POS)) + +/* 0x44 : ef_key_slot_2_w2 */ +#define EF_DATA_0_EF_KEY_SLOT_2_W2_OFFSET (0x44) +#define EF_DATA_0_EF_KEY_SLOT_2_W2 EF_DATA_0_EF_KEY_SLOT_2_W2 +#define EF_DATA_0_EF_KEY_SLOT_2_W2_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_2_W2_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_2_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W2_POS) +#define EF_DATA_0_EF_KEY_SLOT_2_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W2_POS)) + +/* 0x48 : ef_key_slot_2_w3 */ +#define EF_DATA_0_EF_KEY_SLOT_2_W3_OFFSET (0x48) +#define EF_DATA_0_EF_KEY_SLOT_2_W3 EF_DATA_0_EF_KEY_SLOT_2_W3 +#define EF_DATA_0_EF_KEY_SLOT_2_W3_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_2_W3_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_2_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W3_POS) +#define EF_DATA_0_EF_KEY_SLOT_2_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W3_POS)) + +/* 0x4C : ef_key_slot_3_w0 */ +#define EF_DATA_0_EF_KEY_SLOT_3_W0_OFFSET (0x4C) +#define EF_DATA_0_EF_KEY_SLOT_3_W0 EF_DATA_0_EF_KEY_SLOT_3_W0 +#define EF_DATA_0_EF_KEY_SLOT_3_W0_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_3_W0_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_3_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W0_POS) +#define EF_DATA_0_EF_KEY_SLOT_3_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W0_POS)) + +/* 0x50 : ef_key_slot_3_w1 */ +#define EF_DATA_0_EF_KEY_SLOT_3_W1_OFFSET (0x50) +#define EF_DATA_0_EF_KEY_SLOT_3_W1 EF_DATA_0_EF_KEY_SLOT_3_W1 +#define EF_DATA_0_EF_KEY_SLOT_3_W1_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_3_W1_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_3_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W1_POS) +#define EF_DATA_0_EF_KEY_SLOT_3_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W1_POS)) + +/* 0x54 : ef_key_slot_3_w2 */ +#define EF_DATA_0_EF_KEY_SLOT_3_W2_OFFSET (0x54) +#define EF_DATA_0_EF_KEY_SLOT_3_W2 EF_DATA_0_EF_KEY_SLOT_3_W2 +#define EF_DATA_0_EF_KEY_SLOT_3_W2_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_3_W2_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_3_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W2_POS) +#define EF_DATA_0_EF_KEY_SLOT_3_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W2_POS)) + +/* 0x58 : ef_key_slot_3_w3 */ +#define EF_DATA_0_EF_KEY_SLOT_3_W3_OFFSET (0x58) +#define EF_DATA_0_EF_KEY_SLOT_3_W3 EF_DATA_0_EF_KEY_SLOT_3_W3 +#define EF_DATA_0_EF_KEY_SLOT_3_W3_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_3_W3_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_3_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W3_POS) +#define EF_DATA_0_EF_KEY_SLOT_3_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W3_POS)) + +/* 0x5C : ef_key_slot_4_w0 */ +#define EF_DATA_0_EF_KEY_SLOT_4_W0_OFFSET (0x5C) +#define EF_DATA_0_EF_KEY_SLOT_4_W0 EF_DATA_0_EF_KEY_SLOT_4_W0 +#define EF_DATA_0_EF_KEY_SLOT_4_W0_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_4_W0_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_4_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W0_POS) +#define EF_DATA_0_EF_KEY_SLOT_4_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W0_POS)) + +/* 0x60 : ef_key_slot_4_w1 */ +#define EF_DATA_0_EF_KEY_SLOT_4_W1_OFFSET (0x60) +#define EF_DATA_0_EF_KEY_SLOT_4_W1 EF_DATA_0_EF_KEY_SLOT_4_W1 +#define EF_DATA_0_EF_KEY_SLOT_4_W1_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_4_W1_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_4_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W1_POS) +#define EF_DATA_0_EF_KEY_SLOT_4_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W1_POS)) + +/* 0x64 : ef_key_slot_4_w2 */ +#define EF_DATA_0_EF_KEY_SLOT_4_W2_OFFSET (0x64) +#define EF_DATA_0_EF_KEY_SLOT_4_W2 EF_DATA_0_EF_KEY_SLOT_4_W2 +#define EF_DATA_0_EF_KEY_SLOT_4_W2_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_4_W2_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_4_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W2_POS) +#define EF_DATA_0_EF_KEY_SLOT_4_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W2_POS)) + +/* 0x68 : ef_key_slot_4_w3 */ +#define EF_DATA_0_EF_KEY_SLOT_4_W3_OFFSET (0x68) +#define EF_DATA_0_EF_KEY_SLOT_4_W3 EF_DATA_0_EF_KEY_SLOT_4_W3 +#define EF_DATA_0_EF_KEY_SLOT_4_W3_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_4_W3_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_4_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W3_POS) +#define EF_DATA_0_EF_KEY_SLOT_4_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W3_POS)) + +/* 0x6C : ef_key_slot_5_w0 */ +#define EF_DATA_0_EF_KEY_SLOT_5_W0_OFFSET (0x6C) +#define EF_DATA_0_EF_KEY_SLOT_5_W0 EF_DATA_0_EF_KEY_SLOT_5_W0 +#define EF_DATA_0_EF_KEY_SLOT_5_W0_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_5_W0_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_5_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W0_POS) +#define EF_DATA_0_EF_KEY_SLOT_5_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W0_POS)) + +/* 0x70 : ef_key_slot_5_w1 */ +#define EF_DATA_0_EF_KEY_SLOT_5_W1_OFFSET (0x70) +#define EF_DATA_0_EF_KEY_SLOT_5_W1 EF_DATA_0_EF_KEY_SLOT_5_W1 +#define EF_DATA_0_EF_KEY_SLOT_5_W1_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_5_W1_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_5_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W1_POS) +#define EF_DATA_0_EF_KEY_SLOT_5_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W1_POS)) + +/* 0x74 : ef_key_slot_5_w2 */ +#define EF_DATA_0_EF_KEY_SLOT_5_W2_OFFSET (0x74) +#define EF_DATA_0_EF_KEY_SLOT_5_W2 EF_DATA_0_EF_KEY_SLOT_5_W2 +#define EF_DATA_0_EF_KEY_SLOT_5_W2_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_5_W2_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_5_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W2_POS) +#define EF_DATA_0_EF_KEY_SLOT_5_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W2_POS)) + +/* 0x78 : ef_key_slot_5_w3 */ +#define EF_DATA_0_EF_KEY_SLOT_5_W3_OFFSET (0x78) +#define EF_DATA_0_EF_KEY_SLOT_5_W3 EF_DATA_0_EF_KEY_SLOT_5_W3 +#define EF_DATA_0_EF_KEY_SLOT_5_W3_POS (0U) +#define EF_DATA_0_EF_KEY_SLOT_5_W3_LEN (32U) +#define EF_DATA_0_EF_KEY_SLOT_5_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W3_POS) +#define EF_DATA_0_EF_KEY_SLOT_5_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W3_POS)) + +/* 0x7C : ef_data_0_lock */ +#define EF_DATA_0_LOCK_OFFSET (0x7C) +#define EF_DATA_0_EF_ANA_TRIM_1 EF_DATA_0_EF_ANA_TRIM_1 +#define EF_DATA_0_EF_ANA_TRIM_1_POS (0U) +#define EF_DATA_0_EF_ANA_TRIM_1_LEN (13U) +#define EF_DATA_0_EF_ANA_TRIM_1_MSK (((1U << EF_DATA_0_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_1_POS) +#define EF_DATA_0_EF_ANA_TRIM_1_UMSK (~(((1U << EF_DATA_0_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_1_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L EF_DATA_0_WR_LOCK_KEY_SLOT_4_L +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS (13U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L EF_DATA_0_WR_LOCK_KEY_SLOT_5_L +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS (14U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS)) +#define EF_DATA_0_WR_LOCK_BOOT_MODE EF_DATA_0_WR_LOCK_BOOT_MODE +#define EF_DATA_0_WR_LOCK_BOOT_MODE_POS (15U) +#define EF_DATA_0_WR_LOCK_BOOT_MODE_LEN (1U) +#define EF_DATA_0_WR_LOCK_BOOT_MODE_MSK (((1U << EF_DATA_0_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_0_WR_LOCK_BOOT_MODE_POS) +#define EF_DATA_0_WR_LOCK_BOOT_MODE_UMSK (~(((1U << EF_DATA_0_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_0_WR_LOCK_BOOT_MODE_POS)) +#define EF_DATA_0_WR_LOCK_DBG_PWD EF_DATA_0_WR_LOCK_DBG_PWD +#define EF_DATA_0_WR_LOCK_DBG_PWD_POS (16U) +#define EF_DATA_0_WR_LOCK_DBG_PWD_LEN (1U) +#define EF_DATA_0_WR_LOCK_DBG_PWD_MSK (((1U << EF_DATA_0_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_WR_LOCK_DBG_PWD_POS) +#define EF_DATA_0_WR_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_0_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_WR_LOCK_DBG_PWD_POS)) +#define EF_DATA_0_WR_LOCK_SW_USAGE_0 EF_DATA_0_WR_LOCK_SW_USAGE_0 +#define EF_DATA_0_WR_LOCK_SW_USAGE_0_POS (17U) +#define EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN (1U) +#define EF_DATA_0_WR_LOCK_SW_USAGE_0_MSK (((1U << EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_0_POS) +#define EF_DATA_0_WR_LOCK_SW_USAGE_0_UMSK (~(((1U << EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_0_POS)) +#define EF_DATA_0_WR_LOCK_WIFI_MAC EF_DATA_0_WR_LOCK_WIFI_MAC +#define EF_DATA_0_WR_LOCK_WIFI_MAC_POS (18U) +#define EF_DATA_0_WR_LOCK_WIFI_MAC_LEN (1U) +#define EF_DATA_0_WR_LOCK_WIFI_MAC_MSK (((1U << EF_DATA_0_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_0_WR_LOCK_WIFI_MAC_POS) +#define EF_DATA_0_WR_LOCK_WIFI_MAC_UMSK (~(((1U << EF_DATA_0_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_0_WR_LOCK_WIFI_MAC_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_0 EF_DATA_0_WR_LOCK_KEY_SLOT_0 +#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS (19U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_1 EF_DATA_0_WR_LOCK_KEY_SLOT_1 +#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS (20U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_2 EF_DATA_0_WR_LOCK_KEY_SLOT_2 +#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS (21U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_3 EF_DATA_0_WR_LOCK_KEY_SLOT_3 +#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS (22U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H EF_DATA_0_WR_LOCK_KEY_SLOT_4_H +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS (23U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS)) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H EF_DATA_0_WR_LOCK_KEY_SLOT_5_H +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS (24U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN (1U) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS) +#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS)) +#define EF_DATA_0_RD_LOCK_DBG_PWD EF_DATA_0_RD_LOCK_DBG_PWD +#define EF_DATA_0_RD_LOCK_DBG_PWD_POS (25U) +#define EF_DATA_0_RD_LOCK_DBG_PWD_LEN (1U) +#define EF_DATA_0_RD_LOCK_DBG_PWD_MSK (((1U << EF_DATA_0_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_RD_LOCK_DBG_PWD_POS) +#define EF_DATA_0_RD_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_0_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_RD_LOCK_DBG_PWD_POS)) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_0 EF_DATA_0_RD_LOCK_KEY_SLOT_0 +#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS (26U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN (1U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS)) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_1 EF_DATA_0_RD_LOCK_KEY_SLOT_1 +#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS (27U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN (1U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS)) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_2 EF_DATA_0_RD_LOCK_KEY_SLOT_2 +#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS (28U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN (1U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS)) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_3 EF_DATA_0_RD_LOCK_KEY_SLOT_3 +#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS (29U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN (1U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS)) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_4 EF_DATA_0_RD_LOCK_KEY_SLOT_4 +#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS (30U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN (1U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS)) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_5 EF_DATA_0_RD_LOCK_KEY_SLOT_5 +#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS (31U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN (1U) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS) +#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS)) + +struct ef_data_0_reg { + /* 0x0 : ef_cfg_0 */ + union { + struct + { + uint32_t ef_sf_aes_mode : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t ef_sboot_sign_mode : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t ef_sboot_en : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */ + uint32_t ef_cpu0_enc_en : 1; /* [ 7], r/w, 0x0 */ + uint32_t reserved_8_11 : 4; /* [11: 8], rsvd, 0x0 */ + uint32_t ef_sw_usage_1 : 2; /* [13:12], r/w, 0x0 */ + uint32_t rsvd0 : 1; /* [ 14], r/w, 0x0 */ + uint32_t rsvd1 : 1; /* [ 15], r/w, 0x0 */ + uint32_t rsvd2 : 1; /* [ 16], r/w, 0x0 */ + uint32_t ef_0_key_enc_en : 1; /* [ 17], r/w, 0x0 */ + uint32_t reserved_18 : 1; /* [ 18], rsvd, 0x0 */ + uint32_t rsvd3 : 1; /* [ 19], r/w, 0x0 */ + uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ + uint32_t rsvd4 : 1; /* [ 21], r/w, 0x0 */ + uint32_t rsvd5 : 1; /* [ 22], r/w, 0x0 */ + uint32_t rsvd6 : 1; /* [ 23], r/w, 0x0 */ + uint32_t reserved_24_25 : 2; /* [25:24], rsvd, 0x0 */ + uint32_t ef_dbg_jtag_0_dis : 2; /* [27:26], r/w, 0x0 */ + uint32_t ef_dbg_mode : 4; /* [31:28], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_cfg_0; + + /* 0x4 : ef_dbg_pwd_low */ + union { + struct + { + uint32_t ef_dbg_pwd_low : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_dbg_pwd_low; + + /* 0x8 : ef_dbg_pwd_high */ + union { + struct + { + uint32_t ef_dbg_pwd_high : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_dbg_pwd_high; + + /* 0xC : ef_ana_trim_0 */ + union { + struct + { + uint32_t ef_ana_trim_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_ana_trim_0; + + /* 0x10 : ef_sw_usage_0 */ + union { + struct + { + uint32_t ef_sw_usage_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_sw_usage_0; + + /* 0x14 : ef_wifi_mac_low */ + union { + struct + { + uint32_t ef_wifi_mac_low : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_wifi_mac_low; + + /* 0x18 : ef_wifi_mac_high */ + union { + struct + { + uint32_t ef_wifi_mac_high : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_wifi_mac_high; + + /* 0x1C : ef_key_slot_0_w0 */ + union { + struct + { + uint32_t ef_key_slot_0_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_0_w0; + + /* 0x20 : ef_key_slot_0_w1 */ + union { + struct + { + uint32_t ef_key_slot_0_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_0_w1; + + /* 0x24 : ef_key_slot_0_w2 */ + union { + struct + { + uint32_t ef_key_slot_0_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_0_w2; + + /* 0x28 : ef_key_slot_0_w3 */ + union { + struct + { + uint32_t ef_key_slot_0_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_0_w3; + + /* 0x2C : ef_key_slot_1_w0 */ + union { + struct + { + uint32_t ef_key_slot_1_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_1_w0; + + /* 0x30 : ef_key_slot_1_w1 */ + union { + struct + { + uint32_t ef_key_slot_1_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_1_w1; + + /* 0x34 : ef_key_slot_1_w2 */ + union { + struct + { + uint32_t ef_key_slot_1_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_1_w2; + + /* 0x38 : ef_key_slot_1_w3 */ + union { + struct + { + uint32_t ef_key_slot_1_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_1_w3; + + /* 0x3C : ef_key_slot_2_w0 */ + union { + struct + { + uint32_t ef_key_slot_2_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_2_w0; + + /* 0x40 : ef_key_slot_2_w1 */ + union { + struct + { + uint32_t ef_key_slot_2_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_2_w1; + + /* 0x44 : ef_key_slot_2_w2 */ + union { + struct + { + uint32_t ef_key_slot_2_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_2_w2; + + /* 0x48 : ef_key_slot_2_w3 */ + union { + struct + { + uint32_t ef_key_slot_2_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_2_w3; + + /* 0x4C : ef_key_slot_3_w0 */ + union { + struct + { + uint32_t ef_key_slot_3_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_3_w0; + + /* 0x50 : ef_key_slot_3_w1 */ + union { + struct + { + uint32_t ef_key_slot_3_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_3_w1; + + /* 0x54 : ef_key_slot_3_w2 */ + union { + struct + { + uint32_t ef_key_slot_3_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_3_w2; + + /* 0x58 : ef_key_slot_3_w3 */ + union { + struct + { + uint32_t ef_key_slot_3_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_3_w3; + + /* 0x5C : ef_key_slot_4_w0 */ + union { + struct + { + uint32_t ef_key_slot_4_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_4_w0; + + /* 0x60 : ef_key_slot_4_w1 */ + union { + struct + { + uint32_t ef_key_slot_4_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_4_w1; + + /* 0x64 : ef_key_slot_4_w2 */ + union { + struct + { + uint32_t ef_key_slot_4_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_4_w2; + + /* 0x68 : ef_key_slot_4_w3 */ + union { + struct + { + uint32_t ef_key_slot_4_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_4_w3; + + /* 0x6C : ef_key_slot_5_w0 */ + union { + struct + { + uint32_t ef_key_slot_5_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_5_w0; + + /* 0x70 : ef_key_slot_5_w1 */ + union { + struct + { + uint32_t ef_key_slot_5_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_5_w1; + + /* 0x74 : ef_key_slot_5_w2 */ + union { + struct + { + uint32_t ef_key_slot_5_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_5_w2; + + /* 0x78 : ef_key_slot_5_w3 */ + union { + struct + { + uint32_t ef_key_slot_5_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_5_w3; + + /* 0x7C : ef_data_0_lock */ + union { + struct + { + uint32_t ef_ana_trim_1 : 13; /* [12: 0], r/w, 0x0 */ + uint32_t wr_lock_key_slot_4_l : 1; /* [ 13], r/w, 0x0 */ + uint32_t wr_lock_key_slot_5_l : 1; /* [ 14], r/w, 0x0 */ + uint32_t wr_lock_boot_mode : 1; /* [ 15], r/w, 0x0 */ + uint32_t wr_lock_dbg_pwd : 1; /* [ 16], r/w, 0x0 */ + uint32_t wr_lock_sw_usage_0 : 1; /* [ 17], r/w, 0x0 */ + uint32_t wr_lock_wifi_mac : 1; /* [ 18], r/w, 0x0 */ + uint32_t wr_lock_key_slot_0 : 1; /* [ 19], r/w, 0x0 */ + uint32_t wr_lock_key_slot_1 : 1; /* [ 20], r/w, 0x0 */ + uint32_t wr_lock_key_slot_2 : 1; /* [ 21], r/w, 0x0 */ + uint32_t wr_lock_key_slot_3 : 1; /* [ 22], r/w, 0x0 */ + uint32_t wr_lock_key_slot_4_h : 1; /* [ 23], r/w, 0x0 */ + uint32_t wr_lock_key_slot_5_h : 1; /* [ 24], r/w, 0x0 */ + uint32_t rd_lock_dbg_pwd : 1; /* [ 25], r/w, 0x0 */ + uint32_t rd_lock_key_slot_0 : 1; /* [ 26], r/w, 0x0 */ + uint32_t rd_lock_key_slot_1 : 1; /* [ 27], r/w, 0x0 */ + uint32_t rd_lock_key_slot_2 : 1; /* [ 28], r/w, 0x0 */ + uint32_t rd_lock_key_slot_3 : 1; /* [ 29], r/w, 0x0 */ + uint32_t rd_lock_key_slot_4 : 1; /* [ 30], r/w, 0x0 */ + uint32_t rd_lock_key_slot_5 : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_data_0_lock; +}; + +typedef volatile struct ef_data_0_reg ef_data_0_reg_t; + +#endif /* __EF_DATA_0_REG_H__ */ diff --git a/drivers/soc/bl602/bl602_std/include/hardware/glb_reg.h b/drivers/soc/bl602/bl602_std/include/hardware/glb_reg.h new file mode 100644 index 00000000..f60cab64 --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/hardware/glb_reg.h @@ -0,0 +1,4094 @@ +/** + ****************************************************************************** + * @file glb_reg.h + * @version V1.2 + * @date 2020-04-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __GLB_REG_H__ +#define __GLB_REG_H__ + +#include "bl602.h" + +/* 0x0 : clk_cfg0 */ +#define GLB_CLK_CFG0_OFFSET (0x0) +#define GLB_REG_PLL_EN GLB_REG_PLL_EN +#define GLB_REG_PLL_EN_POS (0U) +#define GLB_REG_PLL_EN_LEN (1U) +#define GLB_REG_PLL_EN_MSK (((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS) +#define GLB_REG_PLL_EN_UMSK (~(((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS)) +#define GLB_REG_FCLK_EN GLB_REG_FCLK_EN +#define GLB_REG_FCLK_EN_POS (1U) +#define GLB_REG_FCLK_EN_LEN (1U) +#define GLB_REG_FCLK_EN_MSK (((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS) +#define GLB_REG_FCLK_EN_UMSK (~(((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS)) +#define GLB_REG_HCLK_EN GLB_REG_HCLK_EN +#define GLB_REG_HCLK_EN_POS (2U) +#define GLB_REG_HCLK_EN_LEN (1U) +#define GLB_REG_HCLK_EN_MSK (((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS) +#define GLB_REG_HCLK_EN_UMSK (~(((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS)) +#define GLB_REG_BCLK_EN GLB_REG_BCLK_EN +#define GLB_REG_BCLK_EN_POS (3U) +#define GLB_REG_BCLK_EN_LEN (1U) +#define GLB_REG_BCLK_EN_MSK (((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS) +#define GLB_REG_BCLK_EN_UMSK (~(((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS)) +#define GLB_REG_PLL_SEL GLB_REG_PLL_SEL +#define GLB_REG_PLL_SEL_POS (4U) +#define GLB_REG_PLL_SEL_LEN (2U) +#define GLB_REG_PLL_SEL_MSK (((1U << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS) +#define GLB_REG_PLL_SEL_UMSK (~(((1U << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS)) +#define GLB_HBN_ROOT_CLK_SEL GLB_HBN_ROOT_CLK_SEL +#define GLB_HBN_ROOT_CLK_SEL_POS (6U) +#define GLB_HBN_ROOT_CLK_SEL_LEN (2U) +#define GLB_HBN_ROOT_CLK_SEL_MSK (((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS) +#define GLB_HBN_ROOT_CLK_SEL_UMSK (~(((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS)) +#define GLB_REG_HCLK_DIV GLB_REG_HCLK_DIV +#define GLB_REG_HCLK_DIV_POS (8U) +#define GLB_REG_HCLK_DIV_LEN (8U) +#define GLB_REG_HCLK_DIV_MSK (((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS) +#define GLB_REG_HCLK_DIV_UMSK (~(((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS)) +#define GLB_REG_BCLK_DIV GLB_REG_BCLK_DIV +#define GLB_REG_BCLK_DIV_POS (16U) +#define GLB_REG_BCLK_DIV_LEN (8U) +#define GLB_REG_BCLK_DIV_MSK (((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS) +#define GLB_REG_BCLK_DIV_UMSK (~(((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS)) +#define GLB_FCLK_SW_STATE GLB_FCLK_SW_STATE +#define GLB_FCLK_SW_STATE_POS (24U) +#define GLB_FCLK_SW_STATE_LEN (3U) +#define GLB_FCLK_SW_STATE_MSK (((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS) +#define GLB_FCLK_SW_STATE_UMSK (~(((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS)) +#define GLB_CHIP_RDY GLB_CHIP_RDY +#define GLB_CHIP_RDY_POS (27U) +#define GLB_CHIP_RDY_LEN (1U) +#define GLB_CHIP_RDY_MSK (((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS) +#define GLB_CHIP_RDY_UMSK (~(((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS)) +#define GLB_ID GLB_ID +#define GLB_ID_POS (28U) +#define GLB_ID_LEN (4U) +#define GLB_ID_MSK (((1U << GLB_ID_LEN) - 1) << GLB_ID_POS) +#define GLB_ID_UMSK (~(((1U << GLB_ID_LEN) - 1) << GLB_ID_POS)) + +/* 0x4 : clk_cfg1 */ +#define GLB_CLK_CFG1_OFFSET (0x4) +#define GLB_WIFI_MAC_CORE_DIV GLB_WIFI_MAC_CORE_DIV +#define GLB_WIFI_MAC_CORE_DIV_POS (0U) +#define GLB_WIFI_MAC_CORE_DIV_LEN (4U) +#define GLB_WIFI_MAC_CORE_DIV_MSK (((1U << GLB_WIFI_MAC_CORE_DIV_LEN) - 1) << GLB_WIFI_MAC_CORE_DIV_POS) +#define GLB_WIFI_MAC_CORE_DIV_UMSK (~(((1U << GLB_WIFI_MAC_CORE_DIV_LEN) - 1) << GLB_WIFI_MAC_CORE_DIV_POS)) +#define GLB_WIFI_MAC_WT_DIV GLB_WIFI_MAC_WT_DIV +#define GLB_WIFI_MAC_WT_DIV_POS (4U) +#define GLB_WIFI_MAC_WT_DIV_LEN (4U) +#define GLB_WIFI_MAC_WT_DIV_MSK (((1U << GLB_WIFI_MAC_WT_DIV_LEN) - 1) << GLB_WIFI_MAC_WT_DIV_POS) +#define GLB_WIFI_MAC_WT_DIV_UMSK (~(((1U << GLB_WIFI_MAC_WT_DIV_LEN) - 1) << GLB_WIFI_MAC_WT_DIV_POS)) +#define GLB_BLE_CLK_SEL GLB_BLE_CLK_SEL +#define GLB_BLE_CLK_SEL_POS (16U) +#define GLB_BLE_CLK_SEL_LEN (6U) +#define GLB_BLE_CLK_SEL_MSK (((1U << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS) +#define GLB_BLE_CLK_SEL_UMSK (~(((1U << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS)) +#define GLB_BLE_EN GLB_BLE_EN +#define GLB_BLE_EN_POS (24U) +#define GLB_BLE_EN_LEN (1U) +#define GLB_BLE_EN_MSK (((1U << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS) +#define GLB_BLE_EN_UMSK (~(((1U << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS)) + +/* 0x8 : clk_cfg2 */ +#define GLB_CLK_CFG2_OFFSET (0x8) +#define GLB_UART_CLK_DIV GLB_UART_CLK_DIV +#define GLB_UART_CLK_DIV_POS (0U) +#define GLB_UART_CLK_DIV_LEN (3U) +#define GLB_UART_CLK_DIV_MSK (((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS) +#define GLB_UART_CLK_DIV_UMSK (~(((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS)) +#define GLB_UART_CLK_EN GLB_UART_CLK_EN +#define GLB_UART_CLK_EN_POS (4U) +#define GLB_UART_CLK_EN_LEN (1U) +#define GLB_UART_CLK_EN_MSK (((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS) +#define GLB_UART_CLK_EN_UMSK (~(((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS)) +#define GLB_HBN_UART_CLK_SEL GLB_HBN_UART_CLK_SEL +#define GLB_HBN_UART_CLK_SEL_POS (7U) +#define GLB_HBN_UART_CLK_SEL_LEN (1U) +#define GLB_HBN_UART_CLK_SEL_MSK (((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS) +#define GLB_HBN_UART_CLK_SEL_UMSK (~(((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS)) +#define GLB_SF_CLK_DIV GLB_SF_CLK_DIV +#define GLB_SF_CLK_DIV_POS (8U) +#define GLB_SF_CLK_DIV_LEN (3U) +#define GLB_SF_CLK_DIV_MSK (((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS) +#define GLB_SF_CLK_DIV_UMSK (~(((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS)) +#define GLB_SF_CLK_EN GLB_SF_CLK_EN +#define GLB_SF_CLK_EN_POS (11U) +#define GLB_SF_CLK_EN_LEN (1U) +#define GLB_SF_CLK_EN_MSK (((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS) +#define GLB_SF_CLK_EN_UMSK (~(((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS)) +#define GLB_SF_CLK_SEL GLB_SF_CLK_SEL +#define GLB_SF_CLK_SEL_POS (12U) +#define GLB_SF_CLK_SEL_LEN (2U) +#define GLB_SF_CLK_SEL_MSK (((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS) +#define GLB_SF_CLK_SEL_UMSK (~(((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS)) +#define GLB_SF_CLK_SEL2 GLB_SF_CLK_SEL2 +#define GLB_SF_CLK_SEL2_POS (14U) +#define GLB_SF_CLK_SEL2_LEN (2U) +#define GLB_SF_CLK_SEL2_MSK (((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS) +#define GLB_SF_CLK_SEL2_UMSK (~(((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS)) +#define GLB_IR_CLK_DIV GLB_IR_CLK_DIV +#define GLB_IR_CLK_DIV_POS (16U) +#define GLB_IR_CLK_DIV_LEN (6U) +#define GLB_IR_CLK_DIV_MSK (((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS) +#define GLB_IR_CLK_DIV_UMSK (~(((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS)) +#define GLB_IR_CLK_EN GLB_IR_CLK_EN +#define GLB_IR_CLK_EN_POS (23U) +#define GLB_IR_CLK_EN_LEN (1U) +#define GLB_IR_CLK_EN_MSK (((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS) +#define GLB_IR_CLK_EN_UMSK (~(((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS)) +#define GLB_DMA_CLK_EN GLB_DMA_CLK_EN +#define GLB_DMA_CLK_EN_POS (24U) +#define GLB_DMA_CLK_EN_LEN (8U) +#define GLB_DMA_CLK_EN_MSK (((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS) +#define GLB_DMA_CLK_EN_UMSK (~(((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS)) + +/* 0xC : clk_cfg3 */ +#define GLB_CLK_CFG3_OFFSET (0xC) +#define GLB_SPI_CLK_DIV GLB_SPI_CLK_DIV +#define GLB_SPI_CLK_DIV_POS (0U) +#define GLB_SPI_CLK_DIV_LEN (5U) +#define GLB_SPI_CLK_DIV_MSK (((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS) +#define GLB_SPI_CLK_DIV_UMSK (~(((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS)) +#define GLB_SPI_CLK_EN GLB_SPI_CLK_EN +#define GLB_SPI_CLK_EN_POS (8U) +#define GLB_SPI_CLK_EN_LEN (1U) +#define GLB_SPI_CLK_EN_MSK (((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS) +#define GLB_SPI_CLK_EN_UMSK (~(((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS)) +#define GLB_I2C_CLK_DIV GLB_I2C_CLK_DIV +#define GLB_I2C_CLK_DIV_POS (16U) +#define GLB_I2C_CLK_DIV_LEN (8U) +#define GLB_I2C_CLK_DIV_MSK (((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS) +#define GLB_I2C_CLK_DIV_UMSK (~(((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS)) +#define GLB_I2C_CLK_EN GLB_I2C_CLK_EN +#define GLB_I2C_CLK_EN_POS (24U) +#define GLB_I2C_CLK_EN_LEN (1U) +#define GLB_I2C_CLK_EN_MSK (((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS) +#define GLB_I2C_CLK_EN_UMSK (~(((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS)) + +/* 0x10 : swrst_cfg0 */ +#define GLB_SWRST_CFG0_OFFSET (0x10) +#define GLB_SWRST_S00 GLB_SWRST_S00 +#define GLB_SWRST_S00_POS (0U) +#define GLB_SWRST_S00_LEN (1U) +#define GLB_SWRST_S00_MSK (((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS) +#define GLB_SWRST_S00_UMSK (~(((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS)) +#define GLB_SWRST_S01 GLB_SWRST_S01 +#define GLB_SWRST_S01_POS (1U) +#define GLB_SWRST_S01_LEN (1U) +#define GLB_SWRST_S01_MSK (((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS) +#define GLB_SWRST_S01_UMSK (~(((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS)) +#define GLB_SWRST_S20 GLB_SWRST_S20 +#define GLB_SWRST_S20_POS (4U) +#define GLB_SWRST_S20_LEN (1U) +#define GLB_SWRST_S20_MSK (((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS) +#define GLB_SWRST_S20_UMSK (~(((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS)) +#define GLB_SWRST_S30 GLB_SWRST_S30 +#define GLB_SWRST_S30_POS (8U) +#define GLB_SWRST_S30_LEN (1U) +#define GLB_SWRST_S30_MSK (((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS) +#define GLB_SWRST_S30_UMSK (~(((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS)) + +/* 0x14 : swrst_cfg1 */ +#define GLB_SWRST_CFG1_OFFSET (0x14) +#define GLB_SWRST_S10 GLB_SWRST_S10 +#define GLB_SWRST_S10_POS (0U) +#define GLB_SWRST_S10_LEN (1U) +#define GLB_SWRST_S10_MSK (((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS) +#define GLB_SWRST_S10_UMSK (~(((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS)) +#define GLB_SWRST_S11 GLB_SWRST_S11 +#define GLB_SWRST_S11_POS (1U) +#define GLB_SWRST_S11_LEN (1U) +#define GLB_SWRST_S11_MSK (((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS) +#define GLB_SWRST_S11_UMSK (~(((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS)) +#define GLB_SWRST_S12 GLB_SWRST_S12 +#define GLB_SWRST_S12_POS (2U) +#define GLB_SWRST_S12_LEN (1U) +#define GLB_SWRST_S12_MSK (((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS) +#define GLB_SWRST_S12_UMSK (~(((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS)) +#define GLB_SWRST_S13 GLB_SWRST_S13 +#define GLB_SWRST_S13_POS (3U) +#define GLB_SWRST_S13_LEN (1U) +#define GLB_SWRST_S13_MSK (((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS) +#define GLB_SWRST_S13_UMSK (~(((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS)) +#define GLB_SWRST_S14 GLB_SWRST_S14 +#define GLB_SWRST_S14_POS (4U) +#define GLB_SWRST_S14_LEN (1U) +#define GLB_SWRST_S14_MSK (((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS) +#define GLB_SWRST_S14_UMSK (~(((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS)) +#define GLB_SWRST_S15 GLB_SWRST_S15 +#define GLB_SWRST_S15_POS (5U) +#define GLB_SWRST_S15_LEN (1U) +#define GLB_SWRST_S15_MSK (((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS) +#define GLB_SWRST_S15_UMSK (~(((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS)) +#define GLB_SWRST_S16 GLB_SWRST_S16 +#define GLB_SWRST_S16_POS (6U) +#define GLB_SWRST_S16_LEN (1U) +#define GLB_SWRST_S16_MSK (((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS) +#define GLB_SWRST_S16_UMSK (~(((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS)) +#define GLB_SWRST_S17 GLB_SWRST_S17 +#define GLB_SWRST_S17_POS (7U) +#define GLB_SWRST_S17_LEN (1U) +#define GLB_SWRST_S17_MSK (((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS) +#define GLB_SWRST_S17_UMSK (~(((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS)) +#define GLB_SWRST_S18 GLB_SWRST_S18 +#define GLB_SWRST_S18_POS (8U) +#define GLB_SWRST_S18_LEN (1U) +#define GLB_SWRST_S18_MSK (((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS) +#define GLB_SWRST_S18_UMSK (~(((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS)) +#define GLB_SWRST_S19 GLB_SWRST_S19 +#define GLB_SWRST_S19_POS (9U) +#define GLB_SWRST_S19_LEN (1U) +#define GLB_SWRST_S19_MSK (((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS) +#define GLB_SWRST_S19_UMSK (~(((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS)) +#define GLB_SWRST_S1A GLB_SWRST_S1A +#define GLB_SWRST_S1A_POS (10U) +#define GLB_SWRST_S1A_LEN (1U) +#define GLB_SWRST_S1A_MSK (((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS) +#define GLB_SWRST_S1A_UMSK (~(((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS)) +#define GLB_SWRST_S1B GLB_SWRST_S1B +#define GLB_SWRST_S1B_POS (11U) +#define GLB_SWRST_S1B_LEN (1U) +#define GLB_SWRST_S1B_MSK (((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS) +#define GLB_SWRST_S1B_UMSK (~(((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS)) +#define GLB_SWRST_S1C GLB_SWRST_S1C +#define GLB_SWRST_S1C_POS (12U) +#define GLB_SWRST_S1C_LEN (1U) +#define GLB_SWRST_S1C_MSK (((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS) +#define GLB_SWRST_S1C_UMSK (~(((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS)) +#define GLB_SWRST_S1D GLB_SWRST_S1D +#define GLB_SWRST_S1D_POS (13U) +#define GLB_SWRST_S1D_LEN (1U) +#define GLB_SWRST_S1D_MSK (((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS) +#define GLB_SWRST_S1D_UMSK (~(((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS)) +#define GLB_SWRST_S1E GLB_SWRST_S1E +#define GLB_SWRST_S1E_POS (14U) +#define GLB_SWRST_S1E_LEN (1U) +#define GLB_SWRST_S1E_MSK (((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS) +#define GLB_SWRST_S1E_UMSK (~(((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS)) +#define GLB_SWRST_S1F GLB_SWRST_S1F +#define GLB_SWRST_S1F_POS (15U) +#define GLB_SWRST_S1F_LEN (1U) +#define GLB_SWRST_S1F_MSK (((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS) +#define GLB_SWRST_S1F_UMSK (~(((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS)) +#define GLB_SWRST_S1A0 GLB_SWRST_S1A0 +#define GLB_SWRST_S1A0_POS (16U) +#define GLB_SWRST_S1A0_LEN (1U) +#define GLB_SWRST_S1A0_MSK (((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS) +#define GLB_SWRST_S1A0_UMSK (~(((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS)) +#define GLB_SWRST_S1A1 GLB_SWRST_S1A1 +#define GLB_SWRST_S1A1_POS (17U) +#define GLB_SWRST_S1A1_LEN (1U) +#define GLB_SWRST_S1A1_MSK (((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS) +#define GLB_SWRST_S1A1_UMSK (~(((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS)) +#define GLB_SWRST_S1A2 GLB_SWRST_S1A2 +#define GLB_SWRST_S1A2_POS (18U) +#define GLB_SWRST_S1A2_LEN (1U) +#define GLB_SWRST_S1A2_MSK (((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS) +#define GLB_SWRST_S1A2_UMSK (~(((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS)) +#define GLB_SWRST_S1A3 GLB_SWRST_S1A3 +#define GLB_SWRST_S1A3_POS (19U) +#define GLB_SWRST_S1A3_LEN (1U) +#define GLB_SWRST_S1A3_MSK (((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS) +#define GLB_SWRST_S1A3_UMSK (~(((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS)) +#define GLB_SWRST_S1A4 GLB_SWRST_S1A4 +#define GLB_SWRST_S1A4_POS (20U) +#define GLB_SWRST_S1A4_LEN (1U) +#define GLB_SWRST_S1A4_MSK (((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS) +#define GLB_SWRST_S1A4_UMSK (~(((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS)) +#define GLB_SWRST_S1A5 GLB_SWRST_S1A5 +#define GLB_SWRST_S1A5_POS (21U) +#define GLB_SWRST_S1A5_LEN (1U) +#define GLB_SWRST_S1A5_MSK (((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS) +#define GLB_SWRST_S1A5_UMSK (~(((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS)) +#define GLB_SWRST_S1A6 GLB_SWRST_S1A6 +#define GLB_SWRST_S1A6_POS (22U) +#define GLB_SWRST_S1A6_LEN (1U) +#define GLB_SWRST_S1A6_MSK (((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS) +#define GLB_SWRST_S1A6_UMSK (~(((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS)) +#define GLB_SWRST_S1A7 GLB_SWRST_S1A7 +#define GLB_SWRST_S1A7_POS (23U) +#define GLB_SWRST_S1A7_LEN (1U) +#define GLB_SWRST_S1A7_MSK (((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS) +#define GLB_SWRST_S1A7_UMSK (~(((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS)) + +/* 0x18 : swrst_cfg2 */ +#define GLB_SWRST_CFG2_OFFSET (0x18) +#define GLB_REG_CTRL_PWRON_RST GLB_REG_CTRL_PWRON_RST +#define GLB_REG_CTRL_PWRON_RST_POS (0U) +#define GLB_REG_CTRL_PWRON_RST_LEN (1U) +#define GLB_REG_CTRL_PWRON_RST_MSK (((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS) +#define GLB_REG_CTRL_PWRON_RST_UMSK (~(((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS)) +#define GLB_REG_CTRL_CPU_RESET GLB_REG_CTRL_CPU_RESET +#define GLB_REG_CTRL_CPU_RESET_POS (1U) +#define GLB_REG_CTRL_CPU_RESET_LEN (1U) +#define GLB_REG_CTRL_CPU_RESET_MSK (((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS) +#define GLB_REG_CTRL_CPU_RESET_UMSK (~(((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS)) +#define GLB_REG_CTRL_SYS_RESET GLB_REG_CTRL_SYS_RESET +#define GLB_REG_CTRL_SYS_RESET_POS (2U) +#define GLB_REG_CTRL_SYS_RESET_LEN (1U) +#define GLB_REG_CTRL_SYS_RESET_MSK (((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS) +#define GLB_REG_CTRL_SYS_RESET_UMSK (~(((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS)) +#define GLB_REG_CTRL_RESET_DUMMY GLB_REG_CTRL_RESET_DUMMY +#define GLB_REG_CTRL_RESET_DUMMY_POS (4U) +#define GLB_REG_CTRL_RESET_DUMMY_LEN (4U) +#define GLB_REG_CTRL_RESET_DUMMY_MSK (((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS) +#define GLB_REG_CTRL_RESET_DUMMY_UMSK (~(((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS)) +#define GLB_PKA_CLK_SEL GLB_PKA_CLK_SEL +#define GLB_PKA_CLK_SEL_POS (24U) +#define GLB_PKA_CLK_SEL_LEN (1U) +#define GLB_PKA_CLK_SEL_MSK (((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS) +#define GLB_PKA_CLK_SEL_UMSK (~(((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS)) + +/* 0x1C : swrst_cfg3 */ +#define GLB_SWRST_CFG3_OFFSET (0x1C) + +/* 0x20 : cgen_cfg0 */ +#define GLB_CGEN_CFG0_OFFSET (0x20) +#define GLB_CGEN_M GLB_CGEN_M +#define GLB_CGEN_M_POS (0U) +#define GLB_CGEN_M_LEN (8U) +#define GLB_CGEN_M_MSK (((1U << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS) +#define GLB_CGEN_M_UMSK (~(((1U << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS)) + +/* 0x24 : cgen_cfg1 */ +#define GLB_CGEN_CFG1_OFFSET (0x24) +#define GLB_CGEN_S1 GLB_CGEN_S1 +#define GLB_CGEN_S1_POS (0U) +#define GLB_CGEN_S1_LEN (16U) +#define GLB_CGEN_S1_MSK (((1U << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS) +#define GLB_CGEN_S1_UMSK (~(((1U << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS)) +#define GLB_CGEN_S1A GLB_CGEN_S1A +#define GLB_CGEN_S1A_POS (16U) +#define GLB_CGEN_S1A_LEN (8U) +#define GLB_CGEN_S1A_MSK (((1U << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS) +#define GLB_CGEN_S1A_UMSK (~(((1U << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS)) + +/* 0x28 : cgen_cfg2 */ +#define GLB_CGEN_CFG2_OFFSET (0x28) +#define GLB_CGEN_S2 GLB_CGEN_S2 +#define GLB_CGEN_S2_POS (0U) +#define GLB_CGEN_S2_LEN (1U) +#define GLB_CGEN_S2_MSK (((1U << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS) +#define GLB_CGEN_S2_UMSK (~(((1U << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS)) +#define GLB_CGEN_S3 GLB_CGEN_S3 +#define GLB_CGEN_S3_POS (4U) +#define GLB_CGEN_S3_LEN (1U) +#define GLB_CGEN_S3_MSK (((1U << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS) +#define GLB_CGEN_S3_UMSK (~(((1U << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS)) + +/* 0x2C : cgen_cfg3 */ +#define GLB_CGEN_CFG3_OFFSET (0x2C) + +/* 0x30 : MBIST_CTL */ +#define GLB_MBIST_CTL_OFFSET (0x30) +#define GLB_IROM_MBIST_MODE GLB_IROM_MBIST_MODE +#define GLB_IROM_MBIST_MODE_POS (0U) +#define GLB_IROM_MBIST_MODE_LEN (1U) +#define GLB_IROM_MBIST_MODE_MSK (((1U << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS) +#define GLB_IROM_MBIST_MODE_UMSK (~(((1U << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS)) +#define GLB_HSRAM_MBIST_MODE GLB_HSRAM_MBIST_MODE +#define GLB_HSRAM_MBIST_MODE_POS (1U) +#define GLB_HSRAM_MBIST_MODE_LEN (1U) +#define GLB_HSRAM_MBIST_MODE_MSK (((1U << GLB_HSRAM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MBIST_MODE_POS) +#define GLB_HSRAM_MBIST_MODE_UMSK (~(((1U << GLB_HSRAM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MBIST_MODE_POS)) +#define GLB_TAG_MBIST_MODE GLB_TAG_MBIST_MODE +#define GLB_TAG_MBIST_MODE_POS (2U) +#define GLB_TAG_MBIST_MODE_LEN (1U) +#define GLB_TAG_MBIST_MODE_MSK (((1U << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS) +#define GLB_TAG_MBIST_MODE_UMSK (~(((1U << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS)) +#define GLB_OCRAM_MBIST_MODE GLB_OCRAM_MBIST_MODE +#define GLB_OCRAM_MBIST_MODE_POS (3U) +#define GLB_OCRAM_MBIST_MODE_LEN (1U) +#define GLB_OCRAM_MBIST_MODE_MSK (((1U << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS) +#define GLB_OCRAM_MBIST_MODE_UMSK (~(((1U << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS)) +#define GLB_WIFI_MBIST_MODE GLB_WIFI_MBIST_MODE +#define GLB_WIFI_MBIST_MODE_POS (4U) +#define GLB_WIFI_MBIST_MODE_LEN (1U) +#define GLB_WIFI_MBIST_MODE_MSK (((1U << GLB_WIFI_MBIST_MODE_LEN) - 1) << GLB_WIFI_MBIST_MODE_POS) +#define GLB_WIFI_MBIST_MODE_UMSK (~(((1U << GLB_WIFI_MBIST_MODE_LEN) - 1) << GLB_WIFI_MBIST_MODE_POS)) +#define GLB_REG_MBIST_RST_N GLB_REG_MBIST_RST_N +#define GLB_REG_MBIST_RST_N_POS (31U) +#define GLB_REG_MBIST_RST_N_LEN (1U) +#define GLB_REG_MBIST_RST_N_MSK (((1U << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS) +#define GLB_REG_MBIST_RST_N_UMSK (~(((1U << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS)) + +/* 0x34 : MBIST_STAT */ +#define GLB_MBIST_STAT_OFFSET (0x34) +#define GLB_IROM_MBIST_DONE GLB_IROM_MBIST_DONE +#define GLB_IROM_MBIST_DONE_POS (0U) +#define GLB_IROM_MBIST_DONE_LEN (1U) +#define GLB_IROM_MBIST_DONE_MSK (((1U << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS) +#define GLB_IROM_MBIST_DONE_UMSK (~(((1U << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS)) +#define GLB_HSRAM_MBIST_DONE GLB_HSRAM_MBIST_DONE +#define GLB_HSRAM_MBIST_DONE_POS (1U) +#define GLB_HSRAM_MBIST_DONE_LEN (1U) +#define GLB_HSRAM_MBIST_DONE_MSK (((1U << GLB_HSRAM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MBIST_DONE_POS) +#define GLB_HSRAM_MBIST_DONE_UMSK (~(((1U << GLB_HSRAM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MBIST_DONE_POS)) +#define GLB_TAG_MBIST_DONE GLB_TAG_MBIST_DONE +#define GLB_TAG_MBIST_DONE_POS (2U) +#define GLB_TAG_MBIST_DONE_LEN (1U) +#define GLB_TAG_MBIST_DONE_MSK (((1U << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS) +#define GLB_TAG_MBIST_DONE_UMSK (~(((1U << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS)) +#define GLB_OCRAM_MBIST_DONE GLB_OCRAM_MBIST_DONE +#define GLB_OCRAM_MBIST_DONE_POS (3U) +#define GLB_OCRAM_MBIST_DONE_LEN (1U) +#define GLB_OCRAM_MBIST_DONE_MSK (((1U << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS) +#define GLB_OCRAM_MBIST_DONE_UMSK (~(((1U << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS)) +#define GLB_WIFI_MBIST_DONE GLB_WIFI_MBIST_DONE +#define GLB_WIFI_MBIST_DONE_POS (4U) +#define GLB_WIFI_MBIST_DONE_LEN (1U) +#define GLB_WIFI_MBIST_DONE_MSK (((1U << GLB_WIFI_MBIST_DONE_LEN) - 1) << GLB_WIFI_MBIST_DONE_POS) +#define GLB_WIFI_MBIST_DONE_UMSK (~(((1U << GLB_WIFI_MBIST_DONE_LEN) - 1) << GLB_WIFI_MBIST_DONE_POS)) +#define GLB_IROM_MBIST_FAIL GLB_IROM_MBIST_FAIL +#define GLB_IROM_MBIST_FAIL_POS (16U) +#define GLB_IROM_MBIST_FAIL_LEN (1U) +#define GLB_IROM_MBIST_FAIL_MSK (((1U << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS) +#define GLB_IROM_MBIST_FAIL_UMSK (~(((1U << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS)) +#define GLB_HSRAM_MBIST_FAIL GLB_HSRAM_MBIST_FAIL +#define GLB_HSRAM_MBIST_FAIL_POS (17U) +#define GLB_HSRAM_MBIST_FAIL_LEN (1U) +#define GLB_HSRAM_MBIST_FAIL_MSK (((1U << GLB_HSRAM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MBIST_FAIL_POS) +#define GLB_HSRAM_MBIST_FAIL_UMSK (~(((1U << GLB_HSRAM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MBIST_FAIL_POS)) +#define GLB_TAG_MBIST_FAIL GLB_TAG_MBIST_FAIL +#define GLB_TAG_MBIST_FAIL_POS (18U) +#define GLB_TAG_MBIST_FAIL_LEN (1U) +#define GLB_TAG_MBIST_FAIL_MSK (((1U << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS) +#define GLB_TAG_MBIST_FAIL_UMSK (~(((1U << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS)) +#define GLB_OCRAM_MBIST_FAIL GLB_OCRAM_MBIST_FAIL +#define GLB_OCRAM_MBIST_FAIL_POS (19U) +#define GLB_OCRAM_MBIST_FAIL_LEN (1U) +#define GLB_OCRAM_MBIST_FAIL_MSK (((1U << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS) +#define GLB_OCRAM_MBIST_FAIL_UMSK (~(((1U << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS)) +#define GLB_WIFI_MBIST_FAIL GLB_WIFI_MBIST_FAIL +#define GLB_WIFI_MBIST_FAIL_POS (20U) +#define GLB_WIFI_MBIST_FAIL_LEN (1U) +#define GLB_WIFI_MBIST_FAIL_MSK (((1U << GLB_WIFI_MBIST_FAIL_LEN) - 1) << GLB_WIFI_MBIST_FAIL_POS) +#define GLB_WIFI_MBIST_FAIL_UMSK (~(((1U << GLB_WIFI_MBIST_FAIL_LEN) - 1) << GLB_WIFI_MBIST_FAIL_POS)) + +/* 0x50 : bmx_cfg1 */ +#define GLB_BMX_CFG1_OFFSET (0x50) +#define GLB_BMX_TIMEOUT_EN GLB_BMX_TIMEOUT_EN +#define GLB_BMX_TIMEOUT_EN_POS (0U) +#define GLB_BMX_TIMEOUT_EN_LEN (4U) +#define GLB_BMX_TIMEOUT_EN_MSK (((1U << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS) +#define GLB_BMX_TIMEOUT_EN_UMSK (~(((1U << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS)) +#define GLB_BMX_ARB_MODE GLB_BMX_ARB_MODE +#define GLB_BMX_ARB_MODE_POS (4U) +#define GLB_BMX_ARB_MODE_LEN (2U) +#define GLB_BMX_ARB_MODE_MSK (((1U << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS) +#define GLB_BMX_ARB_MODE_UMSK (~(((1U << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS)) +#define GLB_BMX_ERR_EN GLB_BMX_ERR_EN +#define GLB_BMX_ERR_EN_POS (8U) +#define GLB_BMX_ERR_EN_LEN (1U) +#define GLB_BMX_ERR_EN_MSK (((1U << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS) +#define GLB_BMX_ERR_EN_UMSK (~(((1U << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS)) +#define GLB_BMX_BUSY_OPTION_DIS GLB_BMX_BUSY_OPTION_DIS +#define GLB_BMX_BUSY_OPTION_DIS_POS (9U) +#define GLB_BMX_BUSY_OPTION_DIS_LEN (1U) +#define GLB_BMX_BUSY_OPTION_DIS_MSK (((1U << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS) +#define GLB_BMX_BUSY_OPTION_DIS_UMSK (~(((1U << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS)) +#define GLB_BMX_GATING_DIS GLB_BMX_GATING_DIS +#define GLB_BMX_GATING_DIS_POS (10U) +#define GLB_BMX_GATING_DIS_LEN (1U) +#define GLB_BMX_GATING_DIS_MSK (((1U << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS) +#define GLB_BMX_GATING_DIS_UMSK (~(((1U << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS)) +#define GLB_HSEL_OPTION GLB_HSEL_OPTION +#define GLB_HSEL_OPTION_POS (12U) +#define GLB_HSEL_OPTION_LEN (4U) +#define GLB_HSEL_OPTION_MSK (((1U << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS) +#define GLB_HSEL_OPTION_UMSK (~(((1U << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS)) +#define GLB_PDS_APB_CFG GLB_PDS_APB_CFG +#define GLB_PDS_APB_CFG_POS (16U) +#define GLB_PDS_APB_CFG_LEN (8U) +#define GLB_PDS_APB_CFG_MSK (((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS) +#define GLB_PDS_APB_CFG_UMSK (~(((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS)) +#define GLB_HBN_APB_CFG GLB_HBN_APB_CFG +#define GLB_HBN_APB_CFG_POS (24U) +#define GLB_HBN_APB_CFG_LEN (8U) +#define GLB_HBN_APB_CFG_MSK (((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS) +#define GLB_HBN_APB_CFG_UMSK (~(((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS)) + +/* 0x54 : bmx_cfg2 */ +#define GLB_BMX_CFG2_OFFSET (0x54) +#define GLB_BMX_ERR_ADDR_DIS GLB_BMX_ERR_ADDR_DIS +#define GLB_BMX_ERR_ADDR_DIS_POS (0U) +#define GLB_BMX_ERR_ADDR_DIS_LEN (1U) +#define GLB_BMX_ERR_ADDR_DIS_MSK (((1U << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS) +#define GLB_BMX_ERR_ADDR_DIS_UMSK (~(((1U << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS)) +#define GLB_BMX_ERR_DEC GLB_BMX_ERR_DEC +#define GLB_BMX_ERR_DEC_POS (4U) +#define GLB_BMX_ERR_DEC_LEN (1U) +#define GLB_BMX_ERR_DEC_MSK (((1U << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS) +#define GLB_BMX_ERR_DEC_UMSK (~(((1U << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS)) +#define GLB_BMX_ERR_TZ GLB_BMX_ERR_TZ +#define GLB_BMX_ERR_TZ_POS (5U) +#define GLB_BMX_ERR_TZ_LEN (1U) +#define GLB_BMX_ERR_TZ_MSK (((1U << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS) +#define GLB_BMX_ERR_TZ_UMSK (~(((1U << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS)) +#define GLB_BMX_DBG_SEL GLB_BMX_DBG_SEL +#define GLB_BMX_DBG_SEL_POS (28U) +#define GLB_BMX_DBG_SEL_LEN (4U) +#define GLB_BMX_DBG_SEL_MSK (((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS) +#define GLB_BMX_DBG_SEL_UMSK (~(((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS)) + +/* 0x58 : bmx_err_addr */ +#define GLB_BMX_ERR_ADDR_OFFSET (0x58) +#define GLB_BMX_ERR_ADDR GLB_BMX_ERR_ADDR +#define GLB_BMX_ERR_ADDR_POS (0U) +#define GLB_BMX_ERR_ADDR_LEN (32U) +#define GLB_BMX_ERR_ADDR_MSK (((1U << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS) +#define GLB_BMX_ERR_ADDR_UMSK (~(((1U << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS)) + +/* 0x5C : bmx_dbg_out */ +#define GLB_BMX_DBG_OUT_OFFSET (0x5C) +#define GLB_BMX_DBG_OUT GLB_BMX_DBG_OUT +#define GLB_BMX_DBG_OUT_POS (0U) +#define GLB_BMX_DBG_OUT_LEN (32U) +#define GLB_BMX_DBG_OUT_MSK (((1U << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS) +#define GLB_BMX_DBG_OUT_UMSK (~(((1U << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS)) + +/* 0x60 : rsv0 */ +#define GLB_RSV0_OFFSET (0x60) + +/* 0x64 : rsv1 */ +#define GLB_RSV1_OFFSET (0x64) + +/* 0x68 : rsv2 */ +#define GLB_RSV2_OFFSET (0x68) + +/* 0x6C : rsv3 */ +#define GLB_RSV3_OFFSET (0x6C) + +/* 0x70 : sram_ret */ +#define GLB_SRAM_RET_OFFSET (0x70) +#define GLB_REG_SRAM_RET GLB_REG_SRAM_RET +#define GLB_REG_SRAM_RET_POS (0U) +#define GLB_REG_SRAM_RET_LEN (32U) +#define GLB_REG_SRAM_RET_MSK (((1U << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS) +#define GLB_REG_SRAM_RET_UMSK (~(((1U << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS)) + +/* 0x74 : sram_slp */ +#define GLB_SRAM_SLP_OFFSET (0x74) +#define GLB_REG_SRAM_SLP GLB_REG_SRAM_SLP +#define GLB_REG_SRAM_SLP_POS (0U) +#define GLB_REG_SRAM_SLP_LEN (32U) +#define GLB_REG_SRAM_SLP_MSK (((1U << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS) +#define GLB_REG_SRAM_SLP_UMSK (~(((1U << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS)) + +/* 0x78 : sram_parm */ +#define GLB_SRAM_PARM_OFFSET (0x78) +#define GLB_REG_SRAM_PARM GLB_REG_SRAM_PARM +#define GLB_REG_SRAM_PARM_POS (0U) +#define GLB_REG_SRAM_PARM_LEN (32U) +#define GLB_REG_SRAM_PARM_MSK (((1U << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS) +#define GLB_REG_SRAM_PARM_UMSK (~(((1U << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS)) + +/* 0x7C : seam_misc */ +#define GLB_SEAM_MISC_OFFSET (0x7C) +#define GLB_EM_SEL GLB_EM_SEL +#define GLB_EM_SEL_POS (0U) +#define GLB_EM_SEL_LEN (4U) +#define GLB_EM_SEL_MSK (((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS) +#define GLB_EM_SEL_UMSK (~(((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS)) + +/* 0x80 : glb_parm */ +#define GLB_PARM_OFFSET (0x80) +#define GLB_REG_BD_EN GLB_REG_BD_EN +#define GLB_REG_BD_EN_POS (0U) +#define GLB_REG_BD_EN_LEN (1U) +#define GLB_REG_BD_EN_MSK (((1U << GLB_REG_BD_EN_LEN) - 1) << GLB_REG_BD_EN_POS) +#define GLB_REG_BD_EN_UMSK (~(((1U << GLB_REG_BD_EN_LEN) - 1) << GLB_REG_BD_EN_POS)) +#define GLB_REG_EXT_RST_SMT GLB_REG_EXT_RST_SMT +#define GLB_REG_EXT_RST_SMT_POS (1U) +#define GLB_REG_EXT_RST_SMT_LEN (1U) +#define GLB_REG_EXT_RST_SMT_MSK (((1U << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS) +#define GLB_REG_EXT_RST_SMT_UMSK (~(((1U << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS)) +#define GLB_JTAG_SWAP_SET GLB_JTAG_SWAP_SET +#define GLB_JTAG_SWAP_SET_POS (2U) +#define GLB_JTAG_SWAP_SET_LEN (6U) +#define GLB_JTAG_SWAP_SET_MSK (((1U << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS) +#define GLB_JTAG_SWAP_SET_UMSK (~(((1U << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS)) +#define GLB_SWAP_SFLASH_IO_3_IO_0 GLB_SWAP_SFLASH_IO_3_IO_0 +#define GLB_SWAP_SFLASH_IO_3_IO_0_POS (8U) +#define GLB_SWAP_SFLASH_IO_3_IO_0_LEN (1U) +#define GLB_SWAP_SFLASH_IO_3_IO_0_MSK (((1U << GLB_SWAP_SFLASH_IO_3_IO_0_LEN) - 1) << GLB_SWAP_SFLASH_IO_3_IO_0_POS) +#define GLB_SWAP_SFLASH_IO_3_IO_0_UMSK (~(((1U << GLB_SWAP_SFLASH_IO_3_IO_0_LEN) - 1) << GLB_SWAP_SFLASH_IO_3_IO_0_POS)) +#define GLB_SEL_EMBEDDED_SFLASH GLB_SEL_EMBEDDED_SFLASH +#define GLB_SEL_EMBEDDED_SFLASH_POS (9U) +#define GLB_SEL_EMBEDDED_SFLASH_LEN (1U) +#define GLB_SEL_EMBEDDED_SFLASH_MSK (((1U << GLB_SEL_EMBEDDED_SFLASH_LEN) - 1) << GLB_SEL_EMBEDDED_SFLASH_POS) +#define GLB_SEL_EMBEDDED_SFLASH_UMSK (~(((1U << GLB_SEL_EMBEDDED_SFLASH_LEN) - 1) << GLB_SEL_EMBEDDED_SFLASH_POS)) +#define GLB_REG_SPI_0_MASTER_MODE GLB_REG_SPI_0_MASTER_MODE +#define GLB_REG_SPI_0_MASTER_MODE_POS (12U) +#define GLB_REG_SPI_0_MASTER_MODE_LEN (1U) +#define GLB_REG_SPI_0_MASTER_MODE_MSK (((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) << GLB_REG_SPI_0_MASTER_MODE_POS) +#define GLB_REG_SPI_0_MASTER_MODE_UMSK (~(((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) << GLB_REG_SPI_0_MASTER_MODE_POS)) +#define GLB_REG_SPI_0_SWAP GLB_REG_SPI_0_SWAP +#define GLB_REG_SPI_0_SWAP_POS (13U) +#define GLB_REG_SPI_0_SWAP_LEN (1U) +#define GLB_REG_SPI_0_SWAP_MSK (((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS) +#define GLB_REG_SPI_0_SWAP_UMSK (~(((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS)) +#define GLB_REG_CCI_USE_JTAG_PIN GLB_REG_CCI_USE_JTAG_PIN +#define GLB_REG_CCI_USE_JTAG_PIN_POS (15U) +#define GLB_REG_CCI_USE_JTAG_PIN_LEN (1U) +#define GLB_REG_CCI_USE_JTAG_PIN_MSK (((1U << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) << GLB_REG_CCI_USE_JTAG_PIN_POS) +#define GLB_REG_CCI_USE_JTAG_PIN_UMSK (~(((1U << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) << GLB_REG_CCI_USE_JTAG_PIN_POS)) +#define GLB_REG_CCI_USE_SDIO_PIN GLB_REG_CCI_USE_SDIO_PIN +#define GLB_REG_CCI_USE_SDIO_PIN_POS (16U) +#define GLB_REG_CCI_USE_SDIO_PIN_LEN (1U) +#define GLB_REG_CCI_USE_SDIO_PIN_MSK (((1U << GLB_REG_CCI_USE_SDIO_PIN_LEN) - 1) << GLB_REG_CCI_USE_SDIO_PIN_POS) +#define GLB_REG_CCI_USE_SDIO_PIN_UMSK (~(((1U << GLB_REG_CCI_USE_SDIO_PIN_LEN) - 1) << GLB_REG_CCI_USE_SDIO_PIN_POS)) +#define GLB_P1_ADC_TEST_WITH_CCI GLB_P1_ADC_TEST_WITH_CCI +#define GLB_P1_ADC_TEST_WITH_CCI_POS (17U) +#define GLB_P1_ADC_TEST_WITH_CCI_LEN (1U) +#define GLB_P1_ADC_TEST_WITH_CCI_MSK (((1U << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) << GLB_P1_ADC_TEST_WITH_CCI_POS) +#define GLB_P1_ADC_TEST_WITH_CCI_UMSK (~(((1U << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) << GLB_P1_ADC_TEST_WITH_CCI_POS)) +#define GLB_P2_DAC_TEST_WITH_CCI GLB_P2_DAC_TEST_WITH_CCI +#define GLB_P2_DAC_TEST_WITH_CCI_POS (18U) +#define GLB_P2_DAC_TEST_WITH_CCI_LEN (1U) +#define GLB_P2_DAC_TEST_WITH_CCI_MSK (((1U << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) << GLB_P2_DAC_TEST_WITH_CCI_POS) +#define GLB_P2_DAC_TEST_WITH_CCI_UMSK (~(((1U << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) << GLB_P2_DAC_TEST_WITH_CCI_POS)) +#define GLB_P3_CCI_USE_IO_2_5 GLB_P3_CCI_USE_IO_2_5 +#define GLB_P3_CCI_USE_IO_2_5_POS (19U) +#define GLB_P3_CCI_USE_IO_2_5_LEN (1U) +#define GLB_P3_CCI_USE_IO_2_5_MSK (((1U << GLB_P3_CCI_USE_IO_2_5_LEN) - 1) << GLB_P3_CCI_USE_IO_2_5_POS) +#define GLB_P3_CCI_USE_IO_2_5_UMSK (~(((1U << GLB_P3_CCI_USE_IO_2_5_LEN) - 1) << GLB_P3_CCI_USE_IO_2_5_POS)) +#define GLB_P4_ADC_TEST_WITH_JTAG GLB_P4_ADC_TEST_WITH_JTAG +#define GLB_P4_ADC_TEST_WITH_JTAG_POS (20U) +#define GLB_P4_ADC_TEST_WITH_JTAG_LEN (1U) +#define GLB_P4_ADC_TEST_WITH_JTAG_MSK (((1U << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) << GLB_P4_ADC_TEST_WITH_JTAG_POS) +#define GLB_P4_ADC_TEST_WITH_JTAG_UMSK (~(((1U << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) << GLB_P4_ADC_TEST_WITH_JTAG_POS)) +#define GLB_P5_DAC_TEST_WITH_JTAG GLB_P5_DAC_TEST_WITH_JTAG +#define GLB_P5_DAC_TEST_WITH_JTAG_POS (21U) +#define GLB_P5_DAC_TEST_WITH_JTAG_LEN (1U) +#define GLB_P5_DAC_TEST_WITH_JTAG_MSK (((1U << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) << GLB_P5_DAC_TEST_WITH_JTAG_POS) +#define GLB_P5_DAC_TEST_WITH_JTAG_UMSK (~(((1U << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) << GLB_P5_DAC_TEST_WITH_JTAG_POS)) +#define GLB_P6_SDIO_USE_IO_0_5 GLB_P6_SDIO_USE_IO_0_5 +#define GLB_P6_SDIO_USE_IO_0_5_POS (22U) +#define GLB_P6_SDIO_USE_IO_0_5_LEN (1U) +#define GLB_P6_SDIO_USE_IO_0_5_MSK (((1U << GLB_P6_SDIO_USE_IO_0_5_LEN) - 1) << GLB_P6_SDIO_USE_IO_0_5_POS) +#define GLB_P6_SDIO_USE_IO_0_5_UMSK (~(((1U << GLB_P6_SDIO_USE_IO_0_5_LEN) - 1) << GLB_P6_SDIO_USE_IO_0_5_POS)) +#define GLB_P7_JTAG_USE_IO_2_5 GLB_P7_JTAG_USE_IO_2_5 +#define GLB_P7_JTAG_USE_IO_2_5_POS (23U) +#define GLB_P7_JTAG_USE_IO_2_5_LEN (1U) +#define GLB_P7_JTAG_USE_IO_2_5_MSK (((1U << GLB_P7_JTAG_USE_IO_2_5_LEN) - 1) << GLB_P7_JTAG_USE_IO_2_5_POS) +#define GLB_P7_JTAG_USE_IO_2_5_UMSK (~(((1U << GLB_P7_JTAG_USE_IO_2_5_LEN) - 1) << GLB_P7_JTAG_USE_IO_2_5_POS)) +#define GLB_UART_SWAP_SET GLB_UART_SWAP_SET +#define GLB_UART_SWAP_SET_POS (24U) +#define GLB_UART_SWAP_SET_LEN (3U) +#define GLB_UART_SWAP_SET_MSK (((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS) +#define GLB_UART_SWAP_SET_UMSK (~(((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS)) + +/* 0x90 : CPU_CLK_CFG */ +#define GLB_CPU_CLK_CFG_OFFSET (0x90) +#define GLB_CPU_RTC_DIV GLB_CPU_RTC_DIV +#define GLB_CPU_RTC_DIV_POS (0U) +#define GLB_CPU_RTC_DIV_LEN (17U) +#define GLB_CPU_RTC_DIV_MSK (((1U << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS) +#define GLB_CPU_RTC_DIV_UMSK (~(((1U << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS)) +#define GLB_CPU_RTC_EN GLB_CPU_RTC_EN +#define GLB_CPU_RTC_EN_POS (18U) +#define GLB_CPU_RTC_EN_LEN (1U) +#define GLB_CPU_RTC_EN_MSK (((1U << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS) +#define GLB_CPU_RTC_EN_UMSK (~(((1U << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS)) +#define GLB_CPU_RTC_SEL GLB_CPU_RTC_SEL +#define GLB_CPU_RTC_SEL_POS (19U) +#define GLB_CPU_RTC_SEL_LEN (1U) +#define GLB_CPU_RTC_SEL_MSK (((1U << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS) +#define GLB_CPU_RTC_SEL_UMSK (~(((1U << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS)) +#define GLB_DEBUG_NDRESET_GATE GLB_DEBUG_NDRESET_GATE +#define GLB_DEBUG_NDRESET_GATE_POS (20U) +#define GLB_DEBUG_NDRESET_GATE_LEN (1U) +#define GLB_DEBUG_NDRESET_GATE_MSK (((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS) +#define GLB_DEBUG_NDRESET_GATE_UMSK (~(((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS)) + +/* 0xA4 : GPADC_32M_SRC_CTRL */ +#define GLB_GPADC_32M_SRC_CTRL_OFFSET (0xA4) +#define GLB_GPADC_32M_CLK_DIV GLB_GPADC_32M_CLK_DIV +#define GLB_GPADC_32M_CLK_DIV_POS (0U) +#define GLB_GPADC_32M_CLK_DIV_LEN (6U) +#define GLB_GPADC_32M_CLK_DIV_MSK (((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS) +#define GLB_GPADC_32M_CLK_DIV_UMSK (~(((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS)) +#define GLB_GPADC_32M_CLK_SEL GLB_GPADC_32M_CLK_SEL +#define GLB_GPADC_32M_CLK_SEL_POS (7U) +#define GLB_GPADC_32M_CLK_SEL_LEN (1U) +#define GLB_GPADC_32M_CLK_SEL_MSK (((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS) +#define GLB_GPADC_32M_CLK_SEL_UMSK (~(((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS)) +#define GLB_GPADC_32M_DIV_EN GLB_GPADC_32M_DIV_EN +#define GLB_GPADC_32M_DIV_EN_POS (8U) +#define GLB_GPADC_32M_DIV_EN_LEN (1U) +#define GLB_GPADC_32M_DIV_EN_MSK (((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS) +#define GLB_GPADC_32M_DIV_EN_UMSK (~(((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS)) + +/* 0xA8 : DIG32K_WAKEUP_CTRL */ +#define GLB_DIG32K_WAKEUP_CTRL_OFFSET (0xA8) +#define GLB_DIG_32K_DIV GLB_DIG_32K_DIV +#define GLB_DIG_32K_DIV_POS (0U) +#define GLB_DIG_32K_DIV_LEN (11U) +#define GLB_DIG_32K_DIV_MSK (((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS) +#define GLB_DIG_32K_DIV_UMSK (~(((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS)) +#define GLB_DIG_32K_EN GLB_DIG_32K_EN +#define GLB_DIG_32K_EN_POS (12U) +#define GLB_DIG_32K_EN_LEN (1U) +#define GLB_DIG_32K_EN_MSK (((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS) +#define GLB_DIG_32K_EN_UMSK (~(((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS)) +#define GLB_DIG_32K_COMP GLB_DIG_32K_COMP +#define GLB_DIG_32K_COMP_POS (13U) +#define GLB_DIG_32K_COMP_LEN (1U) +#define GLB_DIG_32K_COMP_MSK (((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS) +#define GLB_DIG_32K_COMP_UMSK (~(((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS)) +#define GLB_DIG_512K_DIV GLB_DIG_512K_DIV +#define GLB_DIG_512K_DIV_POS (16U) +#define GLB_DIG_512K_DIV_LEN (7U) +#define GLB_DIG_512K_DIV_MSK (((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS) +#define GLB_DIG_512K_DIV_UMSK (~(((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS)) +#define GLB_DIG_512K_EN GLB_DIG_512K_EN +#define GLB_DIG_512K_EN_POS (24U) +#define GLB_DIG_512K_EN_LEN (1U) +#define GLB_DIG_512K_EN_MSK (((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS) +#define GLB_DIG_512K_EN_UMSK (~(((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS)) +#define GLB_DIG_512K_COMP GLB_DIG_512K_COMP +#define GLB_DIG_512K_COMP_POS (25U) +#define GLB_DIG_512K_COMP_LEN (1U) +#define GLB_DIG_512K_COMP_MSK (((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS) +#define GLB_DIG_512K_COMP_UMSK (~(((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS)) +#define GLB_DIG_CLK_SRC_SEL GLB_DIG_CLK_SRC_SEL +#define GLB_DIG_CLK_SRC_SEL_POS (28U) +#define GLB_DIG_CLK_SRC_SEL_LEN (1U) +#define GLB_DIG_CLK_SRC_SEL_MSK (((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS) +#define GLB_DIG_CLK_SRC_SEL_UMSK (~(((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS)) +#define GLB_REG_EN_PLATFORM_WAKEUP GLB_REG_EN_PLATFORM_WAKEUP +#define GLB_REG_EN_PLATFORM_WAKEUP_POS (31U) +#define GLB_REG_EN_PLATFORM_WAKEUP_LEN (1U) +#define GLB_REG_EN_PLATFORM_WAKEUP_MSK (((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) << GLB_REG_EN_PLATFORM_WAKEUP_POS) +#define GLB_REG_EN_PLATFORM_WAKEUP_UMSK (~(((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) << GLB_REG_EN_PLATFORM_WAKEUP_POS)) + +/* 0xAC : WIFI_BT_COEX_CTRL */ +#define GLB_WIFI_BT_COEX_CTRL_OFFSET (0xAC) +#define GLB_COEX_BT_CHANNEL GLB_COEX_BT_CHANNEL +#define GLB_COEX_BT_CHANNEL_POS (0U) +#define GLB_COEX_BT_CHANNEL_LEN (7U) +#define GLB_COEX_BT_CHANNEL_MSK (((1U << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS) +#define GLB_COEX_BT_CHANNEL_UMSK (~(((1U << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS)) +#define GLB_COEX_BT_PTI GLB_COEX_BT_PTI +#define GLB_COEX_BT_PTI_POS (7U) +#define GLB_COEX_BT_PTI_LEN (4U) +#define GLB_COEX_BT_PTI_MSK (((1U << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS) +#define GLB_COEX_BT_PTI_UMSK (~(((1U << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS)) +#define GLB_COEX_BT_BW GLB_COEX_BT_BW +#define GLB_COEX_BT_BW_POS (11U) +#define GLB_COEX_BT_BW_LEN (1U) +#define GLB_COEX_BT_BW_MSK (((1U << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS) +#define GLB_COEX_BT_BW_UMSK (~(((1U << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS)) +#define GLB_EN_GPIO_BT_COEX GLB_EN_GPIO_BT_COEX +#define GLB_EN_GPIO_BT_COEX_POS (12U) +#define GLB_EN_GPIO_BT_COEX_LEN (1U) +#define GLB_EN_GPIO_BT_COEX_MSK (((1U << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS) +#define GLB_EN_GPIO_BT_COEX_UMSK (~(((1U << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS)) + +/* 0xC0 : UART_SIG_SEL_0 */ +#define GLB_UART_SIG_SEL_0_OFFSET (0xC0) +#define GLB_UART_SIG_0_SEL GLB_UART_SIG_0_SEL +#define GLB_UART_SIG_0_SEL_POS (0U) +#define GLB_UART_SIG_0_SEL_LEN (4U) +#define GLB_UART_SIG_0_SEL_MSK (((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS) +#define GLB_UART_SIG_0_SEL_UMSK (~(((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS)) +#define GLB_UART_SIG_1_SEL GLB_UART_SIG_1_SEL +#define GLB_UART_SIG_1_SEL_POS (4U) +#define GLB_UART_SIG_1_SEL_LEN (4U) +#define GLB_UART_SIG_1_SEL_MSK (((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS) +#define GLB_UART_SIG_1_SEL_UMSK (~(((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS)) +#define GLB_UART_SIG_2_SEL GLB_UART_SIG_2_SEL +#define GLB_UART_SIG_2_SEL_POS (8U) +#define GLB_UART_SIG_2_SEL_LEN (4U) +#define GLB_UART_SIG_2_SEL_MSK (((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS) +#define GLB_UART_SIG_2_SEL_UMSK (~(((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS)) +#define GLB_UART_SIG_3_SEL GLB_UART_SIG_3_SEL +#define GLB_UART_SIG_3_SEL_POS (12U) +#define GLB_UART_SIG_3_SEL_LEN (4U) +#define GLB_UART_SIG_3_SEL_MSK (((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS) +#define GLB_UART_SIG_3_SEL_UMSK (~(((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS)) +#define GLB_UART_SIG_4_SEL GLB_UART_SIG_4_SEL +#define GLB_UART_SIG_4_SEL_POS (16U) +#define GLB_UART_SIG_4_SEL_LEN (4U) +#define GLB_UART_SIG_4_SEL_MSK (((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS) +#define GLB_UART_SIG_4_SEL_UMSK (~(((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS)) +#define GLB_UART_SIG_5_SEL GLB_UART_SIG_5_SEL +#define GLB_UART_SIG_5_SEL_POS (20U) +#define GLB_UART_SIG_5_SEL_LEN (4U) +#define GLB_UART_SIG_5_SEL_MSK (((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS) +#define GLB_UART_SIG_5_SEL_UMSK (~(((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS)) +#define GLB_UART_SIG_6_SEL GLB_UART_SIG_6_SEL +#define GLB_UART_SIG_6_SEL_POS (24U) +#define GLB_UART_SIG_6_SEL_LEN (4U) +#define GLB_UART_SIG_6_SEL_MSK (((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS) +#define GLB_UART_SIG_6_SEL_UMSK (~(((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS)) +#define GLB_UART_SIG_7_SEL GLB_UART_SIG_7_SEL +#define GLB_UART_SIG_7_SEL_POS (28U) +#define GLB_UART_SIG_7_SEL_LEN (4U) +#define GLB_UART_SIG_7_SEL_MSK (((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS) +#define GLB_UART_SIG_7_SEL_UMSK (~(((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS)) + +/* 0xD0 : DBG_SEL_LL */ +#define GLB_DBG_SEL_LL_OFFSET (0xD0) +#define GLB_REG_DBG_LL_CTRL GLB_REG_DBG_LL_CTRL +#define GLB_REG_DBG_LL_CTRL_POS (0U) +#define GLB_REG_DBG_LL_CTRL_LEN (32U) +#define GLB_REG_DBG_LL_CTRL_MSK (((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS) +#define GLB_REG_DBG_LL_CTRL_UMSK (~(((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS)) + +/* 0xD4 : DBG_SEL_LH */ +#define GLB_DBG_SEL_LH_OFFSET (0xD4) +#define GLB_REG_DBG_LH_CTRL GLB_REG_DBG_LH_CTRL +#define GLB_REG_DBG_LH_CTRL_POS (0U) +#define GLB_REG_DBG_LH_CTRL_LEN (32U) +#define GLB_REG_DBG_LH_CTRL_MSK (((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS) +#define GLB_REG_DBG_LH_CTRL_UMSK (~(((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS)) + +/* 0xD8 : DBG_SEL_HL */ +#define GLB_DBG_SEL_HL_OFFSET (0xD8) +#define GLB_REG_DBG_HL_CTRL GLB_REG_DBG_HL_CTRL +#define GLB_REG_DBG_HL_CTRL_POS (0U) +#define GLB_REG_DBG_HL_CTRL_LEN (32U) +#define GLB_REG_DBG_HL_CTRL_MSK (((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS) +#define GLB_REG_DBG_HL_CTRL_UMSK (~(((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS)) + +/* 0xDC : DBG_SEL_HH */ +#define GLB_DBG_SEL_HH_OFFSET (0xDC) +#define GLB_REG_DBG_HH_CTRL GLB_REG_DBG_HH_CTRL +#define GLB_REG_DBG_HH_CTRL_POS (0U) +#define GLB_REG_DBG_HH_CTRL_LEN (32U) +#define GLB_REG_DBG_HH_CTRL_MSK (((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS) +#define GLB_REG_DBG_HH_CTRL_UMSK (~(((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS)) + +/* 0xE0 : debug */ +#define GLB_DEBUG_OFFSET (0xE0) +#define GLB_DEBUG_OE GLB_DEBUG_OE +#define GLB_DEBUG_OE_POS (0U) +#define GLB_DEBUG_OE_LEN (1U) +#define GLB_DEBUG_OE_MSK (((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS) +#define GLB_DEBUG_OE_UMSK (~(((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS)) +#define GLB_DEBUG_I GLB_DEBUG_I +#define GLB_DEBUG_I_POS (1U) +#define GLB_DEBUG_I_LEN (31U) +#define GLB_DEBUG_I_MSK (((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS) +#define GLB_DEBUG_I_UMSK (~(((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS)) + +/* 0x100 : GPIO_CFGCTL0 */ +#define GLB_GPIO_CFGCTL0_OFFSET (0x100) +#define GLB_REG_GPIO_0_IE GLB_REG_GPIO_0_IE +#define GLB_REG_GPIO_0_IE_POS (0U) +#define GLB_REG_GPIO_0_IE_LEN (1U) +#define GLB_REG_GPIO_0_IE_MSK (((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS) +#define GLB_REG_GPIO_0_IE_UMSK (~(((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)) +#define GLB_REG_GPIO_0_SMT GLB_REG_GPIO_0_SMT +#define GLB_REG_GPIO_0_SMT_POS (1U) +#define GLB_REG_GPIO_0_SMT_LEN (1U) +#define GLB_REG_GPIO_0_SMT_MSK (((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS) +#define GLB_REG_GPIO_0_SMT_UMSK (~(((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)) +#define GLB_REG_GPIO_0_DRV GLB_REG_GPIO_0_DRV +#define GLB_REG_GPIO_0_DRV_POS (2U) +#define GLB_REG_GPIO_0_DRV_LEN (2U) +#define GLB_REG_GPIO_0_DRV_MSK (((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS) +#define GLB_REG_GPIO_0_DRV_UMSK (~(((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)) +#define GLB_REG_GPIO_0_PU GLB_REG_GPIO_0_PU +#define GLB_REG_GPIO_0_PU_POS (4U) +#define GLB_REG_GPIO_0_PU_LEN (1U) +#define GLB_REG_GPIO_0_PU_MSK (((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS) +#define GLB_REG_GPIO_0_PU_UMSK (~(((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)) +#define GLB_REG_GPIO_0_PD GLB_REG_GPIO_0_PD +#define GLB_REG_GPIO_0_PD_POS (5U) +#define GLB_REG_GPIO_0_PD_LEN (1U) +#define GLB_REG_GPIO_0_PD_MSK (((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS) +#define GLB_REG_GPIO_0_PD_UMSK (~(((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)) +#define GLB_REG_GPIO_0_FUNC_SEL GLB_REG_GPIO_0_FUNC_SEL +#define GLB_REG_GPIO_0_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_0_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_0_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS) +#define GLB_REG_GPIO_0_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)) +#define GLB_REAL_GPIO_0_FUNC_SEL GLB_REAL_GPIO_0_FUNC_SEL +#define GLB_REAL_GPIO_0_FUNC_SEL_POS (12U) +#define GLB_REAL_GPIO_0_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_0_FUNC_SEL_MSK (((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS) +#define GLB_REAL_GPIO_0_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS)) +#define GLB_REG_GPIO_1_IE GLB_REG_GPIO_1_IE +#define GLB_REG_GPIO_1_IE_POS (16U) +#define GLB_REG_GPIO_1_IE_LEN (1U) +#define GLB_REG_GPIO_1_IE_MSK (((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS) +#define GLB_REG_GPIO_1_IE_UMSK (~(((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)) +#define GLB_REG_GPIO_1_SMT GLB_REG_GPIO_1_SMT +#define GLB_REG_GPIO_1_SMT_POS (17U) +#define GLB_REG_GPIO_1_SMT_LEN (1U) +#define GLB_REG_GPIO_1_SMT_MSK (((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS) +#define GLB_REG_GPIO_1_SMT_UMSK (~(((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)) +#define GLB_REG_GPIO_1_DRV GLB_REG_GPIO_1_DRV +#define GLB_REG_GPIO_1_DRV_POS (18U) +#define GLB_REG_GPIO_1_DRV_LEN (2U) +#define GLB_REG_GPIO_1_DRV_MSK (((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS) +#define GLB_REG_GPIO_1_DRV_UMSK (~(((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)) +#define GLB_REG_GPIO_1_PU GLB_REG_GPIO_1_PU +#define GLB_REG_GPIO_1_PU_POS (20U) +#define GLB_REG_GPIO_1_PU_LEN (1U) +#define GLB_REG_GPIO_1_PU_MSK (((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS) +#define GLB_REG_GPIO_1_PU_UMSK (~(((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)) +#define GLB_REG_GPIO_1_PD GLB_REG_GPIO_1_PD +#define GLB_REG_GPIO_1_PD_POS (21U) +#define GLB_REG_GPIO_1_PD_LEN (1U) +#define GLB_REG_GPIO_1_PD_MSK (((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS) +#define GLB_REG_GPIO_1_PD_UMSK (~(((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)) +#define GLB_REG_GPIO_1_FUNC_SEL GLB_REG_GPIO_1_FUNC_SEL +#define GLB_REG_GPIO_1_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_1_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_1_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS) +#define GLB_REG_GPIO_1_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)) +#define GLB_REAL_GPIO_1_FUNC_SEL GLB_REAL_GPIO_1_FUNC_SEL +#define GLB_REAL_GPIO_1_FUNC_SEL_POS (28U) +#define GLB_REAL_GPIO_1_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_1_FUNC_SEL_MSK (((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS) +#define GLB_REAL_GPIO_1_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS)) + +/* 0x104 : GPIO_CFGCTL1 */ +#define GLB_GPIO_CFGCTL1_OFFSET (0x104) +#define GLB_REG_GPIO_2_IE GLB_REG_GPIO_2_IE +#define GLB_REG_GPIO_2_IE_POS (0U) +#define GLB_REG_GPIO_2_IE_LEN (1U) +#define GLB_REG_GPIO_2_IE_MSK (((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS) +#define GLB_REG_GPIO_2_IE_UMSK (~(((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS)) +#define GLB_REG_GPIO_2_SMT GLB_REG_GPIO_2_SMT +#define GLB_REG_GPIO_2_SMT_POS (1U) +#define GLB_REG_GPIO_2_SMT_LEN (1U) +#define GLB_REG_GPIO_2_SMT_MSK (((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS) +#define GLB_REG_GPIO_2_SMT_UMSK (~(((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS)) +#define GLB_REG_GPIO_2_DRV GLB_REG_GPIO_2_DRV +#define GLB_REG_GPIO_2_DRV_POS (2U) +#define GLB_REG_GPIO_2_DRV_LEN (2U) +#define GLB_REG_GPIO_2_DRV_MSK (((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS) +#define GLB_REG_GPIO_2_DRV_UMSK (~(((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS)) +#define GLB_REG_GPIO_2_PU GLB_REG_GPIO_2_PU +#define GLB_REG_GPIO_2_PU_POS (4U) +#define GLB_REG_GPIO_2_PU_LEN (1U) +#define GLB_REG_GPIO_2_PU_MSK (((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS) +#define GLB_REG_GPIO_2_PU_UMSK (~(((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS)) +#define GLB_REG_GPIO_2_PD GLB_REG_GPIO_2_PD +#define GLB_REG_GPIO_2_PD_POS (5U) +#define GLB_REG_GPIO_2_PD_LEN (1U) +#define GLB_REG_GPIO_2_PD_MSK (((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS) +#define GLB_REG_GPIO_2_PD_UMSK (~(((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS)) +#define GLB_REG_GPIO_2_FUNC_SEL GLB_REG_GPIO_2_FUNC_SEL +#define GLB_REG_GPIO_2_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_2_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_2_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS) +#define GLB_REG_GPIO_2_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS)) +#define GLB_REAL_GPIO_2_FUNC_SEL GLB_REAL_GPIO_2_FUNC_SEL +#define GLB_REAL_GPIO_2_FUNC_SEL_POS (12U) +#define GLB_REAL_GPIO_2_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_2_FUNC_SEL_MSK (((1U << GLB_REAL_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_2_FUNC_SEL_POS) +#define GLB_REAL_GPIO_2_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_2_FUNC_SEL_POS)) +#define GLB_REG_GPIO_3_IE GLB_REG_GPIO_3_IE +#define GLB_REG_GPIO_3_IE_POS (16U) +#define GLB_REG_GPIO_3_IE_LEN (1U) +#define GLB_REG_GPIO_3_IE_MSK (((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS) +#define GLB_REG_GPIO_3_IE_UMSK (~(((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS)) +#define GLB_REG_GPIO_3_SMT GLB_REG_GPIO_3_SMT +#define GLB_REG_GPIO_3_SMT_POS (17U) +#define GLB_REG_GPIO_3_SMT_LEN (1U) +#define GLB_REG_GPIO_3_SMT_MSK (((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS) +#define GLB_REG_GPIO_3_SMT_UMSK (~(((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS)) +#define GLB_REG_GPIO_3_DRV GLB_REG_GPIO_3_DRV +#define GLB_REG_GPIO_3_DRV_POS (18U) +#define GLB_REG_GPIO_3_DRV_LEN (2U) +#define GLB_REG_GPIO_3_DRV_MSK (((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS) +#define GLB_REG_GPIO_3_DRV_UMSK (~(((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS)) +#define GLB_REG_GPIO_3_PU GLB_REG_GPIO_3_PU +#define GLB_REG_GPIO_3_PU_POS (20U) +#define GLB_REG_GPIO_3_PU_LEN (1U) +#define GLB_REG_GPIO_3_PU_MSK (((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS) +#define GLB_REG_GPIO_3_PU_UMSK (~(((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS)) +#define GLB_REG_GPIO_3_PD GLB_REG_GPIO_3_PD +#define GLB_REG_GPIO_3_PD_POS (21U) +#define GLB_REG_GPIO_3_PD_LEN (1U) +#define GLB_REG_GPIO_3_PD_MSK (((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS) +#define GLB_REG_GPIO_3_PD_UMSK (~(((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS)) +#define GLB_REG_GPIO_3_FUNC_SEL GLB_REG_GPIO_3_FUNC_SEL +#define GLB_REG_GPIO_3_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_3_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_3_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS) +#define GLB_REG_GPIO_3_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS)) +#define GLB_REAL_GPIO_3_FUNC_SEL GLB_REAL_GPIO_3_FUNC_SEL +#define GLB_REAL_GPIO_3_FUNC_SEL_POS (28U) +#define GLB_REAL_GPIO_3_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_3_FUNC_SEL_MSK (((1U << GLB_REAL_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_3_FUNC_SEL_POS) +#define GLB_REAL_GPIO_3_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_3_FUNC_SEL_POS)) + +/* 0x108 : GPIO_CFGCTL2 */ +#define GLB_GPIO_CFGCTL2_OFFSET (0x108) +#define GLB_REG_GPIO_4_IE GLB_REG_GPIO_4_IE +#define GLB_REG_GPIO_4_IE_POS (0U) +#define GLB_REG_GPIO_4_IE_LEN (1U) +#define GLB_REG_GPIO_4_IE_MSK (((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS) +#define GLB_REG_GPIO_4_IE_UMSK (~(((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS)) +#define GLB_REG_GPIO_4_SMT GLB_REG_GPIO_4_SMT +#define GLB_REG_GPIO_4_SMT_POS (1U) +#define GLB_REG_GPIO_4_SMT_LEN (1U) +#define GLB_REG_GPIO_4_SMT_MSK (((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS) +#define GLB_REG_GPIO_4_SMT_UMSK (~(((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS)) +#define GLB_REG_GPIO_4_DRV GLB_REG_GPIO_4_DRV +#define GLB_REG_GPIO_4_DRV_POS (2U) +#define GLB_REG_GPIO_4_DRV_LEN (2U) +#define GLB_REG_GPIO_4_DRV_MSK (((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS) +#define GLB_REG_GPIO_4_DRV_UMSK (~(((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS)) +#define GLB_REG_GPIO_4_PU GLB_REG_GPIO_4_PU +#define GLB_REG_GPIO_4_PU_POS (4U) +#define GLB_REG_GPIO_4_PU_LEN (1U) +#define GLB_REG_GPIO_4_PU_MSK (((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS) +#define GLB_REG_GPIO_4_PU_UMSK (~(((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS)) +#define GLB_REG_GPIO_4_PD GLB_REG_GPIO_4_PD +#define GLB_REG_GPIO_4_PD_POS (5U) +#define GLB_REG_GPIO_4_PD_LEN (1U) +#define GLB_REG_GPIO_4_PD_MSK (((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS) +#define GLB_REG_GPIO_4_PD_UMSK (~(((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS)) +#define GLB_REG_GPIO_4_FUNC_SEL GLB_REG_GPIO_4_FUNC_SEL +#define GLB_REG_GPIO_4_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_4_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_4_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS) +#define GLB_REG_GPIO_4_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS)) +#define GLB_REAL_GPIO_4_FUNC_SEL GLB_REAL_GPIO_4_FUNC_SEL +#define GLB_REAL_GPIO_4_FUNC_SEL_POS (12U) +#define GLB_REAL_GPIO_4_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_4_FUNC_SEL_MSK (((1U << GLB_REAL_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_4_FUNC_SEL_POS) +#define GLB_REAL_GPIO_4_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_4_FUNC_SEL_POS)) +#define GLB_REG_GPIO_5_IE GLB_REG_GPIO_5_IE +#define GLB_REG_GPIO_5_IE_POS (16U) +#define GLB_REG_GPIO_5_IE_LEN (1U) +#define GLB_REG_GPIO_5_IE_MSK (((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS) +#define GLB_REG_GPIO_5_IE_UMSK (~(((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS)) +#define GLB_REG_GPIO_5_SMT GLB_REG_GPIO_5_SMT +#define GLB_REG_GPIO_5_SMT_POS (17U) +#define GLB_REG_GPIO_5_SMT_LEN (1U) +#define GLB_REG_GPIO_5_SMT_MSK (((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS) +#define GLB_REG_GPIO_5_SMT_UMSK (~(((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS)) +#define GLB_REG_GPIO_5_DRV GLB_REG_GPIO_5_DRV +#define GLB_REG_GPIO_5_DRV_POS (18U) +#define GLB_REG_GPIO_5_DRV_LEN (2U) +#define GLB_REG_GPIO_5_DRV_MSK (((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS) +#define GLB_REG_GPIO_5_DRV_UMSK (~(((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS)) +#define GLB_REG_GPIO_5_PU GLB_REG_GPIO_5_PU +#define GLB_REG_GPIO_5_PU_POS (20U) +#define GLB_REG_GPIO_5_PU_LEN (1U) +#define GLB_REG_GPIO_5_PU_MSK (((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS) +#define GLB_REG_GPIO_5_PU_UMSK (~(((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS)) +#define GLB_REG_GPIO_5_PD GLB_REG_GPIO_5_PD +#define GLB_REG_GPIO_5_PD_POS (21U) +#define GLB_REG_GPIO_5_PD_LEN (1U) +#define GLB_REG_GPIO_5_PD_MSK (((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS) +#define GLB_REG_GPIO_5_PD_UMSK (~(((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS)) +#define GLB_REG_GPIO_5_FUNC_SEL GLB_REG_GPIO_5_FUNC_SEL +#define GLB_REG_GPIO_5_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_5_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_5_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS) +#define GLB_REG_GPIO_5_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS)) +#define GLB_REAL_GPIO_5_FUNC_SEL GLB_REAL_GPIO_5_FUNC_SEL +#define GLB_REAL_GPIO_5_FUNC_SEL_POS (28U) +#define GLB_REAL_GPIO_5_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_5_FUNC_SEL_MSK (((1U << GLB_REAL_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_5_FUNC_SEL_POS) +#define GLB_REAL_GPIO_5_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_5_FUNC_SEL_POS)) + +/* 0x10C : GPIO_CFGCTL3 */ +#define GLB_GPIO_CFGCTL3_OFFSET (0x10C) +#define GLB_REG_GPIO_6_IE GLB_REG_GPIO_6_IE +#define GLB_REG_GPIO_6_IE_POS (0U) +#define GLB_REG_GPIO_6_IE_LEN (1U) +#define GLB_REG_GPIO_6_IE_MSK (((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS) +#define GLB_REG_GPIO_6_IE_UMSK (~(((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS)) +#define GLB_REG_GPIO_6_SMT GLB_REG_GPIO_6_SMT +#define GLB_REG_GPIO_6_SMT_POS (1U) +#define GLB_REG_GPIO_6_SMT_LEN (1U) +#define GLB_REG_GPIO_6_SMT_MSK (((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS) +#define GLB_REG_GPIO_6_SMT_UMSK (~(((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS)) +#define GLB_REG_GPIO_6_DRV GLB_REG_GPIO_6_DRV +#define GLB_REG_GPIO_6_DRV_POS (2U) +#define GLB_REG_GPIO_6_DRV_LEN (2U) +#define GLB_REG_GPIO_6_DRV_MSK (((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS) +#define GLB_REG_GPIO_6_DRV_UMSK (~(((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS)) +#define GLB_REG_GPIO_6_PU GLB_REG_GPIO_6_PU +#define GLB_REG_GPIO_6_PU_POS (4U) +#define GLB_REG_GPIO_6_PU_LEN (1U) +#define GLB_REG_GPIO_6_PU_MSK (((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS) +#define GLB_REG_GPIO_6_PU_UMSK (~(((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS)) +#define GLB_REG_GPIO_6_PD GLB_REG_GPIO_6_PD +#define GLB_REG_GPIO_6_PD_POS (5U) +#define GLB_REG_GPIO_6_PD_LEN (1U) +#define GLB_REG_GPIO_6_PD_MSK (((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS) +#define GLB_REG_GPIO_6_PD_UMSK (~(((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS)) +#define GLB_REG_GPIO_6_FUNC_SEL GLB_REG_GPIO_6_FUNC_SEL +#define GLB_REG_GPIO_6_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_6_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_6_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS) +#define GLB_REG_GPIO_6_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS)) +#define GLB_REG_GPIO_7_IE GLB_REG_GPIO_7_IE +#define GLB_REG_GPIO_7_IE_POS (16U) +#define GLB_REG_GPIO_7_IE_LEN (1U) +#define GLB_REG_GPIO_7_IE_MSK (((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS) +#define GLB_REG_GPIO_7_IE_UMSK (~(((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS)) +#define GLB_REG_GPIO_7_SMT GLB_REG_GPIO_7_SMT +#define GLB_REG_GPIO_7_SMT_POS (17U) +#define GLB_REG_GPIO_7_SMT_LEN (1U) +#define GLB_REG_GPIO_7_SMT_MSK (((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS) +#define GLB_REG_GPIO_7_SMT_UMSK (~(((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS)) +#define GLB_REG_GPIO_7_DRV GLB_REG_GPIO_7_DRV +#define GLB_REG_GPIO_7_DRV_POS (18U) +#define GLB_REG_GPIO_7_DRV_LEN (2U) +#define GLB_REG_GPIO_7_DRV_MSK (((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS) +#define GLB_REG_GPIO_7_DRV_UMSK (~(((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS)) +#define GLB_REG_GPIO_7_PU GLB_REG_GPIO_7_PU +#define GLB_REG_GPIO_7_PU_POS (20U) +#define GLB_REG_GPIO_7_PU_LEN (1U) +#define GLB_REG_GPIO_7_PU_MSK (((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS) +#define GLB_REG_GPIO_7_PU_UMSK (~(((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS)) +#define GLB_REG_GPIO_7_PD GLB_REG_GPIO_7_PD +#define GLB_REG_GPIO_7_PD_POS (21U) +#define GLB_REG_GPIO_7_PD_LEN (1U) +#define GLB_REG_GPIO_7_PD_MSK (((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS) +#define GLB_REG_GPIO_7_PD_UMSK (~(((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS)) +#define GLB_REG_GPIO_7_FUNC_SEL GLB_REG_GPIO_7_FUNC_SEL +#define GLB_REG_GPIO_7_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_7_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_7_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS) +#define GLB_REG_GPIO_7_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS)) + +/* 0x110 : GPIO_CFGCTL4 */ +#define GLB_GPIO_CFGCTL4_OFFSET (0x110) +#define GLB_REG_GPIO_8_IE GLB_REG_GPIO_8_IE +#define GLB_REG_GPIO_8_IE_POS (0U) +#define GLB_REG_GPIO_8_IE_LEN (1U) +#define GLB_REG_GPIO_8_IE_MSK (((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS) +#define GLB_REG_GPIO_8_IE_UMSK (~(((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS)) +#define GLB_REG_GPIO_8_SMT GLB_REG_GPIO_8_SMT +#define GLB_REG_GPIO_8_SMT_POS (1U) +#define GLB_REG_GPIO_8_SMT_LEN (1U) +#define GLB_REG_GPIO_8_SMT_MSK (((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS) +#define GLB_REG_GPIO_8_SMT_UMSK (~(((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS)) +#define GLB_REG_GPIO_8_DRV GLB_REG_GPIO_8_DRV +#define GLB_REG_GPIO_8_DRV_POS (2U) +#define GLB_REG_GPIO_8_DRV_LEN (2U) +#define GLB_REG_GPIO_8_DRV_MSK (((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS) +#define GLB_REG_GPIO_8_DRV_UMSK (~(((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS)) +#define GLB_REG_GPIO_8_PU GLB_REG_GPIO_8_PU +#define GLB_REG_GPIO_8_PU_POS (4U) +#define GLB_REG_GPIO_8_PU_LEN (1U) +#define GLB_REG_GPIO_8_PU_MSK (((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS) +#define GLB_REG_GPIO_8_PU_UMSK (~(((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS)) +#define GLB_REG_GPIO_8_PD GLB_REG_GPIO_8_PD +#define GLB_REG_GPIO_8_PD_POS (5U) +#define GLB_REG_GPIO_8_PD_LEN (1U) +#define GLB_REG_GPIO_8_PD_MSK (((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS) +#define GLB_REG_GPIO_8_PD_UMSK (~(((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS)) +#define GLB_REG_GPIO_8_FUNC_SEL GLB_REG_GPIO_8_FUNC_SEL +#define GLB_REG_GPIO_8_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_8_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_8_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS) +#define GLB_REG_GPIO_8_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS)) +#define GLB_REG_GPIO_9_IE GLB_REG_GPIO_9_IE +#define GLB_REG_GPIO_9_IE_POS (16U) +#define GLB_REG_GPIO_9_IE_LEN (1U) +#define GLB_REG_GPIO_9_IE_MSK (((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS) +#define GLB_REG_GPIO_9_IE_UMSK (~(((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS)) +#define GLB_REG_GPIO_9_SMT GLB_REG_GPIO_9_SMT +#define GLB_REG_GPIO_9_SMT_POS (17U) +#define GLB_REG_GPIO_9_SMT_LEN (1U) +#define GLB_REG_GPIO_9_SMT_MSK (((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS) +#define GLB_REG_GPIO_9_SMT_UMSK (~(((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS)) +#define GLB_REG_GPIO_9_DRV GLB_REG_GPIO_9_DRV +#define GLB_REG_GPIO_9_DRV_POS (18U) +#define GLB_REG_GPIO_9_DRV_LEN (2U) +#define GLB_REG_GPIO_9_DRV_MSK (((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS) +#define GLB_REG_GPIO_9_DRV_UMSK (~(((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS)) +#define GLB_REG_GPIO_9_PU GLB_REG_GPIO_9_PU +#define GLB_REG_GPIO_9_PU_POS (20U) +#define GLB_REG_GPIO_9_PU_LEN (1U) +#define GLB_REG_GPIO_9_PU_MSK (((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS) +#define GLB_REG_GPIO_9_PU_UMSK (~(((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS)) +#define GLB_REG_GPIO_9_PD GLB_REG_GPIO_9_PD +#define GLB_REG_GPIO_9_PD_POS (21U) +#define GLB_REG_GPIO_9_PD_LEN (1U) +#define GLB_REG_GPIO_9_PD_MSK (((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS) +#define GLB_REG_GPIO_9_PD_UMSK (~(((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS)) +#define GLB_REG_GPIO_9_FUNC_SEL GLB_REG_GPIO_9_FUNC_SEL +#define GLB_REG_GPIO_9_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_9_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_9_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS) +#define GLB_REG_GPIO_9_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS)) + +/* 0x114 : GPIO_CFGCTL5 */ +#define GLB_GPIO_CFGCTL5_OFFSET (0x114) +#define GLB_REG_GPIO_10_IE GLB_REG_GPIO_10_IE +#define GLB_REG_GPIO_10_IE_POS (0U) +#define GLB_REG_GPIO_10_IE_LEN (1U) +#define GLB_REG_GPIO_10_IE_MSK (((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS) +#define GLB_REG_GPIO_10_IE_UMSK (~(((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS)) +#define GLB_REG_GPIO_10_SMT GLB_REG_GPIO_10_SMT +#define GLB_REG_GPIO_10_SMT_POS (1U) +#define GLB_REG_GPIO_10_SMT_LEN (1U) +#define GLB_REG_GPIO_10_SMT_MSK (((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS) +#define GLB_REG_GPIO_10_SMT_UMSK (~(((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS)) +#define GLB_REG_GPIO_10_DRV GLB_REG_GPIO_10_DRV +#define GLB_REG_GPIO_10_DRV_POS (2U) +#define GLB_REG_GPIO_10_DRV_LEN (2U) +#define GLB_REG_GPIO_10_DRV_MSK (((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS) +#define GLB_REG_GPIO_10_DRV_UMSK (~(((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS)) +#define GLB_REG_GPIO_10_PU GLB_REG_GPIO_10_PU +#define GLB_REG_GPIO_10_PU_POS (4U) +#define GLB_REG_GPIO_10_PU_LEN (1U) +#define GLB_REG_GPIO_10_PU_MSK (((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS) +#define GLB_REG_GPIO_10_PU_UMSK (~(((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS)) +#define GLB_REG_GPIO_10_PD GLB_REG_GPIO_10_PD +#define GLB_REG_GPIO_10_PD_POS (5U) +#define GLB_REG_GPIO_10_PD_LEN (1U) +#define GLB_REG_GPIO_10_PD_MSK (((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS) +#define GLB_REG_GPIO_10_PD_UMSK (~(((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS)) +#define GLB_REG_GPIO_10_FUNC_SEL GLB_REG_GPIO_10_FUNC_SEL +#define GLB_REG_GPIO_10_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_10_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_10_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS) +#define GLB_REG_GPIO_10_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS)) +#define GLB_REG_GPIO_11_IE GLB_REG_GPIO_11_IE +#define GLB_REG_GPIO_11_IE_POS (16U) +#define GLB_REG_GPIO_11_IE_LEN (1U) +#define GLB_REG_GPIO_11_IE_MSK (((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS) +#define GLB_REG_GPIO_11_IE_UMSK (~(((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS)) +#define GLB_REG_GPIO_11_SMT GLB_REG_GPIO_11_SMT +#define GLB_REG_GPIO_11_SMT_POS (17U) +#define GLB_REG_GPIO_11_SMT_LEN (1U) +#define GLB_REG_GPIO_11_SMT_MSK (((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS) +#define GLB_REG_GPIO_11_SMT_UMSK (~(((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS)) +#define GLB_REG_GPIO_11_DRV GLB_REG_GPIO_11_DRV +#define GLB_REG_GPIO_11_DRV_POS (18U) +#define GLB_REG_GPIO_11_DRV_LEN (2U) +#define GLB_REG_GPIO_11_DRV_MSK (((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS) +#define GLB_REG_GPIO_11_DRV_UMSK (~(((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS)) +#define GLB_REG_GPIO_11_PU GLB_REG_GPIO_11_PU +#define GLB_REG_GPIO_11_PU_POS (20U) +#define GLB_REG_GPIO_11_PU_LEN (1U) +#define GLB_REG_GPIO_11_PU_MSK (((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS) +#define GLB_REG_GPIO_11_PU_UMSK (~(((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS)) +#define GLB_REG_GPIO_11_PD GLB_REG_GPIO_11_PD +#define GLB_REG_GPIO_11_PD_POS (21U) +#define GLB_REG_GPIO_11_PD_LEN (1U) +#define GLB_REG_GPIO_11_PD_MSK (((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS) +#define GLB_REG_GPIO_11_PD_UMSK (~(((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS)) +#define GLB_REG_GPIO_11_FUNC_SEL GLB_REG_GPIO_11_FUNC_SEL +#define GLB_REG_GPIO_11_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_11_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_11_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS) +#define GLB_REG_GPIO_11_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS)) + +/* 0x118 : GPIO_CFGCTL6 */ +#define GLB_GPIO_CFGCTL6_OFFSET (0x118) +#define GLB_REG_GPIO_12_IE GLB_REG_GPIO_12_IE +#define GLB_REG_GPIO_12_IE_POS (0U) +#define GLB_REG_GPIO_12_IE_LEN (1U) +#define GLB_REG_GPIO_12_IE_MSK (((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS) +#define GLB_REG_GPIO_12_IE_UMSK (~(((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS)) +#define GLB_REG_GPIO_12_SMT GLB_REG_GPIO_12_SMT +#define GLB_REG_GPIO_12_SMT_POS (1U) +#define GLB_REG_GPIO_12_SMT_LEN (1U) +#define GLB_REG_GPIO_12_SMT_MSK (((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS) +#define GLB_REG_GPIO_12_SMT_UMSK (~(((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS)) +#define GLB_REG_GPIO_12_DRV GLB_REG_GPIO_12_DRV +#define GLB_REG_GPIO_12_DRV_POS (2U) +#define GLB_REG_GPIO_12_DRV_LEN (2U) +#define GLB_REG_GPIO_12_DRV_MSK (((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS) +#define GLB_REG_GPIO_12_DRV_UMSK (~(((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS)) +#define GLB_REG_GPIO_12_PU GLB_REG_GPIO_12_PU +#define GLB_REG_GPIO_12_PU_POS (4U) +#define GLB_REG_GPIO_12_PU_LEN (1U) +#define GLB_REG_GPIO_12_PU_MSK (((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS) +#define GLB_REG_GPIO_12_PU_UMSK (~(((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS)) +#define GLB_REG_GPIO_12_PD GLB_REG_GPIO_12_PD +#define GLB_REG_GPIO_12_PD_POS (5U) +#define GLB_REG_GPIO_12_PD_LEN (1U) +#define GLB_REG_GPIO_12_PD_MSK (((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS) +#define GLB_REG_GPIO_12_PD_UMSK (~(((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS)) +#define GLB_REG_GPIO_12_FUNC_SEL GLB_REG_GPIO_12_FUNC_SEL +#define GLB_REG_GPIO_12_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_12_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_12_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS) +#define GLB_REG_GPIO_12_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS)) +#define GLB_REG_GPIO_13_IE GLB_REG_GPIO_13_IE +#define GLB_REG_GPIO_13_IE_POS (16U) +#define GLB_REG_GPIO_13_IE_LEN (1U) +#define GLB_REG_GPIO_13_IE_MSK (((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS) +#define GLB_REG_GPIO_13_IE_UMSK (~(((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS)) +#define GLB_REG_GPIO_13_SMT GLB_REG_GPIO_13_SMT +#define GLB_REG_GPIO_13_SMT_POS (17U) +#define GLB_REG_GPIO_13_SMT_LEN (1U) +#define GLB_REG_GPIO_13_SMT_MSK (((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS) +#define GLB_REG_GPIO_13_SMT_UMSK (~(((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS)) +#define GLB_REG_GPIO_13_DRV GLB_REG_GPIO_13_DRV +#define GLB_REG_GPIO_13_DRV_POS (18U) +#define GLB_REG_GPIO_13_DRV_LEN (2U) +#define GLB_REG_GPIO_13_DRV_MSK (((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS) +#define GLB_REG_GPIO_13_DRV_UMSK (~(((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS)) +#define GLB_REG_GPIO_13_PU GLB_REG_GPIO_13_PU +#define GLB_REG_GPIO_13_PU_POS (20U) +#define GLB_REG_GPIO_13_PU_LEN (1U) +#define GLB_REG_GPIO_13_PU_MSK (((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS) +#define GLB_REG_GPIO_13_PU_UMSK (~(((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS)) +#define GLB_REG_GPIO_13_PD GLB_REG_GPIO_13_PD +#define GLB_REG_GPIO_13_PD_POS (21U) +#define GLB_REG_GPIO_13_PD_LEN (1U) +#define GLB_REG_GPIO_13_PD_MSK (((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS) +#define GLB_REG_GPIO_13_PD_UMSK (~(((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS)) +#define GLB_REG_GPIO_13_FUNC_SEL GLB_REG_GPIO_13_FUNC_SEL +#define GLB_REG_GPIO_13_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_13_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_13_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS) +#define GLB_REG_GPIO_13_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS)) + +/* 0x11C : GPIO_CFGCTL7 */ +#define GLB_GPIO_CFGCTL7_OFFSET (0x11C) +#define GLB_REG_GPIO_14_IE GLB_REG_GPIO_14_IE +#define GLB_REG_GPIO_14_IE_POS (0U) +#define GLB_REG_GPIO_14_IE_LEN (1U) +#define GLB_REG_GPIO_14_IE_MSK (((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS) +#define GLB_REG_GPIO_14_IE_UMSK (~(((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS)) +#define GLB_REG_GPIO_14_SMT GLB_REG_GPIO_14_SMT +#define GLB_REG_GPIO_14_SMT_POS (1U) +#define GLB_REG_GPIO_14_SMT_LEN (1U) +#define GLB_REG_GPIO_14_SMT_MSK (((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS) +#define GLB_REG_GPIO_14_SMT_UMSK (~(((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS)) +#define GLB_REG_GPIO_14_DRV GLB_REG_GPIO_14_DRV +#define GLB_REG_GPIO_14_DRV_POS (2U) +#define GLB_REG_GPIO_14_DRV_LEN (2U) +#define GLB_REG_GPIO_14_DRV_MSK (((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS) +#define GLB_REG_GPIO_14_DRV_UMSK (~(((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS)) +#define GLB_REG_GPIO_14_PU GLB_REG_GPIO_14_PU +#define GLB_REG_GPIO_14_PU_POS (4U) +#define GLB_REG_GPIO_14_PU_LEN (1U) +#define GLB_REG_GPIO_14_PU_MSK (((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS) +#define GLB_REG_GPIO_14_PU_UMSK (~(((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS)) +#define GLB_REG_GPIO_14_PD GLB_REG_GPIO_14_PD +#define GLB_REG_GPIO_14_PD_POS (5U) +#define GLB_REG_GPIO_14_PD_LEN (1U) +#define GLB_REG_GPIO_14_PD_MSK (((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS) +#define GLB_REG_GPIO_14_PD_UMSK (~(((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS)) +#define GLB_REG_GPIO_14_FUNC_SEL GLB_REG_GPIO_14_FUNC_SEL +#define GLB_REG_GPIO_14_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_14_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_14_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS) +#define GLB_REG_GPIO_14_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS)) +#define GLB_REG_GPIO_15_IE GLB_REG_GPIO_15_IE +#define GLB_REG_GPIO_15_IE_POS (16U) +#define GLB_REG_GPIO_15_IE_LEN (1U) +#define GLB_REG_GPIO_15_IE_MSK (((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS) +#define GLB_REG_GPIO_15_IE_UMSK (~(((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS)) +#define GLB_REG_GPIO_15_SMT GLB_REG_GPIO_15_SMT +#define GLB_REG_GPIO_15_SMT_POS (17U) +#define GLB_REG_GPIO_15_SMT_LEN (1U) +#define GLB_REG_GPIO_15_SMT_MSK (((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS) +#define GLB_REG_GPIO_15_SMT_UMSK (~(((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS)) +#define GLB_REG_GPIO_15_DRV GLB_REG_GPIO_15_DRV +#define GLB_REG_GPIO_15_DRV_POS (18U) +#define GLB_REG_GPIO_15_DRV_LEN (2U) +#define GLB_REG_GPIO_15_DRV_MSK (((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS) +#define GLB_REG_GPIO_15_DRV_UMSK (~(((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS)) +#define GLB_REG_GPIO_15_PU GLB_REG_GPIO_15_PU +#define GLB_REG_GPIO_15_PU_POS (20U) +#define GLB_REG_GPIO_15_PU_LEN (1U) +#define GLB_REG_GPIO_15_PU_MSK (((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS) +#define GLB_REG_GPIO_15_PU_UMSK (~(((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS)) +#define GLB_REG_GPIO_15_PD GLB_REG_GPIO_15_PD +#define GLB_REG_GPIO_15_PD_POS (21U) +#define GLB_REG_GPIO_15_PD_LEN (1U) +#define GLB_REG_GPIO_15_PD_MSK (((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS) +#define GLB_REG_GPIO_15_PD_UMSK (~(((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS)) +#define GLB_REG_GPIO_15_FUNC_SEL GLB_REG_GPIO_15_FUNC_SEL +#define GLB_REG_GPIO_15_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_15_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_15_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS) +#define GLB_REG_GPIO_15_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS)) + +/* 0x120 : GPIO_CFGCTL8 */ +#define GLB_GPIO_CFGCTL8_OFFSET (0x120) +#define GLB_REG_GPIO_16_IE GLB_REG_GPIO_16_IE +#define GLB_REG_GPIO_16_IE_POS (0U) +#define GLB_REG_GPIO_16_IE_LEN (1U) +#define GLB_REG_GPIO_16_IE_MSK (((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS) +#define GLB_REG_GPIO_16_IE_UMSK (~(((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS)) +#define GLB_REG_GPIO_16_SMT GLB_REG_GPIO_16_SMT +#define GLB_REG_GPIO_16_SMT_POS (1U) +#define GLB_REG_GPIO_16_SMT_LEN (1U) +#define GLB_REG_GPIO_16_SMT_MSK (((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS) +#define GLB_REG_GPIO_16_SMT_UMSK (~(((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS)) +#define GLB_REG_GPIO_16_DRV GLB_REG_GPIO_16_DRV +#define GLB_REG_GPIO_16_DRV_POS (2U) +#define GLB_REG_GPIO_16_DRV_LEN (2U) +#define GLB_REG_GPIO_16_DRV_MSK (((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS) +#define GLB_REG_GPIO_16_DRV_UMSK (~(((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS)) +#define GLB_REG_GPIO_16_PU GLB_REG_GPIO_16_PU +#define GLB_REG_GPIO_16_PU_POS (4U) +#define GLB_REG_GPIO_16_PU_LEN (1U) +#define GLB_REG_GPIO_16_PU_MSK (((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS) +#define GLB_REG_GPIO_16_PU_UMSK (~(((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS)) +#define GLB_REG_GPIO_16_PD GLB_REG_GPIO_16_PD +#define GLB_REG_GPIO_16_PD_POS (5U) +#define GLB_REG_GPIO_16_PD_LEN (1U) +#define GLB_REG_GPIO_16_PD_MSK (((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS) +#define GLB_REG_GPIO_16_PD_UMSK (~(((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS)) +#define GLB_REG_GPIO_16_FUNC_SEL GLB_REG_GPIO_16_FUNC_SEL +#define GLB_REG_GPIO_16_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_16_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_16_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS) +#define GLB_REG_GPIO_16_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS)) +#define GLB_REG_GPIO_17_IE GLB_REG_GPIO_17_IE +#define GLB_REG_GPIO_17_IE_POS (16U) +#define GLB_REG_GPIO_17_IE_LEN (1U) +#define GLB_REG_GPIO_17_IE_MSK (((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS) +#define GLB_REG_GPIO_17_IE_UMSK (~(((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS)) +#define GLB_REG_GPIO_17_SMT GLB_REG_GPIO_17_SMT +#define GLB_REG_GPIO_17_SMT_POS (17U) +#define GLB_REG_GPIO_17_SMT_LEN (1U) +#define GLB_REG_GPIO_17_SMT_MSK (((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS) +#define GLB_REG_GPIO_17_SMT_UMSK (~(((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS)) +#define GLB_REG_GPIO_17_DRV GLB_REG_GPIO_17_DRV +#define GLB_REG_GPIO_17_DRV_POS (18U) +#define GLB_REG_GPIO_17_DRV_LEN (2U) +#define GLB_REG_GPIO_17_DRV_MSK (((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS) +#define GLB_REG_GPIO_17_DRV_UMSK (~(((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS)) +#define GLB_REG_GPIO_17_PU GLB_REG_GPIO_17_PU +#define GLB_REG_GPIO_17_PU_POS (20U) +#define GLB_REG_GPIO_17_PU_LEN (1U) +#define GLB_REG_GPIO_17_PU_MSK (((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS) +#define GLB_REG_GPIO_17_PU_UMSK (~(((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS)) +#define GLB_REG_GPIO_17_PD GLB_REG_GPIO_17_PD +#define GLB_REG_GPIO_17_PD_POS (21U) +#define GLB_REG_GPIO_17_PD_LEN (1U) +#define GLB_REG_GPIO_17_PD_MSK (((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS) +#define GLB_REG_GPIO_17_PD_UMSK (~(((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS)) +#define GLB_REG_GPIO_17_FUNC_SEL GLB_REG_GPIO_17_FUNC_SEL +#define GLB_REG_GPIO_17_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_17_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_17_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS) +#define GLB_REG_GPIO_17_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS)) + +/* 0x124 : GPIO_CFGCTL9 */ +#define GLB_GPIO_CFGCTL9_OFFSET (0x124) +#define GLB_REG_GPIO_18_IE GLB_REG_GPIO_18_IE +#define GLB_REG_GPIO_18_IE_POS (0U) +#define GLB_REG_GPIO_18_IE_LEN (1U) +#define GLB_REG_GPIO_18_IE_MSK (((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS) +#define GLB_REG_GPIO_18_IE_UMSK (~(((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS)) +#define GLB_REG_GPIO_18_SMT GLB_REG_GPIO_18_SMT +#define GLB_REG_GPIO_18_SMT_POS (1U) +#define GLB_REG_GPIO_18_SMT_LEN (1U) +#define GLB_REG_GPIO_18_SMT_MSK (((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS) +#define GLB_REG_GPIO_18_SMT_UMSK (~(((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS)) +#define GLB_REG_GPIO_18_DRV GLB_REG_GPIO_18_DRV +#define GLB_REG_GPIO_18_DRV_POS (2U) +#define GLB_REG_GPIO_18_DRV_LEN (2U) +#define GLB_REG_GPIO_18_DRV_MSK (((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS) +#define GLB_REG_GPIO_18_DRV_UMSK (~(((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS)) +#define GLB_REG_GPIO_18_PU GLB_REG_GPIO_18_PU +#define GLB_REG_GPIO_18_PU_POS (4U) +#define GLB_REG_GPIO_18_PU_LEN (1U) +#define GLB_REG_GPIO_18_PU_MSK (((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS) +#define GLB_REG_GPIO_18_PU_UMSK (~(((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS)) +#define GLB_REG_GPIO_18_PD GLB_REG_GPIO_18_PD +#define GLB_REG_GPIO_18_PD_POS (5U) +#define GLB_REG_GPIO_18_PD_LEN (1U) +#define GLB_REG_GPIO_18_PD_MSK (((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS) +#define GLB_REG_GPIO_18_PD_UMSK (~(((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS)) +#define GLB_REG_GPIO_18_FUNC_SEL GLB_REG_GPIO_18_FUNC_SEL +#define GLB_REG_GPIO_18_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_18_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_18_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS) +#define GLB_REG_GPIO_18_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS)) +#define GLB_REG_GPIO_19_IE GLB_REG_GPIO_19_IE +#define GLB_REG_GPIO_19_IE_POS (16U) +#define GLB_REG_GPIO_19_IE_LEN (1U) +#define GLB_REG_GPIO_19_IE_MSK (((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS) +#define GLB_REG_GPIO_19_IE_UMSK (~(((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS)) +#define GLB_REG_GPIO_19_SMT GLB_REG_GPIO_19_SMT +#define GLB_REG_GPIO_19_SMT_POS (17U) +#define GLB_REG_GPIO_19_SMT_LEN (1U) +#define GLB_REG_GPIO_19_SMT_MSK (((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS) +#define GLB_REG_GPIO_19_SMT_UMSK (~(((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS)) +#define GLB_REG_GPIO_19_DRV GLB_REG_GPIO_19_DRV +#define GLB_REG_GPIO_19_DRV_POS (18U) +#define GLB_REG_GPIO_19_DRV_LEN (2U) +#define GLB_REG_GPIO_19_DRV_MSK (((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS) +#define GLB_REG_GPIO_19_DRV_UMSK (~(((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS)) +#define GLB_REG_GPIO_19_PU GLB_REG_GPIO_19_PU +#define GLB_REG_GPIO_19_PU_POS (20U) +#define GLB_REG_GPIO_19_PU_LEN (1U) +#define GLB_REG_GPIO_19_PU_MSK (((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS) +#define GLB_REG_GPIO_19_PU_UMSK (~(((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS)) +#define GLB_REG_GPIO_19_PD GLB_REG_GPIO_19_PD +#define GLB_REG_GPIO_19_PD_POS (21U) +#define GLB_REG_GPIO_19_PD_LEN (1U) +#define GLB_REG_GPIO_19_PD_MSK (((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS) +#define GLB_REG_GPIO_19_PD_UMSK (~(((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS)) +#define GLB_REG_GPIO_19_FUNC_SEL GLB_REG_GPIO_19_FUNC_SEL +#define GLB_REG_GPIO_19_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_19_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_19_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS) +#define GLB_REG_GPIO_19_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS)) + +/* 0x128 : GPIO_CFGCTL10 */ +#define GLB_GPIO_CFGCTL10_OFFSET (0x128) +#define GLB_REG_GPIO_20_IE GLB_REG_GPIO_20_IE +#define GLB_REG_GPIO_20_IE_POS (0U) +#define GLB_REG_GPIO_20_IE_LEN (1U) +#define GLB_REG_GPIO_20_IE_MSK (((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS) +#define GLB_REG_GPIO_20_IE_UMSK (~(((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS)) +#define GLB_REG_GPIO_20_SMT GLB_REG_GPIO_20_SMT +#define GLB_REG_GPIO_20_SMT_POS (1U) +#define GLB_REG_GPIO_20_SMT_LEN (1U) +#define GLB_REG_GPIO_20_SMT_MSK (((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS) +#define GLB_REG_GPIO_20_SMT_UMSK (~(((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS)) +#define GLB_REG_GPIO_20_DRV GLB_REG_GPIO_20_DRV +#define GLB_REG_GPIO_20_DRV_POS (2U) +#define GLB_REG_GPIO_20_DRV_LEN (2U) +#define GLB_REG_GPIO_20_DRV_MSK (((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS) +#define GLB_REG_GPIO_20_DRV_UMSK (~(((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS)) +#define GLB_REG_GPIO_20_PU GLB_REG_GPIO_20_PU +#define GLB_REG_GPIO_20_PU_POS (4U) +#define GLB_REG_GPIO_20_PU_LEN (1U) +#define GLB_REG_GPIO_20_PU_MSK (((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS) +#define GLB_REG_GPIO_20_PU_UMSK (~(((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS)) +#define GLB_REG_GPIO_20_PD GLB_REG_GPIO_20_PD +#define GLB_REG_GPIO_20_PD_POS (5U) +#define GLB_REG_GPIO_20_PD_LEN (1U) +#define GLB_REG_GPIO_20_PD_MSK (((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS) +#define GLB_REG_GPIO_20_PD_UMSK (~(((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS)) +#define GLB_REG_GPIO_20_FUNC_SEL GLB_REG_GPIO_20_FUNC_SEL +#define GLB_REG_GPIO_20_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_20_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_20_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS) +#define GLB_REG_GPIO_20_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS)) +#define GLB_REG_GPIO_21_IE GLB_REG_GPIO_21_IE +#define GLB_REG_GPIO_21_IE_POS (16U) +#define GLB_REG_GPIO_21_IE_LEN (1U) +#define GLB_REG_GPIO_21_IE_MSK (((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS) +#define GLB_REG_GPIO_21_IE_UMSK (~(((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS)) +#define GLB_REG_GPIO_21_SMT GLB_REG_GPIO_21_SMT +#define GLB_REG_GPIO_21_SMT_POS (17U) +#define GLB_REG_GPIO_21_SMT_LEN (1U) +#define GLB_REG_GPIO_21_SMT_MSK (((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS) +#define GLB_REG_GPIO_21_SMT_UMSK (~(((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS)) +#define GLB_REG_GPIO_21_DRV GLB_REG_GPIO_21_DRV +#define GLB_REG_GPIO_21_DRV_POS (18U) +#define GLB_REG_GPIO_21_DRV_LEN (2U) +#define GLB_REG_GPIO_21_DRV_MSK (((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS) +#define GLB_REG_GPIO_21_DRV_UMSK (~(((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS)) +#define GLB_REG_GPIO_21_PU GLB_REG_GPIO_21_PU +#define GLB_REG_GPIO_21_PU_POS (20U) +#define GLB_REG_GPIO_21_PU_LEN (1U) +#define GLB_REG_GPIO_21_PU_MSK (((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS) +#define GLB_REG_GPIO_21_PU_UMSK (~(((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS)) +#define GLB_REG_GPIO_21_PD GLB_REG_GPIO_21_PD +#define GLB_REG_GPIO_21_PD_POS (21U) +#define GLB_REG_GPIO_21_PD_LEN (1U) +#define GLB_REG_GPIO_21_PD_MSK (((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS) +#define GLB_REG_GPIO_21_PD_UMSK (~(((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS)) +#define GLB_REG_GPIO_21_FUNC_SEL GLB_REG_GPIO_21_FUNC_SEL +#define GLB_REG_GPIO_21_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_21_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_21_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS) +#define GLB_REG_GPIO_21_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS)) + +/* 0x12C : GPIO_CFGCTL11 */ +#define GLB_GPIO_CFGCTL11_OFFSET (0x12C) +#define GLB_REG_GPIO_22_IE GLB_REG_GPIO_22_IE +#define GLB_REG_GPIO_22_IE_POS (0U) +#define GLB_REG_GPIO_22_IE_LEN (1U) +#define GLB_REG_GPIO_22_IE_MSK (((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS) +#define GLB_REG_GPIO_22_IE_UMSK (~(((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS)) +#define GLB_REG_GPIO_22_SMT GLB_REG_GPIO_22_SMT +#define GLB_REG_GPIO_22_SMT_POS (1U) +#define GLB_REG_GPIO_22_SMT_LEN (1U) +#define GLB_REG_GPIO_22_SMT_MSK (((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS) +#define GLB_REG_GPIO_22_SMT_UMSK (~(((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS)) +#define GLB_REG_GPIO_22_DRV GLB_REG_GPIO_22_DRV +#define GLB_REG_GPIO_22_DRV_POS (2U) +#define GLB_REG_GPIO_22_DRV_LEN (2U) +#define GLB_REG_GPIO_22_DRV_MSK (((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS) +#define GLB_REG_GPIO_22_DRV_UMSK (~(((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS)) +#define GLB_REG_GPIO_22_PU GLB_REG_GPIO_22_PU +#define GLB_REG_GPIO_22_PU_POS (4U) +#define GLB_REG_GPIO_22_PU_LEN (1U) +#define GLB_REG_GPIO_22_PU_MSK (((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS) +#define GLB_REG_GPIO_22_PU_UMSK (~(((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS)) +#define GLB_REG_GPIO_22_PD GLB_REG_GPIO_22_PD +#define GLB_REG_GPIO_22_PD_POS (5U) +#define GLB_REG_GPIO_22_PD_LEN (1U) +#define GLB_REG_GPIO_22_PD_MSK (((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS) +#define GLB_REG_GPIO_22_PD_UMSK (~(((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS)) +#define GLB_REG_GPIO_22_FUNC_SEL GLB_REG_GPIO_22_FUNC_SEL +#define GLB_REG_GPIO_22_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_22_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_22_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS) +#define GLB_REG_GPIO_22_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS)) +#define GLB_REG_GPIO_23_IE GLB_REG_GPIO_23_IE +#define GLB_REG_GPIO_23_IE_POS (16U) +#define GLB_REG_GPIO_23_IE_LEN (1U) +#define GLB_REG_GPIO_23_IE_MSK (((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS) +#define GLB_REG_GPIO_23_IE_UMSK (~(((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS)) +#define GLB_REG_GPIO_23_SMT GLB_REG_GPIO_23_SMT +#define GLB_REG_GPIO_23_SMT_POS (17U) +#define GLB_REG_GPIO_23_SMT_LEN (1U) +#define GLB_REG_GPIO_23_SMT_MSK (((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS) +#define GLB_REG_GPIO_23_SMT_UMSK (~(((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS)) +#define GLB_REG_GPIO_23_DRV GLB_REG_GPIO_23_DRV +#define GLB_REG_GPIO_23_DRV_POS (18U) +#define GLB_REG_GPIO_23_DRV_LEN (2U) +#define GLB_REG_GPIO_23_DRV_MSK (((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS) +#define GLB_REG_GPIO_23_DRV_UMSK (~(((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS)) +#define GLB_REG_GPIO_23_PU GLB_REG_GPIO_23_PU +#define GLB_REG_GPIO_23_PU_POS (20U) +#define GLB_REG_GPIO_23_PU_LEN (1U) +#define GLB_REG_GPIO_23_PU_MSK (((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS) +#define GLB_REG_GPIO_23_PU_UMSK (~(((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS)) +#define GLB_REG_GPIO_23_PD GLB_REG_GPIO_23_PD +#define GLB_REG_GPIO_23_PD_POS (21U) +#define GLB_REG_GPIO_23_PD_LEN (1U) +#define GLB_REG_GPIO_23_PD_MSK (((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS) +#define GLB_REG_GPIO_23_PD_UMSK (~(((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS)) + +/* 0x130 : GPIO_CFGCTL12 */ +#define GLB_GPIO_CFGCTL12_OFFSET (0x130) +#define GLB_REG_GPIO_24_IE GLB_REG_GPIO_24_IE +#define GLB_REG_GPIO_24_IE_POS (0U) +#define GLB_REG_GPIO_24_IE_LEN (1U) +#define GLB_REG_GPIO_24_IE_MSK (((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS) +#define GLB_REG_GPIO_24_IE_UMSK (~(((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS)) +#define GLB_REG_GPIO_24_SMT GLB_REG_GPIO_24_SMT +#define GLB_REG_GPIO_24_SMT_POS (1U) +#define GLB_REG_GPIO_24_SMT_LEN (1U) +#define GLB_REG_GPIO_24_SMT_MSK (((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS) +#define GLB_REG_GPIO_24_SMT_UMSK (~(((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS)) +#define GLB_REG_GPIO_24_DRV GLB_REG_GPIO_24_DRV +#define GLB_REG_GPIO_24_DRV_POS (2U) +#define GLB_REG_GPIO_24_DRV_LEN (2U) +#define GLB_REG_GPIO_24_DRV_MSK (((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS) +#define GLB_REG_GPIO_24_DRV_UMSK (~(((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS)) +#define GLB_REG_GPIO_24_PU GLB_REG_GPIO_24_PU +#define GLB_REG_GPIO_24_PU_POS (4U) +#define GLB_REG_GPIO_24_PU_LEN (1U) +#define GLB_REG_GPIO_24_PU_MSK (((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS) +#define GLB_REG_GPIO_24_PU_UMSK (~(((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS)) +#define GLB_REG_GPIO_24_PD GLB_REG_GPIO_24_PD +#define GLB_REG_GPIO_24_PD_POS (5U) +#define GLB_REG_GPIO_24_PD_LEN (1U) +#define GLB_REG_GPIO_24_PD_MSK (((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS) +#define GLB_REG_GPIO_24_PD_UMSK (~(((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS)) +#define GLB_REG_GPIO_25_IE GLB_REG_GPIO_25_IE +#define GLB_REG_GPIO_25_IE_POS (16U) +#define GLB_REG_GPIO_25_IE_LEN (1U) +#define GLB_REG_GPIO_25_IE_MSK (((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS) +#define GLB_REG_GPIO_25_IE_UMSK (~(((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS)) +#define GLB_REG_GPIO_25_SMT GLB_REG_GPIO_25_SMT +#define GLB_REG_GPIO_25_SMT_POS (17U) +#define GLB_REG_GPIO_25_SMT_LEN (1U) +#define GLB_REG_GPIO_25_SMT_MSK (((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS) +#define GLB_REG_GPIO_25_SMT_UMSK (~(((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS)) +#define GLB_REG_GPIO_25_DRV GLB_REG_GPIO_25_DRV +#define GLB_REG_GPIO_25_DRV_POS (18U) +#define GLB_REG_GPIO_25_DRV_LEN (2U) +#define GLB_REG_GPIO_25_DRV_MSK (((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS) +#define GLB_REG_GPIO_25_DRV_UMSK (~(((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS)) +#define GLB_REG_GPIO_25_PU GLB_REG_GPIO_25_PU +#define GLB_REG_GPIO_25_PU_POS (20U) +#define GLB_REG_GPIO_25_PU_LEN (1U) +#define GLB_REG_GPIO_25_PU_MSK (((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS) +#define GLB_REG_GPIO_25_PU_UMSK (~(((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS)) +#define GLB_REG_GPIO_25_PD GLB_REG_GPIO_25_PD +#define GLB_REG_GPIO_25_PD_POS (21U) +#define GLB_REG_GPIO_25_PD_LEN (1U) +#define GLB_REG_GPIO_25_PD_MSK (((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS) +#define GLB_REG_GPIO_25_PD_UMSK (~(((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS)) + +/* 0x134 : GPIO_CFGCTL13 */ +#define GLB_GPIO_CFGCTL13_OFFSET (0x134) +#define GLB_REG_GPIO_26_IE GLB_REG_GPIO_26_IE +#define GLB_REG_GPIO_26_IE_POS (0U) +#define GLB_REG_GPIO_26_IE_LEN (1U) +#define GLB_REG_GPIO_26_IE_MSK (((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS) +#define GLB_REG_GPIO_26_IE_UMSK (~(((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS)) +#define GLB_REG_GPIO_26_SMT GLB_REG_GPIO_26_SMT +#define GLB_REG_GPIO_26_SMT_POS (1U) +#define GLB_REG_GPIO_26_SMT_LEN (1U) +#define GLB_REG_GPIO_26_SMT_MSK (((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS) +#define GLB_REG_GPIO_26_SMT_UMSK (~(((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS)) +#define GLB_REG_GPIO_26_DRV GLB_REG_GPIO_26_DRV +#define GLB_REG_GPIO_26_DRV_POS (2U) +#define GLB_REG_GPIO_26_DRV_LEN (2U) +#define GLB_REG_GPIO_26_DRV_MSK (((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS) +#define GLB_REG_GPIO_26_DRV_UMSK (~(((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS)) +#define GLB_REG_GPIO_26_PU GLB_REG_GPIO_26_PU +#define GLB_REG_GPIO_26_PU_POS (4U) +#define GLB_REG_GPIO_26_PU_LEN (1U) +#define GLB_REG_GPIO_26_PU_MSK (((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS) +#define GLB_REG_GPIO_26_PU_UMSK (~(((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS)) +#define GLB_REG_GPIO_26_PD GLB_REG_GPIO_26_PD +#define GLB_REG_GPIO_26_PD_POS (5U) +#define GLB_REG_GPIO_26_PD_LEN (1U) +#define GLB_REG_GPIO_26_PD_MSK (((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS) +#define GLB_REG_GPIO_26_PD_UMSK (~(((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS)) +#define GLB_REG_GPIO_27_IE GLB_REG_GPIO_27_IE +#define GLB_REG_GPIO_27_IE_POS (16U) +#define GLB_REG_GPIO_27_IE_LEN (1U) +#define GLB_REG_GPIO_27_IE_MSK (((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS) +#define GLB_REG_GPIO_27_IE_UMSK (~(((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS)) +#define GLB_REG_GPIO_27_SMT GLB_REG_GPIO_27_SMT +#define GLB_REG_GPIO_27_SMT_POS (17U) +#define GLB_REG_GPIO_27_SMT_LEN (1U) +#define GLB_REG_GPIO_27_SMT_MSK (((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS) +#define GLB_REG_GPIO_27_SMT_UMSK (~(((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS)) +#define GLB_REG_GPIO_27_DRV GLB_REG_GPIO_27_DRV +#define GLB_REG_GPIO_27_DRV_POS (18U) +#define GLB_REG_GPIO_27_DRV_LEN (2U) +#define GLB_REG_GPIO_27_DRV_MSK (((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS) +#define GLB_REG_GPIO_27_DRV_UMSK (~(((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS)) +#define GLB_REG_GPIO_27_PU GLB_REG_GPIO_27_PU +#define GLB_REG_GPIO_27_PU_POS (20U) +#define GLB_REG_GPIO_27_PU_LEN (1U) +#define GLB_REG_GPIO_27_PU_MSK (((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS) +#define GLB_REG_GPIO_27_PU_UMSK (~(((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS)) +#define GLB_REG_GPIO_27_PD GLB_REG_GPIO_27_PD +#define GLB_REG_GPIO_27_PD_POS (21U) +#define GLB_REG_GPIO_27_PD_LEN (1U) +#define GLB_REG_GPIO_27_PD_MSK (((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS) +#define GLB_REG_GPIO_27_PD_UMSK (~(((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS)) + +/* 0x138 : GPIO_CFGCTL14 */ +#define GLB_GPIO_CFGCTL14_OFFSET (0x138) +#define GLB_REG_GPIO_28_IE GLB_REG_GPIO_28_IE +#define GLB_REG_GPIO_28_IE_POS (0U) +#define GLB_REG_GPIO_28_IE_LEN (1U) +#define GLB_REG_GPIO_28_IE_MSK (((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS) +#define GLB_REG_GPIO_28_IE_UMSK (~(((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS)) +#define GLB_REG_GPIO_28_SMT GLB_REG_GPIO_28_SMT +#define GLB_REG_GPIO_28_SMT_POS (1U) +#define GLB_REG_GPIO_28_SMT_LEN (1U) +#define GLB_REG_GPIO_28_SMT_MSK (((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS) +#define GLB_REG_GPIO_28_SMT_UMSK (~(((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS)) +#define GLB_REG_GPIO_28_DRV GLB_REG_GPIO_28_DRV +#define GLB_REG_GPIO_28_DRV_POS (2U) +#define GLB_REG_GPIO_28_DRV_LEN (2U) +#define GLB_REG_GPIO_28_DRV_MSK (((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS) +#define GLB_REG_GPIO_28_DRV_UMSK (~(((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS)) +#define GLB_REG_GPIO_28_PU GLB_REG_GPIO_28_PU +#define GLB_REG_GPIO_28_PU_POS (4U) +#define GLB_REG_GPIO_28_PU_LEN (1U) +#define GLB_REG_GPIO_28_PU_MSK (((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS) +#define GLB_REG_GPIO_28_PU_UMSK (~(((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS)) +#define GLB_REG_GPIO_28_PD GLB_REG_GPIO_28_PD +#define GLB_REG_GPIO_28_PD_POS (5U) +#define GLB_REG_GPIO_28_PD_LEN (1U) +#define GLB_REG_GPIO_28_PD_MSK (((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS) +#define GLB_REG_GPIO_28_PD_UMSK (~(((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS)) + +/* 0x180 : GPIO_CFGCTL30 */ +#define GLB_GPIO_CFGCTL30_OFFSET (0x180) +#define GLB_REG_GPIO_0_I GLB_REG_GPIO_0_I +#define GLB_REG_GPIO_0_I_POS (0U) +#define GLB_REG_GPIO_0_I_LEN (1U) +#define GLB_REG_GPIO_0_I_MSK (((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS) +#define GLB_REG_GPIO_0_I_UMSK (~(((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS)) +#define GLB_REG_GPIO_1_I GLB_REG_GPIO_1_I +#define GLB_REG_GPIO_1_I_POS (1U) +#define GLB_REG_GPIO_1_I_LEN (1U) +#define GLB_REG_GPIO_1_I_MSK (((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS) +#define GLB_REG_GPIO_1_I_UMSK (~(((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS)) +#define GLB_REG_GPIO_2_I GLB_REG_GPIO_2_I +#define GLB_REG_GPIO_2_I_POS (2U) +#define GLB_REG_GPIO_2_I_LEN (1U) +#define GLB_REG_GPIO_2_I_MSK (((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS) +#define GLB_REG_GPIO_2_I_UMSK (~(((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS)) +#define GLB_REG_GPIO_3_I GLB_REG_GPIO_3_I +#define GLB_REG_GPIO_3_I_POS (3U) +#define GLB_REG_GPIO_3_I_LEN (1U) +#define GLB_REG_GPIO_3_I_MSK (((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS) +#define GLB_REG_GPIO_3_I_UMSK (~(((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS)) +#define GLB_REG_GPIO_4_I GLB_REG_GPIO_4_I +#define GLB_REG_GPIO_4_I_POS (4U) +#define GLB_REG_GPIO_4_I_LEN (1U) +#define GLB_REG_GPIO_4_I_MSK (((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS) +#define GLB_REG_GPIO_4_I_UMSK (~(((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS)) +#define GLB_REG_GPIO_5_I GLB_REG_GPIO_5_I +#define GLB_REG_GPIO_5_I_POS (5U) +#define GLB_REG_GPIO_5_I_LEN (1U) +#define GLB_REG_GPIO_5_I_MSK (((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS) +#define GLB_REG_GPIO_5_I_UMSK (~(((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS)) +#define GLB_REG_GPIO_6_I GLB_REG_GPIO_6_I +#define GLB_REG_GPIO_6_I_POS (6U) +#define GLB_REG_GPIO_6_I_LEN (1U) +#define GLB_REG_GPIO_6_I_MSK (((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS) +#define GLB_REG_GPIO_6_I_UMSK (~(((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS)) +#define GLB_REG_GPIO_7_I GLB_REG_GPIO_7_I +#define GLB_REG_GPIO_7_I_POS (7U) +#define GLB_REG_GPIO_7_I_LEN (1U) +#define GLB_REG_GPIO_7_I_MSK (((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS) +#define GLB_REG_GPIO_7_I_UMSK (~(((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS)) +#define GLB_REG_GPIO_8_I GLB_REG_GPIO_8_I +#define GLB_REG_GPIO_8_I_POS (8U) +#define GLB_REG_GPIO_8_I_LEN (1U) +#define GLB_REG_GPIO_8_I_MSK (((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS) +#define GLB_REG_GPIO_8_I_UMSK (~(((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS)) +#define GLB_REG_GPIO_9_I GLB_REG_GPIO_9_I +#define GLB_REG_GPIO_9_I_POS (9U) +#define GLB_REG_GPIO_9_I_LEN (1U) +#define GLB_REG_GPIO_9_I_MSK (((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS) +#define GLB_REG_GPIO_9_I_UMSK (~(((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS)) +#define GLB_REG_GPIO_10_I GLB_REG_GPIO_10_I +#define GLB_REG_GPIO_10_I_POS (10U) +#define GLB_REG_GPIO_10_I_LEN (1U) +#define GLB_REG_GPIO_10_I_MSK (((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS) +#define GLB_REG_GPIO_10_I_UMSK (~(((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS)) +#define GLB_REG_GPIO_11_I GLB_REG_GPIO_11_I +#define GLB_REG_GPIO_11_I_POS (11U) +#define GLB_REG_GPIO_11_I_LEN (1U) +#define GLB_REG_GPIO_11_I_MSK (((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS) +#define GLB_REG_GPIO_11_I_UMSK (~(((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS)) +#define GLB_REG_GPIO_12_I GLB_REG_GPIO_12_I +#define GLB_REG_GPIO_12_I_POS (12U) +#define GLB_REG_GPIO_12_I_LEN (1U) +#define GLB_REG_GPIO_12_I_MSK (((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS) +#define GLB_REG_GPIO_12_I_UMSK (~(((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS)) +#define GLB_REG_GPIO_13_I GLB_REG_GPIO_13_I +#define GLB_REG_GPIO_13_I_POS (13U) +#define GLB_REG_GPIO_13_I_LEN (1U) +#define GLB_REG_GPIO_13_I_MSK (((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS) +#define GLB_REG_GPIO_13_I_UMSK (~(((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS)) +#define GLB_REG_GPIO_14_I GLB_REG_GPIO_14_I +#define GLB_REG_GPIO_14_I_POS (14U) +#define GLB_REG_GPIO_14_I_LEN (1U) +#define GLB_REG_GPIO_14_I_MSK (((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS) +#define GLB_REG_GPIO_14_I_UMSK (~(((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS)) +#define GLB_REG_GPIO_15_I GLB_REG_GPIO_15_I +#define GLB_REG_GPIO_15_I_POS (15U) +#define GLB_REG_GPIO_15_I_LEN (1U) +#define GLB_REG_GPIO_15_I_MSK (((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS) +#define GLB_REG_GPIO_15_I_UMSK (~(((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS)) +#define GLB_REG_GPIO_16_I GLB_REG_GPIO_16_I +#define GLB_REG_GPIO_16_I_POS (16U) +#define GLB_REG_GPIO_16_I_LEN (1U) +#define GLB_REG_GPIO_16_I_MSK (((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS) +#define GLB_REG_GPIO_16_I_UMSK (~(((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS)) +#define GLB_REG_GPIO_17_I GLB_REG_GPIO_17_I +#define GLB_REG_GPIO_17_I_POS (17U) +#define GLB_REG_GPIO_17_I_LEN (1U) +#define GLB_REG_GPIO_17_I_MSK (((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS) +#define GLB_REG_GPIO_17_I_UMSK (~(((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS)) +#define GLB_REG_GPIO_18_I GLB_REG_GPIO_18_I +#define GLB_REG_GPIO_18_I_POS (18U) +#define GLB_REG_GPIO_18_I_LEN (1U) +#define GLB_REG_GPIO_18_I_MSK (((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS) +#define GLB_REG_GPIO_18_I_UMSK (~(((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS)) +#define GLB_REG_GPIO_19_I GLB_REG_GPIO_19_I +#define GLB_REG_GPIO_19_I_POS (19U) +#define GLB_REG_GPIO_19_I_LEN (1U) +#define GLB_REG_GPIO_19_I_MSK (((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS) +#define GLB_REG_GPIO_19_I_UMSK (~(((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS)) +#define GLB_REG_GPIO_20_I GLB_REG_GPIO_20_I +#define GLB_REG_GPIO_20_I_POS (20U) +#define GLB_REG_GPIO_20_I_LEN (1U) +#define GLB_REG_GPIO_20_I_MSK (((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS) +#define GLB_REG_GPIO_20_I_UMSK (~(((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS)) +#define GLB_REG_GPIO_21_I GLB_REG_GPIO_21_I +#define GLB_REG_GPIO_21_I_POS (21U) +#define GLB_REG_GPIO_21_I_LEN (1U) +#define GLB_REG_GPIO_21_I_MSK (((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS) +#define GLB_REG_GPIO_21_I_UMSK (~(((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS)) +#define GLB_REG_GPIO_22_I GLB_REG_GPIO_22_I +#define GLB_REG_GPIO_22_I_POS (22U) +#define GLB_REG_GPIO_22_I_LEN (1U) +#define GLB_REG_GPIO_22_I_MSK (((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS) +#define GLB_REG_GPIO_22_I_UMSK (~(((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS)) + +/* 0x184 : GPIO_CFGCTL31 */ +#define GLB_GPIO_CFGCTL31_OFFSET (0x184) + +/* 0x188 : GPIO_CFGCTL32 */ +#define GLB_GPIO_CFGCTL32_OFFSET (0x188) +#define GLB_REG_GPIO_0_O GLB_REG_GPIO_0_O +#define GLB_REG_GPIO_0_O_POS (0U) +#define GLB_REG_GPIO_0_O_LEN (1U) +#define GLB_REG_GPIO_0_O_MSK (((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS) +#define GLB_REG_GPIO_0_O_UMSK (~(((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS)) +#define GLB_REG_GPIO_1_O GLB_REG_GPIO_1_O +#define GLB_REG_GPIO_1_O_POS (1U) +#define GLB_REG_GPIO_1_O_LEN (1U) +#define GLB_REG_GPIO_1_O_MSK (((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS) +#define GLB_REG_GPIO_1_O_UMSK (~(((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS)) +#define GLB_REG_GPIO_2_O GLB_REG_GPIO_2_O +#define GLB_REG_GPIO_2_O_POS (2U) +#define GLB_REG_GPIO_2_O_LEN (1U) +#define GLB_REG_GPIO_2_O_MSK (((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS) +#define GLB_REG_GPIO_2_O_UMSK (~(((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS)) +#define GLB_REG_GPIO_3_O GLB_REG_GPIO_3_O +#define GLB_REG_GPIO_3_O_POS (3U) +#define GLB_REG_GPIO_3_O_LEN (1U) +#define GLB_REG_GPIO_3_O_MSK (((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS) +#define GLB_REG_GPIO_3_O_UMSK (~(((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS)) +#define GLB_REG_GPIO_4_O GLB_REG_GPIO_4_O +#define GLB_REG_GPIO_4_O_POS (4U) +#define GLB_REG_GPIO_4_O_LEN (1U) +#define GLB_REG_GPIO_4_O_MSK (((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS) +#define GLB_REG_GPIO_4_O_UMSK (~(((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS)) +#define GLB_REG_GPIO_5_O GLB_REG_GPIO_5_O +#define GLB_REG_GPIO_5_O_POS (5U) +#define GLB_REG_GPIO_5_O_LEN (1U) +#define GLB_REG_GPIO_5_O_MSK (((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS) +#define GLB_REG_GPIO_5_O_UMSK (~(((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS)) +#define GLB_REG_GPIO_6_O GLB_REG_GPIO_6_O +#define GLB_REG_GPIO_6_O_POS (6U) +#define GLB_REG_GPIO_6_O_LEN (1U) +#define GLB_REG_GPIO_6_O_MSK (((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS) +#define GLB_REG_GPIO_6_O_UMSK (~(((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS)) +#define GLB_REG_GPIO_7_O GLB_REG_GPIO_7_O +#define GLB_REG_GPIO_7_O_POS (7U) +#define GLB_REG_GPIO_7_O_LEN (1U) +#define GLB_REG_GPIO_7_O_MSK (((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS) +#define GLB_REG_GPIO_7_O_UMSK (~(((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS)) +#define GLB_REG_GPIO_8_O GLB_REG_GPIO_8_O +#define GLB_REG_GPIO_8_O_POS (8U) +#define GLB_REG_GPIO_8_O_LEN (1U) +#define GLB_REG_GPIO_8_O_MSK (((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS) +#define GLB_REG_GPIO_8_O_UMSK (~(((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS)) +#define GLB_REG_GPIO_9_O GLB_REG_GPIO_9_O +#define GLB_REG_GPIO_9_O_POS (9U) +#define GLB_REG_GPIO_9_O_LEN (1U) +#define GLB_REG_GPIO_9_O_MSK (((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS) +#define GLB_REG_GPIO_9_O_UMSK (~(((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS)) +#define GLB_REG_GPIO_10_O GLB_REG_GPIO_10_O +#define GLB_REG_GPIO_10_O_POS (10U) +#define GLB_REG_GPIO_10_O_LEN (1U) +#define GLB_REG_GPIO_10_O_MSK (((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS) +#define GLB_REG_GPIO_10_O_UMSK (~(((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS)) +#define GLB_REG_GPIO_11_O GLB_REG_GPIO_11_O +#define GLB_REG_GPIO_11_O_POS (11U) +#define GLB_REG_GPIO_11_O_LEN (1U) +#define GLB_REG_GPIO_11_O_MSK (((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS) +#define GLB_REG_GPIO_11_O_UMSK (~(((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS)) +#define GLB_REG_GPIO_12_O GLB_REG_GPIO_12_O +#define GLB_REG_GPIO_12_O_POS (12U) +#define GLB_REG_GPIO_12_O_LEN (1U) +#define GLB_REG_GPIO_12_O_MSK (((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS) +#define GLB_REG_GPIO_12_O_UMSK (~(((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS)) +#define GLB_REG_GPIO_13_O GLB_REG_GPIO_13_O +#define GLB_REG_GPIO_13_O_POS (13U) +#define GLB_REG_GPIO_13_O_LEN (1U) +#define GLB_REG_GPIO_13_O_MSK (((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS) +#define GLB_REG_GPIO_13_O_UMSK (~(((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS)) +#define GLB_REG_GPIO_14_O GLB_REG_GPIO_14_O +#define GLB_REG_GPIO_14_O_POS (14U) +#define GLB_REG_GPIO_14_O_LEN (1U) +#define GLB_REG_GPIO_14_O_MSK (((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS) +#define GLB_REG_GPIO_14_O_UMSK (~(((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS)) +#define GLB_REG_GPIO_15_O GLB_REG_GPIO_15_O +#define GLB_REG_GPIO_15_O_POS (15U) +#define GLB_REG_GPIO_15_O_LEN (1U) +#define GLB_REG_GPIO_15_O_MSK (((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS) +#define GLB_REG_GPIO_15_O_UMSK (~(((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS)) +#define GLB_REG_GPIO_16_O GLB_REG_GPIO_16_O +#define GLB_REG_GPIO_16_O_POS (16U) +#define GLB_REG_GPIO_16_O_LEN (1U) +#define GLB_REG_GPIO_16_O_MSK (((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS) +#define GLB_REG_GPIO_16_O_UMSK (~(((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS)) +#define GLB_REG_GPIO_17_O GLB_REG_GPIO_17_O +#define GLB_REG_GPIO_17_O_POS (17U) +#define GLB_REG_GPIO_17_O_LEN (1U) +#define GLB_REG_GPIO_17_O_MSK (((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS) +#define GLB_REG_GPIO_17_O_UMSK (~(((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS)) +#define GLB_REG_GPIO_18_O GLB_REG_GPIO_18_O +#define GLB_REG_GPIO_18_O_POS (18U) +#define GLB_REG_GPIO_18_O_LEN (1U) +#define GLB_REG_GPIO_18_O_MSK (((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS) +#define GLB_REG_GPIO_18_O_UMSK (~(((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS)) +#define GLB_REG_GPIO_19_O GLB_REG_GPIO_19_O +#define GLB_REG_GPIO_19_O_POS (19U) +#define GLB_REG_GPIO_19_O_LEN (1U) +#define GLB_REG_GPIO_19_O_MSK (((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS) +#define GLB_REG_GPIO_19_O_UMSK (~(((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS)) +#define GLB_REG_GPIO_20_O GLB_REG_GPIO_20_O +#define GLB_REG_GPIO_20_O_POS (20U) +#define GLB_REG_GPIO_20_O_LEN (1U) +#define GLB_REG_GPIO_20_O_MSK (((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS) +#define GLB_REG_GPIO_20_O_UMSK (~(((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS)) +#define GLB_REG_GPIO_21_O GLB_REG_GPIO_21_O +#define GLB_REG_GPIO_21_O_POS (21U) +#define GLB_REG_GPIO_21_O_LEN (1U) +#define GLB_REG_GPIO_21_O_MSK (((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS) +#define GLB_REG_GPIO_21_O_UMSK (~(((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS)) +#define GLB_REG_GPIO_22_O GLB_REG_GPIO_22_O +#define GLB_REG_GPIO_22_O_POS (22U) +#define GLB_REG_GPIO_22_O_LEN (1U) +#define GLB_REG_GPIO_22_O_MSK (((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS) +#define GLB_REG_GPIO_22_O_UMSK (~(((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS)) + +/* 0x18C : GPIO_CFGCTL33 */ +#define GLB_GPIO_CFGCTL33_OFFSET (0x18C) + +/* 0x190 : GPIO_CFGCTL34 */ +#define GLB_GPIO_CFGCTL34_OFFSET (0x190) +#define GLB_REG_GPIO_0_OE GLB_REG_GPIO_0_OE +#define GLB_REG_GPIO_0_OE_POS (0U) +#define GLB_REG_GPIO_0_OE_LEN (1U) +#define GLB_REG_GPIO_0_OE_MSK (((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS) +#define GLB_REG_GPIO_0_OE_UMSK (~(((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS)) +#define GLB_REG_GPIO_1_OE GLB_REG_GPIO_1_OE +#define GLB_REG_GPIO_1_OE_POS (1U) +#define GLB_REG_GPIO_1_OE_LEN (1U) +#define GLB_REG_GPIO_1_OE_MSK (((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS) +#define GLB_REG_GPIO_1_OE_UMSK (~(((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS)) +#define GLB_REG_GPIO_2_OE GLB_REG_GPIO_2_OE +#define GLB_REG_GPIO_2_OE_POS (2U) +#define GLB_REG_GPIO_2_OE_LEN (1U) +#define GLB_REG_GPIO_2_OE_MSK (((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS) +#define GLB_REG_GPIO_2_OE_UMSK (~(((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS)) +#define GLB_REG_GPIO_3_OE GLB_REG_GPIO_3_OE +#define GLB_REG_GPIO_3_OE_POS (3U) +#define GLB_REG_GPIO_3_OE_LEN (1U) +#define GLB_REG_GPIO_3_OE_MSK (((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS) +#define GLB_REG_GPIO_3_OE_UMSK (~(((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS)) +#define GLB_REG_GPIO_4_OE GLB_REG_GPIO_4_OE +#define GLB_REG_GPIO_4_OE_POS (4U) +#define GLB_REG_GPIO_4_OE_LEN (1U) +#define GLB_REG_GPIO_4_OE_MSK (((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS) +#define GLB_REG_GPIO_4_OE_UMSK (~(((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS)) +#define GLB_REG_GPIO_5_OE GLB_REG_GPIO_5_OE +#define GLB_REG_GPIO_5_OE_POS (5U) +#define GLB_REG_GPIO_5_OE_LEN (1U) +#define GLB_REG_GPIO_5_OE_MSK (((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS) +#define GLB_REG_GPIO_5_OE_UMSK (~(((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS)) +#define GLB_REG_GPIO_6_OE GLB_REG_GPIO_6_OE +#define GLB_REG_GPIO_6_OE_POS (6U) +#define GLB_REG_GPIO_6_OE_LEN (1U) +#define GLB_REG_GPIO_6_OE_MSK (((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS) +#define GLB_REG_GPIO_6_OE_UMSK (~(((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS)) +#define GLB_REG_GPIO_7_OE GLB_REG_GPIO_7_OE +#define GLB_REG_GPIO_7_OE_POS (7U) +#define GLB_REG_GPIO_7_OE_LEN (1U) +#define GLB_REG_GPIO_7_OE_MSK (((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS) +#define GLB_REG_GPIO_7_OE_UMSK (~(((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS)) +#define GLB_REG_GPIO_8_OE GLB_REG_GPIO_8_OE +#define GLB_REG_GPIO_8_OE_POS (8U) +#define GLB_REG_GPIO_8_OE_LEN (1U) +#define GLB_REG_GPIO_8_OE_MSK (((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS) +#define GLB_REG_GPIO_8_OE_UMSK (~(((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS)) +#define GLB_REG_GPIO_9_OE GLB_REG_GPIO_9_OE +#define GLB_REG_GPIO_9_OE_POS (9U) +#define GLB_REG_GPIO_9_OE_LEN (1U) +#define GLB_REG_GPIO_9_OE_MSK (((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS) +#define GLB_REG_GPIO_9_OE_UMSK (~(((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS)) +#define GLB_REG_GPIO_10_OE GLB_REG_GPIO_10_OE +#define GLB_REG_GPIO_10_OE_POS (10U) +#define GLB_REG_GPIO_10_OE_LEN (1U) +#define GLB_REG_GPIO_10_OE_MSK (((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS) +#define GLB_REG_GPIO_10_OE_UMSK (~(((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS)) +#define GLB_REG_GPIO_11_OE GLB_REG_GPIO_11_OE +#define GLB_REG_GPIO_11_OE_POS (11U) +#define GLB_REG_GPIO_11_OE_LEN (1U) +#define GLB_REG_GPIO_11_OE_MSK (((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS) +#define GLB_REG_GPIO_11_OE_UMSK (~(((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS)) +#define GLB_REG_GPIO_12_OE GLB_REG_GPIO_12_OE +#define GLB_REG_GPIO_12_OE_POS (12U) +#define GLB_REG_GPIO_12_OE_LEN (1U) +#define GLB_REG_GPIO_12_OE_MSK (((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS) +#define GLB_REG_GPIO_12_OE_UMSK (~(((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS)) +#define GLB_REG_GPIO_13_OE GLB_REG_GPIO_13_OE +#define GLB_REG_GPIO_13_OE_POS (13U) +#define GLB_REG_GPIO_13_OE_LEN (1U) +#define GLB_REG_GPIO_13_OE_MSK (((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS) +#define GLB_REG_GPIO_13_OE_UMSK (~(((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS)) +#define GLB_REG_GPIO_14_OE GLB_REG_GPIO_14_OE +#define GLB_REG_GPIO_14_OE_POS (14U) +#define GLB_REG_GPIO_14_OE_LEN (1U) +#define GLB_REG_GPIO_14_OE_MSK (((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS) +#define GLB_REG_GPIO_14_OE_UMSK (~(((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS)) +#define GLB_REG_GPIO_15_OE GLB_REG_GPIO_15_OE +#define GLB_REG_GPIO_15_OE_POS (15U) +#define GLB_REG_GPIO_15_OE_LEN (1U) +#define GLB_REG_GPIO_15_OE_MSK (((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS) +#define GLB_REG_GPIO_15_OE_UMSK (~(((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS)) +#define GLB_REG_GPIO_16_OE GLB_REG_GPIO_16_OE +#define GLB_REG_GPIO_16_OE_POS (16U) +#define GLB_REG_GPIO_16_OE_LEN (1U) +#define GLB_REG_GPIO_16_OE_MSK (((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS) +#define GLB_REG_GPIO_16_OE_UMSK (~(((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS)) +#define GLB_REG_GPIO_17_OE GLB_REG_GPIO_17_OE +#define GLB_REG_GPIO_17_OE_POS (17U) +#define GLB_REG_GPIO_17_OE_LEN (1U) +#define GLB_REG_GPIO_17_OE_MSK (((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS) +#define GLB_REG_GPIO_17_OE_UMSK (~(((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS)) +#define GLB_REG_GPIO_18_OE GLB_REG_GPIO_18_OE +#define GLB_REG_GPIO_18_OE_POS (18U) +#define GLB_REG_GPIO_18_OE_LEN (1U) +#define GLB_REG_GPIO_18_OE_MSK (((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS) +#define GLB_REG_GPIO_18_OE_UMSK (~(((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS)) +#define GLB_REG_GPIO_19_OE GLB_REG_GPIO_19_OE +#define GLB_REG_GPIO_19_OE_POS (19U) +#define GLB_REG_GPIO_19_OE_LEN (1U) +#define GLB_REG_GPIO_19_OE_MSK (((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS) +#define GLB_REG_GPIO_19_OE_UMSK (~(((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS)) +#define GLB_REG_GPIO_20_OE GLB_REG_GPIO_20_OE +#define GLB_REG_GPIO_20_OE_POS (20U) +#define GLB_REG_GPIO_20_OE_LEN (1U) +#define GLB_REG_GPIO_20_OE_MSK (((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS) +#define GLB_REG_GPIO_20_OE_UMSK (~(((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS)) +#define GLB_REG_GPIO_21_OE GLB_REG_GPIO_21_OE +#define GLB_REG_GPIO_21_OE_POS (21U) +#define GLB_REG_GPIO_21_OE_LEN (1U) +#define GLB_REG_GPIO_21_OE_MSK (((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS) +#define GLB_REG_GPIO_21_OE_UMSK (~(((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS)) +#define GLB_REG_GPIO_22_OE GLB_REG_GPIO_22_OE +#define GLB_REG_GPIO_22_OE_POS (22U) +#define GLB_REG_GPIO_22_OE_LEN (1U) +#define GLB_REG_GPIO_22_OE_MSK (((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS) +#define GLB_REG_GPIO_22_OE_UMSK (~(((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS)) + +/* 0x194 : GPIO_CFGCTL35 */ +#define GLB_GPIO_CFGCTL35_OFFSET (0x194) + +/* 0x1A0 : GPIO_INT_MASK1 */ +#define GLB_GPIO_INT_MASK1_OFFSET (0x1A0) +#define GLB_REG_GPIO_INT_MASK1 GLB_REG_GPIO_INT_MASK1 +#define GLB_REG_GPIO_INT_MASK1_POS (0U) +#define GLB_REG_GPIO_INT_MASK1_LEN (32U) +#define GLB_REG_GPIO_INT_MASK1_MSK (((1U << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS) +#define GLB_REG_GPIO_INT_MASK1_UMSK (~(((1U << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS)) + +/* 0x1A8 : GPIO_INT_STAT1 */ +#define GLB_GPIO_INT_STAT1_OFFSET (0x1A8) +#define GLB_GPIO_INT_STAT1 GLB_GPIO_INT_STAT1 +#define GLB_GPIO_INT_STAT1_POS (0U) +#define GLB_GPIO_INT_STAT1_LEN (32U) +#define GLB_GPIO_INT_STAT1_MSK (((1U << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS) +#define GLB_GPIO_INT_STAT1_UMSK (~(((1U << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS)) + +/* 0x1B0 : GPIO_INT_CLR1 */ +#define GLB_GPIO_INT_CLR1_OFFSET (0x1B0) +#define GLB_REG_GPIO_INT_CLR1 GLB_REG_GPIO_INT_CLR1 +#define GLB_REG_GPIO_INT_CLR1_POS (0U) +#define GLB_REG_GPIO_INT_CLR1_LEN (32U) +#define GLB_REG_GPIO_INT_CLR1_MSK (((1U << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS) +#define GLB_REG_GPIO_INT_CLR1_UMSK (~(((1U << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS)) + +/* 0x1C0 : GPIO_INT_MODE_SET1 */ +#define GLB_GPIO_INT_MODE_SET1_OFFSET (0x1C0) +#define GLB_REG_GPIO_INT_MODE_SET1 GLB_REG_GPIO_INT_MODE_SET1 +#define GLB_REG_GPIO_INT_MODE_SET1_POS (0U) +#define GLB_REG_GPIO_INT_MODE_SET1_LEN (32U) +#define GLB_REG_GPIO_INT_MODE_SET1_MSK (((1U << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET1_POS) +#define GLB_REG_GPIO_INT_MODE_SET1_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET1_POS)) + +/* 0x1C4 : GPIO_INT_MODE_SET2 */ +#define GLB_GPIO_INT_MODE_SET2_OFFSET (0x1C4) +#define GLB_REG_GPIO_INT_MODE_SET2 GLB_REG_GPIO_INT_MODE_SET2 +#define GLB_REG_GPIO_INT_MODE_SET2_POS (0U) +#define GLB_REG_GPIO_INT_MODE_SET2_LEN (32U) +#define GLB_REG_GPIO_INT_MODE_SET2_MSK (((1U << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET2_POS) +#define GLB_REG_GPIO_INT_MODE_SET2_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET2_POS)) + +/* 0x1C8 : GPIO_INT_MODE_SET3 */ +#define GLB_GPIO_INT_MODE_SET3_OFFSET (0x1C8) +#define GLB_REG_GPIO_INT_MODE_SET3 GLB_REG_GPIO_INT_MODE_SET3 +#define GLB_REG_GPIO_INT_MODE_SET3_POS (0U) +#define GLB_REG_GPIO_INT_MODE_SET3_LEN (32U) +#define GLB_REG_GPIO_INT_MODE_SET3_MSK (((1U << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET3_POS) +#define GLB_REG_GPIO_INT_MODE_SET3_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET3_POS)) + +/* 0x224 : led_driver */ +#define GLB_LED_DRIVER_OFFSET (0x224) +#define GLB_LED_DIN_REG GLB_LED_DIN_REG +#define GLB_LED_DIN_REG_POS (0U) +#define GLB_LED_DIN_REG_LEN (1U) +#define GLB_LED_DIN_REG_MSK (((1U << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS) +#define GLB_LED_DIN_REG_UMSK (~(((1U << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS)) +#define GLB_LED_DIN_SEL GLB_LED_DIN_SEL +#define GLB_LED_DIN_SEL_POS (1U) +#define GLB_LED_DIN_SEL_LEN (1U) +#define GLB_LED_DIN_SEL_MSK (((1U << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS) +#define GLB_LED_DIN_SEL_UMSK (~(((1U << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS)) +#define GLB_LED_DIN_POLARITY_SEL GLB_LED_DIN_POLARITY_SEL +#define GLB_LED_DIN_POLARITY_SEL_POS (2U) +#define GLB_LED_DIN_POLARITY_SEL_LEN (1U) +#define GLB_LED_DIN_POLARITY_SEL_MSK (((1U << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) << GLB_LED_DIN_POLARITY_SEL_POS) +#define GLB_LED_DIN_POLARITY_SEL_UMSK (~(((1U << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) << GLB_LED_DIN_POLARITY_SEL_POS)) +#define GLB_LEDDRV_IBIAS GLB_LEDDRV_IBIAS +#define GLB_LEDDRV_IBIAS_POS (4U) +#define GLB_LEDDRV_IBIAS_LEN (4U) +#define GLB_LEDDRV_IBIAS_MSK (((1U << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS) +#define GLB_LEDDRV_IBIAS_UMSK (~(((1U << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS)) +#define GLB_IR_RX_GPIO_SEL GLB_IR_RX_GPIO_SEL +#define GLB_IR_RX_GPIO_SEL_POS (8U) +#define GLB_IR_RX_GPIO_SEL_LEN (2U) +#define GLB_IR_RX_GPIO_SEL_MSK (((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS) +#define GLB_IR_RX_GPIO_SEL_UMSK (~(((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS)) +#define GLB_PU_LEDDRV GLB_PU_LEDDRV +#define GLB_PU_LEDDRV_POS (31U) +#define GLB_PU_LEDDRV_LEN (1U) +#define GLB_PU_LEDDRV_MSK (((1U << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS) +#define GLB_PU_LEDDRV_UMSK (~(((1U << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS)) + +/* 0x308 : gpdac_ctrl */ +#define GLB_GPDAC_CTRL_OFFSET (0x308) +#define GLB_GPDACA_RSTN_ANA GLB_GPDACA_RSTN_ANA +#define GLB_GPDACA_RSTN_ANA_POS (0U) +#define GLB_GPDACA_RSTN_ANA_LEN (1U) +#define GLB_GPDACA_RSTN_ANA_MSK (((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS) +#define GLB_GPDACA_RSTN_ANA_UMSK (~(((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS)) +#define GLB_GPDACB_RSTN_ANA GLB_GPDACB_RSTN_ANA +#define GLB_GPDACB_RSTN_ANA_POS (1U) +#define GLB_GPDACB_RSTN_ANA_LEN (1U) +#define GLB_GPDACB_RSTN_ANA_MSK (((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS) +#define GLB_GPDACB_RSTN_ANA_UMSK (~(((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS)) +#define GLB_GPDAC_TEST_EN GLB_GPDAC_TEST_EN +#define GLB_GPDAC_TEST_EN_POS (7U) +#define GLB_GPDAC_TEST_EN_LEN (1U) +#define GLB_GPDAC_TEST_EN_MSK (((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS) +#define GLB_GPDAC_TEST_EN_UMSK (~(((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS)) +#define GLB_GPDAC_REF_SEL GLB_GPDAC_REF_SEL +#define GLB_GPDAC_REF_SEL_POS (8U) +#define GLB_GPDAC_REF_SEL_LEN (1U) +#define GLB_GPDAC_REF_SEL_MSK (((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS) +#define GLB_GPDAC_REF_SEL_UMSK (~(((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS)) +#define GLB_GPDAC_TEST_SEL GLB_GPDAC_TEST_SEL +#define GLB_GPDAC_TEST_SEL_POS (9U) +#define GLB_GPDAC_TEST_SEL_LEN (3U) +#define GLB_GPDAC_TEST_SEL_MSK (((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS) +#define GLB_GPDAC_TEST_SEL_UMSK (~(((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS)) +#define GLB_GPDAC_RESERVED GLB_GPDAC_RESERVED +#define GLB_GPDAC_RESERVED_POS (24U) +#define GLB_GPDAC_RESERVED_LEN (8U) +#define GLB_GPDAC_RESERVED_MSK (((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS) +#define GLB_GPDAC_RESERVED_UMSK (~(((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS)) + +/* 0x30C : gpdac_actrl */ +#define GLB_GPDAC_ACTRL_OFFSET (0x30C) +#define GLB_GPDAC_A_EN GLB_GPDAC_A_EN +#define GLB_GPDAC_A_EN_POS (0U) +#define GLB_GPDAC_A_EN_LEN (1U) +#define GLB_GPDAC_A_EN_MSK (((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS) +#define GLB_GPDAC_A_EN_UMSK (~(((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS)) +#define GLB_GPDAC_IOA_EN GLB_GPDAC_IOA_EN +#define GLB_GPDAC_IOA_EN_POS (1U) +#define GLB_GPDAC_IOA_EN_LEN (1U) +#define GLB_GPDAC_IOA_EN_MSK (((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS) +#define GLB_GPDAC_IOA_EN_UMSK (~(((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS)) +#define GLB_GPDAC_A_RNG GLB_GPDAC_A_RNG +#define GLB_GPDAC_A_RNG_POS (18U) +#define GLB_GPDAC_A_RNG_LEN (2U) +#define GLB_GPDAC_A_RNG_MSK (((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS) +#define GLB_GPDAC_A_RNG_UMSK (~(((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS)) +#define GLB_GPDAC_A_OUTMUX GLB_GPDAC_A_OUTMUX +#define GLB_GPDAC_A_OUTMUX_POS (20U) +#define GLB_GPDAC_A_OUTMUX_LEN (3U) +#define GLB_GPDAC_A_OUTMUX_MSK (((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS) +#define GLB_GPDAC_A_OUTMUX_UMSK (~(((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS)) + +/* 0x310 : gpdac_bctrl */ +#define GLB_GPDAC_BCTRL_OFFSET (0x310) +#define GLB_GPDAC_B_EN GLB_GPDAC_B_EN +#define GLB_GPDAC_B_EN_POS (0U) +#define GLB_GPDAC_B_EN_LEN (1U) +#define GLB_GPDAC_B_EN_MSK (((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS) +#define GLB_GPDAC_B_EN_UMSK (~(((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS)) +#define GLB_GPDAC_IOB_EN GLB_GPDAC_IOB_EN +#define GLB_GPDAC_IOB_EN_POS (1U) +#define GLB_GPDAC_IOB_EN_LEN (1U) +#define GLB_GPDAC_IOB_EN_MSK (((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS) +#define GLB_GPDAC_IOB_EN_UMSK (~(((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS)) +#define GLB_GPDAC_B_RNG GLB_GPDAC_B_RNG +#define GLB_GPDAC_B_RNG_POS (18U) +#define GLB_GPDAC_B_RNG_LEN (2U) +#define GLB_GPDAC_B_RNG_MSK (((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS) +#define GLB_GPDAC_B_RNG_UMSK (~(((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS)) +#define GLB_GPDAC_B_OUTMUX GLB_GPDAC_B_OUTMUX +#define GLB_GPDAC_B_OUTMUX_POS (20U) +#define GLB_GPDAC_B_OUTMUX_LEN (3U) +#define GLB_GPDAC_B_OUTMUX_MSK (((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS) +#define GLB_GPDAC_B_OUTMUX_UMSK (~(((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS)) + +/* 0x314 : gpdac_data */ +#define GLB_GPDAC_DATA_OFFSET (0x314) +#define GLB_GPDAC_B_DATA GLB_GPDAC_B_DATA +#define GLB_GPDAC_B_DATA_POS (0U) +#define GLB_GPDAC_B_DATA_LEN (10U) +#define GLB_GPDAC_B_DATA_MSK (((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS) +#define GLB_GPDAC_B_DATA_UMSK (~(((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS)) +#define GLB_GPDAC_A_DATA GLB_GPDAC_A_DATA +#define GLB_GPDAC_A_DATA_POS (16U) +#define GLB_GPDAC_A_DATA_LEN (10U) +#define GLB_GPDAC_A_DATA_MSK (((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS) +#define GLB_GPDAC_A_DATA_UMSK (~(((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS)) + +/* 0xF00 : tzc_glb_ctrl_0 */ +#define GLB_TZC_GLB_CTRL_0_OFFSET (0xF00) +#define GLB_TZC_GLB_SWRST_S00_LOCK GLB_TZC_GLB_SWRST_S00_LOCK +#define GLB_TZC_GLB_SWRST_S00_LOCK_POS (0U) +#define GLB_TZC_GLB_SWRST_S00_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S00_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S00_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S00_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S00_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S01_LOCK GLB_TZC_GLB_SWRST_S01_LOCK +#define GLB_TZC_GLB_SWRST_S01_LOCK_POS (1U) +#define GLB_TZC_GLB_SWRST_S01_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S01_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S01_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S01_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S01_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S30_LOCK GLB_TZC_GLB_SWRST_S30_LOCK +#define GLB_TZC_GLB_SWRST_S30_LOCK_POS (8U) +#define GLB_TZC_GLB_SWRST_S30_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S30_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S30_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S30_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S30_LOCK_POS)) +#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK GLB_TZC_GLB_CTRL_PWRON_RST_LOCK +#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS (12U) +#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN (1U) +#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_MSK (((1U << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS) +#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS)) +#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK GLB_TZC_GLB_CTRL_CPU_RESET_LOCK +#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS (13U) +#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN (1U) +#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_MSK (((1U << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS) +#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS)) +#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK GLB_TZC_GLB_CTRL_SYS_RESET_LOCK +#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS (14U) +#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN (1U) +#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_MSK (((1U << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS) +#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS)) +#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK +#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS (15U) +#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN (1U) +#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_MSK (((1U << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS) +#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS)) +#define GLB_TZC_GLB_MISC_LOCK GLB_TZC_GLB_MISC_LOCK +#define GLB_TZC_GLB_MISC_LOCK_POS (25U) +#define GLB_TZC_GLB_MISC_LOCK_LEN (1U) +#define GLB_TZC_GLB_MISC_LOCK_MSK (((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS) +#define GLB_TZC_GLB_MISC_LOCK_UMSK (~(((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS)) +#define GLB_TZC_GLB_SRAM_LOCK GLB_TZC_GLB_SRAM_LOCK +#define GLB_TZC_GLB_SRAM_LOCK_POS (26U) +#define GLB_TZC_GLB_SRAM_LOCK_LEN (1U) +#define GLB_TZC_GLB_SRAM_LOCK_MSK (((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS) +#define GLB_TZC_GLB_SRAM_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS)) +#define GLB_TZC_GLB_L2C_LOCK GLB_TZC_GLB_L2C_LOCK +#define GLB_TZC_GLB_L2C_LOCK_POS (27U) +#define GLB_TZC_GLB_L2C_LOCK_LEN (1U) +#define GLB_TZC_GLB_L2C_LOCK_MSK (((1U << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS) +#define GLB_TZC_GLB_L2C_LOCK_UMSK (~(((1U << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS)) +#define GLB_TZC_GLB_BMX_LOCK GLB_TZC_GLB_BMX_LOCK +#define GLB_TZC_GLB_BMX_LOCK_POS (28U) +#define GLB_TZC_GLB_BMX_LOCK_LEN (1U) +#define GLB_TZC_GLB_BMX_LOCK_MSK (((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS) +#define GLB_TZC_GLB_BMX_LOCK_UMSK (~(((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS)) +#define GLB_TZC_GLB_DBG_LOCK GLB_TZC_GLB_DBG_LOCK +#define GLB_TZC_GLB_DBG_LOCK_POS (29U) +#define GLB_TZC_GLB_DBG_LOCK_LEN (1U) +#define GLB_TZC_GLB_DBG_LOCK_MSK (((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS) +#define GLB_TZC_GLB_DBG_LOCK_UMSK (~(((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS)) +#define GLB_TZC_GLB_MBIST_LOCK GLB_TZC_GLB_MBIST_LOCK +#define GLB_TZC_GLB_MBIST_LOCK_POS (30U) +#define GLB_TZC_GLB_MBIST_LOCK_LEN (1U) +#define GLB_TZC_GLB_MBIST_LOCK_MSK (((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS) +#define GLB_TZC_GLB_MBIST_LOCK_UMSK (~(((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS)) +#define GLB_TZC_GLB_CLK_LOCK GLB_TZC_GLB_CLK_LOCK +#define GLB_TZC_GLB_CLK_LOCK_POS (31U) +#define GLB_TZC_GLB_CLK_LOCK_LEN (1U) +#define GLB_TZC_GLB_CLK_LOCK_MSK (((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS) +#define GLB_TZC_GLB_CLK_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS)) + +/* 0xF04 : tzc_glb_ctrl_1 */ +#define GLB_TZC_GLB_CTRL_1_OFFSET (0xF04) +#define GLB_TZC_GLB_SWRST_S20_LOCK GLB_TZC_GLB_SWRST_S20_LOCK +#define GLB_TZC_GLB_SWRST_S20_LOCK_POS (0U) +#define GLB_TZC_GLB_SWRST_S20_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S20_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S20_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S20_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S20_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S21_LOCK GLB_TZC_GLB_SWRST_S21_LOCK +#define GLB_TZC_GLB_SWRST_S21_LOCK_POS (1U) +#define GLB_TZC_GLB_SWRST_S21_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S21_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S21_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S21_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S21_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S22_LOCK GLB_TZC_GLB_SWRST_S22_LOCK +#define GLB_TZC_GLB_SWRST_S22_LOCK_POS (2U) +#define GLB_TZC_GLB_SWRST_S22_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S22_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S22_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S22_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S22_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S23_LOCK GLB_TZC_GLB_SWRST_S23_LOCK +#define GLB_TZC_GLB_SWRST_S23_LOCK_POS (3U) +#define GLB_TZC_GLB_SWRST_S23_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S23_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S23_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S23_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S23_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S24_LOCK GLB_TZC_GLB_SWRST_S24_LOCK +#define GLB_TZC_GLB_SWRST_S24_LOCK_POS (4U) +#define GLB_TZC_GLB_SWRST_S24_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S24_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S24_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S24_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S24_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S25_LOCK GLB_TZC_GLB_SWRST_S25_LOCK +#define GLB_TZC_GLB_SWRST_S25_LOCK_POS (5U) +#define GLB_TZC_GLB_SWRST_S25_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S25_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S25_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S25_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S25_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S26_LOCK GLB_TZC_GLB_SWRST_S26_LOCK +#define GLB_TZC_GLB_SWRST_S26_LOCK_POS (6U) +#define GLB_TZC_GLB_SWRST_S26_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S26_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S26_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S26_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S26_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S27_LOCK GLB_TZC_GLB_SWRST_S27_LOCK +#define GLB_TZC_GLB_SWRST_S27_LOCK_POS (7U) +#define GLB_TZC_GLB_SWRST_S27_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S27_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S27_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S27_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S27_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S28_LOCK GLB_TZC_GLB_SWRST_S28_LOCK +#define GLB_TZC_GLB_SWRST_S28_LOCK_POS (8U) +#define GLB_TZC_GLB_SWRST_S28_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S28_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S28_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S28_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S28_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S29_LOCK GLB_TZC_GLB_SWRST_S29_LOCK +#define GLB_TZC_GLB_SWRST_S29_LOCK_POS (9U) +#define GLB_TZC_GLB_SWRST_S29_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S29_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S29_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S29_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S29_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S2A_LOCK GLB_TZC_GLB_SWRST_S2A_LOCK +#define GLB_TZC_GLB_SWRST_S2A_LOCK_POS (10U) +#define GLB_TZC_GLB_SWRST_S2A_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2A_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2A_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S2A_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2A_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S2B_LOCK GLB_TZC_GLB_SWRST_S2B_LOCK +#define GLB_TZC_GLB_SWRST_S2B_LOCK_POS (11U) +#define GLB_TZC_GLB_SWRST_S2B_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2B_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2B_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S2B_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2B_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S2C_LOCK GLB_TZC_GLB_SWRST_S2C_LOCK +#define GLB_TZC_GLB_SWRST_S2C_LOCK_POS (12U) +#define GLB_TZC_GLB_SWRST_S2C_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2C_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2C_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S2C_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2C_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S2D_LOCK GLB_TZC_GLB_SWRST_S2D_LOCK +#define GLB_TZC_GLB_SWRST_S2D_LOCK_POS (13U) +#define GLB_TZC_GLB_SWRST_S2D_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2D_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2D_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S2D_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2D_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S2E_LOCK GLB_TZC_GLB_SWRST_S2E_LOCK +#define GLB_TZC_GLB_SWRST_S2E_LOCK_POS (14U) +#define GLB_TZC_GLB_SWRST_S2E_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2E_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2E_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S2E_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2E_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S2F_LOCK GLB_TZC_GLB_SWRST_S2F_LOCK +#define GLB_TZC_GLB_SWRST_S2F_LOCK_POS (15U) +#define GLB_TZC_GLB_SWRST_S2F_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S2F_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2F_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S2F_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2F_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S10_LOCK GLB_TZC_GLB_SWRST_S10_LOCK +#define GLB_TZC_GLB_SWRST_S10_LOCK_POS (16U) +#define GLB_TZC_GLB_SWRST_S10_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S10_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S10_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S10_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S10_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S11_LOCK GLB_TZC_GLB_SWRST_S11_LOCK +#define GLB_TZC_GLB_SWRST_S11_LOCK_POS (17U) +#define GLB_TZC_GLB_SWRST_S11_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S11_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S11_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S11_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S11_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S12_LOCK GLB_TZC_GLB_SWRST_S12_LOCK +#define GLB_TZC_GLB_SWRST_S12_LOCK_POS (18U) +#define GLB_TZC_GLB_SWRST_S12_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S12_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S12_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S12_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S12_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S13_LOCK GLB_TZC_GLB_SWRST_S13_LOCK +#define GLB_TZC_GLB_SWRST_S13_LOCK_POS (19U) +#define GLB_TZC_GLB_SWRST_S13_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S13_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S13_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S13_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S13_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S14_LOCK GLB_TZC_GLB_SWRST_S14_LOCK +#define GLB_TZC_GLB_SWRST_S14_LOCK_POS (20U) +#define GLB_TZC_GLB_SWRST_S14_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S14_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S14_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S14_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S14_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S15_LOCK GLB_TZC_GLB_SWRST_S15_LOCK +#define GLB_TZC_GLB_SWRST_S15_LOCK_POS (21U) +#define GLB_TZC_GLB_SWRST_S15_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S15_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S15_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S15_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S15_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S16_LOCK GLB_TZC_GLB_SWRST_S16_LOCK +#define GLB_TZC_GLB_SWRST_S16_LOCK_POS (22U) +#define GLB_TZC_GLB_SWRST_S16_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S16_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S16_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S16_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S16_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S17_LOCK GLB_TZC_GLB_SWRST_S17_LOCK +#define GLB_TZC_GLB_SWRST_S17_LOCK_POS (23U) +#define GLB_TZC_GLB_SWRST_S17_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S17_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S17_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S17_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S17_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S18_LOCK GLB_TZC_GLB_SWRST_S18_LOCK +#define GLB_TZC_GLB_SWRST_S18_LOCK_POS (24U) +#define GLB_TZC_GLB_SWRST_S18_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S18_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S18_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S18_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S18_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S19_LOCK GLB_TZC_GLB_SWRST_S19_LOCK +#define GLB_TZC_GLB_SWRST_S19_LOCK_POS (25U) +#define GLB_TZC_GLB_SWRST_S19_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S19_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S19_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S19_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S19_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S1A_LOCK GLB_TZC_GLB_SWRST_S1A_LOCK +#define GLB_TZC_GLB_SWRST_S1A_LOCK_POS (26U) +#define GLB_TZC_GLB_SWRST_S1A_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1A_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1A_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S1A_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1A_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S1B_LOCK GLB_TZC_GLB_SWRST_S1B_LOCK +#define GLB_TZC_GLB_SWRST_S1B_LOCK_POS (27U) +#define GLB_TZC_GLB_SWRST_S1B_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1B_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1B_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S1B_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1B_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S1C_LOCK GLB_TZC_GLB_SWRST_S1C_LOCK +#define GLB_TZC_GLB_SWRST_S1C_LOCK_POS (28U) +#define GLB_TZC_GLB_SWRST_S1C_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1C_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1C_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S1C_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1C_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S1D_LOCK GLB_TZC_GLB_SWRST_S1D_LOCK +#define GLB_TZC_GLB_SWRST_S1D_LOCK_POS (29U) +#define GLB_TZC_GLB_SWRST_S1D_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1D_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1D_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S1D_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1D_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S1E_LOCK GLB_TZC_GLB_SWRST_S1E_LOCK +#define GLB_TZC_GLB_SWRST_S1E_LOCK_POS (30U) +#define GLB_TZC_GLB_SWRST_S1E_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1E_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1E_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S1E_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1E_LOCK_POS)) +#define GLB_TZC_GLB_SWRST_S1F_LOCK GLB_TZC_GLB_SWRST_S1F_LOCK +#define GLB_TZC_GLB_SWRST_S1F_LOCK_POS (31U) +#define GLB_TZC_GLB_SWRST_S1F_LOCK_LEN (1U) +#define GLB_TZC_GLB_SWRST_S1F_LOCK_MSK (((1U << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1F_LOCK_POS) +#define GLB_TZC_GLB_SWRST_S1F_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1F_LOCK_POS)) + +/* 0xF08 : tzc_glb_ctrl_2 */ +#define GLB_TZC_GLB_CTRL_2_OFFSET (0xF08) +#define GLB_TZC_GLB_GPIO_0_LOCK GLB_TZC_GLB_GPIO_0_LOCK +#define GLB_TZC_GLB_GPIO_0_LOCK_POS (0U) +#define GLB_TZC_GLB_GPIO_0_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_0_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_0_LOCK_POS) +#define GLB_TZC_GLB_GPIO_0_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_0_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_1_LOCK GLB_TZC_GLB_GPIO_1_LOCK +#define GLB_TZC_GLB_GPIO_1_LOCK_POS (1U) +#define GLB_TZC_GLB_GPIO_1_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_1_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_1_LOCK_POS) +#define GLB_TZC_GLB_GPIO_1_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_1_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_2_LOCK GLB_TZC_GLB_GPIO_2_LOCK +#define GLB_TZC_GLB_GPIO_2_LOCK_POS (2U) +#define GLB_TZC_GLB_GPIO_2_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_2_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_2_LOCK_POS) +#define GLB_TZC_GLB_GPIO_2_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_2_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_3_LOCK GLB_TZC_GLB_GPIO_3_LOCK +#define GLB_TZC_GLB_GPIO_3_LOCK_POS (3U) +#define GLB_TZC_GLB_GPIO_3_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_3_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_3_LOCK_POS) +#define GLB_TZC_GLB_GPIO_3_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_3_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_4_LOCK GLB_TZC_GLB_GPIO_4_LOCK +#define GLB_TZC_GLB_GPIO_4_LOCK_POS (4U) +#define GLB_TZC_GLB_GPIO_4_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_4_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_4_LOCK_POS) +#define GLB_TZC_GLB_GPIO_4_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_4_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_5_LOCK GLB_TZC_GLB_GPIO_5_LOCK +#define GLB_TZC_GLB_GPIO_5_LOCK_POS (5U) +#define GLB_TZC_GLB_GPIO_5_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_5_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_5_LOCK_POS) +#define GLB_TZC_GLB_GPIO_5_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_5_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_6_LOCK GLB_TZC_GLB_GPIO_6_LOCK +#define GLB_TZC_GLB_GPIO_6_LOCK_POS (6U) +#define GLB_TZC_GLB_GPIO_6_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_6_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_6_LOCK_POS) +#define GLB_TZC_GLB_GPIO_6_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_6_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_7_LOCK GLB_TZC_GLB_GPIO_7_LOCK +#define GLB_TZC_GLB_GPIO_7_LOCK_POS (7U) +#define GLB_TZC_GLB_GPIO_7_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_7_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_7_LOCK_POS) +#define GLB_TZC_GLB_GPIO_7_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_7_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_8_LOCK GLB_TZC_GLB_GPIO_8_LOCK +#define GLB_TZC_GLB_GPIO_8_LOCK_POS (8U) +#define GLB_TZC_GLB_GPIO_8_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_8_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_8_LOCK_POS) +#define GLB_TZC_GLB_GPIO_8_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_8_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_9_LOCK GLB_TZC_GLB_GPIO_9_LOCK +#define GLB_TZC_GLB_GPIO_9_LOCK_POS (9U) +#define GLB_TZC_GLB_GPIO_9_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_9_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_9_LOCK_POS) +#define GLB_TZC_GLB_GPIO_9_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_9_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_10_LOCK GLB_TZC_GLB_GPIO_10_LOCK +#define GLB_TZC_GLB_GPIO_10_LOCK_POS (10U) +#define GLB_TZC_GLB_GPIO_10_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_10_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_10_LOCK_POS) +#define GLB_TZC_GLB_GPIO_10_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_10_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_11_LOCK GLB_TZC_GLB_GPIO_11_LOCK +#define GLB_TZC_GLB_GPIO_11_LOCK_POS (11U) +#define GLB_TZC_GLB_GPIO_11_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_11_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_11_LOCK_POS) +#define GLB_TZC_GLB_GPIO_11_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_11_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_12_LOCK GLB_TZC_GLB_GPIO_12_LOCK +#define GLB_TZC_GLB_GPIO_12_LOCK_POS (12U) +#define GLB_TZC_GLB_GPIO_12_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_12_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_12_LOCK_POS) +#define GLB_TZC_GLB_GPIO_12_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_12_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_13_LOCK GLB_TZC_GLB_GPIO_13_LOCK +#define GLB_TZC_GLB_GPIO_13_LOCK_POS (13U) +#define GLB_TZC_GLB_GPIO_13_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_13_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_13_LOCK_POS) +#define GLB_TZC_GLB_GPIO_13_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_13_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_14_LOCK GLB_TZC_GLB_GPIO_14_LOCK +#define GLB_TZC_GLB_GPIO_14_LOCK_POS (14U) +#define GLB_TZC_GLB_GPIO_14_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_14_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_14_LOCK_POS) +#define GLB_TZC_GLB_GPIO_14_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_14_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_15_LOCK GLB_TZC_GLB_GPIO_15_LOCK +#define GLB_TZC_GLB_GPIO_15_LOCK_POS (15U) +#define GLB_TZC_GLB_GPIO_15_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_15_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_15_LOCK_POS) +#define GLB_TZC_GLB_GPIO_15_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_15_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_16_LOCK GLB_TZC_GLB_GPIO_16_LOCK +#define GLB_TZC_GLB_GPIO_16_LOCK_POS (16U) +#define GLB_TZC_GLB_GPIO_16_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_16_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_16_LOCK_POS) +#define GLB_TZC_GLB_GPIO_16_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_16_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_17_LOCK GLB_TZC_GLB_GPIO_17_LOCK +#define GLB_TZC_GLB_GPIO_17_LOCK_POS (17U) +#define GLB_TZC_GLB_GPIO_17_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_17_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_17_LOCK_POS) +#define GLB_TZC_GLB_GPIO_17_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_17_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_18_LOCK GLB_TZC_GLB_GPIO_18_LOCK +#define GLB_TZC_GLB_GPIO_18_LOCK_POS (18U) +#define GLB_TZC_GLB_GPIO_18_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_18_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_18_LOCK_POS) +#define GLB_TZC_GLB_GPIO_18_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_18_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_19_LOCK GLB_TZC_GLB_GPIO_19_LOCK +#define GLB_TZC_GLB_GPIO_19_LOCK_POS (19U) +#define GLB_TZC_GLB_GPIO_19_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_19_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_19_LOCK_POS) +#define GLB_TZC_GLB_GPIO_19_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_19_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_20_LOCK GLB_TZC_GLB_GPIO_20_LOCK +#define GLB_TZC_GLB_GPIO_20_LOCK_POS (20U) +#define GLB_TZC_GLB_GPIO_20_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_20_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_20_LOCK_POS) +#define GLB_TZC_GLB_GPIO_20_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_20_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_21_LOCK GLB_TZC_GLB_GPIO_21_LOCK +#define GLB_TZC_GLB_GPIO_21_LOCK_POS (21U) +#define GLB_TZC_GLB_GPIO_21_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_21_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_21_LOCK_POS) +#define GLB_TZC_GLB_GPIO_21_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_21_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_22_LOCK GLB_TZC_GLB_GPIO_22_LOCK +#define GLB_TZC_GLB_GPIO_22_LOCK_POS (22U) +#define GLB_TZC_GLB_GPIO_22_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_22_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_22_LOCK_POS) +#define GLB_TZC_GLB_GPIO_22_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_22_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_23_LOCK GLB_TZC_GLB_GPIO_23_LOCK +#define GLB_TZC_GLB_GPIO_23_LOCK_POS (23U) +#define GLB_TZC_GLB_GPIO_23_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_23_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_23_LOCK_POS) +#define GLB_TZC_GLB_GPIO_23_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_23_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_24_LOCK GLB_TZC_GLB_GPIO_24_LOCK +#define GLB_TZC_GLB_GPIO_24_LOCK_POS (24U) +#define GLB_TZC_GLB_GPIO_24_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_24_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_24_LOCK_POS) +#define GLB_TZC_GLB_GPIO_24_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_24_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_25_LOCK GLB_TZC_GLB_GPIO_25_LOCK +#define GLB_TZC_GLB_GPIO_25_LOCK_POS (25U) +#define GLB_TZC_GLB_GPIO_25_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_25_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_25_LOCK_POS) +#define GLB_TZC_GLB_GPIO_25_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_25_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_26_LOCK GLB_TZC_GLB_GPIO_26_LOCK +#define GLB_TZC_GLB_GPIO_26_LOCK_POS (26U) +#define GLB_TZC_GLB_GPIO_26_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_26_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_26_LOCK_POS) +#define GLB_TZC_GLB_GPIO_26_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_26_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_27_LOCK GLB_TZC_GLB_GPIO_27_LOCK +#define GLB_TZC_GLB_GPIO_27_LOCK_POS (27U) +#define GLB_TZC_GLB_GPIO_27_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_27_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_27_LOCK_POS) +#define GLB_TZC_GLB_GPIO_27_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_27_LOCK_POS)) +#define GLB_TZC_GLB_GPIO_28_LOCK GLB_TZC_GLB_GPIO_28_LOCK +#define GLB_TZC_GLB_GPIO_28_LOCK_POS (28U) +#define GLB_TZC_GLB_GPIO_28_LOCK_LEN (1U) +#define GLB_TZC_GLB_GPIO_28_LOCK_MSK (((1U << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_28_LOCK_POS) +#define GLB_TZC_GLB_GPIO_28_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_28_LOCK_POS)) + +/* 0xF0C : tzc_glb_ctrl_3 */ +#define GLB_TZC_GLB_CTRL_3_OFFSET (0xF0C) + +struct glb_reg { + /* 0x0 : clk_cfg0 */ + union { + struct + { + uint32_t reg_pll_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_fclk_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_hclk_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reg_bclk_en : 1; /* [ 3], r/w, 0x1 */ + uint32_t reg_pll_sel : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t hbn_root_clk_sel : 2; /* [ 7: 6], r, 0x0 */ + uint32_t reg_hclk_div : 8; /* [15: 8], r/w, 0x0 */ + uint32_t reg_bclk_div : 8; /* [23:16], r/w, 0x0 */ + uint32_t fclk_sw_state : 3; /* [26:24], r, 0x0 */ + uint32_t chip_rdy : 1; /* [ 27], r, 0x0 */ + uint32_t glb_id : 4; /* [31:28], r, 0x6 */ + } BF; + uint32_t WORD; + } clk_cfg0; + + /* 0x4 : clk_cfg1 */ + union { + struct + { + uint32_t wifi_mac_core_div : 4; /* [ 3: 0], r/w, 0x1 */ + uint32_t wifi_mac_wt_div : 4; /* [ 7: 4], r/w, 0x0 */ + uint32_t reserved_8_15 : 8; /* [15: 8], rsvd, 0x0 */ + uint32_t ble_clk_sel : 6; /* [21:16], r/w, 0x10 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t ble_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clk_cfg1; + + /* 0x8 : clk_cfg2 */ + union { + struct + { + uint32_t uart_clk_div : 3; /* [ 2: 0], r/w, 0x7 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t uart_clk_en : 1; /* [ 4], r/w, 0x1 */ + uint32_t reserved_5_6 : 2; /* [ 6: 5], rsvd, 0x0 */ + uint32_t hbn_uart_clk_sel : 1; /* [ 7], r, 0x0 */ + uint32_t sf_clk_div : 3; /* [10: 8], r/w, 0x3 */ + uint32_t sf_clk_en : 1; /* [ 11], r/w, 0x1 */ + uint32_t sf_clk_sel : 2; /* [13:12], r/w, 0x2 */ + uint32_t sf_clk_sel2 : 2; /* [15:14], r/w, 0x0 */ + uint32_t ir_clk_div : 6; /* [21:16], r/w, 0xf */ + uint32_t reserved_22 : 1; /* [ 22], rsvd, 0x0 */ + uint32_t ir_clk_en : 1; /* [ 23], r/w, 0x1 */ + uint32_t dma_clk_en : 8; /* [31:24], r/w, 0xff */ + } BF; + uint32_t WORD; + } clk_cfg2; + + /* 0xC : clk_cfg3 */ + union { + struct + { + uint32_t spi_clk_div : 5; /* [ 4: 0], r/w, 0x3 */ + uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ + uint32_t spi_clk_en : 1; /* [ 8], r/w, 0x1 */ + uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ + uint32_t i2c_clk_div : 8; /* [23:16], r/w, 0xff */ + uint32_t i2c_clk_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clk_cfg3; + + /* 0x10 : swrst_cfg0 */ + union { + struct + { + uint32_t swrst_s00 : 1; /* [ 0], r/w, 0x0 */ + uint32_t swrst_s01 : 1; /* [ 1], r/w, 0x0 */ + uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ + uint32_t swrst_s20 : 1; /* [ 4], r/w, 0x0 */ + uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ + uint32_t swrst_s30 : 1; /* [ 8], r/w, 0x0 */ + uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } swrst_cfg0; + + /* 0x14 : swrst_cfg1 */ + union { + struct + { + uint32_t swrst_s10 : 1; /* [ 0], r/w, 0x0 */ + uint32_t swrst_s11 : 1; /* [ 1], r/w, 0x0 */ + uint32_t swrst_s12 : 1; /* [ 2], r/w, 0x0 */ + uint32_t swrst_s13 : 1; /* [ 3], r/w, 0x0 */ + uint32_t swrst_s14 : 1; /* [ 4], r/w, 0x0 */ + uint32_t swrst_s15 : 1; /* [ 5], r/w, 0x0 */ + uint32_t swrst_s16 : 1; /* [ 6], r/w, 0x0 */ + uint32_t swrst_s17 : 1; /* [ 7], r/w, 0x0 */ + uint32_t swrst_s18 : 1; /* [ 8], r/w, 0x0 */ + uint32_t swrst_s19 : 1; /* [ 9], r/w, 0x0 */ + uint32_t swrst_s1a : 1; /* [ 10], r/w, 0x0 */ + uint32_t swrst_s1b : 1; /* [ 11], r/w, 0x0 */ + uint32_t swrst_s1c : 1; /* [ 12], r/w, 0x0 */ + uint32_t swrst_s1d : 1; /* [ 13], r/w, 0x0 */ + uint32_t swrst_s1e : 1; /* [ 14], r/w, 0x0 */ + uint32_t swrst_s1f : 1; /* [ 15], r/w, 0x0 */ + uint32_t swrst_s1a0 : 1; /* [ 16], r/w, 0x0 */ + uint32_t swrst_s1a1 : 1; /* [ 17], r/w, 0x0 */ + uint32_t swrst_s1a2 : 1; /* [ 18], r/w, 0x0 */ + uint32_t swrst_s1a3 : 1; /* [ 19], r/w, 0x0 */ + uint32_t swrst_s1a4 : 1; /* [ 20], r/w, 0x0 */ + uint32_t swrst_s1a5 : 1; /* [ 21], r/w, 0x0 */ + uint32_t swrst_s1a6 : 1; /* [ 22], r/w, 0x0 */ + uint32_t swrst_s1a7 : 1; /* [ 23], r/w, 0x0 */ + uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } swrst_cfg1; + + /* 0x18 : swrst_cfg2 */ + union { + struct + { + uint32_t reg_ctrl_pwron_rst : 1; /* [ 0], r/w, 0x0 */ + uint32_t reg_ctrl_cpu_reset : 1; /* [ 1], r/w, 0x0 */ + uint32_t reg_ctrl_sys_reset : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t reg_ctrl_reset_dummy : 4; /* [ 7: 4], r/w, 0x0 */ + uint32_t reserved_8_23 : 16; /* [23: 8], rsvd, 0x0 */ + uint32_t pka_clk_sel : 1; /* [ 24], r/w, 0x0 */ + uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } swrst_cfg2; + + /* 0x1C : swrst_cfg3 */ + union { + struct + { + uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } swrst_cfg3; + + /* 0x20 : cgen_cfg0 */ + union { + struct + { + uint32_t cgen_m : 8; /* [ 7: 0], r/w, 0xff */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } cgen_cfg0; + + /* 0x24 : cgen_cfg1 */ + union { + struct + { + uint32_t cgen_s1 : 16; /* [15: 0], r/w, 0xffff */ + uint32_t cgen_s1a : 8; /* [23:16], r/w, 0xff */ + uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } cgen_cfg1; + + /* 0x28 : cgen_cfg2 */ + union { + struct + { + uint32_t cgen_s2 : 1; /* [ 0], r/w, 0x1 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t cgen_s3 : 1; /* [ 4], r/w, 0x1 */ + uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } cgen_cfg2; + + /* 0x2C : cgen_cfg3 */ + union { + struct + { + uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } cgen_cfg3; + + /* 0x30 : MBIST_CTL */ + union { + struct + { + uint32_t irom_mbist_mode : 1; /* [ 0], r/w, 0x0 */ + uint32_t hsram_mbist_mode : 1; /* [ 1], r/w, 0x0 */ + uint32_t tag_mbist_mode : 1; /* [ 2], r/w, 0x0 */ + uint32_t ocram_mbist_mode : 1; /* [ 3], r/w, 0x0 */ + uint32_t wifi_mbist_mode : 1; /* [ 4], r/w, 0x0 */ + uint32_t reserved_5_30 : 26; /* [30: 5], rsvd, 0x0 */ + uint32_t reg_mbist_rst_n : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } MBIST_CTL; + + /* 0x34 : MBIST_STAT */ + union { + struct + { + uint32_t irom_mbist_done : 1; /* [ 0], r, 0x0 */ + uint32_t hsram_mbist_done : 1; /* [ 1], r, 0x0 */ + uint32_t tag_mbist_done : 1; /* [ 2], r, 0x0 */ + uint32_t ocram_mbist_done : 1; /* [ 3], r, 0x0 */ + uint32_t wifi_mbist_done : 1; /* [ 4], r, 0x0 */ + uint32_t reserved_5_15 : 11; /* [15: 5], rsvd, 0x0 */ + uint32_t irom_mbist_fail : 1; /* [ 16], r, 0x0 */ + uint32_t hsram_mbist_fail : 1; /* [ 17], r, 0x0 */ + uint32_t tag_mbist_fail : 1; /* [ 18], r, 0x0 */ + uint32_t ocram_mbist_fail : 1; /* [ 19], r, 0x0 */ + uint32_t wifi_mbist_fail : 1; /* [ 20], r, 0x0 */ + uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } MBIST_STAT; + + /* 0x38 reserved */ + uint8_t RESERVED0x38[24]; + + /* 0x50 : bmx_cfg1 */ + union { + struct + { + uint32_t bmx_timeout_en : 4; /* [ 3: 0], r/w, 0x0 */ + uint32_t bmx_arb_mode : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t bmx_err_en : 1; /* [ 8], r/w, 0x0 */ + uint32_t bmx_busy_option_dis : 1; /* [ 9], r/w, 0x0 */ + uint32_t bmx_gating_dis : 1; /* [ 10], r/w, 0x0 */ + uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ + uint32_t hsel_option : 4; /* [15:12], r/w, 0x0 */ + uint32_t pds_apb_cfg : 8; /* [23:16], r/w, 0x0 */ + uint32_t hbn_apb_cfg : 8; /* [31:24], r/w, 0x0 */ + } BF; + uint32_t WORD; + } bmx_cfg1; + + /* 0x54 : bmx_cfg2 */ + union { + struct + { + uint32_t bmx_err_addr_dis : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t bmx_err_dec : 1; /* [ 4], r, 0x0 */ + uint32_t bmx_err_tz : 1; /* [ 5], r, 0x0 */ + uint32_t reserved_6_27 : 22; /* [27: 6], rsvd, 0x0 */ + uint32_t bmx_dbg_sel : 4; /* [31:28], r/w, 0x0 */ + } BF; + uint32_t WORD; + } bmx_cfg2; + + /* 0x58 : bmx_err_addr */ + union { + struct + { + uint32_t bmx_err_addr : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } bmx_err_addr; + + /* 0x5C : bmx_dbg_out */ + union { + struct + { + uint32_t bmx_dbg_out : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } bmx_dbg_out; + + /* 0x60 : rsv0 */ + union { + struct + { + uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } rsv0; + + /* 0x64 : rsv1 */ + union { + struct + { + uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } rsv1; + + /* 0x68 : rsv2 */ + union { + struct + { + uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } rsv2; + + /* 0x6C : rsv3 */ + union { + struct + { + uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0xffffffffL */ + } BF; + uint32_t WORD; + } rsv3; + + /* 0x70 : sram_ret */ + union { + struct + { + uint32_t reg_sram_ret : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sram_ret; + + /* 0x74 : sram_slp */ + union { + struct + { + uint32_t reg_sram_slp : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sram_slp; + + /* 0x78 : sram_parm */ + union { + struct + { + uint32_t reg_sram_parm : 32; /* [31: 0], r/w, 0xc0c0c0c */ + } BF; + uint32_t WORD; + } sram_parm; + + /* 0x7C : seam_misc */ + union { + struct + { + uint32_t em_sel : 4; /* [ 3: 0], r/w, 0x3 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } seam_misc; + + /* 0x80 : glb_parm */ + union { + struct + { + uint32_t reg_bd_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t reg_ext_rst_smt : 1; /* [ 1], r/w, 0x0 */ + uint32_t jtag_swap_set : 6; /* [ 7: 2], r/w, 0x0 */ + uint32_t swap_sflash_io_3_io_0 : 1; /* [ 8], r/w, 0x1 */ + uint32_t sel_embedded_sflash : 1; /* [ 9], r/w, 0x1 */ + uint32_t reserved_10_11 : 2; /* [11:10], rsvd, 0x0 */ + uint32_t reg_spi_0_master_mode : 1; /* [ 12], r/w, 0x0 */ + uint32_t reg_spi_0_swap : 1; /* [ 13], r/w, 0x0 */ + uint32_t reserved_14 : 1; /* [ 14], rsvd, 0x0 */ + uint32_t reg_cci_use_jtag_pin : 1; /* [ 15], r/w, 0x1 */ + uint32_t reg_cci_use_sdio_pin : 1; /* [ 16], r/w, 0x1 */ + uint32_t p1_adc_test_with_cci : 1; /* [ 17], r/w, 0x0 */ + uint32_t p2_dac_test_with_cci : 1; /* [ 18], r/w, 0x0 */ + uint32_t p3_cci_use_io_2_5 : 1; /* [ 19], r/w, 0x0 */ + uint32_t p4_adc_test_with_jtag : 1; /* [ 20], r/w, 0x0 */ + uint32_t p5_dac_test_with_jtag : 1; /* [ 21], r/w, 0x0 */ + uint32_t p6_sdio_use_io_0_5 : 1; /* [ 22], r/w, 0x0 */ + uint32_t p7_jtag_use_io_2_5 : 1; /* [ 23], r/w, 0x0 */ + uint32_t uart_swap_set : 3; /* [26:24], r/w, 0x0 */ + uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } glb_parm; + + /* 0x84 reserved */ + uint8_t RESERVED0x84[12]; + + /* 0x90 : CPU_CLK_CFG */ + union { + struct + { + uint32_t cpu_rtc_div : 17; /* [16: 0], r/w, 0x10 */ + uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */ + uint32_t cpu_rtc_en : 1; /* [ 18], r/w, 0x0 */ + uint32_t cpu_rtc_sel : 1; /* [ 19], r/w, 0x1 */ + uint32_t debug_ndreset_gate : 1; /* [ 20], r/w, 0x0 */ + uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } CPU_CLK_CFG; + + /* 0x94 reserved */ + uint8_t RESERVED0x94[16]; + + /* 0xA4 : GPADC_32M_SRC_CTRL */ + union { + struct + { + uint32_t gpadc_32m_clk_div : 6; /* [ 5: 0], r/w, 0x2 */ + uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */ + uint32_t gpadc_32m_clk_sel : 1; /* [ 7], r/w, 0x0 */ + uint32_t gpadc_32m_div_en : 1; /* [ 8], r/w, 0x1 */ + uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPADC_32M_SRC_CTRL; + + /* 0xA8 : DIG32K_WAKEUP_CTRL */ + union { + struct + { + uint32_t dig_32k_div : 11; /* [10: 0], r/w, 0x3e8 */ + uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ + uint32_t dig_32k_en : 1; /* [ 12], r/w, 0x1 */ + uint32_t dig_32k_comp : 1; /* [ 13], r/w, 0x0 */ + uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ + uint32_t dig_512k_div : 7; /* [22:16], r/w, 0x3e */ + uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ + uint32_t dig_512k_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t dig_512k_comp : 1; /* [ 25], r/w, 0x1 */ + uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */ + uint32_t dig_clk_src_sel : 1; /* [ 28], r/w, 0x0 */ + uint32_t reserved_29_30 : 2; /* [30:29], rsvd, 0x0 */ + uint32_t reg_en_platform_wakeup : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DIG32K_WAKEUP_CTRL; + + /* 0xAC : WIFI_BT_COEX_CTRL */ + union { + struct + { + uint32_t coex_bt_channel : 7; /* [ 6: 0], r/w, 0x0 */ + uint32_t coex_bt_pti : 4; /* [10: 7], r/w, 0x0 */ + uint32_t coex_bt_bw : 1; /* [ 11], r/w, 0x0 */ + uint32_t en_gpio_bt_coex : 1; /* [ 12], r/w, 0x0 */ + uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } WIFI_BT_COEX_CTRL; + + /* 0xb0 reserved */ + uint8_t RESERVED0xb0[16]; + + /* 0xC0 : UART_SIG_SEL_0 */ + union { + struct + { + uint32_t uart_sig_0_sel : 4; /* [ 3: 0], r/w, 0x0 */ + uint32_t uart_sig_1_sel : 4; /* [ 7: 4], r/w, 0x1 */ + uint32_t uart_sig_2_sel : 4; /* [11: 8], r/w, 0x2 */ + uint32_t uart_sig_3_sel : 4; /* [15:12], r/w, 0x3 */ + uint32_t uart_sig_4_sel : 4; /* [19:16], r/w, 0x4 */ + uint32_t uart_sig_5_sel : 4; /* [23:20], r/w, 0x5 */ + uint32_t uart_sig_6_sel : 4; /* [27:24], r/w, 0x6 */ + uint32_t uart_sig_7_sel : 4; /* [31:28], r/w, 0x7 */ + } BF; + uint32_t WORD; + } UART_SIG_SEL_0; + + /* 0xc4 reserved */ + uint8_t RESERVED0xc4[12]; + + /* 0xD0 : DBG_SEL_LL */ + union { + struct + { + uint32_t reg_dbg_ll_ctrl : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DBG_SEL_LL; + + /* 0xD4 : DBG_SEL_LH */ + union { + struct + { + uint32_t reg_dbg_lh_ctrl : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DBG_SEL_LH; + + /* 0xD8 : DBG_SEL_HL */ + union { + struct + { + uint32_t reg_dbg_hl_ctrl : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DBG_SEL_HL; + + /* 0xDC : DBG_SEL_HH */ + union { + struct + { + uint32_t reg_dbg_hh_ctrl : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } DBG_SEL_HH; + + /* 0xE0 : debug */ + union { + struct + { + uint32_t debug_oe : 1; /* [ 0], r/w, 0x0 */ + uint32_t debug_i : 31; /* [31: 1], r, 0x0 */ + } BF; + uint32_t WORD; + } debug; + + /* 0xe4 reserved */ + uint8_t RESERVED0xe4[28]; + + /* 0x100 : GPIO_CFGCTL0 */ + union { + struct + { + uint32_t reg_gpio_0_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_0_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_0_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_0_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_0_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_0_func_sel : 4; /* [11: 8], r/w, 0x1 */ + uint32_t real_gpio_0_func_sel : 4; /* [15:12], r, 0x1 */ + uint32_t reg_gpio_1_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_1_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_1_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_1_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_1_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_1_func_sel : 4; /* [27:24], r/w, 0x1 */ + uint32_t real_gpio_1_func_sel : 4; /* [31:28], r, 0x1 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL0; + + /* 0x104 : GPIO_CFGCTL1 */ + union { + struct + { + uint32_t reg_gpio_2_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_2_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_2_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_2_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_2_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_2_func_sel : 4; /* [11: 8], r/w, 0x1 */ + uint32_t real_gpio_2_func_sel : 4; /* [15:12], r, 0x1 */ + uint32_t reg_gpio_3_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_3_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_3_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_3_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_3_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_3_func_sel : 4; /* [27:24], r/w, 0x1 */ + uint32_t real_gpio_3_func_sel : 4; /* [31:28], r, 0x1 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL1; + + /* 0x108 : GPIO_CFGCTL2 */ + union { + struct + { + uint32_t reg_gpio_4_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_4_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_4_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_4_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_4_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_4_func_sel : 4; /* [11: 8], r/w, 0x1 */ + uint32_t real_gpio_4_func_sel : 4; /* [15:12], r, 0x1 */ + uint32_t reg_gpio_5_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_5_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_5_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_5_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_5_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_5_func_sel : 4; /* [27:24], r/w, 0x1 */ + uint32_t real_gpio_5_func_sel : 4; /* [31:28], r, 0x1 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL2; + + /* 0x10C : GPIO_CFGCTL3 */ + union { + struct + { + uint32_t reg_gpio_6_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_6_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_6_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_6_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_6_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_6_func_sel : 4; /* [11: 8], r/w, 0xb */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t reg_gpio_7_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_7_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_7_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_7_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_7_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_7_func_sel : 4; /* [27:24], r/w, 0xb */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL3; + + /* 0x110 : GPIO_CFGCTL4 */ + union { + struct + { + uint32_t reg_gpio_8_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_8_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_8_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_8_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_8_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_8_func_sel : 4; /* [11: 8], r/w, 0xb */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t reg_gpio_9_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_9_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_9_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_9_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_9_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_9_func_sel : 4; /* [27:24], r/w, 0xb */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL4; + + /* 0x114 : GPIO_CFGCTL5 */ + union { + struct + { + uint32_t reg_gpio_10_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_10_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_10_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_10_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_10_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_10_func_sel : 4; /* [11: 8], r/w, 0xb */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t reg_gpio_11_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_11_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_11_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_11_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_11_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_11_func_sel : 4; /* [27:24], r/w, 0xe */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL5; + + /* 0x118 : GPIO_CFGCTL6 */ + union { + struct + { + uint32_t reg_gpio_12_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_12_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_12_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_12_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_12_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_12_func_sel : 4; /* [11: 8], r/w, 0xe */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t reg_gpio_13_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_13_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_13_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_13_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_13_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_13_func_sel : 4; /* [27:24], r/w, 0xb */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL6; + + /* 0x11C : GPIO_CFGCTL7 */ + union { + struct + { + uint32_t reg_gpio_14_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_14_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_14_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_14_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_14_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_14_func_sel : 4; /* [11: 8], r/w, 0xe */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t reg_gpio_15_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_15_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_15_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_15_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_15_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_15_func_sel : 4; /* [27:24], r/w, 0xb */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL7; + + /* 0x120 : GPIO_CFGCTL8 */ + union { + struct + { + uint32_t reg_gpio_16_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_16_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_16_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_16_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_16_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_16_func_sel : 4; /* [11: 8], r/w, 0xb */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t reg_gpio_17_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_17_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_17_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_17_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_17_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_17_func_sel : 4; /* [27:24], r/w, 0xe */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL8; + + /* 0x124 : GPIO_CFGCTL9 */ + union { + struct + { + uint32_t reg_gpio_18_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_18_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_18_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_18_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_18_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_18_func_sel : 4; /* [11: 8], r/w, 0xb */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t reg_gpio_19_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_19_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_19_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_19_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_19_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_19_func_sel : 4; /* [27:24], r/w, 0xb */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL9; + + /* 0x128 : GPIO_CFGCTL10 */ + union { + struct + { + uint32_t reg_gpio_20_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_20_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_20_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_20_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_20_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_20_func_sel : 4; /* [11: 8], r/w, 0xb */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t reg_gpio_21_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_21_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_21_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_21_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_21_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_21_func_sel : 4; /* [27:24], r/w, 0xb */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL10; + + /* 0x12C : GPIO_CFGCTL11 */ + union { + struct + { + uint32_t reg_gpio_22_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_22_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_22_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_22_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_22_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_22_func_sel : 4; /* [11: 8], r/w, 0xb */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t reg_gpio_23_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_23_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_23_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_23_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_23_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL11; + + /* 0x130 : GPIO_CFGCTL12 */ + union { + struct + { + uint32_t reg_gpio_24_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_24_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_24_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_24_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_24_pd : 1; /* [ 5], r/w, 0x1 */ + uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */ + uint32_t reg_gpio_25_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_25_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_25_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_25_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_25_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL12; + + /* 0x134 : GPIO_CFGCTL13 */ + union { + struct + { + uint32_t reg_gpio_26_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_26_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_26_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_26_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_26_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */ + uint32_t reg_gpio_27_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_27_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_27_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_27_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_27_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL13; + + /* 0x138 : GPIO_CFGCTL14 */ + union { + struct + { + uint32_t reg_gpio_28_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_28_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_28_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_28_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_28_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL14; + + /* 0x13c reserved */ + uint8_t RESERVED0x13c[68]; + + /* 0x180 : GPIO_CFGCTL30 */ + union { + struct + { + uint32_t reg_gpio_0_i : 1; /* [ 0], r, 0x0 */ + uint32_t reg_gpio_1_i : 1; /* [ 1], r, 0x0 */ + uint32_t reg_gpio_2_i : 1; /* [ 2], r, 0x0 */ + uint32_t reg_gpio_3_i : 1; /* [ 3], r, 0x0 */ + uint32_t reg_gpio_4_i : 1; /* [ 4], r, 0x0 */ + uint32_t reg_gpio_5_i : 1; /* [ 5], r, 0x0 */ + uint32_t reg_gpio_6_i : 1; /* [ 6], r, 0x0 */ + uint32_t reg_gpio_7_i : 1; /* [ 7], r, 0x0 */ + uint32_t reg_gpio_8_i : 1; /* [ 8], r, 0x0 */ + uint32_t reg_gpio_9_i : 1; /* [ 9], r, 0x0 */ + uint32_t reg_gpio_10_i : 1; /* [ 10], r, 0x0 */ + uint32_t reg_gpio_11_i : 1; /* [ 11], r, 0x0 */ + uint32_t reg_gpio_12_i : 1; /* [ 12], r, 0x0 */ + uint32_t reg_gpio_13_i : 1; /* [ 13], r, 0x0 */ + uint32_t reg_gpio_14_i : 1; /* [ 14], r, 0x0 */ + uint32_t reg_gpio_15_i : 1; /* [ 15], r, 0x0 */ + uint32_t reg_gpio_16_i : 1; /* [ 16], r, 0x0 */ + uint32_t reg_gpio_17_i : 1; /* [ 17], r, 0x0 */ + uint32_t reg_gpio_18_i : 1; /* [ 18], r, 0x0 */ + uint32_t reg_gpio_19_i : 1; /* [ 19], r, 0x0 */ + uint32_t reg_gpio_20_i : 1; /* [ 20], r, 0x0 */ + uint32_t reg_gpio_21_i : 1; /* [ 21], r, 0x0 */ + uint32_t reg_gpio_22_i : 1; /* [ 22], r, 0x0 */ + uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL30; + + /* 0x184 : GPIO_CFGCTL31 */ + union { + struct + { + uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL31; + + /* 0x188 : GPIO_CFGCTL32 */ + union { + struct + { + uint32_t reg_gpio_0_o : 1; /* [ 0], r/w, 0x0 */ + uint32_t reg_gpio_1_o : 1; /* [ 1], r/w, 0x0 */ + uint32_t reg_gpio_2_o : 1; /* [ 2], r/w, 0x0 */ + uint32_t reg_gpio_3_o : 1; /* [ 3], r/w, 0x0 */ + uint32_t reg_gpio_4_o : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_5_o : 1; /* [ 5], r/w, 0x0 */ + uint32_t reg_gpio_6_o : 1; /* [ 6], r/w, 0x0 */ + uint32_t reg_gpio_7_o : 1; /* [ 7], r/w, 0x0 */ + uint32_t reg_gpio_8_o : 1; /* [ 8], r/w, 0x0 */ + uint32_t reg_gpio_9_o : 1; /* [ 9], r/w, 0x0 */ + uint32_t reg_gpio_10_o : 1; /* [ 10], r/w, 0x0 */ + uint32_t reg_gpio_11_o : 1; /* [ 11], r/w, 0x0 */ + uint32_t reg_gpio_12_o : 1; /* [ 12], r/w, 0x0 */ + uint32_t reg_gpio_13_o : 1; /* [ 13], r/w, 0x0 */ + uint32_t reg_gpio_14_o : 1; /* [ 14], r/w, 0x0 */ + uint32_t reg_gpio_15_o : 1; /* [ 15], r/w, 0x0 */ + uint32_t reg_gpio_16_o : 1; /* [ 16], r/w, 0x0 */ + uint32_t reg_gpio_17_o : 1; /* [ 17], r/w, 0x0 */ + uint32_t reg_gpio_18_o : 1; /* [ 18], r/w, 0x0 */ + uint32_t reg_gpio_19_o : 1; /* [ 19], r/w, 0x0 */ + uint32_t reg_gpio_20_o : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_21_o : 1; /* [ 21], r/w, 0x0 */ + uint32_t reg_gpio_22_o : 1; /* [ 22], r/w, 0x0 */ + uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL32; + + /* 0x18C : GPIO_CFGCTL33 */ + union { + struct + { + uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL33; + + /* 0x190 : GPIO_CFGCTL34 */ + union { + struct + { + uint32_t reg_gpio_0_oe : 1; /* [ 0], r/w, 0x0 */ + uint32_t reg_gpio_1_oe : 1; /* [ 1], r/w, 0x0 */ + uint32_t reg_gpio_2_oe : 1; /* [ 2], r/w, 0x0 */ + uint32_t reg_gpio_3_oe : 1; /* [ 3], r/w, 0x0 */ + uint32_t reg_gpio_4_oe : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_5_oe : 1; /* [ 5], r/w, 0x0 */ + uint32_t reg_gpio_6_oe : 1; /* [ 6], r/w, 0x0 */ + uint32_t reg_gpio_7_oe : 1; /* [ 7], r/w, 0x0 */ + uint32_t reg_gpio_8_oe : 1; /* [ 8], r/w, 0x0 */ + uint32_t reg_gpio_9_oe : 1; /* [ 9], r/w, 0x0 */ + uint32_t reg_gpio_10_oe : 1; /* [ 10], r/w, 0x0 */ + uint32_t reg_gpio_11_oe : 1; /* [ 11], r/w, 0x0 */ + uint32_t reg_gpio_12_oe : 1; /* [ 12], r/w, 0x0 */ + uint32_t reg_gpio_13_oe : 1; /* [ 13], r/w, 0x0 */ + uint32_t reg_gpio_14_oe : 1; /* [ 14], r/w, 0x0 */ + uint32_t reg_gpio_15_oe : 1; /* [ 15], r/w, 0x0 */ + uint32_t reg_gpio_16_oe : 1; /* [ 16], r/w, 0x0 */ + uint32_t reg_gpio_17_oe : 1; /* [ 17], r/w, 0x0 */ + uint32_t reg_gpio_18_oe : 1; /* [ 18], r/w, 0x0 */ + uint32_t reg_gpio_19_oe : 1; /* [ 19], r/w, 0x0 */ + uint32_t reg_gpio_20_oe : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_21_oe : 1; /* [ 21], r/w, 0x0 */ + uint32_t reg_gpio_22_oe : 1; /* [ 22], r/w, 0x0 */ + uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL34; + + /* 0x194 : GPIO_CFGCTL35 */ + union { + struct + { + uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL35; + + /* 0x198 reserved */ + uint8_t RESERVED0x198[8]; + + /* 0x1A0 : GPIO_INT_MASK1 */ + union { + struct + { + uint32_t reg_gpio_int_mask1 : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } GPIO_INT_MASK1; + + /* 0x1a4 reserved */ + uint8_t RESERVED0x1a4[4]; + + /* 0x1A8 : GPIO_INT_STAT1 */ + union { + struct + { + uint32_t gpio_int_stat1 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_INT_STAT1; + + /* 0x1ac reserved */ + uint8_t RESERVED0x1ac[4]; + + /* 0x1B0 : GPIO_INT_CLR1 */ + union { + struct + { + uint32_t reg_gpio_int_clr1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_INT_CLR1; + + /* 0x1b4 reserved */ + uint8_t RESERVED0x1b4[12]; + + /* 0x1C0 : GPIO_INT_MODE_SET1 */ + union { + struct + { + uint32_t reg_gpio_int_mode_set1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_INT_MODE_SET1; + + /* 0x1C4 : GPIO_INT_MODE_SET2 */ + union { + struct + { + uint32_t reg_gpio_int_mode_set2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_INT_MODE_SET2; + + /* 0x1C8 : GPIO_INT_MODE_SET3 */ + union { + struct + { + uint32_t reg_gpio_int_mode_set3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } GPIO_INT_MODE_SET3; + + /* 0x1cc reserved */ + uint8_t RESERVED0x1cc[88]; + + /* 0x224 : led_driver */ + union { + struct + { + uint32_t led_din_reg : 1; /* [ 0], r/w, 0x0 */ + uint32_t led_din_sel : 1; /* [ 1], r/w, 0x0 */ + uint32_t led_din_polarity_sel : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t leddrv_ibias : 4; /* [ 7: 4], r/w, 0x8 */ + uint32_t ir_rx_gpio_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_30 : 21; /* [30:10], rsvd, 0x0 */ + uint32_t pu_leddrv : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } led_driver; + + /* 0x228 reserved */ + uint8_t RESERVED0x228[224]; + + /* 0x308 : gpdac_ctrl */ + union { + struct + { + uint32_t gpdaca_rstn_ana : 1; /* [ 0], r/w, 0x1 */ + uint32_t gpdacb_rstn_ana : 1; /* [ 1], r/w, 0x1 */ + uint32_t reserved_2_6 : 5; /* [ 6: 2], rsvd, 0x0 */ + uint32_t gpdac_test_en : 1; /* [ 7], r/w, 0x0 */ + uint32_t gpdac_ref_sel : 1; /* [ 8], r/w, 0x0 */ + uint32_t gpdac_test_sel : 3; /* [11: 9], r/w, 0x0 */ + uint32_t reserved_12_23 : 12; /* [23:12], rsvd, 0x0 */ + uint32_t gpdac_reserved : 8; /* [31:24], r/w, 0xf */ + } BF; + uint32_t WORD; + } gpdac_ctrl; + + /* 0x30C : gpdac_actrl */ + union { + struct + { + uint32_t gpdac_a_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t gpdac_ioa_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t reserved_2_17 : 16; /* [17: 2], rsvd, 0x0 */ + uint32_t gpdac_a_rng : 2; /* [19:18], r/w, 0x3 */ + uint32_t gpdac_a_outmux : 3; /* [22:20], r/w, 0x0 */ + uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpdac_actrl; + + /* 0x310 : gpdac_bctrl */ + union { + struct + { + uint32_t gpdac_b_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t gpdac_iob_en : 1; /* [ 1], r/w, 0x0 */ + uint32_t reserved_2_17 : 16; /* [17: 2], rsvd, 0x0 */ + uint32_t gpdac_b_rng : 2; /* [19:18], r/w, 0x3 */ + uint32_t gpdac_b_outmux : 3; /* [22:20], r/w, 0x0 */ + uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpdac_bctrl; + + /* 0x314 : gpdac_data */ + union { + struct + { + uint32_t gpdac_b_data : 10; /* [ 9: 0], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t gpdac_a_data : 10; /* [25:16], r/w, 0x0 */ + uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } gpdac_data; + + /* 0x318 reserved */ + uint8_t RESERVED0x318[3048]; + + /* 0xF00 : tzc_glb_ctrl_0 */ + union { + struct + { + uint32_t tzc_glb_swrst_s00_lock : 1; /* [ 0], r, 0x0 */ + uint32_t tzc_glb_swrst_s01_lock : 1; /* [ 1], r, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t tzc_glb_swrst_s30_lock : 1; /* [ 8], r, 0x0 */ + uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */ + uint32_t tzc_glb_ctrl_pwron_rst_lock : 1; /* [ 12], r, 0x0 */ + uint32_t tzc_glb_ctrl_cpu_reset_lock : 1; /* [ 13], r, 0x0 */ + uint32_t tzc_glb_ctrl_sys_reset_lock : 1; /* [ 14], r, 0x0 */ + uint32_t tzc_glb_ctrl_ungated_ap_lock : 1; /* [ 15], r, 0x0 */ + uint32_t reserved_16_24 : 9; /* [24:16], rsvd, 0x0 */ + uint32_t tzc_glb_misc_lock : 1; /* [ 25], r, 0x0 */ + uint32_t tzc_glb_sram_lock : 1; /* [ 26], r, 0x0 */ + uint32_t tzc_glb_l2c_lock : 1; /* [ 27], r, 0x0 */ + uint32_t tzc_glb_bmx_lock : 1; /* [ 28], r, 0x0 */ + uint32_t tzc_glb_dbg_lock : 1; /* [ 29], r, 0x0 */ + uint32_t tzc_glb_mbist_lock : 1; /* [ 30], r, 0x0 */ + uint32_t tzc_glb_clk_lock : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } tzc_glb_ctrl_0; + + /* 0xF04 : tzc_glb_ctrl_1 */ + union { + struct + { + uint32_t tzc_glb_swrst_s20_lock : 1; /* [ 0], r, 0x0 */ + uint32_t tzc_glb_swrst_s21_lock : 1; /* [ 1], r, 0x0 */ + uint32_t tzc_glb_swrst_s22_lock : 1; /* [ 2], r, 0x0 */ + uint32_t tzc_glb_swrst_s23_lock : 1; /* [ 3], r, 0x0 */ + uint32_t tzc_glb_swrst_s24_lock : 1; /* [ 4], r, 0x0 */ + uint32_t tzc_glb_swrst_s25_lock : 1; /* [ 5], r, 0x0 */ + uint32_t tzc_glb_swrst_s26_lock : 1; /* [ 6], r, 0x0 */ + uint32_t tzc_glb_swrst_s27_lock : 1; /* [ 7], r, 0x0 */ + uint32_t tzc_glb_swrst_s28_lock : 1; /* [ 8], r, 0x0 */ + uint32_t tzc_glb_swrst_s29_lock : 1; /* [ 9], r, 0x0 */ + uint32_t tzc_glb_swrst_s2a_lock : 1; /* [ 10], r, 0x0 */ + uint32_t tzc_glb_swrst_s2b_lock : 1; /* [ 11], r, 0x0 */ + uint32_t tzc_glb_swrst_s2c_lock : 1; /* [ 12], r, 0x0 */ + uint32_t tzc_glb_swrst_s2d_lock : 1; /* [ 13], r, 0x0 */ + uint32_t tzc_glb_swrst_s2e_lock : 1; /* [ 14], r, 0x0 */ + uint32_t tzc_glb_swrst_s2f_lock : 1; /* [ 15], r, 0x0 */ + uint32_t tzc_glb_swrst_s10_lock : 1; /* [ 16], r, 0x0 */ + uint32_t tzc_glb_swrst_s11_lock : 1; /* [ 17], r, 0x0 */ + uint32_t tzc_glb_swrst_s12_lock : 1; /* [ 18], r, 0x0 */ + uint32_t tzc_glb_swrst_s13_lock : 1; /* [ 19], r, 0x0 */ + uint32_t tzc_glb_swrst_s14_lock : 1; /* [ 20], r, 0x0 */ + uint32_t tzc_glb_swrst_s15_lock : 1; /* [ 21], r, 0x0 */ + uint32_t tzc_glb_swrst_s16_lock : 1; /* [ 22], r, 0x0 */ + uint32_t tzc_glb_swrst_s17_lock : 1; /* [ 23], r, 0x0 */ + uint32_t tzc_glb_swrst_s18_lock : 1; /* [ 24], r, 0x0 */ + uint32_t tzc_glb_swrst_s19_lock : 1; /* [ 25], r, 0x0 */ + uint32_t tzc_glb_swrst_s1a_lock : 1; /* [ 26], r, 0x0 */ + uint32_t tzc_glb_swrst_s1b_lock : 1; /* [ 27], r, 0x0 */ + uint32_t tzc_glb_swrst_s1c_lock : 1; /* [ 28], r, 0x0 */ + uint32_t tzc_glb_swrst_s1d_lock : 1; /* [ 29], r, 0x0 */ + uint32_t tzc_glb_swrst_s1e_lock : 1; /* [ 30], r, 0x0 */ + uint32_t tzc_glb_swrst_s1f_lock : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } tzc_glb_ctrl_1; + + /* 0xF08 : tzc_glb_ctrl_2 */ + union { + struct + { + uint32_t tzc_glb_gpio_0_lock : 1; /* [ 0], r, 0x0 */ + uint32_t tzc_glb_gpio_1_lock : 1; /* [ 1], r, 0x0 */ + uint32_t tzc_glb_gpio_2_lock : 1; /* [ 2], r, 0x0 */ + uint32_t tzc_glb_gpio_3_lock : 1; /* [ 3], r, 0x0 */ + uint32_t tzc_glb_gpio_4_lock : 1; /* [ 4], r, 0x0 */ + uint32_t tzc_glb_gpio_5_lock : 1; /* [ 5], r, 0x0 */ + uint32_t tzc_glb_gpio_6_lock : 1; /* [ 6], r, 0x0 */ + uint32_t tzc_glb_gpio_7_lock : 1; /* [ 7], r, 0x0 */ + uint32_t tzc_glb_gpio_8_lock : 1; /* [ 8], r, 0x0 */ + uint32_t tzc_glb_gpio_9_lock : 1; /* [ 9], r, 0x0 */ + uint32_t tzc_glb_gpio_10_lock : 1; /* [ 10], r, 0x0 */ + uint32_t tzc_glb_gpio_11_lock : 1; /* [ 11], r, 0x0 */ + uint32_t tzc_glb_gpio_12_lock : 1; /* [ 12], r, 0x0 */ + uint32_t tzc_glb_gpio_13_lock : 1; /* [ 13], r, 0x0 */ + uint32_t tzc_glb_gpio_14_lock : 1; /* [ 14], r, 0x0 */ + uint32_t tzc_glb_gpio_15_lock : 1; /* [ 15], r, 0x0 */ + uint32_t tzc_glb_gpio_16_lock : 1; /* [ 16], r, 0x0 */ + uint32_t tzc_glb_gpio_17_lock : 1; /* [ 17], r, 0x0 */ + uint32_t tzc_glb_gpio_18_lock : 1; /* [ 18], r, 0x0 */ + uint32_t tzc_glb_gpio_19_lock : 1; /* [ 19], r, 0x0 */ + uint32_t tzc_glb_gpio_20_lock : 1; /* [ 20], r, 0x0 */ + uint32_t tzc_glb_gpio_21_lock : 1; /* [ 21], r, 0x0 */ + uint32_t tzc_glb_gpio_22_lock : 1; /* [ 22], r, 0x0 */ + uint32_t tzc_glb_gpio_23_lock : 1; /* [ 23], r, 0x0 */ + uint32_t tzc_glb_gpio_24_lock : 1; /* [ 24], r, 0x0 */ + uint32_t tzc_glb_gpio_25_lock : 1; /* [ 25], r, 0x0 */ + uint32_t tzc_glb_gpio_26_lock : 1; /* [ 26], r, 0x0 */ + uint32_t tzc_glb_gpio_27_lock : 1; /* [ 27], r, 0x0 */ + uint32_t tzc_glb_gpio_28_lock : 1; /* [ 28], r, 0x0 */ + uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } tzc_glb_ctrl_2; + + /* 0xF0C : tzc_glb_ctrl_3 */ + union { + struct + { + uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } tzc_glb_ctrl_3; +}; + +typedef volatile struct glb_reg glb_reg_t; + +/*Following is reg patch*/ + +/* 0x0 : GPIO_CFGCTL */ +#define GLB_GPIO_CFGCTL_OFFSET (0x0) +#define GLB_REG_GPIO_0_IE GLB_REG_GPIO_0_IE +#define GLB_REG_GPIO_0_IE_POS (0U) +#define GLB_REG_GPIO_0_IE_LEN (1U) +#define GLB_REG_GPIO_0_IE_MSK (((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS) +#define GLB_REG_GPIO_0_IE_UMSK (~(((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)) +#define GLB_REG_GPIO_0_SMT GLB_REG_GPIO_0_SMT +#define GLB_REG_GPIO_0_SMT_POS (1U) +#define GLB_REG_GPIO_0_SMT_LEN (1U) +#define GLB_REG_GPIO_0_SMT_MSK (((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS) +#define GLB_REG_GPIO_0_SMT_UMSK (~(((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)) +#define GLB_REG_GPIO_0_DRV GLB_REG_GPIO_0_DRV +#define GLB_REG_GPIO_0_DRV_POS (2U) +#define GLB_REG_GPIO_0_DRV_LEN (2U) +#define GLB_REG_GPIO_0_DRV_MSK (((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS) +#define GLB_REG_GPIO_0_DRV_UMSK (~(((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)) +#define GLB_REG_GPIO_0_PU GLB_REG_GPIO_0_PU +#define GLB_REG_GPIO_0_PU_POS (4U) +#define GLB_REG_GPIO_0_PU_LEN (1U) +#define GLB_REG_GPIO_0_PU_MSK (((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS) +#define GLB_REG_GPIO_0_PU_UMSK (~(((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)) +#define GLB_REG_GPIO_0_PD GLB_REG_GPIO_0_PD +#define GLB_REG_GPIO_0_PD_POS (5U) +#define GLB_REG_GPIO_0_PD_LEN (1U) +#define GLB_REG_GPIO_0_PD_MSK (((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS) +#define GLB_REG_GPIO_0_PD_UMSK (~(((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)) +#define GLB_REG_GPIO_0_FUNC_SEL GLB_REG_GPIO_0_FUNC_SEL +#define GLB_REG_GPIO_0_FUNC_SEL_POS (8U) +#define GLB_REG_GPIO_0_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_0_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS) +#define GLB_REG_GPIO_0_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)) +#define GLB_REAL_GPIO_0_FUNC_SEL GLB_REAL_GPIO_0_FUNC_SEL +#define GLB_REAL_GPIO_0_FUNC_SEL_POS (12U) +#define GLB_REAL_GPIO_0_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_0_FUNC_SEL_MSK (((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS) +#define GLB_REAL_GPIO_0_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS)) +#define GLB_REG_GPIO_1_IE GLB_REG_GPIO_1_IE +#define GLB_REG_GPIO_1_IE_POS (16U) +#define GLB_REG_GPIO_1_IE_LEN (1U) +#define GLB_REG_GPIO_1_IE_MSK (((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS) +#define GLB_REG_GPIO_1_IE_UMSK (~(((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)) +#define GLB_REG_GPIO_1_SMT GLB_REG_GPIO_1_SMT +#define GLB_REG_GPIO_1_SMT_POS (17U) +#define GLB_REG_GPIO_1_SMT_LEN (1U) +#define GLB_REG_GPIO_1_SMT_MSK (((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS) +#define GLB_REG_GPIO_1_SMT_UMSK (~(((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)) +#define GLB_REG_GPIO_1_DRV GLB_REG_GPIO_1_DRV +#define GLB_REG_GPIO_1_DRV_POS (18U) +#define GLB_REG_GPIO_1_DRV_LEN (2U) +#define GLB_REG_GPIO_1_DRV_MSK (((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS) +#define GLB_REG_GPIO_1_DRV_UMSK (~(((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)) +#define GLB_REG_GPIO_1_PU GLB_REG_GPIO_1_PU +#define GLB_REG_GPIO_1_PU_POS (20U) +#define GLB_REG_GPIO_1_PU_LEN (1U) +#define GLB_REG_GPIO_1_PU_MSK (((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS) +#define GLB_REG_GPIO_1_PU_UMSK (~(((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)) +#define GLB_REG_GPIO_1_PD GLB_REG_GPIO_1_PD +#define GLB_REG_GPIO_1_PD_POS (21U) +#define GLB_REG_GPIO_1_PD_LEN (1U) +#define GLB_REG_GPIO_1_PD_MSK (((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS) +#define GLB_REG_GPIO_1_PD_UMSK (~(((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)) +#define GLB_REG_GPIO_1_FUNC_SEL GLB_REG_GPIO_1_FUNC_SEL +#define GLB_REG_GPIO_1_FUNC_SEL_POS (24U) +#define GLB_REG_GPIO_1_FUNC_SEL_LEN (4U) +#define GLB_REG_GPIO_1_FUNC_SEL_MSK (((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS) +#define GLB_REG_GPIO_1_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)) +#define GLB_REAL_GPIO_1_FUNC_SEL GLB_REAL_GPIO_1_FUNC_SEL +#define GLB_REAL_GPIO_1_FUNC_SEL_POS (28U) +#define GLB_REAL_GPIO_1_FUNC_SEL_LEN (4U) +#define GLB_REAL_GPIO_1_FUNC_SEL_MSK (((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS) +#define GLB_REAL_GPIO_1_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS)) + +struct glb_gpio_reg { + /* 0x0 : GPIO_CFGCTL */ + union { + struct + { + uint32_t reg_gpio_0_ie : 1; /* [ 0], r/w, 0x1 */ + uint32_t reg_gpio_0_smt : 1; /* [ 1], r/w, 0x1 */ + uint32_t reg_gpio_0_drv : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t reg_gpio_0_pu : 1; /* [ 4], r/w, 0x0 */ + uint32_t reg_gpio_0_pd : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t reg_gpio_0_func_sel : 4; /* [11: 8], r/w, 0x1 */ + uint32_t real_gpio_0_func_sel : 4; /* [15:12], r, 0x1 */ + uint32_t reg_gpio_1_ie : 1; /* [ 16], r/w, 0x1 */ + uint32_t reg_gpio_1_smt : 1; /* [ 17], r/w, 0x1 */ + uint32_t reg_gpio_1_drv : 2; /* [19:18], r/w, 0x0 */ + uint32_t reg_gpio_1_pu : 1; /* [ 20], r/w, 0x0 */ + uint32_t reg_gpio_1_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t reg_gpio_1_func_sel : 4; /* [27:24], r/w, 0x1 */ + uint32_t real_gpio_1_func_sel : 4; /* [31:28], r, 0x1 */ + } BF; + uint32_t WORD; + } GPIO_CFGCTL; +}; + +typedef volatile struct glb_gpio_reg glb_gpio_reg_t; + +#define GLB_GPIO_OFFSET 0x100 +#define GLB_GPIO_INPUT_OFFSET 0x180 +#define GLB_GPIO_OUTPUT_OFFSET 0x188 +#define GLB_GPIO_OUTPUT_EN_OFFSET 0x190 + +#endif /* __GLB_REG_H__ */ diff --git a/drivers/soc/bl602/bl602_std/include/hardware/hbn_reg.h b/drivers/soc/bl602/bl602_std/include/hardware/hbn_reg.h new file mode 100644 index 00000000..1aef0ab7 --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/hardware/hbn_reg.h @@ -0,0 +1,760 @@ +/** + ****************************************************************************** + * @file hbn_reg.h + * @version V1.2 + * @date 2020-04-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HBN_REG_H__ +#define __HBN_REG_H__ + +#include "bl602.h" + +/* 0x0 : HBN_CTL */ +#define HBN_CTL_OFFSET (0x0) +#define HBN_RTC_CTL HBN_RTC_CTL +#define HBN_RTC_CTL_POS (0U) +#define HBN_RTC_CTL_LEN (7U) +#define HBN_RTC_CTL_MSK (((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS) +#define HBN_RTC_CTL_UMSK (~(((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS)) +#define HBN_MODE HBN_MODE +#define HBN_MODE_POS (7U) +#define HBN_MODE_LEN (1U) +#define HBN_MODE_MSK (((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS) +#define HBN_MODE_UMSK (~(((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS)) +#define HBN_TRAP_MODE HBN_TRAP_MODE +#define HBN_TRAP_MODE_POS (8U) +#define HBN_TRAP_MODE_LEN (1U) +#define HBN_TRAP_MODE_MSK (((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS) +#define HBN_TRAP_MODE_UMSK (~(((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS)) +#define HBN_PWRDN_HBN_CORE HBN_PWRDN_HBN_CORE +#define HBN_PWRDN_HBN_CORE_POS (9U) +#define HBN_PWRDN_HBN_CORE_LEN (1U) +#define HBN_PWRDN_HBN_CORE_MSK (((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS) +#define HBN_PWRDN_HBN_CORE_UMSK (~(((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS)) +#define HBN_PWRDN_HBN_RTC HBN_PWRDN_HBN_RTC +#define HBN_PWRDN_HBN_RTC_POS (11U) +#define HBN_PWRDN_HBN_RTC_LEN (1U) +#define HBN_PWRDN_HBN_RTC_MSK (((1U << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS) +#define HBN_PWRDN_HBN_RTC_UMSK (~(((1U << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS)) +#define HBN_SW_RST HBN_SW_RST +#define HBN_SW_RST_POS (12U) +#define HBN_SW_RST_LEN (1U) +#define HBN_SW_RST_MSK (((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS) +#define HBN_SW_RST_UMSK (~(((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS)) +#define HBN_DIS_PWR_OFF_LDO11 HBN_DIS_PWR_OFF_LDO11 +#define HBN_DIS_PWR_OFF_LDO11_POS (13U) +#define HBN_DIS_PWR_OFF_LDO11_LEN (1U) +#define HBN_DIS_PWR_OFF_LDO11_MSK (((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS) +#define HBN_DIS_PWR_OFF_LDO11_UMSK (~(((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS)) +#define HBN_DIS_PWR_OFF_LDO11_RT HBN_DIS_PWR_OFF_LDO11_RT +#define HBN_DIS_PWR_OFF_LDO11_RT_POS (14U) +#define HBN_DIS_PWR_OFF_LDO11_RT_LEN (1U) +#define HBN_DIS_PWR_OFF_LDO11_RT_MSK (((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS) +#define HBN_DIS_PWR_OFF_LDO11_RT_UMSK (~(((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS)) +#define HBN_LDO11_RT_VOUT_SEL HBN_LDO11_RT_VOUT_SEL +#define HBN_LDO11_RT_VOUT_SEL_POS (15U) +#define HBN_LDO11_RT_VOUT_SEL_LEN (4U) +#define HBN_LDO11_RT_VOUT_SEL_MSK (((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS) +#define HBN_LDO11_RT_VOUT_SEL_UMSK (~(((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS)) +#define HBN_LDO11_AON_VOUT_SEL HBN_LDO11_AON_VOUT_SEL +#define HBN_LDO11_AON_VOUT_SEL_POS (19U) +#define HBN_LDO11_AON_VOUT_SEL_LEN (4U) +#define HBN_LDO11_AON_VOUT_SEL_MSK (((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS) +#define HBN_LDO11_AON_VOUT_SEL_UMSK (~(((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS)) +#define HBN_PU_DCDC18_AON HBN_PU_DCDC18_AON +#define HBN_PU_DCDC18_AON_POS (23U) +#define HBN_PU_DCDC18_AON_LEN (1U) +#define HBN_PU_DCDC18_AON_MSK (((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS) +#define HBN_PU_DCDC18_AON_UMSK (~(((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS)) +#define HBN_RTC_DLY_OPTION HBN_RTC_DLY_OPTION +#define HBN_RTC_DLY_OPTION_POS (24U) +#define HBN_RTC_DLY_OPTION_LEN (1U) +#define HBN_RTC_DLY_OPTION_MSK (((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS) +#define HBN_RTC_DLY_OPTION_UMSK (~(((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS)) +#define HBN_PWR_ON_OPTION HBN_PWR_ON_OPTION +#define HBN_PWR_ON_OPTION_POS (25U) +#define HBN_PWR_ON_OPTION_LEN (1U) +#define HBN_PWR_ON_OPTION_MSK (((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS) +#define HBN_PWR_ON_OPTION_UMSK (~(((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS)) +#define HBN_SRAM_SLP_OPTION HBN_SRAM_SLP_OPTION +#define HBN_SRAM_SLP_OPTION_POS (26U) +#define HBN_SRAM_SLP_OPTION_LEN (1U) +#define HBN_SRAM_SLP_OPTION_MSK (((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS) +#define HBN_SRAM_SLP_OPTION_UMSK (~(((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS)) +#define HBN_SRAM_SLP HBN_SRAM_SLP +#define HBN_SRAM_SLP_POS (27U) +#define HBN_SRAM_SLP_LEN (1U) +#define HBN_SRAM_SLP_MSK (((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS) +#define HBN_SRAM_SLP_UMSK (~(((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS)) +#define HBN_STATE HBN_STATE +#define HBN_STATE_POS (28U) +#define HBN_STATE_LEN (4U) +#define HBN_STATE_MSK (((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS) +#define HBN_STATE_UMSK (~(((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS)) + +/* 0x4 : HBN_TIME_L */ +#define HBN_TIME_L_OFFSET (0x4) +#define HBN_TIME_L HBN_TIME_L +#define HBN_TIME_L_POS (0U) +#define HBN_TIME_L_LEN (32U) +#define HBN_TIME_L_MSK (((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS) +#define HBN_TIME_L_UMSK (~(((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS)) + +/* 0x8 : HBN_TIME_H */ +#define HBN_TIME_H_OFFSET (0x8) +#define HBN_TIME_H HBN_TIME_H +#define HBN_TIME_H_POS (0U) +#define HBN_TIME_H_LEN (8U) +#define HBN_TIME_H_MSK (((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS) +#define HBN_TIME_H_UMSK (~(((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS)) + +/* 0xC : RTC_TIME_L */ +#define HBN_RTC_TIME_L_OFFSET (0xC) +#define HBN_RTC_TIME_LATCH_L HBN_RTC_TIME_LATCH_L +#define HBN_RTC_TIME_LATCH_L_POS (0U) +#define HBN_RTC_TIME_LATCH_L_LEN (32U) +#define HBN_RTC_TIME_LATCH_L_MSK (((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS) +#define HBN_RTC_TIME_LATCH_L_UMSK (~(((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS)) + +/* 0x10 : RTC_TIME_H */ +#define HBN_RTC_TIME_H_OFFSET (0x10) +#define HBN_RTC_TIME_LATCH_H HBN_RTC_TIME_LATCH_H +#define HBN_RTC_TIME_LATCH_H_POS (0U) +#define HBN_RTC_TIME_LATCH_H_LEN (8U) +#define HBN_RTC_TIME_LATCH_H_MSK (((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS) +#define HBN_RTC_TIME_LATCH_H_UMSK (~(((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS)) +#define HBN_RTC_TIME_LATCH HBN_RTC_TIME_LATCH +#define HBN_RTC_TIME_LATCH_POS (31U) +#define HBN_RTC_TIME_LATCH_LEN (1U) +#define HBN_RTC_TIME_LATCH_MSK (((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS) +#define HBN_RTC_TIME_LATCH_UMSK (~(((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS)) + +/* 0x14 : HBN_IRQ_MODE */ +#define HBN_IRQ_MODE_OFFSET (0x14) +#define HBN_PIN_WAKEUP_MODE HBN_PIN_WAKEUP_MODE +#define HBN_PIN_WAKEUP_MODE_POS (0U) +#define HBN_PIN_WAKEUP_MODE_LEN (3U) +#define HBN_PIN_WAKEUP_MODE_MSK (((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS) +#define HBN_PIN_WAKEUP_MODE_UMSK (~(((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS)) +#define HBN_PIN_WAKEUP_MASK HBN_PIN_WAKEUP_MASK +#define HBN_PIN_WAKEUP_MASK_POS (3U) +#define HBN_PIN_WAKEUP_MASK_LEN (2U) +#define HBN_PIN_WAKEUP_MASK_MSK (((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS) +#define HBN_PIN_WAKEUP_MASK_UMSK (~(((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS)) +#define HBN_REG_AON_PAD_IE_SMT HBN_REG_AON_PAD_IE_SMT +#define HBN_REG_AON_PAD_IE_SMT_POS (8U) +#define HBN_REG_AON_PAD_IE_SMT_LEN (1U) +#define HBN_REG_AON_PAD_IE_SMT_MSK (((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS) +#define HBN_REG_AON_PAD_IE_SMT_UMSK (~(((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS)) +#define HBN_REG_EN_HW_PU_PD HBN_REG_EN_HW_PU_PD +#define HBN_REG_EN_HW_PU_PD_POS (16U) +#define HBN_REG_EN_HW_PU_PD_LEN (1U) +#define HBN_REG_EN_HW_PU_PD_MSK (((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS) +#define HBN_REG_EN_HW_PU_PD_UMSK (~(((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS)) +#define HBN_IRQ_BOR_EN HBN_IRQ_BOR_EN +#define HBN_IRQ_BOR_EN_POS (18U) +#define HBN_IRQ_BOR_EN_LEN (1U) +#define HBN_IRQ_BOR_EN_MSK (((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS) +#define HBN_IRQ_BOR_EN_UMSK (~(((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS)) +#define HBN_IRQ_ACOMP0_EN HBN_IRQ_ACOMP0_EN +#define HBN_IRQ_ACOMP0_EN_POS (20U) +#define HBN_IRQ_ACOMP0_EN_LEN (2U) +#define HBN_IRQ_ACOMP0_EN_MSK (((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS) +#define HBN_IRQ_ACOMP0_EN_UMSK (~(((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS)) +#define HBN_IRQ_ACOMP1_EN HBN_IRQ_ACOMP1_EN +#define HBN_IRQ_ACOMP1_EN_POS (22U) +#define HBN_IRQ_ACOMP1_EN_LEN (2U) +#define HBN_IRQ_ACOMP1_EN_MSK (((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS) +#define HBN_IRQ_ACOMP1_EN_UMSK (~(((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS)) +#define HBN_PIN_WAKEUP_SEL HBN_PIN_WAKEUP_SEL +#define HBN_PIN_WAKEUP_SEL_POS (24U) +#define HBN_PIN_WAKEUP_SEL_LEN (3U) +#define HBN_PIN_WAKEUP_SEL_MSK (((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS) +#define HBN_PIN_WAKEUP_SEL_UMSK (~(((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS)) +#define HBN_PIN_WAKEUP_EN HBN_PIN_WAKEUP_EN +#define HBN_PIN_WAKEUP_EN_POS (27U) +#define HBN_PIN_WAKEUP_EN_LEN (1U) +#define HBN_PIN_WAKEUP_EN_MSK (((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS) +#define HBN_PIN_WAKEUP_EN_UMSK (~(((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS)) + +/* 0x18 : HBN_IRQ_STAT */ +#define HBN_IRQ_STAT_OFFSET (0x18) +#define HBN_IRQ_STAT HBN_IRQ_STAT +#define HBN_IRQ_STAT_POS (0U) +#define HBN_IRQ_STAT_LEN (32U) +#define HBN_IRQ_STAT_MSK (((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS) +#define HBN_IRQ_STAT_UMSK (~(((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS)) + +/* 0x1C : HBN_IRQ_CLR */ +#define HBN_IRQ_CLR_OFFSET (0x1C) +#define HBN_IRQ_CLR HBN_IRQ_CLR +#define HBN_IRQ_CLR_POS (0U) +#define HBN_IRQ_CLR_LEN (32U) +#define HBN_IRQ_CLR_MSK (((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS) +#define HBN_IRQ_CLR_UMSK (~(((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS)) + +/* 0x20 : HBN_PIR_CFG */ +#define HBN_PIR_CFG_OFFSET (0x20) +#define HBN_PIR_HPF_SEL HBN_PIR_HPF_SEL +#define HBN_PIR_HPF_SEL_POS (0U) +#define HBN_PIR_HPF_SEL_LEN (2U) +#define HBN_PIR_HPF_SEL_MSK (((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS) +#define HBN_PIR_HPF_SEL_UMSK (~(((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS)) +#define HBN_PIR_LPF_SEL HBN_PIR_LPF_SEL +#define HBN_PIR_LPF_SEL_POS (2U) +#define HBN_PIR_LPF_SEL_LEN (1U) +#define HBN_PIR_LPF_SEL_MSK (((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS) +#define HBN_PIR_LPF_SEL_UMSK (~(((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS)) +#define HBN_PIR_DIS HBN_PIR_DIS +#define HBN_PIR_DIS_POS (4U) +#define HBN_PIR_DIS_LEN (2U) +#define HBN_PIR_DIS_MSK (((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS) +#define HBN_PIR_DIS_UMSK (~(((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS)) +#define HBN_PIR_EN HBN_PIR_EN +#define HBN_PIR_EN_POS (7U) +#define HBN_PIR_EN_LEN (1U) +#define HBN_PIR_EN_MSK (((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS) +#define HBN_PIR_EN_UMSK (~(((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS)) +#define HBN_GPADC_CGEN HBN_GPADC_CGEN +#define HBN_GPADC_CGEN_POS (8U) +#define HBN_GPADC_CGEN_LEN (1U) +#define HBN_GPADC_CGEN_MSK (((1U << HBN_GPADC_CGEN_LEN) - 1) << HBN_GPADC_CGEN_POS) +#define HBN_GPADC_CGEN_UMSK (~(((1U << HBN_GPADC_CGEN_LEN) - 1) << HBN_GPADC_CGEN_POS)) +#define HBN_GPADC_NOSYNC HBN_GPADC_NOSYNC +#define HBN_GPADC_NOSYNC_POS (9U) +#define HBN_GPADC_NOSYNC_LEN (1U) +#define HBN_GPADC_NOSYNC_MSK (((1U << HBN_GPADC_NOSYNC_LEN) - 1) << HBN_GPADC_NOSYNC_POS) +#define HBN_GPADC_NOSYNC_UMSK (~(((1U << HBN_GPADC_NOSYNC_LEN) - 1) << HBN_GPADC_NOSYNC_POS)) + +/* 0x24 : HBN_PIR_VTH */ +#define HBN_PIR_VTH_OFFSET (0x24) +#define HBN_PIR_VTH HBN_PIR_VTH +#define HBN_PIR_VTH_POS (0U) +#define HBN_PIR_VTH_LEN (14U) +#define HBN_PIR_VTH_MSK (((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS) +#define HBN_PIR_VTH_UMSK (~(((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS)) + +/* 0x28 : HBN_PIR_INTERVAL */ +#define HBN_PIR_INTERVAL_OFFSET (0x28) +#define HBN_PIR_INTERVAL HBN_PIR_INTERVAL +#define HBN_PIR_INTERVAL_POS (0U) +#define HBN_PIR_INTERVAL_LEN (12U) +#define HBN_PIR_INTERVAL_MSK (((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS) +#define HBN_PIR_INTERVAL_UMSK (~(((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS)) + +/* 0x2C : HBN_BOR_CFG */ +#define HBN_BOR_CFG_OFFSET (0x2C) +#define HBN_BOR_SEL HBN_BOR_SEL +#define HBN_BOR_SEL_POS (0U) +#define HBN_BOR_SEL_LEN (1U) +#define HBN_BOR_SEL_MSK (((1U << HBN_BOR_SEL_LEN) - 1) << HBN_BOR_SEL_POS) +#define HBN_BOR_SEL_UMSK (~(((1U << HBN_BOR_SEL_LEN) - 1) << HBN_BOR_SEL_POS)) +#define HBN_BOR_VTH HBN_BOR_VTH +#define HBN_BOR_VTH_POS (1U) +#define HBN_BOR_VTH_LEN (1U) +#define HBN_BOR_VTH_MSK (((1U << HBN_BOR_VTH_LEN) - 1) << HBN_BOR_VTH_POS) +#define HBN_BOR_VTH_UMSK (~(((1U << HBN_BOR_VTH_LEN) - 1) << HBN_BOR_VTH_POS)) +#define HBN_PU_BOR HBN_PU_BOR +#define HBN_PU_BOR_POS (2U) +#define HBN_PU_BOR_LEN (1U) +#define HBN_PU_BOR_MSK (((1U << HBN_PU_BOR_LEN) - 1) << HBN_PU_BOR_POS) +#define HBN_PU_BOR_UMSK (~(((1U << HBN_PU_BOR_LEN) - 1) << HBN_PU_BOR_POS)) +#define HBN_R_BOR_OUT HBN_R_BOR_OUT +#define HBN_R_BOR_OUT_POS (3U) +#define HBN_R_BOR_OUT_LEN (1U) +#define HBN_R_BOR_OUT_MSK (((1U << HBN_R_BOR_OUT_LEN) - 1) << HBN_R_BOR_OUT_POS) +#define HBN_R_BOR_OUT_UMSK (~(((1U << HBN_R_BOR_OUT_LEN) - 1) << HBN_R_BOR_OUT_POS)) + +/* 0x30 : HBN_GLB */ +#define HBN_GLB_OFFSET (0x30) +#define HBN_ROOT_CLK_SEL HBN_ROOT_CLK_SEL +#define HBN_ROOT_CLK_SEL_POS (0U) +#define HBN_ROOT_CLK_SEL_LEN (2U) +#define HBN_ROOT_CLK_SEL_MSK (((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS) +#define HBN_ROOT_CLK_SEL_UMSK (~(((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS)) +#define HBN_UART_CLK_SEL HBN_UART_CLK_SEL +#define HBN_UART_CLK_SEL_POS (2U) +#define HBN_UART_CLK_SEL_LEN (1U) +#define HBN_UART_CLK_SEL_MSK (((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS) +#define HBN_UART_CLK_SEL_UMSK (~(((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS)) +#define HBN_F32K_SEL HBN_F32K_SEL +#define HBN_F32K_SEL_POS (3U) +#define HBN_F32K_SEL_LEN (2U) +#define HBN_F32K_SEL_MSK (((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS) +#define HBN_F32K_SEL_UMSK (~(((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS)) +#define HBN_PU_RC32K HBN_PU_RC32K +#define HBN_PU_RC32K_POS (5U) +#define HBN_PU_RC32K_LEN (1U) +#define HBN_PU_RC32K_MSK (((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS) +#define HBN_PU_RC32K_UMSK (~(((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS)) +#define HBN_SW_LDO11SOC_VOUT_SEL_AON HBN_SW_LDO11SOC_VOUT_SEL_AON +#define HBN_SW_LDO11SOC_VOUT_SEL_AON_POS (16U) +#define HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN (4U) +#define HBN_SW_LDO11SOC_VOUT_SEL_AON_MSK (((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS) +#define HBN_SW_LDO11SOC_VOUT_SEL_AON_UMSK (~(((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS)) +#define HBN_SW_LDO11_RT_VOUT_SEL HBN_SW_LDO11_RT_VOUT_SEL +#define HBN_SW_LDO11_RT_VOUT_SEL_POS (24U) +#define HBN_SW_LDO11_RT_VOUT_SEL_LEN (4U) +#define HBN_SW_LDO11_RT_VOUT_SEL_MSK (((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS) +#define HBN_SW_LDO11_RT_VOUT_SEL_UMSK (~(((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS)) +#define HBN_SW_LDO11_AON_VOUT_SEL HBN_SW_LDO11_AON_VOUT_SEL +#define HBN_SW_LDO11_AON_VOUT_SEL_POS (28U) +#define HBN_SW_LDO11_AON_VOUT_SEL_LEN (4U) +#define HBN_SW_LDO11_AON_VOUT_SEL_MSK (((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_AON_VOUT_SEL_POS) +#define HBN_SW_LDO11_AON_VOUT_SEL_UMSK (~(((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_AON_VOUT_SEL_POS)) + +/* 0x34 : HBN_SRAM */ +#define HBN_SRAM_OFFSET (0x34) +#define HBN_RETRAM_RET HBN_RETRAM_RET +#define HBN_RETRAM_RET_POS (6U) +#define HBN_RETRAM_RET_LEN (1U) +#define HBN_RETRAM_RET_MSK (((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS) +#define HBN_RETRAM_RET_UMSK (~(((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS)) +#define HBN_RETRAM_SLP HBN_RETRAM_SLP +#define HBN_RETRAM_SLP_POS (7U) +#define HBN_RETRAM_SLP_LEN (1U) +#define HBN_RETRAM_SLP_MSK (((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS) +#define HBN_RETRAM_SLP_UMSK (~(((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS)) + +/* 0x100 : HBN_RSV0 */ +#define HBN_RSV0_OFFSET (0x100) +#define HBN_RSV0 HBN_RSV0 +#define HBN_RSV0_POS (0U) +#define HBN_RSV0_LEN (32U) +#define HBN_RSV0_MSK (((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS) +#define HBN_RSV0_UMSK (~(((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS)) + +/* 0x104 : HBN_RSV1 */ +#define HBN_RSV1_OFFSET (0x104) +#define HBN_RSV1 HBN_RSV1 +#define HBN_RSV1_POS (0U) +#define HBN_RSV1_LEN (32U) +#define HBN_RSV1_MSK (((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS) +#define HBN_RSV1_UMSK (~(((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS)) + +/* 0x108 : HBN_RSV2 */ +#define HBN_RSV2_OFFSET (0x108) +#define HBN_RSV2 HBN_RSV2 +#define HBN_RSV2_POS (0U) +#define HBN_RSV2_LEN (32U) +#define HBN_RSV2_MSK (((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS) +#define HBN_RSV2_UMSK (~(((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS)) + +/* 0x10C : HBN_RSV3 */ +#define HBN_RSV3_OFFSET (0x10C) +#define HBN_RSV3 HBN_RSV3 +#define HBN_RSV3_POS (0U) +#define HBN_RSV3_LEN (32U) +#define HBN_RSV3_MSK (((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS) +#define HBN_RSV3_UMSK (~(((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS)) + +/* 0x200 : rc32k_ctrl0 */ +#define HBN_RC32K_CTRL0_OFFSET (0x200) +#define HBN_RC32K_CAL_DONE HBN_RC32K_CAL_DONE +#define HBN_RC32K_CAL_DONE_POS (0U) +#define HBN_RC32K_CAL_DONE_LEN (1U) +#define HBN_RC32K_CAL_DONE_MSK (((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS) +#define HBN_RC32K_CAL_DONE_UMSK (~(((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS)) +#define HBN_RC32K_RDY HBN_RC32K_RDY +#define HBN_RC32K_RDY_POS (1U) +#define HBN_RC32K_RDY_LEN (1U) +#define HBN_RC32K_RDY_MSK (((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS) +#define HBN_RC32K_RDY_UMSK (~(((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS)) +#define HBN_RC32K_CAL_INPROGRESS HBN_RC32K_CAL_INPROGRESS +#define HBN_RC32K_CAL_INPROGRESS_POS (2U) +#define HBN_RC32K_CAL_INPROGRESS_LEN (1U) +#define HBN_RC32K_CAL_INPROGRESS_MSK (((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS) +#define HBN_RC32K_CAL_INPROGRESS_UMSK (~(((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS)) +#define HBN_RC32K_CAL_DIV HBN_RC32K_CAL_DIV +#define HBN_RC32K_CAL_DIV_POS (3U) +#define HBN_RC32K_CAL_DIV_LEN (2U) +#define HBN_RC32K_CAL_DIV_MSK (((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS) +#define HBN_RC32K_CAL_DIV_UMSK (~(((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS)) +#define HBN_RC32K_CAL_PRECHARGE HBN_RC32K_CAL_PRECHARGE +#define HBN_RC32K_CAL_PRECHARGE_POS (5U) +#define HBN_RC32K_CAL_PRECHARGE_LEN (1U) +#define HBN_RC32K_CAL_PRECHARGE_MSK (((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS) +#define HBN_RC32K_CAL_PRECHARGE_UMSK (~(((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS)) +#define HBN_RC32K_DIG_CODE_FR_CAL HBN_RC32K_DIG_CODE_FR_CAL +#define HBN_RC32K_DIG_CODE_FR_CAL_POS (6U) +#define HBN_RC32K_DIG_CODE_FR_CAL_LEN (10U) +#define HBN_RC32K_DIG_CODE_FR_CAL_MSK (((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) << HBN_RC32K_DIG_CODE_FR_CAL_POS) +#define HBN_RC32K_DIG_CODE_FR_CAL_UMSK (~(((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) << HBN_RC32K_DIG_CODE_FR_CAL_POS)) +#define HBN_RC32K_VREF_DLY HBN_RC32K_VREF_DLY +#define HBN_RC32K_VREF_DLY_POS (16U) +#define HBN_RC32K_VREF_DLY_LEN (2U) +#define HBN_RC32K_VREF_DLY_MSK (((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS) +#define HBN_RC32K_VREF_DLY_UMSK (~(((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS)) +#define HBN_RC32K_ALLOW_CAL HBN_RC32K_ALLOW_CAL +#define HBN_RC32K_ALLOW_CAL_POS (18U) +#define HBN_RC32K_ALLOW_CAL_LEN (1U) +#define HBN_RC32K_ALLOW_CAL_MSK (((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS) +#define HBN_RC32K_ALLOW_CAL_UMSK (~(((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS)) +#define HBN_RC32K_EXT_CODE_EN HBN_RC32K_EXT_CODE_EN +#define HBN_RC32K_EXT_CODE_EN_POS (19U) +#define HBN_RC32K_EXT_CODE_EN_LEN (1U) +#define HBN_RC32K_EXT_CODE_EN_MSK (((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS) +#define HBN_RC32K_EXT_CODE_EN_UMSK (~(((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS)) +#define HBN_RC32K_CAL_EN HBN_RC32K_CAL_EN +#define HBN_RC32K_CAL_EN_POS (20U) +#define HBN_RC32K_CAL_EN_LEN (1U) +#define HBN_RC32K_CAL_EN_MSK (((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS) +#define HBN_RC32K_CAL_EN_UMSK (~(((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS)) +#define HBN_RC32K_CODE_FR_EXT HBN_RC32K_CODE_FR_EXT +#define HBN_RC32K_CODE_FR_EXT_POS (22U) +#define HBN_RC32K_CODE_FR_EXT_LEN (10U) +#define HBN_RC32K_CODE_FR_EXT_MSK (((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS) +#define HBN_RC32K_CODE_FR_EXT_UMSK (~(((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS)) + +/* 0x204 : xtal32k */ +#define HBN_XTAL32K_OFFSET (0x204) +#define HBN_XTAL32K_EXT_SEL HBN_XTAL32K_EXT_SEL +#define HBN_XTAL32K_EXT_SEL_POS (2U) +#define HBN_XTAL32K_EXT_SEL_LEN (1U) +#define HBN_XTAL32K_EXT_SEL_MSK (((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS) +#define HBN_XTAL32K_EXT_SEL_UMSK (~(((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS)) +#define HBN_XTAL32K_AMP_CTRL HBN_XTAL32K_AMP_CTRL +#define HBN_XTAL32K_AMP_CTRL_POS (3U) +#define HBN_XTAL32K_AMP_CTRL_LEN (2U) +#define HBN_XTAL32K_AMP_CTRL_MSK (((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS) +#define HBN_XTAL32K_AMP_CTRL_UMSK (~(((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS)) +#define HBN_XTAL32K_REG HBN_XTAL32K_REG +#define HBN_XTAL32K_REG_POS (5U) +#define HBN_XTAL32K_REG_LEN (2U) +#define HBN_XTAL32K_REG_MSK (((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS) +#define HBN_XTAL32K_REG_UMSK (~(((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS)) +#define HBN_XTAL32K_OUTBUF_STRE HBN_XTAL32K_OUTBUF_STRE +#define HBN_XTAL32K_OUTBUF_STRE_POS (7U) +#define HBN_XTAL32K_OUTBUF_STRE_LEN (1U) +#define HBN_XTAL32K_OUTBUF_STRE_MSK (((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS) +#define HBN_XTAL32K_OUTBUF_STRE_UMSK (~(((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS)) +#define HBN_XTAL32K_OTF_SHORT HBN_XTAL32K_OTF_SHORT +#define HBN_XTAL32K_OTF_SHORT_POS (8U) +#define HBN_XTAL32K_OTF_SHORT_LEN (1U) +#define HBN_XTAL32K_OTF_SHORT_MSK (((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS) +#define HBN_XTAL32K_OTF_SHORT_UMSK (~(((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS)) +#define HBN_XTAL32K_INV_STRE HBN_XTAL32K_INV_STRE +#define HBN_XTAL32K_INV_STRE_POS (9U) +#define HBN_XTAL32K_INV_STRE_LEN (2U) +#define HBN_XTAL32K_INV_STRE_MSK (((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS) +#define HBN_XTAL32K_INV_STRE_UMSK (~(((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS)) +#define HBN_XTAL32K_CAPBANK HBN_XTAL32K_CAPBANK +#define HBN_XTAL32K_CAPBANK_POS (11U) +#define HBN_XTAL32K_CAPBANK_LEN (6U) +#define HBN_XTAL32K_CAPBANK_MSK (((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS) +#define HBN_XTAL32K_CAPBANK_UMSK (~(((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS)) +#define HBN_XTAL32K_AC_CAP_SHORT HBN_XTAL32K_AC_CAP_SHORT +#define HBN_XTAL32K_AC_CAP_SHORT_POS (17U) +#define HBN_XTAL32K_AC_CAP_SHORT_LEN (1U) +#define HBN_XTAL32K_AC_CAP_SHORT_MSK (((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS) +#define HBN_XTAL32K_AC_CAP_SHORT_UMSK (~(((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS)) +#define HBN_PU_XTAL32K_BUF HBN_PU_XTAL32K_BUF +#define HBN_PU_XTAL32K_BUF_POS (18U) +#define HBN_PU_XTAL32K_BUF_LEN (1U) +#define HBN_PU_XTAL32K_BUF_MSK (((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS) +#define HBN_PU_XTAL32K_BUF_UMSK (~(((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS)) +#define HBN_PU_XTAL32K HBN_PU_XTAL32K +#define HBN_PU_XTAL32K_POS (19U) +#define HBN_PU_XTAL32K_LEN (1U) +#define HBN_PU_XTAL32K_MSK (((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS) +#define HBN_PU_XTAL32K_UMSK (~(((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS)) + +struct hbn_reg { + /* 0x0 : HBN_CTL */ + union { + struct + { + uint32_t rtc_ctl : 7; /* [ 6: 0], r/w, 0x0 */ + uint32_t hbn_mode : 1; /* [ 7], w, 0x0 */ + uint32_t trap_mode : 1; /* [ 8], r, 0x0 */ + uint32_t pwrdn_hbn_core : 1; /* [ 9], r/w, 0x0 */ + uint32_t reserved_10 : 1; /* [ 10], rsvd, 0x0 */ + uint32_t pwrdn_hbn_rtc : 1; /* [ 11], r/w, 0x0 */ + uint32_t sw_rst : 1; /* [ 12], r/w, 0x0 */ + uint32_t hbn_dis_pwr_off_ldo11 : 1; /* [ 13], r/w, 0x0 */ + uint32_t hbn_dis_pwr_off_ldo11_rt : 1; /* [ 14], r/w, 0x0 */ + uint32_t hbn_ldo11_rt_vout_sel : 4; /* [18:15], r/w, 0xa */ + uint32_t hbn_ldo11_aon_vout_sel : 4; /* [22:19], r/w, 0xa */ + uint32_t pu_dcdc18_aon : 1; /* [ 23], r/w, 0x1 */ + uint32_t rtc_dly_option : 1; /* [ 24], r/w, 0x0 */ + uint32_t pwr_on_option : 1; /* [ 25], r/w, 0x0 */ + uint32_t sram_slp_option : 1; /* [ 26], r/w, 0x0 */ + uint32_t sram_slp : 1; /* [ 27], r, 0x0 */ + uint32_t hbn_state : 4; /* [31:28], r, 0x0 */ + } BF; + uint32_t WORD; + } HBN_CTL; + + /* 0x4 : HBN_TIME_L */ + union { + struct + { + uint32_t hbn_time_l : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } HBN_TIME_L; + + /* 0x8 : HBN_TIME_H */ + union { + struct + { + uint32_t hbn_time_h : 8; /* [ 7: 0], r/w, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } HBN_TIME_H; + + /* 0xC : RTC_TIME_L */ + union { + struct + { + uint32_t rtc_time_latch_l : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } RTC_TIME_L; + + /* 0x10 : RTC_TIME_H */ + union { + struct + { + uint32_t rtc_time_latch_h : 8; /* [ 7: 0], r, 0x0 */ + uint32_t reserved_8_30 : 23; /* [30: 8], rsvd, 0x0 */ + uint32_t rtc_time_latch : 1; /* [ 31], w, 0x0 */ + } BF; + uint32_t WORD; + } RTC_TIME_H; + + /* 0x14 : HBN_IRQ_MODE */ + union { + struct + { + uint32_t hbn_pin_wakeup_mode : 3; /* [ 2: 0], r/w, 0x5 */ + uint32_t hbn_pin_wakeup_mask : 2; /* [ 4: 3], r/w, 0x0 */ + uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ + uint32_t reg_aon_pad_ie_smt : 1; /* [ 8], r/w, 0x1 */ + uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ + uint32_t reg_en_hw_pu_pd : 1; /* [ 16], r/w, 0x1 */ + uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */ + uint32_t irq_bor_en : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ + uint32_t irq_acomp0_en : 2; /* [21:20], r/w, 0x0 */ + uint32_t irq_acomp1_en : 2; /* [23:22], r/w, 0x0 */ + uint32_t pin_wakeup_sel : 3; /* [26:24], r/w, 0x3 */ + uint32_t pin_wakeup_en : 1; /* [ 27], r/w, 0x0 */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } HBN_IRQ_MODE; + + /* 0x18 : HBN_IRQ_STAT */ + union { + struct + { + uint32_t irq_stat : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } HBN_IRQ_STAT; + + /* 0x1C : HBN_IRQ_CLR */ + union { + struct + { + uint32_t irq_clr : 32; /* [31: 0], w, 0x0 */ + } BF; + uint32_t WORD; + } HBN_IRQ_CLR; + + /* 0x20 : HBN_PIR_CFG */ + union { + struct + { + uint32_t pir_hpf_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t pir_lpf_sel : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t pir_dis : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */ + uint32_t pir_en : 1; /* [ 7], r/w, 0x0 */ + uint32_t gpadc_cgen : 1; /* [ 8], r/w, 0x0 */ + uint32_t gpadc_nosync : 1; /* [ 9], r/w, 0x0 */ + uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } HBN_PIR_CFG; + + /* 0x24 : HBN_PIR_VTH */ + union { + struct + { + uint32_t pir_vth : 14; /* [13: 0], r/w, 0x3ff */ + uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } HBN_PIR_VTH; + + /* 0x28 : HBN_PIR_INTERVAL */ + union { + struct + { + uint32_t pir_interval : 12; /* [11: 0], r/w, 0xa3d */ + uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } HBN_PIR_INTERVAL; + + /* 0x2C : HBN_BOR_CFG */ + union { + struct + { + uint32_t bor_sel : 1; /* [ 0], r/w, 0x0 */ + uint32_t bor_vth : 1; /* [ 1], r/w, 0x1 */ + uint32_t pu_bor : 1; /* [ 2], r/w, 0x0 */ + uint32_t r_bor_out : 1; /* [ 3], r, 0x0 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } HBN_BOR_CFG; + + /* 0x30 : HBN_GLB */ + union { + struct + { + uint32_t hbn_root_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t hbn_uart_clk_sel : 1; /* [ 2], r/w, 0x0 */ + uint32_t hbn_f32k_sel : 2; /* [ 4: 3], r/w, 0x0 */ + uint32_t hbn_pu_rc32k : 1; /* [ 5], r/w, 0x1 */ + uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */ + uint32_t sw_ldo11soc_vout_sel_aon : 4; /* [19:16], r/w, 0xa */ + uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */ + uint32_t sw_ldo11_rt_vout_sel : 4; /* [27:24], r/w, 0xa */ + uint32_t sw_ldo11_aon_vout_sel : 4; /* [31:28], r/w, 0xa */ + } BF; + uint32_t WORD; + } HBN_GLB; + + /* 0x34 : HBN_SRAM */ + union { + struct + { + uint32_t reserved_0_5 : 6; /* [ 5: 0], rsvd, 0x0 */ + uint32_t retram_ret : 1; /* [ 6], r/w, 0x0 */ + uint32_t retram_slp : 1; /* [ 7], r/w, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } HBN_SRAM; + + /* 0x38 reserved */ + uint8_t RESERVED0x38[200]; + + /* 0x100 : HBN_RSV0 */ + union { + struct + { + uint32_t HBN_RSV0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } HBN_RSV0; + + /* 0x104 : HBN_RSV1 */ + union { + struct + { + uint32_t HBN_RSV1 : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } HBN_RSV1; + + /* 0x108 : HBN_RSV2 */ + union { + struct + { + uint32_t HBN_RSV2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } HBN_RSV2; + + /* 0x10C : HBN_RSV3 */ + union { + struct + { + uint32_t HBN_RSV3 : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } HBN_RSV3; + + /* 0x110 reserved */ + uint8_t RESERVED0x110[240]; + + /* 0x200 : rc32k_ctrl0 */ + union { + struct + { + uint32_t rc32k_cal_done : 1; /* [ 0], r, 0x1 */ + uint32_t rc32k_rdy : 1; /* [ 1], r, 0x1 */ + uint32_t rc32k_cal_inprogress : 1; /* [ 2], r, 0x0 */ + uint32_t rc32k_cal_div : 2; /* [ 4: 3], r/w, 0x3 */ + uint32_t rc32k_cal_precharge : 1; /* [ 5], r, 0x0 */ + uint32_t rc32k_dig_code_fr_cal : 10; /* [15: 6], r, 0x200 */ + uint32_t rc32k_vref_dly : 2; /* [17:16], r/w, 0x0 */ + uint32_t rc32k_allow_cal : 1; /* [ 18], r/w, 0x0 */ + uint32_t rc32k_ext_code_en : 1; /* [ 19], r/w, 0x1 */ + uint32_t rc32k_cal_en : 1; /* [ 20], r/w, 0x0 */ + uint32_t reserved_21 : 1; /* [ 21], rsvd, 0x0 */ + uint32_t rc32k_code_fr_ext : 10; /* [31:22], r/w, 0x140 */ + } BF; + uint32_t WORD; + } rc32k_ctrl0; + + /* 0x204 : xtal32k */ + union { + struct + { + uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ + uint32_t xtal32k_ext_sel : 1; /* [ 2], r/w, 0x0 */ + uint32_t xtal32k_amp_ctrl : 2; /* [ 4: 3], r/w, 0x1 */ + uint32_t xtal32k_reg : 2; /* [ 6: 5], r/w, 0x1 */ + uint32_t xtal32k_outbuf_stre : 1; /* [ 7], r/w, 0x0 */ + uint32_t xtal32k_otf_short : 1; /* [ 8], r/w, 0x0 */ + uint32_t xtal32k_inv_stre : 2; /* [10: 9], r/w, 0x1 */ + uint32_t xtal32k_capbank : 6; /* [16:11], r/w, 0x20 */ + uint32_t xtal32k_ac_cap_short : 1; /* [ 17], r/w, 0x1 */ + uint32_t pu_xtal32k_buf : 1; /* [ 18], r/w, 0x1 */ + uint32_t pu_xtal32k : 1; /* [ 19], r/w, 0x1 */ + uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } xtal32k; +}; + +typedef volatile struct hbn_reg hbn_reg_t; + +#endif /* __HBN_REG_H__ */ diff --git a/drivers/soc/bl602/bl602_std/include/hardware/pds_reg.h b/drivers/soc/bl602/bl602_std/include/hardware/pds_reg.h new file mode 100644 index 00000000..5b5ebe66 --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/hardware/pds_reg.h @@ -0,0 +1,1085 @@ +/** + ****************************************************************************** + * @file pds_reg.h + * @version V1.2 + * @date 2020-04-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __PDS_REG_H__ +#define __PDS_REG_H__ + +#include "bl602.h" + +/* 0x0 : PDS_CTL */ +#define PDS_CTL_OFFSET (0x0) +#define PDS_START_PS PDS_START_PS +#define PDS_START_PS_POS (0U) +#define PDS_START_PS_LEN (1U) +#define PDS_START_PS_MSK (((1U << PDS_START_PS_LEN) - 1) << PDS_START_PS_POS) +#define PDS_START_PS_UMSK (~(((1U << PDS_START_PS_LEN) - 1) << PDS_START_PS_POS)) +#define PDS_CR_SLEEP_FOREVER PDS_CR_SLEEP_FOREVER +#define PDS_CR_SLEEP_FOREVER_POS (1U) +#define PDS_CR_SLEEP_FOREVER_LEN (1U) +#define PDS_CR_SLEEP_FOREVER_MSK (((1U << PDS_CR_SLEEP_FOREVER_LEN) - 1) << PDS_CR_SLEEP_FOREVER_POS) +#define PDS_CR_SLEEP_FOREVER_UMSK (~(((1U << PDS_CR_SLEEP_FOREVER_LEN) - 1) << PDS_CR_SLEEP_FOREVER_POS)) +#define PDS_CR_XTAL_FORCE_OFF PDS_CR_XTAL_FORCE_OFF +#define PDS_CR_XTAL_FORCE_OFF_POS (2U) +#define PDS_CR_XTAL_FORCE_OFF_LEN (1U) +#define PDS_CR_XTAL_FORCE_OFF_MSK (((1U << PDS_CR_XTAL_FORCE_OFF_LEN) - 1) << PDS_CR_XTAL_FORCE_OFF_POS) +#define PDS_CR_XTAL_FORCE_OFF_UMSK (~(((1U << PDS_CR_XTAL_FORCE_OFF_LEN) - 1) << PDS_CR_XTAL_FORCE_OFF_POS)) +#define PDS_CR_WIFI_PDS_SAVE_STATE PDS_CR_WIFI_PDS_SAVE_STATE +#define PDS_CR_WIFI_PDS_SAVE_STATE_POS (3U) +#define PDS_CR_WIFI_PDS_SAVE_STATE_LEN (1U) +#define PDS_CR_WIFI_PDS_SAVE_STATE_MSK (((1U << PDS_CR_WIFI_PDS_SAVE_STATE_LEN) - 1) << PDS_CR_WIFI_PDS_SAVE_STATE_POS) +#define PDS_CR_WIFI_PDS_SAVE_STATE_UMSK (~(((1U << PDS_CR_WIFI_PDS_SAVE_STATE_LEN) - 1) << PDS_CR_WIFI_PDS_SAVE_STATE_POS)) +#define PDS_CR_PDS_PD_DCDC18 PDS_CR_PDS_PD_DCDC18 +#define PDS_CR_PDS_PD_DCDC18_POS (4U) +#define PDS_CR_PDS_PD_DCDC18_LEN (1U) +#define PDS_CR_PDS_PD_DCDC18_MSK (((1U << PDS_CR_PDS_PD_DCDC18_LEN) - 1) << PDS_CR_PDS_PD_DCDC18_POS) +#define PDS_CR_PDS_PD_DCDC18_UMSK (~(((1U << PDS_CR_PDS_PD_DCDC18_LEN) - 1) << PDS_CR_PDS_PD_DCDC18_POS)) +#define PDS_CR_PDS_PD_BG_SYS PDS_CR_PDS_PD_BG_SYS +#define PDS_CR_PDS_PD_BG_SYS_POS (5U) +#define PDS_CR_PDS_PD_BG_SYS_LEN (1U) +#define PDS_CR_PDS_PD_BG_SYS_MSK (((1U << PDS_CR_PDS_PD_BG_SYS_LEN) - 1) << PDS_CR_PDS_PD_BG_SYS_POS) +#define PDS_CR_PDS_PD_BG_SYS_UMSK (~(((1U << PDS_CR_PDS_PD_BG_SYS_LEN) - 1) << PDS_CR_PDS_PD_BG_SYS_POS)) +#define PDS_CR_PDS_GATE_CLK PDS_CR_PDS_GATE_CLK +#define PDS_CR_PDS_GATE_CLK_POS (8U) +#define PDS_CR_PDS_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_GATE_CLK_MSK (((1U << PDS_CR_PDS_GATE_CLK_LEN) - 1) << PDS_CR_PDS_GATE_CLK_POS) +#define PDS_CR_PDS_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_GATE_CLK_LEN) - 1) << PDS_CR_PDS_GATE_CLK_POS)) +#define PDS_CR_PDS_MEM_STBY PDS_CR_PDS_MEM_STBY +#define PDS_CR_PDS_MEM_STBY_POS (9U) +#define PDS_CR_PDS_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_MEM_STBY_MSK (((1U << PDS_CR_PDS_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MEM_STBY_POS) +#define PDS_CR_PDS_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MEM_STBY_POS)) +#define PDS_CR_PDS_ISO_EN PDS_CR_PDS_ISO_EN +#define PDS_CR_PDS_ISO_EN_POS (11U) +#define PDS_CR_PDS_ISO_EN_LEN (1U) +#define PDS_CR_PDS_ISO_EN_MSK (((1U << PDS_CR_PDS_ISO_EN_LEN) - 1) << PDS_CR_PDS_ISO_EN_POS) +#define PDS_CR_PDS_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_ISO_EN_LEN) - 1) << PDS_CR_PDS_ISO_EN_POS)) +#define PDS_CR_PDS_WAIT_XTAL_RDY PDS_CR_PDS_WAIT_XTAL_RDY +#define PDS_CR_PDS_WAIT_XTAL_RDY_POS (12U) +#define PDS_CR_PDS_WAIT_XTAL_RDY_LEN (1U) +#define PDS_CR_PDS_WAIT_XTAL_RDY_MSK (((1U << PDS_CR_PDS_WAIT_XTAL_RDY_LEN) - 1) << PDS_CR_PDS_WAIT_XTAL_RDY_POS) +#define PDS_CR_PDS_WAIT_XTAL_RDY_UMSK (~(((1U << PDS_CR_PDS_WAIT_XTAL_RDY_LEN) - 1) << PDS_CR_PDS_WAIT_XTAL_RDY_POS)) +#define PDS_CR_PDS_PWR_OFF PDS_CR_PDS_PWR_OFF +#define PDS_CR_PDS_PWR_OFF_POS (13U) +#define PDS_CR_PDS_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_PWR_OFF_MSK (((1U << PDS_CR_PDS_PWR_OFF_LEN) - 1) << PDS_CR_PDS_PWR_OFF_POS) +#define PDS_CR_PDS_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_PWR_OFF_LEN) - 1) << PDS_CR_PDS_PWR_OFF_POS)) +#define PDS_CR_PDS_PD_XTAL PDS_CR_PDS_PD_XTAL +#define PDS_CR_PDS_PD_XTAL_POS (14U) +#define PDS_CR_PDS_PD_XTAL_LEN (1U) +#define PDS_CR_PDS_PD_XTAL_MSK (((1U << PDS_CR_PDS_PD_XTAL_LEN) - 1) << PDS_CR_PDS_PD_XTAL_POS) +#define PDS_CR_PDS_PD_XTAL_UMSK (~(((1U << PDS_CR_PDS_PD_XTAL_LEN) - 1) << PDS_CR_PDS_PD_XTAL_POS)) +#define PDS_CR_PDS_SOC_ENB_FORCE_ON PDS_CR_PDS_SOC_ENB_FORCE_ON +#define PDS_CR_PDS_SOC_ENB_FORCE_ON_POS (15U) +#define PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN (1U) +#define PDS_CR_PDS_SOC_ENB_FORCE_ON_MSK (((1U << PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN) - 1) << PDS_CR_PDS_SOC_ENB_FORCE_ON_POS) +#define PDS_CR_PDS_SOC_ENB_FORCE_ON_UMSK (~(((1U << PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN) - 1) << PDS_CR_PDS_SOC_ENB_FORCE_ON_POS)) +#define PDS_CR_PDS_RST_SOC_EN PDS_CR_PDS_RST_SOC_EN +#define PDS_CR_PDS_RST_SOC_EN_POS (16U) +#define PDS_CR_PDS_RST_SOC_EN_LEN (1U) +#define PDS_CR_PDS_RST_SOC_EN_MSK (((1U << PDS_CR_PDS_RST_SOC_EN_LEN) - 1) << PDS_CR_PDS_RST_SOC_EN_POS) +#define PDS_CR_PDS_RST_SOC_EN_UMSK (~(((1U << PDS_CR_PDS_RST_SOC_EN_LEN) - 1) << PDS_CR_PDS_RST_SOC_EN_POS)) +#define PDS_CR_PDS_RC32M_OFF_DIS PDS_CR_PDS_RC32M_OFF_DIS +#define PDS_CR_PDS_RC32M_OFF_DIS_POS (17U) +#define PDS_CR_PDS_RC32M_OFF_DIS_LEN (1U) +#define PDS_CR_PDS_RC32M_OFF_DIS_MSK (((1U << PDS_CR_PDS_RC32M_OFF_DIS_LEN) - 1) << PDS_CR_PDS_RC32M_OFF_DIS_POS) +#define PDS_CR_PDS_RC32M_OFF_DIS_UMSK (~(((1U << PDS_CR_PDS_RC32M_OFF_DIS_LEN) - 1) << PDS_CR_PDS_RC32M_OFF_DIS_POS)) +#define PDS_CR_PDS_LDO_VSEL_EN PDS_CR_PDS_LDO_VSEL_EN +#define PDS_CR_PDS_LDO_VSEL_EN_POS (18U) +#define PDS_CR_PDS_LDO_VSEL_EN_LEN (1U) +#define PDS_CR_PDS_LDO_VSEL_EN_MSK (((1U << PDS_CR_PDS_LDO_VSEL_EN_LEN) - 1) << PDS_CR_PDS_LDO_VSEL_EN_POS) +#define PDS_CR_PDS_LDO_VSEL_EN_UMSK (~(((1U << PDS_CR_PDS_LDO_VSEL_EN_LEN) - 1) << PDS_CR_PDS_LDO_VSEL_EN_POS)) +#define PDS_CR_NP_WFI_MASK PDS_CR_NP_WFI_MASK +#define PDS_CR_NP_WFI_MASK_POS (21U) +#define PDS_CR_NP_WFI_MASK_LEN (1U) +#define PDS_CR_NP_WFI_MASK_MSK (((1U << PDS_CR_NP_WFI_MASK_LEN) - 1) << PDS_CR_NP_WFI_MASK_POS) +#define PDS_CR_NP_WFI_MASK_UMSK (~(((1U << PDS_CR_NP_WFI_MASK_LEN) - 1) << PDS_CR_NP_WFI_MASK_POS)) +#define PDS_CR_PDS_PD_LDO11 PDS_CR_PDS_PD_LDO11 +#define PDS_CR_PDS_PD_LDO11_POS (22U) +#define PDS_CR_PDS_PD_LDO11_LEN (1U) +#define PDS_CR_PDS_PD_LDO11_MSK (((1U << PDS_CR_PDS_PD_LDO11_LEN) - 1) << PDS_CR_PDS_PD_LDO11_POS) +#define PDS_CR_PDS_PD_LDO11_UMSK (~(((1U << PDS_CR_PDS_PD_LDO11_LEN) - 1) << PDS_CR_PDS_PD_LDO11_POS)) +#define PDS_CR_PDS_LDO_VOL PDS_CR_PDS_LDO_VOL +#define PDS_CR_PDS_LDO_VOL_POS (24U) +#define PDS_CR_PDS_LDO_VOL_LEN (4U) +#define PDS_CR_PDS_LDO_VOL_MSK (((1U << PDS_CR_PDS_LDO_VOL_LEN) - 1) << PDS_CR_PDS_LDO_VOL_POS) +#define PDS_CR_PDS_LDO_VOL_UMSK (~(((1U << PDS_CR_PDS_LDO_VOL_LEN) - 1) << PDS_CR_PDS_LDO_VOL_POS)) +#define PDS_CR_PDS_CTRL_RF PDS_CR_PDS_CTRL_RF +#define PDS_CR_PDS_CTRL_RF_POS (28U) +#define PDS_CR_PDS_CTRL_RF_LEN (2U) +#define PDS_CR_PDS_CTRL_RF_MSK (((1U << PDS_CR_PDS_CTRL_RF_LEN) - 1) << PDS_CR_PDS_CTRL_RF_POS) +#define PDS_CR_PDS_CTRL_RF_UMSK (~(((1U << PDS_CR_PDS_CTRL_RF_LEN) - 1) << PDS_CR_PDS_CTRL_RF_POS)) +#define PDS_CR_PDS_CTRL_PLL PDS_CR_PDS_CTRL_PLL +#define PDS_CR_PDS_CTRL_PLL_POS (30U) +#define PDS_CR_PDS_CTRL_PLL_LEN (2U) +#define PDS_CR_PDS_CTRL_PLL_MSK (((1U << PDS_CR_PDS_CTRL_PLL_LEN) - 1) << PDS_CR_PDS_CTRL_PLL_POS) +#define PDS_CR_PDS_CTRL_PLL_UMSK (~(((1U << PDS_CR_PDS_CTRL_PLL_LEN) - 1) << PDS_CR_PDS_CTRL_PLL_POS)) + +/* 0x4 : PDS_TIME1 */ +#define PDS_TIME1_OFFSET (0x4) +#define PDS_CR_SLEEP_DURATION PDS_CR_SLEEP_DURATION +#define PDS_CR_SLEEP_DURATION_POS (0U) +#define PDS_CR_SLEEP_DURATION_LEN (32U) +#define PDS_CR_SLEEP_DURATION_MSK (((1U << PDS_CR_SLEEP_DURATION_LEN) - 1) << PDS_CR_SLEEP_DURATION_POS) +#define PDS_CR_SLEEP_DURATION_UMSK (~(((1U << PDS_CR_SLEEP_DURATION_LEN) - 1) << PDS_CR_SLEEP_DURATION_POS)) + +/* 0xC : PDS_INT */ +#define PDS_INT_OFFSET (0xC) +#define PDS_RO_PDS_WAKE_INT PDS_RO_PDS_WAKE_INT +#define PDS_RO_PDS_WAKE_INT_POS (0U) +#define PDS_RO_PDS_WAKE_INT_LEN (1U) +#define PDS_RO_PDS_WAKE_INT_MSK (((1U << PDS_RO_PDS_WAKE_INT_LEN) - 1) << PDS_RO_PDS_WAKE_INT_POS) +#define PDS_RO_PDS_WAKE_INT_UMSK (~(((1U << PDS_RO_PDS_WAKE_INT_LEN) - 1) << PDS_RO_PDS_WAKE_INT_POS)) +#define PDS_RO_PDS_IRQ_IN PDS_RO_PDS_IRQ_IN +#define PDS_RO_PDS_IRQ_IN_POS (1U) +#define PDS_RO_PDS_IRQ_IN_LEN (1U) +#define PDS_RO_PDS_IRQ_IN_MSK (((1U << PDS_RO_PDS_IRQ_IN_LEN) - 1) << PDS_RO_PDS_IRQ_IN_POS) +#define PDS_RO_PDS_IRQ_IN_UMSK (~(((1U << PDS_RO_PDS_IRQ_IN_LEN) - 1) << PDS_RO_PDS_IRQ_IN_POS)) +#define PDS_RO_PDS_RF_DONE_INT PDS_RO_PDS_RF_DONE_INT +#define PDS_RO_PDS_RF_DONE_INT_POS (2U) +#define PDS_RO_PDS_RF_DONE_INT_LEN (1U) +#define PDS_RO_PDS_RF_DONE_INT_MSK (((1U << PDS_RO_PDS_RF_DONE_INT_LEN) - 1) << PDS_RO_PDS_RF_DONE_INT_POS) +#define PDS_RO_PDS_RF_DONE_INT_UMSK (~(((1U << PDS_RO_PDS_RF_DONE_INT_LEN) - 1) << PDS_RO_PDS_RF_DONE_INT_POS)) +#define PDS_RO_PDS_PLL_DONE_INT PDS_RO_PDS_PLL_DONE_INT +#define PDS_RO_PDS_PLL_DONE_INT_POS (3U) +#define PDS_RO_PDS_PLL_DONE_INT_LEN (1U) +#define PDS_RO_PDS_PLL_DONE_INT_MSK (((1U << PDS_RO_PDS_PLL_DONE_INT_LEN) - 1) << PDS_RO_PDS_PLL_DONE_INT_POS) +#define PDS_RO_PDS_PLL_DONE_INT_UMSK (~(((1U << PDS_RO_PDS_PLL_DONE_INT_LEN) - 1) << PDS_RO_PDS_PLL_DONE_INT_POS)) +#define PDS_CR_PDS_WAKE_INT_MASK PDS_CR_PDS_WAKE_INT_MASK +#define PDS_CR_PDS_WAKE_INT_MASK_POS (8U) +#define PDS_CR_PDS_WAKE_INT_MASK_LEN (1U) +#define PDS_CR_PDS_WAKE_INT_MASK_MSK (((1U << PDS_CR_PDS_WAKE_INT_MASK_LEN) - 1) << PDS_CR_PDS_WAKE_INT_MASK_POS) +#define PDS_CR_PDS_WAKE_INT_MASK_UMSK (~(((1U << PDS_CR_PDS_WAKE_INT_MASK_LEN) - 1) << PDS_CR_PDS_WAKE_INT_MASK_POS)) +#define PDS_CR_PDS_IRQ_IN_DIS PDS_CR_PDS_IRQ_IN_DIS +#define PDS_CR_PDS_IRQ_IN_DIS_POS (9U) +#define PDS_CR_PDS_IRQ_IN_DIS_LEN (1U) +#define PDS_CR_PDS_IRQ_IN_DIS_MSK (((1U << PDS_CR_PDS_IRQ_IN_DIS_LEN) - 1) << PDS_CR_PDS_IRQ_IN_DIS_POS) +#define PDS_CR_PDS_IRQ_IN_DIS_UMSK (~(((1U << PDS_CR_PDS_IRQ_IN_DIS_LEN) - 1) << PDS_CR_PDS_IRQ_IN_DIS_POS)) +#define PDS_CR_PDS_RF_DONE_INT_MASK PDS_CR_PDS_RF_DONE_INT_MASK +#define PDS_CR_PDS_RF_DONE_INT_MASK_POS (10U) +#define PDS_CR_PDS_RF_DONE_INT_MASK_LEN (1U) +#define PDS_CR_PDS_RF_DONE_INT_MASK_MSK (((1U << PDS_CR_PDS_RF_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_RF_DONE_INT_MASK_POS) +#define PDS_CR_PDS_RF_DONE_INT_MASK_UMSK (~(((1U << PDS_CR_PDS_RF_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_RF_DONE_INT_MASK_POS)) +#define PDS_CR_PDS_PLL_DONE_INT_MASK PDS_CR_PDS_PLL_DONE_INT_MASK +#define PDS_CR_PDS_PLL_DONE_INT_MASK_POS (11U) +#define PDS_CR_PDS_PLL_DONE_INT_MASK_LEN (1U) +#define PDS_CR_PDS_PLL_DONE_INT_MASK_MSK (((1U << PDS_CR_PDS_PLL_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_PLL_DONE_INT_MASK_POS) +#define PDS_CR_PDS_PLL_DONE_INT_MASK_UMSK (~(((1U << PDS_CR_PDS_PLL_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_PLL_DONE_INT_MASK_POS)) +#define PDS_CR_PDS_INT_CLR PDS_CR_PDS_INT_CLR +#define PDS_CR_PDS_INT_CLR_POS (16U) +#define PDS_CR_PDS_INT_CLR_LEN (1U) +#define PDS_CR_PDS_INT_CLR_MSK (((1U << PDS_CR_PDS_INT_CLR_LEN) - 1) << PDS_CR_PDS_INT_CLR_POS) +#define PDS_CR_PDS_INT_CLR_UMSK (~(((1U << PDS_CR_PDS_INT_CLR_LEN) - 1) << PDS_CR_PDS_INT_CLR_POS)) + +/* 0x10 : PDS_CTL2 */ +#define PDS_CTL2_OFFSET (0x10) +#define PDS_CR_PDS_FORCE_NP_PWR_OFF PDS_CR_PDS_FORCE_NP_PWR_OFF +#define PDS_CR_PDS_FORCE_NP_PWR_OFF_POS (0U) +#define PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_FORCE_NP_PWR_OFF_MSK (((1U << PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PWR_OFF_POS) +#define PDS_CR_PDS_FORCE_NP_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PWR_OFF_POS)) +#define PDS_CR_PDS_FORCE_WB_PWR_OFF PDS_CR_PDS_FORCE_WB_PWR_OFF +#define PDS_CR_PDS_FORCE_WB_PWR_OFF_POS (2U) +#define PDS_CR_PDS_FORCE_WB_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_FORCE_WB_PWR_OFF_MSK (((1U << PDS_CR_PDS_FORCE_WB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_WB_PWR_OFF_POS) +#define PDS_CR_PDS_FORCE_WB_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_FORCE_WB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_WB_PWR_OFF_POS)) +#define PDS_CR_PDS_FORCE_NP_ISO_EN PDS_CR_PDS_FORCE_NP_ISO_EN +#define PDS_CR_PDS_FORCE_NP_ISO_EN_POS (4U) +#define PDS_CR_PDS_FORCE_NP_ISO_EN_LEN (1U) +#define PDS_CR_PDS_FORCE_NP_ISO_EN_MSK (((1U << PDS_CR_PDS_FORCE_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_NP_ISO_EN_POS) +#define PDS_CR_PDS_FORCE_NP_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_NP_ISO_EN_POS)) +#define PDS_CR_PDS_FORCE_WB_ISO_EN PDS_CR_PDS_FORCE_WB_ISO_EN +#define PDS_CR_PDS_FORCE_WB_ISO_EN_POS (6U) +#define PDS_CR_PDS_FORCE_WB_ISO_EN_LEN (1U) +#define PDS_CR_PDS_FORCE_WB_ISO_EN_MSK (((1U << PDS_CR_PDS_FORCE_WB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_WB_ISO_EN_POS) +#define PDS_CR_PDS_FORCE_WB_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_FORCE_WB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_WB_ISO_EN_POS)) +#define PDS_CR_PDS_FORCE_NP_PDS_RST PDS_CR_PDS_FORCE_NP_PDS_RST +#define PDS_CR_PDS_FORCE_NP_PDS_RST_POS (8U) +#define PDS_CR_PDS_FORCE_NP_PDS_RST_LEN (1U) +#define PDS_CR_PDS_FORCE_NP_PDS_RST_MSK (((1U << PDS_CR_PDS_FORCE_NP_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PDS_RST_POS) +#define PDS_CR_PDS_FORCE_NP_PDS_RST_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PDS_RST_POS)) +#define PDS_CR_PDS_FORCE_WB_PDS_RST PDS_CR_PDS_FORCE_WB_PDS_RST +#define PDS_CR_PDS_FORCE_WB_PDS_RST_POS (10U) +#define PDS_CR_PDS_FORCE_WB_PDS_RST_LEN (1U) +#define PDS_CR_PDS_FORCE_WB_PDS_RST_MSK (((1U << PDS_CR_PDS_FORCE_WB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_WB_PDS_RST_POS) +#define PDS_CR_PDS_FORCE_WB_PDS_RST_UMSK (~(((1U << PDS_CR_PDS_FORCE_WB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_WB_PDS_RST_POS)) +#define PDS_CR_PDS_FORCE_NP_MEM_STBY PDS_CR_PDS_FORCE_NP_MEM_STBY +#define PDS_CR_PDS_FORCE_NP_MEM_STBY_POS (12U) +#define PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_FORCE_NP_MEM_STBY_MSK (((1U << PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_NP_MEM_STBY_POS) +#define PDS_CR_PDS_FORCE_NP_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_NP_MEM_STBY_POS)) +#define PDS_CR_PDS_FORCE_WB_MEM_STBY PDS_CR_PDS_FORCE_WB_MEM_STBY +#define PDS_CR_PDS_FORCE_WB_MEM_STBY_POS (14U) +#define PDS_CR_PDS_FORCE_WB_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_FORCE_WB_MEM_STBY_MSK (((1U << PDS_CR_PDS_FORCE_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_WB_MEM_STBY_POS) +#define PDS_CR_PDS_FORCE_WB_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_WB_MEM_STBY_POS)) +#define PDS_CR_PDS_FORCE_NP_GATE_CLK PDS_CR_PDS_FORCE_NP_GATE_CLK +#define PDS_CR_PDS_FORCE_NP_GATE_CLK_POS (16U) +#define PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_FORCE_NP_GATE_CLK_MSK (((1U << PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_NP_GATE_CLK_POS) +#define PDS_CR_PDS_FORCE_NP_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_NP_GATE_CLK_POS)) +#define PDS_CR_PDS_FORCE_WB_GATE_CLK PDS_CR_PDS_FORCE_WB_GATE_CLK +#define PDS_CR_PDS_FORCE_WB_GATE_CLK_POS (18U) +#define PDS_CR_PDS_FORCE_WB_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_FORCE_WB_GATE_CLK_MSK (((1U << PDS_CR_PDS_FORCE_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_WB_GATE_CLK_POS) +#define PDS_CR_PDS_FORCE_WB_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_WB_GATE_CLK_POS)) + +/* 0x14 : PDS_CTL3 */ +#define PDS_CTL3_OFFSET (0x14) +#define PDS_CR_PDS_FORCE_MISC_PWR_OFF PDS_CR_PDS_FORCE_MISC_PWR_OFF +#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS (1U) +#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_MSK (((1U << PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS) +#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS)) +#define PDS_CR_PDS_FORCE_MISC_ISO_EN PDS_CR_PDS_FORCE_MISC_ISO_EN +#define PDS_CR_PDS_FORCE_MISC_ISO_EN_POS (4U) +#define PDS_CR_PDS_FORCE_MISC_ISO_EN_LEN (1U) +#define PDS_CR_PDS_FORCE_MISC_ISO_EN_MSK (((1U << PDS_CR_PDS_FORCE_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_ISO_EN_POS) +#define PDS_CR_PDS_FORCE_MISC_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_ISO_EN_POS)) +#define PDS_CR_PDS_FORCE_MISC_PDS_RST PDS_CR_PDS_FORCE_MISC_PDS_RST +#define PDS_CR_PDS_FORCE_MISC_PDS_RST_POS (7U) +#define PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN (1U) +#define PDS_CR_PDS_FORCE_MISC_PDS_RST_MSK (((1U << PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PDS_RST_POS) +#define PDS_CR_PDS_FORCE_MISC_PDS_RST_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PDS_RST_POS)) +#define PDS_CR_PDS_FORCE_MISC_MEM_STBY PDS_CR_PDS_FORCE_MISC_MEM_STBY +#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS (10U) +#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_MSK (((1U << PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS) +#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS)) +#define PDS_CR_PDS_FORCE_MISC_GATE_CLK PDS_CR_PDS_FORCE_MISC_GATE_CLK +#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS (13U) +#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_MSK (((1U << PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS) +#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS)) +#define PDS_CR_PDS_NP_ISO_EN PDS_CR_PDS_NP_ISO_EN +#define PDS_CR_PDS_NP_ISO_EN_POS (24U) +#define PDS_CR_PDS_NP_ISO_EN_LEN (1U) +#define PDS_CR_PDS_NP_ISO_EN_MSK (((1U << PDS_CR_PDS_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_NP_ISO_EN_POS) +#define PDS_CR_PDS_NP_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_NP_ISO_EN_POS)) +#define PDS_CR_PDS_WB_ISO_EN PDS_CR_PDS_WB_ISO_EN +#define PDS_CR_PDS_WB_ISO_EN_POS (27U) +#define PDS_CR_PDS_WB_ISO_EN_LEN (1U) +#define PDS_CR_PDS_WB_ISO_EN_MSK (((1U << PDS_CR_PDS_WB_ISO_EN_LEN) - 1) << PDS_CR_PDS_WB_ISO_EN_POS) +#define PDS_CR_PDS_WB_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_WB_ISO_EN_LEN) - 1) << PDS_CR_PDS_WB_ISO_EN_POS)) +#define PDS_CR_PDS_MISC_ISO_EN PDS_CR_PDS_MISC_ISO_EN +#define PDS_CR_PDS_MISC_ISO_EN_POS (30U) +#define PDS_CR_PDS_MISC_ISO_EN_LEN (1U) +#define PDS_CR_PDS_MISC_ISO_EN_MSK (((1U << PDS_CR_PDS_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_MISC_ISO_EN_POS) +#define PDS_CR_PDS_MISC_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_MISC_ISO_EN_POS)) + +/* 0x18 : PDS_CTL4 */ +#define PDS_CTL4_OFFSET (0x18) +#define PDS_CR_PDS_NP_PWR_OFF PDS_CR_PDS_NP_PWR_OFF +#define PDS_CR_PDS_NP_PWR_OFF_POS (0U) +#define PDS_CR_PDS_NP_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_NP_PWR_OFF_MSK (((1U << PDS_CR_PDS_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_NP_PWR_OFF_POS) +#define PDS_CR_PDS_NP_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_NP_PWR_OFF_POS)) +#define PDS_CR_PDS_NP_RESET PDS_CR_PDS_NP_RESET +#define PDS_CR_PDS_NP_RESET_POS (1U) +#define PDS_CR_PDS_NP_RESET_LEN (1U) +#define PDS_CR_PDS_NP_RESET_MSK (((1U << PDS_CR_PDS_NP_RESET_LEN) - 1) << PDS_CR_PDS_NP_RESET_POS) +#define PDS_CR_PDS_NP_RESET_UMSK (~(((1U << PDS_CR_PDS_NP_RESET_LEN) - 1) << PDS_CR_PDS_NP_RESET_POS)) +#define PDS_CR_PDS_NP_MEM_STBY PDS_CR_PDS_NP_MEM_STBY +#define PDS_CR_PDS_NP_MEM_STBY_POS (2U) +#define PDS_CR_PDS_NP_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_NP_MEM_STBY_MSK (((1U << PDS_CR_PDS_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_NP_MEM_STBY_POS) +#define PDS_CR_PDS_NP_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_NP_MEM_STBY_POS)) +#define PDS_CR_PDS_NP_GATE_CLK PDS_CR_PDS_NP_GATE_CLK +#define PDS_CR_PDS_NP_GATE_CLK_POS (3U) +#define PDS_CR_PDS_NP_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_NP_GATE_CLK_MSK (((1U << PDS_CR_PDS_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_NP_GATE_CLK_POS) +#define PDS_CR_PDS_NP_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_NP_GATE_CLK_POS)) +#define PDS_CR_PDS_WB_PWR_OFF PDS_CR_PDS_WB_PWR_OFF +#define PDS_CR_PDS_WB_PWR_OFF_POS (12U) +#define PDS_CR_PDS_WB_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_WB_PWR_OFF_MSK (((1U << PDS_CR_PDS_WB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_WB_PWR_OFF_POS) +#define PDS_CR_PDS_WB_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_WB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_WB_PWR_OFF_POS)) +#define PDS_CR_PDS_WB_RESET PDS_CR_PDS_WB_RESET +#define PDS_CR_PDS_WB_RESET_POS (13U) +#define PDS_CR_PDS_WB_RESET_LEN (1U) +#define PDS_CR_PDS_WB_RESET_MSK (((1U << PDS_CR_PDS_WB_RESET_LEN) - 1) << PDS_CR_PDS_WB_RESET_POS) +#define PDS_CR_PDS_WB_RESET_UMSK (~(((1U << PDS_CR_PDS_WB_RESET_LEN) - 1) << PDS_CR_PDS_WB_RESET_POS)) +#define PDS_CR_PDS_WB_MEM_STBY PDS_CR_PDS_WB_MEM_STBY +#define PDS_CR_PDS_WB_MEM_STBY_POS (14U) +#define PDS_CR_PDS_WB_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_WB_MEM_STBY_MSK (((1U << PDS_CR_PDS_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_WB_MEM_STBY_POS) +#define PDS_CR_PDS_WB_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_WB_MEM_STBY_POS)) +#define PDS_CR_PDS_WB_GATE_CLK PDS_CR_PDS_WB_GATE_CLK +#define PDS_CR_PDS_WB_GATE_CLK_POS (15U) +#define PDS_CR_PDS_WB_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_WB_GATE_CLK_MSK (((1U << PDS_CR_PDS_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_WB_GATE_CLK_POS) +#define PDS_CR_PDS_WB_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_WB_GATE_CLK_POS)) +#define PDS_CR_PDS_MISC_PWR_OFF PDS_CR_PDS_MISC_PWR_OFF +#define PDS_CR_PDS_MISC_PWR_OFF_POS (24U) +#define PDS_CR_PDS_MISC_PWR_OFF_LEN (1U) +#define PDS_CR_PDS_MISC_PWR_OFF_MSK (((1U << PDS_CR_PDS_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_PWR_OFF_POS) +#define PDS_CR_PDS_MISC_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_PWR_OFF_POS)) +#define PDS_CR_PDS_MISC_RESET PDS_CR_PDS_MISC_RESET +#define PDS_CR_PDS_MISC_RESET_POS (25U) +#define PDS_CR_PDS_MISC_RESET_LEN (1U) +#define PDS_CR_PDS_MISC_RESET_MSK (((1U << PDS_CR_PDS_MISC_RESET_LEN) - 1) << PDS_CR_PDS_MISC_RESET_POS) +#define PDS_CR_PDS_MISC_RESET_UMSK (~(((1U << PDS_CR_PDS_MISC_RESET_LEN) - 1) << PDS_CR_PDS_MISC_RESET_POS)) +#define PDS_CR_PDS_MISC_MEM_STBY PDS_CR_PDS_MISC_MEM_STBY +#define PDS_CR_PDS_MISC_MEM_STBY_POS (26U) +#define PDS_CR_PDS_MISC_MEM_STBY_LEN (1U) +#define PDS_CR_PDS_MISC_MEM_STBY_MSK (((1U << PDS_CR_PDS_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MISC_MEM_STBY_POS) +#define PDS_CR_PDS_MISC_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MISC_MEM_STBY_POS)) +#define PDS_CR_PDS_MISC_GATE_CLK PDS_CR_PDS_MISC_GATE_CLK +#define PDS_CR_PDS_MISC_GATE_CLK_POS (27U) +#define PDS_CR_PDS_MISC_GATE_CLK_LEN (1U) +#define PDS_CR_PDS_MISC_GATE_CLK_MSK (((1U << PDS_CR_PDS_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MISC_GATE_CLK_POS) +#define PDS_CR_PDS_MISC_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MISC_GATE_CLK_POS)) + +/* 0x1C : pds_stat */ +#define PDS_STAT_OFFSET (0x1C) +#define PDS_RO_PDS_STATE PDS_RO_PDS_STATE +#define PDS_RO_PDS_STATE_POS (0U) +#define PDS_RO_PDS_STATE_LEN (4U) +#define PDS_RO_PDS_STATE_MSK (((1U << PDS_RO_PDS_STATE_LEN) - 1) << PDS_RO_PDS_STATE_POS) +#define PDS_RO_PDS_STATE_UMSK (~(((1U << PDS_RO_PDS_STATE_LEN) - 1) << PDS_RO_PDS_STATE_POS)) +#define PDS_RO_PDS_RF_STATE PDS_RO_PDS_RF_STATE +#define PDS_RO_PDS_RF_STATE_POS (8U) +#define PDS_RO_PDS_RF_STATE_LEN (4U) +#define PDS_RO_PDS_RF_STATE_MSK (((1U << PDS_RO_PDS_RF_STATE_LEN) - 1) << PDS_RO_PDS_RF_STATE_POS) +#define PDS_RO_PDS_RF_STATE_UMSK (~(((1U << PDS_RO_PDS_RF_STATE_LEN) - 1) << PDS_RO_PDS_RF_STATE_POS)) +#define PDS_RO_PDS_PLL_STATE PDS_RO_PDS_PLL_STATE +#define PDS_RO_PDS_PLL_STATE_POS (16U) +#define PDS_RO_PDS_PLL_STATE_LEN (2U) +#define PDS_RO_PDS_PLL_STATE_MSK (((1U << PDS_RO_PDS_PLL_STATE_LEN) - 1) << PDS_RO_PDS_PLL_STATE_POS) +#define PDS_RO_PDS_PLL_STATE_UMSK (~(((1U << PDS_RO_PDS_PLL_STATE_LEN) - 1) << PDS_RO_PDS_PLL_STATE_POS)) + +/* 0x20 : pds_ram1 */ +#define PDS_RAM1_OFFSET (0x20) +#define PDS_CR_NP_SRAM_PWR PDS_CR_NP_SRAM_PWR +#define PDS_CR_NP_SRAM_PWR_POS (0U) +#define PDS_CR_NP_SRAM_PWR_LEN (8U) +#define PDS_CR_NP_SRAM_PWR_MSK (((1U << PDS_CR_NP_SRAM_PWR_LEN) - 1) << PDS_CR_NP_SRAM_PWR_POS) +#define PDS_CR_NP_SRAM_PWR_UMSK (~(((1U << PDS_CR_NP_SRAM_PWR_LEN) - 1) << PDS_CR_NP_SRAM_PWR_POS)) + +/* 0x300 : rc32m_ctrl0 */ +#define PDS_RC32M_CTRL0_OFFSET (0x300) +#define PDS_RC32M_CAL_DONE PDS_RC32M_CAL_DONE +#define PDS_RC32M_CAL_DONE_POS (0U) +#define PDS_RC32M_CAL_DONE_LEN (1U) +#define PDS_RC32M_CAL_DONE_MSK (((1U << PDS_RC32M_CAL_DONE_LEN) - 1) << PDS_RC32M_CAL_DONE_POS) +#define PDS_RC32M_CAL_DONE_UMSK (~(((1U << PDS_RC32M_CAL_DONE_LEN) - 1) << PDS_RC32M_CAL_DONE_POS)) +#define PDS_RC32M_RDY PDS_RC32M_RDY +#define PDS_RC32M_RDY_POS (1U) +#define PDS_RC32M_RDY_LEN (1U) +#define PDS_RC32M_RDY_MSK (((1U << PDS_RC32M_RDY_LEN) - 1) << PDS_RC32M_RDY_POS) +#define PDS_RC32M_RDY_UMSK (~(((1U << PDS_RC32M_RDY_LEN) - 1) << PDS_RC32M_RDY_POS)) +#define PDS_RC32M_CAL_INPROGRESS PDS_RC32M_CAL_INPROGRESS +#define PDS_RC32M_CAL_INPROGRESS_POS (2U) +#define PDS_RC32M_CAL_INPROGRESS_LEN (1U) +#define PDS_RC32M_CAL_INPROGRESS_MSK (((1U << PDS_RC32M_CAL_INPROGRESS_LEN) - 1) << PDS_RC32M_CAL_INPROGRESS_POS) +#define PDS_RC32M_CAL_INPROGRESS_UMSK (~(((1U << PDS_RC32M_CAL_INPROGRESS_LEN) - 1) << PDS_RC32M_CAL_INPROGRESS_POS)) +#define PDS_RC32M_CAL_DIV PDS_RC32M_CAL_DIV +#define PDS_RC32M_CAL_DIV_POS (3U) +#define PDS_RC32M_CAL_DIV_LEN (2U) +#define PDS_RC32M_CAL_DIV_MSK (((1U << PDS_RC32M_CAL_DIV_LEN) - 1) << PDS_RC32M_CAL_DIV_POS) +#define PDS_RC32M_CAL_DIV_UMSK (~(((1U << PDS_RC32M_CAL_DIV_LEN) - 1) << PDS_RC32M_CAL_DIV_POS)) +#define PDS_RC32M_CAL_PRECHARGE PDS_RC32M_CAL_PRECHARGE +#define PDS_RC32M_CAL_PRECHARGE_POS (5U) +#define PDS_RC32M_CAL_PRECHARGE_LEN (1U) +#define PDS_RC32M_CAL_PRECHARGE_MSK (((1U << PDS_RC32M_CAL_PRECHARGE_LEN) - 1) << PDS_RC32M_CAL_PRECHARGE_POS) +#define PDS_RC32M_CAL_PRECHARGE_UMSK (~(((1U << PDS_RC32M_CAL_PRECHARGE_LEN) - 1) << PDS_RC32M_CAL_PRECHARGE_POS)) +#define PDS_RC32M_DIG_CODE_FR_CAL PDS_RC32M_DIG_CODE_FR_CAL +#define PDS_RC32M_DIG_CODE_FR_CAL_POS (6U) +#define PDS_RC32M_DIG_CODE_FR_CAL_LEN (8U) +#define PDS_RC32M_DIG_CODE_FR_CAL_MSK (((1U << PDS_RC32M_DIG_CODE_FR_CAL_LEN) - 1) << PDS_RC32M_DIG_CODE_FR_CAL_POS) +#define PDS_RC32M_DIG_CODE_FR_CAL_UMSK (~(((1U << PDS_RC32M_DIG_CODE_FR_CAL_LEN) - 1) << PDS_RC32M_DIG_CODE_FR_CAL_POS)) +#define PDS_RC32M_ALLOW_CAL PDS_RC32M_ALLOW_CAL +#define PDS_RC32M_ALLOW_CAL_POS (17U) +#define PDS_RC32M_ALLOW_CAL_LEN (1U) +#define PDS_RC32M_ALLOW_CAL_MSK (((1U << PDS_RC32M_ALLOW_CAL_LEN) - 1) << PDS_RC32M_ALLOW_CAL_POS) +#define PDS_RC32M_ALLOW_CAL_UMSK (~(((1U << PDS_RC32M_ALLOW_CAL_LEN) - 1) << PDS_RC32M_ALLOW_CAL_POS)) +#define PDS_RC32M_REFCLK_HALF PDS_RC32M_REFCLK_HALF +#define PDS_RC32M_REFCLK_HALF_POS (18U) +#define PDS_RC32M_REFCLK_HALF_LEN (1U) +#define PDS_RC32M_REFCLK_HALF_MSK (((1U << PDS_RC32M_REFCLK_HALF_LEN) - 1) << PDS_RC32M_REFCLK_HALF_POS) +#define PDS_RC32M_REFCLK_HALF_UMSK (~(((1U << PDS_RC32M_REFCLK_HALF_LEN) - 1) << PDS_RC32M_REFCLK_HALF_POS)) +#define PDS_RC32M_EXT_CODE_EN PDS_RC32M_EXT_CODE_EN +#define PDS_RC32M_EXT_CODE_EN_POS (19U) +#define PDS_RC32M_EXT_CODE_EN_LEN (1U) +#define PDS_RC32M_EXT_CODE_EN_MSK (((1U << PDS_RC32M_EXT_CODE_EN_LEN) - 1) << PDS_RC32M_EXT_CODE_EN_POS) +#define PDS_RC32M_EXT_CODE_EN_UMSK (~(((1U << PDS_RC32M_EXT_CODE_EN_LEN) - 1) << PDS_RC32M_EXT_CODE_EN_POS)) +#define PDS_RC32M_CAL_EN PDS_RC32M_CAL_EN +#define PDS_RC32M_CAL_EN_POS (20U) +#define PDS_RC32M_CAL_EN_LEN (1U) +#define PDS_RC32M_CAL_EN_MSK (((1U << PDS_RC32M_CAL_EN_LEN) - 1) << PDS_RC32M_CAL_EN_POS) +#define PDS_RC32M_CAL_EN_UMSK (~(((1U << PDS_RC32M_CAL_EN_LEN) - 1) << PDS_RC32M_CAL_EN_POS)) +#define PDS_RC32M_PD PDS_RC32M_PD +#define PDS_RC32M_PD_POS (21U) +#define PDS_RC32M_PD_LEN (1U) +#define PDS_RC32M_PD_MSK (((1U << PDS_RC32M_PD_LEN) - 1) << PDS_RC32M_PD_POS) +#define PDS_RC32M_PD_UMSK (~(((1U << PDS_RC32M_PD_LEN) - 1) << PDS_RC32M_PD_POS)) +#define PDS_RC32M_CODE_FR_EXT PDS_RC32M_CODE_FR_EXT +#define PDS_RC32M_CODE_FR_EXT_POS (22U) +#define PDS_RC32M_CODE_FR_EXT_LEN (8U) +#define PDS_RC32M_CODE_FR_EXT_MSK (((1U << PDS_RC32M_CODE_FR_EXT_LEN) - 1) << PDS_RC32M_CODE_FR_EXT_POS) +#define PDS_RC32M_CODE_FR_EXT_UMSK (~(((1U << PDS_RC32M_CODE_FR_EXT_LEN) - 1) << PDS_RC32M_CODE_FR_EXT_POS)) + +/* 0x304 : rc32m_ctrl1 */ +#define PDS_RC32M_CTRL1_OFFSET (0x304) +#define PDS_RC32M_TEST_EN PDS_RC32M_TEST_EN +#define PDS_RC32M_TEST_EN_POS (0U) +#define PDS_RC32M_TEST_EN_LEN (1U) +#define PDS_RC32M_TEST_EN_MSK (((1U << PDS_RC32M_TEST_EN_LEN) - 1) << PDS_RC32M_TEST_EN_POS) +#define PDS_RC32M_TEST_EN_UMSK (~(((1U << PDS_RC32M_TEST_EN_LEN) - 1) << PDS_RC32M_TEST_EN_POS)) +#define PDS_RC32M_SOFT_RST PDS_RC32M_SOFT_RST +#define PDS_RC32M_SOFT_RST_POS (1U) +#define PDS_RC32M_SOFT_RST_LEN (1U) +#define PDS_RC32M_SOFT_RST_MSK (((1U << PDS_RC32M_SOFT_RST_LEN) - 1) << PDS_RC32M_SOFT_RST_POS) +#define PDS_RC32M_SOFT_RST_UMSK (~(((1U << PDS_RC32M_SOFT_RST_LEN) - 1) << PDS_RC32M_SOFT_RST_POS)) +#define PDS_RC32M_CLK_SOFT_RST PDS_RC32M_CLK_SOFT_RST +#define PDS_RC32M_CLK_SOFT_RST_POS (2U) +#define PDS_RC32M_CLK_SOFT_RST_LEN (1U) +#define PDS_RC32M_CLK_SOFT_RST_MSK (((1U << PDS_RC32M_CLK_SOFT_RST_LEN) - 1) << PDS_RC32M_CLK_SOFT_RST_POS) +#define PDS_RC32M_CLK_SOFT_RST_UMSK (~(((1U << PDS_RC32M_CLK_SOFT_RST_LEN) - 1) << PDS_RC32M_CLK_SOFT_RST_POS)) +#define PDS_RC32M_CLK_INV PDS_RC32M_CLK_INV +#define PDS_RC32M_CLK_INV_POS (3U) +#define PDS_RC32M_CLK_INV_LEN (1U) +#define PDS_RC32M_CLK_INV_MSK (((1U << PDS_RC32M_CLK_INV_LEN) - 1) << PDS_RC32M_CLK_INV_POS) +#define PDS_RC32M_CLK_INV_UMSK (~(((1U << PDS_RC32M_CLK_INV_LEN) - 1) << PDS_RC32M_CLK_INV_POS)) +#define PDS_RC32M_CLK_FORCE_ON PDS_RC32M_CLK_FORCE_ON +#define PDS_RC32M_CLK_FORCE_ON_POS (4U) +#define PDS_RC32M_CLK_FORCE_ON_LEN (1U) +#define PDS_RC32M_CLK_FORCE_ON_MSK (((1U << PDS_RC32M_CLK_FORCE_ON_LEN) - 1) << PDS_RC32M_CLK_FORCE_ON_POS) +#define PDS_RC32M_CLK_FORCE_ON_UMSK (~(((1U << PDS_RC32M_CLK_FORCE_ON_LEN) - 1) << PDS_RC32M_CLK_FORCE_ON_POS)) +#define PDS_RC32M_RESERVED PDS_RC32M_RESERVED +#define PDS_RC32M_RESERVED_POS (24U) +#define PDS_RC32M_RESERVED_LEN (8U) +#define PDS_RC32M_RESERVED_MSK (((1U << PDS_RC32M_RESERVED_LEN) - 1) << PDS_RC32M_RESERVED_POS) +#define PDS_RC32M_RESERVED_UMSK (~(((1U << PDS_RC32M_RESERVED_LEN) - 1) << PDS_RC32M_RESERVED_POS)) + +/* 0x400 : pu_rst_clkpll */ +#define PDS_PU_RST_CLKPLL_OFFSET (0x400) +#define PDS_CLKPLL_SDM_RESET PDS_CLKPLL_SDM_RESET +#define PDS_CLKPLL_SDM_RESET_POS (0U) +#define PDS_CLKPLL_SDM_RESET_LEN (1U) +#define PDS_CLKPLL_SDM_RESET_MSK (((1U << PDS_CLKPLL_SDM_RESET_LEN) - 1) << PDS_CLKPLL_SDM_RESET_POS) +#define PDS_CLKPLL_SDM_RESET_UMSK (~(((1U << PDS_CLKPLL_SDM_RESET_LEN) - 1) << PDS_CLKPLL_SDM_RESET_POS)) +#define PDS_CLKPLL_RESET_POSTDIV PDS_CLKPLL_RESET_POSTDIV +#define PDS_CLKPLL_RESET_POSTDIV_POS (1U) +#define PDS_CLKPLL_RESET_POSTDIV_LEN (1U) +#define PDS_CLKPLL_RESET_POSTDIV_MSK (((1U << PDS_CLKPLL_RESET_POSTDIV_LEN) - 1) << PDS_CLKPLL_RESET_POSTDIV_POS) +#define PDS_CLKPLL_RESET_POSTDIV_UMSK (~(((1U << PDS_CLKPLL_RESET_POSTDIV_LEN) - 1) << PDS_CLKPLL_RESET_POSTDIV_POS)) +#define PDS_CLKPLL_RESET_FBDV PDS_CLKPLL_RESET_FBDV +#define PDS_CLKPLL_RESET_FBDV_POS (2U) +#define PDS_CLKPLL_RESET_FBDV_LEN (1U) +#define PDS_CLKPLL_RESET_FBDV_MSK (((1U << PDS_CLKPLL_RESET_FBDV_LEN) - 1) << PDS_CLKPLL_RESET_FBDV_POS) +#define PDS_CLKPLL_RESET_FBDV_UMSK (~(((1U << PDS_CLKPLL_RESET_FBDV_LEN) - 1) << PDS_CLKPLL_RESET_FBDV_POS)) +#define PDS_CLKPLL_RESET_REFDIV PDS_CLKPLL_RESET_REFDIV +#define PDS_CLKPLL_RESET_REFDIV_POS (3U) +#define PDS_CLKPLL_RESET_REFDIV_LEN (1U) +#define PDS_CLKPLL_RESET_REFDIV_MSK (((1U << PDS_CLKPLL_RESET_REFDIV_LEN) - 1) << PDS_CLKPLL_RESET_REFDIV_POS) +#define PDS_CLKPLL_RESET_REFDIV_UMSK (~(((1U << PDS_CLKPLL_RESET_REFDIV_LEN) - 1) << PDS_CLKPLL_RESET_REFDIV_POS)) +#define PDS_CLKPLL_PU_POSTDIV PDS_CLKPLL_PU_POSTDIV +#define PDS_CLKPLL_PU_POSTDIV_POS (4U) +#define PDS_CLKPLL_PU_POSTDIV_LEN (1U) +#define PDS_CLKPLL_PU_POSTDIV_MSK (((1U << PDS_CLKPLL_PU_POSTDIV_LEN) - 1) << PDS_CLKPLL_PU_POSTDIV_POS) +#define PDS_CLKPLL_PU_POSTDIV_UMSK (~(((1U << PDS_CLKPLL_PU_POSTDIV_LEN) - 1) << PDS_CLKPLL_PU_POSTDIV_POS)) +#define PDS_CLKPLL_PU_FBDV PDS_CLKPLL_PU_FBDV +#define PDS_CLKPLL_PU_FBDV_POS (5U) +#define PDS_CLKPLL_PU_FBDV_LEN (1U) +#define PDS_CLKPLL_PU_FBDV_MSK (((1U << PDS_CLKPLL_PU_FBDV_LEN) - 1) << PDS_CLKPLL_PU_FBDV_POS) +#define PDS_CLKPLL_PU_FBDV_UMSK (~(((1U << PDS_CLKPLL_PU_FBDV_LEN) - 1) << PDS_CLKPLL_PU_FBDV_POS)) +#define PDS_CLKPLL_PU_CLAMP_OP PDS_CLKPLL_PU_CLAMP_OP +#define PDS_CLKPLL_PU_CLAMP_OP_POS (6U) +#define PDS_CLKPLL_PU_CLAMP_OP_LEN (1U) +#define PDS_CLKPLL_PU_CLAMP_OP_MSK (((1U << PDS_CLKPLL_PU_CLAMP_OP_LEN) - 1) << PDS_CLKPLL_PU_CLAMP_OP_POS) +#define PDS_CLKPLL_PU_CLAMP_OP_UMSK (~(((1U << PDS_CLKPLL_PU_CLAMP_OP_LEN) - 1) << PDS_CLKPLL_PU_CLAMP_OP_POS)) +#define PDS_CLKPLL_PU_PFD PDS_CLKPLL_PU_PFD +#define PDS_CLKPLL_PU_PFD_POS (7U) +#define PDS_CLKPLL_PU_PFD_LEN (1U) +#define PDS_CLKPLL_PU_PFD_MSK (((1U << PDS_CLKPLL_PU_PFD_LEN) - 1) << PDS_CLKPLL_PU_PFD_POS) +#define PDS_CLKPLL_PU_PFD_UMSK (~(((1U << PDS_CLKPLL_PU_PFD_LEN) - 1) << PDS_CLKPLL_PU_PFD_POS)) +#define PDS_CLKPLL_PU_CP PDS_CLKPLL_PU_CP +#define PDS_CLKPLL_PU_CP_POS (8U) +#define PDS_CLKPLL_PU_CP_LEN (1U) +#define PDS_CLKPLL_PU_CP_MSK (((1U << PDS_CLKPLL_PU_CP_LEN) - 1) << PDS_CLKPLL_PU_CP_POS) +#define PDS_CLKPLL_PU_CP_UMSK (~(((1U << PDS_CLKPLL_PU_CP_LEN) - 1) << PDS_CLKPLL_PU_CP_POS)) +#define PDS_PU_CLKPLL_SFREG PDS_PU_CLKPLL_SFREG +#define PDS_PU_CLKPLL_SFREG_POS (9U) +#define PDS_PU_CLKPLL_SFREG_LEN (1U) +#define PDS_PU_CLKPLL_SFREG_MSK (((1U << PDS_PU_CLKPLL_SFREG_LEN) - 1) << PDS_PU_CLKPLL_SFREG_POS) +#define PDS_PU_CLKPLL_SFREG_UMSK (~(((1U << PDS_PU_CLKPLL_SFREG_LEN) - 1) << PDS_PU_CLKPLL_SFREG_POS)) +#define PDS_PU_CLKPLL PDS_PU_CLKPLL +#define PDS_PU_CLKPLL_POS (10U) +#define PDS_PU_CLKPLL_LEN (1U) +#define PDS_PU_CLKPLL_MSK (((1U << PDS_PU_CLKPLL_LEN) - 1) << PDS_PU_CLKPLL_POS) +#define PDS_PU_CLKPLL_UMSK (~(((1U << PDS_PU_CLKPLL_LEN) - 1) << PDS_PU_CLKPLL_POS)) + +/* 0x404 : clkpll_top_ctrl */ +#define PDS_CLKPLL_TOP_CTRL_OFFSET (0x404) +#define PDS_CLKPLL_POSTDIV PDS_CLKPLL_POSTDIV +#define PDS_CLKPLL_POSTDIV_POS (0U) +#define PDS_CLKPLL_POSTDIV_LEN (7U) +#define PDS_CLKPLL_POSTDIV_MSK (((1U << PDS_CLKPLL_POSTDIV_LEN) - 1) << PDS_CLKPLL_POSTDIV_POS) +#define PDS_CLKPLL_POSTDIV_UMSK (~(((1U << PDS_CLKPLL_POSTDIV_LEN) - 1) << PDS_CLKPLL_POSTDIV_POS)) +#define PDS_CLKPLL_REFDIV_RATIO PDS_CLKPLL_REFDIV_RATIO +#define PDS_CLKPLL_REFDIV_RATIO_POS (8U) +#define PDS_CLKPLL_REFDIV_RATIO_LEN (4U) +#define PDS_CLKPLL_REFDIV_RATIO_MSK (((1U << PDS_CLKPLL_REFDIV_RATIO_LEN) - 1) << PDS_CLKPLL_REFDIV_RATIO_POS) +#define PDS_CLKPLL_REFDIV_RATIO_UMSK (~(((1U << PDS_CLKPLL_REFDIV_RATIO_LEN) - 1) << PDS_CLKPLL_REFDIV_RATIO_POS)) +#define PDS_CLKPLL_XTAL_RC32M_SEL PDS_CLKPLL_XTAL_RC32M_SEL +#define PDS_CLKPLL_XTAL_RC32M_SEL_POS (12U) +#define PDS_CLKPLL_XTAL_RC32M_SEL_LEN (1U) +#define PDS_CLKPLL_XTAL_RC32M_SEL_MSK (((1U << PDS_CLKPLL_XTAL_RC32M_SEL_LEN) - 1) << PDS_CLKPLL_XTAL_RC32M_SEL_POS) +#define PDS_CLKPLL_XTAL_RC32M_SEL_UMSK (~(((1U << PDS_CLKPLL_XTAL_RC32M_SEL_LEN) - 1) << PDS_CLKPLL_XTAL_RC32M_SEL_POS)) +#define PDS_CLKPLL_REFCLK_SEL PDS_CLKPLL_REFCLK_SEL +#define PDS_CLKPLL_REFCLK_SEL_POS (16U) +#define PDS_CLKPLL_REFCLK_SEL_LEN (1U) +#define PDS_CLKPLL_REFCLK_SEL_MSK (((1U << PDS_CLKPLL_REFCLK_SEL_LEN) - 1) << PDS_CLKPLL_REFCLK_SEL_POS) +#define PDS_CLKPLL_REFCLK_SEL_UMSK (~(((1U << PDS_CLKPLL_REFCLK_SEL_LEN) - 1) << PDS_CLKPLL_REFCLK_SEL_POS)) +#define PDS_CLKPLL_VG11_SEL PDS_CLKPLL_VG11_SEL +#define PDS_CLKPLL_VG11_SEL_POS (20U) +#define PDS_CLKPLL_VG11_SEL_LEN (2U) +#define PDS_CLKPLL_VG11_SEL_MSK (((1U << PDS_CLKPLL_VG11_SEL_LEN) - 1) << PDS_CLKPLL_VG11_SEL_POS) +#define PDS_CLKPLL_VG11_SEL_UMSK (~(((1U << PDS_CLKPLL_VG11_SEL_LEN) - 1) << PDS_CLKPLL_VG11_SEL_POS)) +#define PDS_CLKPLL_VG13_SEL PDS_CLKPLL_VG13_SEL +#define PDS_CLKPLL_VG13_SEL_POS (24U) +#define PDS_CLKPLL_VG13_SEL_LEN (2U) +#define PDS_CLKPLL_VG13_SEL_MSK (((1U << PDS_CLKPLL_VG13_SEL_LEN) - 1) << PDS_CLKPLL_VG13_SEL_POS) +#define PDS_CLKPLL_VG13_SEL_UMSK (~(((1U << PDS_CLKPLL_VG13_SEL_LEN) - 1) << PDS_CLKPLL_VG13_SEL_POS)) + +/* 0x408 : clkpll_cp */ +#define PDS_CLKPLL_CP_OFFSET (0x408) +#define PDS_CLKPLL_SEL_CP_BIAS PDS_CLKPLL_SEL_CP_BIAS +#define PDS_CLKPLL_SEL_CP_BIAS_POS (0U) +#define PDS_CLKPLL_SEL_CP_BIAS_LEN (1U) +#define PDS_CLKPLL_SEL_CP_BIAS_MSK (((1U << PDS_CLKPLL_SEL_CP_BIAS_LEN) - 1) << PDS_CLKPLL_SEL_CP_BIAS_POS) +#define PDS_CLKPLL_SEL_CP_BIAS_UMSK (~(((1U << PDS_CLKPLL_SEL_CP_BIAS_LEN) - 1) << PDS_CLKPLL_SEL_CP_BIAS_POS)) +#define PDS_CLKPLL_ICP_5U PDS_CLKPLL_ICP_5U +#define PDS_CLKPLL_ICP_5U_POS (4U) +#define PDS_CLKPLL_ICP_5U_LEN (2U) +#define PDS_CLKPLL_ICP_5U_MSK (((1U << PDS_CLKPLL_ICP_5U_LEN) - 1) << PDS_CLKPLL_ICP_5U_POS) +#define PDS_CLKPLL_ICP_5U_UMSK (~(((1U << PDS_CLKPLL_ICP_5U_LEN) - 1) << PDS_CLKPLL_ICP_5U_POS)) +#define PDS_CLKPLL_ICP_1U PDS_CLKPLL_ICP_1U +#define PDS_CLKPLL_ICP_1U_POS (6U) +#define PDS_CLKPLL_ICP_1U_LEN (2U) +#define PDS_CLKPLL_ICP_1U_MSK (((1U << PDS_CLKPLL_ICP_1U_LEN) - 1) << PDS_CLKPLL_ICP_1U_POS) +#define PDS_CLKPLL_ICP_1U_UMSK (~(((1U << PDS_CLKPLL_ICP_1U_LEN) - 1) << PDS_CLKPLL_ICP_1U_POS)) +#define PDS_CLKPLL_INT_FRAC_SW PDS_CLKPLL_INT_FRAC_SW +#define PDS_CLKPLL_INT_FRAC_SW_POS (8U) +#define PDS_CLKPLL_INT_FRAC_SW_LEN (1U) +#define PDS_CLKPLL_INT_FRAC_SW_MSK (((1U << PDS_CLKPLL_INT_FRAC_SW_LEN) - 1) << PDS_CLKPLL_INT_FRAC_SW_POS) +#define PDS_CLKPLL_INT_FRAC_SW_UMSK (~(((1U << PDS_CLKPLL_INT_FRAC_SW_LEN) - 1) << PDS_CLKPLL_INT_FRAC_SW_POS)) +#define PDS_CLKPLL_CP_STARTUP_EN PDS_CLKPLL_CP_STARTUP_EN +#define PDS_CLKPLL_CP_STARTUP_EN_POS (9U) +#define PDS_CLKPLL_CP_STARTUP_EN_LEN (1U) +#define PDS_CLKPLL_CP_STARTUP_EN_MSK (((1U << PDS_CLKPLL_CP_STARTUP_EN_LEN) - 1) << PDS_CLKPLL_CP_STARTUP_EN_POS) +#define PDS_CLKPLL_CP_STARTUP_EN_UMSK (~(((1U << PDS_CLKPLL_CP_STARTUP_EN_LEN) - 1) << PDS_CLKPLL_CP_STARTUP_EN_POS)) +#define PDS_CLKPLL_CP_OPAMP_EN PDS_CLKPLL_CP_OPAMP_EN +#define PDS_CLKPLL_CP_OPAMP_EN_POS (10U) +#define PDS_CLKPLL_CP_OPAMP_EN_LEN (1U) +#define PDS_CLKPLL_CP_OPAMP_EN_MSK (((1U << PDS_CLKPLL_CP_OPAMP_EN_LEN) - 1) << PDS_CLKPLL_CP_OPAMP_EN_POS) +#define PDS_CLKPLL_CP_OPAMP_EN_UMSK (~(((1U << PDS_CLKPLL_CP_OPAMP_EN_LEN) - 1) << PDS_CLKPLL_CP_OPAMP_EN_POS)) + +/* 0x40C : clkpll_rz */ +#define PDS_CLKPLL_RZ_OFFSET (0x40C) +#define PDS_CLKPLL_C4_EN PDS_CLKPLL_C4_EN +#define PDS_CLKPLL_C4_EN_POS (0U) +#define PDS_CLKPLL_C4_EN_LEN (1U) +#define PDS_CLKPLL_C4_EN_MSK (((1U << PDS_CLKPLL_C4_EN_LEN) - 1) << PDS_CLKPLL_C4_EN_POS) +#define PDS_CLKPLL_C4_EN_UMSK (~(((1U << PDS_CLKPLL_C4_EN_LEN) - 1) << PDS_CLKPLL_C4_EN_POS)) +#define PDS_CLKPLL_R4 PDS_CLKPLL_R4 +#define PDS_CLKPLL_R4_POS (4U) +#define PDS_CLKPLL_R4_LEN (2U) +#define PDS_CLKPLL_R4_MSK (((1U << PDS_CLKPLL_R4_LEN) - 1) << PDS_CLKPLL_R4_POS) +#define PDS_CLKPLL_R4_UMSK (~(((1U << PDS_CLKPLL_R4_LEN) - 1) << PDS_CLKPLL_R4_POS)) +#define PDS_CLKPLL_R4_SHORT PDS_CLKPLL_R4_SHORT +#define PDS_CLKPLL_R4_SHORT_POS (8U) +#define PDS_CLKPLL_R4_SHORT_LEN (1U) +#define PDS_CLKPLL_R4_SHORT_MSK (((1U << PDS_CLKPLL_R4_SHORT_LEN) - 1) << PDS_CLKPLL_R4_SHORT_POS) +#define PDS_CLKPLL_R4_SHORT_UMSK (~(((1U << PDS_CLKPLL_R4_SHORT_LEN) - 1) << PDS_CLKPLL_R4_SHORT_POS)) +#define PDS_CLKPLL_C3 PDS_CLKPLL_C3 +#define PDS_CLKPLL_C3_POS (12U) +#define PDS_CLKPLL_C3_LEN (2U) +#define PDS_CLKPLL_C3_MSK (((1U << PDS_CLKPLL_C3_LEN) - 1) << PDS_CLKPLL_C3_POS) +#define PDS_CLKPLL_C3_UMSK (~(((1U << PDS_CLKPLL_C3_LEN) - 1) << PDS_CLKPLL_C3_POS)) +#define PDS_CLKPLL_CZ PDS_CLKPLL_CZ +#define PDS_CLKPLL_CZ_POS (14U) +#define PDS_CLKPLL_CZ_LEN (2U) +#define PDS_CLKPLL_CZ_MSK (((1U << PDS_CLKPLL_CZ_LEN) - 1) << PDS_CLKPLL_CZ_POS) +#define PDS_CLKPLL_CZ_UMSK (~(((1U << PDS_CLKPLL_CZ_LEN) - 1) << PDS_CLKPLL_CZ_POS)) +#define PDS_CLKPLL_RZ PDS_CLKPLL_RZ +#define PDS_CLKPLL_RZ_POS (16U) +#define PDS_CLKPLL_RZ_LEN (3U) +#define PDS_CLKPLL_RZ_MSK (((1U << PDS_CLKPLL_RZ_LEN) - 1) << PDS_CLKPLL_RZ_POS) +#define PDS_CLKPLL_RZ_UMSK (~(((1U << PDS_CLKPLL_RZ_LEN) - 1) << PDS_CLKPLL_RZ_POS)) + +/* 0x410 : clkpll_fbdv */ +#define PDS_CLKPLL_FBDV_OFFSET (0x410) +#define PDS_CLKPLL_SEL_SAMPLE_CLK PDS_CLKPLL_SEL_SAMPLE_CLK +#define PDS_CLKPLL_SEL_SAMPLE_CLK_POS (0U) +#define PDS_CLKPLL_SEL_SAMPLE_CLK_LEN (2U) +#define PDS_CLKPLL_SEL_SAMPLE_CLK_MSK (((1U << PDS_CLKPLL_SEL_SAMPLE_CLK_LEN) - 1) << PDS_CLKPLL_SEL_SAMPLE_CLK_POS) +#define PDS_CLKPLL_SEL_SAMPLE_CLK_UMSK (~(((1U << PDS_CLKPLL_SEL_SAMPLE_CLK_LEN) - 1) << PDS_CLKPLL_SEL_SAMPLE_CLK_POS)) +#define PDS_CLKPLL_SEL_FB_CLK PDS_CLKPLL_SEL_FB_CLK +#define PDS_CLKPLL_SEL_FB_CLK_POS (2U) +#define PDS_CLKPLL_SEL_FB_CLK_LEN (2U) +#define PDS_CLKPLL_SEL_FB_CLK_MSK (((1U << PDS_CLKPLL_SEL_FB_CLK_LEN) - 1) << PDS_CLKPLL_SEL_FB_CLK_POS) +#define PDS_CLKPLL_SEL_FB_CLK_UMSK (~(((1U << PDS_CLKPLL_SEL_FB_CLK_LEN) - 1) << PDS_CLKPLL_SEL_FB_CLK_POS)) + +/* 0x414 : clkpll_vco */ +#define PDS_CLKPLL_VCO_OFFSET (0x414) +#define PDS_CLKPLL_VCO_SPEED PDS_CLKPLL_VCO_SPEED +#define PDS_CLKPLL_VCO_SPEED_POS (0U) +#define PDS_CLKPLL_VCO_SPEED_LEN (3U) +#define PDS_CLKPLL_VCO_SPEED_MSK (((1U << PDS_CLKPLL_VCO_SPEED_LEN) - 1) << PDS_CLKPLL_VCO_SPEED_POS) +#define PDS_CLKPLL_VCO_SPEED_UMSK (~(((1U << PDS_CLKPLL_VCO_SPEED_LEN) - 1) << PDS_CLKPLL_VCO_SPEED_POS)) +#define PDS_CLKPLL_SHRTR PDS_CLKPLL_SHRTR +#define PDS_CLKPLL_SHRTR_POS (3U) +#define PDS_CLKPLL_SHRTR_LEN (1U) +#define PDS_CLKPLL_SHRTR_MSK (((1U << PDS_CLKPLL_SHRTR_LEN) - 1) << PDS_CLKPLL_SHRTR_POS) +#define PDS_CLKPLL_SHRTR_UMSK (~(((1U << PDS_CLKPLL_SHRTR_LEN) - 1) << PDS_CLKPLL_SHRTR_POS)) + +/* 0x418 : clkpll_sdm */ +#define PDS_CLKPLL_SDM_OFFSET (0x418) +#define PDS_CLKPLL_SDMIN PDS_CLKPLL_SDMIN +#define PDS_CLKPLL_SDMIN_POS (0U) +#define PDS_CLKPLL_SDMIN_LEN (24U) +#define PDS_CLKPLL_SDMIN_MSK (((1U << PDS_CLKPLL_SDMIN_LEN) - 1) << PDS_CLKPLL_SDMIN_POS) +#define PDS_CLKPLL_SDMIN_UMSK (~(((1U << PDS_CLKPLL_SDMIN_LEN) - 1) << PDS_CLKPLL_SDMIN_POS)) +#define PDS_CLKPLL_DITHER_SEL PDS_CLKPLL_DITHER_SEL +#define PDS_CLKPLL_DITHER_SEL_POS (24U) +#define PDS_CLKPLL_DITHER_SEL_LEN (2U) +#define PDS_CLKPLL_DITHER_SEL_MSK (((1U << PDS_CLKPLL_DITHER_SEL_LEN) - 1) << PDS_CLKPLL_DITHER_SEL_POS) +#define PDS_CLKPLL_DITHER_SEL_UMSK (~(((1U << PDS_CLKPLL_DITHER_SEL_LEN) - 1) << PDS_CLKPLL_DITHER_SEL_POS)) +#define PDS_CLKPLL_SDM_FLAG PDS_CLKPLL_SDM_FLAG +#define PDS_CLKPLL_SDM_FLAG_POS (28U) +#define PDS_CLKPLL_SDM_FLAG_LEN (1U) +#define PDS_CLKPLL_SDM_FLAG_MSK (((1U << PDS_CLKPLL_SDM_FLAG_LEN) - 1) << PDS_CLKPLL_SDM_FLAG_POS) +#define PDS_CLKPLL_SDM_FLAG_UMSK (~(((1U << PDS_CLKPLL_SDM_FLAG_LEN) - 1) << PDS_CLKPLL_SDM_FLAG_POS)) +#define PDS_CLKPLL_SDM_BYPASS PDS_CLKPLL_SDM_BYPASS +#define PDS_CLKPLL_SDM_BYPASS_POS (29U) +#define PDS_CLKPLL_SDM_BYPASS_LEN (1U) +#define PDS_CLKPLL_SDM_BYPASS_MSK (((1U << PDS_CLKPLL_SDM_BYPASS_LEN) - 1) << PDS_CLKPLL_SDM_BYPASS_POS) +#define PDS_CLKPLL_SDM_BYPASS_UMSK (~(((1U << PDS_CLKPLL_SDM_BYPASS_LEN) - 1) << PDS_CLKPLL_SDM_BYPASS_POS)) + +/* 0x41C : clkpll_output_en */ +#define PDS_CLKPLL_OUTPUT_EN_OFFSET (0x41C) +#define PDS_CLKPLL_EN_480M PDS_CLKPLL_EN_480M +#define PDS_CLKPLL_EN_480M_POS (0U) +#define PDS_CLKPLL_EN_480M_LEN (1U) +#define PDS_CLKPLL_EN_480M_MSK (((1U << PDS_CLKPLL_EN_480M_LEN) - 1) << PDS_CLKPLL_EN_480M_POS) +#define PDS_CLKPLL_EN_480M_UMSK (~(((1U << PDS_CLKPLL_EN_480M_LEN) - 1) << PDS_CLKPLL_EN_480M_POS)) +#define PDS_CLKPLL_EN_240M PDS_CLKPLL_EN_240M +#define PDS_CLKPLL_EN_240M_POS (1U) +#define PDS_CLKPLL_EN_240M_LEN (1U) +#define PDS_CLKPLL_EN_240M_MSK (((1U << PDS_CLKPLL_EN_240M_LEN) - 1) << PDS_CLKPLL_EN_240M_POS) +#define PDS_CLKPLL_EN_240M_UMSK (~(((1U << PDS_CLKPLL_EN_240M_LEN) - 1) << PDS_CLKPLL_EN_240M_POS)) +#define PDS_CLKPLL_EN_192M PDS_CLKPLL_EN_192M +#define PDS_CLKPLL_EN_192M_POS (2U) +#define PDS_CLKPLL_EN_192M_LEN (1U) +#define PDS_CLKPLL_EN_192M_MSK (((1U << PDS_CLKPLL_EN_192M_LEN) - 1) << PDS_CLKPLL_EN_192M_POS) +#define PDS_CLKPLL_EN_192M_UMSK (~(((1U << PDS_CLKPLL_EN_192M_LEN) - 1) << PDS_CLKPLL_EN_192M_POS)) +#define PDS_CLKPLL_EN_160M PDS_CLKPLL_EN_160M +#define PDS_CLKPLL_EN_160M_POS (3U) +#define PDS_CLKPLL_EN_160M_LEN (1U) +#define PDS_CLKPLL_EN_160M_MSK (((1U << PDS_CLKPLL_EN_160M_LEN) - 1) << PDS_CLKPLL_EN_160M_POS) +#define PDS_CLKPLL_EN_160M_UMSK (~(((1U << PDS_CLKPLL_EN_160M_LEN) - 1) << PDS_CLKPLL_EN_160M_POS)) +#define PDS_CLKPLL_EN_120M PDS_CLKPLL_EN_120M +#define PDS_CLKPLL_EN_120M_POS (4U) +#define PDS_CLKPLL_EN_120M_LEN (1U) +#define PDS_CLKPLL_EN_120M_MSK (((1U << PDS_CLKPLL_EN_120M_LEN) - 1) << PDS_CLKPLL_EN_120M_POS) +#define PDS_CLKPLL_EN_120M_UMSK (~(((1U << PDS_CLKPLL_EN_120M_LEN) - 1) << PDS_CLKPLL_EN_120M_POS)) +#define PDS_CLKPLL_EN_96M PDS_CLKPLL_EN_96M +#define PDS_CLKPLL_EN_96M_POS (5U) +#define PDS_CLKPLL_EN_96M_LEN (1U) +#define PDS_CLKPLL_EN_96M_MSK (((1U << PDS_CLKPLL_EN_96M_LEN) - 1) << PDS_CLKPLL_EN_96M_POS) +#define PDS_CLKPLL_EN_96M_UMSK (~(((1U << PDS_CLKPLL_EN_96M_LEN) - 1) << PDS_CLKPLL_EN_96M_POS)) +#define PDS_CLKPLL_EN_80M PDS_CLKPLL_EN_80M +#define PDS_CLKPLL_EN_80M_POS (6U) +#define PDS_CLKPLL_EN_80M_LEN (1U) +#define PDS_CLKPLL_EN_80M_MSK (((1U << PDS_CLKPLL_EN_80M_LEN) - 1) << PDS_CLKPLL_EN_80M_POS) +#define PDS_CLKPLL_EN_80M_UMSK (~(((1U << PDS_CLKPLL_EN_80M_LEN) - 1) << PDS_CLKPLL_EN_80M_POS)) +#define PDS_CLKPLL_EN_48M PDS_CLKPLL_EN_48M +#define PDS_CLKPLL_EN_48M_POS (7U) +#define PDS_CLKPLL_EN_48M_LEN (1U) +#define PDS_CLKPLL_EN_48M_MSK (((1U << PDS_CLKPLL_EN_48M_LEN) - 1) << PDS_CLKPLL_EN_48M_POS) +#define PDS_CLKPLL_EN_48M_UMSK (~(((1U << PDS_CLKPLL_EN_48M_LEN) - 1) << PDS_CLKPLL_EN_48M_POS)) +#define PDS_CLKPLL_EN_32M PDS_CLKPLL_EN_32M +#define PDS_CLKPLL_EN_32M_POS (8U) +#define PDS_CLKPLL_EN_32M_LEN (1U) +#define PDS_CLKPLL_EN_32M_MSK (((1U << PDS_CLKPLL_EN_32M_LEN) - 1) << PDS_CLKPLL_EN_32M_POS) +#define PDS_CLKPLL_EN_32M_UMSK (~(((1U << PDS_CLKPLL_EN_32M_LEN) - 1) << PDS_CLKPLL_EN_32M_POS)) +#define PDS_CLKPLL_EN_DIV2_480M PDS_CLKPLL_EN_DIV2_480M +#define PDS_CLKPLL_EN_DIV2_480M_POS (9U) +#define PDS_CLKPLL_EN_DIV2_480M_LEN (1U) +#define PDS_CLKPLL_EN_DIV2_480M_MSK (((1U << PDS_CLKPLL_EN_DIV2_480M_LEN) - 1) << PDS_CLKPLL_EN_DIV2_480M_POS) +#define PDS_CLKPLL_EN_DIV2_480M_UMSK (~(((1U << PDS_CLKPLL_EN_DIV2_480M_LEN) - 1) << PDS_CLKPLL_EN_DIV2_480M_POS)) + +struct pds_reg { + /* 0x0 : PDS_CTL */ + union { + struct + { + uint32_t pds_start_ps : 1; /* [ 0], w1p, 0x0 */ + uint32_t cr_sleep_forever : 1; /* [ 1], r/w, 0x0 */ + uint32_t cr_xtal_force_off : 1; /* [ 2], r/w, 0x0 */ + uint32_t cr_wifi_pds_save_state : 1; /* [ 3], r/w, 0x0 */ + uint32_t cr_pds_pd_dcdc18 : 1; /* [ 4], r/w, 0x0 */ + uint32_t cr_pds_pd_bg_sys : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t cr_pds_gate_clk : 1; /* [ 8], r/w, 0x1 */ + uint32_t cr_pds_mem_stby : 1; /* [ 9], r/w, 0x1 */ + uint32_t reserved_10 : 1; /* [ 10], rsvd, 0x0 */ + uint32_t cr_pds_iso_en : 1; /* [ 11], r/w, 0x1 */ + uint32_t cr_pds_wait_xtal_rdy : 1; /* [ 12], r/w, 0x0 */ + uint32_t cr_pds_pwr_off : 1; /* [ 13], r/w, 0x1 */ + uint32_t cr_pds_pd_xtal : 1; /* [ 14], r/w, 0x1 */ + uint32_t cr_pds_soc_enb_force_on : 1; /* [ 15], r/w, 0x0 */ + uint32_t cr_pds_rst_soc_en : 1; /* [ 16], r/w, 0x0 */ + uint32_t cr_pds_rc32m_off_dis : 1; /* [ 17], r/w, 0x0 */ + uint32_t cr_pds_ldo_vsel_en : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19_20 : 2; /* [20:19], rsvd, 0x0 */ + uint32_t cr_np_wfi_mask : 1; /* [ 21], r/w, 0x0 */ + uint32_t cr_pds_pd_ldo11 : 1; /* [ 22], r/w, 0x0 */ + uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ + uint32_t cr_pds_ldo_vol : 4; /* [27:24], r/w, 0xa */ + uint32_t cr_pds_ctrl_rf : 2; /* [29:28], r/w, 0x1 */ + uint32_t cr_pds_ctrl_pll : 2; /* [31:30], r/w, 0x0 */ + } BF; + uint32_t WORD; + } PDS_CTL; + + /* 0x4 : PDS_TIME1 */ + union { + struct + { + uint32_t cr_sleep_duration : 32; /* [31: 0], r/w, 0xca8 */ + } BF; + uint32_t WORD; + } PDS_TIME1; + + /* 0x8 reserved */ + uint8_t RESERVED0x8[4]; + + /* 0xC : PDS_INT */ + union { + struct + { + uint32_t ro_pds_wake_int : 1; /* [ 0], r, 0x0 */ + uint32_t ro_pds_irq_in : 1; /* [ 1], r, 0x0 */ + uint32_t ro_pds_rf_done_int : 1; /* [ 2], r, 0x0 */ + uint32_t ro_pds_pll_done_int : 1; /* [ 3], r, 0x0 */ + uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */ + uint32_t cr_pds_wake_int_mask : 1; /* [ 8], r/w, 0x0 */ + uint32_t cr_pds_irq_in_dis : 1; /* [ 9], r/w, 0x0 */ + uint32_t cr_pds_rf_done_int_mask : 1; /* [ 10], r/w, 0x0 */ + uint32_t cr_pds_pll_done_int_mask : 1; /* [ 11], r/w, 0x0 */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t cr_pds_int_clr : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } PDS_INT; + + /* 0x10 : PDS_CTL2 */ + union { + struct + { + uint32_t cr_pds_force_np_pwr_off : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */ + uint32_t cr_pds_force_wb_pwr_off : 1; /* [ 2], r/w, 0x0 */ + uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ + uint32_t cr_pds_force_np_iso_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t reserved_5 : 1; /* [ 5], rsvd, 0x0 */ + uint32_t cr_pds_force_wb_iso_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t cr_pds_force_np_pds_rst : 1; /* [ 8], r/w, 0x0 */ + uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */ + uint32_t cr_pds_force_wb_pds_rst : 1; /* [ 10], r/w, 0x0 */ + uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ + uint32_t cr_pds_force_np_mem_stby : 1; /* [ 12], r/w, 0x0 */ + uint32_t reserved_13 : 1; /* [ 13], rsvd, 0x0 */ + uint32_t cr_pds_force_wb_mem_stby : 1; /* [ 14], r/w, 0x0 */ + uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ + uint32_t cr_pds_force_np_gate_clk : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */ + uint32_t cr_pds_force_wb_gate_clk : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } PDS_CTL2; + + /* 0x14 : PDS_CTL3 */ + union { + struct + { + uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ + uint32_t cr_pds_force_misc_pwr_off : 1; /* [ 1], r/w, 0x0 */ + uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ + uint32_t cr_pds_force_misc_iso_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t reserved_5_6 : 2; /* [ 6: 5], rsvd, 0x0 */ + uint32_t cr_pds_force_misc_pds_rst : 1; /* [ 7], r/w, 0x0 */ + uint32_t reserved_8_9 : 2; /* [ 9: 8], rsvd, 0x0 */ + uint32_t cr_pds_force_misc_mem_stby : 1; /* [ 10], r/w, 0x0 */ + uint32_t reserved_11_12 : 2; /* [12:11], rsvd, 0x0 */ + uint32_t cr_pds_force_misc_gate_clk : 1; /* [ 13], r/w, 0x0 */ + uint32_t reserved_14_23 : 10; /* [23:14], rsvd, 0x0 */ + uint32_t cr_pds_np_iso_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t reserved_25_26 : 2; /* [26:25], rsvd, 0x0 */ + uint32_t cr_pds_wb_iso_en : 1; /* [ 27], r/w, 0x1 */ + uint32_t reserved_28_29 : 2; /* [29:28], rsvd, 0x0 */ + uint32_t cr_pds_misc_iso_en : 1; /* [ 30], r/w, 0x1 */ + uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } PDS_CTL3; + + /* 0x18 : PDS_CTL4 */ + union { + struct + { + uint32_t cr_pds_np_pwr_off : 1; /* [ 0], r/w, 0x1 */ + uint32_t cr_pds_np_reset : 1; /* [ 1], r/w, 0x1 */ + uint32_t cr_pds_np_mem_stby : 1; /* [ 2], r/w, 0x1 */ + uint32_t cr_pds_np_gate_clk : 1; /* [ 3], r/w, 0x1 */ + uint32_t reserved_4_11 : 8; /* [11: 4], rsvd, 0x0 */ + uint32_t cr_pds_wb_pwr_off : 1; /* [ 12], r/w, 0x1 */ + uint32_t cr_pds_wb_reset : 1; /* [ 13], r/w, 0x1 */ + uint32_t cr_pds_wb_mem_stby : 1; /* [ 14], r/w, 0x1 */ + uint32_t cr_pds_wb_gate_clk : 1; /* [ 15], r/w, 0x1 */ + uint32_t reserved_16_23 : 8; /* [23:16], rsvd, 0x0 */ + uint32_t cr_pds_misc_pwr_off : 1; /* [ 24], r/w, 0x1 */ + uint32_t cr_pds_misc_reset : 1; /* [ 25], r/w, 0x1 */ + uint32_t cr_pds_misc_mem_stby : 1; /* [ 26], r/w, 0x1 */ + uint32_t cr_pds_misc_gate_clk : 1; /* [ 27], r/w, 0x1 */ + uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } PDS_CTL4; + + /* 0x1C : pds_stat */ + union { + struct + { + uint32_t ro_pds_state : 4; /* [ 3: 0], r, 0x0 */ + uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */ + uint32_t ro_pds_rf_state : 4; /* [11: 8], r, 0x0 */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t ro_pds_pll_state : 2; /* [17:16], r, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pds_stat; + + /* 0x20 : pds_ram1 */ + union { + struct + { + uint32_t cr_np_sram_pwr : 8; /* [ 7: 0], r/w, 0x0 */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pds_ram1; + + /* 0x24 reserved */ + uint8_t RESERVED0x24[732]; + + /* 0x300 : rc32m_ctrl0 */ + union { + struct + { + uint32_t rc32m_cal_done : 1; /* [ 0], r, 0x0 */ + uint32_t rc32m_rdy : 1; /* [ 1], r, 0x0 */ + uint32_t rc32m_cal_inprogress : 1; /* [ 2], r, 0x0 */ + uint32_t rc32m_cal_div : 2; /* [ 4: 3], r/w, 0x3 */ + uint32_t rc32m_cal_precharge : 1; /* [ 5], r, 0x0 */ + uint32_t rc32m_dig_code_fr_cal : 8; /* [13: 6], r, 0x0 */ + uint32_t reserved_14_16 : 3; /* [16:14], rsvd, 0x0 */ + uint32_t rc32m_allow_cal : 1; /* [ 17], r/w, 0x0 */ + uint32_t rc32m_refclk_half : 1; /* [ 18], r/w, 0x0 */ + uint32_t rc32m_ext_code_en : 1; /* [ 19], r/w, 0x1 */ + uint32_t rc32m_cal_en : 1; /* [ 20], r/w, 0x0 */ + uint32_t rc32m_pd : 1; /* [ 21], r/w, 0x0 */ + uint32_t rc32m_code_fr_ext : 8; /* [29:22], r/w, 0x60 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } rc32m_ctrl0; + + /* 0x304 : rc32m_ctrl1 */ + union { + struct + { + uint32_t rc32m_test_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t rc32m_soft_rst : 1; /* [ 1], r/w, 0x0 */ + uint32_t rc32m_clk_soft_rst : 1; /* [ 2], r/w, 0x0 */ + uint32_t rc32m_clk_inv : 1; /* [ 3], r/w, 0x0 */ + uint32_t rc32m_clk_force_on : 1; /* [ 4], r/w, 0x0 */ + uint32_t reserved_5_23 : 19; /* [23: 5], rsvd, 0x0 */ + uint32_t rc32m_reserved : 8; /* [31:24], r/w, 0xf */ + } BF; + uint32_t WORD; + } rc32m_ctrl1; + + /* 0x308 reserved */ + uint8_t RESERVED0x308[248]; + + /* 0x400 : pu_rst_clkpll */ + union { + struct + { + uint32_t clkpll_sdm_reset : 1; /* [ 0], r/w, 0x0 */ + uint32_t clkpll_reset_postdiv : 1; /* [ 1], r/w, 0x0 */ + uint32_t clkpll_reset_fbdv : 1; /* [ 2], r/w, 0x0 */ + uint32_t clkpll_reset_refdiv : 1; /* [ 3], r/w, 0x0 */ + uint32_t clkpll_pu_postdiv : 1; /* [ 4], r/w, 0x1 */ + uint32_t clkpll_pu_fbdv : 1; /* [ 5], r/w, 0x1 */ + uint32_t clkpll_pu_clamp_op : 1; /* [ 6], r/w, 0x1 */ + uint32_t clkpll_pu_pfd : 1; /* [ 7], r/w, 0x1 */ + uint32_t clkpll_pu_cp : 1; /* [ 8], r/w, 0x1 */ + uint32_t pu_clkpll_sfreg : 1; /* [ 9], r/w, 0x0 */ + uint32_t pu_clkpll : 1; /* [ 10], r/w, 0x0 */ + uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pu_rst_clkpll; + + /* 0x404 : clkpll_top_ctrl */ + union { + struct + { + uint32_t clkpll_postdiv : 7; /* [ 6: 0], r/w, 0x14 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t clkpll_refdiv_ratio : 4; /* [11: 8], r/w, 0x4 */ + uint32_t clkpll_xtal_rc32m_sel : 1; /* [ 12], r/w, 0x0 */ + uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ + uint32_t clkpll_refclk_sel : 1; /* [ 16], r/w, 0x0 */ + uint32_t reserved_17_19 : 3; /* [19:17], rsvd, 0x0 */ + uint32_t clkpll_vg11_sel : 2; /* [21:20], r/w, 0x1 */ + uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ + uint32_t clkpll_vg13_sel : 2; /* [25:24], r/w, 0x1 */ + uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clkpll_top_ctrl; + + /* 0x408 : clkpll_cp */ + union { + struct + { + uint32_t clkpll_sel_cp_bias : 1; /* [ 0], r/w, 0x1 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t clkpll_icp_5u : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t clkpll_icp_1u : 2; /* [ 7: 6], r/w, 0x1 */ + uint32_t clkpll_int_frac_sw : 1; /* [ 8], r/w, 0x1 */ + uint32_t clkpll_cp_startup_en : 1; /* [ 9], r/w, 0x1 */ + uint32_t clkpll_cp_opamp_en : 1; /* [ 10], r/w, 0x1 */ + uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clkpll_cp; + + /* 0x40C : clkpll_rz */ + union { + struct + { + uint32_t clkpll_c4_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t clkpll_r4 : 2; /* [ 5: 4], r/w, 0x2 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t clkpll_r4_short : 1; /* [ 8], r/w, 0x0 */ + uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */ + uint32_t clkpll_c3 : 2; /* [13:12], r/w, 0x2 */ + uint32_t clkpll_cz : 2; /* [15:14], r/w, 0x2 */ + uint32_t clkpll_rz : 3; /* [18:16], r/w, 0x5 */ + uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clkpll_rz; + + /* 0x410 : clkpll_fbdv */ + union { + struct + { + uint32_t clkpll_sel_sample_clk : 2; /* [ 1: 0], r/w, 0x1 */ + uint32_t clkpll_sel_fb_clk : 2; /* [ 3: 2], r/w, 0x1 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clkpll_fbdv; + + /* 0x414 : clkpll_vco */ + union { + struct + { + uint32_t clkpll_vco_speed : 3; /* [ 2: 0], r/w, 0x7 */ + uint32_t clkpll_shrtr : 1; /* [ 3], r/w, 0x0 */ + uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clkpll_vco; + + /* 0x418 : clkpll_sdm */ + union { + struct + { + uint32_t clkpll_sdmin : 24; /* [23: 0], r/w, 0x600000 */ + uint32_t clkpll_dither_sel : 2; /* [25:24], r/w, 0x0 */ + uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */ + uint32_t clkpll_sdm_flag : 1; /* [ 28], r/w, 0x1 */ + uint32_t clkpll_sdm_bypass : 1; /* [ 29], r/w, 0x0 */ + uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clkpll_sdm; + + /* 0x41C : clkpll_output_en */ + union { + struct + { + uint32_t clkpll_en_480m : 1; /* [ 0], r/w, 0x0 */ + uint32_t clkpll_en_240m : 1; /* [ 1], r/w, 0x0 */ + uint32_t clkpll_en_192m : 1; /* [ 2], r/w, 0x0 */ + uint32_t clkpll_en_160m : 1; /* [ 3], r/w, 0x0 */ + uint32_t clkpll_en_120m : 1; /* [ 4], r/w, 0x0 */ + uint32_t clkpll_en_96m : 1; /* [ 5], r/w, 0x0 */ + uint32_t clkpll_en_80m : 1; /* [ 6], r/w, 0x0 */ + uint32_t clkpll_en_48m : 1; /* [ 7], r/w, 0x0 */ + uint32_t clkpll_en_32m : 1; /* [ 8], r/w, 0x1 */ + uint32_t clkpll_en_div2_480m : 1; /* [ 9], r/w, 0x0 */ + uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } clkpll_output_en; +}; + +typedef volatile struct pds_reg pds_reg_t; + +#endif /* __PDS_REG_H__ */ diff --git a/drivers/soc/bl602/bl602_std/include/hardware/sf_ctrl_reg.h b/drivers/soc/bl602/bl602_std/include/hardware/sf_ctrl_reg.h new file mode 100644 index 00000000..5c369545 --- /dev/null +++ b/drivers/soc/bl602/bl602_std/include/hardware/sf_ctrl_reg.h @@ -0,0 +1,2450 @@ +/** + ****************************************************************************** + * @file sf_ctrl_reg.h + * @version V1.2 + * @date 2019-10-21 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __SF_CTRL_REG_H__ +#define __SF_CTRL_REG_H__ + +#include "bl602.h" + +/* 0x0 : sf_ctrl_0 */ +#define SF_CTRL_0_OFFSET (0x0) +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL SF_CTRL_SF_CLK_SF_RX_INV_SEL +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS (2U) +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN (1U) +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_MSK (((1U << SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS) +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS)) +#define SF_CTRL_SF_CLK_OUT_GATE_EN SF_CTRL_SF_CLK_OUT_GATE_EN +#define SF_CTRL_SF_CLK_OUT_GATE_EN_POS (3U) +#define SF_CTRL_SF_CLK_OUT_GATE_EN_LEN (1U) +#define SF_CTRL_SF_CLK_OUT_GATE_EN_MSK (((1U << SF_CTRL_SF_CLK_OUT_GATE_EN_LEN) - 1) << SF_CTRL_SF_CLK_OUT_GATE_EN_POS) +#define SF_CTRL_SF_CLK_OUT_GATE_EN_UMSK (~(((1U << SF_CTRL_SF_CLK_OUT_GATE_EN_LEN) - 1) << SF_CTRL_SF_CLK_OUT_GATE_EN_POS)) +#define SF_CTRL_SF_CLK_OUT_INV_SEL SF_CTRL_SF_CLK_OUT_INV_SEL +#define SF_CTRL_SF_CLK_OUT_INV_SEL_POS (4U) +#define SF_CTRL_SF_CLK_OUT_INV_SEL_LEN (1U) +#define SF_CTRL_SF_CLK_OUT_INV_SEL_MSK (((1U << SF_CTRL_SF_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_INV_SEL_POS) +#define SF_CTRL_SF_CLK_OUT_INV_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_INV_SEL_POS)) +#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL SF_CTRL_SF_CLK_SAHB_SRAM_SEL +#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS (5U) +#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN (1U) +#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_MSK (((1U << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS) +#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS)) +#define SF_CTRL_SF_IF_READ_DLY_N SF_CTRL_SF_IF_READ_DLY_N +#define SF_CTRL_SF_IF_READ_DLY_N_POS (8U) +#define SF_CTRL_SF_IF_READ_DLY_N_LEN (3U) +#define SF_CTRL_SF_IF_READ_DLY_N_MSK (((1U << SF_CTRL_SF_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_N_POS) +#define SF_CTRL_SF_IF_READ_DLY_N_UMSK (~(((1U << SF_CTRL_SF_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_N_POS)) +#define SF_CTRL_SF_IF_READ_DLY_EN SF_CTRL_SF_IF_READ_DLY_EN +#define SF_CTRL_SF_IF_READ_DLY_EN_POS (11U) +#define SF_CTRL_SF_IF_READ_DLY_EN_LEN (1U) +#define SF_CTRL_SF_IF_READ_DLY_EN_MSK (((1U << SF_CTRL_SF_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_EN_POS) +#define SF_CTRL_SF_IF_READ_DLY_EN_UMSK (~(((1U << SF_CTRL_SF_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_EN_POS)) +#define SF_CTRL_SF_IF_INT SF_CTRL_SF_IF_INT +#define SF_CTRL_SF_IF_INT_POS (16U) +#define SF_CTRL_SF_IF_INT_LEN (1U) +#define SF_CTRL_SF_IF_INT_MSK (((1U << SF_CTRL_SF_IF_INT_LEN) - 1) << SF_CTRL_SF_IF_INT_POS) +#define SF_CTRL_SF_IF_INT_UMSK (~(((1U << SF_CTRL_SF_IF_INT_LEN) - 1) << SF_CTRL_SF_IF_INT_POS)) +#define SF_CTRL_SF_IF_INT_CLR SF_CTRL_SF_IF_INT_CLR +#define SF_CTRL_SF_IF_INT_CLR_POS (17U) +#define SF_CTRL_SF_IF_INT_CLR_LEN (1U) +#define SF_CTRL_SF_IF_INT_CLR_MSK (((1U << SF_CTRL_SF_IF_INT_CLR_LEN) - 1) << SF_CTRL_SF_IF_INT_CLR_POS) +#define SF_CTRL_SF_IF_INT_CLR_UMSK (~(((1U << SF_CTRL_SF_IF_INT_CLR_LEN) - 1) << SF_CTRL_SF_IF_INT_CLR_POS)) +#define SF_CTRL_SF_IF_INT_SET SF_CTRL_SF_IF_INT_SET +#define SF_CTRL_SF_IF_INT_SET_POS (18U) +#define SF_CTRL_SF_IF_INT_SET_LEN (1U) +#define SF_CTRL_SF_IF_INT_SET_MSK (((1U << SF_CTRL_SF_IF_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_INT_SET_POS) +#define SF_CTRL_SF_IF_INT_SET_UMSK (~(((1U << SF_CTRL_SF_IF_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_INT_SET_POS)) +#define SF_CTRL_SF_AES_DLY_MODE SF_CTRL_SF_AES_DLY_MODE +#define SF_CTRL_SF_AES_DLY_MODE_POS (19U) +#define SF_CTRL_SF_AES_DLY_MODE_LEN (1U) +#define SF_CTRL_SF_AES_DLY_MODE_MSK (((1U << SF_CTRL_SF_AES_DLY_MODE_LEN) - 1) << SF_CTRL_SF_AES_DLY_MODE_POS) +#define SF_CTRL_SF_AES_DLY_MODE_UMSK (~(((1U << SF_CTRL_SF_AES_DLY_MODE_LEN) - 1) << SF_CTRL_SF_AES_DLY_MODE_POS)) +#define SF_CTRL_SF_AES_DOUT_ENDIAN SF_CTRL_SF_AES_DOUT_ENDIAN +#define SF_CTRL_SF_AES_DOUT_ENDIAN_POS (20U) +#define SF_CTRL_SF_AES_DOUT_ENDIAN_LEN (1U) +#define SF_CTRL_SF_AES_DOUT_ENDIAN_MSK (((1U << SF_CTRL_SF_AES_DOUT_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_DOUT_ENDIAN_POS) +#define SF_CTRL_SF_AES_DOUT_ENDIAN_UMSK (~(((1U << SF_CTRL_SF_AES_DOUT_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_DOUT_ENDIAN_POS)) +#define SF_CTRL_SF_AES_CTR_PLUS_EN SF_CTRL_SF_AES_CTR_PLUS_EN +#define SF_CTRL_SF_AES_CTR_PLUS_EN_POS (21U) +#define SF_CTRL_SF_AES_CTR_PLUS_EN_LEN (1U) +#define SF_CTRL_SF_AES_CTR_PLUS_EN_MSK (((1U << SF_CTRL_SF_AES_CTR_PLUS_EN_LEN) - 1) << SF_CTRL_SF_AES_CTR_PLUS_EN_POS) +#define SF_CTRL_SF_AES_CTR_PLUS_EN_UMSK (~(((1U << SF_CTRL_SF_AES_CTR_PLUS_EN_LEN) - 1) << SF_CTRL_SF_AES_CTR_PLUS_EN_POS)) +#define SF_CTRL_SF_AES_KEY_ENDIAN SF_CTRL_SF_AES_KEY_ENDIAN +#define SF_CTRL_SF_AES_KEY_ENDIAN_POS (22U) +#define SF_CTRL_SF_AES_KEY_ENDIAN_LEN (1U) +#define SF_CTRL_SF_AES_KEY_ENDIAN_MSK (((1U << SF_CTRL_SF_AES_KEY_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_KEY_ENDIAN_POS) +#define SF_CTRL_SF_AES_KEY_ENDIAN_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_KEY_ENDIAN_POS)) +#define SF_CTRL_SF_AES_IV_ENDIAN SF_CTRL_SF_AES_IV_ENDIAN +#define SF_CTRL_SF_AES_IV_ENDIAN_POS (23U) +#define SF_CTRL_SF_AES_IV_ENDIAN_LEN (1U) +#define SF_CTRL_SF_AES_IV_ENDIAN_MSK (((1U << SF_CTRL_SF_AES_IV_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_IV_ENDIAN_POS) +#define SF_CTRL_SF_AES_IV_ENDIAN_UMSK (~(((1U << SF_CTRL_SF_AES_IV_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_IV_ENDIAN_POS)) +#define SF_CTRL_SF_ID SF_CTRL_SF_ID +#define SF_CTRL_SF_ID_POS (24U) +#define SF_CTRL_SF_ID_LEN (8U) +#define SF_CTRL_SF_ID_MSK (((1U << SF_CTRL_SF_ID_LEN) - 1) << SF_CTRL_SF_ID_POS) +#define SF_CTRL_SF_ID_UMSK (~(((1U << SF_CTRL_SF_ID_LEN) - 1) << SF_CTRL_SF_ID_POS)) + +/* 0x4 : sf_ctrl_1 */ +#define SF_CTRL_1_OFFSET (0x4) +#define SF_CTRL_SF_IF_SR_PAT_MASK SF_CTRL_SF_IF_SR_PAT_MASK +#define SF_CTRL_SF_IF_SR_PAT_MASK_POS (0U) +#define SF_CTRL_SF_IF_SR_PAT_MASK_LEN (8U) +#define SF_CTRL_SF_IF_SR_PAT_MASK_MSK (((1U << SF_CTRL_SF_IF_SR_PAT_MASK_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_MASK_POS) +#define SF_CTRL_SF_IF_SR_PAT_MASK_UMSK (~(((1U << SF_CTRL_SF_IF_SR_PAT_MASK_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_MASK_POS)) +#define SF_CTRL_SF_IF_SR_PAT SF_CTRL_SF_IF_SR_PAT +#define SF_CTRL_SF_IF_SR_PAT_POS (8U) +#define SF_CTRL_SF_IF_SR_PAT_LEN (8U) +#define SF_CTRL_SF_IF_SR_PAT_MSK (((1U << SF_CTRL_SF_IF_SR_PAT_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_POS) +#define SF_CTRL_SF_IF_SR_PAT_UMSK (~(((1U << SF_CTRL_SF_IF_SR_PAT_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_POS)) +#define SF_CTRL_SF_IF_SR_INT SF_CTRL_SF_IF_SR_INT +#define SF_CTRL_SF_IF_SR_INT_POS (16U) +#define SF_CTRL_SF_IF_SR_INT_LEN (1U) +#define SF_CTRL_SF_IF_SR_INT_MSK (((1U << SF_CTRL_SF_IF_SR_INT_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_POS) +#define SF_CTRL_SF_IF_SR_INT_UMSK (~(((1U << SF_CTRL_SF_IF_SR_INT_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_POS)) +#define SF_CTRL_SF_IF_SR_INT_EN SF_CTRL_SF_IF_SR_INT_EN +#define SF_CTRL_SF_IF_SR_INT_EN_POS (17U) +#define SF_CTRL_SF_IF_SR_INT_EN_LEN (1U) +#define SF_CTRL_SF_IF_SR_INT_EN_MSK (((1U << SF_CTRL_SF_IF_SR_INT_EN_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_EN_POS) +#define SF_CTRL_SF_IF_SR_INT_EN_UMSK (~(((1U << SF_CTRL_SF_IF_SR_INT_EN_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_EN_POS)) +#define SF_CTRL_SF_IF_SR_INT_SET SF_CTRL_SF_IF_SR_INT_SET +#define SF_CTRL_SF_IF_SR_INT_SET_POS (18U) +#define SF_CTRL_SF_IF_SR_INT_SET_LEN (1U) +#define SF_CTRL_SF_IF_SR_INT_SET_MSK (((1U << SF_CTRL_SF_IF_SR_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_SET_POS) +#define SF_CTRL_SF_IF_SR_INT_SET_UMSK (~(((1U << SF_CTRL_SF_IF_SR_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_SET_POS)) +#define SF_CTRL_SF_IF_0_ACK_LAT SF_CTRL_SF_IF_0_ACK_LAT +#define SF_CTRL_SF_IF_0_ACK_LAT_POS (20U) +#define SF_CTRL_SF_IF_0_ACK_LAT_LEN (3U) +#define SF_CTRL_SF_IF_0_ACK_LAT_MSK (((1U << SF_CTRL_SF_IF_0_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_0_ACK_LAT_POS) +#define SF_CTRL_SF_IF_0_ACK_LAT_UMSK (~(((1U << SF_CTRL_SF_IF_0_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_0_ACK_LAT_POS)) +#define SF_CTRL_SF_IF_REG_HOLD SF_CTRL_SF_IF_REG_HOLD +#define SF_CTRL_SF_IF_REG_HOLD_POS (24U) +#define SF_CTRL_SF_IF_REG_HOLD_LEN (1U) +#define SF_CTRL_SF_IF_REG_HOLD_MSK (((1U << SF_CTRL_SF_IF_REG_HOLD_LEN) - 1) << SF_CTRL_SF_IF_REG_HOLD_POS) +#define SF_CTRL_SF_IF_REG_HOLD_UMSK (~(((1U << SF_CTRL_SF_IF_REG_HOLD_LEN) - 1) << SF_CTRL_SF_IF_REG_HOLD_POS)) +#define SF_CTRL_SF_IF_REG_WP SF_CTRL_SF_IF_REG_WP +#define SF_CTRL_SF_IF_REG_WP_POS (25U) +#define SF_CTRL_SF_IF_REG_WP_LEN (1U) +#define SF_CTRL_SF_IF_REG_WP_MSK (((1U << SF_CTRL_SF_IF_REG_WP_LEN) - 1) << SF_CTRL_SF_IF_REG_WP_POS) +#define SF_CTRL_SF_IF_REG_WP_UMSK (~(((1U << SF_CTRL_SF_IF_REG_WP_LEN) - 1) << SF_CTRL_SF_IF_REG_WP_POS)) +#define SF_CTRL_SF_AHB2SIF_STOPPED SF_CTRL_SF_AHB2SIF_STOPPED +#define SF_CTRL_SF_AHB2SIF_STOPPED_POS (26U) +#define SF_CTRL_SF_AHB2SIF_STOPPED_LEN (1U) +#define SF_CTRL_SF_AHB2SIF_STOPPED_MSK (((1U << SF_CTRL_SF_AHB2SIF_STOPPED_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOPPED_POS) +#define SF_CTRL_SF_AHB2SIF_STOPPED_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_STOPPED_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOPPED_POS)) +#define SF_CTRL_SF_AHB2SIF_STOP SF_CTRL_SF_AHB2SIF_STOP +#define SF_CTRL_SF_AHB2SIF_STOP_POS (27U) +#define SF_CTRL_SF_AHB2SIF_STOP_LEN (1U) +#define SF_CTRL_SF_AHB2SIF_STOP_MSK (((1U << SF_CTRL_SF_AHB2SIF_STOP_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOP_POS) +#define SF_CTRL_SF_AHB2SIF_STOP_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_STOP_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOP_POS)) +#define SF_CTRL_SF_IF_FN_SEL SF_CTRL_SF_IF_FN_SEL +#define SF_CTRL_SF_IF_FN_SEL_POS (28U) +#define SF_CTRL_SF_IF_FN_SEL_LEN (1U) +#define SF_CTRL_SF_IF_FN_SEL_MSK (((1U << SF_CTRL_SF_IF_FN_SEL_LEN) - 1) << SF_CTRL_SF_IF_FN_SEL_POS) +#define SF_CTRL_SF_IF_FN_SEL_UMSK (~(((1U << SF_CTRL_SF_IF_FN_SEL_LEN) - 1) << SF_CTRL_SF_IF_FN_SEL_POS)) +#define SF_CTRL_SF_IF_EN SF_CTRL_SF_IF_EN +#define SF_CTRL_SF_IF_EN_POS (29U) +#define SF_CTRL_SF_IF_EN_LEN (1U) +#define SF_CTRL_SF_IF_EN_MSK (((1U << SF_CTRL_SF_IF_EN_LEN) - 1) << SF_CTRL_SF_IF_EN_POS) +#define SF_CTRL_SF_IF_EN_UMSK (~(((1U << SF_CTRL_SF_IF_EN_LEN) - 1) << SF_CTRL_SF_IF_EN_POS)) +#define SF_CTRL_SF_AHB2SIF_EN SF_CTRL_SF_AHB2SIF_EN +#define SF_CTRL_SF_AHB2SIF_EN_POS (30U) +#define SF_CTRL_SF_AHB2SIF_EN_LEN (1U) +#define SF_CTRL_SF_AHB2SIF_EN_MSK (((1U << SF_CTRL_SF_AHB2SIF_EN_LEN) - 1) << SF_CTRL_SF_AHB2SIF_EN_POS) +#define SF_CTRL_SF_AHB2SIF_EN_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_EN_LEN) - 1) << SF_CTRL_SF_AHB2SIF_EN_POS)) +#define SF_CTRL_SF_AHB2SRAM_EN SF_CTRL_SF_AHB2SRAM_EN +#define SF_CTRL_SF_AHB2SRAM_EN_POS (31U) +#define SF_CTRL_SF_AHB2SRAM_EN_LEN (1U) +#define SF_CTRL_SF_AHB2SRAM_EN_MSK (((1U << SF_CTRL_SF_AHB2SRAM_EN_LEN) - 1) << SF_CTRL_SF_AHB2SRAM_EN_POS) +#define SF_CTRL_SF_AHB2SRAM_EN_UMSK (~(((1U << SF_CTRL_SF_AHB2SRAM_EN_LEN) - 1) << SF_CTRL_SF_AHB2SRAM_EN_POS)) + +/* 0x8 : sf_if_sahb_0 */ +#define SF_CTRL_SF_IF_SAHB_0_OFFSET (0x8) +#define SF_CTRL_SF_IF_BUSY SF_CTRL_SF_IF_BUSY +#define SF_CTRL_SF_IF_BUSY_POS (0U) +#define SF_CTRL_SF_IF_BUSY_LEN (1U) +#define SF_CTRL_SF_IF_BUSY_MSK (((1U << SF_CTRL_SF_IF_BUSY_LEN) - 1) << SF_CTRL_SF_IF_BUSY_POS) +#define SF_CTRL_SF_IF_BUSY_UMSK (~(((1U << SF_CTRL_SF_IF_BUSY_LEN) - 1) << SF_CTRL_SF_IF_BUSY_POS)) +#define SF_CTRL_SF_IF_0_TRIG SF_CTRL_SF_IF_0_TRIG +#define SF_CTRL_SF_IF_0_TRIG_POS (1U) +#define SF_CTRL_SF_IF_0_TRIG_LEN (1U) +#define SF_CTRL_SF_IF_0_TRIG_MSK (((1U << SF_CTRL_SF_IF_0_TRIG_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_POS) +#define SF_CTRL_SF_IF_0_TRIG_UMSK (~(((1U << SF_CTRL_SF_IF_0_TRIG_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_POS)) +#define SF_CTRL_SF_IF_0_DAT_BYTE SF_CTRL_SF_IF_0_DAT_BYTE +#define SF_CTRL_SF_IF_0_DAT_BYTE_POS (2U) +#define SF_CTRL_SF_IF_0_DAT_BYTE_LEN (10U) +#define SF_CTRL_SF_IF_0_DAT_BYTE_MSK (((1U << SF_CTRL_SF_IF_0_DAT_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_BYTE_POS) +#define SF_CTRL_SF_IF_0_DAT_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_0_DAT_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_BYTE_POS)) +#define SF_CTRL_SF_IF_0_DMY_BYTE SF_CTRL_SF_IF_0_DMY_BYTE +#define SF_CTRL_SF_IF_0_DMY_BYTE_POS (12U) +#define SF_CTRL_SF_IF_0_DMY_BYTE_LEN (5U) +#define SF_CTRL_SF_IF_0_DMY_BYTE_MSK (((1U << SF_CTRL_SF_IF_0_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_BYTE_POS) +#define SF_CTRL_SF_IF_0_DMY_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_0_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_BYTE_POS)) +#define SF_CTRL_SF_IF_0_ADR_BYTE SF_CTRL_SF_IF_0_ADR_BYTE +#define SF_CTRL_SF_IF_0_ADR_BYTE_POS (17U) +#define SF_CTRL_SF_IF_0_ADR_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_0_ADR_BYTE_MSK (((1U << SF_CTRL_SF_IF_0_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_BYTE_POS) +#define SF_CTRL_SF_IF_0_ADR_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_0_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_BYTE_POS)) +#define SF_CTRL_SF_IF_0_CMD_BYTE SF_CTRL_SF_IF_0_CMD_BYTE +#define SF_CTRL_SF_IF_0_CMD_BYTE_POS (20U) +#define SF_CTRL_SF_IF_0_CMD_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_0_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF_0_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BYTE_POS) +#define SF_CTRL_SF_IF_0_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BYTE_POS)) +#define SF_CTRL_SF_IF_0_DAT_RW SF_CTRL_SF_IF_0_DAT_RW +#define SF_CTRL_SF_IF_0_DAT_RW_POS (23U) +#define SF_CTRL_SF_IF_0_DAT_RW_LEN (1U) +#define SF_CTRL_SF_IF_0_DAT_RW_MSK (((1U << SF_CTRL_SF_IF_0_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_RW_POS) +#define SF_CTRL_SF_IF_0_DAT_RW_UMSK (~(((1U << SF_CTRL_SF_IF_0_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_RW_POS)) +#define SF_CTRL_SF_IF_0_DAT_EN SF_CTRL_SF_IF_0_DAT_EN +#define SF_CTRL_SF_IF_0_DAT_EN_POS (24U) +#define SF_CTRL_SF_IF_0_DAT_EN_LEN (1U) +#define SF_CTRL_SF_IF_0_DAT_EN_MSK (((1U << SF_CTRL_SF_IF_0_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_EN_POS) +#define SF_CTRL_SF_IF_0_DAT_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_EN_POS)) +#define SF_CTRL_SF_IF_0_DMY_EN SF_CTRL_SF_IF_0_DMY_EN +#define SF_CTRL_SF_IF_0_DMY_EN_POS (25U) +#define SF_CTRL_SF_IF_0_DMY_EN_LEN (1U) +#define SF_CTRL_SF_IF_0_DMY_EN_MSK (((1U << SF_CTRL_SF_IF_0_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_EN_POS) +#define SF_CTRL_SF_IF_0_DMY_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_EN_POS)) +#define SF_CTRL_SF_IF_0_ADR_EN SF_CTRL_SF_IF_0_ADR_EN +#define SF_CTRL_SF_IF_0_ADR_EN_POS (26U) +#define SF_CTRL_SF_IF_0_ADR_EN_LEN (1U) +#define SF_CTRL_SF_IF_0_ADR_EN_MSK (((1U << SF_CTRL_SF_IF_0_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_EN_POS) +#define SF_CTRL_SF_IF_0_ADR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_EN_POS)) +#define SF_CTRL_SF_IF_0_CMD_EN SF_CTRL_SF_IF_0_CMD_EN +#define SF_CTRL_SF_IF_0_CMD_EN_POS (27U) +#define SF_CTRL_SF_IF_0_CMD_EN_LEN (1U) +#define SF_CTRL_SF_IF_0_CMD_EN_MSK (((1U << SF_CTRL_SF_IF_0_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_EN_POS) +#define SF_CTRL_SF_IF_0_CMD_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_EN_POS)) +#define SF_CTRL_SF_IF_0_SPI_MODE SF_CTRL_SF_IF_0_SPI_MODE +#define SF_CTRL_SF_IF_0_SPI_MODE_POS (28U) +#define SF_CTRL_SF_IF_0_SPI_MODE_LEN (3U) +#define SF_CTRL_SF_IF_0_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF_0_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_0_SPI_MODE_POS) +#define SF_CTRL_SF_IF_0_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_0_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_0_SPI_MODE_POS)) +#define SF_CTRL_SF_IF_0_QPI_MODE_EN SF_CTRL_SF_IF_0_QPI_MODE_EN +#define SF_CTRL_SF_IF_0_QPI_MODE_EN_POS (31U) +#define SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN (1U) +#define SF_CTRL_SF_IF_0_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_0_QPI_MODE_EN_POS) +#define SF_CTRL_SF_IF_0_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_0_QPI_MODE_EN_POS)) + +/* 0xC : sf_if_sahb_1 */ +#define SF_CTRL_SF_IF_SAHB_1_OFFSET (0xC) +#define SF_CTRL_SF_IF_0_CMD_BUF_0 SF_CTRL_SF_IF_0_CMD_BUF_0 +#define SF_CTRL_SF_IF_0_CMD_BUF_0_POS (0U) +#define SF_CTRL_SF_IF_0_CMD_BUF_0_LEN (32U) +#define SF_CTRL_SF_IF_0_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF_0_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_0_POS) +#define SF_CTRL_SF_IF_0_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_0_POS)) + +/* 0x10 : sf_if_sahb_2 */ +#define SF_CTRL_SF_IF_SAHB_2_OFFSET (0x10) +#define SF_CTRL_SF_IF_0_CMD_BUF_1 SF_CTRL_SF_IF_0_CMD_BUF_1 +#define SF_CTRL_SF_IF_0_CMD_BUF_1_POS (0U) +#define SF_CTRL_SF_IF_0_CMD_BUF_1_LEN (32U) +#define SF_CTRL_SF_IF_0_CMD_BUF_1_MSK (((1U << SF_CTRL_SF_IF_0_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_1_POS) +#define SF_CTRL_SF_IF_0_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_1_POS)) + +/* 0x14 : sf_if_iahb_0 */ +#define SF_CTRL_SF_IF_IAHB_0_OFFSET (0x14) +#define SF_CTRL_SF_IF_1_DMY_BYTE SF_CTRL_SF_IF_1_DMY_BYTE +#define SF_CTRL_SF_IF_1_DMY_BYTE_POS (12U) +#define SF_CTRL_SF_IF_1_DMY_BYTE_LEN (5U) +#define SF_CTRL_SF_IF_1_DMY_BYTE_MSK (((1U << SF_CTRL_SF_IF_1_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_BYTE_POS) +#define SF_CTRL_SF_IF_1_DMY_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_1_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_BYTE_POS)) +#define SF_CTRL_SF_IF_1_ADR_BYTE SF_CTRL_SF_IF_1_ADR_BYTE +#define SF_CTRL_SF_IF_1_ADR_BYTE_POS (17U) +#define SF_CTRL_SF_IF_1_ADR_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_1_ADR_BYTE_MSK (((1U << SF_CTRL_SF_IF_1_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_BYTE_POS) +#define SF_CTRL_SF_IF_1_ADR_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_1_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_BYTE_POS)) +#define SF_CTRL_SF_IF_1_CMD_BYTE SF_CTRL_SF_IF_1_CMD_BYTE +#define SF_CTRL_SF_IF_1_CMD_BYTE_POS (20U) +#define SF_CTRL_SF_IF_1_CMD_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_1_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF_1_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BYTE_POS) +#define SF_CTRL_SF_IF_1_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BYTE_POS)) +#define SF_CTRL_SF_IF_1_DAT_RW SF_CTRL_SF_IF_1_DAT_RW +#define SF_CTRL_SF_IF_1_DAT_RW_POS (23U) +#define SF_CTRL_SF_IF_1_DAT_RW_LEN (1U) +#define SF_CTRL_SF_IF_1_DAT_RW_MSK (((1U << SF_CTRL_SF_IF_1_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_RW_POS) +#define SF_CTRL_SF_IF_1_DAT_RW_UMSK (~(((1U << SF_CTRL_SF_IF_1_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_RW_POS)) +#define SF_CTRL_SF_IF_1_DAT_EN SF_CTRL_SF_IF_1_DAT_EN +#define SF_CTRL_SF_IF_1_DAT_EN_POS (24U) +#define SF_CTRL_SF_IF_1_DAT_EN_LEN (1U) +#define SF_CTRL_SF_IF_1_DAT_EN_MSK (((1U << SF_CTRL_SF_IF_1_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_EN_POS) +#define SF_CTRL_SF_IF_1_DAT_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_EN_POS)) +#define SF_CTRL_SF_IF_1_DMY_EN SF_CTRL_SF_IF_1_DMY_EN +#define SF_CTRL_SF_IF_1_DMY_EN_POS (25U) +#define SF_CTRL_SF_IF_1_DMY_EN_LEN (1U) +#define SF_CTRL_SF_IF_1_DMY_EN_MSK (((1U << SF_CTRL_SF_IF_1_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_EN_POS) +#define SF_CTRL_SF_IF_1_DMY_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_EN_POS)) +#define SF_CTRL_SF_IF_1_ADR_EN SF_CTRL_SF_IF_1_ADR_EN +#define SF_CTRL_SF_IF_1_ADR_EN_POS (26U) +#define SF_CTRL_SF_IF_1_ADR_EN_LEN (1U) +#define SF_CTRL_SF_IF_1_ADR_EN_MSK (((1U << SF_CTRL_SF_IF_1_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_EN_POS) +#define SF_CTRL_SF_IF_1_ADR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_EN_POS)) +#define SF_CTRL_SF_IF_1_CMD_EN SF_CTRL_SF_IF_1_CMD_EN +#define SF_CTRL_SF_IF_1_CMD_EN_POS (27U) +#define SF_CTRL_SF_IF_1_CMD_EN_LEN (1U) +#define SF_CTRL_SF_IF_1_CMD_EN_MSK (((1U << SF_CTRL_SF_IF_1_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_EN_POS) +#define SF_CTRL_SF_IF_1_CMD_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_EN_POS)) +#define SF_CTRL_SF_IF_1_SPI_MODE SF_CTRL_SF_IF_1_SPI_MODE +#define SF_CTRL_SF_IF_1_SPI_MODE_POS (28U) +#define SF_CTRL_SF_IF_1_SPI_MODE_LEN (3U) +#define SF_CTRL_SF_IF_1_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF_1_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_1_SPI_MODE_POS) +#define SF_CTRL_SF_IF_1_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_1_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_1_SPI_MODE_POS)) +#define SF_CTRL_SF_IF_1_QPI_MODE_EN SF_CTRL_SF_IF_1_QPI_MODE_EN +#define SF_CTRL_SF_IF_1_QPI_MODE_EN_POS (31U) +#define SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN (1U) +#define SF_CTRL_SF_IF_1_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_1_QPI_MODE_EN_POS) +#define SF_CTRL_SF_IF_1_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_1_QPI_MODE_EN_POS)) + +/* 0x18 : sf_if_iahb_1 */ +#define SF_CTRL_SF_IF_IAHB_1_OFFSET (0x18) +#define SF_CTRL_SF_IF_1_CMD_BUF_0 SF_CTRL_SF_IF_1_CMD_BUF_0 +#define SF_CTRL_SF_IF_1_CMD_BUF_0_POS (0U) +#define SF_CTRL_SF_IF_1_CMD_BUF_0_LEN (32U) +#define SF_CTRL_SF_IF_1_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF_1_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_0_POS) +#define SF_CTRL_SF_IF_1_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_0_POS)) + +/* 0x1C : sf_if_iahb_2 */ +#define SF_CTRL_SF_IF_IAHB_2_OFFSET (0x1C) +#define SF_CTRL_SF_IF_1_CMD_BUF_1 SF_CTRL_SF_IF_1_CMD_BUF_1 +#define SF_CTRL_SF_IF_1_CMD_BUF_1_POS (0U) +#define SF_CTRL_SF_IF_1_CMD_BUF_1_LEN (32U) +#define SF_CTRL_SF_IF_1_CMD_BUF_1_MSK (((1U << SF_CTRL_SF_IF_1_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_1_POS) +#define SF_CTRL_SF_IF_1_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_1_POS)) + +/* 0x20 : sf_if_status_0 */ +#define SF_CTRL_SF_IF_STATUS_0_OFFSET (0x20) +#define SF_CTRL_SF_IF_STATUS_0 SF_CTRL_SF_IF_STATUS_0 +#define SF_CTRL_SF_IF_STATUS_0_POS (0U) +#define SF_CTRL_SF_IF_STATUS_0_LEN (32U) +#define SF_CTRL_SF_IF_STATUS_0_MSK (((1U << SF_CTRL_SF_IF_STATUS_0_LEN) - 1) << SF_CTRL_SF_IF_STATUS_0_POS) +#define SF_CTRL_SF_IF_STATUS_0_UMSK (~(((1U << SF_CTRL_SF_IF_STATUS_0_LEN) - 1) << SF_CTRL_SF_IF_STATUS_0_POS)) + +/* 0x24 : sf_if_status_1 */ +#define SF_CTRL_SF_IF_STATUS_1_OFFSET (0x24) +#define SF_CTRL_SF_IF_STATUS_1 SF_CTRL_SF_IF_STATUS_1 +#define SF_CTRL_SF_IF_STATUS_1_POS (0U) +#define SF_CTRL_SF_IF_STATUS_1_LEN (32U) +#define SF_CTRL_SF_IF_STATUS_1_MSK (((1U << SF_CTRL_SF_IF_STATUS_1_LEN) - 1) << SF_CTRL_SF_IF_STATUS_1_POS) +#define SF_CTRL_SF_IF_STATUS_1_UMSK (~(((1U << SF_CTRL_SF_IF_STATUS_1_LEN) - 1) << SF_CTRL_SF_IF_STATUS_1_POS)) + +/* 0x28 : sf_aes */ +#define SF_CTRL_SF_AES_OFFSET (0x28) +#define SF_CTRL_SF_AES_EN SF_CTRL_SF_AES_EN +#define SF_CTRL_SF_AES_EN_POS (0U) +#define SF_CTRL_SF_AES_EN_LEN (1U) +#define SF_CTRL_SF_AES_EN_MSK (((1U << SF_CTRL_SF_AES_EN_LEN) - 1) << SF_CTRL_SF_AES_EN_POS) +#define SF_CTRL_SF_AES_EN_UMSK (~(((1U << SF_CTRL_SF_AES_EN_LEN) - 1) << SF_CTRL_SF_AES_EN_POS)) +#define SF_CTRL_SF_AES_MODE SF_CTRL_SF_AES_MODE +#define SF_CTRL_SF_AES_MODE_POS (1U) +#define SF_CTRL_SF_AES_MODE_LEN (2U) +#define SF_CTRL_SF_AES_MODE_MSK (((1U << SF_CTRL_SF_AES_MODE_LEN) - 1) << SF_CTRL_SF_AES_MODE_POS) +#define SF_CTRL_SF_AES_MODE_UMSK (~(((1U << SF_CTRL_SF_AES_MODE_LEN) - 1) << SF_CTRL_SF_AES_MODE_POS)) +#define SF_CTRL_SF_AES_PREF_TRIG SF_CTRL_SF_AES_PREF_TRIG +#define SF_CTRL_SF_AES_PREF_TRIG_POS (3U) +#define SF_CTRL_SF_AES_PREF_TRIG_LEN (1U) +#define SF_CTRL_SF_AES_PREF_TRIG_MSK (((1U << SF_CTRL_SF_AES_PREF_TRIG_LEN) - 1) << SF_CTRL_SF_AES_PREF_TRIG_POS) +#define SF_CTRL_SF_AES_PREF_TRIG_UMSK (~(((1U << SF_CTRL_SF_AES_PREF_TRIG_LEN) - 1) << SF_CTRL_SF_AES_PREF_TRIG_POS)) +#define SF_CTRL_SF_AES_PREF_BUSY SF_CTRL_SF_AES_PREF_BUSY +#define SF_CTRL_SF_AES_PREF_BUSY_POS (4U) +#define SF_CTRL_SF_AES_PREF_BUSY_LEN (1U) +#define SF_CTRL_SF_AES_PREF_BUSY_MSK (((1U << SF_CTRL_SF_AES_PREF_BUSY_LEN) - 1) << SF_CTRL_SF_AES_PREF_BUSY_POS) +#define SF_CTRL_SF_AES_PREF_BUSY_UMSK (~(((1U << SF_CTRL_SF_AES_PREF_BUSY_LEN) - 1) << SF_CTRL_SF_AES_PREF_BUSY_POS)) +#define SF_CTRL_SF_AES_STATUS SF_CTRL_SF_AES_STATUS +#define SF_CTRL_SF_AES_STATUS_POS (5U) +#define SF_CTRL_SF_AES_STATUS_LEN (27U) +#define SF_CTRL_SF_AES_STATUS_MSK (((1U << SF_CTRL_SF_AES_STATUS_LEN) - 1) << SF_CTRL_SF_AES_STATUS_POS) +#define SF_CTRL_SF_AES_STATUS_UMSK (~(((1U << SF_CTRL_SF_AES_STATUS_LEN) - 1) << SF_CTRL_SF_AES_STATUS_POS)) + +/* 0x2C : sf_ahb2sif_status */ +#define SF_CTRL_SF_AHB2SIF_STATUS_OFFSET (0x2C) +#define SF_CTRL_SF_AHB2SIF_STATUS SF_CTRL_SF_AHB2SIF_STATUS +#define SF_CTRL_SF_AHB2SIF_STATUS_POS (0U) +#define SF_CTRL_SF_AHB2SIF_STATUS_LEN (32U) +#define SF_CTRL_SF_AHB2SIF_STATUS_MSK (((1U << SF_CTRL_SF_AHB2SIF_STATUS_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STATUS_POS) +#define SF_CTRL_SF_AHB2SIF_STATUS_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_STATUS_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STATUS_POS)) + +/* 0x30 : sf_if_io_dly_0 */ +#define SF_CTRL_SF_IF_IO_DLY_0_OFFSET (0x30) +#define SF_CTRL_SF_CS_DLY_SEL SF_CTRL_SF_CS_DLY_SEL +#define SF_CTRL_SF_CS_DLY_SEL_POS (0U) +#define SF_CTRL_SF_CS_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_CS_DLY_SEL_MSK (((1U << SF_CTRL_SF_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS_DLY_SEL_POS) +#define SF_CTRL_SF_CS_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS_DLY_SEL_POS)) +#define SF_CTRL_SF_CLK_OUT_DLY_SEL SF_CTRL_SF_CLK_OUT_DLY_SEL +#define SF_CTRL_SF_CLK_OUT_DLY_SEL_POS (8U) +#define SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_CLK_OUT_DLY_SEL_MSK (((1U << SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_DLY_SEL_POS) +#define SF_CTRL_SF_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_DLY_SEL_POS)) +#define SF_CTRL_SF_DQS_OE_DLY_SEL SF_CTRL_SF_DQS_OE_DLY_SEL +#define SF_CTRL_SF_DQS_OE_DLY_SEL_POS (26U) +#define SF_CTRL_SF_DQS_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_DQS_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_OE_DLY_SEL_POS) +#define SF_CTRL_SF_DQS_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_OE_DLY_SEL_POS)) +#define SF_CTRL_SF_DQS_DI_DLY_SEL SF_CTRL_SF_DQS_DI_DLY_SEL +#define SF_CTRL_SF_DQS_DI_DLY_SEL_POS (28U) +#define SF_CTRL_SF_DQS_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_DQS_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DI_DLY_SEL_POS) +#define SF_CTRL_SF_DQS_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DI_DLY_SEL_POS)) +#define SF_CTRL_SF_DQS_DO_DLY_SEL SF_CTRL_SF_DQS_DO_DLY_SEL +#define SF_CTRL_SF_DQS_DO_DLY_SEL_POS (30U) +#define SF_CTRL_SF_DQS_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_DQS_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DO_DLY_SEL_POS) +#define SF_CTRL_SF_DQS_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DO_DLY_SEL_POS)) + +/* 0x34 : sf_if_io_dly_1 */ +#define SF_CTRL_SF_IF_IO_DLY_1_OFFSET (0x34) +#define SF_CTRL_SF_IO_0_OE_DLY_SEL SF_CTRL_SF_IO_0_OE_DLY_SEL +#define SF_CTRL_SF_IO_0_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_0_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_OE_DLY_SEL_POS) +#define SF_CTRL_SF_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_OE_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_0_DI_DLY_SEL SF_CTRL_SF_IO_0_DI_DLY_SEL +#define SF_CTRL_SF_IO_0_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_0_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DI_DLY_SEL_POS) +#define SF_CTRL_SF_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DI_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_0_DO_DLY_SEL SF_CTRL_SF_IO_0_DO_DLY_SEL +#define SF_CTRL_SF_IO_0_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_0_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DO_DLY_SEL_POS) +#define SF_CTRL_SF_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DO_DLY_SEL_POS)) + +/* 0x38 : sf_if_io_dly_2 */ +#define SF_CTRL_SF_IF_IO_DLY_2_OFFSET (0x38) +#define SF_CTRL_SF_IO_1_OE_DLY_SEL SF_CTRL_SF_IO_1_OE_DLY_SEL +#define SF_CTRL_SF_IO_1_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_1_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_OE_DLY_SEL_POS) +#define SF_CTRL_SF_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_OE_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_1_DI_DLY_SEL SF_CTRL_SF_IO_1_DI_DLY_SEL +#define SF_CTRL_SF_IO_1_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_1_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DI_DLY_SEL_POS) +#define SF_CTRL_SF_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DI_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_1_DO_DLY_SEL SF_CTRL_SF_IO_1_DO_DLY_SEL +#define SF_CTRL_SF_IO_1_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_1_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DO_DLY_SEL_POS) +#define SF_CTRL_SF_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DO_DLY_SEL_POS)) + +/* 0x3C : sf_if_io_dly_3 */ +#define SF_CTRL_SF_IF_IO_DLY_3_OFFSET (0x3C) +#define SF_CTRL_SF_IO_2_OE_DLY_SEL SF_CTRL_SF_IO_2_OE_DLY_SEL +#define SF_CTRL_SF_IO_2_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_2_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_OE_DLY_SEL_POS) +#define SF_CTRL_SF_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_OE_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_2_DI_DLY_SEL SF_CTRL_SF_IO_2_DI_DLY_SEL +#define SF_CTRL_SF_IO_2_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_2_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DI_DLY_SEL_POS) +#define SF_CTRL_SF_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DI_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_2_DO_DLY_SEL SF_CTRL_SF_IO_2_DO_DLY_SEL +#define SF_CTRL_SF_IO_2_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_2_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DO_DLY_SEL_POS) +#define SF_CTRL_SF_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DO_DLY_SEL_POS)) + +/* 0x40 : sf_if_io_dly_4 */ +#define SF_CTRL_SF_IF_IO_DLY_4_OFFSET (0x40) +#define SF_CTRL_SF_IO_3_OE_DLY_SEL SF_CTRL_SF_IO_3_OE_DLY_SEL +#define SF_CTRL_SF_IO_3_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_3_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_OE_DLY_SEL_POS) +#define SF_CTRL_SF_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_OE_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_3_DI_DLY_SEL SF_CTRL_SF_IO_3_DI_DLY_SEL +#define SF_CTRL_SF_IO_3_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_3_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DI_DLY_SEL_POS) +#define SF_CTRL_SF_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DI_DLY_SEL_POS)) +#define SF_CTRL_SF_IO_3_DO_DLY_SEL SF_CTRL_SF_IO_3_DO_DLY_SEL +#define SF_CTRL_SF_IO_3_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF_IO_3_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DO_DLY_SEL_POS) +#define SF_CTRL_SF_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DO_DLY_SEL_POS)) + +/* 0x44 : sf_reserved */ +#define SF_CTRL_SF_RESERVED_OFFSET (0x44) +#define SF_CTRL_SF_RESERVED SF_CTRL_SF_RESERVED +#define SF_CTRL_SF_RESERVED_POS (0U) +#define SF_CTRL_SF_RESERVED_LEN (32U) +#define SF_CTRL_SF_RESERVED_MSK (((1U << SF_CTRL_SF_RESERVED_LEN) - 1) << SF_CTRL_SF_RESERVED_POS) +#define SF_CTRL_SF_RESERVED_UMSK (~(((1U << SF_CTRL_SF_RESERVED_LEN) - 1) << SF_CTRL_SF_RESERVED_POS)) + +/* 0x48 : sf2_if_io_dly_0 */ +#define SF_CTRL_SF2_IF_IO_DLY_0_OFFSET (0x48) +#define SF_CTRL_SF2_CS_DLY_SEL SF_CTRL_SF2_CS_DLY_SEL +#define SF_CTRL_SF2_CS_DLY_SEL_POS (0U) +#define SF_CTRL_SF2_CS_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_CS_DLY_SEL_MSK (((1U << SF_CTRL_SF2_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS_DLY_SEL_POS) +#define SF_CTRL_SF2_CS_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS_DLY_SEL_POS)) +#define SF_CTRL_SF2_CLK_OUT_DLY_SEL SF_CTRL_SF2_CLK_OUT_DLY_SEL +#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS (8U) +#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_MSK (((1U << SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS) +#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS)) +#define SF_CTRL_SF2_DQS_OE_DLY_SEL SF_CTRL_SF2_DQS_OE_DLY_SEL +#define SF_CTRL_SF2_DQS_OE_DLY_SEL_POS (26U) +#define SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_DQS_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_OE_DLY_SEL_POS) +#define SF_CTRL_SF2_DQS_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_OE_DLY_SEL_POS)) +#define SF_CTRL_SF2_DQS_DI_DLY_SEL SF_CTRL_SF2_DQS_DI_DLY_SEL +#define SF_CTRL_SF2_DQS_DI_DLY_SEL_POS (28U) +#define SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_DQS_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DI_DLY_SEL_POS) +#define SF_CTRL_SF2_DQS_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DI_DLY_SEL_POS)) +#define SF_CTRL_SF2_DQS_DO_DLY_SEL SF_CTRL_SF2_DQS_DO_DLY_SEL +#define SF_CTRL_SF2_DQS_DO_DLY_SEL_POS (30U) +#define SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_DQS_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DO_DLY_SEL_POS) +#define SF_CTRL_SF2_DQS_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DO_DLY_SEL_POS)) + +/* 0x4C : sf2_if_io_dly_1 */ +#define SF_CTRL_SF2_IF_IO_DLY_1_OFFSET (0x4C) +#define SF_CTRL_SF2_IO_0_OE_DLY_SEL SF_CTRL_SF2_IO_0_OE_DLY_SEL +#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_0_DI_DLY_SEL SF_CTRL_SF2_IO_0_DI_DLY_SEL +#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_0_DO_DLY_SEL SF_CTRL_SF2_IO_0_DO_DLY_SEL +#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS)) + +/* 0x50 : sf2_if_io_dly_2 */ +#define SF_CTRL_SF2_IF_IO_DLY_2_OFFSET (0x50) +#define SF_CTRL_SF2_IO_1_OE_DLY_SEL SF_CTRL_SF2_IO_1_OE_DLY_SEL +#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_1_DI_DLY_SEL SF_CTRL_SF2_IO_1_DI_DLY_SEL +#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_1_DO_DLY_SEL SF_CTRL_SF2_IO_1_DO_DLY_SEL +#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS)) + +/* 0x54 : sf2_if_io_dly_3 */ +#define SF_CTRL_SF2_IF_IO_DLY_3_OFFSET (0x54) +#define SF_CTRL_SF2_IO_2_OE_DLY_SEL SF_CTRL_SF2_IO_2_OE_DLY_SEL +#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_2_DI_DLY_SEL SF_CTRL_SF2_IO_2_DI_DLY_SEL +#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_2_DO_DLY_SEL SF_CTRL_SF2_IO_2_DO_DLY_SEL +#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS)) + +/* 0x58 : sf2_if_io_dly_4 */ +#define SF_CTRL_SF2_IF_IO_DLY_4_OFFSET (0x58) +#define SF_CTRL_SF2_IO_3_OE_DLY_SEL SF_CTRL_SF2_IO_3_OE_DLY_SEL +#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_3_DI_DLY_SEL SF_CTRL_SF2_IO_3_DI_DLY_SEL +#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS)) +#define SF_CTRL_SF2_IO_3_DO_DLY_SEL SF_CTRL_SF2_IO_3_DO_DLY_SEL +#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS) +#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS)) + +/* 0x5C : sf3_if_io_dly_0 */ +#define SF_CTRL_SF3_IF_IO_DLY_0_OFFSET (0x5C) +#define SF_CTRL_SF3_CS_DLY_SEL SF_CTRL_SF3_CS_DLY_SEL +#define SF_CTRL_SF3_CS_DLY_SEL_POS (0U) +#define SF_CTRL_SF3_CS_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_CS_DLY_SEL_MSK (((1U << SF_CTRL_SF3_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS_DLY_SEL_POS) +#define SF_CTRL_SF3_CS_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS_DLY_SEL_POS)) +#define SF_CTRL_SF3_CLK_OUT_DLY_SEL SF_CTRL_SF3_CLK_OUT_DLY_SEL +#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS (8U) +#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_MSK (((1U << SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS) +#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS)) +#define SF_CTRL_SF3_DQS_OE_DLY_SEL SF_CTRL_SF3_DQS_OE_DLY_SEL +#define SF_CTRL_SF3_DQS_OE_DLY_SEL_POS (26U) +#define SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_DQS_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_OE_DLY_SEL_POS) +#define SF_CTRL_SF3_DQS_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_OE_DLY_SEL_POS)) +#define SF_CTRL_SF3_DQS_DI_DLY_SEL SF_CTRL_SF3_DQS_DI_DLY_SEL +#define SF_CTRL_SF3_DQS_DI_DLY_SEL_POS (28U) +#define SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_DQS_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DI_DLY_SEL_POS) +#define SF_CTRL_SF3_DQS_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DI_DLY_SEL_POS)) +#define SF_CTRL_SF3_DQS_DO_DLY_SEL SF_CTRL_SF3_DQS_DO_DLY_SEL +#define SF_CTRL_SF3_DQS_DO_DLY_SEL_POS (30U) +#define SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_DQS_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DO_DLY_SEL_POS) +#define SF_CTRL_SF3_DQS_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DO_DLY_SEL_POS)) + +/* 0x60 : sf3_if_io_dly_1 */ +#define SF_CTRL_SF3_IF_IO_DLY_1_OFFSET (0x60) +#define SF_CTRL_SF3_IO_0_OE_DLY_SEL SF_CTRL_SF3_IO_0_OE_DLY_SEL +#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_0_DI_DLY_SEL SF_CTRL_SF3_IO_0_DI_DLY_SEL +#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_0_DO_DLY_SEL SF_CTRL_SF3_IO_0_DO_DLY_SEL +#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS)) + +/* 0x64 : sf3_if_io_dly_2 */ +#define SF_CTRL_SF3_IF_IO_DLY_2_OFFSET (0x64) +#define SF_CTRL_SF3_IO_1_OE_DLY_SEL SF_CTRL_SF3_IO_1_OE_DLY_SEL +#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_1_DI_DLY_SEL SF_CTRL_SF3_IO_1_DI_DLY_SEL +#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_1_DO_DLY_SEL SF_CTRL_SF3_IO_1_DO_DLY_SEL +#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS)) + +/* 0x68 : sf3_if_io_dly_3 */ +#define SF_CTRL_SF3_IF_IO_DLY_3_OFFSET (0x68) +#define SF_CTRL_SF3_IO_2_OE_DLY_SEL SF_CTRL_SF3_IO_2_OE_DLY_SEL +#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_2_DI_DLY_SEL SF_CTRL_SF3_IO_2_DI_DLY_SEL +#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_2_DO_DLY_SEL SF_CTRL_SF3_IO_2_DO_DLY_SEL +#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS)) + +/* 0x6C : sf3_if_io_dly_4 */ +#define SF_CTRL_SF3_IF_IO_DLY_4_OFFSET (0x6C) +#define SF_CTRL_SF3_IO_3_OE_DLY_SEL SF_CTRL_SF3_IO_3_OE_DLY_SEL +#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS (0U) +#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_3_DI_DLY_SEL SF_CTRL_SF3_IO_3_DI_DLY_SEL +#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS (8U) +#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS)) +#define SF_CTRL_SF3_IO_3_DO_DLY_SEL SF_CTRL_SF3_IO_3_DO_DLY_SEL +#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS (16U) +#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN (2U) +#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS) +#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS)) + +/* 0x70 : sf_ctrl_2 */ +#define SF_CTRL_2_OFFSET (0x70) +#define SF_CTRL_SF_IF_PAD_SEL SF_CTRL_SF_IF_PAD_SEL +#define SF_CTRL_SF_IF_PAD_SEL_POS (0U) +#define SF_CTRL_SF_IF_PAD_SEL_LEN (2U) +#define SF_CTRL_SF_IF_PAD_SEL_MSK (((1U << SF_CTRL_SF_IF_PAD_SEL_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_POS) +#define SF_CTRL_SF_IF_PAD_SEL_UMSK (~(((1U << SF_CTRL_SF_IF_PAD_SEL_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_POS)) +#define SF_CTRL_SF_IF_PAD_SEL_LOCK SF_CTRL_SF_IF_PAD_SEL_LOCK +#define SF_CTRL_SF_IF_PAD_SEL_LOCK_POS (3U) +#define SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN (1U) +#define SF_CTRL_SF_IF_PAD_SEL_LOCK_MSK (((1U << SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_LOCK_POS) +#define SF_CTRL_SF_IF_PAD_SEL_LOCK_UMSK (~(((1U << SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_LOCK_POS)) +#define SF_CTRL_SF_IF_DTR_EN SF_CTRL_SF_IF_DTR_EN +#define SF_CTRL_SF_IF_DTR_EN_POS (4U) +#define SF_CTRL_SF_IF_DTR_EN_LEN (1U) +#define SF_CTRL_SF_IF_DTR_EN_MSK (((1U << SF_CTRL_SF_IF_DTR_EN_LEN) - 1) << SF_CTRL_SF_IF_DTR_EN_POS) +#define SF_CTRL_SF_IF_DTR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_DTR_EN_LEN) - 1) << SF_CTRL_SF_IF_DTR_EN_POS)) +#define SF_CTRL_SF_IF_DQS_EN SF_CTRL_SF_IF_DQS_EN +#define SF_CTRL_SF_IF_DQS_EN_POS (5U) +#define SF_CTRL_SF_IF_DQS_EN_LEN (1U) +#define SF_CTRL_SF_IF_DQS_EN_MSK (((1U << SF_CTRL_SF_IF_DQS_EN_LEN) - 1) << SF_CTRL_SF_IF_DQS_EN_POS) +#define SF_CTRL_SF_IF_DQS_EN_UMSK (~(((1U << SF_CTRL_SF_IF_DQS_EN_LEN) - 1) << SF_CTRL_SF_IF_DQS_EN_POS)) + +/* 0x74 : sf_ctrl_3 */ +#define SF_CTRL_3_OFFSET (0x74) +#define SF_CTRL_SF_CMDS_WRAP_LEN SF_CTRL_SF_CMDS_WRAP_LEN +#define SF_CTRL_SF_CMDS_WRAP_LEN_POS (0U) +#define SF_CTRL_SF_CMDS_WRAP_LEN_LEN (4U) +#define SF_CTRL_SF_CMDS_WRAP_LEN_MSK (((1U << SF_CTRL_SF_CMDS_WRAP_LEN_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_LEN_POS) +#define SF_CTRL_SF_CMDS_WRAP_LEN_UMSK (~(((1U << SF_CTRL_SF_CMDS_WRAP_LEN_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_LEN_POS)) +#define SF_CTRL_SF_CMDS_EN SF_CTRL_SF_CMDS_EN +#define SF_CTRL_SF_CMDS_EN_POS (4U) +#define SF_CTRL_SF_CMDS_EN_LEN (1U) +#define SF_CTRL_SF_CMDS_EN_MSK (((1U << SF_CTRL_SF_CMDS_EN_LEN) - 1) << SF_CTRL_SF_CMDS_EN_POS) +#define SF_CTRL_SF_CMDS_EN_UMSK (~(((1U << SF_CTRL_SF_CMDS_EN_LEN) - 1) << SF_CTRL_SF_CMDS_EN_POS)) +#define SF_CTRL_SF_CMDS_BT_DLY SF_CTRL_SF_CMDS_BT_DLY +#define SF_CTRL_SF_CMDS_BT_DLY_POS (5U) +#define SF_CTRL_SF_CMDS_BT_DLY_LEN (3U) +#define SF_CTRL_SF_CMDS_BT_DLY_MSK (((1U << SF_CTRL_SF_CMDS_BT_DLY_LEN) - 1) << SF_CTRL_SF_CMDS_BT_DLY_POS) +#define SF_CTRL_SF_CMDS_BT_DLY_UMSK (~(((1U << SF_CTRL_SF_CMDS_BT_DLY_LEN) - 1) << SF_CTRL_SF_CMDS_BT_DLY_POS)) +#define SF_CTRL_SF_CMDS_BT_EN SF_CTRL_SF_CMDS_BT_EN +#define SF_CTRL_SF_CMDS_BT_EN_POS (8U) +#define SF_CTRL_SF_CMDS_BT_EN_LEN (1U) +#define SF_CTRL_SF_CMDS_BT_EN_MSK (((1U << SF_CTRL_SF_CMDS_BT_EN_LEN) - 1) << SF_CTRL_SF_CMDS_BT_EN_POS) +#define SF_CTRL_SF_CMDS_BT_EN_UMSK (~(((1U << SF_CTRL_SF_CMDS_BT_EN_LEN) - 1) << SF_CTRL_SF_CMDS_BT_EN_POS)) +#define SF_CTRL_SF_CMDS_WRAP_Q_INI SF_CTRL_SF_CMDS_WRAP_Q_INI +#define SF_CTRL_SF_CMDS_WRAP_Q_INI_POS (9U) +#define SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN (1U) +#define SF_CTRL_SF_CMDS_WRAP_Q_INI_MSK (((1U << SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_INI_POS) +#define SF_CTRL_SF_CMDS_WRAP_Q_INI_UMSK (~(((1U << SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_INI_POS)) +#define SF_CTRL_SF_CMDS_WRAP_MODE SF_CTRL_SF_CMDS_WRAP_MODE +#define SF_CTRL_SF_CMDS_WRAP_MODE_POS (10U) +#define SF_CTRL_SF_CMDS_WRAP_MODE_LEN (1U) +#define SF_CTRL_SF_CMDS_WRAP_MODE_MSK (((1U << SF_CTRL_SF_CMDS_WRAP_MODE_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_MODE_POS) +#define SF_CTRL_SF_CMDS_WRAP_MODE_UMSK (~(((1U << SF_CTRL_SF_CMDS_WRAP_MODE_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_MODE_POS)) +#define SF_CTRL_SF_IF_1_ACK_LAT SF_CTRL_SF_IF_1_ACK_LAT +#define SF_CTRL_SF_IF_1_ACK_LAT_POS (29U) +#define SF_CTRL_SF_IF_1_ACK_LAT_LEN (3U) +#define SF_CTRL_SF_IF_1_ACK_LAT_MSK (((1U << SF_CTRL_SF_IF_1_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_1_ACK_LAT_POS) +#define SF_CTRL_SF_IF_1_ACK_LAT_UMSK (~(((1U << SF_CTRL_SF_IF_1_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_1_ACK_LAT_POS)) + +/* 0x78 : sf_if_iahb_3 */ +#define SF_CTRL_SF_IF_IAHB_3_OFFSET (0x78) +#define SF_CTRL_SF_IF_2_DMY_BYTE SF_CTRL_SF_IF_2_DMY_BYTE +#define SF_CTRL_SF_IF_2_DMY_BYTE_POS (12U) +#define SF_CTRL_SF_IF_2_DMY_BYTE_LEN (5U) +#define SF_CTRL_SF_IF_2_DMY_BYTE_MSK (((1U << SF_CTRL_SF_IF_2_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_BYTE_POS) +#define SF_CTRL_SF_IF_2_DMY_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_2_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_BYTE_POS)) +#define SF_CTRL_SF_IF_2_ADR_BYTE SF_CTRL_SF_IF_2_ADR_BYTE +#define SF_CTRL_SF_IF_2_ADR_BYTE_POS (17U) +#define SF_CTRL_SF_IF_2_ADR_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_2_ADR_BYTE_MSK (((1U << SF_CTRL_SF_IF_2_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_BYTE_POS) +#define SF_CTRL_SF_IF_2_ADR_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_2_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_BYTE_POS)) +#define SF_CTRL_SF_IF_2_CMD_BYTE SF_CTRL_SF_IF_2_CMD_BYTE +#define SF_CTRL_SF_IF_2_CMD_BYTE_POS (20U) +#define SF_CTRL_SF_IF_2_CMD_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_2_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF_2_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BYTE_POS) +#define SF_CTRL_SF_IF_2_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BYTE_POS)) +#define SF_CTRL_SF_IF_2_DAT_RW SF_CTRL_SF_IF_2_DAT_RW +#define SF_CTRL_SF_IF_2_DAT_RW_POS (23U) +#define SF_CTRL_SF_IF_2_DAT_RW_LEN (1U) +#define SF_CTRL_SF_IF_2_DAT_RW_MSK (((1U << SF_CTRL_SF_IF_2_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_RW_POS) +#define SF_CTRL_SF_IF_2_DAT_RW_UMSK (~(((1U << SF_CTRL_SF_IF_2_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_RW_POS)) +#define SF_CTRL_SF_IF_2_DAT_EN SF_CTRL_SF_IF_2_DAT_EN +#define SF_CTRL_SF_IF_2_DAT_EN_POS (24U) +#define SF_CTRL_SF_IF_2_DAT_EN_LEN (1U) +#define SF_CTRL_SF_IF_2_DAT_EN_MSK (((1U << SF_CTRL_SF_IF_2_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_EN_POS) +#define SF_CTRL_SF_IF_2_DAT_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_EN_POS)) +#define SF_CTRL_SF_IF_2_DMY_EN SF_CTRL_SF_IF_2_DMY_EN +#define SF_CTRL_SF_IF_2_DMY_EN_POS (25U) +#define SF_CTRL_SF_IF_2_DMY_EN_LEN (1U) +#define SF_CTRL_SF_IF_2_DMY_EN_MSK (((1U << SF_CTRL_SF_IF_2_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_EN_POS) +#define SF_CTRL_SF_IF_2_DMY_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_EN_POS)) +#define SF_CTRL_SF_IF_2_ADR_EN SF_CTRL_SF_IF_2_ADR_EN +#define SF_CTRL_SF_IF_2_ADR_EN_POS (26U) +#define SF_CTRL_SF_IF_2_ADR_EN_LEN (1U) +#define SF_CTRL_SF_IF_2_ADR_EN_MSK (((1U << SF_CTRL_SF_IF_2_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_EN_POS) +#define SF_CTRL_SF_IF_2_ADR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_EN_POS)) +#define SF_CTRL_SF_IF_2_CMD_EN SF_CTRL_SF_IF_2_CMD_EN +#define SF_CTRL_SF_IF_2_CMD_EN_POS (27U) +#define SF_CTRL_SF_IF_2_CMD_EN_LEN (1U) +#define SF_CTRL_SF_IF_2_CMD_EN_MSK (((1U << SF_CTRL_SF_IF_2_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_EN_POS) +#define SF_CTRL_SF_IF_2_CMD_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_EN_POS)) +#define SF_CTRL_SF_IF_2_SPI_MODE SF_CTRL_SF_IF_2_SPI_MODE +#define SF_CTRL_SF_IF_2_SPI_MODE_POS (28U) +#define SF_CTRL_SF_IF_2_SPI_MODE_LEN (3U) +#define SF_CTRL_SF_IF_2_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF_2_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_2_SPI_MODE_POS) +#define SF_CTRL_SF_IF_2_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_2_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_2_SPI_MODE_POS)) +#define SF_CTRL_SF_IF_2_QPI_MODE_EN SF_CTRL_SF_IF_2_QPI_MODE_EN +#define SF_CTRL_SF_IF_2_QPI_MODE_EN_POS (31U) +#define SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN (1U) +#define SF_CTRL_SF_IF_2_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_2_QPI_MODE_EN_POS) +#define SF_CTRL_SF_IF_2_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_2_QPI_MODE_EN_POS)) + +/* 0x7C : sf_if_iahb_4 */ +#define SF_CTRL_SF_IF_IAHB_4_OFFSET (0x7C) +#define SF_CTRL_SF_IF_2_CMD_BUF_0 SF_CTRL_SF_IF_2_CMD_BUF_0 +#define SF_CTRL_SF_IF_2_CMD_BUF_0_POS (0U) +#define SF_CTRL_SF_IF_2_CMD_BUF_0_LEN (32U) +#define SF_CTRL_SF_IF_2_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF_2_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_0_POS) +#define SF_CTRL_SF_IF_2_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_0_POS)) + +/* 0x80 : sf_if_iahb_5 */ +#define SF_CTRL_SF_IF_IAHB_5_OFFSET (0x80) +#define SF_CTRL_SF_IF_2_CMD_BUF_1 SF_CTRL_SF_IF_2_CMD_BUF_1 +#define SF_CTRL_SF_IF_2_CMD_BUF_1_POS (0U) +#define SF_CTRL_SF_IF_2_CMD_BUF_1_LEN (32U) +#define SF_CTRL_SF_IF_2_CMD_BUF_1_MSK (((1U << SF_CTRL_SF_IF_2_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_1_POS) +#define SF_CTRL_SF_IF_2_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_1_POS)) + +/* 0x84 : sf_if_iahb_6 */ +#define SF_CTRL_SF_IF_IAHB_6_OFFSET (0x84) +#define SF_CTRL_SF_IF_3_CMD_BYTE SF_CTRL_SF_IF_3_CMD_BYTE +#define SF_CTRL_SF_IF_3_CMD_BYTE_POS (20U) +#define SF_CTRL_SF_IF_3_CMD_BYTE_LEN (3U) +#define SF_CTRL_SF_IF_3_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF_3_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BYTE_POS) +#define SF_CTRL_SF_IF_3_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_3_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BYTE_POS)) +#define SF_CTRL_SF_IF_3_SPI_MODE SF_CTRL_SF_IF_3_SPI_MODE +#define SF_CTRL_SF_IF_3_SPI_MODE_POS (28U) +#define SF_CTRL_SF_IF_3_SPI_MODE_LEN (3U) +#define SF_CTRL_SF_IF_3_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF_3_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_3_SPI_MODE_POS) +#define SF_CTRL_SF_IF_3_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_3_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_3_SPI_MODE_POS)) +#define SF_CTRL_SF_IF_3_QPI_MODE_EN SF_CTRL_SF_IF_3_QPI_MODE_EN +#define SF_CTRL_SF_IF_3_QPI_MODE_EN_POS (31U) +#define SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN (1U) +#define SF_CTRL_SF_IF_3_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_3_QPI_MODE_EN_POS) +#define SF_CTRL_SF_IF_3_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_3_QPI_MODE_EN_POS)) + +/* 0x88 : sf_if_iahb_7 */ +#define SF_CTRL_SF_IF_IAHB_7_OFFSET (0x88) +#define SF_CTRL_SF_IF_3_CMD_BUF_0 SF_CTRL_SF_IF_3_CMD_BUF_0 +#define SF_CTRL_SF_IF_3_CMD_BUF_0_POS (0U) +#define SF_CTRL_SF_IF_3_CMD_BUF_0_LEN (32U) +#define SF_CTRL_SF_IF_3_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF_3_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_0_POS) +#define SF_CTRL_SF_IF_3_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_3_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_0_POS)) + +/* 0x100 : sf_ctrl_prot_en_rd */ +#define SF_CTRL_PROT_EN_RD_OFFSET (0x100) +#define SF_CTRL_PROT_EN_RD SF_CTRL_PROT_EN_RD +#define SF_CTRL_PROT_EN_RD_POS (0U) +#define SF_CTRL_PROT_EN_RD_LEN (1U) +#define SF_CTRL_PROT_EN_RD_MSK (((1U << SF_CTRL_PROT_EN_RD_LEN) - 1) << SF_CTRL_PROT_EN_RD_POS) +#define SF_CTRL_PROT_EN_RD_UMSK (~(((1U << SF_CTRL_PROT_EN_RD_LEN) - 1) << SF_CTRL_PROT_EN_RD_POS)) +#define SF_CTRL_ID0_EN_RD SF_CTRL_ID0_EN_RD +#define SF_CTRL_ID0_EN_RD_POS (1U) +#define SF_CTRL_ID0_EN_RD_LEN (1U) +#define SF_CTRL_ID0_EN_RD_MSK (((1U << SF_CTRL_ID0_EN_RD_LEN) - 1) << SF_CTRL_ID0_EN_RD_POS) +#define SF_CTRL_ID0_EN_RD_UMSK (~(((1U << SF_CTRL_ID0_EN_RD_LEN) - 1) << SF_CTRL_ID0_EN_RD_POS)) +#define SF_CTRL_ID1_EN_RD SF_CTRL_ID1_EN_RD +#define SF_CTRL_ID1_EN_RD_POS (2U) +#define SF_CTRL_ID1_EN_RD_LEN (1U) +#define SF_CTRL_ID1_EN_RD_MSK (((1U << SF_CTRL_ID1_EN_RD_LEN) - 1) << SF_CTRL_ID1_EN_RD_POS) +#define SF_CTRL_ID1_EN_RD_UMSK (~(((1U << SF_CTRL_ID1_EN_RD_LEN) - 1) << SF_CTRL_ID1_EN_RD_POS)) +#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK SF_CTRL_SF_IF_0_TRIG_WR_LOCK +#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS (30U) +#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN (1U) +#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_MSK (((1U << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS) +#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_UMSK (~(((1U << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS)) +#define SF_CTRL_SF_DBG_DIS SF_CTRL_SF_DBG_DIS +#define SF_CTRL_SF_DBG_DIS_POS (31U) +#define SF_CTRL_SF_DBG_DIS_LEN (1U) +#define SF_CTRL_SF_DBG_DIS_MSK (((1U << SF_CTRL_SF_DBG_DIS_LEN) - 1) << SF_CTRL_SF_DBG_DIS_POS) +#define SF_CTRL_SF_DBG_DIS_UMSK (~(((1U << SF_CTRL_SF_DBG_DIS_LEN) - 1) << SF_CTRL_SF_DBG_DIS_POS)) + +/* 0x104 : sf_ctrl_prot_en */ +#define SF_CTRL_PROT_EN_OFFSET (0x104) +#define SF_CTRL_PROT_EN SF_CTRL_PROT_EN +#define SF_CTRL_PROT_EN_POS (0U) +#define SF_CTRL_PROT_EN_LEN (1U) +#define SF_CTRL_PROT_EN_MSK (((1U << SF_CTRL_PROT_EN_LEN) - 1) << SF_CTRL_PROT_EN_POS) +#define SF_CTRL_PROT_EN_UMSK (~(((1U << SF_CTRL_PROT_EN_LEN) - 1) << SF_CTRL_PROT_EN_POS)) +#define SF_CTRL_ID0_EN SF_CTRL_ID0_EN +#define SF_CTRL_ID0_EN_POS (1U) +#define SF_CTRL_ID0_EN_LEN (1U) +#define SF_CTRL_ID0_EN_MSK (((1U << SF_CTRL_ID0_EN_LEN) - 1) << SF_CTRL_ID0_EN_POS) +#define SF_CTRL_ID0_EN_UMSK (~(((1U << SF_CTRL_ID0_EN_LEN) - 1) << SF_CTRL_ID0_EN_POS)) +#define SF_CTRL_ID1_EN SF_CTRL_ID1_EN +#define SF_CTRL_ID1_EN_POS (2U) +#define SF_CTRL_ID1_EN_LEN (1U) +#define SF_CTRL_ID1_EN_MSK (((1U << SF_CTRL_ID1_EN_LEN) - 1) << SF_CTRL_ID1_EN_POS) +#define SF_CTRL_ID1_EN_UMSK (~(((1U << SF_CTRL_ID1_EN_LEN) - 1) << SF_CTRL_ID1_EN_POS)) + +/* 0x200 : sf_aes_key_r0_0 */ +#define SF_CTRL_SF_AES_KEY_R0_0_OFFSET (0x200) +#define SF_CTRL_SF_AES_KEY_R0_0 SF_CTRL_SF_AES_KEY_R0_0 +#define SF_CTRL_SF_AES_KEY_R0_0_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_0_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_0_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_0_POS) +#define SF_CTRL_SF_AES_KEY_R0_0_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_0_POS)) + +/* 0x204 : sf_aes_key_r0_1 */ +#define SF_CTRL_SF_AES_KEY_R0_1_OFFSET (0x204) +#define SF_CTRL_SF_AES_KEY_R0_1 SF_CTRL_SF_AES_KEY_R0_1 +#define SF_CTRL_SF_AES_KEY_R0_1_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_1_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_1_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_1_POS) +#define SF_CTRL_SF_AES_KEY_R0_1_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_1_POS)) + +/* 0x208 : sf_aes_key_r0_2 */ +#define SF_CTRL_SF_AES_KEY_R0_2_OFFSET (0x208) +#define SF_CTRL_SF_AES_KEY_R0_2 SF_CTRL_SF_AES_KEY_R0_2 +#define SF_CTRL_SF_AES_KEY_R0_2_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_2_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_2_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_2_POS) +#define SF_CTRL_SF_AES_KEY_R0_2_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_2_POS)) + +/* 0x20C : sf_aes_key_r0_3 */ +#define SF_CTRL_SF_AES_KEY_R0_3_OFFSET (0x20C) +#define SF_CTRL_SF_AES_KEY_R0_3 SF_CTRL_SF_AES_KEY_R0_3 +#define SF_CTRL_SF_AES_KEY_R0_3_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_3_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_3_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_3_POS) +#define SF_CTRL_SF_AES_KEY_R0_3_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_3_POS)) + +/* 0x210 : sf_aes_key_r0_4 */ +#define SF_CTRL_SF_AES_KEY_R0_4_OFFSET (0x210) +#define SF_CTRL_SF_AES_KEY_R0_4 SF_CTRL_SF_AES_KEY_R0_4 +#define SF_CTRL_SF_AES_KEY_R0_4_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_4_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_4_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_4_POS) +#define SF_CTRL_SF_AES_KEY_R0_4_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_4_POS)) + +/* 0x214 : sf_aes_key_r0_5 */ +#define SF_CTRL_SF_AES_KEY_R0_5_OFFSET (0x214) +#define SF_CTRL_SF_AES_KEY_R0_5 SF_CTRL_SF_AES_KEY_R0_5 +#define SF_CTRL_SF_AES_KEY_R0_5_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_5_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_5_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_5_POS) +#define SF_CTRL_SF_AES_KEY_R0_5_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_5_POS)) + +/* 0x218 : sf_aes_key_r0_6 */ +#define SF_CTRL_SF_AES_KEY_R0_6_OFFSET (0x218) +#define SF_CTRL_SF_AES_KEY_R0_6 SF_CTRL_SF_AES_KEY_R0_6 +#define SF_CTRL_SF_AES_KEY_R0_6_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_6_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_6_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_6_POS) +#define SF_CTRL_SF_AES_KEY_R0_6_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_6_POS)) + +/* 0x21C : sf_aes_key_r0_7 */ +#define SF_CTRL_SF_AES_KEY_R0_7_OFFSET (0x21C) +#define SF_CTRL_SF_AES_KEY_R0_7 SF_CTRL_SF_AES_KEY_R0_7 +#define SF_CTRL_SF_AES_KEY_R0_7_POS (0U) +#define SF_CTRL_SF_AES_KEY_R0_7_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R0_7_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_7_POS) +#define SF_CTRL_SF_AES_KEY_R0_7_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_7_POS)) + +/* 0x220 : sf_aes_iv_r0_w0 */ +#define SF_CTRL_SF_AES_IV_R0_W0_OFFSET (0x220) +#define SF_CTRL_SF_AES_IV_R0_W0 SF_CTRL_SF_AES_IV_R0_W0 +#define SF_CTRL_SF_AES_IV_R0_W0_POS (0U) +#define SF_CTRL_SF_AES_IV_R0_W0_LEN (32U) +#define SF_CTRL_SF_AES_IV_R0_W0_MSK (((1U << SF_CTRL_SF_AES_IV_R0_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W0_POS) +#define SF_CTRL_SF_AES_IV_R0_W0_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R0_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W0_POS)) + +/* 0x224 : sf_aes_iv_r0_w1 */ +#define SF_CTRL_SF_AES_IV_R0_W1_OFFSET (0x224) +#define SF_CTRL_SF_AES_IV_R0_W1 SF_CTRL_SF_AES_IV_R0_W1 +#define SF_CTRL_SF_AES_IV_R0_W1_POS (0U) +#define SF_CTRL_SF_AES_IV_R0_W1_LEN (32U) +#define SF_CTRL_SF_AES_IV_R0_W1_MSK (((1U << SF_CTRL_SF_AES_IV_R0_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W1_POS) +#define SF_CTRL_SF_AES_IV_R0_W1_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R0_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W1_POS)) + +/* 0x228 : sf_aes_iv_r0_w2 */ +#define SF_CTRL_SF_AES_IV_R0_W2_OFFSET (0x228) +#define SF_CTRL_SF_AES_IV_R0_W2 SF_CTRL_SF_AES_IV_R0_W2 +#define SF_CTRL_SF_AES_IV_R0_W2_POS (0U) +#define SF_CTRL_SF_AES_IV_R0_W2_LEN (32U) +#define SF_CTRL_SF_AES_IV_R0_W2_MSK (((1U << SF_CTRL_SF_AES_IV_R0_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W2_POS) +#define SF_CTRL_SF_AES_IV_R0_W2_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R0_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W2_POS)) + +/* 0x22C : sf_aes_iv_r0_w3 */ +#define SF_CTRL_SF_AES_IV_R0_W3_OFFSET (0x22C) +#define SF_CTRL_SF_AES_IV_R0_W3 SF_CTRL_SF_AES_IV_R0_W3 +#define SF_CTRL_SF_AES_IV_R0_W3_POS (0U) +#define SF_CTRL_SF_AES_IV_R0_W3_LEN (32U) +#define SF_CTRL_SF_AES_IV_R0_W3_MSK (((1U << SF_CTRL_SF_AES_IV_R0_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W3_POS) +#define SF_CTRL_SF_AES_IV_R0_W3_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R0_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W3_POS)) + +/* 0x230 : sf_aes_cfg_r0 */ +#define SF_CTRL_SF_AES_CFG_R0_OFFSET (0x230) +#define SF_CTRL_SF_AES_REGION_R0_END SF_CTRL_SF_AES_REGION_R0_END +#define SF_CTRL_SF_AES_REGION_R0_END_POS (0U) +#define SF_CTRL_SF_AES_REGION_R0_END_LEN (14U) +#define SF_CTRL_SF_AES_REGION_R0_END_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_END_POS) +#define SF_CTRL_SF_AES_REGION_R0_END_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_END_POS)) +#define SF_CTRL_SF_AES_REGION_R0_START SF_CTRL_SF_AES_REGION_R0_START +#define SF_CTRL_SF_AES_REGION_R0_START_POS (14U) +#define SF_CTRL_SF_AES_REGION_R0_START_LEN (14U) +#define SF_CTRL_SF_AES_REGION_R0_START_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_START_POS) +#define SF_CTRL_SF_AES_REGION_R0_START_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_START_POS)) +#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN +#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS (29U) +#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN (1U) +#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS) +#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS)) +#define SF_CTRL_SF_AES_REGION_R0_EN SF_CTRL_SF_AES_REGION_R0_EN +#define SF_CTRL_SF_AES_REGION_R0_EN_POS (30U) +#define SF_CTRL_SF_AES_REGION_R0_EN_LEN (1U) +#define SF_CTRL_SF_AES_REGION_R0_EN_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_EN_POS) +#define SF_CTRL_SF_AES_REGION_R0_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_EN_POS)) +#define SF_CTRL_SF_AES_REGION_R0_LOCK SF_CTRL_SF_AES_REGION_R0_LOCK +#define SF_CTRL_SF_AES_REGION_R0_LOCK_POS (31U) +#define SF_CTRL_SF_AES_REGION_R0_LOCK_LEN (1U) +#define SF_CTRL_SF_AES_REGION_R0_LOCK_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_LOCK_POS) +#define SF_CTRL_SF_AES_REGION_R0_LOCK_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_LOCK_POS)) + +/* 0x300 : sf_aes_key_r1_0 */ +#define SF_CTRL_SF_AES_KEY_R1_0_OFFSET (0x300) +#define SF_CTRL_SF_AES_KEY_R1_0 SF_CTRL_SF_AES_KEY_R1_0 +#define SF_CTRL_SF_AES_KEY_R1_0_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_0_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_0_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_0_POS) +#define SF_CTRL_SF_AES_KEY_R1_0_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_0_POS)) + +/* 0x304 : sf_aes_key_r1_1 */ +#define SF_CTRL_SF_AES_KEY_R1_1_OFFSET (0x304) +#define SF_CTRL_SF_AES_KEY_R1_1 SF_CTRL_SF_AES_KEY_R1_1 +#define SF_CTRL_SF_AES_KEY_R1_1_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_1_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_1_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_1_POS) +#define SF_CTRL_SF_AES_KEY_R1_1_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_1_POS)) + +/* 0x308 : sf_aes_key_r1_2 */ +#define SF_CTRL_SF_AES_KEY_R1_2_OFFSET (0x308) +#define SF_CTRL_SF_AES_KEY_R1_2 SF_CTRL_SF_AES_KEY_R1_2 +#define SF_CTRL_SF_AES_KEY_R1_2_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_2_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_2_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_2_POS) +#define SF_CTRL_SF_AES_KEY_R1_2_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_2_POS)) + +/* 0x30C : sf_aes_key_r1_3 */ +#define SF_CTRL_SF_AES_KEY_R1_3_OFFSET (0x30C) +#define SF_CTRL_SF_AES_KEY_R1_3 SF_CTRL_SF_AES_KEY_R1_3 +#define SF_CTRL_SF_AES_KEY_R1_3_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_3_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_3_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_3_POS) +#define SF_CTRL_SF_AES_KEY_R1_3_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_3_POS)) + +/* 0x310 : sf_aes_key_r1_4 */ +#define SF_CTRL_SF_AES_KEY_R1_4_OFFSET (0x310) +#define SF_CTRL_SF_AES_KEY_R1_4 SF_CTRL_SF_AES_KEY_R1_4 +#define SF_CTRL_SF_AES_KEY_R1_4_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_4_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_4_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_4_POS) +#define SF_CTRL_SF_AES_KEY_R1_4_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_4_POS)) + +/* 0x314 : sf_aes_key_r1_5 */ +#define SF_CTRL_SF_AES_KEY_R1_5_OFFSET (0x314) +#define SF_CTRL_SF_AES_KEY_R1_5 SF_CTRL_SF_AES_KEY_R1_5 +#define SF_CTRL_SF_AES_KEY_R1_5_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_5_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_5_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_5_POS) +#define SF_CTRL_SF_AES_KEY_R1_5_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_5_POS)) + +/* 0x318 : sf_aes_key_r1_6 */ +#define SF_CTRL_SF_AES_KEY_R1_6_OFFSET (0x318) +#define SF_CTRL_SF_AES_KEY_R1_6 SF_CTRL_SF_AES_KEY_R1_6 +#define SF_CTRL_SF_AES_KEY_R1_6_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_6_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_6_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_6_POS) +#define SF_CTRL_SF_AES_KEY_R1_6_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_6_POS)) + +/* 0x31C : sf_aes_key_r1_7 */ +#define SF_CTRL_SF_AES_KEY_R1_7_OFFSET (0x31C) +#define SF_CTRL_SF_AES_KEY_R1_7 SF_CTRL_SF_AES_KEY_R1_7 +#define SF_CTRL_SF_AES_KEY_R1_7_POS (0U) +#define SF_CTRL_SF_AES_KEY_R1_7_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R1_7_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_7_POS) +#define SF_CTRL_SF_AES_KEY_R1_7_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_7_POS)) + +/* 0x320 : sf_aes_iv_r1_w0 */ +#define SF_CTRL_SF_AES_IV_R1_W0_OFFSET (0x320) +#define SF_CTRL_SF_AES_IV_R1_W0 SF_CTRL_SF_AES_IV_R1_W0 +#define SF_CTRL_SF_AES_IV_R1_W0_POS (0U) +#define SF_CTRL_SF_AES_IV_R1_W0_LEN (32U) +#define SF_CTRL_SF_AES_IV_R1_W0_MSK (((1U << SF_CTRL_SF_AES_IV_R1_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W0_POS) +#define SF_CTRL_SF_AES_IV_R1_W0_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R1_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W0_POS)) + +/* 0x324 : sf_aes_iv_r1_w1 */ +#define SF_CTRL_SF_AES_IV_R1_W1_OFFSET (0x324) +#define SF_CTRL_SF_AES_IV_R1_W1 SF_CTRL_SF_AES_IV_R1_W1 +#define SF_CTRL_SF_AES_IV_R1_W1_POS (0U) +#define SF_CTRL_SF_AES_IV_R1_W1_LEN (32U) +#define SF_CTRL_SF_AES_IV_R1_W1_MSK (((1U << SF_CTRL_SF_AES_IV_R1_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W1_POS) +#define SF_CTRL_SF_AES_IV_R1_W1_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R1_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W1_POS)) + +/* 0x328 : sf_aes_iv_r1_w2 */ +#define SF_CTRL_SF_AES_IV_R1_W2_OFFSET (0x328) +#define SF_CTRL_SF_AES_IV_R1_W2 SF_CTRL_SF_AES_IV_R1_W2 +#define SF_CTRL_SF_AES_IV_R1_W2_POS (0U) +#define SF_CTRL_SF_AES_IV_R1_W2_LEN (32U) +#define SF_CTRL_SF_AES_IV_R1_W2_MSK (((1U << SF_CTRL_SF_AES_IV_R1_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W2_POS) +#define SF_CTRL_SF_AES_IV_R1_W2_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R1_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W2_POS)) + +/* 0x32C : sf_aes_iv_r1_w3 */ +#define SF_CTRL_SF_AES_IV_R1_W3_OFFSET (0x32C) +#define SF_CTRL_SF_AES_IV_R1_W3 SF_CTRL_SF_AES_IV_R1_W3 +#define SF_CTRL_SF_AES_IV_R1_W3_POS (0U) +#define SF_CTRL_SF_AES_IV_R1_W3_LEN (32U) +#define SF_CTRL_SF_AES_IV_R1_W3_MSK (((1U << SF_CTRL_SF_AES_IV_R1_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W3_POS) +#define SF_CTRL_SF_AES_IV_R1_W3_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R1_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W3_POS)) + +/* 0x330 : sf_aes_r1 */ +#define SF_CTRL_SF_AES_R1_OFFSET (0x330) +#define SF_CTRL_SF_AES_R1_END SF_CTRL_SF_AES_R1_END +#define SF_CTRL_SF_AES_R1_END_POS (0U) +#define SF_CTRL_SF_AES_R1_END_LEN (14U) +#define SF_CTRL_SF_AES_R1_END_MSK (((1U << SF_CTRL_SF_AES_R1_END_LEN) - 1) << SF_CTRL_SF_AES_R1_END_POS) +#define SF_CTRL_SF_AES_R1_END_UMSK (~(((1U << SF_CTRL_SF_AES_R1_END_LEN) - 1) << SF_CTRL_SF_AES_R1_END_POS)) +#define SF_CTRL_SF_AES_R1_START SF_CTRL_SF_AES_R1_START +#define SF_CTRL_SF_AES_R1_START_POS (14U) +#define SF_CTRL_SF_AES_R1_START_LEN (14U) +#define SF_CTRL_SF_AES_R1_START_MSK (((1U << SF_CTRL_SF_AES_R1_START_LEN) - 1) << SF_CTRL_SF_AES_R1_START_POS) +#define SF_CTRL_SF_AES_R1_START_UMSK (~(((1U << SF_CTRL_SF_AES_R1_START_LEN) - 1) << SF_CTRL_SF_AES_R1_START_POS)) +#define SF_CTRL_SF_AES_R1_HW_KEY_EN SF_CTRL_SF_AES_R1_HW_KEY_EN +#define SF_CTRL_SF_AES_R1_HW_KEY_EN_POS (29U) +#define SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN (1U) +#define SF_CTRL_SF_AES_R1_HW_KEY_EN_MSK (((1U << SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_HW_KEY_EN_POS) +#define SF_CTRL_SF_AES_R1_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_HW_KEY_EN_POS)) +#define SF_CTRL_SF_AES_R1_EN SF_CTRL_SF_AES_R1_EN +#define SF_CTRL_SF_AES_R1_EN_POS (30U) +#define SF_CTRL_SF_AES_R1_EN_LEN (1U) +#define SF_CTRL_SF_AES_R1_EN_MSK (((1U << SF_CTRL_SF_AES_R1_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_EN_POS) +#define SF_CTRL_SF_AES_R1_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R1_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_EN_POS)) +#define SF_CTRL_SF_AES_R1_LOCK SF_CTRL_SF_AES_R1_LOCK +#define SF_CTRL_SF_AES_R1_LOCK_POS (31U) +#define SF_CTRL_SF_AES_R1_LOCK_LEN (1U) +#define SF_CTRL_SF_AES_R1_LOCK_MSK (((1U << SF_CTRL_SF_AES_R1_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R1_LOCK_POS) +#define SF_CTRL_SF_AES_R1_LOCK_UMSK (~(((1U << SF_CTRL_SF_AES_R1_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R1_LOCK_POS)) + +/* 0x400 : sf_aes_key_r2_0 */ +#define SF_CTRL_SF_AES_KEY_R2_0_OFFSET (0x400) +#define SF_CTRL_SF_AES_KEY_R2_0 SF_CTRL_SF_AES_KEY_R2_0 +#define SF_CTRL_SF_AES_KEY_R2_0_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_0_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_0_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_0_POS) +#define SF_CTRL_SF_AES_KEY_R2_0_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_0_POS)) + +/* 0x404 : sf_aes_key_r2_1 */ +#define SF_CTRL_SF_AES_KEY_R2_1_OFFSET (0x404) +#define SF_CTRL_SF_AES_KEY_R2_1 SF_CTRL_SF_AES_KEY_R2_1 +#define SF_CTRL_SF_AES_KEY_R2_1_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_1_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_1_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_1_POS) +#define SF_CTRL_SF_AES_KEY_R2_1_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_1_POS)) + +/* 0x408 : sf_aes_key_r2_2 */ +#define SF_CTRL_SF_AES_KEY_R2_2_OFFSET (0x408) +#define SF_CTRL_SF_AES_KEY_R2_2 SF_CTRL_SF_AES_KEY_R2_2 +#define SF_CTRL_SF_AES_KEY_R2_2_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_2_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_2_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_2_POS) +#define SF_CTRL_SF_AES_KEY_R2_2_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_2_POS)) + +/* 0x40C : sf_aes_key_r2_3 */ +#define SF_CTRL_SF_AES_KEY_R2_3_OFFSET (0x40C) +#define SF_CTRL_SF_AES_KEY_R2_3 SF_CTRL_SF_AES_KEY_R2_3 +#define SF_CTRL_SF_AES_KEY_R2_3_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_3_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_3_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_3_POS) +#define SF_CTRL_SF_AES_KEY_R2_3_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_3_POS)) + +/* 0x410 : sf_aes_key_r2_4 */ +#define SF_CTRL_SF_AES_KEY_R2_4_OFFSET (0x410) +#define SF_CTRL_SF_AES_KEY_R2_4 SF_CTRL_SF_AES_KEY_R2_4 +#define SF_CTRL_SF_AES_KEY_R2_4_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_4_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_4_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_4_POS) +#define SF_CTRL_SF_AES_KEY_R2_4_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_4_POS)) + +/* 0x414 : sf_aes_key_r2_5 */ +#define SF_CTRL_SF_AES_KEY_R2_5_OFFSET (0x414) +#define SF_CTRL_SF_AES_KEY_R2_5 SF_CTRL_SF_AES_KEY_R2_5 +#define SF_CTRL_SF_AES_KEY_R2_5_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_5_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_5_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_5_POS) +#define SF_CTRL_SF_AES_KEY_R2_5_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_5_POS)) + +/* 0x418 : sf_aes_key_r2_6 */ +#define SF_CTRL_SF_AES_KEY_R2_6_OFFSET (0x418) +#define SF_CTRL_SF_AES_KEY_R2_6 SF_CTRL_SF_AES_KEY_R2_6 +#define SF_CTRL_SF_AES_KEY_R2_6_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_6_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_6_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_6_POS) +#define SF_CTRL_SF_AES_KEY_R2_6_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_6_POS)) + +/* 0x41C : sf_aes_key_r2_7 */ +#define SF_CTRL_SF_AES_KEY_R2_7_OFFSET (0x41C) +#define SF_CTRL_SF_AES_KEY_R2_7 SF_CTRL_SF_AES_KEY_R2_7 +#define SF_CTRL_SF_AES_KEY_R2_7_POS (0U) +#define SF_CTRL_SF_AES_KEY_R2_7_LEN (32U) +#define SF_CTRL_SF_AES_KEY_R2_7_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_7_POS) +#define SF_CTRL_SF_AES_KEY_R2_7_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_7_POS)) + +/* 0x420 : sf_aes_iv_r2_w0 */ +#define SF_CTRL_SF_AES_IV_R2_W0_OFFSET (0x420) +#define SF_CTRL_SF_AES_IV_R2_W0 SF_CTRL_SF_AES_IV_R2_W0 +#define SF_CTRL_SF_AES_IV_R2_W0_POS (0U) +#define SF_CTRL_SF_AES_IV_R2_W0_LEN (32U) +#define SF_CTRL_SF_AES_IV_R2_W0_MSK (((1U << SF_CTRL_SF_AES_IV_R2_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W0_POS) +#define SF_CTRL_SF_AES_IV_R2_W0_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R2_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W0_POS)) + +/* 0x424 : sf_aes_iv_r2_w1 */ +#define SF_CTRL_SF_AES_IV_R2_W1_OFFSET (0x424) +#define SF_CTRL_SF_AES_IV_R2_W1 SF_CTRL_SF_AES_IV_R2_W1 +#define SF_CTRL_SF_AES_IV_R2_W1_POS (0U) +#define SF_CTRL_SF_AES_IV_R2_W1_LEN (32U) +#define SF_CTRL_SF_AES_IV_R2_W1_MSK (((1U << SF_CTRL_SF_AES_IV_R2_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W1_POS) +#define SF_CTRL_SF_AES_IV_R2_W1_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R2_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W1_POS)) + +/* 0x428 : sf_aes_iv_r2_w2 */ +#define SF_CTRL_SF_AES_IV_R2_W2_OFFSET (0x428) +#define SF_CTRL_SF_AES_IV_R2_W2 SF_CTRL_SF_AES_IV_R2_W2 +#define SF_CTRL_SF_AES_IV_R2_W2_POS (0U) +#define SF_CTRL_SF_AES_IV_R2_W2_LEN (32U) +#define SF_CTRL_SF_AES_IV_R2_W2_MSK (((1U << SF_CTRL_SF_AES_IV_R2_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W2_POS) +#define SF_CTRL_SF_AES_IV_R2_W2_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R2_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W2_POS)) + +/* 0x42C : sf_aes_iv_r2_w3 */ +#define SF_CTRL_SF_AES_IV_R2_W3_OFFSET (0x42C) +#define SF_CTRL_SF_AES_IV_R2_W3 SF_CTRL_SF_AES_IV_R2_W3 +#define SF_CTRL_SF_AES_IV_R2_W3_POS (0U) +#define SF_CTRL_SF_AES_IV_R2_W3_LEN (32U) +#define SF_CTRL_SF_AES_IV_R2_W3_MSK (((1U << SF_CTRL_SF_AES_IV_R2_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W3_POS) +#define SF_CTRL_SF_AES_IV_R2_W3_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R2_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W3_POS)) + +/* 0x430 : sf_aes_r2 */ +#define SF_CTRL_SF_AES_R2_OFFSET (0x430) +#define SF_CTRL_SF_AES_R2_END SF_CTRL_SF_AES_R2_END +#define SF_CTRL_SF_AES_R2_END_POS (0U) +#define SF_CTRL_SF_AES_R2_END_LEN (14U) +#define SF_CTRL_SF_AES_R2_END_MSK (((1U << SF_CTRL_SF_AES_R2_END_LEN) - 1) << SF_CTRL_SF_AES_R2_END_POS) +#define SF_CTRL_SF_AES_R2_END_UMSK (~(((1U << SF_CTRL_SF_AES_R2_END_LEN) - 1) << SF_CTRL_SF_AES_R2_END_POS)) +#define SF_CTRL_SF_AES_R2_START SF_CTRL_SF_AES_R2_START +#define SF_CTRL_SF_AES_R2_START_POS (14U) +#define SF_CTRL_SF_AES_R2_START_LEN (14U) +#define SF_CTRL_SF_AES_R2_START_MSK (((1U << SF_CTRL_SF_AES_R2_START_LEN) - 1) << SF_CTRL_SF_AES_R2_START_POS) +#define SF_CTRL_SF_AES_R2_START_UMSK (~(((1U << SF_CTRL_SF_AES_R2_START_LEN) - 1) << SF_CTRL_SF_AES_R2_START_POS)) +#define SF_CTRL_SF_AES_R2_HW_KEY_EN SF_CTRL_SF_AES_R2_HW_KEY_EN +#define SF_CTRL_SF_AES_R2_HW_KEY_EN_POS (29U) +#define SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN (1U) +#define SF_CTRL_SF_AES_R2_HW_KEY_EN_MSK (((1U << SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_HW_KEY_EN_POS) +#define SF_CTRL_SF_AES_R2_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_HW_KEY_EN_POS)) +#define SF_CTRL_SF_AES_R2_EN SF_CTRL_SF_AES_R2_EN +#define SF_CTRL_SF_AES_R2_EN_POS (30U) +#define SF_CTRL_SF_AES_R2_EN_LEN (1U) +#define SF_CTRL_SF_AES_R2_EN_MSK (((1U << SF_CTRL_SF_AES_R2_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_EN_POS) +#define SF_CTRL_SF_AES_R2_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R2_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_EN_POS)) +#define SF_CTRL_SF_AES_R2_LOCK SF_CTRL_SF_AES_R2_LOCK +#define SF_CTRL_SF_AES_R2_LOCK_POS (31U) +#define SF_CTRL_SF_AES_R2_LOCK_LEN (1U) +#define SF_CTRL_SF_AES_R2_LOCK_MSK (((1U << SF_CTRL_SF_AES_R2_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R2_LOCK_POS) +#define SF_CTRL_SF_AES_R2_LOCK_UMSK (~(((1U << SF_CTRL_SF_AES_R2_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R2_LOCK_POS)) + +/* 0x434 : sf_id0_offset */ +#define SF_CTRL_SF_ID0_OFFSET_OFFSET (0x434) +#define SF_CTRL_SF_ID0_OFFSET SF_CTRL_SF_ID0_OFFSET +#define SF_CTRL_SF_ID0_OFFSET_POS (0U) +#define SF_CTRL_SF_ID0_OFFSET_LEN (24U) +#define SF_CTRL_SF_ID0_OFFSET_MSK (((1U << SF_CTRL_SF_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_ID0_OFFSET_POS) +#define SF_CTRL_SF_ID0_OFFSET_UMSK (~(((1U << SF_CTRL_SF_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_ID0_OFFSET_POS)) + +/* 0x438 : sf_id1_offset */ +#define SF_CTRL_SF_ID1_OFFSET_OFFSET (0x438) +#define SF_CTRL_SF_ID1_OFFSET SF_CTRL_SF_ID1_OFFSET +#define SF_CTRL_SF_ID1_OFFSET_POS (0U) +#define SF_CTRL_SF_ID1_OFFSET_LEN (24U) +#define SF_CTRL_SF_ID1_OFFSET_MSK (((1U << SF_CTRL_SF_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_ID1_OFFSET_POS) +#define SF_CTRL_SF_ID1_OFFSET_UMSK (~(((1U << SF_CTRL_SF_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_ID1_OFFSET_POS)) + +struct sf_ctrl_reg { + /* 0x0 : sf_ctrl_0 */ + union { + struct + { + uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ + uint32_t sf_clk_sf_rx_inv_sel : 1; /* [ 2], r/w, 0x1 */ + uint32_t sf_clk_out_gate_en : 1; /* [ 3], r/w, 0x1 */ + uint32_t sf_clk_out_inv_sel : 1; /* [ 4], r/w, 0x1 */ + uint32_t sf_clk_sahb_sram_sel : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t sf_if_read_dly_n : 3; /* [10: 8], r/w, 0x0 */ + uint32_t sf_if_read_dly_en : 1; /* [ 11], r/w, 0x0 */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t sf_if_int : 1; /* [ 16], r, 0x0 */ + uint32_t sf_if_int_clr : 1; /* [ 17], r/w, 0x1 */ + uint32_t sf_if_int_set : 1; /* [ 18], r/w, 0x0 */ + uint32_t sf_aes_dly_mode : 1; /* [ 19], r/w, 0x0 */ + uint32_t sf_aes_dout_endian : 1; /* [ 20], r/w, 0x1 */ + uint32_t sf_aes_ctr_plus_en : 1; /* [ 21], r/w, 0x0 */ + uint32_t sf_aes_key_endian : 1; /* [ 22], r/w, 0x1 */ + uint32_t sf_aes_iv_endian : 1; /* [ 23], r/w, 0x1 */ + uint32_t sf_id : 8; /* [31:24], r/w, 0x1a */ + } BF; + uint32_t WORD; + } sf_ctrl_0; + + /* 0x4 : sf_ctrl_1 */ + union { + struct + { + uint32_t sf_if_sr_pat_mask : 8; /* [ 7: 0], r/w, 0x0 */ + uint32_t sf_if_sr_pat : 8; /* [15: 8], r/w, 0x0 */ + uint32_t sf_if_sr_int : 1; /* [ 16], r, 0x0 */ + uint32_t sf_if_sr_int_en : 1; /* [ 17], r/w, 0x0 */ + uint32_t sf_if_sr_int_set : 1; /* [ 18], r/w, 0x0 */ + uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ + uint32_t sf_if_0_ack_lat : 3; /* [22:20], r/w, 0x6 */ + uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ + uint32_t sf_if_reg_hold : 1; /* [ 24], r/w, 0x1 */ + uint32_t sf_if_reg_wp : 1; /* [ 25], r/w, 0x1 */ + uint32_t sf_ahb2sif_stopped : 1; /* [ 26], r, 0x0 */ + uint32_t sf_ahb2sif_stop : 1; /* [ 27], r/w, 0x0 */ + uint32_t sf_if_fn_sel : 1; /* [ 28], r/w, 0x1 */ + uint32_t sf_if_en : 1; /* [ 29], r/w, 0x1 */ + uint32_t sf_ahb2sif_en : 1; /* [ 30], r/w, 0x1 */ + uint32_t sf_ahb2sram_en : 1; /* [ 31], r/w, 0x1 */ + } BF; + uint32_t WORD; + } sf_ctrl_1; + + /* 0x8 : sf_if_sahb_0 */ + union { + struct sf_if_sahb { + uint32_t sf_if_busy : 1; /* [ 0], r, 0x0 */ + uint32_t sf_if_0_trig : 1; /* [ 1], r/w, 0x0 */ + uint32_t sf_if_0_dat_byte : 10; /* [11: 2], r/w, 0x0 */ + uint32_t sf_if_0_dmy_byte : 5; /* [16:12], r/w, 0x0 */ + uint32_t sf_if_0_adr_byte : 3; /* [19:17], r/w, 0x0 */ + uint32_t sf_if_0_cmd_byte : 3; /* [22:20], r/w, 0x0 */ + uint32_t sf_if_0_dat_rw : 1; /* [ 23], r/w, 0x0 */ + uint32_t sf_if_0_dat_en : 1; /* [ 24], r/w, 0x0 */ + uint32_t sf_if_0_dmy_en : 1; /* [ 25], r/w, 0x0 */ + uint32_t sf_if_0_adr_en : 1; /* [ 26], r/w, 0x0 */ + uint32_t sf_if_0_cmd_en : 1; /* [ 27], r/w, 0x0 */ + uint32_t sf_if_0_spi_mode : 3; /* [30:28], r/w, 0x0 */ + uint32_t sf_if_0_qpi_mode_en : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_sahb_0; + + /* 0xC : sf_if_sahb_1 */ + union { + struct + { + uint32_t sf_if_0_cmd_buf_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_sahb_1; + + /* 0x10 : sf_if_sahb_2 */ + union { + struct + { + uint32_t sf_if_0_cmd_buf_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_sahb_2; + + /* 0x14 : sf_if_iahb_0 */ + union { + struct sf_if_iahb { + uint32_t reserved_0_11 : 12; /* [11: 0], rsvd, 0x0 */ + uint32_t sf_if_1_dmy_byte : 5; /* [16:12], r/w, 0x0 */ + uint32_t sf_if_1_adr_byte : 3; /* [19:17], r/w, 0x2 */ + uint32_t sf_if_1_cmd_byte : 3; /* [22:20], r/w, 0x0 */ + uint32_t sf_if_1_dat_rw : 1; /* [ 23], r/w, 0x0 */ + uint32_t sf_if_1_dat_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t sf_if_1_dmy_en : 1; /* [ 25], r/w, 0x0 */ + uint32_t sf_if_1_adr_en : 1; /* [ 26], r/w, 0x1 */ + uint32_t sf_if_1_cmd_en : 1; /* [ 27], r/w, 0x1 */ + uint32_t sf_if_1_spi_mode : 3; /* [30:28], r/w, 0x0 */ + uint32_t sf_if_1_qpi_mode_en : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_iahb_0; + + /* 0x18 : sf_if_iahb_1 */ + union { + struct + { + uint32_t sf_if_1_cmd_buf_0 : 32; /* [31: 0], r/w, 0x3000000 */ + } BF; + uint32_t WORD; + } sf_if_iahb_1; + + /* 0x1C : sf_if_iahb_2 */ + union { + struct + { + uint32_t sf_if_1_cmd_buf_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_iahb_2; + + /* 0x20 : sf_if_status_0 */ + union { + struct + { + uint32_t sf_if_status_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_status_0; + + /* 0x24 : sf_if_status_1 */ + union { + struct + { + uint32_t sf_if_status_1 : 32; /* [31: 0], r, 0x20000000 */ + } BF; + uint32_t WORD; + } sf_if_status_1; + + /* 0x28 : sf_aes */ + union { + struct + { + uint32_t sf_aes_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t sf_aes_mode : 2; /* [ 2: 1], r/w, 0x0 */ + uint32_t sf_aes_pref_trig : 1; /* [ 3], r/w, 0x0 */ + uint32_t sf_aes_pref_busy : 1; /* [ 4], r, 0x0 */ + uint32_t sf_aes_status : 27; /* [31: 5], r, 0x2 */ + } BF; + uint32_t WORD; + } sf_aes; + + /* 0x2C : sf_ahb2sif_status */ + union { + struct + { + uint32_t sf_ahb2sif_status : 32; /* [31: 0], r, 0x10000003 */ + } BF; + uint32_t WORD; + } sf_ahb2sif_status; + + /* 0x30 : sf_if_io_dly_0 */ + union { + struct + { + uint32_t sf_cs_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf_clk_out_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_25 : 16; /* [25:10], rsvd, 0x0 */ + uint32_t sf_dqs_oe_dly_sel : 2; /* [27:26], r/w, 0x0 */ + uint32_t sf_dqs_di_dly_sel : 2; /* [29:28], r/w, 0x0 */ + uint32_t sf_dqs_do_dly_sel : 2; /* [31:30], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_io_dly_0; + + /* 0x34 : sf_if_io_dly_1 */ + union { + struct + { + uint32_t sf_io_0_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf_io_0_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf_io_0_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_io_dly_1; + + /* 0x38 : sf_if_io_dly_2 */ + union { + struct + { + uint32_t sf_io_1_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf_io_1_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf_io_1_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_io_dly_2; + + /* 0x3C : sf_if_io_dly_3 */ + union { + struct + { + uint32_t sf_io_2_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf_io_2_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf_io_2_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_io_dly_3; + + /* 0x40 : sf_if_io_dly_4 */ + union { + struct + { + uint32_t sf_io_3_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf_io_3_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf_io_3_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_io_dly_4; + + /* 0x44 : sf_reserved */ + union { + struct + { + uint32_t sf_reserved : 32; /* [31: 0], r/w, 0xffff */ + } BF; + uint32_t WORD; + } sf_reserved; + + /* 0x48 : sf2_if_io_dly_0 */ + union { + struct + { + uint32_t sf2_cs_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf2_clk_out_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_25 : 16; /* [25:10], rsvd, 0x0 */ + uint32_t sf2_dqs_oe_dly_sel : 2; /* [27:26], r/w, 0x0 */ + uint32_t sf2_dqs_di_dly_sel : 2; /* [29:28], r/w, 0x0 */ + uint32_t sf2_dqs_do_dly_sel : 2; /* [31:30], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf2_if_io_dly_0; + + /* 0x4C : sf2_if_io_dly_1 */ + union { + struct + { + uint32_t sf2_io_0_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf2_io_0_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf2_io_0_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf2_if_io_dly_1; + + /* 0x50 : sf2_if_io_dly_2 */ + union { + struct + { + uint32_t sf2_io_1_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf2_io_1_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf2_io_1_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf2_if_io_dly_2; + + /* 0x54 : sf2_if_io_dly_3 */ + union { + struct + { + uint32_t sf2_io_2_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf2_io_2_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf2_io_2_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf2_if_io_dly_3; + + /* 0x58 : sf2_if_io_dly_4 */ + union { + struct + { + uint32_t sf2_io_3_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf2_io_3_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf2_io_3_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf2_if_io_dly_4; + + /* 0x5C : sf3_if_io_dly_0 */ + union { + struct + { + uint32_t sf3_cs_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf3_clk_out_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_25 : 16; /* [25:10], rsvd, 0x0 */ + uint32_t sf3_dqs_oe_dly_sel : 2; /* [27:26], r/w, 0x0 */ + uint32_t sf3_dqs_di_dly_sel : 2; /* [29:28], r/w, 0x0 */ + uint32_t sf3_dqs_do_dly_sel : 2; /* [31:30], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf3_if_io_dly_0; + + /* 0x60 : sf3_if_io_dly_1 */ + union { + struct + { + uint32_t sf3_io_0_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf3_io_0_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf3_io_0_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf3_if_io_dly_1; + + /* 0x64 : sf3_if_io_dly_2 */ + union { + struct + { + uint32_t sf3_io_1_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf3_io_1_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf3_io_1_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf3_if_io_dly_2; + + /* 0x68 : sf3_if_io_dly_3 */ + union { + struct + { + uint32_t sf3_io_2_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf3_io_2_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf3_io_2_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf3_if_io_dly_3; + + /* 0x6C : sf3_if_io_dly_4 */ + union { + struct + { + uint32_t sf3_io_3_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ + uint32_t sf3_io_3_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t sf3_io_3_do_dly_sel : 2; /* [17:16], r/w, 0x0 */ + uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf3_if_io_dly_4; + + /* 0x70 : sf_ctrl_2 */ + union { + struct + { + uint32_t sf_if_pad_sel : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t reserved_2 : 1; /* [ 2], rsvd, 0x0 */ + uint32_t sf_if_pad_sel_lock : 1; /* [ 3], r/w, 0x0 */ + uint32_t sf_if_dtr_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t sf_if_dqs_en : 1; /* [ 5], r/w, 0x0 */ + uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_ctrl_2; + + /* 0x74 : sf_ctrl_3 */ + union { + struct + { + uint32_t sf_cmds_wrap_len : 4; /* [ 3: 0], r/w, 0x6 */ + uint32_t sf_cmds_en : 1; /* [ 4], r/w, 0x0 */ + uint32_t sf_cmds_bt_dly : 3; /* [ 7: 5], r/w, 0x2 */ + uint32_t sf_cmds_bt_en : 1; /* [ 8], r/w, 0x0 */ + uint32_t sf_cmds_wrap_q_ini : 1; /* [ 9], r/w, 0x0 */ + uint32_t sf_cmds_wrap_mode : 1; /* [ 10], r/w, 0x0 */ + uint32_t reserved_11_28 : 18; /* [28:11], rsvd, 0x0 */ + uint32_t sf_if_1_ack_lat : 3; /* [31:29], r/w, 0x1 */ + } BF; + uint32_t WORD; + } sf_ctrl_3; + + /* 0x78 : sf_if_iahb_3 */ + union { + struct + { + uint32_t reserved_0_11 : 12; /* [11: 0], rsvd, 0x0 */ + uint32_t sf_if_2_dmy_byte : 5; /* [16:12], r/w, 0x0 */ + uint32_t sf_if_2_adr_byte : 3; /* [19:17], r/w, 0x2 */ + uint32_t sf_if_2_cmd_byte : 3; /* [22:20], r/w, 0x0 */ + uint32_t sf_if_2_dat_rw : 1; /* [ 23], r/w, 0x1 */ + uint32_t sf_if_2_dat_en : 1; /* [ 24], r/w, 0x1 */ + uint32_t sf_if_2_dmy_en : 1; /* [ 25], r/w, 0x0 */ + uint32_t sf_if_2_adr_en : 1; /* [ 26], r/w, 0x1 */ + uint32_t sf_if_2_cmd_en : 1; /* [ 27], r/w, 0x1 */ + uint32_t sf_if_2_spi_mode : 3; /* [30:28], r/w, 0x0 */ + uint32_t sf_if_2_qpi_mode_en : 1; /* [ 31], r/w, 0x1 */ + } BF; + uint32_t WORD; + } sf_if_iahb_3; + + /* 0x7C : sf_if_iahb_4 */ + union { + struct + { + uint32_t sf_if_2_cmd_buf_0 : 32; /* [31: 0], r/w, 0x38000000 */ + } BF; + uint32_t WORD; + } sf_if_iahb_4; + + /* 0x80 : sf_if_iahb_5 */ + union { + struct + { + uint32_t sf_if_2_cmd_buf_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_if_iahb_5; + + /* 0x84 : sf_if_iahb_6 */ + union { + struct + { + uint32_t reserved_0_19 : 20; /* [19: 0], rsvd, 0x0 */ + uint32_t sf_if_3_cmd_byte : 3; /* [22:20], r/w, 0x0 */ + uint32_t reserved_23_27 : 5; /* [27:23], rsvd, 0x0 */ + uint32_t sf_if_3_spi_mode : 3; /* [30:28], r/w, 0x0 */ + uint32_t sf_if_3_qpi_mode_en : 1; /* [ 31], r/w, 0x1 */ + } BF; + uint32_t WORD; + } sf_if_iahb_6; + + /* 0x88 : sf_if_iahb_7 */ + union { + struct + { + uint32_t sf_if_3_cmd_buf_0 : 32; /* [31: 0], r/w, 0xc0000000L */ + } BF; + uint32_t WORD; + } sf_if_iahb_7; + + /* 0x8c reserved */ + uint8_t RESERVED0x8c[116]; + + /* 0x100 : sf_ctrl_prot_en_rd */ + union { + struct + { + uint32_t sf_ctrl_prot_en_rd : 1; /* [ 0], r, 0x1 */ + uint32_t sf_ctrl_id0_en_rd : 1; /* [ 1], r, 0x1 */ + uint32_t sf_ctrl_id1_en_rd : 1; /* [ 2], r, 0x1 */ + uint32_t reserved_3_29 : 27; /* [29: 3], rsvd, 0x0 */ + uint32_t sf_if_0_trig_wr_lock : 1; /* [ 30], r, 0x0 */ + uint32_t sf_dbg_dis : 1; /* [ 31], r, 0x0 */ + } BF; + uint32_t WORD; + } sf_ctrl_prot_en_rd; + + /* 0x104 : sf_ctrl_prot_en */ + union { + struct + { + uint32_t sf_ctrl_prot_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t sf_ctrl_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t sf_ctrl_id1_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_ctrl_prot_en; + + /* 0x108 reserved */ + uint8_t RESERVED0x108[248]; + + /* 0x200 : sf_aes_key_r0_0 */ + union { + struct + { + uint32_t sf_aes_key_r0_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_0; + + /* 0x204 : sf_aes_key_r0_1 */ + union { + struct + { + uint32_t sf_aes_key_r0_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_1; + + /* 0x208 : sf_aes_key_r0_2 */ + union { + struct + { + uint32_t sf_aes_key_r0_2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_2; + + /* 0x20C : sf_aes_key_r0_3 */ + union { + struct + { + uint32_t sf_aes_key_r0_3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_3; + + /* 0x210 : sf_aes_key_r0_4 */ + union { + struct + { + uint32_t sf_aes_key_r0_4 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_4; + + /* 0x214 : sf_aes_key_r0_5 */ + union { + struct + { + uint32_t sf_aes_key_r0_5 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_5; + + /* 0x218 : sf_aes_key_r0_6 */ + union { + struct + { + uint32_t sf_aes_key_r0_6 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_6; + + /* 0x21C : sf_aes_key_r0_7 */ + union { + struct + { + uint32_t sf_aes_key_r0_7 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r0_7; + + /* 0x220 : sf_aes_iv_r0_w0 */ + union { + struct + { + uint32_t sf_aes_iv_r0_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r0_w0; + + /* 0x224 : sf_aes_iv_r0_w1 */ + union { + struct + { + uint32_t sf_aes_iv_r0_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r0_w1; + + /* 0x228 : sf_aes_iv_r0_w2 */ + union { + struct + { + uint32_t sf_aes_iv_r0_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r0_w2; + + /* 0x22C : sf_aes_iv_r0_w3 */ + union { + struct + { + uint32_t sf_aes_iv_r0_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r0_w3; + + /* 0x230 : sf_aes_cfg_r0 */ + union { + struct + { + uint32_t sf_aes_region_r0_end : 14; /* [13: 0], r/w, 0x3fff */ + uint32_t sf_aes_region_r0_start : 14; /* [27:14], r/w, 0x0 */ + uint32_t reserved_28 : 1; /* [ 28], rsvd, 0x0 */ + uint32_t sf_aes_region_r0_hw_key_en : 1; /* [ 29], r/w, 0x0 */ + uint32_t sf_aes_region_r0_en : 1; /* [ 30], r/w, 0x0 */ + uint32_t sf_aes_region_r0_lock : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_cfg_r0; + + /* 0x234 reserved */ + uint8_t RESERVED0x234[204]; + + /* 0x300 : sf_aes_key_r1_0 */ + union { + struct + { + uint32_t sf_aes_key_r1_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_0; + + /* 0x304 : sf_aes_key_r1_1 */ + union { + struct + { + uint32_t sf_aes_key_r1_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_1; + + /* 0x308 : sf_aes_key_r1_2 */ + union { + struct + { + uint32_t sf_aes_key_r1_2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_2; + + /* 0x30C : sf_aes_key_r1_3 */ + union { + struct + { + uint32_t sf_aes_key_r1_3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_3; + + /* 0x310 : sf_aes_key_r1_4 */ + union { + struct + { + uint32_t sf_aes_key_r1_4 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_4; + + /* 0x314 : sf_aes_key_r1_5 */ + union { + struct + { + uint32_t sf_aes_key_r1_5 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_5; + + /* 0x318 : sf_aes_key_r1_6 */ + union { + struct + { + uint32_t sf_aes_key_r1_6 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_6; + + /* 0x31C : sf_aes_key_r1_7 */ + union { + struct + { + uint32_t sf_aes_key_r1_7 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r1_7; + + /* 0x320 : sf_aes_iv_r1_w0 */ + union { + struct + { + uint32_t sf_aes_iv_r1_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r1_w0; + + /* 0x324 : sf_aes_iv_r1_w1 */ + union { + struct + { + uint32_t sf_aes_iv_r1_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r1_w1; + + /* 0x328 : sf_aes_iv_r1_w2 */ + union { + struct + { + uint32_t sf_aes_iv_r1_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r1_w2; + + /* 0x32C : sf_aes_iv_r1_w3 */ + union { + struct + { + uint32_t sf_aes_iv_r1_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r1_w3; + + /* 0x330 : sf_aes_r1 */ + union { + struct + { + uint32_t sf_aes_r1_end : 14; /* [13: 0], r/w, 0x3fff */ + uint32_t sf_aes_r1_start : 14; /* [27:14], r/w, 0x0 */ + uint32_t reserved_28 : 1; /* [ 28], rsvd, 0x0 */ + uint32_t sf_aes_r1_hw_key_en : 1; /* [ 29], r/w, 0x0 */ + uint32_t sf_aes_r1_en : 1; /* [ 30], r/w, 0x0 */ + uint32_t sf_aes_r1_lock : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_r1; + + /* 0x334 reserved */ + uint8_t RESERVED0x334[204]; + + /* 0x400 : sf_aes_key_r2_0 */ + union { + struct + { + uint32_t sf_aes_key_r2_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_0; + + /* 0x404 : sf_aes_key_r2_1 */ + union { + struct + { + uint32_t sf_aes_key_r2_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_1; + + /* 0x408 : sf_aes_key_r2_2 */ + union { + struct + { + uint32_t sf_aes_key_r2_2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_2; + + /* 0x40C : sf_aes_key_r2_3 */ + union { + struct + { + uint32_t sf_aes_key_r2_3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_3; + + /* 0x410 : sf_aes_key_r2_4 */ + union { + struct + { + uint32_t sf_aes_key_r2_4 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_4; + + /* 0x414 : sf_aes_key_r2_5 */ + union { + struct + { + uint32_t sf_aes_key_r2_5 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_5; + + /* 0x418 : sf_aes_key_r2_6 */ + union { + struct + { + uint32_t sf_aes_key_r2_6 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_6; + + /* 0x41C : sf_aes_key_r2_7 */ + union { + struct + { + uint32_t sf_aes_key_r2_7 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_r2_7; + + /* 0x420 : sf_aes_iv_r2_w0 */ + union { + struct + { + uint32_t sf_aes_iv_r2_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r2_w0; + + /* 0x424 : sf_aes_iv_r2_w1 */ + union { + struct + { + uint32_t sf_aes_iv_r2_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r2_w1; + + /* 0x428 : sf_aes_iv_r2_w2 */ + union { + struct + { + uint32_t sf_aes_iv_r2_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r2_w2; + + /* 0x42C : sf_aes_iv_r2_w3 */ + union { + struct + { + uint32_t sf_aes_iv_r2_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_r2_w3; + + /* 0x430 : sf_aes_r2 */ + union { + struct + { + uint32_t sf_aes_r2_end : 14; /* [13: 0], r/w, 0x3fff */ + uint32_t sf_aes_r2_start : 14; /* [27:14], r/w, 0x0 */ + uint32_t reserved_28 : 1; /* [ 28], rsvd, 0x0 */ + uint32_t sf_aes_r2_hw_key_en : 1; /* [ 29], r/w, 0x0 */ + uint32_t sf_aes_r2_en : 1; /* [ 30], r/w, 0x0 */ + uint32_t sf_aes_r2_lock : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_r2; + + /* 0x434 : sf_id0_offset */ + union { + struct + { + uint32_t sf_id0_offset : 24; /* [23: 0], r/w, 0x0 */ + uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_id0_offset; + + /* 0x438 : sf_id1_offset */ + union { + struct + { + uint32_t sf_id1_offset : 24; /* [23: 0], r/w, 0x0 */ + uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } sf_id1_offset; +}; + +typedef volatile struct sf_ctrl_reg sf_ctrl_reg_t; + +/* 0x0 : sf_aes_key_0 */ +#define SF_CTRL_SF_AES_KEY_0_OFFSET (0x0) +#define SF_CTRL_SF_AES_KEY_0 SF_CTRL_SF_AES_KEY_0 +#define SF_CTRL_SF_AES_KEY_0_POS (0U) +#define SF_CTRL_SF_AES_KEY_0_LEN (32U) +#define SF_CTRL_SF_AES_KEY_0_MSK (((1U << SF_CTRL_SF_AES_KEY_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_0_POS) +#define SF_CTRL_SF_AES_KEY_0_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_0_POS)) + +/* 0x4 : sf_aes_key_1 */ +#define SF_CTRL_SF_AES_KEY_1_OFFSET (0x4) +#define SF_CTRL_SF_AES_KEY_1 SF_CTRL_SF_AES_KEY_1 +#define SF_CTRL_SF_AES_KEY_1_POS (0U) +#define SF_CTRL_SF_AES_KEY_1_LEN (32U) +#define SF_CTRL_SF_AES_KEY_1_MSK (((1U << SF_CTRL_SF_AES_KEY_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_1_POS) +#define SF_CTRL_SF_AES_KEY_1_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_1_POS)) + +/* 0x8 : sf_aes_key_2 */ +#define SF_CTRL_SF_AES_KEY_2_OFFSET (0x8) +#define SF_CTRL_SF_AES_KEY_2 SF_CTRL_SF_AES_KEY_2 +#define SF_CTRL_SF_AES_KEY_2_POS (0U) +#define SF_CTRL_SF_AES_KEY_2_LEN (32U) +#define SF_CTRL_SF_AES_KEY_2_MSK (((1U << SF_CTRL_SF_AES_KEY_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_2_POS) +#define SF_CTRL_SF_AES_KEY_2_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_2_POS)) + +/* 0xc : sf_aes_key_3 */ +#define SF_CTRL_SF_AES_KEY_3_OFFSET (0xc) +#define SF_CTRL_SF_AES_KEY_3 SF_CTRL_SF_AES_KEY_3 +#define SF_CTRL_SF_AES_KEY_3_POS (0U) +#define SF_CTRL_SF_AES_KEY_3_LEN (32U) +#define SF_CTRL_SF_AES_KEY_3_MSK (((1U << SF_CTRL_SF_AES_KEY_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_3_POS) +#define SF_CTRL_SF_AES_KEY_3_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_3_POS)) + +/* 0x10 : sf_aes_key_4 */ +#define SF_CTRL_SF_AES_KEY_4_OFFSET (0x10) +#define SF_CTRL_SF_AES_KEY_4 SF_CTRL_SF_AES_KEY_4 +#define SF_CTRL_SF_AES_KEY_4_POS (0U) +#define SF_CTRL_SF_AES_KEY_4_LEN (32U) +#define SF_CTRL_SF_AES_KEY_4_MSK (((1U << SF_CTRL_SF_AES_KEY_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_4_POS) +#define SF_CTRL_SF_AES_KEY_4_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_4_POS)) + +/* 0x14 : sf_aes_key_5 */ +#define SF_CTRL_SF_AES_KEY_5_OFFSET (0x14) +#define SF_CTRL_SF_AES_KEY_5 SF_CTRL_SF_AES_KEY_5 +#define SF_CTRL_SF_AES_KEY_5_POS (0U) +#define SF_CTRL_SF_AES_KEY_5_LEN (32U) +#define SF_CTRL_SF_AES_KEY_5_MSK (((1U << SF_CTRL_SF_AES_KEY_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_5_POS) +#define SF_CTRL_SF_AES_KEY_5_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_5_POS)) + +/* 0x18 : sf_aes_key_6 */ +#define SF_CTRL_SF_AES_KEY_6_OFFSET (0x18) +#define SF_CTRL_SF_AES_KEY_6 SF_CTRL_SF_AES_KEY_6 +#define SF_CTRL_SF_AES_KEY_6_POS (0U) +#define SF_CTRL_SF_AES_KEY_6_LEN (32U) +#define SF_CTRL_SF_AES_KEY_6_MSK (((1U << SF_CTRL_SF_AES_KEY_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_6_POS) +#define SF_CTRL_SF_AES_KEY_6_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_6_POS)) + +/* 0x1c : sf_aes_key_7 */ +#define SF_CTRL_SF_AES_KEY_7_OFFSET (0x1c) +#define SF_CTRL_SF_AES_KEY_7 SF_CTRL_SF_AES_KEY_7 +#define SF_CTRL_SF_AES_KEY_7_POS (0U) +#define SF_CTRL_SF_AES_KEY_7_LEN (32U) +#define SF_CTRL_SF_AES_KEY_7_MSK (((1U << SF_CTRL_SF_AES_KEY_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_7_POS) +#define SF_CTRL_SF_AES_KEY_7_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_7_POS)) + +/* 0x20 : sf_aes_iv_w0 */ +#define SF_CTRL_SF_AES_IV_W0_OFFSET (0x20) +#define SF_CTRL_SF_AES_IV_W0 SF_CTRL_SF_AES_IV_W0 +#define SF_CTRL_SF_AES_IV_W0_POS (0U) +#define SF_CTRL_SF_AES_IV_W0_LEN (32U) +#define SF_CTRL_SF_AES_IV_W0_MSK (((1U << SF_CTRL_SF_AES_IV_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_W0_POS) +#define SF_CTRL_SF_AES_IV_W0_UMSK (~(((1U << SF_CTRL_SF_AES_IV_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_W0_POS)) + +/* 0x24 : sf_aes_iv_w1 */ +#define SF_CTRL_SF_AES_IV_W1_OFFSET (0x24) +#define SF_CTRL_SF_AES_IV_W1 SF_CTRL_SF_AES_IV_W1 +#define SF_CTRL_SF_AES_IV_W1_POS (0U) +#define SF_CTRL_SF_AES_IV_W1_LEN (32U) +#define SF_CTRL_SF_AES_IV_W1_MSK (((1U << SF_CTRL_SF_AES_IV_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_W1_POS) +#define SF_CTRL_SF_AES_IV_W1_UMSK (~(((1U << SF_CTRL_SF_AES_IV_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_W1_POS)) + +/* 0x28 : sf_aes_iv_w2 */ +#define SF_CTRL_SF_AES_IV_W2_OFFSET (0x28) +#define SF_CTRL_SF_AES_IV_W2 SF_CTRL_SF_AES_IV_W2 +#define SF_CTRL_SF_AES_IV_W2_POS (0U) +#define SF_CTRL_SF_AES_IV_W2_LEN (32U) +#define SF_CTRL_SF_AES_IV_W2_MSK (((1U << SF_CTRL_SF_AES_IV_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_W2_POS) +#define SF_CTRL_SF_AES_IV_W2_UMSK (~(((1U << SF_CTRL_SF_AES_IV_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_W2_POS)) + +/* 0x2c : sf_aes_iv_w3 */ +#define SF_CTRL_SF_AES_IV_W3_OFFSET (0x2c) +#define SF_CTRL_SF_AES_IV_W3 SF_CTRL_SF_AES_IV_W3 +#define SF_CTRL_SF_AES_IV_W3_POS (0U) +#define SF_CTRL_SF_AES_IV_W3_LEN (32U) +#define SF_CTRL_SF_AES_IV_W3_MSK (((1U << SF_CTRL_SF_AES_IV_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_W3_POS) +#define SF_CTRL_SF_AES_IV_W3_UMSK (~(((1U << SF_CTRL_SF_AES_IV_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_W3_POS)) + +/* 0x30 : sf_aes_cfg */ +#define SF_CTRL_SF_AES_CFG_OFFSET (0x30) +#define SF_CTRL_SF_AES_REGION_END SF_CTRL_SF_AES_REGION_END +#define SF_CTRL_SF_AES_REGION_END_POS (0U) +#define SF_CTRL_SF_AES_REGION_END_LEN (14U) +#define SF_CTRL_SF_AES_REGION_END_MSK (((1U << SF_CTRL_SF_AES_REGION_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_END_POS) +#define SF_CTRL_SF_AES_REGION_END_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_END_POS)) +#define SF_CTRL_SF_AES_REGION_START SF_CTRL_SF_AES_REGION_START +#define SF_CTRL_SF_AES_REGION_START_POS (14U) +#define SF_CTRL_SF_AES_REGION_START_LEN (14U) +#define SF_CTRL_SF_AES_REGION_START_MSK (((1U << SF_CTRL_SF_AES_REGION_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_START_POS) +#define SF_CTRL_SF_AES_REGION_START_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_START_POS)) +#define SF_CTRL_SF_AES_REGION_HW_KEY_EN SF_CTRL_SF_AES_REGION_HW_KEY_EN +#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS (29U) +#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN (1U) +#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_MSK (((1U << SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS) +#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS)) +#define SF_CTRL_SF_AES_REGION_EN SF_CTRL_SF_AES_REGION_EN +#define SF_CTRL_SF_AES_REGION_EN_POS (30U) +#define SF_CTRL_SF_AES_REGION_EN_LEN (1U) +#define SF_CTRL_SF_AES_REGION_EN_MSK (((1U << SF_CTRL_SF_AES_REGION_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_EN_POS) +#define SF_CTRL_SF_AES_REGION_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_EN_POS)) +#define SF_CTRL_SF_AES_REGION_LOCK SF_CTRL_SF_AES_REGION_LOCK +#define SF_CTRL_SF_AES_REGION_LOCK_POS (31U) +#define SF_CTRL_SF_AES_REGION_LOCK_LEN (1U) +#define SF_CTRL_SF_AES_REGION_LOCK_MSK (((1U << SF_CTRL_SF_AES_REGION_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_LOCK_POS) +#define SF_CTRL_SF_AES_REGION_LOCK_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_LOCK_POS)) + +struct sf_ctrl_aes_region_reg { + /* 0x0 : sf_aes_key_0 */ + union { + struct + { + uint32_t sf_aes_key_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_0; + + /* 0x4 : sf_aes_key_1 */ + union { + struct + { + uint32_t sf_aes_key_1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_1; + + /* 0x8 : sf_aes_key_2 */ + union { + struct + { + uint32_t sf_aes_key_2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_2; + + /* 0xc : sf_aes_key_3 */ + union { + struct + { + uint32_t sf_aes_key_3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_3; + + /* 0x10 : sf_aes_key_4 */ + union { + struct + { + uint32_t sf_aes_key_4 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_4; + + /* 0x14 : sf_aes_key_5 */ + union { + struct + { + uint32_t sf_aes_key_5 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_5; + + /* 0x18 : sf_aes_key_6 */ + union { + struct + { + uint32_t sf_aes_key_6 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_6; + + /* 0x1c : sf_aes_key_7 */ + union { + struct + { + uint32_t sf_aes_key_7 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_key_7; + + /* 0x20 : sf_aes_iv_w0 */ + union { + struct + { + uint32_t sf_aes_iv_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_w0; + + /* 0x24 : sf_aes_iv_w1 */ + union { + struct + { + uint32_t sf_aes_iv_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_w1; + + /* 0x28 : sf_aes_iv_w2 */ + union { + struct + { + uint32_t sf_aes_iv_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_w2; + + /* 0x2c : sf_aes_iv_w3 */ + union { + struct + { + uint32_t sf_aes_iv_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_iv_w3; + + /* 0x30 : sf_aes_cfg */ + union { + struct + { + uint32_t sf_aes_region_end : 14; /* [13: 0], r/w, 0x3fff */ + uint32_t sf_aes_region_start : 14; /* [27:14], r/w, 0x0 */ + uint32_t reserved_28 : 1; /* [ 28], rsvd, 0x0 */ + uint32_t sf_aes_region_hw_key_en : 1; /* [ 29], r/w, 0x0 */ + uint32_t sf_aes_region_en : 1; /* [ 30], r/w, 0x0 */ + uint32_t sf_aes_region_lock : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } sf_aes_cfg; +}; + +typedef volatile struct sf_ctrl_aes_region_reg sf_ctrl_aes_region_reg_t; + +#define SF_CTRL_AES_REGION_OFFSET 0x200 + +#endif /* __SF_CTRL_REG_H__ */ diff --git a/drivers/soc/bl602/bl602_std/src/bl602_clock.c b/drivers/soc/bl602/bl602_std/src/bl602_clock.c new file mode 100644 index 00000000..eb1c6c12 --- /dev/null +++ b/drivers/soc/bl602/bl602_std/src/bl602_clock.c @@ -0,0 +1,601 @@ +/** + ****************************************************************************** + * @file bl602_clock.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_clock.h" +// #include "bl602_pwm.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup CLOCK + * @{ + */ + +/** @defgroup CLOCK_Private_Macros + * @{ + */ + +/*@} end of group CLOCK_Private_Macros */ + +/** @defgroup CLOCK_Private_Types + * @{ + */ + +/*@} end of group CLOCK_Private_Types */ + +/** @defgroup CLOCK_Private_Variables + * @{ + */ +//static Clock_Cfg_Type clkCfg; + +/*@} end of group CLOCK_Private_Variables */ + +/** @defgroup CLOCK_Global_Variables + * @{ + */ + +/*@} end of group CLOCK_Global_Variables */ + +/** @defgroup CLOCK_Private_Fun_Declaration + * @{ + */ + +/*@} end of group CLOCK_Private_Fun_Declaration */ + +/** @defgroup CLOCK_Private_Functions + * @{ + */ + +/*@} end of group CLOCK_Private_Functions */ + +/** @defgroup CLOCK_Public_Functions + * @{ + */ + +static uint32_t ATTR_CLOCK_SECTION Clock_Xtal_Output(void) +{ + uint32_t tmpVal; + + /* get clkpll_sdmin */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN); + + switch (tmpVal) { + case 0x500000: + /* 24m */ + return (24 * 1000 * 1000); + + case 0x3C0000: + /* 32m */ + return (32 * 1000 * 1000); + + case 0x320000: + /* 38.4m */ + return (384 * 100 * 1000); + + case 0x300000: + /* 40m */ + return (40 * 1000 * 1000); + + case 0x49D39D: + /* 26m */ + return (26 * 1000 * 1000); + + default: + /* 32m */ + return (32 * 1000 * 1000); + } +} + +static uint32_t ATTR_CLOCK_SECTION Clock_XClk_Mux_Output(uint8_t sel) +{ + if (sel == 0) { + /* rc32m */ + return (32 * 1000 * 1000); + } else { + /* xtal */ + return Clock_Xtal_Output(); + } +} + +static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_XClk_Sel_Val(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_ROOT_CLK_SEL); + + return (tmpVal & 0x1); +} + +static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_Root_Clk_Sel_Val(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_ROOT_CLK_SEL); + + return ((tmpVal >> 1) & 0x1); +} + +static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Clk_Mux_Output(uint8_t sel) +{ + if (sel == 0) { + /* pll 48m */ + return (48 * 1000 * 1000); + } else if (sel == 1) { + /* pll 120m */ + return (120 * 1000 * 1000); + } else if (sel == 2) { + /* pll 160m */ + return (160 * 1000 * 1000); + } else if (sel == 3) { + /* pll 192m */ + return (192 * 1000 * 1000); + } else { + return 0; + } +} + +static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Root_Clk_Mux_Output(uint8_t sel) +{ + uint32_t tmpVal; + + if (sel == 0) { + /* xclk */ + return Clock_XClk_Mux_Output(Clock_Get_MCU_XClk_Sel_Val()); + } else if (sel == 1) { + /* pll */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PLL_SEL); + return Clock_MCU_Clk_Mux_Output(tmpVal); + } else { + return 0; + } +} + +static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_HClk_Div_Val(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV); +} + +static uint8_t ATTR_CLOCK_SECTION Clock_Get_Peri_BClk_Div_Val(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV); +} + +static uint32_t ATTR_CLOCK_SECTION Clock_F32k_Mux_Output(uint8_t sel) +{ + uint32_t tmpVal; + uint32_t div = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + div = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV); + + if (sel == 0) { + /* src32K */ + return (32 * 1000); + } else if (sel == 1) { + /* xtal 32K */ + return (32 * 1000); + } else { + return Clock_Xtal_Output() / (div + 1); + } +} + +static uint8_t ATTR_CLOCK_SECTION Clock_Get_F32k_Sel_Val(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + + return BL_GET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL); +} + +/****************************************************************************/ /** + * @brief Get System Clock + * + * @param type: System clock type + * + * @return System clock value + * +*******************************************************************************/ +uint32_t Clock_System_Clock_Get(BL_System_Clock_Type type) +{ + uint32_t clock = 0; + uint32_t div = 0; + + switch (type) { + case BL_SYSTEM_CLOCK_XCLK: + /*!< mcu xclk clock */ + return Clock_XClk_Mux_Output(Clock_Get_MCU_XClk_Sel_Val()); + + case BL_SYSTEM_CLOCK_ROOT: + /*!< mcu root clock */ + return Clock_MCU_Root_Clk_Mux_Output(Clock_Get_MCU_Root_Clk_Sel_Val()); + + case BL_SYSTEM_CLOCK_FCLK: + /*!< mcu fast clock/cpu clock */ + clock = Clock_MCU_Root_Clk_Mux_Output(Clock_Get_MCU_Root_Clk_Sel_Val()); + div = Clock_Get_MCU_HClk_Div_Val(); + return clock / (div + 1); + + case BL_SYSTEM_CLOCK_BCLK: + /*!< mcu peri bus clock */ + clock = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_FCLK); + div = Clock_Get_Peri_BClk_Div_Val(); + return clock / (div + 1); + + case BL_SYSTEM_CLOCK_XTAL: + /*!< xtal clock */ + return Clock_Xtal_Output(); + + case BL_SYSTEM_CLOCK_F32K: + /*!< f32k clock */ + return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val()); + + default: + return 0; + } +} + +static uint32_t ATTR_CLOCK_SECTION Clock_UART_Clk_Mux_Output(uint8_t sel) +{ + if (sel == 0) { + /* fclk */ + return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_FCLK); + } else { + /* 160m */ + return (160 * 1000 * 1000); + } +} + +static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Clk_Sel_Val(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + + return BL_GET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL); +} + +static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Div_Val(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV); +} + +static uint32_t ATTR_CLOCK_SECTION Clock_SPI_Clk_Mux_Output(void) +{ + /* pbclk */ + return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK); +} + +static uint8_t ATTR_CLOCK_SECTION Clock_Get_SPI_Div_Val(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV); +} + +static uint32_t ATTR_CLOCK_SECTION Clock_I2C_Clk_Mux_Output() +{ + /* pbclk */ + return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK); +} + +static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2C_Div_Val(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV); +} + +static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Div_Val(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV); +} + +static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Output(uint8_t sel) +{ + if (sel == 0) { + /* 96m */ + return (96 * 1000 * 1000); + } else { + /* xclk */ + return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK); + } +} + +static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_32M_Clk_Sel_Val(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL); +} + +static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Mux_Output(uint8_t sel) +{ + uint32_t div = 0; + + if (sel == 1) { + /* f32k clk */ + return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val()); + } else { + div = Clock_Get_GPADC_Div_Val(); + return Clock_GPADC_Clk_Output(Clock_Get_GPADC_32M_Clk_Sel_Val()) / (div + 1); + } +} + +static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Clk_Sel_Val(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG); + + return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_EN); +} + +static uint32_t ATTR_CLOCK_SECTION Clock_GPDAC_Clk_Mux_Output(uint8_t sel) +{ + if (sel == 0) { + /* pll 32m */ + return (32 * 1000 * 1000); + } else { + /* xclk */ + return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK); + } +} + +static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Div_Val(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV); +} + +static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Clk_Sel_Val(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL); +} + +// static uint32_t ATTR_CLOCK_SECTION Clock_PWM_Clk_Mux_Output(uint8_t sel) +// { +// if (sel == 0) { +// /* xclk */ +// return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK); +// } else if (sel == 1) { +// /* pbclk */ +// return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK); +// } else { +// /* f32k clk */ +// return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val()); +// } +// } + +// static uint8_t ATTR_CLOCK_SECTION Clock_Get_PWM_Div_Val(void) +// { +// uint32_t tmpVal; + +// tmpVal = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CLKDIV); + +// return tmpVal; +// } + +// static uint8_t ATTR_CLOCK_SECTION Clock_Get_PWM_Clk_Sel_Val(void) +// { +// uint32_t tmpVal; + +// tmpVal = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CONFIG); + +// return BL_GET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL); +// } + +static uint32_t ATTR_CLOCK_SECTION Clock_IR_Clk_Mux_Output(void) +{ + /* xclk */ + return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK); +} + +static uint8_t ATTR_CLOCK_SECTION Clock_Get_IR_Div_Val(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV); +} + +static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel2_Val(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2); +} + +static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel) +{ + if (sel == 0) { + /* 120m */ + return (120 * 1000 * 1000); + } else if (sel == 1) { + /* xclk */ + return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK); + } else { + /* 48m */ + return (48 * 1000 * 1000); + } +} + +static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL_Clk_Mux_Output(uint8_t sel) +{ + if (sel == 0) { + /* sf sel2 */ + return Clock_SF_SEL2_Clk_Mux_Output(Clock_Get_SF_Clk_Sel2_Val()); + } else if (sel == 1) { + /* 80m */ + return (80 * 1000 * 1000); + } else if (sel == 2) { + /* pbclk */ + return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK); + } else { + /* 96m */ + return (96 * 1000 * 1000); + } +} + +static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel_Val(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL); +} + +static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Div_Val(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV); +} + +/****************************************************************************/ /** + * @brief Get Peripheral Clock + * + * @param type: Peripheral clock type + * + * @return Peripheral clock value + * +*******************************************************************************/ +uint32_t Clock_Peripheral_Clock_Get(BL_Peripheral_Type type) +{ + uint32_t clock = 0; + uint32_t div = 0; + + switch (type) { + /*!< uart0 clock */ + case BL_PERIPHERAL_CLOCK_UART0: + ATTR_FALLTHROUGH(); + + /*!< uart1 clock */ + case BL_PERIPHERAL_CLOCK_UART1: + clock = Clock_UART_Clk_Mux_Output(Clock_Get_UART_Clk_Sel_Val()); + div = Clock_Get_UART_Div_Val(); + return clock / (div + 1); + + /*!< FLASH clock */ + case BL_PERIPHERAL_CLOCK_FLASH: + clock = Clock_SF_SEL_Clk_Mux_Output(Clock_Get_SF_Clk_Sel_Val()); + div = Clock_Get_SF_Div_Val(); + return clock / (div + 1); + + /*!< spi0 clock */ + case BL_PERIPHERAL_CLOCK_SPI0: + clock = Clock_SPI_Clk_Mux_Output(); + div = Clock_Get_SPI_Div_Val(); + return clock / (div + 1); + + /*!< i2c0 clock */ + case BL_PERIPHERAL_CLOCK_I2C0: + clock = Clock_I2C_Clk_Mux_Output(); + div = Clock_Get_I2C_Div_Val(); + return clock / (div + 1); + + /*!< GPADC clock */ + case BL_PERIPHERAL_CLOCK_GPADC: + return Clock_GPADC_Clk_Mux_Output(Clock_Get_GPADC_Clk_Sel_Val()); + + /*!< GPDAC clock */ + case BL_PERIPHERAL_CLOCK_GPDAC: + clock = Clock_GPDAC_Clk_Mux_Output(Clock_Get_GPDAC_Clk_Sel_Val()); + div = Clock_Get_GPDAC_Div_Val(); + return clock / (div + 1); + + /*!< PWM clock */ + // case BL_PERIPHERAL_CLOCK_PWM: + // clock = Clock_PWM_Clk_Mux_Output(Clock_Get_PWM_Clk_Sel_Val()); + // div = Clock_Get_PWM_Div_Val(); + // return clock / div; + + /*!< IR clock */ + case BL_PERIPHERAL_CLOCK_IR: + clock = Clock_IR_Clk_Mux_Output(); + div = Clock_Get_IR_Div_Val(); + return clock / (div + 1); + + default: + return 0; + } +} + +/*@} end of group CLOCK_Public_Functions */ + +/*@} end of group CLOCK */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/soc/bl602/bl602_std/src/bl602_glb.c b/drivers/soc/bl602/bl602_std/src/bl602_glb.c new file mode 100644 index 00000000..324f4840 --- /dev/null +++ b/drivers/soc/bl602/bl602_std/src/bl602_glb.c @@ -0,0 +1,2619 @@ +/** + ****************************************************************************** + * @file bl602_glb.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_glb.h" +#include "bl602_hbn.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup GLB + * @{ + */ + +/** @defgroup GLB_Private_Macros + * @{ + */ +#define GLB_CLK_SET_DUMMY_WAIT \ + { \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + } +#define GLB_GPIO_Get_Reg(pin) (glb_gpio_reg_t *)(GLB_BASE + GLB_GPIO_OFFSET + (pin / 2) * 4) +#define GLB_GPIO_INT0_NUM (23) +#define GLB_REG_BCLK_DIS_TRUE (*(volatile uint32_t *)(0x40000FFC) = (0x00000001)) +#define GLB_REG_BCLK_DIS_FALSE (*(volatile uint32_t *)(0x40000FFC) = (0x00000000)) +#define GLB_GPIO_INT0_CLEAR_TIMEOUT (32) + +/*@} end of group GLB_Private_Macros */ + +/** @defgroup GLB_Private_Types + * @{ + */ + +/*@} end of group GLB_Private_Types */ + +/** @defgroup GLB_Private_Variables + * @{ + */ +static intCallback_Type *glbBmxErrIntCbfArra[BMX_ERR_INT_ALL] = { NULL }; +static intCallback_Type *glbBmxToIntCbfArra[BMX_TO_INT_ALL] = { NULL }; +static intCallback_Type *glbGpioInt0CbfArra[GLB_GPIO_INT0_NUM] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL }; + +/*@} end of group GLB_Private_Variables */ + +/** @defgroup GLB_Global_Variables + * @{ + */ + +/*@} end of group GLB_Global_Variables */ + +/** @defgroup GLB_Private_Fun_Declaration + * @{ + */ + +/*@} end of group GLB_Private_Fun_Declaration */ + +/** @defgroup GLB_Private_Functions + * @{ + */ + +/*@} end of group GLB_Private_Functions */ + +/** @defgroup GLB_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief get root clock selection + * + * @param None + * + * @return root clock selection + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +GLB_ROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_Root_CLK_Sel(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + + switch (BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_ROOT_CLK_SEL)) { + case 0: + return GLB_ROOT_CLK_RC32M; + + case 1: + return GLB_ROOT_CLK_XTAL; + + case 2: + return GLB_ROOT_CLK_PLL; + + case 3: + return GLB_ROOT_CLK_PLL; + + default: + return GLB_ROOT_CLK_RC32M; + } +} +#endif + +/****************************************************************************/ /** + * @brief Set System clock divider + * + * @param hclkDiv: HCLK divider + * @param bclkDiv: BCLK divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv) +{ + /***********************************************************************************/ + /* NOTE */ + /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */ + /* OCRAM use bclk as source clock. Pay attention to risks when using this API. */ + /***********************************************************************************/ + uint32_t tmpVal; + + /* recommended: fclk<=160MHz, bclk<=80MHz */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, hclkDiv); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, bclkDiv); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + GLB_REG_BCLK_DIS_TRUE; + GLB_REG_BCLK_DIS_FALSE; + SystemCoreClockSet(SystemCoreClockGet() / ((uint16_t)hclkDiv + 1)); + GLB_CLK_SET_DUMMY_WAIT; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_HCLK_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BCLK_EN); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + GLB_CLK_SET_DUMMY_WAIT; + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Get Bus clock divider + * + * @param None + * + * @return Clock Divider + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint8_t ATTR_CLOCK_SECTION GLB_Get_BCLK_Div(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV); +} +#endif + +/****************************************************************************/ /** + * @brief Get CPU clock divider + * + * @param None + * + * @return Clock Divider + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint8_t ATTR_CLOCK_SECTION GLB_Get_HCLK_Div(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV); +} +#endif + +/****************************************************************************/ /** + * @brief update SystemCoreClock value + * + * @param xtalType: XTAL frequency type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION Update_SystemCoreClockWith_XTAL(GLB_PLL_XTAL_Type xtalType) +{ + CHECK_PARAM(IS_GLB_PLL_XTAL_TYPE(xtalType)); + + switch (xtalType) { + case GLB_PLL_XTAL_NONE: + break; + + case GLB_PLL_XTAL_24M: + SystemCoreClockSet(24000000); + break; + + case GLB_PLL_XTAL_32M: + SystemCoreClockSet(32000000); + break; + + case GLB_PLL_XTAL_38P4M: + SystemCoreClockSet(38400000); + break; + + case GLB_PLL_XTAL_40M: + SystemCoreClockSet(40000000); + break; + + case GLB_PLL_XTAL_26M: + SystemCoreClockSet(26000000); + break; + + case GLB_PLL_XTAL_RC32M: + SystemCoreClockSet(32000000); + break; + + default: + break; + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Set System clock + * + * @param xtalType: XTAL frequency type + * @param clkFreq: clock frequency selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK(GLB_PLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GLB_PLL_XTAL_TYPE(xtalType)); + CHECK_PARAM(IS_GLB_SYS_CLK_TYPE(clkFreq)); + + /* reg_bclk_en = reg_hclk_en = reg_fclk_en = 1, cannot be zero */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BCLK_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_HCLK_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_FCLK_EN); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + + /* Before config XTAL and PLL ,make sure root clk is from RC32M */ + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M); + GLB_Set_System_CLK_Div(0, 0); + SystemCoreClockSet(32 * 1000 * 1000); + + /* Select PKA clock from hclk */ + GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_HCLK); + + if (xtalType == GLB_PLL_XTAL_NONE) { + if (clkFreq == GLB_SYS_CLK_RC32M) { + return SUCCESS; + } else { + return ERROR; + } + } + + if (xtalType != GLB_PLL_XTAL_RC32M) { + /* power on xtal first */ + AON_Power_On_XTAL(); + } + + /* always power up PLL and enable all PLL clock output */ + PDS_Power_On_PLL((PDS_PLL_XTAL_Type)xtalType); + BL602_Delay_US(55); + PDS_Enable_PLL_All_Clks(); + + /* reg_pll_en = 1, cannot be zero */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PLL_EN); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + + /* select pll output clock before select root clock */ + if (clkFreq >= GLB_SYS_CLK_PLL48M) { + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PLL_SEL, clkFreq - GLB_SYS_CLK_PLL48M); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + } + + /* select root clock */ + switch (clkFreq) { + case GLB_SYS_CLK_RC32M: + break; + + case GLB_SYS_CLK_XTAL: + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + Update_SystemCoreClockWith_XTAL(xtalType); + break; + + case GLB_SYS_CLK_PLL48M: + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_PLL); + SystemCoreClockSet(48 * 1000 * 1000); + break; + + case GLB_SYS_CLK_PLL120M: + GLB_Set_System_CLK_Div(0, 1); + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_PLL); + SystemCoreClockSet(120 * 1000 * 1000); + break; + + case GLB_SYS_CLK_PLL160M: + L1C_IROM_2T_Access_Set(ENABLE); + GLB_Set_System_CLK_Div(0, 1); + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_PLL); + SystemCoreClockSet(160 * 1000 * 1000); + break; + + case GLB_SYS_CLK_PLL192M: + L1C_IROM_2T_Access_Set(ENABLE); + GLB_Set_System_CLK_Div(0, 1); + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_PLL); + SystemCoreClockSet(192 * 1000 * 1000); + break; + + default: + break; + } + + GLB_CLK_SET_DUMMY_WAIT; + + /* select PKA clock from 120M since we power up PLL */ + GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_PLL120M); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief This is demo for user that use RC32M as default bootup clock instead of PLL,when APP is + * started, this function can be called to set PLL to 160M + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION System_Core_Clock_Update_From_RC32M(void) +{ + SF_Ctrl_Cfg_Type sfCtrlCfg = { + .owner = SF_CTRL_OWNER_IAHB, + .clkDelay = 1, + .clkInvert = 1, + .rxClkInvert = 1, + .doDelay = 0, + .diDelay = 0, + .oeDelay = 0, + }; + /* Use RC32M as PLL ref source to set up PLL to 160M */ + GLB_Set_System_CLK(GLB_PLL_XTAL_RC32M, GLB_SYS_CLK_PLL160M); + /* Flash controller also need changes since system (bus) clock changed */ + SF_Ctrl_Enable(&sfCtrlCfg); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief set BLE clock + * + * @param enable: Enable or disable BLE clock + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_BLE_CLK(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BLE_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BLE_EN); + } + + BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set wifi core clock divider + * + * @param clkDiv: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_WiFi_Core_CLK(uint8_t clkDiv) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((clkDiv <= 0x3)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFI_MAC_CORE_DIV, clkDiv); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set wifi encryption clock + * + * @param clkDiv: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_WiFi_Encrypt_CLK(uint8_t clkDiv) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((clkDiv <= 0x3)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFI_MAC_WT_DIV, clkDiv); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set DMA clock + * + * @param enable: Enable or disable BLE clock + * @param clk: DMA clock type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN); + + if (enable) { + tmpVal2 |= (1 << clk); + } else { + tmpVal2 &= (~(1 << clk)); + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN, tmpVal2); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set IR clock divider + * + * @param enable: enable or disable IR clock + * @param clkSel: IR clock type + * @param div: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_IR_CLK_SRC_TYPE(clkSel)); + CHECK_PARAM((div <= 0x3F)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV, div); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_IR_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN); + } + + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set sflash clock + * + * @param enable: enable or disable sflash clock + * @param clkSel: sflash clock type + * @param div: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div) +{ + uint32_t tmpVal = 0; + GLB_PLL_CLK_Type clk; + + CHECK_PARAM(IS_GLB_SFLASH_CLK_TYPE(clkSel)); + CHECK_PARAM((div <= 0x7)); + + /* disable SFLASH clock first */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + /* Select flash clock, all Flash CLKs are divied by PLL_480M */ + clk = GLB_PLL_CLK_480M; + PDS_Enable_PLL_Clk((PDS_PLL_CLK_Type)clk); + /* clock divider */ + /* Select flash clock, all Flash CLKs are divied by PLL_480M */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV, div); + + switch (clkSel) { + case GLB_SFLASH_CLK_120M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x0); + break; + + case GLB_SFLASH_CLK_XTAL: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x1); + break; + + case GLB_SFLASH_CLK_48M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x3); + break; + + case GLB_SFLASH_CLK_80M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x1); + break; + + case GLB_SFLASH_CLK_BCLK: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x2); + break; + + case GLB_SFLASH_CLK_96M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x3); + break; + + default: + break; + } + + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + /* enable or disable flash clock */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SF_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN); + } + + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Set UART clock + * + * @param enable: Enable or disable UART clock + * @param clkSel: UART clock type + * @param div: UART clock divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((div <= 0x7)); + CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel)); + + /* disable UART clock first */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + /* Set div */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV, div); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + /* Select clock source for uart */ + HBN_Set_UART_CLK_Sel(clkSel); + + /* Set enable or disable */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_UART_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN); + } + + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set I2C clock + * + * @param enable: Enable or disable I2C clock + * @param div: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, uint8_t div) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV, div); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_I2C_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN); + } + + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set SPI clock + * + * @param enable: Enable or disable SPI clock + * @param div: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, uint8_t div) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((div <= 0x1F)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV, div); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SPI_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN); + } + + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief select PKA clock source + * + * @param clkSel: PKA clock selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_PKA_CLK_TYPE(clkSel)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL, clkSel); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Software system reset + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_SW_System_Reset(void) +{ + /***********************************************************************************/ + /* NOTE */ + /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */ + /* OCRAM use bclk as source clock. Pay attention to risks when using this API. */ + /***********************************************************************************/ + uint32_t tmpVal; + + /* Swicth clock to 32M as default */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + GLB_CLK_SET_DUMMY_WAIT; + + /* HCLK is RC32M , so BCLK/HCLK no need divider */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + GLB_REG_BCLK_DIS_TRUE; + GLB_REG_BCLK_DIS_FALSE; + GLB_CLK_SET_DUMMY_WAIT; + + /* Do reset */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + /* waiting for reset */ + while (1) { + BL602_Delay_US(10); + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Software CPU reset + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_SW_CPU_Reset(void) +{ + /***********************************************************************************/ + /* NOTE */ + /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */ + /* OCRAM use bclk as source clock. Pay attention to risks when using this API. */ + /***********************************************************************************/ + uint32_t tmpVal; + + /* Swicth clock to 32M as default */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + GLB_CLK_SET_DUMMY_WAIT; + + /* HCLK is RC32M , so BCLK/HCLK no need divider */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + GLB_REG_BCLK_DIS_TRUE; + GLB_REG_BCLK_DIS_FALSE; + GLB_CLK_SET_DUMMY_WAIT; + + /* Do reset */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + /* waiting for reset */ + while (1) { + BL602_Delay_US(10); + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Software power on reset + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_SW_POR_Reset(void) +{ + /***********************************************************************************/ + /* NOTE */ + /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */ + /* OCRAM use bclk as source clock. Pay attention to risks when using this API. */ + /***********************************************************************************/ + uint32_t tmpVal; + + /* Swicth clock to 32M as default */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + GLB_CLK_SET_DUMMY_WAIT; + + /* HCLK is RC32M , so BCLK/HCLK no need divider */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + GLB_REG_BCLK_DIS_TRUE; + GLB_REG_BCLK_DIS_FALSE; + GLB_CLK_SET_DUMMY_WAIT; + + /* Do reset */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + /* waiting for reset */ + while (1) { + BL602_Delay_US(10); + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Reset slave 1 + * + * @param slave1: slave num + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_AHB_Slave1_Reset(BL_AHB_Slave1_Type slave1) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1); + tmpVal &= (~(1 << slave1)); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal); + BL_DRV_DUMMY; + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1); + tmpVal |= (1 << slave1); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal); + BL_DRV_DUMMY; + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1); + tmpVal &= (~(1 << slave1)); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief clock gate + * + * @param enable: ENABLE or DISABLE + * @param slave1: AHB slaveClk type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_AHB_Slave1_Clock_Gate(uint8_t enable, BL_AHB_Slave1_Type slave1) +{ + uint32_t tmpVal = 0; + + if ((BL_AHB_SLAVE1_GLB == slave1) || (BL_AHB_SLAVE1_TZ2 == slave1) || + (BL_AHB_SLAVE1_CCI == slave1) || (BL_AHB_SLAVE1_L1C == slave1) || + (BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM == slave1)) { + /* not support */ + return ERROR; + } + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); + + if (enable) { + /* clear bit means clock gate */ + tmpVal &= (~(1 << slave1)); + } else { + /* set bit means clock pass */ + tmpVal |= (1 << slave1); + } + + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX init + * + * @param BmxCfg: BMX config + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_Init(BMX_Cfg_Type *BmxCfg) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((BmxCfg->timeoutEn) <= 0xF); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_TIMEOUT_EN, BmxCfg->timeoutEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_EN, BmxCfg->errEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_ARB_MODE, BmxCfg->arbMod); + BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(BMX_ERR_IRQn, BMX_ERR_IRQHandler); + Interrupt_Handler_Register(BMX_TO_IRQn, BMX_TO_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX address monitor enable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_Addr_Monitor_Enable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BMX_ERR_ADDR_DIS); + BL_WR_REG(GLB_BASE, GLB_BMX_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX address monitor disable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_Addr_Monitor_Disable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BMX_ERR_ADDR_DIS); + BL_WR_REG(GLB_BASE, GLB_BMX_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX bus error response enable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_BusErrResponse_Enable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BMX_ERR_EN); + BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX bus error response disable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_BusErrResponse_Disable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BMX_ERR_EN); + BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get BMX error status + * + * @param errType: BMX error status type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_BMX_BUS_ERR_TYPE(errType)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2); + + if (errType == BMX_BUS_ERR_TRUSTZONE_DECODE) { + return BL_GET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_TZ) ? SET : RESET; + } else { + return BL_GET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_DEC) ? SET : RESET; + } +} + +/****************************************************************************/ /** + * @brief Get BMX error address + * + * @param None + * + * @return NP BMX error address + * +*******************************************************************************/ +uint32_t GLB_BMX_Get_Err_Addr(void) +{ + return BL_RD_REG(GLB_BASE, GLB_BMX_ERR_ADDR); +} + +/****************************************************************************/ /** + * @brief BMX error interrupt callback install + * + * @param intType: BMX error interrupt type + * @param cbFun: callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type BMX_ERR_INT_Callback_Install(BMX_ERR_INT_Type intType, intCallback_Type *cbFun) +{ + CHECK_PARAM(IS_BMX_ERR_INT_TYPE(intType)); + + glbBmxErrIntCbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX ERR interrupt IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void BMX_ERR_IRQHandler(void) +{ + BMX_ERR_INT_Type intType; + + for (intType = BMX_ERR_INT_ERR; intType < BMX_ERR_INT_ALL; intType++) { + if (glbBmxErrIntCbfArra[intType] != NULL) { + glbBmxErrIntCbfArra[intType](); + } + } + + while (1) { + MSG("BMX_ERR_IRQHandler\r\n"); + BL602_Delay_MS(1000); + } +} +#endif + +/****************************************************************************/ /** + * @brief BMX timeout interrupt callback install + * + * @param intType: BMX timeout interrupt type + * @param cbFun: callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun) +{ + CHECK_PARAM(IS_BMX_TO_INT_TYPE(intType)); + + glbBmxToIntCbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX Time Out interrupt IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void BMX_TO_IRQHandler(void) +{ + BMX_TO_INT_Type intType; + + for (intType = BMX_TO_INT_TIMEOUT; intType < BMX_TO_INT_ALL; intType++) { + if (glbBmxToIntCbfArra[intType] != NULL) { + glbBmxToIntCbfArra[intType](); + } + } + + while (1) { + MSG("BMX_TO_IRQHandler\r\n"); + BL602_Delay_MS(1000); + } +} +#endif + +/****************************************************************************/ /** + * @brief set sram_ret value + * + * @param value: value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_SRAM_RET(uint32_t value) +{ + BL_WR_REG(GLB_BASE, GLB_SRAM_RET, value); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get sram_ret value + * + * @param None + * + * @return value + * +*******************************************************************************/ +uint32_t GLB_Get_SRAM_RET(void) +{ + return BL_RD_REG(GLB_BASE, GLB_SRAM_RET); +} + +/****************************************************************************/ /** + * @brief set sram_slp value + * + * @param value: value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value) +{ + BL_WR_REG(GLB_BASE, GLB_SRAM_SLP, value); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get sram_slp value + * + * @param None + * + * @return value + * +*******************************************************************************/ +uint32_t GLB_Get_SRAM_SLP(void) +{ + return BL_RD_REG(GLB_BASE, GLB_SRAM_SLP); +} + +/****************************************************************************/ /** + * @brief set sram_param value + * + * @param value: value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value) +{ + BL_WR_REG(GLB_BASE, GLB_SRAM_PARM, value); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get sram_parm value + * + * @param None + * + * @return value + * +*******************************************************************************/ +uint32_t GLB_Get_SRAM_PARM(void) +{ + return BL_RD_REG(GLB_BASE, GLB_SRAM_PARM); +} + +/****************************************************************************/ /** + * @brief select EM type + * + * @param emType: EM type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_EM_TYPE(emType)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, emType); + BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief swap UART gpio pins sig function + * + * @param swapSel: UART swap set gpio pins selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_UART_Sig_Swap_Set(uint8_t swapSel) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((swapSel <= 0x7)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, swapSel); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief swap JTAG gpio pins function + * + * @param swapSel: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_JTAG_Sig_Swap_Set(uint8_t swapSel) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((swapSel <= 0x3F)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_JTAG_SWAP_SET, swapSel); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief swap SPI0 MOSI with MISO + * + * @param newState: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Swap_SPI_0_MOSI_With_MISO(BL_Fun_Type newState) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_SWAP, newState); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select SPI_0 act mode + * + * @param mod: SPI work mode + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GLB_SPI_PAD_ACT_AS_TYPE(mod)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_MASTER_MODE, mod); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief use internal flash + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_Select_Internal_Flash(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SEL_EMBEDDED_SFLASH); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief use external flash + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_Select_External_Flash(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SEL_EMBEDDED_SFLASH); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Deswap internal flash IO3 and IO0 pin + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_Deswap_Flash_Pin(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Swap internal flash IO3 and IO0 pin + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_Swap_Flash_Pin(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief set MTimer clock + * + * @param enable: enable or disable MTimer clock + * @param clkSel: clock selection + * @param div: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_MTimer_CLK(uint8_t enable, GLB_MTIMER_CLK_Type clkSel, uint32_t div) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GLB_MTIMER_CLK_TYPE(clkSel)); + CHECK_PARAM((div <= 0x1FFFF)); + + /* disable MTimer clock first */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CPU_RTC_EN); + BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CPU_RTC_SEL, clkSel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CPU_RTC_DIV, div); + BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CPU_RTC_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CPU_RTC_EN); + } + + BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set ADC clock + * + * @param enable: enable frequency divider or not + * @param clkSel: ADC clock selection + * @param div: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GLB_ADC_CLK_TYPE(clkSel)); + + /* disable ADC clock first */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN); + BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV, div); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL, clkSel); + BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN); + } + + BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set DAC clock + * + * @param enable: enable frequency divider or not + * @param clkSel: ADC clock selection + * @param div: src divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_DAC_CLK(uint8_t enable, GLB_DAC_CLK_Type clkSel, uint8_t div) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GLB_DAC_CLK_TYPE(clkSel)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN); + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_COMP); + + if (clkSel == GLB_DAC_CLK_32M) { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_CLK_SRC_SEL); + } else { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_CLK_SRC_SEL); + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV, div); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN); + } + + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief platform wakeup will becomes one of pds_wakeup source + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Platform_Wakeup_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_EN_PLATFORM_WAKEUP); + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief platform wakeup will not becomes one of pds_wakeup source + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Platform_Wakeup_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EN_PLATFORM_WAKEUP); + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief select DIG clock source + * + * @param clkSel: DIG clock selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel) +{ + uint32_t tmpVal; + uint32_t dig512kEn; + uint32_t dig32kEn; + + /* disable DIG512K and DIG32K clock first */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + dig512kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN); + dig32kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN); + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL, clkSel); + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + /* repristinate DIG512K and DIG32K clock */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN, dig512kEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN, dig32kEn); + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set DIG 512K clock + * + * @param enable: enable or disable DIG 512K clock + * @param compensation: enable or disable DIG 512K clock compensation + * @param div: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensation, uint8_t div) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + + if (compensation) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_COMP); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_COMP); + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV, div); + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN); + } + + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set DIG 32K clock + * + * @param enable: enable or disable DIG 32K clock + * @param compensation: enable or disable DIG 32K clock compensation + * @param div: divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensation, uint16_t div) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + + if (compensation) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_COMP); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_COMP); + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV, div); + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN); + } + + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set BT coex signal + * + * @param enable: ENABLE or DISABLE, if enable, the AP JTAG will be replaced by BT Coex Signal + * @param bandWidth: BT Bandwidth + * @param pti: BT Packet Traffic Information + * @param channel: BT Channel + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_BT_Coex_Signal(uint8_t enable, GLB_BT_BANDWIDTH_Type bandWidth, uint8_t pti, uint8_t channel) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_BT_BANDWIDTH_TYPE(bandWidth)); + CHECK_PARAM((pti <= 0xF)); + CHECK_PARAM((channel <= 78)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_BW, bandWidth); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_PTI, pti); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_CHANNEL, channel); + BL_WR_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL); + + if (enable) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EN_GPIO_BT_COEX, 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EN_GPIO_BT_COEX, 0); + } + + BL_WR_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select UART signal function + * + * @param sig: UART signal + * @param fun: UART function + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun) +{ + uint32_t sig_pos = 0; + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_UART_SIG_TYPE(sig)); + CHECK_PARAM(IS_GLB_UART_SIG_FUN_TYPE(fun)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_SIG_SEL_0); + sig_pos = (sig * 4); + /* Clear original val */ + tmpVal &= (~(0xf << sig_pos)); + /* Set new value */ + tmpVal |= (fun << sig_pos); + BL_WR_REG(GLB_BASE, GLB_UART_SIG_SEL_0, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select ir rx gpio (gpio11~gpio13) + * + * @param gpio: IR gpio selected + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio) +{ + uint32_t tmpVal = 0; + + /* Select gpio between gpio11 and gpio13 */ + if (gpio > 10 && gpio < 14) { + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, gpio - 10); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + } + + /* Close ir rx */ + if (gpio == 0) { + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, 0); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable ir led driver + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_IR_LED_Driver_Enable(void) +{ + uint32_t tmpVal = 0; + + /* Enable led driver */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_LEDDRV); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Disable ir led driver + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_IR_LED_Driver_Disable(void) +{ + uint32_t tmpVal = 0; + + /* Disable led driver */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LEDDRV); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set ir led driver ibias + * + * @param ibias: Ibias value,0x0:0mA~0xf:120mA,8mA/step + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias) +{ + uint32_t tmpVal = 0; + + /* Set driver ibias */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_IBIAS, ibias & 0xF); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO initialization + * + * @param cfg: GPIO configuration + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg) +{ + uint8_t gpioPin = cfg->gpioPin; + uint32_t *pOut; + uint32_t pos; + uint32_t tmpOut; + uint32_t tmpVal; + + /* drive strength(drive) = 0 <=> 8.0mA @ 3.3V */ + /* drive strength(drive) = 1 <=> 9.6mA @ 3.3V */ + /* drive strength(drive) = 2 <=> 11.2mA @ 3.3V */ + /* drive strength(drive) = 3 <=> 12.8mA @ 3.3V */ + + pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + ((gpioPin >> 5) << 2)); + pos = gpioPin % 32; + tmpOut = *pOut; + + /* Disable output anyway*/ + tmpOut &= (~(1 << pos)); + *pOut = tmpOut; + + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4); + + if (gpioPin % 2 == 0) { + if (cfg->gpioMode != GPIO_MODE_ANALOG) { + /* not analog mode */ + + /* Set input or output */ + if (cfg->gpioMode == GPIO_MODE_OUTPUT) { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); + tmpOut |= (1 << pos); + } else { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); + } + + /* Set pull up or down */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD); + + if (cfg->pullType == GPIO_PULL_UP) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU); + } else if (cfg->pullType == GPIO_PULL_DOWN) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD); + } + } else { + /* analog mode */ + + /* clear ie && oe */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); + tmpOut &= ~(1 << pos); + + /* clear pu && pd */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD); + } + + /* set drive && smt && func */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_DRV, cfg->drive); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_SMT, cfg->smtCtrl); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpioFun); + } else { + if (cfg->gpioMode != GPIO_MODE_ANALOG) { + /* not analog mode */ + + /* Set input or output */ + if (cfg->gpioMode == GPIO_MODE_OUTPUT) { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE); + tmpOut |= (1 << pos); + } else { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE); + } + + /* Set pull up or down */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD); + + if (cfg->pullType == GPIO_PULL_UP) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU); + } else if (cfg->pullType == GPIO_PULL_DOWN) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD); + } + } else { + /* analog mode */ + + /* clear ie && oe */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE); + tmpOut &= ~(1 << pos); + + /* clear pu && pd */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD); + } + + /* set drive && smt && func */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_DRV, cfg->drive); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_SMT, cfg->smtCtrl); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL, cfg->gpioFun); + } + + BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal); + + *pOut = tmpOut; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief init GPIO function in pin list + * + * @param gpioFun: GPIO pin function + * @param pinList: GPIO pin list + * @param cnt: GPIO pin count + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt) +{ + GLB_GPIO_Cfg_Type gpioCfg = { + .gpioPin = GLB_GPIO_PIN_0, + .gpioFun = (uint8_t)gpioFun, + .gpioMode = GPIO_MODE_AF, + .pullType = GPIO_PULL_UP, + .drive = 1, + .smtCtrl = 1 + }; + + if (gpioFun == GPIO_FUN_ANALOG) { + gpioCfg.gpioMode = GPIO_MODE_ANALOG; + } + + for (uint8_t i = 0; i < cnt; i++) { + gpioCfg.gpioPin = pinList[i]; + GLB_GPIO_Init(&gpioCfg); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO set input function enable + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_INPUT_Enable(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + uint32_t pinOffset; + + pinOffset = (gpioPin >> 1) << 2; + tmpVal = *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset); + + if (gpioPin % 2 == 0) { + /* [0] is ie */ + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); + } else { + /* [16] is ie */ + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE); + } + + *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset) = tmpVal; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO set input function disable + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + uint32_t pinOffset; + + pinOffset = (gpioPin >> 1) << 2; + tmpVal = *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset); + + if (gpioPin % 2 == 0) { + /* [0] is ie */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); + } else { + /* [16] is ie */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE); + } + + *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset) = tmpVal; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO set output function enable + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFGCTL34); + tmpVal = tmpVal | (1 << gpioPin); + BL_WR_REG(GLB_BASE, GLB_GPIO_CFGCTL34, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief GPIO set output function disable + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFGCTL34); + tmpVal = tmpVal & ~(1 << gpioPin); + BL_WR_REG(GLB_BASE, GLB_GPIO_CFGCTL34, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief GPIO set High-Z + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin) +{ + uint32_t *pOut; + uint32_t pos; + uint32_t tmpOut; + uint32_t tmpVal; + + pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + ((gpioPin >> 5) << 2)); + pos = gpioPin % 32; + tmpOut = *pOut; + + /* Disable output anyway*/ + tmpOut &= (~(1 << pos)); + *pOut = tmpOut; + + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4); + + /* select GPIO_FUN_GPIO as FUNC_SEL */ + if (gpioPin % 2 == 0) { + tmpVal = (tmpVal & 0xffff0000); + tmpVal |= 0x0B00; + } else { + tmpVal = (tmpVal & 0x0000ffff); + tmpVal |= (0x0B00 << 16); + } + + BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal); + + /* Disable output anyway*/ + *pOut = tmpOut; + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief GPIO set Pull up + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_PullUp(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4); + + /* Set Pull up */ + if (gpioPin % 2 == 0) { + tmpVal &= (~(1 << 5)); + tmpVal |= (1 << 4); + } else { + tmpVal &= (~(1 << 21)); + tmpVal |= (1 << 20); + } + + BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO set Pull down + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_PullDown(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4); + + /* Set Pull up */ + if (gpioPin % 2 == 0) { + tmpVal &= (~(1 << 4)); + tmpVal |= (1 << 5); + } else { + tmpVal &= (~(1 << 20)); + tmpVal |= (1 << 21); + } + + BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get GPIO function + * + * @param gpioPin: GPIO type + * + * @return GPIO function + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint8_t ATTR_TCM_SECTION GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4); + + if (gpioPin % 2 == 0) { + return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL); + } else { + return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL); + } +} +#endif + +/****************************************************************************/ /** + * @brief Get GPIO0-GPIO5 real function + * + * @param gpioPin: GPIO type + * + * @return GPIO real function + * +*******************************************************************************/ +GLB_GPIO_REAL_MODE_Type GLB_GPIO_Get_Real_Fun(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + + CHECK_PARAM((gpioPin <= GLB_GPIO_PIN_5)); + + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4); + + if (gpioPin % 2 == 0) { + return (GLB_GPIO_REAL_MODE_Type)BL_GET_REG_BITS_VAL(tmpVal, GLB_REAL_GPIO_0_FUNC_SEL); + } else { + return (GLB_GPIO_REAL_MODE_Type)BL_GET_REG_BITS_VAL(tmpVal, GLB_REAL_GPIO_1_FUNC_SEL); + } +} + +/****************************************************************************/ /** + * @brief Write GPIO + * + * @param gpioPin: GPIO type + * @param val: GPIO value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val) +{ + uint32_t *pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_OFFSET + ((gpioPin >> 5) << 2)); + uint32_t pos = gpioPin % 32; + uint32_t tmpOut; + + tmpOut = *pOut; + + if (val > 0) { + tmpOut |= (1 << pos); + } else { + tmpOut &= (~(1 << pos)); + } + + *pOut = tmpOut; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Read GPIO + * + * @param gpioPin: GPIO type + * + * @return GPIO value + * +*******************************************************************************/ +uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin) +{ + uint32_t *p = (uint32_t *)(GLB_BASE + GLB_GPIO_INPUT_OFFSET + ((gpioPin >> 5) << 2)); + uint32_t pos = gpioPin % 32; + + if ((*p) & (1 << pos)) { + return 1; + } else { + return 0; + } +} + +/****************************************************************************/ /** + * @brief Set GLB GPIO interrupt mask + * + * @param gpioPin: GPIO type + * @param intMask: GPIO interrupt MASK or UNMASK + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + + if (gpioPin < 32) { + /* GPIO0 ~ GPIO31 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MASK1); + + if (intMask == MASK) { + tmpVal = tmpVal | (1 << gpioPin); + } else { + tmpVal = tmpVal & ~(1 << gpioPin); + } + + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MASK1, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set GLB GPIO interrupt mask + * + * @param gpioPin: GPIO type + * @param intClear: GPIO interrupt clear or unclear + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_IntClear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear) +{ + uint32_t tmpVal; + + if (gpioPin < 32) { + /* GPIO0 ~ GPIO31 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_CLR1); + + if (intClear == SET) { + tmpVal = tmpVal | (1 << gpioPin); + } else { + tmpVal = tmpVal & ~(1 << gpioPin); + } + + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_CLR1, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get GLB GPIO interrrupt status + * + * @param gpioPin: GPIO type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal = 0; + + if (gpioPin < 32) { + /* GPIO0 ~ GPIO31 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_STAT1); + } + + return (tmpVal & (1 << gpioPin)) ? SET : RESET; +} + +/****************************************************************************/ /** + * @brief Clear GLB GPIO interrrupt status + * + * @param gpioPin: GPIO type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + + if (gpioPin < 32) { + /* GPIO0 ~ GPIO31 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_CLR1); + tmpVal = tmpVal | (1 << gpioPin); + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_CLR1, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set GLB GPIO interrupt mode + * + * @param gpioPin: GPIO type + * @param intCtlMod: GPIO interrupt control mode + * @param intTrgMod: GPIO interrupt trigger mode + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_GPIO_IntMod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod, GLB_GPIO_INT_TRIG_Type intTrgMod) +{ + uint32_t tmpVal; + uint32_t tmpGpioPin; + + CHECK_PARAM(IS_GLB_GPIO_INT_CONTROL_TYPE(intCtlMod)); + CHECK_PARAM(IS_GLB_GPIO_INT_TRIG_TYPE(intTrgMod)); + + if (gpioPin < GLB_GPIO_PIN_10) { + /* GPIO0 ~ GPIO9 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1); + tmpGpioPin = gpioPin; + tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin)); + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1, tmpVal); + } else if (gpioPin < GLB_GPIO_PIN_20) { + /* GPIO10 ~ GPIO19 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2); + tmpGpioPin = gpioPin - GLB_GPIO_PIN_10; + tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin)); + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2, tmpVal); + } else { + /* GPIO20 ~ GPIO29 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3); + tmpGpioPin = gpioPin - GLB_GPIO_PIN_20; + tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin)); + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get GPIO interrupt control mode + * + * @param gpioPin: GPIO pin type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_IntCtlMod(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + uint32_t bitVal; + + if (gpioPin < GLB_GPIO_PIN_10) { + /* GPIO0 - GPIO9 */ + bitVal = gpioPin - 0; + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1); + tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3); + return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC; + } else if ((gpioPin > GLB_GPIO_PIN_9) && (gpioPin < GLB_GPIO_PIN_20)) { + /* GPIO10 - GPIO19 */ + bitVal = gpioPin - 10; + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2); + tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3); + return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC; + } else { + /* GPIO20 - GPIO29 */ + bitVal = gpioPin - 20; + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3); + tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3); + return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC; + } +} + +/****************************************************************************/ /** + * @brief GPIO INT0 IRQHandler install + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void) +{ +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO_INT0_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO interrupt IRQ handler callback install + * + * @param gpioPin: GPIO pin type + * @param cbFun: callback function + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun) +{ + if (gpioPin < 32) { + glbGpioInt0CbfArra[gpioPin] = cbFun; + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO interrupt IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void GPIO_INT0_IRQHandler(void) +{ + GLB_GPIO_Type gpioPin; + uint32_t timeOut = 0; + + for (gpioPin = GLB_GPIO_PIN_0; gpioPin <= GLB_GPIO_PIN_22; gpioPin++) { + if (SET == GLB_Get_GPIO_IntStatus(gpioPin)) { + GLB_GPIO_IntClear(gpioPin, SET); + + /* timeout check */ + timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT; + + do { + timeOut--; + } while ((SET == GLB_Get_GPIO_IntStatus(gpioPin)) && timeOut); + + if (!timeOut) { + MSG("WARNING: Clear GPIO interrupt status fail.\r\n"); + } + + /* if timeOut==0, GPIO interrupt status not cleared */ + GLB_GPIO_IntClear(gpioPin, RESET); + + if (glbGpioInt0CbfArra[gpioPin] != NULL) { + /* Call the callback function */ + glbGpioInt0CbfArra[gpioPin](); + } + } + } +} +#endif + +/*@} end of group GLB_Public_Functions */ + +/*@} end of group GLB */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/soc/bl602/bl602_std/src/bl602_hbn.c b/drivers/soc/bl602/bl602_std/src/bl602_hbn.c new file mode 100644 index 00000000..cda54a12 --- /dev/null +++ b/drivers/soc/bl602/bl602_std/src/bl602_hbn.c @@ -0,0 +1,1799 @@ +/** + ****************************************************************************** + * @file bl602_hbn.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_hbn.h" +#include "bl602_glb.h" +#include "bl602_xip_sflash.h" +// #include "risc-v/Core/Include/clic.h" + +/** @addtogroup BL602_Peripheral_Driver + * @{ + */ + +/** @addtogroup HBN + * @{ + */ + +/** @defgroup HBN_Private_Macros + * @{ + */ +#define HBN_CLK_SET_DUMMY_WAIT \ + { \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + } + +/*@} end of group HBN_Private_Macros */ + +/** @defgroup HBN_Private_Types + * @{ + */ + +/*@} end of group HBN_Private_Types */ + +/** @defgroup HBN_Private_Variables + * @{ + */ +static intCallback_Type *hbnInt0CbfArra[3] = { NULL, NULL, NULL }; +static intCallback_Type *hbnInt1CbfArra[4] = { NULL, NULL, NULL, NULL }; + +/*@} end of group HBN_Private_Variables */ + +/** @defgroup HBN_Global_Variables + * @{ + */ + +/*@} end of group HBN_Global_Variables */ + +/** @defgroup HBN_Private_Fun_Declaration + * @{ + */ + +/*@} end of group HBN_Private_Fun_Declaration */ + +/** @defgroup HBN_Private_Functions + * @{ + */ + +/*@} end of group HBN_Private_Functions */ + +/** @defgroup HBN_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Enter HBN + * + * @param cfg: HBN APP Config + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION HBN_Mode_Enter_Ext(HBN_APP_CFG_Type *cfg) +{ + uint32_t valLow = 0, valHigh = 0; + uint64_t val; + + if (cfg->useXtal32k) { + HBN_32K_Sel(HBN_32K_XTAL); + } else { + HBN_32K_Sel(HBN_32K_RC); + HBN_Power_Off_Xtal_32K(); + } + + /* always disable HBN pin pull up/down to reduce PDS/HBN current, 0x4000F014[16]=0 */ + HBN_Hw_Pu_Pd_Cfg(DISABLE); + + HBN_Pin_WakeUp_Mask(~(cfg->gpioWakeupSrc)); + + if (cfg->gpioWakeupSrc != 0) { + HBN_Aon_Pad_IeSmt_Cfg(ENABLE); + HBN_GPIO_INT_Enable(cfg->gpioTrigType); + } else { + HBN_Aon_Pad_IeSmt_Cfg(DISABLE); + } + + /* HBN RTC config and enable */ + if (cfg->sleepTime != 0) { + HBN_Clear_RTC_Counter(); + HBN_Get_RTC_Timer_Val(&valLow, &valHigh); + val = valLow + ((uint64_t)valHigh << 32); + val += cfg->sleepTime; + HBN_Set_RTC_Timer(HBN_RTC_INT_DELAY_0T, val & 0xffffffff, val >> 32, HBN_RTC_COMP_BIT0_39); + HBN_Enable_RTC_Counter(); + } + + HBN_Power_Down_Flash(cfg->flashCfg); + HBN_Set_Embedded_Flash_Pullup(ENABLE); /* E_ITEM_06 */ + + GLB_Set_System_CLK(GLB_PLL_XTAL_NONE, GLB_SYS_CLK_RC32M); + + HBN_Enable_Ext(cfg->gpioWakeupSrc, cfg->ldoLevel, cfg->hbnLevel); +} + +/****************************************************************************/ /** + * @brief power down and switch clock + * + * @param flashCfg: None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg) +{ + SPI_Flash_Cfg_Type bhFlashCfg; + + if (flashCfg == NULL) { + SFlash_Cache_Flush(); + XIP_SFlash_Read_Via_Cache_Need_Lock(BL602_FLASH_XIP_BASE + 8 + 4, (uint8_t *)(&bhFlashCfg), sizeof(SPI_Flash_Cfg_Type)); + SFlash_Cache_Flush(); + + SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); + SFlash_Reset_Continue_Read(&bhFlashCfg); + } else { + SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); + SFlash_Reset_Continue_Read(flashCfg); + } + + SFlash_Powerdown(); +} +#endif +#if 0 +/****************************************************************************/ /** + * @brief Enable HBN mode + * + * @param aGPIOIeCfg: AON GPIO input enable config. Bit(s) of Wakeup GPIO(s) must not be set to + * 0(s),say when use GPIO7 as wake up pin,aGPIOIeCfg should be 0x01. + * @param ldoLevel: LDO volatge level + * @param hbnLevel: HBN work level + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION HBN_Enable_Ext(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + CHECK_PARAM(IS_HBN_LEVEL_TYPE(hbnLevel)); + + /* Setting from guide */ + /* RAM Retion */ + BL_WR_REG(HBN_BASE, HBN_SRAM, 0x24); + /* AON GPIO IE */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + if (aGPIOIeCfg) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, 0); + } + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + /* HBN mode LDO level */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_AON_VOUT_SEL, ldoLevel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_RT_VOUT_SEL, ldoLevel); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + /* Select RC32M */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + /* Set HBN flag */ + BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + + /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */ + switch (hbnLevel) { + case HBN_LEVEL_0: + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_1: + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_2: + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_3: + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + default: + break; + } + + /* Set power on option:0 for por reset twice for robust 1 for reset only once*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + HBN_OUT0_IRQn) = 0; + *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + HBN_OUT1_IRQn) = 0; + + BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff); + BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0); + + /* Enable HBN mode */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + while (1) { + BL602_Delay_MS(1000); + } +} +#endif +/****************************************************************************/ /** + * @brief Reset HBN mode + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_Reset(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Reset HBN mode */ + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_SW_RST); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief reset HBN by software + * + * @param npXtalType: NP clock type + * @param bclkDiv: NP clock div + * @param apXtalType: AP clock type + * @param fclkDiv: AP clock div + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_App_Reset(uint8_t npXtalType, uint8_t bclkDiv, uint8_t apXtalType, uint8_t fclkDiv) +{ + uint32_t tmp[12]; + + tmp[0] = BL_RD_REG(HBN_BASE, HBN_CTL); + tmp[1] = BL_RD_REG(HBN_BASE, HBN_TIME_L); + tmp[2] = BL_RD_REG(HBN_BASE, HBN_TIME_H); + tmp[3] = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmp[4] = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR); + tmp[5] = BL_RD_REG(HBN_BASE, HBN_PIR_CFG); + tmp[6] = BL_RD_REG(HBN_BASE, HBN_PIR_VTH); + tmp[7] = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL); + tmp[8] = BL_RD_REG(HBN_BASE, HBN_SRAM); + tmp[9] = BL_RD_REG(HBN_BASE, HBN_RSV0); + tmp[10] = BL_RD_REG(HBN_BASE, HBN_RSV1); + tmp[11] = BL_RD_REG(HBN_BASE, HBN_RSV2); + /* DO HBN reset */ + HBN_Reset(); + /* HBN need 3 32k cyclce to recovery */ + BL602_Delay_US(100); + /* Recover HBN value */ + BL_WR_REG(HBN_BASE, HBN_TIME_L, tmp[1]); + BL_WR_REG(HBN_BASE, HBN_TIME_H, tmp[2]); + BL_WR_REG(HBN_BASE, HBN_CTL, tmp[0]); + + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmp[3]); + BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmp[4]); + BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmp[5]); + BL_WR_REG(HBN_BASE, HBN_PIR_VTH, tmp[6]); + BL_WR_REG(HBN_BASE, HBN_PIR_INTERVAL, tmp[7]); + BL_WR_REG(HBN_BASE, HBN_SRAM, tmp[8]); + BL_WR_REG(HBN_BASE, HBN_RSV0, tmp[9]); + BL_WR_REG(HBN_BASE, HBN_RSV1, tmp[10]); + BL_WR_REG(HBN_BASE, HBN_RSV2, tmp[11]); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Disable HBN mode + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Disable HBN mode */ + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_MODE); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable HBN PIR + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_PIR_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PIR_EN); + BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Disable HBN PIR + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_PIR_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PIR_EN); + BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Config HBN PIR interrupt + * + * @param pirIntCfg: HBN PIR interrupt configuration + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg) +{ + uint32_t tmpVal; + uint32_t bit4 = 0; + uint32_t bit5 = 0; + uint32_t bitVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG); + + /* low trigger interrupt */ + if (pirIntCfg->lowIntEn == ENABLE) { + bit5 = 0; + } else { + bit5 = 1; + } + + /* high trigger interrupt */ + if (pirIntCfg->highIntEn == ENABLE) { + bit4 = 0; + } else { + bit4 = 1; + } + + bitVal = bit4 | (bit5 << 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_DIS, bitVal); + BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select HBN PIR low pass filter + * + * @param lpf: HBN PIR low pass filter selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_PIR_LPF_TYPE(lpf)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_LPF_SEL, lpf); + BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select HBN PIR high pass filter + * + * @param hpf: HBN PIR high pass filter selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_PIR_HPF_TYPE(hpf)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_HPF_SEL, hpf); + BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set HBN PIR threshold value + * + * @param threshold: HBN PIR threshold value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold) +{ + uint32_t tmpVal; + + CHECK_PARAM((threshold <= 0x3FFF)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_VTH); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH, threshold); + BL_WR_REG(HBN_BASE, HBN_PIR_VTH, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get HBN PIR threshold value + * + * @param None + * + * @return HBN PIR threshold value + * +*******************************************************************************/ +uint16_t HBN_Get_PIR_Threshold(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_VTH); + + return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH); +} + +/****************************************************************************/ /** + * @brief Set HBN PIR interval value + * + * @param interval: HBN PIR interval value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval) +{ + uint32_t tmpVal; + + CHECK_PARAM((interval <= 0xFFF)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL, interval); + BL_WR_REG(HBN_BASE, HBN_PIR_INTERVAL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get HBN PIR interval value + * + * @param None + * + * @return HBN PIR interval value + * +*******************************************************************************/ +uint16_t HBN_Get_PIR_Interval(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL); + + return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL); +} + +/****************************************************************************/ /** + * @brief get HBN bor out state + * + * @param None + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type HBN_Get_BOR_OUT_State(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_BOR_CFG), HBN_R_BOR_OUT) ? SET : RESET; +} + +/****************************************************************************/ /** + * @brief set HBN bor config + * + * @param enable: ENABLE or DISABLE, if enable, Power up Brown Out Reset + * @param threshold: bor threshold + * @param mode: bor work mode with por + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_BOR_Config(uint8_t enable, HBN_BOR_THRES_Type threshold, HBN_BOR_MODE_Type mode) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_BOR_THRES_TYPE(threshold)); + CHECK_PARAM(IS_HBN_BOR_MODE_TYPE(mode)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_BOR_CFG); + + if (enable) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOR, 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOR, 0); + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_VTH, threshold); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_SEL, mode); + BL_WR_REG(HBN_BASE, HBN_BOR_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN set ldo11aon voltage out + * + * @param ldoLevel: LDO volatge level + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief HBN set ldo11rt voltage out + * + * @param ldoLevel: LDO volatge level + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_RT_VOUT_SEL, ldoLevel); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief HBN set ldo11soc voltage out + * + * @param ldoLevel: LDO volatge level + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11SOC_VOUT_SEL_AON, ldoLevel); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief HBN set ldo11 all voltage out + * + * @param ldoLevel: LDO volatge level + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_RT_VOUT_SEL, ldoLevel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11SOC_VOUT_SEL_AON, ldoLevel); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN select 32K + * + * @param clkType: HBN 32k clock type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION HBN_32K_Sel(HBN_32K_CLK_Type clkType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_HBN_32K_CLK_TYPE(clkType)); + + HBN_Trim_RC32K(); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL, clkType); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Select uart clock source + * + * @param clkSel: uart clock type selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL, clkSel); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select xclk clock source + * + * @param xClk: xclk clock type selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_HBN_XCLK_CLK_TYPE(xClk)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL); + + switch (xClk) { + case HBN_XCLK_CLK_RC32M: + tmpVal2 &= (~(1 << 0)); + break; + + case HBN_XCLK_CLK_XTAL: + tmpVal2 |= (1 << 0); + break; + + default: + break; + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + HBN_CLK_SET_DUMMY_WAIT; + + return SUCCESS; +} + +/****************************************************************************/ /** +* @brief get root clock selection +* +* @param None +* +* @return root clock selection +* +*******************************************************************************/ +HBN_ROOT_CLK_Type ATTR_CLOCK_SECTION HBN_Get_Root_CLK_Sel(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + + switch (BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL)) { + case 0: + return HBN_ROOT_CLK_RC32M; + case 1: + return HBN_ROOT_CLK_XTAL; + case 2: + return HBN_ROOT_CLK_PLL; + case 3: + return HBN_ROOT_CLK_PLL; + default: + return HBN_ROOT_CLK_RC32M; + } +} + +/****************************************************************************/ /** + * @brief Select root clk source + * + * @param rootClk: root clock type selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_HBN_ROOT_CLK_TYPE(rootClk)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL); + + switch (rootClk) { + case HBN_ROOT_CLK_RC32M: + tmpVal2 = 0x0; + break; + + case HBN_ROOT_CLK_XTAL: + tmpVal2 = 0x1; + break; + + case HBN_ROOT_CLK_PLL: + tmpVal2 |= (1 << 1); + break; + + default: + break; + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + HBN_CLK_SET_DUMMY_WAIT; + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief set HBN_RAM sleep mode + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_HRAM_slp(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_SLP); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_RET); + BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set HBN_RAM retension mode + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_HRAM_Ret(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_SLP); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_RET); + BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power on XTAL 32K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_Xtal_32K(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF); + BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal); + + /* Delay >1s */ + BL602_Delay_US(1100); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power off XTAL 32K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_Xtal_32K(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF); + BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power on RC32K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_RC32K(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_RC32K); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + /* Delay >800us */ + BL602_Delay_US(880); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power off RC3K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_RC32K(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_RC32K); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Trim RC32K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION HBN_Trim_RC32K(void) +{ + Efuse_Ana_RC32K_Trim_Type trim; + int32_t tmpVal = 0; + + EF_Ctrl_Read_RC32K_Trim(&trim); + + if (trim.trimRc32kExtCodeEn) { + if (trim.trimRc32kCodeFrExtParity == EF_Ctrl_Get_Trim_Parity(trim.trimRc32kCodeFrExt, 10)) { + tmpVal = BL_RD_REG(HBN_BASE, HBN_RC32K_CTRL0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RC32K_CODE_FR_EXT, trim.trimRc32kCodeFrExt); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RC32K_EXT_CODE_EN); + BL_WR_REG(HBN_BASE, HBN_RC32K_CTRL0, tmpVal); + BL602_Delay_US(2); + return SUCCESS; + } + } + + return ERROR; +} +#endif + +/****************************************************************************/ /** + * @brief Get HBN status flag + * + * @param None + * + * @return HBN status flag value + * +*******************************************************************************/ +uint32_t HBN_Get_Status_Flag(void) +{ + return BL_RD_REG(HBN_BASE, HBN_RSV0); +} + +/****************************************************************************/ /** + * @brief Set HBN status flag + * + * @param flag: Status Flag + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_Status_Flag(uint32_t flag) +{ + BL_WR_REG(HBN_BASE, HBN_RSV0, flag); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get HBN wakeup address + * + * @param None + * + * @return HBN wakeup address + * +*******************************************************************************/ +uint32_t HBN_Get_Wakeup_Addr(void) +{ + return BL_RD_REG(HBN_BASE, HBN_RSV1); +} + +/****************************************************************************/ /** + * @brief Set HBN wakeup address + * + * @param addr: HBN wakeup address + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr) +{ + BL_WR_REG(HBN_BASE, HBN_RSV1, addr); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN clear RTC timer counter + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Clear_RTC_Counter(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Clear RTC control bit0 */ + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffffe); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN clear RTC timer counter + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Enable_RTC_Counter(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Set RTC control bit0 */ + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal | 0x01); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN set RTC timer configuration + * + * @param delay: RTC interrupt delay 32 clocks + * @param compValLow: RTC interrupt commpare value low 32 bits + * @param compValHigh: RTC interrupt commpare value high 32 bits + * @param compMode: RTC interrupt commpare + * mode:HBN_RTC_COMP_BIT0_39,HBN_RTC_COMP_BIT0_23,HBN_RTC_COMP_BIT13_39 + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_HBN_RTC_INT_DELAY_TYPE(delay)); + + BL_WR_REG(HBN_BASE, HBN_TIME_L, compValLow); + BL_WR_REG(HBN_BASE, HBN_TIME_H, compValHigh & 0xff); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Set interrupt delay option */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RTC_DLY_OPTION, delay); + /* Set RTC compare mode */ + tmpVal |= (compMode << 1); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN get RTC async timer count value + * + * @param valLow: RTC count value pointer for low 32 bits + * @param valHigh: RTC count value pointer for high 8 bits + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +static BL_Err_Type HBN_Get_RTC_Timer_Async_Val(uint32_t *valLow, uint32_t *valHigh) +{ + uint32_t tmpVal; + + /* Tigger RTC val read */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH); + BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH); + BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal); + + /* Read RTC val */ + *valLow = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_L); + *valHigh = (BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H) & 0xff); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN get RTC timer count value + * + * @param valLow: RTC count value pointer for low 32 bits + * @param valHigh: RTC count value pointer for high 8 bits + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh) +{ + uint32_t tmpValLow, tmpValHigh, tmpValLow1, tmpValHigh1; + uint64_t val, val1; + + do { + HBN_Get_RTC_Timer_Async_Val(&tmpValLow, &tmpValHigh); + val = ((uint64_t)tmpValHigh << 32) | ((uint64_t)tmpValLow); + HBN_Get_RTC_Timer_Async_Val(&tmpValLow1, &tmpValHigh1); + val1 = ((uint64_t)tmpValHigh1 << 32) | ((uint64_t)tmpValLow1); + } while (val1 < val); + + *valLow = tmpValLow1; + *valHigh = tmpValHigh1; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN clear RTC timer interrupt,this function must be called to clear delayed rtc IRQ + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Clear_RTC_INT(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Clear RTC commpare:bit1-3 for clearing Delayed RTC IRQ */ + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffff1); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN enable GPIO interrupt + * + * @param gpioIntTrigType: HBN GPIO interrupt trigger type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_HBN_GPIO_INT_TRIGGER_TYPE(gpioIntTrigType)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MODE, gpioIntTrigType); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN disable GPIO interrupt + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_GPIO_INT_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, 0); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN get interrupt status + * + * @param irqType: HBN interrupt type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_STAT); + + if (tmpVal & (1 << irqType)) { + return SET; + } else { + return RESET; + } +} + +/****************************************************************************/ /** + * @brief HBN get pin wakeup mode value + * + * @param None + * + * @return HBN pin wakeup mode value + * +*******************************************************************************/ +uint8_t HBN_Get_Pin_Wakeup_Mode(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_IRQ_MODE), HBN_PIN_WAKEUP_MODE); +} + +/****************************************************************************/ /** + * @brief HBN clear interrupt status + * + * @param irqType: HBN interrupt type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_INT_TYPE(irqType)); + + /* set clear bit */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR); + tmpVal |= (1 << irqType); + BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal); + + /* unset clear bit */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR); + tmpVal &= (~(1 << irqType)); + BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN hardware pullup or pulldown configuration + * + * @param enable: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_Hw_Pu_Pd_Cfg(uint8_t enable) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD); + } + + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief HBN Config AON pad input and SMT + * + * @param padCfg: AON pad config + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Aon_Pad_IeSmt_Cfg(uint8_t padCfg) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, padCfg); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN wakeup pin mask configuration + * + * @param maskVal: mask value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_Pin_WakeUp_Mask(uint8_t maskVal) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, maskVal); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief HBN enable ACOMP0 interrupt + * + * @param edge: HBN acomp interrupt edge type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN); + tmpVal2 = tmpVal2 | (1 << edge); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN disable ACOMP0 interrupt + * + * @param edge: HBN acomp interrupt edge type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN); + tmpVal2 = tmpVal2 & (~(1 << edge)); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN enable ACOMP1 interrupt + * + * @param edge: HBN acomp interrupt edge type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN); + tmpVal2 = tmpVal2 | (1 << edge); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN disable ACOMP1 interrupt + * + * @param edge: HBN acomp interrupt edge type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN); + tmpVal2 = tmpVal2 & (~(1 << edge)); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN enable BOR interrupt + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Enable_BOR_IRQ(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_IRQ_BOR_EN); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN disable BOR interrupt + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Disable_BOR_IRQ(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_IRQ_BOR_EN); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN out0 IRQHandler install + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Out0_IRQHandler_Install(void) +{ +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(HBN_OUT0_IRQn, HBN_OUT0_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN out0 install interrupt callback + * + * @param intType: HBN out0 interrupt type + * @param cbFun: HBN out0 interrupt callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_HBN_OUT0_INT_TYPE(intType)); + + hbnInt0CbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN out1 IRQHandler install + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Out1_IRQHandler_Install(void) +{ +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(HBN_OUT1_IRQn, HBN_OUT1_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN out1 install interrupt callback + * + * @param intType: HBN out1 interrupt type + * @param cbFun: HBN out1 interrupt callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_HBN_OUT1_INT_TYPE(intType)); + + hbnInt1CbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN GPIO7 debbug pull config + * + * @param pupdEn: Enable or disable GPIO7 pull down and pull up + * @param iesmtEn: Enable or disable GPIO7 IE and SMT + * @param dlyEn: Enable or disable GPIO7 wakeup delay function + * @param dlySec: GPIO7 wakeup delay sec 1 to 7 + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_GPIO7_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type iesmtEn, BL_Fun_Type dlyEn, uint8_t dlySec) +{ + uint32_t tmpVal; + + CHECK_PARAM(((dlySec >= 1) && (dlySec <= 7))); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_EN, dlyEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_SEL, dlySec); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_EN_HW_PU_PD, pupdEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, iesmtEn); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Set Embedded Flash Pullup enabe or disable + * + * @param enable: Enable or disable + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Embedded_Flash_Pullup(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV3); + + enable = (!enable); + tmpVal = ((tmpVal & 0xfffffffe) | (enable & 0x01)); + + BL_WR_REG(HBN_BASE, HBN_RSV3, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Set Embedded Flash Pullup enabe or disable + * + * @param cfg: Enable or disable + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_BOR_Cfg(HBN_BOR_CFG_Type *cfg) +{ + uint32_t tmpVal = 0; + + if (cfg->enableBorInt) { + HBN_Enable_BOR_IRQ(); + } else { + HBN_Disable_BOR_IRQ(); + } + + tmpVal = BL_RD_REG(HBN_BASE, HBN_BOR_CFG); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_VTH, cfg->borThreshold); + + if (cfg->enablePorInBor) { + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_BOR_SEL); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_BOR_SEL); + } + + if (cfg->enableBor) { + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_BOR); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_BOR); + } + + BL_WR_REG(HBN_BASE, HBN_BOR_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN OUT0 interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void HBN_OUT0_IRQHandler(void) +{ + /* GPIO7 GPIO8 and RTC */ + if (SET == HBN_Get_INT_State(HBN_INT_GPIO7)) { + /* gpio7 sync/async mode */ + HBN_Clear_IRQ(HBN_INT_GPIO7); + + if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO7] != NULL) { + hbnInt0CbfArra[HBN_OUT0_INT_GPIO7](); + } + } + + if (SET == HBN_Get_INT_State(HBN_INT_GPIO8)) { + /* gpio8 sync/async mode */ + HBN_Clear_IRQ(HBN_INT_GPIO8); + + if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO8] != NULL) { + hbnInt0CbfArra[HBN_OUT0_INT_GPIO8](); + } + } + + if (SET == HBN_Get_INT_State(HBN_INT_RTC)) { + HBN_Clear_IRQ(HBN_INT_RTC); + HBN_Clear_RTC_INT(); + + if (hbnInt0CbfArra[HBN_OUT0_INT_RTC] != NULL) { + hbnInt0CbfArra[HBN_OUT0_INT_RTC](); + } + } +} +#endif + +/****************************************************************************/ /** + * @brief HBN OUT1 interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void HBN_OUT1_IRQHandler(void) +{ + /* PIR */ + if (SET == HBN_Get_INT_State(HBN_INT_PIR)) { + HBN_Clear_IRQ(HBN_INT_PIR); + + if (hbnInt1CbfArra[HBN_OUT1_INT_PIR] != NULL) { + hbnInt1CbfArra[HBN_OUT1_INT_PIR](); + } + } + + /* BOR */ + if (SET == HBN_Get_INT_State(HBN_INT_BOR)) { + HBN_Clear_IRQ(HBN_INT_BOR); + + if (hbnInt1CbfArra[HBN_OUT1_INT_BOR] != NULL) { + hbnInt1CbfArra[HBN_OUT1_INT_BOR](); + } + } + + /* ACOMP0 */ + if (SET == HBN_Get_INT_State(HBN_INT_ACOMP0)) { + HBN_Clear_IRQ(HBN_INT_ACOMP0); + + if (hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0] != NULL) { + hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0](); + } + } + + /* ACOMP1 */ + if (SET == HBN_Get_INT_State(HBN_INT_ACOMP1)) { + HBN_Clear_IRQ(HBN_INT_ACOMP1); + + if (hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1] != NULL) { + hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1](); + } + } +} +#endif + +/*@} end of group HBN_Public_Functions */ + +/*@} end of group HBN */ + +/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/soc/bl602/bl602_std/src/bl602_romapi.c b/drivers/soc/bl602/bl602_std/src/bl602_romapi.c new file mode 100644 index 00000000..c22dbcc6 --- /dev/null +++ b/drivers/soc/bl602/bl602_std/src/bl602_romapi.c @@ -0,0 +1,1031 @@ +#include "bl602_romdriver.h" + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void) +{ + return RomDriver_AON_Power_On_MBG(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void) +{ + return RomDriver_AON_Power_Off_MBG(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void) +{ + return RomDriver_AON_Power_On_XTAL(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut) +{ + return RomDriver_AON_Set_Xtal_CapCode(capIn, capOut); +} + +__ALWAYS_INLINE +uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void) +{ + return RomDriver_AON_Get_Xtal_CapCode(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void) +{ + return RomDriver_AON_Power_Off_XTAL(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void) +{ + return RomDriver_AON_Power_On_BG(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void) +{ + return RomDriver_AON_Power_Off_BG(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO11_SOC(void) +{ + return RomDriver_AON_Power_On_LDO11_SOC(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO11_SOC(void) +{ + return RomDriver_AON_Power_Off_LDO11_SOC(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void) +{ + return RomDriver_AON_Power_On_LDO15_RF(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO15_RF(void) +{ + return RomDriver_AON_Power_Off_LDO15_RF(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void) +{ + return RomDriver_AON_Power_On_SFReg(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void) +{ + return RomDriver_AON_Power_Off_SFReg(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Enter_PDS0(void) +{ + return RomDriver_AON_LowPower_Enter_PDS0(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void) +{ + return RomDriver_AON_LowPower_Exit_PDS0(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt) +{ + return RomDriver_ASM_Delay_Us(core, cnt); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION BL602_Delay_US(uint32_t cnt) +{ + return RomDriver_BL602_Delay_US(cnt); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION BL602_Delay_MS(uint32_t cnt) +{ + return RomDriver_BL602_Delay_MS(cnt); +} + +__ALWAYS_INLINE +void *ATTR_TCM_SECTION BL602_MemCpy(void *dst, const void *src, uint32_t n) +{ + return RomDriver_BL602_MemCpy(dst, src, n); +} + +__ALWAYS_INLINE +uint32_t *ATTR_TCM_SECTION BL602_MemCpy4(uint32_t *dst, const uint32_t *src, uint32_t n) +{ + return RomDriver_BL602_MemCpy4(dst, src, n); +} + +__ALWAYS_INLINE +void *ATTR_TCM_SECTION BL602_MemCpy_Fast(void *pdst, const void *psrc, uint32_t n) +{ + return RomDriver_BL602_MemCpy_Fast(pdst, psrc, n); +} + +__ALWAYS_INLINE +void *ATTR_TCM_SECTION BL602_MemSet(void *s, uint8_t c, uint32_t n) +{ + return RomDriver_BL602_MemSet(s, c, n); +} + +__ALWAYS_INLINE +uint32_t *ATTR_TCM_SECTION BL602_MemSet4(uint32_t *dst, const uint32_t val, uint32_t n) +{ + return RomDriver_BL602_MemSet4(dst, val, n); +} + +__ALWAYS_INLINE +int ATTR_TCM_SECTION BL602_MemCmp(const void *s1, const void *s2, uint32_t n) +{ + return RomDriver_BL602_MemCmp(s1, s2, n); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION EF_Ctrl_Sw_AHB_Clk_0(void) +{ + return RomDriver_EF_Ctrl_Sw_AHB_Clk_0(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION EF_Ctrl_Program_Efuse_0(void) +{ + return RomDriver_EF_Ctrl_Program_Efuse_0(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION EF_Ctrl_Load_Efuse_R0(void) +{ + return RomDriver_EF_Ctrl_Load_Efuse_R0(); +} + +__ALWAYS_INLINE +BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_Busy(void) +{ + return RomDriver_EF_Ctrl_Busy(); +} + +__ALWAYS_INLINE +BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_AutoLoad_Done(void) +{ + return RomDriver_EF_Ctrl_AutoLoad_Done(); +} + +__ALWAYS_INLINE +uint8_t ATTR_CLOCK_SECTION EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len) +{ + return RomDriver_EF_Ctrl_Get_Trim_Parity(val, len); +} + +__ALWAYS_INLINE +void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim) +{ + return RomDriver_EF_Ctrl_Read_RC32M_Trim(trim); +} + +__ALWAYS_INLINE +void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim) +{ + return RomDriver_EF_Ctrl_Read_RC32K_Trim(trim); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION EF_Ctrl_Clear(uint32_t index, uint32_t len) +{ + return RomDriver_EF_Ctrl_Clear(index, len); +} + +__ALWAYS_INLINE +GLB_ROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_Root_CLK_Sel(void) +{ + return RomDriver_GLB_Get_Root_CLK_Sel(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv) +{ + return RomDriver_GLB_Set_System_CLK_Div(hclkDiv, bclkDiv); +} + +__ALWAYS_INLINE +uint8_t ATTR_CLOCK_SECTION GLB_Get_BCLK_Div(void) +{ + return RomDriver_GLB_Get_BCLK_Div(); +} + +__ALWAYS_INLINE +uint8_t ATTR_CLOCK_SECTION GLB_Get_HCLK_Div(void) +{ + return RomDriver_GLB_Get_HCLK_Div(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION Update_SystemCoreClockWith_XTAL(GLB_PLL_XTAL_Type xtalType) +{ + return RomDriver_Update_SystemCoreClockWith_XTAL(xtalType); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK(GLB_PLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq) +{ + return RomDriver_GLB_Set_System_CLK(xtalType, clkFreq); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION System_Core_Clock_Update_From_RC32M(void) +{ + return RomDriver_System_Core_Clock_Update_From_RC32M(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div) +{ + return RomDriver_GLB_Set_SF_CLK(enable, clkSel, div); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel) +{ + return RomDriver_GLB_Set_PKA_CLK_Sel(clkSel); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_SW_System_Reset(void) +{ + return RomDriver_GLB_SW_System_Reset(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_SW_CPU_Reset(void) +{ + return RomDriver_GLB_SW_CPU_Reset(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_SW_POR_Reset(void) +{ + return RomDriver_GLB_SW_POR_Reset(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_Select_Internal_Flash(void) +{ + return RomDriver_GLB_Select_Internal_Flash(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_Select_External_Flash(void) +{ + return RomDriver_GLB_Select_External_Flash(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_Deswap_Flash_Pin(void) +{ + return RomDriver_GLB_Deswap_Flash_Pin(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_Swap_Flash_Pin(void) +{ + return RomDriver_GLB_Swap_Flash_Pin(); +} + +#if 0 +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg) +{ + return RomDriver_GLB_GPIO_Init(cfg); +} +#endif + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin) +{ + return RomDriver_GLB_GPIO_OUTPUT_Enable(gpioPin); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin) +{ + return RomDriver_GLB_GPIO_OUTPUT_Disable(gpioPin); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin) +{ + return RomDriver_GLB_GPIO_Set_HZ(gpioPin); +} + +__ALWAYS_INLINE +uint8_t ATTR_TCM_SECTION GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin) +{ + return RomDriver_GLB_GPIO_Get_Fun(gpioPin); +} + +#if 0 +__ALWAYS_INLINE +void ATTR_TCM_SECTION HBN_Mode_Enter(HBN_APP_CFG_Type *cfg) +{ + return RomDriver_HBN_Mode_Enter(cfg); +} +#endif + +__ALWAYS_INLINE +void ATTR_TCM_SECTION HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_HBN_Power_Down_Flash(flashCfg); +} + +#if 0 +__ALWAYS_INLINE +void ATTR_TCM_SECTION HBN_Enable(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel) +{ + return RomDriver_HBN_Enable(aGPIOIeCfg, ldoLevel, hbnLevel); +} +#endif + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_Reset(void) +{ + return RomDriver_HBN_Reset(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + return RomDriver_HBN_Set_Ldo11_Aon_Vout(ldoLevel); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + return RomDriver_HBN_Set_Ldo11_Rt_Vout(ldoLevel); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + return RomDriver_HBN_Set_Ldo11_Soc_Vout(ldoLevel); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION HBN_32K_Sel(HBN_32K_CLK_Type clkType) +{ + return RomDriver_HBN_32K_Sel(clkType); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk) +{ + return RomDriver_HBN_Set_ROOT_CLK_Sel(rootClk); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_Xtal_32K(void) +{ + return RomDriver_HBN_Power_On_Xtal_32K(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_Xtal_32K(void) +{ + return RomDriver_HBN_Power_Off_Xtal_32K(); +} + +#if 0 +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_RC32K(void) +{ + return RomDriver_HBN_Power_On_RC32K(); +} +#endif + +#if 0 +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_RC32K(void) +{ + return RomDriver_HBN_Power_Off_RC32K(); +} +#endif + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION HBN_Trim_RC32K(void) +{ + return RomDriver_HBN_Trim_RC32K(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_Hw_Pu_Pd_Cfg(uint8_t enable) +{ + return RomDriver_HBN_Hw_Pu_Pd_Cfg(enable); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_Pin_WakeUp_Mask(uint8_t maskVal) +{ + return RomDriver_HBN_Pin_WakeUp_Mask(maskVal); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_GPIO7_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type iesmtEn, BL_Fun_Type dlyEn, uint8_t dlySec) +{ + return RomDriver_HBN_GPIO7_Dbg_Pull_Cfg(pupdEn, iesmtEn, dlyEn, dlySec); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Embedded_Flash_Pullup(uint8_t enable) +{ + return RomDriver_HBN_Set_Embedded_Flash_Pullup(enable); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION L1C_Set_Wrap(BL_Fun_Type wrap) +{ + return RomDriver_L1C_Set_Wrap(wrap); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION L1C_Set_Way_Disable(uint8_t disableVal) +{ + return RomDriver_L1C_Set_Way_Disable(disableVal); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION L1C_IROM_2T_Access_Set(uint8_t enable) +{ + return RomDriver_L1C_IROM_2T_Access_Set(enable); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION PDS_Reset(void) +{ + return RomDriver_PDS_Reset(); +} + +#if 0 +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION PDS_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt) +{ + return RomDriver_PDS_Enable(cfg, cfg4, pdsSleepCnt); +} +#endif + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3) +{ + return RomDriver_PDS_Force_Config(cfg2, cfg3); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg) +{ + return RomDriver_PDS_RAM_Config(ramCfg); +} + +#if 0 +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, PDS_RAM_CFG_Type *ramCfg, uint32_t pdsSleepCnt) +{ + return RomDriver_PDS_Default_Level_Config(defaultLvCfg, ramCfg, pdsSleepCnt); +} +#endif + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Trim_RC32M(void) +{ + return RomDriver_PDS_Trim_RC32M(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_RC32M_As_PLL_Ref(void) +{ + return RomDriver_PDS_Select_RC32M_As_PLL_Ref(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_XTAL_As_PLL_Ref(void) +{ + return RomDriver_PDS_Select_XTAL_As_PLL_Ref(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType) +{ + return RomDriver_PDS_Power_On_PLL(xtalType); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_All_Clks(void) +{ + return RomDriver_PDS_Enable_PLL_All_Clks(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_All_Clks(void) +{ + return RomDriver_PDS_Disable_PLL_All_Clks(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk) +{ + return RomDriver_PDS_Enable_PLL_Clk(pllClk); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk) +{ + return RomDriver_PDS_Disable_PLL_Clk(pllClk); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_Off_PLL(void) +{ + return RomDriver_PDS_Power_Off_PLL(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SEC_Eng_Turn_On_Sec_Ring(void) +{ + return RomDriver_SEC_Eng_Turn_On_Sec_Ring(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SEC_Eng_Turn_Off_Sec_Ring(void) +{ + return RomDriver_SEC_Eng_Turn_Off_Sec_Ring(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg) +{ + return RomDriver_SFlash_Init(pSfCtrlCfg); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode) +{ + return RomDriver_SFlash_SetSPIMode(mode); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) +{ + return RomDriver_SFlash_Read_Reg(flashCfg, regIndex, regValue, regLen); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) +{ + return RomDriver_SFlash_Write_Reg(flashCfg, regIndex, regValue, regLen); +} + +__ALWAYS_INLINE +BL_Sts_Type ATTR_TCM_SECTION SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_Busy(flashCfg); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_Write_Enable(flashCfg); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_Qspi_Enable(flashCfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_Volatile_Reg_Write_Enable(flashCfg); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_Chip_Erase(flashCfg); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum) +{ + return RomDriver_SFlash_Sector_Erase(flashCfg, secNum); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) +{ + return RomDriver_SFlash_Blk32_Erase(flashCfg, blkNum); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) +{ + return RomDriver_SFlash_Blk64_Erase(flashCfg, blkNum); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr) +{ + return RomDriver_SFlash_Erase(flashCfg, startaddr, endaddr); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) +{ + return RomDriver_SFlash_Program(flashCfg, ioMode, addr, data, len); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_GetUniqueId(uint8_t *data, uint8_t idLen) +{ + return RomDriver_SFlash_GetUniqueId(data, idLen); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data) +{ + return RomDriver_SFlash_GetJedecId(flashCfg, data); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_GetDeviceId(uint8_t *data) +{ + return RomDriver_SFlash_GetDeviceId(data); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_Powerdown(void) +{ + return RomDriver_SFlash_Powerdown(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_Releae_Powerdown(flashCfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_SetBurstWrap(flashCfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_DisableBurstWrap(flashCfg); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_Software_Reset(flashCfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg) +{ + return RomDriver_SFlash_Reset_Continue_Read(flashCfg); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len) +{ + return RomDriver_SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, addr, len); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead) +{ + return RomDriver_SFlash_IDbus_Read_Enable(flashCfg, ioMode, contRead); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Enable_Set(uint8_t wayDisable) +{ + return RomDriver_SFlash_Cache_Enable_Set(wayDisable); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Flush(void) +{ + return RomDriver_SFlash_Cache_Flush(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint8_t wayDisable) +{ + return RomDriver_SFlash_Cache_Read_Enable(flashCfg, ioMode, contRead, wayDisable); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh) +{ + return RomDriver_SFlash_Cache_Hit_Count_Get(hitCountLow, hitCountHigh); +} + +__ALWAYS_INLINE +uint32_t ATTR_TCM_SECTION SFlash_Cache_Miss_Count_Get(void) +{ + return RomDriver_SFlash_Cache_Miss_Count_Get(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SFlash_Cache_Read_Disable(void) +{ + return RomDriver_SFlash_Cache_Read_Disable(); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len) +{ + return RomDriver_SFlash_Read(flashCfg, ioMode, contRead, addr, data, len); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen) +{ + return RomDriver_SFlash_Read_Reg_With_Cmd(flashCfg, readRegCmd, regValue, regLen); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen) +{ + return RomDriver_SFlash_Write_Reg_With_Cmd(flashCfg, writeRegCmd, regValue, regLen); +} + +#if 0 +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead) +{ + return RomDriver_SFlash_Restore_From_Powerdown(pFlashCfg, flashContRead); +} +#endif + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin) +{ + return RomDriver_SF_Cfg_Init_Ext_Flash_Gpio(extFlashPin); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Cfg_Init_Internal_Flash_Gpio(void) +{ + return RomDriver_SF_Cfg_Init_Internal_Flash_Gpio(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin) +{ + return RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio(extFlashPin); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Cfg_Restore_GPIO17_Fun(uint8_t fun) +{ + return RomDriver_SF_Cfg_Restore_GPIO17_Fun(fun); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg) +{ + return RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg, uint8_t restoreDefault) +{ + return RomDriver_SF_Cfg_Init_Flash_Gpio(flashPinCfg, restoreDefault); +} + +__ALWAYS_INLINE +uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg) +{ + return RomDriver_SF_Cfg_Flash_Identify(callFromFlash, autoScan, flashPinCfg, restoreDefault, pFlashCfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg) +{ + return RomDriver_SF_Ctrl_Enable(cfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Sel sel) +{ + return RomDriver_SF_Ctrl_Select_Pad(sel); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner) +{ + return RomDriver_SF_Ctrl_Set_Owner(owner); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Disable(void) +{ + return RomDriver_SF_Ctrl_Disable(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_BE(void) +{ + return RomDriver_SF_Ctrl_AES_Enable_BE(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_LE(void) +{ + return RomDriver_SF_Ctrl_AES_Enable_LE(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked) +{ + return RomDriver_SF_Ctrl_AES_Set_Region(region, enable, hwKey, startAddr, endAddr, locked); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) +{ + return RomDriver_SF_Ctrl_AES_Set_Key(region, key, keyType); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) +{ + return RomDriver_SF_Ctrl_AES_Set_Key_BE(region, key, keyType); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset) +{ + return RomDriver_SF_Ctrl_AES_Set_IV(region, iv, addrOffset); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset) +{ + return RomDriver_SF_Ctrl_AES_Set_IV_BE(region, iv, addrOffset); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Enable(void) +{ + return RomDriver_SF_Ctrl_AES_Enable(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_AES_Disable(void) +{ + return RomDriver_SF_Ctrl_AES_Disable(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset) +{ + return RomDriver_SF_Ctrl_Set_Flash_Image_Offset(addrOffset); +} + +__ALWAYS_INLINE +uint32_t ATTR_TCM_SECTION SF_Ctrl_Get_Flash_Image_Offset(void) +{ + return RomDriver_SF_Ctrl_Get_Flash_Image_Offset(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType) +{ + return RomDriver_SF_Ctrl_Select_Clock(sahbType); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg) +{ + return RomDriver_SF_Ctrl_SendCmd(cfg); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) +{ + return RomDriver_SF_Ctrl_Icache_Set(cfg, cmdValid); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Icache2_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) +{ + return RomDriver_SF_Ctrl_Icache2_Set(cfg, cmdValid); +} + +__ALWAYS_INLINE +BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_GetBusyState(void) +{ + return RomDriver_SF_Ctrl_GetBusyState(); +} + +__ALWAYS_INLINE +uint8_t ATTR_TCM_SECTION SF_Ctrl_Is_AES_Enable(void) +{ + return RomDriver_SF_Ctrl_Is_AES_Enable(); +} + +__ALWAYS_INLINE +uint8_t ATTR_TCM_SECTION SF_Ctrl_Get_Clock_Delay(void) +{ + return RomDriver_SF_Ctrl_Get_Clock_Delay(); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION SF_Ctrl_Set_Clock_Delay(uint8_t delay) +{ + return RomDriver_SF_Ctrl_Set_Clock_Delay(delay); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset) +{ + return RomDriver_XIP_SFlash_State_Save(pFlashCfg, offset); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset) +{ + return RomDriver_XIP_SFlash_State_Restore(pFlashCfg, offset); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, uint32_t endaddr) +{ + return RomDriver_XIP_SFlash_Erase_Need_Lock(pFlashCfg, startaddr, endaddr); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len) +{ + return RomDriver_XIP_SFlash_Write_Need_Lock(pFlashCfg, addr, data, len); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len) +{ + return RomDriver_XIP_SFlash_Read_Need_Lock(pFlashCfg, addr, data, len); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data) +{ + return RomDriver_XIP_SFlash_GetJedecId_Need_Lock(pFlashCfg, data); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data) +{ + return RomDriver_XIP_SFlash_GetDeviceId_Need_Lock(pFlashCfg, data); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen) +{ + return RomDriver_XIP_SFlash_GetUniqueId_Need_Lock(pFlashCfg, data, idLen); +} + +__ALWAYS_INLINE +BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len) +{ + return RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock(addr, data, len); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION XIP_SFlash_Opt_Enter(uint8_t *aesEnable) +{ + return RomDriver_XIP_SFlash_Opt_Enter(aesEnable); +} + +__ALWAYS_INLINE +void ATTR_TCM_SECTION XIP_SFlash_Opt_Exit(uint8_t aesEnable) +{ + return RomDriver_XIP_SFlash_Opt_Exit(aesEnable); +} + +__ALWAYS_INLINE +uint32_t ATTR_TCM_SECTION BFLB_Soft_CRC32(void *dataIn, uint32_t len) +{ + return RomDriver_BFLB_Soft_CRC32(dataIn, len); +} \ No newline at end of file diff --git a/drivers/soc/bl602/port/bl602_clock.c b/drivers/soc/bl602/port/bl602_clock.c new file mode 100644 index 00000000..735b9311 --- /dev/null +++ b/drivers/soc/bl602/port/bl602_clock.c @@ -0,0 +1,19 @@ +#include "bflb_clock.h" +#include "bl602_clock.h" + +uint32_t bflb_clk_get_system_clock(uint8_t type) +{ + return 0; +} + +uint32_t bflb_clk_get_peripheral_clock(uint8_t type, uint8_t idx) +{ + if (type == BFLB_DEVICE_TYPE_UART) { + return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_UART0); + } else if (type == BFLB_DEVICE_TYPE_SPI) { + return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_SPI0); + } else if (type == BFLB_DEVICE_TYPE_I2C) { + return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_I2C0); + } + return 0; +} \ No newline at end of file diff --git a/drivers/soc/bl602/startup/interrupt.c b/drivers/soc/bl602/startup/interrupt.c new file mode 100644 index 00000000..5ef58d0a --- /dev/null +++ b/drivers/soc/bl602/startup/interrupt.c @@ -0,0 +1,191 @@ +/** + * @file interrupt.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "bflb_irq.h" + +typedef void (*pFunc)(void); + +struct bflb_irq_info_s g_irqvector[CONFIG_IRQ_NUM]; + +extern void default_trap_handler(void); +extern void default_interrupt_handler(void); + +const pFunc __Vectors[] __attribute__((section(".init"), aligned(64))) = { + default_interrupt_handler, /* */ + default_interrupt_handler, /* */ + default_interrupt_handler, /* */ + default_interrupt_handler, /* 3 */ + default_interrupt_handler, /* */ + default_interrupt_handler, /* */ + default_interrupt_handler, /* */ + default_interrupt_handler, /* 7 */ + default_interrupt_handler, /* */ + default_interrupt_handler, /* */ + default_interrupt_handler, /* */ + default_interrupt_handler, /* 11 */ + default_interrupt_handler, /* 12 */ + default_interrupt_handler, /* */ + default_interrupt_handler, /* */ + default_interrupt_handler, /* */ + default_interrupt_handler, /* 16 + 0 */ + default_interrupt_handler, /* 16 + 1 */ + default_interrupt_handler, /* 16 + 2 */ + default_interrupt_handler, /* 16 + 3 */ + default_interrupt_handler, /* 16 + 4 */ + default_interrupt_handler, /* 16 + 5 */ + default_interrupt_handler, /* 16 + 6 */ + default_interrupt_handler, /* 16 + 7 */ + default_interrupt_handler, /* 16 + 8 */ + default_interrupt_handler, /* 16 + 9 */ + default_interrupt_handler, /* 16 + 10 */ + default_interrupt_handler, /* 16 + 11 */ + default_interrupt_handler, /* 16 + 12 */ + default_interrupt_handler, /* 16 + 13 */ + default_interrupt_handler, /* 16 + 14 */ + default_interrupt_handler, /* 16 + 15 */ + default_interrupt_handler, /* 16 + 16 */ + default_interrupt_handler, /* 16 + 17 */ + default_interrupt_handler, /* 16 + 18 */ + default_interrupt_handler, /* 16 + 19 */ + default_interrupt_handler, /* 16 + 20 */ + default_interrupt_handler, /* 16 + 21 */ + default_interrupt_handler, /* 16 + 22 */ + default_interrupt_handler, /* 16 + 23 */ + default_interrupt_handler, /* 16 + 24 */ + default_interrupt_handler, /* 16 + 25 */ + default_interrupt_handler, /* 16 + 26 */ + default_interrupt_handler, /* 16 + 27 */ + default_interrupt_handler, /* 16 + 28 */ + default_interrupt_handler, /* 16 + 29 */ + default_interrupt_handler, /* 16 + 30 */ + default_interrupt_handler, /* 16 + 31 */ + default_interrupt_handler, /* 16 + 32 */ + default_interrupt_handler, /* 16 + 33 */ + default_interrupt_handler, /* 16 + 34 */ + default_interrupt_handler, /* 16 + 35 */ + default_interrupt_handler, /* 16 + 36 */ + default_interrupt_handler, /* 16 + 37 */ + default_interrupt_handler, /* 16 + 38 */ + default_interrupt_handler, /* 16 + 39 */ + default_interrupt_handler, /* 16 + 40 */ + default_interrupt_handler, /* 16 + 41 */ + default_interrupt_handler, /* 16 + 42 */ + default_interrupt_handler, /* 16 + 43 */ + default_interrupt_handler, /* 16 + 44 */ + default_interrupt_handler, /* 16 + 45 */ + default_interrupt_handler, /* 16 + 46 */ + default_interrupt_handler, /* 16 + 47 */ + default_interrupt_handler, /* 16 + 48 */ + default_interrupt_handler, /* 16 + 49 */ + default_interrupt_handler, /* 16 + 50 */ + default_interrupt_handler, /* 16 + 51 */ + default_interrupt_handler, /* 16 + 52 */ + default_interrupt_handler, /* 16 + 53 */ + default_interrupt_handler, /* 16 + 54 */ + default_interrupt_handler, /* 16 + 55 */ + default_interrupt_handler, /* 16 + 56 */ + default_interrupt_handler, /* 16 + 57 */ + default_interrupt_handler, /* 16 + 58 */ + default_interrupt_handler, /* 16 + 59 */ + default_interrupt_handler, /* 16 + 60 */ + default_interrupt_handler, /* 16 + 61 */ + default_interrupt_handler, /* 16 + 62 */ + default_interrupt_handler, /* 16 + 63 */ +}; + +void exception_entry(void) +{ + unsigned long cause; + unsigned long epc; + unsigned long tval; + + printf("exception_entry\r\n"); + + cause = READ_CSR(CSR_MCAUSE); + printf("mcause=%08x\r\n", (int)cause); + epc = READ_CSR(CSR_MEPC); + printf("mepc:%08x\r\n", (int)epc); + tval = READ_CSR(CSR_MTVAL); + printf("mtval:%08x\r\n", (int)tval); + + cause = (cause & 0x3ff); + + const char *mcause_str[] = { + "Instruction address misaligned", + "Instruction access fault", + "Illegal instruction", + "Breakpoint", + "Load address misaligned", + "Load access fault", + "Store/AMO address misaligned", + "Store/AMO access fault", + "Environment call from U-mode", + "Environment call from S-mode", + "RSVD", + "Environment call from M-mode", + "Instruction page fault", + "Load page fault", + "RSVD", + "Store/AMO page fault" + }; + + printf("%s\r\n", mcause_str[cause & 0xf]); + + if ((cause == 8) || (cause == 11)) { + epc += 4; + WRITE_CSR(CSR_MEPC, epc); + } else { + while (1) { + } + } +} + +void interrupt_entry(void) +{ + irq_callback handler; + void *arg; + volatile uint32_t mcause = 0UL; + uint32_t irq_num; + + mcause = READ_CSR(CSR_MCAUSE); + irq_num = mcause & 0x3FF; + + if (irq_num < CONFIG_IRQ_NUM) { + handler = g_irqvector[irq_num].handler; + arg = g_irqvector[irq_num].arg; + if (handler) { + handler(irq_num, arg); + } else { + } + } else { + } +} + +__attribute__((interrupt, aligned(64))) void default_trap_handler(void) +{ + exception_entry(); +} + +__attribute__((interrupt)) __attribute__((weak)) void default_interrupt_handler(void) +{ + interrupt_entry(); +} \ No newline at end of file diff --git a/drivers/soc/bl602/startup/start.S b/drivers/soc/bl602/startup/start.S new file mode 100644 index 00000000..29845cdd --- /dev/null +++ b/drivers/soc/bl602/startup/start.S @@ -0,0 +1,96 @@ +/* Copyright 2018 SiFive, Inc */ +/* SPDX-License-Identifier: Apache-2.0 */ +#include + +/* This code executes before _start, which is contained inside the C library. + * In embedded systems we want to ensure that _enter, which contains the first + * code to be executed, can be loaded at a specific address. To enable this + * feature we provide the '.text.metal.init.enter' section, which is + * defined to have the first address being where execution should start. */ + .section .init + .global __start + .type __start, %function +__start: + .cfi_startproc + + /* Inform the debugger that there is nowhere to backtrace past _enter. */ + .cfi_undefined ra + + /* The absolute first thing that must happen is configuring the global + * pointer register, which must be done with relaxation disabled because + * it's not valid to obtain the address of any symbol without GP + * configured. The C environment might go ahead and do this again, but + * that's safe as it's a fixed register. */ +.option push +.option norelax + la gp, __global_pointer$ +.option pop + + /* Disable global interrupt */ + csrci mstatus,8 + + /* Set up a simple trap vector to catch anything that goes wrong early in + * the boot process. */ + la t0, default_trap_handler + # /* enable CLIC Vectored mode */ + ori t0,t0,3 + csrw mtvec, t0 + /* enable chicken bit if core is bullet series*/ + la t0, __metal_chicken_bit + beqz t0, 1f + csrwi 0x7C1, 0 +1: + + /* There may be pre-initialization routines inside the MBI code that run in + * C, so here we set up a C environment. First we set up a stack pointer, + * which is left as a weak reference in order to allow initialization + * routines that do not need a stack to be set up to transparently be + * called. */ + .weak __StackTop + la sp, __StackTop + + /* Intial the mtvt, MUST BE 64 bytes aligned*/ + .weak __Vectors + la t0, __Vectors + csrw mtvt, t0 + +#ifdef __riscv_float_abi_single + /* deal with FP */ + /* Is F extension present? */ + csrr t0, misa + andi t0, t0, (1 << ('F' - 'A')) + beqz t0, 1f + /* If so, enable it */ + li t0, MSTATUS_FS + csrs mstatus, t0 + fssr x0 +1: +#endif + + /* Check for an initialization routine and call it if one exists, otherwise + * just skip over the call entirely. Note that __metal_initialize isn't + * actually a full C function, as it doesn't end up with the .bss or .data + * segments having been initialized. This is done to avoid putting a + * burden on systems that can be initialized without having a C environment + * set up. */ + jal SystemInit + + /* start load code to itcm like. */ + jal start_load + + jal System_Post_Init + + /* At this point we can enter the C runtime's startup file. The arguments + * to this function are designed to match those provided to the SEE, just + * so we don't have to write another ABI. */ + csrr a0, mhartid + li a1, 0 + li a2, 0 + jal main + + csrci mstatus, (1 << 3) + +__exit: + j __exit + + .cfi_endproc diff --git a/drivers/soc/bl602/startup/start_load.c b/drivers/soc/bl602/startup/start_load.c new file mode 100644 index 00000000..1bc8d924 --- /dev/null +++ b/drivers/soc/bl602/startup/start_load.c @@ -0,0 +1,114 @@ +/** + * @file start_load.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include + +#define __STARTUP_CLEAR_BSS 1 + +/*---------------------------------------------------------------------------- + Linker generated Symbols + *----------------------------------------------------------------------------*/ +extern uint32_t __itcm_load_addr; +extern uint32_t __dtcm_load_addr; +extern uint32_t __system_ram_load_addr; +extern uint32_t __ram_load_addr; + +extern uint32_t __text_code_start__; +extern uint32_t __text_code_end__; +extern uint32_t __tcm_code_start__; +extern uint32_t __tcm_code_end__; +extern uint32_t __tcm_data_start__; +extern uint32_t __tcm_data_end__; +extern uint32_t __system_ram_data_start__; +extern uint32_t __system_ram_data_end__; +extern uint32_t __ram_data_start__; +extern uint32_t __ram_data_end__; +extern uint32_t __bss_start__; +extern uint32_t __bss_end__; +extern uint32_t __noinit_data_start__; +extern uint32_t __noinit_data_end__; + +extern uint32_t __StackTop; +extern uint32_t __StackLimit; +extern uint32_t __HeapBase; +extern uint32_t __HeapLimit; + +//extern uint32_t __copy_table_start__; +//extern uint32_t __copy_table_end__; +//extern uint32_t __zero_table_start__; +//extern uint32_t __zero_table_end__; + +void start_load(void) +{ + uint32_t *pSrc, *pDest; + uint32_t *pTable __attribute__((unused)); + + /* Copy ITCM code */ + pSrc = &__itcm_load_addr; + pDest = &__tcm_code_start__; + + for (; pDest < &__tcm_code_end__;) { + *pDest++ = *pSrc++; + } + + /* Copy DTCM code */ + pSrc = &__dtcm_load_addr; + pDest = &__tcm_data_start__; + + for (; pDest < &__tcm_data_end__;) { + *pDest++ = *pSrc++; + } + + /* BF Add system RAM data copy */ + pSrc = &__system_ram_load_addr; + pDest = &__system_ram_data_start__; + + for (; pDest < &__system_ram_data_end__;) { + *pDest++ = *pSrc++; + } + + /* BF Add OCARAM data copy */ + pSrc = &__ram_load_addr; + pDest = &__ram_data_start__; + + for (; pDest < &__ram_data_end__;) { + *pDest++ = *pSrc++; + } + +#ifdef __STARTUP_CLEAR_BSS + /* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + pDest = &__bss_start__; + + for (; pDest < &__bss_end__;) { + *pDest++ = 0ul; + } + +#endif +} \ No newline at end of file diff --git a/drivers/soc/bl602/startup/system_bl602.c b/drivers/soc/bl602/startup/system_bl602.c new file mode 100644 index 00000000..89360e6f --- /dev/null +++ b/drivers/soc/bl602/startup/system_bl602.c @@ -0,0 +1,83 @@ +/** + * @file system_bl702.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "bl602_glb.h" +#include + +void SystemInit(void) +{ + uint32_t *p; + uint8_t i; + uint32_t tmpVal = 0; + uint8_t flashCfg = 0; + uint8_t psramCfg = 0; + uint8_t isInternalFlash = 0; + uint8_t isInternalPsram = 0; + + /* global IRQ disable */ + __disable_irq(); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal |= (1 << 8); /*mask pds wakeup*/ + tmpVal |= (1 << 10); /*mask rf done*/ + tmpVal |= (1 << 11); /*mask pll done*/ + tmpVal &= ~(0xff << 16); /*mask all pds wakeup source int*/ + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + /* GLB_Set_EM_Sel(GLB_EM_0KB); */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x00); //GLB_EM_0KB + BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal); + + /* Restore default setting*/ + /* GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, 0x00); //UART_SIG_SWAP_NONE + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + /* CLear all interrupt */ + p = (uint32_t *)(CLIC_HART0_BASE + CLIC_INTIE_OFFSET); + + for (i = 0; i < (IRQn_LAST + 3) / 4; i++) { + p[i] = 0; + } + + p = (uint32_t *)(CLIC_HART0_BASE + CLIC_INTIP_OFFSET); + + for (i = 0; i < (IRQn_LAST + 3) / 4; i++) { + p[i] = 0; + } + + BL_WR_REG(GLB_BASE, GLB_UART_SIG_SEL_0, 0xffffffff); + + /* init bor for all platform */ + // HBN_BOR_CFG_Type borCfg = { 0 /* pu_bor */, 0 /* irq_bor_en */, 1 /* bor_vth */, 0 /* bor_sel */ }; + // HBN_Set_BOR_Cfg(&borCfg); +} + +void System_Post_Init(void) +{ + PDS_Trim_RC32M(); + HBN_Trim_RC32K(); + /* global IRQ enable */ + __enable_irq(); +} \ No newline at end of file