[update] update lhal, soc and demos

* Add flash driver and init in boards.
* Add timeout for all poll wait apis
* Add 808 d0 startup to bringup
* Update lhal device tables
* Update demos

examples/peripherals/wdg/wdg_clksource_check/CMakeLists.txt

@@ -0,0 +1,9 @@
+cmake_minimum_required(VERSION 3.15)
+
+include(proj.conf)
+
+find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE})
+
+sdk_set_main_file(main.c)
+
+project(wdg_clksource_check)

examples/peripherals/wdg/wdg_clksource_check/Makefile

@@ -0,0 +1,13 @@
+SDK_DEMO_PATH ?= .
+BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../../..
+
+export BL_SDK_BASE
+
+CHIP ?= bl616
+BOARD ?= bl616dk
+CROSS_COMPILE ?= riscv64-unknown-elf-
+
+# add custom cmake definition
+#cmake_definition+=-Dxxx=sss
+
+include $(BL_SDK_BASE)/project.build

examples/peripherals/wdg/wdg_clksource_check/main.c

@@ -0,0 +1,80 @@
+#include "bflb_mtimer.h"
+#include "bflb_wdg.h"
+#include "board.h"
+
+#if !defined(BL702L)
+uint8_t wdg_clk_src_type[] = {
+    WDG_CLKSRC_BCLK,
+    WDG_CLKSRC_32K,
+    WDG_CLKSRC_1K,
+    WDG_CLKSRC_XTAL,
+};
+#else
+uint8_t wdg_clk_src_type[] = {
+    WDG_CLKSRC_32K,
+    WDG_CLKSRC_1K,
+    WDG_CLKSRC_XTAL,
+};
+#endif
+
+int main(void)
+{
+    uint32_t i = 0;
+    uint32_t j = 0;
+    uint32_t cnt = 0;
+
+    board_init();
+    printf("Timer clksource check\n");
+
+    struct bflb_device_s *wdt;
+    wdt = bflb_device_get_by_name("watchdog");
+
+    /* watchdog clk = clock_source/(div + 1)*/
+    struct bflb_wdg_config_s cfg;
+    cfg.clock_source = WDG_CLKSRC_32K;
+    cfg.clock_div = 0;
+    cfg.comp_val = 0xffff;
+    cfg.mode = WDG_MODE_INTERRUPT;
+
+    for (i = 0; i < sizeof(wdg_clk_src_type) / sizeof(wdg_clk_src_type[0]); i++) {
+        cnt = 0;
+
+        if (wdg_clk_src_type[i] == WDG_CLKSRC_XTAL) {
+            printf("Watchdog Src Clk is XTAL\r\n");
+            cfg.clock_div = 199;
+        } else if (wdg_clk_src_type[i] == WDG_CLKSRC_32K) {
+            printf("Watchdog Src Clk is 32K\r\n");
+            cfg.clock_div = 1;
+        } else if (wdg_clk_src_type[i] == WDG_CLKSRC_1K) {
+            printf("Watchdog Src Clk is 1K\r\n");
+            cfg.clock_div = 1;
+        }
+#if !defined(BL702L)
+        else if (wdg_clk_src_type[i] == WDG_CLKSRC_BCLK) {
+            printf("Watchdog Src Clk is BCLK\r\n");
+            cfg.clock_div = 199;
+        }
+#endif
+        else {
+            printf("Other clock, not test.\r\n");
+            continue;
+        }
+
+        cfg.clock_source = wdg_clk_src_type[i];
+        bflb_wdg_init(wdt, &cfg);
+
+        for (j = 0; j < 10; j++) {
+            bflb_wdg_reset_countervalue(wdt);
+            bflb_wdg_start(wdt);
+            bflb_mtimer_delay_ms(200);
+            cnt = bflb_wdg_get_countervalue(wdt);
+            bflb_wdg_stop(wdt);
+            bflb_mtimer_delay_ms(10);
+            printf("Delay 200ms, div = %lu, test %lu times, cnt: %lu\r\n", cfg.clock_div + 1, j, cnt);
+        }
+    }
+    printf("case success.\r\n");
+    while (1) {
+        bflb_mtimer_delay_ms(1500);
+    }
+}

examples/peripherals/wdg/wdg_clksource_check/proj.conf

@@ -0,0 +1 @@
+#set(CONFIG_XXX 1)

examples/peripherals/wdg/wdg_int/main.c

@@ -7,8 +7,8 @@ static volatile uint8_t wdg_int_arrived = 0;
 
 void wdg_isr(int irq, void *arg)
 {
-    wdg_int_arrived = 1;
     bflb_wdg_compint_clear(wdg);
+    wdg_int_arrived = 1;
 }
 
 int main(void)