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[refactor][cam] refactor camera driver,add standard interfaces for camera
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parent
9792e36ab4
commit
e27aedace2
20 changed files with 404 additions and 259 deletions
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@ -77,7 +77,7 @@
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#define BSP_DAC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ
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#define BSP_DAC_CLOCK_DIV 1
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#endif
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#if defined(BSP_USING_CAM)
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#if defined(BSP_USING_CAM0)
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#define BSP_CAM_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_96M
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#define BSP_CAM_CLOCK_DIV 3
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#endif
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@ -72,7 +72,7 @@
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#define BSP_DAC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ
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#define BSP_DAC_CLOCK_DIV 1
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#endif
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#if defined(BSP_USING_CAM)
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#if defined(BSP_USING_CAM0)
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#define BSP_CAM_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_96M
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#define BSP_CAM_CLOCK_DIV 3
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#endif
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@ -76,7 +76,7 @@
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#define BSP_DAC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ
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#define BSP_DAC_CLOCK_DIV 1
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#endif
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#if defined(BSP_USING_CAM)
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#if defined(BSP_USING_CAM0)
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#define BSP_CAM_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_96M
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#define BSP_CAM_CLOCK_DIV 3
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#endif
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@ -44,7 +44,7 @@
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#define BSP_USING_QDEC1
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#define BSP_USING_QDEC2
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#define BSP_USING_USB
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#define BSP_USING_CAM
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#define BSP_USING_CAM0
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/* ----------------------*/
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/* PERIPHERAL With DMA LIST */
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@ -125,6 +125,8 @@
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.clk_phase = SPI_PHASE_1EDGE, \
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.datasize = SPI_DATASIZE_8BIT, \
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.fifo_threshold = 4, \
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.pin_swap_enable = 1, \
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.delitch_cnt = 0, \
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}
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#endif
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#endif
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@ -462,4 +464,24 @@
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#endif
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#endif
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#if defined(BSP_USING_CAM0)
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#ifndef CAM0_CONFIG
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#define CAM0_CONFIG \
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{ \
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.id = 0, \
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.software_mode = CAM_AUTO_MODE, \
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.frame_mode = CAM_FRAME_INTERLEAVE_MODE, \
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.yuv_format = CAM_YUV_FORMAT_YUV422, \
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.hsp = CAM_HSPOLARITY_LOW, \
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.vsp = CAM_VSPOLARITY_LOW, \
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.cam_write_ram_addr = 0, \
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.cam_write_ram_size = 0, \
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.cam_frame_size = 0, \
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.cam_write_ram_addr1 = 0, \
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.cam_write_ram_size1 = 0, \
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.cam_frame_size1 = 0, \
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}
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#endif
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#endif
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#endif
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@ -72,7 +72,7 @@
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#define BSP_DAC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ
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#define BSP_DAC_CLOCK_DIV 1
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#endif
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#if defined(BSP_USING_CAM)
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#if defined(BSP_USING_CAM0)
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#define BSP_CAM_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_96M
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#define BSP_CAM_CLOCK_DIV 3
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#endif
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@ -125,6 +125,8 @@
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.clk_phase = SPI_PHASE_1EDGE, \
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.datasize = SPI_DATASIZE_8BIT, \
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.fifo_threshold = 1, \
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.pin_swap_enable = 1, \
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.delitch_cnt = 0, \
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}
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#endif
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#endif
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@ -60,7 +60,7 @@
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#define BSP_DAC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ
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#define BSP_DAC_CLOCK_DIV 1
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#endif
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#if defined(BSP_USING_CAM)
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#if defined(BSP_USING_CAM0)
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#define BSP_CAM_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_96M
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#define BSP_CAM_CLOCK_DIV 3
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#endif
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@ -679,24 +679,37 @@ uint8_t image_sensor_init(BL_Fun_Type mjpeg_en, cam_device_t *cam_cfg, mjpeg_dev
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return 1;
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}
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cam_stop();
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mjpeg_stop();
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if (mjpeg_en) {
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#if (CAM_MODE == CAM_USING_INT_MODE)
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cam_init(cam_cfg, DEVICE_OFLAG_INT);
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#elif (CAM_MODE == CAM_USING_POLL_MODE)
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cam_init(cam_cfg, DEVICE_OFLAG_POLL);
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#endif
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mjpeg_init(mjpeg_cfg);
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} else {
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#if (CAM_MODE == CAM_USING_INT_MODE)
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cam_init(cam_cfg, DEVICE_OFLAG_INT);
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#elif (CAM_MODE == CAM_USING_POLL_MODE)
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cam_init(cam_cfg, DEVICE_OFLAG_POLL);
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#endif
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cam_register(CAM0_INDEX, "camera0");
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struct device *cam0 = device_find("camera0");
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if(!cam0)
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{
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MSG("cam do not find\r\n");
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return 1;
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}
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if (mjpeg_en) {
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mjpeg_init(mjpeg_cfg);
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}
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CAM_DEV(cam0)->hsp = CAM_HSPOLARITY_HIGH;
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CAM_DEV(cam0)->vsp = CAM_VSPOLARITY_HIGH;
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CAM_DEV(cam0)->software_mode = cam_cfg->software_mode;
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CAM_DEV(cam0)->frame_mode = cam_cfg->frame_mode;
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CAM_DEV(cam0)->yuv_format = cam_cfg->yuv_format;
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CAM_DEV(cam0)->cam_write_ram_addr = cam_cfg->cam_write_ram_addr;
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CAM_DEV(cam0)->cam_write_ram_size = cam_cfg->cam_write_ram_size;
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CAM_DEV(cam0)->cam_frame_size = cam_cfg->cam_frame_size;
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CAM_DEV(cam0)->cam_write_ram_addr1 = cam_cfg->cam_write_ram_addr1;
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CAM_DEV(cam0)->cam_write_ram_size1 = cam_cfg->cam_write_ram_size1;
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CAM_DEV(cam0)->cam_frame_size1 = cam_cfg->cam_frame_size1;
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#if (CAM_MODE == CAM_USING_INT_MODE)
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device_open(cam0, DEVICE_OFLAG_INT_RX);
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#elif (CAM_MODE == CAM_USING_POLL_MODE)
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device_open(cam0, DEVICE_OFLAG_STREAM_RX);
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#endif
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return SUCCESS;
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}
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