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[update][board] enable fw header for new flash tool

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This commit is contained in:
jzlv 2023-02-24 21:21:34 +08:00
parent 15a70512a7
commit e70e482d21
46 changed files with 601 additions and 1042 deletions
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4
bsp/board/bl602dk/CMakeLists.txt
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@ -1,8 +1,8 @@
sdk_add_include_directories(.)
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/board.c)
# target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/fw_header.c)
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/fw_header.c)
sdk_set_linker_script(bl602_flash.ld)
# sdk_add_link_options(-ufw_header)
sdk_add_link_options(-ufw_header)

19
bsp/board/bl602dk/bl602_flash.ld
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@ -163,21 +163,7 @@ SECTIONS
ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
/*************************************************************************/
__system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
.system_ram_data_region : AT (__system_ram_load_addr)
{
. = ALIGN(4);
__system_ram_data_start__ = .;
*(.system_ram)
*(.nocache_ram)
. = ALIGN(4);
__system_ram_data_end__ = .;
} > ram_memory
__ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
__ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
/* Data section */
RAM_DATA : AT (__ram_load_addr)
@ -194,6 +180,8 @@ SECTIONS
*(.sdata2)
*(.sdata2.*)
*(.nocache_ram)
. = ALIGN(4);
__bflog_tags_start__ = .;
*(.bflog_tags_array)
@ -221,6 +209,7 @@ SECTIONS
__noinit_data_start__ = .;
*(.noinit_data*)
*(.nocache_noinit_ram)
. = ALIGN(4);
__noinit_data_end__ = .;

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bsp/board/bl602dk/builtin_imgs/boot2_bl602_debug_v8.0.7.bin Normal file
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bsp/board/bl602dk/builtin_imgs/boot2_bl602_release_v8.0.7.bin Normal file
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bsp/board/bl602dk/builtin_imgs/mfg_bl602_gu_33c89c10b_40m_autoboot_v2.71.bin Normal file
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bsp/board/bl602dk/builtin_imgs/mfg_bl602_gu_33c89c10b_40m_v2.71.bin Normal file
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0
bsp/board/bl602dk/config/.gitkeep Normal file
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4
bsp/board/bl602dk/fw_header.c
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@ -111,7 +111,11 @@ __attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
.img_segment_info.img_len = 0x00010000, /* image length or segment count */
.rsvd0 = 0x00000000,
#ifdef BFLB_BOOT2
.img_start.flashoffset = 0x00002000, /* flash controller offset */
#else
.img_start.flashoffset = 0x00001000, /* flash controller offset */
#endif
.hash = { 0xdeadbeef }, /* hash of the image */
.crc32 = 0xdeadbeef /* 4 */

3
bsp/board/bl602dk/fw_header.h
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@ -162,4 +162,7 @@ struct __attribute__((packed, aligned(4))) bootheader_t {
uint32_t crc32;
};
#define BFLB_FW_LENGTH_OFFSET 120
#define BFLB_FW_HASH_OFFSET 132
#endif

4
bsp/board/bl616dk/CMakeLists.txt
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@ -1,7 +1,7 @@
sdk_add_include_directories(.)
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/board.c)
# target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/fw_header.c)
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/fw_header.c)
sdk_set_linker_script(bl616_flash.ld)
@ -9,4 +9,4 @@ if(CONFIG_PSRAM)
sdk_add_compile_definitions(-DCONFIG_PSRAM)
endif()
# sdk_add_link_options(-ufw_header)
sdk_add_link_options(-ufw_header)

24
bsp/board/bl616dk/bl616_flash.ld
View file

@ -185,28 +185,7 @@ SECTIONS
__nocache_ram_data_end__ = .;
} > nocache_ram_memory
__system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
.system_ram_data_region : AT (__system_ram_load_addr)
{
. = ALIGN(4);
__system_ram_data_start__ = .;
*(.system_ram)
. = ALIGN(4);
__system_ram_data_end__ = .;
} > ram_memory
.system_ram_noinit_data_region (NOLOAD) :
{
. = ALIGN(4);
*(.system_ram_noinit)
. = ALIGN(4);
} > ram_memory
__ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
__ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
/* Data section */
RAM_DATA : AT (__ram_load_addr)
@ -294,6 +273,7 @@ SECTIONS
/*__end__ = .;*/
/*end = __end__;*/
KEEP(*(.psram_data*))
KEEP(*(.img_buf*))
. = ALIGN(4);
__psram_data_end__ = .;

20
bsp/board/bl616dk/board.c
View file

@ -58,14 +58,16 @@ static void peripheral_clock_init(void)
PERIPHERAL_CLOCK_I2S_ENABLE();
PERIPHERAL_CLOCK_USB_ENABLE();
PERIPHERAL_CLOCK_CAN_ENABLE();
PERIPHERAL_CLOCK_AUDIO_ENABLE();
GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_XCLK, 0);
GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_MCU_MUXPLL_160M, 0);
GLB_Set_DBI_CLK(ENABLE, GLB_SPI_CLK_MCU_MUXPLL_160M, 0);
GLB_Set_I2C_CLK(ENABLE, GLB_I2C_CLK_XCLK, 0);
GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1);
GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_XCLK);
GLB_Set_DIG_512K_CLK(ENABLE, ENABLE, 0x4E);
GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_DIFF_END);
GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_SINGLE_END);
GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, 19);
GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_WIFIPLL_96M, 3);
@ -263,7 +265,7 @@ void board_i2c0_gpio_init()
/* I2C0_SDA */
bflb_gpio_init(gpio, GPIO_PIN_11, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
/* I2C0_SCL */
bflb_gpio_init(gpio, GPIO_PIN_16, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_init(gpio, GPIO_PIN_14, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
}
void board_spi0_gpio_init()
@ -303,6 +305,20 @@ void board_adc_gpio_init()
gpio = bflb_device_get_by_name("gpio");
/* ADC_CH0 */
bflb_gpio_init(gpio, GPIO_PIN_20, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
/* ADC_CH1 */
bflb_gpio_init(gpio, GPIO_PIN_19, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
/* ADC_CH2 */
bflb_gpio_init(gpio, GPIO_PIN_2, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
/* ADC_CH3 */
bflb_gpio_init(gpio, GPIO_PIN_3, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
/* ADC_CH4 */
bflb_gpio_init(gpio, GPIO_PIN_14, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
/* ADC_CH5 */
bflb_gpio_init(gpio, GPIO_PIN_13, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
/* ADC_CH6 */
bflb_gpio_init(gpio, GPIO_PIN_12, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
/* ADC_CH7 */
bflb_gpio_init(gpio, GPIO_PIN_10, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
/* ADC_CH8 */
bflb_gpio_init(gpio, GPIO_PIN_1, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
/* ADC_CH9 */

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bsp/board/bl616dk/builtin_imgs/boot2_bl616_debug_v8.0.7.bin Normal file
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bsp/board/bl616dk/builtin_imgs/boot2_bl616_release_v8.0.7.bin Normal file
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bsp/board/bl616dk/builtin_imgs/mfg_bl616_gu_af8b0946f_autoboot_v2.26.bin Normal file
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bsp/board/bl616dk/builtin_imgs/mfg_bl616_gu_af8b0946f_v2.26.bin Normal file
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352
bsp/board/bl616dk/config/bl_factory_params_IoTKitA_auto.dts Normal file
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@ -0,0 +1,352 @@
/dts-v1/;
/include/ "bl602_base.dtsi";
// version: 17
// last_comp_version: 16
// boot_cpuid_phys: 0x0
/ {
model = "bl bl602 IOT board";
compatible = "bl,bl602-sample", "bl,bl602-common";
#address-cells = <0x1>;
#size-cells = <0x1>;
gpio {
#address-cells = <1>;
#size-cells = <1>;
max_num = <40>;
gpio0 {
status = "okay";
pin = <5>;
feature = "led";
active = "Hi"; //Hi or Lo
mode = "blink"; //blink or hearbeat
time = <100>; //duration for this mode
};
gpio1 {
status = "disable";
pin = <6>;
feature = "led";
active = "Hi"; //Hi or Lo
mode = "blink"; //blink or hearbeat
time = <100>; //duration for this mode
};
gpio2 {
status = "okay";
pin = <2>;
feature = "button";
active = "Hi";
mode = "multipress";
button {
debounce = <10>;
short_press_ms {
start = <100>;
end = <3000>;
kevent = <2>;
};
long_press_ms {
start = <6000>;
end = <10000>;
kevent = <3>;
};
longlong_press_ms {
start = <15000>;
kevent = <4>;
};
trig_level = "Hi";
};
hbn_use = "disable";
};
};
i2s {
#address-cells = <1>;
#size-cells = <1>;
i2s@40017000 {
status = "okay";
compatible = "bl602_i2s";
reg = <0x40017000 0x100>;
mclk_only = "okay";
pin {
mclk = <11>;
};
};
i2s@40017100 {
status = "okay";
compatible = "bl602_i2s";
reg = <0x40017100 0x100>;
mclk_only = "disable";
pin {
bclk = <12>;
fs = <29>;
do = <30>;
di = <31>;
};
};
};
i2c {
#address-cells = <1>;
#size-cells = <1>;
i2c@40011000 {
status = "okay";
compatible = "bl602_i2c";
reg = <0x40011000 0x100>;
pin {
scl = <32>;
sda = <13>;
};
devices {
list_addr = <0x18 0x21>;
list_driver = "i2c_es8311", "i2c_gc0308>";
};
};
i2c@40011100 {
status = "disable";
compatible = "bl602_i2c";
reg = <0x40011100 0x100>;
pin {
/*empty here*/
};
};
};
timer {
#address-cells = <1>;
#size-cells = <1>;
timer@40014000 {
status = "disable";
compatible = "bl602_timer";
reg = <0x40014000 0x100>;
};
timer@40014100 {
status = "disable";
compatible = "bl602_timer";
reg = <0x40014100 0x100>;
};
};
pwm {
#address-cells = <1>;
#size-cells = <1>;
pwm@4000A420 {
status = "okay";
compatible = "bl602_pwm";
reg = <0x4000A420 0x20>;
path = "/dev/pwm0";
id = <0>;
pin = <0>;
freq = <800000>;
duty = <50>;
};
pwm@4000A440 {
status = "disable";
reg = <0x4000A440 0x20>;
path = "/dev/pwm1";
id = <1>;
pin = <1>;
freq = <5000>;
duty = <50>;
};
pwm@4000A460 {
status = "disable";
reg = <0x4000A460 0x20>;
path = "/dev/pwm2";
id = <2>;
pin = <2>;
freq = <5000>;
duty = <50>;
};
pwm@4000A480 {
status = "disable";
reg = <0x4000A480 0x20>;
path = "/dev/pwm3";
id = <3>;
pin = <3>;
freq = <5000>;
duty = <50>;
};
pwm@4000A4A0 {
status = "disable";
reg = <0x4000A4A0 0x20>;
path = "/dev/pwm4";
id = <4>;
pin = <4>;
freq = <5000>;
duty = <50>;
};
};
ir {
#address-cells = <1>;
#size-cells = <1>;
ctrltype = <0>;
tx {
status = "disable";
pin = <11>; // only support 11
mode = "NEC"; // NEC,ExtenedNEC,RC5,SWM
interval = <100>; // ms
active_mode = "Hi"; //Hi,Lo
};
rx {
status = "okay";
pin = <12>; // only support 12 13
mode = "NEC"; // NEC,ExtenedNEC,RC5,SWM
active_mode = "Hi"; //Hi,Lo
data_check = <2>; //bit 0:check cmd, bit 1:check addr
};
};
uart {
#address-cells = <1>;
#size-cells = <1>;
uart@4000A000 {
status = "okay";
id = <0>;
compatible = "bl602_uart";
path = "/dev/ttyS0";
baudrate = <2000000>;
pin {
rx = <7>;
tx = <16>;
};
buf_size {
rx_size = <512>;
tx_size = <512>;
};
feature {
tx = "okay";
rx = "okay";
cts = "disable";
rts = "disable";
};
};
uart@4000A100 {
status = "okay";
id = <1>;
compatible = "bl602_uart";
path = "/dev/ttyS1";
baudrate = <115200>;
pin {
rx = <3>;
tx = <4>;
};
buf_size {
rx_size = <512>;
tx_size = <512>;
};
feature {
tx = "okay";
rx = "okay";
cts = "disable";
rts = "disable";
};
};
};
spi {
#address-cells = <1>;
#size-cells = <1>;
spi@4000F000 {
status = "okay"; /* okay disable */
mode = "master";
reg = <0x4000F000 0x100>; /* 4KB */
path = "/dev/spi0";
port = <0>;
polar_phase = <1>; /* 0,1,2,3 */
freq = <6000000>;
pin {
clk = <3>;
cs = <2>;
mosi = <1>;
miso = <0>;
};
dma_cfg {
tx_dma_ch = <2>;
rx_dma_ch = <3>;
};
};
};
gpip {
#address-cells = <1>;
#size-cells = <1>;
adc_key {
status = "disable";
pin = <9>;
interrupt = <3>;
key_vol = <0 100 400 300 500>;
key_pcb = "SW1", "SW2", "SW3", "SW4","SW5";
key_event = "Usr1", "Usr2", "Start", "Up", "Down";
key_raw = <1 2 3 4 5>;
};
};
qspi {
#address-cells = <1>;
#size-cells = <1>;
qspi@4000A000 {
status = "disable";
reg = <0x4000A000 0x1000>;/* 4KB */
};
};
wifi {
#address-cells = <1>;
#size-cells = <1>;
region {
country_code = <86>;
};
mac {
mode = "MBF";
sta_mac_addr = [C8 43 57 82 73 40];
ap_mac_addr = [C8 43 57 82 73 02];
};
sta {
ssid = "yourssid";
pwd = "yourapssword";
auto_connect_enable = <0>;
};
ap {
ssid = "bl_test_005";
pwd = "12345678";
ap_channel = <11>;
auto_chan_detect = "disable";
};
brd_rf {
xtal_mode = "MF";
xtal = <36 36 0 60 60>;
pwr_mode = "bf";//B: only use power offset in EFUSE; b: use power offset in EFUSE with incremental mode; F: only use power offset in Flash; f: use power offset in Flash with incremental mode
pwr_table_11b = <20 20 20 20>;//1Mbps 2Mbps 5.5Mbps 11Mbps
pwr_table_11g = <18 18 18 18 18 18 16 16>; //6Mbps 9Mbps 12Mbps 18MBps 24Mbps 36Mbps 48Mbps 54Mbps
pwr_table_11n_ht20 = <18 18 18 18 18 16 15 15>; //MCS0~MCS7
pwr_table_11n_ht40 = <18 18 18 18 18 16 15 14>; //MCS0~MCS7
pwr_table_11ac_vht20 = <18 18 18 18 18 16 15 15 15 14>; //MSC0~MSC9
pwr_table_11ac_vht40 = <18 18 18 18 18 16 15 14 14 13>; //MSC0~MSC9
pwr_table_11ac_vht80 = <18 18 18 18 18 15 14 13 13 12>; //MSC0~MSC9
pwr_table_11ax_he20 = <18 18 18 18 18 16 15 15 15 14 13 13>; //MSC0~MSC11
pwr_table_11ax_he40 = <18 18 18 18 18 16 15 14 14 13 12 12>; //MSC0~MSC11
pwr_table_11ax_he80 = <18 18 18 18 18 15 14 13 13 12 11 11>; //MSC0~MSC11
pwr_table_11ax_he160 = <18 18 18 18 18 15 14 13 12 11 10 10>; //MSC0~MSC11
pwr_offset = <16 16 16 16 16 16 16 16 16 16 16 16 16 16>;//due to the limit of current DTC, negative value is used. So we work around by adding all the poweroffset with 16.
pwr_offset_lp = <16 16 16 16 16 16 16 16 16 16 16 16 16 16>;
//so 14 represents -0.5dBm; 16 represents 0dBm; 20 represents 1dBm;(step is 0.25dBm)
};
rf_temp {
en_tcal = <0>;
linear_or_follow = <1>;
Tchannels = <2412 2427 2442 2457 2472>;
Tchannel_os = <180 168 163 160 157>;
Tchannel_os_low = <199 186 170 165 160>;
Troom_os = <255>;
//negative value is NOT supported. So we use '256' for 0, '255' for -1, '257' for 1,'511' for 256
};
};
bluetooth_zigbee {
#address-cells = <1>;
#size-cells = <1>;
brd_rf {
pwr_table_ble = <13>; //range:0~15dbm
pwr_table_bt = <10 8 8>; //BR 1M,EDR 2M,EDR 3M
pwr_table_zigbee = <13>; //range:0~15dbm
pwr_offset = <16 16 16 16 16>; //step is 0.25dBm
};
};
info {
#address-cells = <1>;
#size-cells = <1>;
brd {
country_code = <86>;
};
};
};

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bsp/board/bl616dk/config/boot2_bl616_release_v8.0.7.bin Normal file
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bsp/board/bl616dk/config/mfg_bl616_gu_af8b0946f_v2.26.bin Normal file
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126
bsp/board/bl616dk/config/partition_cfg_4M.toml Normal file
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@ -0,0 +1,126 @@
[pt_table]
#partition table is 4K in size
address0 = 0xE000
address1 = 0xF000
# If version is 2, It will use dynamic mode.
version = 2
[[pt_entry]]
type = 16
name = "Boot2"
device = 0
address0 = 0
size0 = 0xE000
address1 = 0
size1 = 0
# compressed image must set len,normal image can left it to 0
len = 0
# If header is 1, it will add the header.
header = 1
# If header is 1 and security is 1, It will be encrypted.
security = 1
[[pt_entry]]
type = 0
name = "FW"
device = 0
address0 = 0x10000
size0 = 0x200000
address1 = 0x210000
size1 = 0x168000
# compressed image must set len,normal image can left it to 0
len = 0
# If header is 1, it will add the header.
header = 1
# If header is 1 and security is 1, It will be encrypted.
security= 1
[[pt_entry]]
type = 10
name = "mfg"
device = 0
address0 = 0x210000
size0 = 0x168000
address1 = 0
size1 = 0
# compressed image must set len,normal image can left it to 0
len = 0
# If header is 1, it will add the header.
header = 1
# If header is 1 and security is 1, It will be encrypted.
security= 1
[[pt_entry]]
type = 2
name = "media"
device = 0
address0 = 0x378000
size0 = 0x71000
address1 = 0
size1 = 0
# compressed image must set len,normal image can left it to 0
len = 0
# If header is 1, it will add the header.
header = 0
# If header is 1 and security is 1, It will be encrypted.
security= 0
[[pt_entry]]
type = 3
name = "PSM"
device = 0
address0 = 0x3E9000
size0 = 0x8000
address1 = 0
size1 = 0
# compressed image must set len,normal image can left it to 0
len = 0
# If header is 1, it will add the header.
header = 0
# If header is 1 and security is 1, It will be encrypted.
security= 0
[[pt_entry]]
type = 4
name = "KEY"
device = 0
address0 = 0x3F1000
size0 = 0x2000
address1 = 0
size1 = 0
# compressed image must set len,normal image can left it to 0
len = 0
# If header is 1, it will add the header.
header = 0
# If header is 1 and security is 1, It will be encrypted.
security= 0
[[pt_entry]]
type = 5
name = "DATA"
device = 0
address0 = 0x3F3000
size0 = 0x5000
address1 = 0
size1 = 0
# compressed image must set len,normal image can left it to 0
len = 0
# If header is 1, it will add the header.
header = 0
# If header is 1 and security is 1, It will be encrypted.
security = 0
[[pt_entry]]
type = 6
name = "factory"
device = 0
address0 = 0x3F8000
size0 = 0x8000
address1 = 0
size1 = 0
# compressed image must set len,normal image can left it to 0
len = 0
# If header is 1, it will add the header.
header = 0
# If header is 1 and security is 1, It will be encrypted.
security= 0

4
bsp/board/bl616dk/fw_header.c
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@ -130,7 +130,11 @@ __attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
.basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */
.basic_cfg.rsvd_3 = 0x0, /* [31] rsvd_3 */
#ifdef BFLB_BOOT2
.basic_cfg.group_image_offset = 0x00002000, /* flash controller offset */
#else
.basic_cfg.group_image_offset = 0x00001000, /* flash controller offset */
#endif
.basic_cfg.aes_region_len = 0x00000000, /* aes region length */
.basic_cfg.img_len_cnt = 0x00010000, /* image length or segment count */

3
bsp/board/bl616dk/fw_header.h
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@ -194,4 +194,7 @@ struct __attribute__((packed, aligned(4))) bootheader_t {
uint32_t crc32; /* 4 */
};
#define BFLB_FW_LENGTH_OFFSET 132
#define BFLB_FW_HASH_OFFSET 136
#endif

4
bsp/board/bl702dk/CMakeLists.txt
View file

@ -1,7 +1,7 @@
sdk_add_include_directories(.)
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/board.c)
# target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/fw_header.c)
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/fw_header.c)
sdk_set_linker_script(bl702_flash.ld)
@ -9,4 +9,4 @@ if(CONFIG_PSRAM)
sdk_add_compile_definitions(-DCONFIG_PSRAM)
endif()
# sdk_add_link_options(-ufw_header)
sdk_add_link_options(-ufw_header)

19
bsp/board/bl702dk/bl702_flash.ld
View file

@ -157,21 +157,7 @@ SECTIONS
ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
/*************************************************************************/
__system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
.system_ram_data_region : AT (__system_ram_load_addr)
{
. = ALIGN(4);
__system_ram_data_start__ = .;
*(.system_ram)
*(.nocache_ram)
. = ALIGN(4);
__system_ram_data_end__ = .;
} > ram_memory
__ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
__ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
/* Data section */
RAM_DATA : AT (__ram_load_addr)
@ -188,6 +174,8 @@ SECTIONS
*(.sdata2)
*(.sdata2.*)
*(.nocache_ram)
. = ALIGN(4);
__bflog_tags_start__ = .;
*(.bflog_tags_array)
@ -215,6 +203,7 @@ SECTIONS
__noinit_data_start__ = .;
*(.noinit_data*)
*(.nocache_noinit_ram)
. = ALIGN(4);
__noinit_data_end__ = .;

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bsp/board/bl702dk/builtin_imgs/boot2_bl702_debug_v8.0.7.bin Normal file
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bsp/board/bl702dk/builtin_imgs/boot2_bl702_release_v8.0.7.bin Normal file
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bsp/board/bl702dk/builtin_imgs/mfg_bl702_stdfw.bin Normal file
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0
bsp/board/bl702dk/config/.gitkeep Normal file
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4
bsp/board/bl702dk/fw_header.c
View file

@ -113,7 +113,11 @@ __attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
.img_segment_info.img_len = 0x00010000, /* image length or segment count */
.rsvd0 = 0x00000000,
#ifdef BFLB_BOOT2
.img_start.flashoffset = 0x00002000, /* flash controller offset */
#else
.img_start.flashoffset = 0x00001000, /* flash controller offset */
#endif
.hash = { 0xdeadbeef }, /* hash of the image */
.boot2_pt_table_0 = 0x1000, /* address of partition table 0 */

3
bsp/board/bl702dk/fw_header.h
View file

@ -164,4 +164,7 @@ struct __attribute__((packed, aligned(4))) bootheader_t {
uint32_t crc32;
};
#define BFLB_FW_LENGTH_OFFSET 120
#define BFLB_FW_HASH_OFFSET 132
#endif

13
bsp/board/bl808dk/CMakeLists.txt
View file

@ -2,16 +2,9 @@ sdk_add_include_directories(.)
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/board.c)
if(CONFIG_IOT)
# target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/iot/fw_header.c)
sdk_set_linker_script(iot/bl808_flash_${CPU_ID}.ld)
# sdk_add_link_options(-ufw_header)
else()
# target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/mcu/fw_header.c)
sdk_set_linker_script(mcu/bl808_flash_${CPU_ID}.ld)
# sdk_add_link_options(-ufw_header0)
# sdk_add_link_options(-ufw_header1)
endif()
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/fw_header.c)
sdk_set_linker_script(bl808_flash_${CPU_ID}.ld)
sdk_add_link_options(-ufw_header)
if(CONFIG_PSRAM)
sdk_add_compile_definitions(-DCONFIG_PSRAM)

23
bsp/board/bl808dk/iot/bl808_flash_d0.ld → bsp/board/bl808dk/bl808_flash_d0.ld
View file

@ -162,28 +162,7 @@ SECTIONS
__nocache_ram_data_end__ = .;
} > nocache_ram_memory
__system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
.system_ram_data_region : AT (__system_ram_load_addr)
{
. = ALIGN(4);
__system_ram_data_start__ = .;
*(.system_ram)
. = ALIGN(4);
__system_ram_data_end__ = .;
} > ram_memory
.system_ram_noinit_data_region (NOLOAD) :
{
. = ALIGN(4);
*(.system_ram_noinit)
. = ALIGN(4);
} > ram_memory
__ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
__ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
/* Data section */
RAM_DATA : AT (__ram_load_addr)

41
bsp/board/bl808dk/mcu/bl808_flash_m0.ld → bsp/board/bl808dk/bl808_flash_lp.ld
View file

@ -22,13 +22,12 @@ HeapMinSize = 0x1000; /* 4KB */
MEMORY
{
fw_header_memory0 (rx) : ORIGIN = 0x58000000 - 0x2000, LENGTH = 4K
fw_header_memory1 (rx) : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K
xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 32M
itcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 20K
dtcm_memory (rx) : ORIGIN = 0x62025000, LENGTH = 4K
nocache_ram_memory (!rx) : ORIGIN = 0x22026000, LENGTH = 40K
ram_memory (!rx) : ORIGIN = 0x62030000, LENGTH = 160K + 64K - 20K - 4K - 40K
fw_header_memory0 (rx) : ORIGIN = 0x58020000 - 0x1000, LENGTH = 4K
xip_memory (rx) : ORIGIN = 0x58020000, LENGTH = 1M
itcm_memory (rx) : ORIGIN = 0x2202C000, LENGTH = 16K
dtcm_memory (rx) : ORIGIN = 0x22030000, LENGTH = 16K
nocache_ram_memory (!rx) : ORIGIN = 0x22030000, LENGTH = 0K
ram_memory (!rx) : ORIGIN = 0x22034000, LENGTH = 16K
xram_memory (!rx) : ORIGIN = 0x40000000, LENGTH = 16K
}
@ -39,11 +38,6 @@ SECTIONS
KEEP(*(.fw_header0))
} > fw_header_memory0
.fw_header1 :
{
KEEP(*(.fw_header1))
} > fw_header_memory1
.text :
{
. = ALIGN(4);
@ -176,28 +170,7 @@ SECTIONS
__nocache_ram_data_end__ = .;
} > nocache_ram_memory
__system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
.system_ram_data_region : AT (__system_ram_load_addr)
{
. = ALIGN(4);
__system_ram_data_start__ = .;
*(.system_ram)
. = ALIGN(4);
__system_ram_data_end__ = .;
} > ram_memory
.system_ram_noinit_data_region (NOLOAD) :
{
. = ALIGN(4);
*(.system_ram_noinit)
. = ALIGN(4);
} > ram_memory
__ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
__ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
/* Data section */
RAM_DATA : AT (__ram_load_addr)

23
bsp/board/bl808dk/iot/bl808_flash_m0.ld → bsp/board/bl808dk/bl808_flash_m0.ld
View file

@ -168,28 +168,7 @@ SECTIONS
__nocache_ram_data_end__ = .;
} > nocache_ram_memory
__system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
.system_ram_data_region : AT (__system_ram_load_addr)
{
. = ALIGN(4);
__system_ram_data_start__ = .;
*(.system_ram)
. = ALIGN(4);
__system_ram_data_end__ = .;
} > ram_memory
.system_ram_noinit_data_region (NOLOAD) :
{
. = ALIGN(4);
*(.system_ram_noinit)
. = ALIGN(4);
} > ram_memory
__ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
__ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
/* Data section */
RAM_DATA : AT (__ram_load_addr)

37
bsp/board/bl808dk/board.c
View file

@ -202,6 +202,9 @@ static void console_init()
/* sipeed m1s dock */
bflb_gpio_init(gpio, GPIO_PIN_16, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_init(gpio, GPIO_PIN_17, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
#elif defined(CPU_LP)
bflb_gpio_uart_init(gpio, GPIO_PIN_16, GPIO_UART_FUNC_UART1_TX);
bflb_gpio_uart_init(gpio, GPIO_PIN_17, GPIO_UART_FUNC_UART1_RX);
#endif
struct bflb_uart_config_s cfg;
cfg.baudrate = 2000000;
@ -215,6 +218,8 @@ static void console_init()
uart0 = bflb_device_get_by_name("uart0");
#elif defined(CPU_D0)
uart0 = bflb_device_get_by_name("uart3");
#elif defined(CPU_LP)
uart0 = bflb_device_get_by_name("uart1");
#endif
bflb_uart_init(uart0, &cfg);
bflb_uart_set_console(uart0);
@ -229,6 +234,7 @@ void board_init(void)
flag = bflb_irq_save();
GLB_Halt_CPU(GLB_CORE_ID_D0);
GLB_Halt_CPU(GLB_CORE_ID_LP);
ret = bflb_flash_init();
@ -265,16 +271,16 @@ void board_init(void)
}
#endif
/* set CPU D0 boot XIP address and flash address */
// Tzc_Sec_Set_CPU_Group(GLB_CORE_ID_D0, 1);
// /* D0 boot from 0x58000000 */
// GLB_Set_CPU_Reset_Address(GLB_CORE_ID_D0, 0x58000000);
// /* D0 image offset on flash is 0x100000+0x1000(header) */
// bflb_sf_ctrl_set_flash_image_offset(0x101000, 1, SF_CTRL_FLASH_BANK0);
Tzc_Sec_Set_CPU_Group(GLB_CORE_ID_D0, 1);
/* D0 boot from 0x58000000 */
GLB_Set_CPU_Reset_Address(GLB_CORE_ID_D0, 0x58000000);
/* D0 image offset on flash is CONFIG_D0_FLASH_ADDR+0x1000(header) */
bflb_sf_ctrl_set_flash_image_offset(CONFIG_D0_FLASH_ADDR + 0x1000, 1, SF_CTRL_FLASH_BANK0);
bflb_irq_restore(flag);
/* we do not check header at 0x100000, just boot */
GLB_Release_CPU(GLB_CORE_ID_D0);
GLB_Release_CPU(GLB_CORE_ID_LP);
/* release d0 and then do can run */
BL_WR_WORD(IPC_SYNC_ADDR1, IPC_SYNC_FLAG);
@ -303,6 +309,25 @@ void board_init(void)
log_start();
}
#elif defined(CPU_LP)
void board_init(void)
{
CPU_Set_MTimer_CLK(ENABLE, CPU_Get_MTimer_Source_Clock() / 1000 / 1000 - 1);
bflb_irq_initialize();
console_init();
bl_show_log();
printf("lp does not use memheap due to little ram \r\n");
printf("sig1:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG1));
printf("sig2:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG2));
printf("cgen1:%08x\r\n", getreg32(BFLB_GLB_CGEN1_BASE));
log_start();
}
#endif
void board_uartx_gpio_init(void)

3
bsp/board/bl808dk/board.h
View file

@ -23,4 +23,7 @@ void board_iso11898_gpio_init(void);
#define DEFAULT_TEST_UART_DMA_TDR DMA_ADDR_UART1_TDR
#define DEFAULT_TEST_UART_DMA_RDR DMA_ADDR_UART1_RDR
#define CONFIG_D0_FLASH_ADDR 0x100000
#define CONFIG_LP_FLASH_ADDR 0x200000
#endif

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bsp/board/bl808dk/builtin_imgs/boot2_bl808_debug_v8.0.7.bin Normal file
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bsp/board/bl808dk/builtin_imgs/boot2_bl808_release_v8.0.7.bin Normal file
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bsp/board/bl808dk/builtin_imgs/mfg_bl808_gu_7c2526e09_autoboot_v0.56.bin Normal file
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bsp/board/bl808dk/builtin_imgs/mfg_bl808_gu_7c2526e09_v0.56.bin Normal file
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0
bsp/board/bl808dk/config/.gitkeep Normal file
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23
bsp/board/bl808dk/iot/fw_header.c → bsp/board/bl808dk/fw_header.c
View file

@ -145,7 +145,11 @@ __attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
.basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */
.basic_cfg.rsvd_3 = 0x0, /* [31] rsvd_3 */
#ifdef BFLB_BOOT2
.basic_cfg.group_image_offset = 0x00002000, /* flash controller offset */
#else
.basic_cfg.group_image_offset = 0x00001000, /* flash controller offset */
#endif
.basic_cfg.aes_region_len = 0x00000000, /* aes region length */
.basic_cfg.img_len_cnt = 0x00010000, /* image length or segment count */
@ -169,13 +173,13 @@ __attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
.cpu_cfg[0].msp_val = 0x00000000, /* msp value */
/* cpu cfg */
.cpu_cfg[1].config_enable = 0x01, /* coinfig this cpu */
.cpu_cfg[1].halt_cpu = 0x0, /* halt this cpu */
.cpu_cfg[1].cache_enable = 0x0, /* cache setting :only for BL Cache */
.cpu_cfg[1].cache_wa = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_wb = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_wt = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].config_enable = 0x0, /* coinfig this cpu */
.cpu_cfg[1].halt_cpu = 0x0, /* halt this cpu */
.cpu_cfg[1].cache_enable = 0x0, /* cache setting :only for BL Cache */
.cpu_cfg[1].cache_wa = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_wb = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_wt = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].rsvd = 0x0,
.cpu_cfg[1].cache_range_h = 0x00000000,
@ -195,5 +199,10 @@ __attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
/* flashcfg table list len */ /* 4 */
.flash_cfg_table_len = 0x00000000,
.rsvd1[0] = 0x20000320,
.rsvd1[1] = 0x00000000,
.rsvd1[2] = 0x2000F038,
.rsvd1[3] = 0x18000000,
.crc32 = 0xdeadbeef /* 4 */
};

9
bsp/board/bl808dk/mcu/fw_header.h → bsp/board/bl808dk/fw_header.h
View file

@ -199,12 +199,15 @@ struct __attribute__((packed, aligned(4))) bootheader_t {
uint32_t flash_cfg_table_addr; /* address of flashcfg table list */ /* 4 */
uint32_t flash_cfg_table_len; /* flashcfg table list len */ /* 4 */
uint32_t rsvd0[6]; /* rsvd */
uint32_t rsvd1[6]; /* rsvd */
uint32_t rsvd0[8]; /* rsvd */
uint32_t rsvd1[8]; /* rsvd */
uint32_t rsvd3[5]; /* 4 */
uint32_t rsvd3[5]; /* 20 */
uint32_t crc32; /* 4 */
};
#define BFLB_FW_LENGTH_OFFSET 140
#define BFLB_FW_HASH_OFFSET 144
#endif

210
bsp/board/bl808dk/iot/fw_header.h
View file

@ -1,210 +0,0 @@
#ifndef __FW_HEADER_H__
#define __FW_HEADER_H__
#include "stdint.h"
#include "stdio.h"
struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
uint8_t resetEnCmd; /*!< Flash enable reset command */
uint8_t resetCmd; /*!< Flash reset command */
uint8_t resetCreadCmd; /*!< Flash reset continuous read command */
uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */
uint8_t jedecIdCmd; /*!< JEDEC ID command */
uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */
uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */
uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */
uint8_t sectorSize; /*!< *1024bytes */
uint8_t mid; /*!< Manufacturer ID */
uint16_t pageSize; /*!< Page size */
uint8_t chipEraseCmd; /*!< Chip erase cmd */
uint8_t sectorEraseCmd; /*!< Sector erase command */
uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */
uint8_t blk64EraseCmd; /*!< Block 64K erase command */
uint8_t writeEnableCmd; /*!< Need before every erase or program */
uint8_t pageProgramCmd; /*!< Page program cmd */
uint8_t qpageProgramCmd; /*!< QIO page program cmd */
uint8_t qppAddrMode; /*!< QIO page program address mode */
uint8_t fastReadCmd; /*!< Fast read command */
uint8_t frDmyClk; /*!< Fast read command dummy clock */
uint8_t qpiFastReadCmd; /*!< QPI fast read command */
uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */
uint8_t fastReadDoCmd; /*!< Fast read dual output command */
uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */
uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */
uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */
uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */
uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */
uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */
uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */
uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */
uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */
uint8_t qpiPageProgramCmd; /*!< QPI program command */
uint8_t writeVregEnableCmd; /*!< Enable write reg */
uint8_t wrEnableIndex; /*!< Write enable register index */
uint8_t qeIndex; /*!< Quad mode enable register index */
uint8_t busyIndex; /*!< Busy status register index */
uint8_t wrEnableBit; /*!< Write enable bit pos */
uint8_t qeBit; /*!< Quad enable bit pos */
uint8_t busyBit; /*!< Busy status bit pos */
uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */
uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */
uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */
uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */
uint8_t releasePowerDown; /*!< Release power down command */
uint8_t busyReadRegLen; /*!< Register length of contain busy status */
uint8_t readRegCmd[4]; /*!< Read register command buffer */
uint8_t writeRegCmd[4]; /*!< Write register command buffer */
uint8_t enterQpi; /*!< Enter qpi command */
uint8_t exitQpi; /*!< Exit qpi command */
uint8_t cReadMode; /*!< Config data for continuous read mode */
uint8_t cRExit; /*!< Config data for exit continuous read mode */
uint8_t burstWrapCmd; /*!< Enable burst wrap command */
uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */
uint8_t burstWrapDataMode; /*!< Data and address mode for this command */
uint8_t burstWrapData; /*!< Data to enable burst wrap */
uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */
uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */
uint8_t deBurstWrapData; /*!< Data to disable burst wrap */
uint16_t timeEsector; /*!< 4K erase time */
uint16_t timeE32k; /*!< 32K erase time */
uint16_t timeE64k; /*!< 64K erase time */
uint16_t timePagePgm; /*!< Page program time */
uint16_t timeCe; /*!< Chip erase time in ms */
uint8_t pdDelay; /*!< Release power down command delay time for wake up */
uint8_t qeData; /*!< QE set data */
};
struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
uint32_t magiccode;
struct spi_flash_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
uint8_t xtal_type;
uint8_t mcu_clk;
uint8_t mcu_clk_div;
uint8_t mcu_bclk_div;
uint8_t mcu_pbclk_div;
uint8_t lp_div;
uint8_t dsp_clk;
uint8_t dsp_clk_div;
uint8_t dsp_bclk_div;
uint8_t dsp_pbclk;
uint8_t dsp_pbclk_div;
uint8_t emi_clk;
uint8_t emi_clk_div;
uint8_t flash_clk_type;
uint8_t flash_clk_div;
uint8_t wifipll_pu;
uint8_t aupll_pu;
uint8_t cpupll_pu;
uint8_t mipipll_pu;
uint8_t uhspll_pu;
};
struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
uint32_t magiccode;
struct sys_clk_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) boot_basic_cfg_t {
uint32_t sign_type : 2; /* [1: 0] for sign */
uint32_t encrypt_type : 2; /* [3: 2] for encrypt */
uint32_t key_sel : 2; /* [5: 4] key slot */
uint32_t xts_mode : 1; /* [6] for xts mode */
uint32_t aes_region_lock : 1; /* [7] rsvd */
uint32_t no_segment : 1; /* [8] no segment info */
uint32_t rsvd_0 : 1; /* [9] boot2 enable(rsvd_0) */
uint32_t rsvd_1 : 1; /* [10] boot2 rollback(rsvd_1) */
uint32_t cpu_master_id : 4; /* [14: 11] master id */
uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */
uint32_t crc_ignore : 1; /* [16] ignore crc */
uint32_t hash_ignore : 1; /* [17] hash ignore */
uint32_t power_on_mm : 1; /* [18] power on mm */
uint32_t em_sel : 3; /* [21: 19] em_sel */
uint32_t cmds_en : 1; /* [22] command spliter enable */
uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */
uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */
uint32_t icache_invalid : 1; /* [29] icache invalid */
uint32_t dcache_invalid : 1; /* [30] dcache invalid */
uint32_t rsvd_3 : 1; /* [31] rsvd_3 */
uint32_t group_image_offset; /* flash controller offset */
uint32_t aes_region_len; /* aes region length */
uint32_t img_len_cnt; /* image length or segment count */
uint32_t hash[32 / 4]; /* hash of the image */
};
struct __attribute__((packed, aligned(4))) boot_cpu_cfg_t {
uint8_t config_enable; /* coinfig this cpu */
uint8_t halt_cpu; /* halt this cpu */
uint8_t cache_enable : 1; /* cache setting */
uint8_t cache_wa : 1; /* cache setting */
uint8_t cache_wb : 1; /* cache setting */
uint8_t cache_wt : 1; /* cache setting */
uint8_t cache_way_dis : 4; /* cache setting */
uint8_t rsvd;
uint32_t cache_range_h; /* cache range high */
uint32_t cache_range_l; /* cache range low */
uint32_t image_address_offset; /* image_address_offset */
uint32_t rsvd0; /* rsvd0 */
uint32_t msp_val; /* msp value */
};
struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
uint8_t aesiv[16];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) pkey_cfg_t {
uint8_t eckeyx[32]; /* ec key in boot header */
uint8_t eckeyy[32]; /* ec key in boot header */
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sign_cfg_t {
uint32_t sig_len;
uint8_t signature[32];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) bootheader_t {
uint32_t magiccode; /* 4 */
uint32_t rivison; /* 4 */
struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */
struct boot_clk_cfg_t clk_cfg; /* 4 + 20 + 4 */
struct boot_basic_cfg_t basic_cfg; /* 4 + 4 + 4 + 4 + 4*8 */
struct boot_cpu_cfg_t cpu_cfg[3]; /*24*3 */
uint32_t boot2_pt_table_0_rsvd; /* address of partition table 0 */ /* 4 */
uint32_t boot2_pt_table_1_rsvd; /* address of partition table 1 */ /* 4 */
uint32_t flash_cfg_table_addr; /* address of flashcfg table list */ /* 4 */
uint32_t flash_cfg_table_len; /* flashcfg table list len */ /* 4 */
uint32_t rsvd0[6]; /* rsvd */
uint32_t rsvd1[6]; /* rsvd */
uint32_t rsvd3[5]; /* 4 */
uint32_t crc32; /* 4 */
};
#endif

265
bsp/board/bl808dk/mcu/bl808_flash_d0.ld
View file

@ -1,265 +0,0 @@
/****************************************************************************************
* @file flash.ld
*
* @brief This file is the link script file (gnuarm or armgcc).
*
* Copyright (C) BouffaloLab 2021
*
****************************************************************************************
*/
/* configure the CPU type */
OUTPUT_ARCH( "riscv" )
/* link with the standard c library */
INPUT(-lc)
/* link with the standard GCC library */
INPUT(-lgcc)
/* configure the entry point */
ENTRY(__start)
StackSize = 0x0400; /* 1KB */
HeapMinSize = 0x1000; /* 4KB */
MEMORY
{
fw_header_memory (rx) : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K
xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 32M
itcm_memory (rx) : ORIGIN = 0x3eff0000, LENGTH = 28K
dtcm_memory (rx) : ORIGIN = 0x3eff7000, LENGTH = 4K
nocache_ram_memory (!rx) : ORIGIN = 0x3eff8000, LENGTH = 0K
ram_memory (!rx) : ORIGIN = 0x3eff8000, LENGTH = 32K + 32K
xram_memory (!rx) : ORIGIN = 0x40004000, LENGTH = 16K
}
SECTIONS
{
.fw_header :
{
KEEP(*(.fw_header0))
} > fw_header_memory
.text :
{
. = ALIGN(4);
__text_code_start__ = .;
KEEP (*(SORT_NONE(.init)))
*(.text)
*(.text.*)
/* section information for shell */
. = ALIGN(8);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
/*put .rodata**/
*(EXCLUDE_FILE( *bl808_glb*.o* \
*bl808_glb_gpio*.o* \
*bl808_pds*.o* \
*bl808_aon*.o* \
*bl808_hbn*.o* \
*bl808_l1c*.o* \
*bl808_common*.o* \
*bl808_clock*.o* \
*bl808_ef_ctrl*.o* \
*bl808_sf_cfg*.o* \
*bl808_sf_ctrl*.o* \
*bl808_sflash*.o* \
*bl808_xip_sflash*.o* \
*bl808_romapi_patch*.o* ) .rodata*)
*(.srodata)
*(.srodata.*)
. = ALIGN(4);
__text_code_end__ = .;
} > xip_memory
. = ALIGN(4);
__itcm_load_addr = .;
.itcm_region : AT (__itcm_load_addr)
{
. = ALIGN(4);
__tcm_code_start__ = .;
*(.tcm_code.*)
*(.tcm_const.*)
*(.sclock_rlt_code.*)
*(.sclock_rlt_const.*)
*bl808_glb*.o*(.rodata*)
*bl808_glb_gpio*.o*(.rodata*)
*bl808_pds*.o*(.rodata*)
*bl808_aon*.o*(.rodata*)
*bl808_hbn*.o*(.rodata*)
*bl808_l1c*.o*(.rodata*)
*bl808_common*.o*(.rodata*)
*bl808_clock*.o*(.rodata*)
*bl808_ef_ctrl*.o*(.rodata*)
*bl808_sf_cfg*.o*(.rodata*)
*bl808_sf_ctrl*.o*(.rodata*)
*bl808_sflash*.o*(.rodata*)
*bl808_xip_sflash*.o*(.rodata*)
*bl808_romapi_patch*.o*(.rodata*)
. = ALIGN(4);
__tcm_code_end__ = .;
} > itcm_memory
__dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
.dtcm_region : AT (__dtcm_load_addr)
{
. = ALIGN(4);
__tcm_data_start__ = .;
*(.tcm_data)
/* *finger_print.o(.data*) */
. = ALIGN(4);
__tcm_data_end__ = .;
} > dtcm_memory
/*************************************************************************/
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
. = ALIGN(0x4);
. = . + StackSize;
. = ALIGN(0x4);
} > dtcm_memory
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
PROVIDE( __freertos_irq_stack_top = __StackTop);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
/*************************************************************************/
__nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
.nocache_ram_region (NOLOAD) : AT (__nocache_ram_load_addr)
{
. = ALIGN(4);
__nocache_ram_data_start__ = .;
*(.nocache_ram)
. = ALIGN(4);
__nocache_ram_data_end__ = .;
} > nocache_ram_memory
__system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
.system_ram_data_region : AT (__system_ram_load_addr)
{
. = ALIGN(4);
__system_ram_data_start__ = .;
*(.system_ram)
. = ALIGN(4);
__system_ram_data_end__ = .;
} > ram_memory
.system_ram_noinit_data_region (NOLOAD) :
{
. = ALIGN(4);
*(.system_ram_noinit)
. = ALIGN(4);
} > ram_memory
__ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
/* Data section */
RAM_DATA : AT (__ram_load_addr)
{
. = ALIGN(4);
__ram_data_start__ = .;
PROVIDE( __global_pointer$ = . + 0x800 );
*(.data)
*(.data.*)
*(.sdata)
*(.sdata.*)
*(.sdata2)
*(.sdata2.*)
. = ALIGN(4);
__bflog_tags_start__ = .;
*(.bflog_tags_array)
. = ALIGN(4);
__bflog_tags_end__ = .;
__ram_data_end__ = .;
} > ram_memory
__etext_final = (__ram_load_addr + SIZEOF (RAM_DATA));
ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow")
.bss (NOLOAD) :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram_memory
.noinit_data (NOLOAD) :
{
. = ALIGN(4);
__noinit_data_start__ = .;
*(.noinit_data*)
. = ALIGN(4);
__noinit_data_end__ = .;
} > ram_memory
.nocache_noinit_ram_region (NOLOAD) :
{
. = ALIGN(4);
__nocache_ram_data_start__ = .;
*(.nocache_noinit_ram)
. = ALIGN(4);
__nocache_ram_data_end__ = .;
} > nocache_ram_memory
.heap (NOLOAD):
{
. = ALIGN(4);
__HeapBase = .;
/*__end__ = .;*/
/*end = __end__;*/
KEEP(*(.heap*))
. = ALIGN(4);
__HeapLimit = .;
} > ram_memory
__HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow")
}

403
bsp/board/bl808dk/mcu/fw_header.c
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@ -1,403 +0,0 @@
#include "fw_header.h"
__attribute__((section(".fw_header0"))) struct bootheader_t fw_header0 = {
.magiccode = 0x504e4642,
.rivison = 0x00000001,
/*flash config */
.flash_cfg.magiccode = 0x47464346,
.flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
.flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
.flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
.flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
.flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */
.flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */
.flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */
.flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */
.flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */
.flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */
.flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */
.flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */
.flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */
.flash_cfg.cfg.mid = 0x00, /*!< Manufacturer ID */
.flash_cfg.cfg.pageSize = 0x100, /*!< Page size */
.flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */
.flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */
.flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */
.flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */
.flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */
.flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */
.flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */
.flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */
.flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */
.flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */
.flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */
.flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */
.flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */
.flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */
.flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */
.flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */
.flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */
.flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */
.flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */
.flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */
.flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */
.flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */
.flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */
.flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */
.flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */
.flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */
.flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */
.flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */
.flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */
.flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */
.flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */
.flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */
.flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */
.flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */
.flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */
.flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */
.flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */
.flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */
.flash_cfg.cfg.cReadMode = 0x20, /*!< Config data for continuous read mode */
.flash_cfg.cfg.cRExit = 0xf0, /*!< Config data for exit continuous read mode */
.flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */
.flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */
.flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */
.flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */
.flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
.flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */
.flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */
.flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */
.flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */
.flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */
.flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */
.flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */
.flash_cfg.cfg.qeData = 0, /*!< QE set data */
.flash_cfg.crc32 = 0xdeadbeef,
/* clock cfg */
.clk_cfg.magiccode = 0x47464350,
.clk_cfg.cfg.xtal_type = 0x07, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */
.clk_cfg.cfg.mcu_clk = 0x04, /*!< mcu_clk 0:RC32M,1:Xtal,2:cpupll 400M,3:wifipll 192M,4:wifipll 320M */
.clk_cfg.cfg.mcu_clk_div = 0x00,
.clk_cfg.cfg.mcu_bclk_div = 0x00,
.clk_cfg.cfg.mcu_pbclk_div = 0x03,
.clk_cfg.cfg.lp_div = 0x01,
.clk_cfg.cfg.dsp_clk = 0x03, /* 0:RC32M,1:Xtal,2:wifipll 240M,3:wifipll 320M,4:cpupll 400M */
.clk_cfg.cfg.dsp_clk_div = 0x00,
.clk_cfg.cfg.dsp_bclk_div = 0x01,
.clk_cfg.cfg.dsp_pbclk = 0x02, /* 0:RC32M,1:Xtal,2:wifipll 160M,3:cpupll 160M,4:wifipll 240M */
.clk_cfg.cfg.dsp_pbclk_div = 0x00,
.clk_cfg.cfg.emi_clk = 0x02, /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */
.clk_cfg.cfg.emi_clk_div = 0x01,
.clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll 120M,1:xtal,2:cpupll 100M,3:wifipll 80M,4:bclk,5:wifipll 96M */
.clk_cfg.cfg.flash_clk_div = 0x00,
.clk_cfg.cfg.wifipll_pu = 0x01,
.clk_cfg.cfg.aupll_pu = 0x01,
.clk_cfg.cfg.cpupll_pu = 0x01,
.clk_cfg.cfg.mipipll_pu = 0x01,
.clk_cfg.cfg.uhspll_pu = 0x01,
.clk_cfg.crc32 = 0xdeadbeef,
/* basic cfg */
.basic_cfg.sign_type = 0x0, /* [1: 0] for sign */
.basic_cfg.encrypt_type = 0x0, /* [3: 2] for encrypt */
.basic_cfg.key_sel = 0x0, /* [5: 4] key slot */
.basic_cfg.xts_mode = 0x0, /* [6] for xts mode */
.basic_cfg.aes_region_lock = 0x0, /* [7] rsvd */
.basic_cfg.no_segment = 0x1, /* [8] no segment info */
.basic_cfg.rsvd_0 = 0x0, /* [9] boot2 enable(rsvd_0) */
.basic_cfg.rsvd_1 = 0x0, /* [10] boot2 rollback(rsvd_1) */
.basic_cfg.cpu_master_id = 0x0, /* [14: 11] master id */
.basic_cfg.notload_in_bootrom = 0x0, /* [15] notload in bootrom */
.basic_cfg.crc_ignore = 0x1, /* [16] ignore crc */
.basic_cfg.hash_ignore = 0x1, /* [17] hash ignore */
.basic_cfg.power_on_mm = 0x1, /* [18] power on mm */
.basic_cfg.em_sel = 0x1, /* [21: 19] em_sel */
.basic_cfg.cmds_en = 0x1, /* [22] command spliter enable */
#if 0
# 0 : cmds bypass wrap commands to macro, original mode;
# 1 : cmds handle wrap commands, original mode;
# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4;
# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4
#endif
.basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */
#if 0
# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32,
# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096
#endif
.basic_cfg.cmds_wrap_len = 0x9, /* [28: 25] cmds wrap len */
.basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */
.basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */
.basic_cfg.rsvd_3 = 0x0, /* [31] rsvd_3 */
.basic_cfg.group_image_offset = 0x00002000, /* flash controller offset */
.basic_cfg.aes_region_len = 0x00000000, /* aes region length */
.basic_cfg.img_len_cnt = 0x00004000, /* image length or segment count */
.basic_cfg.hash = { 0xdeadbeef }, /* hash of the image */
/* cpu cfg */
.cpu_cfg[0].config_enable = 0x01, /* coinfig this cpu */
.cpu_cfg[0].halt_cpu = 0x0, /* halt this cpu */
.cpu_cfg[0].cache_enable = 0x0, /* cache setting :only for BL Cache */
.cpu_cfg[0].cache_wa = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_wb = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_wt = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].rsvd = 0x0,
.cpu_cfg[0].cache_range_h = 0x00000000,
.cpu_cfg[0].cache_range_l = 0x00000000,
/* image_address_offset */
.cpu_cfg[0].image_address_offset = 0x0,
.cpu_cfg[0].rsvd0 = 0x58000000, /* rsvd0 */
.cpu_cfg[0].msp_val = 0x00000000, /* msp value */
/* cpu cfg */
.cpu_cfg[1].config_enable = 0x00, /* coinfig this cpu */
.cpu_cfg[1].halt_cpu = 0x0, /* halt this cpu */
.cpu_cfg[1].cache_enable = 0x0, /* cache setting :only for BL Cache */
.cpu_cfg[1].cache_wa = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_wb = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_wt = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].rsvd = 0x0,
.cpu_cfg[1].cache_range_h = 0x00000000,
.cpu_cfg[1].cache_range_l = 0x00000000,
/* image_address_offset */
.cpu_cfg[1].image_address_offset = 0x0,
.cpu_cfg[1].rsvd0 = 0x58000000, /* rsvd0 */
.cpu_cfg[1].msp_val = 0x00000000, /* msp value */
/* address of partition table 0 */ /* 4 */
.boot2_pt_table_0_rsvd = 0x00000000,
/* address of partition table 1 */ /* 4 */
.boot2_pt_table_1_rsvd = 0x00000000,
/* address of flashcfg table list */ /* 4 */
.flash_cfg_table_addr = 0x00000000,
/* flashcfg table list len */ /* 4 */
.flash_cfg_table_len = 0x00000000,
.rsvd1[0] = 0x20000320,
.rsvd1[1] = 0x00000000,
.rsvd1[2] = 0x2000F038,
.rsvd1[3] = 0x18000000,
.crc32 = 0xdeadbeef /* 4 */
};
__attribute__((section(".fw_header1"))) struct bootheader_t fw_header1 = {
.magiccode = 0x50414642,
.rivison = 0x00000001,
/*flash config */
.flash_cfg.magiccode = 0x47464346,
.flash_cfg.cfg.ioMode = 0x10, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
.flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
.flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
.flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
.flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */
.flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */
.flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */
.flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */
.flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */
.flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */
.flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */
.flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */
.flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */
.flash_cfg.cfg.mid = 0x00, /*!< Manufacturer ID */
.flash_cfg.cfg.pageSize = 0x100, /*!< Page size */
.flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */
.flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */
.flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */
.flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */
.flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */
.flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */
.flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */
.flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */
.flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */
.flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */
.flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */
.flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */
.flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */
.flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */
.flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */
.flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */
.flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */
.flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */
.flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */
.flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */
.flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */
.flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */
.flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */
.flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */
.flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */
.flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */
.flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */
.flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */
.flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */
.flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */
.flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */
.flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */
.flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */
.flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */
.flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */
.flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */
.flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */
.flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */
.flash_cfg.cfg.cReadMode = 0x20, /*!< Config data for continuous read mode */
.flash_cfg.cfg.cRExit = 0xf0, /*!< Config data for exit continuous read mode */
.flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */
.flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */
.flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */
.flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */
.flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
.flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */
.flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */
.flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */
.flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */
.flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */
.flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */
.flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */
.flash_cfg.cfg.qeData = 0, /*!< QE set data */
.flash_cfg.crc32 = 0xdeadbeef,
/* clock cfg */
.clk_cfg.magiccode = 0x47464350,
.clk_cfg.cfg.xtal_type = 0x07, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */
.clk_cfg.cfg.mcu_clk = 0x04, /*!< mcu_clk 0:RC32M,1:Xtal,2:cpupll 400M,3:wifipll 192M,4:wifipll 320M */
.clk_cfg.cfg.mcu_clk_div = 0x00,
.clk_cfg.cfg.mcu_bclk_div = 0x00,
.clk_cfg.cfg.mcu_pbclk_div = 0x03,
.clk_cfg.cfg.lp_div = 0x01,
.clk_cfg.cfg.dsp_clk = 0x03, /* 0:RC32M,1:Xtal,2:wifipll 240M,3:wifipll 320M,4:cpupll 400M */
.clk_cfg.cfg.dsp_clk_div = 0x00,
.clk_cfg.cfg.dsp_bclk_div = 0x01,
.clk_cfg.cfg.dsp_pbclk = 0x02, /* 0:RC32M,1:Xtal,2:wifipll 160M,3:cpupll 160M,4:wifipll 240M */
.clk_cfg.cfg.dsp_pbclk_div = 0x00,
.clk_cfg.cfg.emi_clk = 0x02, /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */
.clk_cfg.cfg.emi_clk_div = 0x01,
.clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll 120M,1:xtal,2:cpupll 100M,3:wifipll 80M,4:bclk,5:wifipll 96M */
.clk_cfg.cfg.flash_clk_div = 0x00,
.clk_cfg.cfg.wifipll_pu = 0x01,
.clk_cfg.cfg.aupll_pu = 0x01,
.clk_cfg.cfg.cpupll_pu = 0x01,
.clk_cfg.cfg.mipipll_pu = 0x01,
.clk_cfg.cfg.uhspll_pu = 0x01,
.clk_cfg.crc32 = 0xdeadbeef,
/* basic cfg */
.basic_cfg.sign_type = 0x0, /* [1: 0] for sign */
.basic_cfg.encrypt_type = 0x0, /* [3: 2] for encrypt */
.basic_cfg.key_sel = 0x0, /* [5: 4] key slot */
.basic_cfg.xts_mode = 0x0, /* [6] for xts mode */
.basic_cfg.aes_region_lock = 0x0, /* [7] rsvd */
.basic_cfg.no_segment = 0x1, /* [8] no segment info */
.basic_cfg.rsvd_0 = 0x0, /* [9] boot2 enable(rsvd_0) */
.basic_cfg.rsvd_1 = 0x0, /* [10] boot2 rollback(rsvd_1) */
.basic_cfg.cpu_master_id = 0x0, /* [14: 11] master id */
.basic_cfg.notload_in_bootrom = 0x0, /* [15] notload in bootrom */
.basic_cfg.crc_ignore = 0x1, /* [16] ignore crc */
.basic_cfg.hash_ignore = 0x1, /* [17] hash ignore */
.basic_cfg.power_on_mm = 0x1, /* [18] power on mm */
.basic_cfg.em_sel = 0x1, /* [21: 19] em_sel */
.basic_cfg.cmds_en = 0x1, /* [22] command spliter enable */
#if 0
# 0 : cmds bypass wrap commands to macro, original mode;
# 1 : cmds handle wrap commands, original mode;
# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4;
# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4
#endif
.basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */
#if 0
# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32,
# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096
#endif
.basic_cfg.cmds_wrap_len = 0x9, /* [28: 25] cmds wrap len */
.basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */
.basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */
.basic_cfg.rsvd_3 = 0x0, /* [31] rsvd_3 */
.basic_cfg.group_image_offset = 0x00011000, /* flash controller offset */
.basic_cfg.aes_region_len = 0x00000000, /* aes region length */
.basic_cfg.img_len_cnt = 0x00004000, /* image length or segment count */
.basic_cfg.hash = { 0xdeadbeef }, /* hash of the image */
/* cpu cfg */
.cpu_cfg[0].config_enable = 0x00, /* coinfig this cpu */
.cpu_cfg[0].halt_cpu = 0x0, /* halt this cpu */
.cpu_cfg[0].cache_enable = 0x0, /* cache setting :only for BL Cache */
.cpu_cfg[0].cache_wa = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_wb = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_wt = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].rsvd = 0x0,
.cpu_cfg[0].cache_range_h = 0x00000000,
.cpu_cfg[0].cache_range_l = 0x00000000,
/* image_address_offset */
.cpu_cfg[0].image_address_offset = 0x0,
.cpu_cfg[0].rsvd0 = 0x58000000, /* rsvd0 */
.cpu_cfg[0].msp_val = 0x00000000, /* msp value */
/* cpu cfg */
.cpu_cfg[1].config_enable = 0x01, /* coinfig this cpu */
.cpu_cfg[1].halt_cpu = 0x0, /* halt this cpu */
.cpu_cfg[1].cache_enable = 0x0, /* cache setting :only for BL Cache */
.cpu_cfg[1].cache_wa = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_wb = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_wt = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].rsvd = 0x0,
.cpu_cfg[1].cache_range_h = 0x00000000,
.cpu_cfg[1].cache_range_l = 0x00000000,
/* image_address_offset */
.cpu_cfg[1].image_address_offset = 0x0,
.cpu_cfg[1].rsvd0 = 0x58000000, /* rsvd0 */
.cpu_cfg[1].msp_val = 0x00000000, /* msp value */
/* address of partition table 0 */ /* 4 */
.boot2_pt_table_0_rsvd = 0x00000000,
/* address of partition table 1 */ /* 4 */
.boot2_pt_table_1_rsvd = 0x00000000,
/* address of flashcfg table list */ /* 4 */
.flash_cfg_table_addr = 0x00000000,
/* flashcfg table list len */ /* 4 */
.flash_cfg_table_len = 0x00000000,
.crc32 = 0xdeadbeef /* 4 */
};