diff --git a/bsp/board/bl702/bl702_iot/clock_config.h b/bsp/board/bl702/bl702_iot/clock_config.h
new file mode 100644
index 00000000..775ab650
--- /dev/null
+++ b/bsp/board/bl702/bl702_iot/clock_config.h
@@ -0,0 +1,71 @@
+/**
+ * @file clock_config.h
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+
+#ifndef _CLOCK_CONFIG_H
+#define _CLOCK_CONFIG_H
+
+#define CLOCK_XTAL                 EXTERNAL_XTAL_32M
+#define BSP_ROOT_CLOCK_SOURCE      ROOT_CLOCK_SOURCE_XTAL_32M
+#define BSP_AUDIO_PLL_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ
+
+#define BSP_FCLK_DIV 0
+#define BSP_BCLK_DIV 1
+
+#if defined(BSP_USING_UART0) || defined(BSP_USING_UART1)
+#define BSP_UART_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_96M
+#define BSP_UART_CLOCK_DIV    0
+#endif
+#if defined(BSP_USING_I2C0)
+#define BSP_I2C_CLOCK_SOURCE ROOT_CLOCK_SOURCE_BCLK
+#define BSP_I2C_CLOCK_DIV    0
+#endif
+#if defined(BSP_USING_SPI0)
+#define BSP_SPI_CLOCK_SOURCE ROOT_CLOCK_SOURCE_BCLK
+#define BSP_SPI_CLOCK_DIV    0
+#endif
+#if defined(BSP_USING_PWM_CH0) || defined(BSP_USING_PWM_CH1) || defined(BSP_USING_PWM_CH2) || defined(BSP_USING_PWM_CH3) || defined(BSP_USING_PWM_CH4) || defined(BSP_USING_PWM_CH5)
+#define BSP_PWM_CLOCK_SOURCE ROOT_CLOCK_SOURCE_32K_CLK
+#define BSP_PWM_CLOCK_DIV    32
+#endif
+#if defined(BSP_USING_IR)
+#define BSP_IR_CLOCK_SOURCE ROOT_CLOCK_SOURCE_XCLK
+#define BSP_IR_CLOCK_DIV    0
+#endif
+#if defined(BSP_USING_ADC0)
+#define BSP_ADC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_XCLK
+#define BSP_ADC_CLOCK_DIV    0
+#endif
+#if defined(BSP_USING_DAC0)
+#define BSP_DAC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ
+#define BSP_DAC_CLOCK_DIV    1
+#endif
+#if defined(BSP_USING_CAM)
+#define BSP_CAM_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_96M
+#define BSP_CAM_CLOCK_DIV    3
+#endif
+#if defined(BSP_USING_QDEC0) || defined(BSP_USING_QDEC1) || defined(BSP_USING_QDEC2) || defined(BSP_USING_KEYSCAN)
+#define BSP_QDEC_KEYSCAN_CLOCK_SOURCE ROOT_CLOCK_SOURCE_XCLK
+#define BSP_QDEC_KEYSCAN_CLOCK_DIV    31
+#endif
+
+#endif
\ No newline at end of file
diff --git a/bsp/board/bl702/bl702_iot/peripheral_config.h b/bsp/board/bl702/bl702_iot/peripheral_config.h
new file mode 100644
index 00000000..e777ee9d
--- /dev/null
+++ b/bsp/board/bl702/bl702_iot/peripheral_config.h
@@ -0,0 +1,361 @@
+/**
+ * @file peripheral_config.h
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+
+#ifndef _PERIPHERAL_CONFIG_H_
+#define _PERIPHERAL_CONFIG_H_
+
+/* PERIPHERAL USING LIST */
+// #define BSP_USING_ADC0
+// #define BSP_USING_DAC0
+#define BSP_USING_UART0
+// #define BSP_USING_UART1
+// #define BSP_USING_SPI0
+// #define BSP_USING_I2C0
+// #define BSP_USING_I2S0
+// #define BSP_USING_USB
+// #define BSP_USING_PWM_CH0
+// #define BSP_USING_PWM_CH1
+// #define BSP_USING_PWM_CH2
+// #define BSP_USING_PWM_CH3
+// #define BSP_USING_TIMER_CH0
+// #define BSP_USING_TIMER_CH1
+/* ----------------------*/
+
+/* PERIPHERAL With DMA LIST */
+
+#define BSP_USING_DMA0_CH0
+#define BSP_USING_DMA0_CH1
+#define BSP_USING_DMA0_CH2
+#define BSP_USING_DMA0_CH3
+#define BSP_USING_DMA0_CH4
+#define BSP_USING_DMA0_CH5
+#define BSP_USING_DMA0_CH6
+#define BSP_USING_DMA0_CH7
+
+/* PERIPHERAL CONFIG */
+#if defined(BSP_USING_ADC0)
+#ifndef ADC0_CONFIG
+#define ADC0_CONFIG                                        \
+    {                                                      \
+        .clk_div = ADC_CLOCK_DIV_32,                       \
+        .vref = ADC_VREF_3V2,                              \
+        .continuous_conv_mode = DISABLE,                   \
+        .differential_mode = DISABLE,                      \
+        .data_width = ADC_DATA_WIDTH_16B_WITH_256_AVERAGE, \
+        .fifo_threshold = ADC_FIFO_THRESHOLD_1BYTE,        \
+        .gain = ADC_GAIN_1                                 \
+    }
+#endif
+#endif
+
+#if defined(BSP_USING_DAC0)
+#ifndef DAC_CONFIG
+#define DAC_CONFIG                   \
+    {                                \
+        .clk = DAC_CLK_500KHZ,       \
+        .pin.dac0 = GLB_GPIO_PIN_11, \
+        .pin.pin_num = 1,            \
+    }
+#endif
+#endif
+
+#if defined(BSP_USING_UART0)
+#ifndef UART0_CONFIG
+#define UART0_CONFIG                 \
+    {                                \
+        .id = 0,                     \
+        .baudrate = 2000000,         \
+        .databits = UART_DATA_LEN_8, \
+        .stopbits = UART_STOP_ONE,   \
+        .parity = UART_PAR_NONE,     \
+        .fifo_threshold = 1,         \
+    }
+#endif
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                 \
+    {                                \
+        .id = 1,                     \
+        .baudrate = 2000000,         \
+        .databits = UART_DATA_LEN_8, \
+        .stopbits = UART_STOP_ONE,   \
+        .parity = UART_PAR_NONE,     \
+        .fifo_threshold = 64,        \
+    }
+#endif
+#endif
+
+#if defined(BSP_USING_SPI0)
+#ifndef SPI0_CONFIG
+#define SPI0_CONFIG                                 \
+    {                                               \
+        .id = 0,                                    \
+        .clk = 18000000,                            \
+        .mode = SPI_MASTER_MODE,                    \
+        .direction = SPI_MSB_BYTE0_DIRECTION_FIRST, \
+        .clk_polaraity = SPI_POLARITY_LOW,          \
+        .clk_phase = SPI_PHASE_1EDGE,               \
+        .datasize = SPI_DATASIZE_8BIT,              \
+        .fifo_threshold = 1,                        \
+    }
+#endif
+#endif
+
+#if defined(BSP_USING_PWM_CH0)
+#ifndef PWM_CH0_CONFIG
+#define PWM_CH0_CONFIG                   \
+    {                                    \
+        .ch = 0,                         \
+        .polarity_invert_mode = DISABLE, \
+        .period = 0,                     \
+        .threshold_low = 0,              \
+        .threshold_high = 0,             \
+        .it_pulse_count = 0,             \
+    }
+#endif
+#endif
+
+#if defined(BSP_USING_PWM_CH1)
+#ifndef PWM_CH1_CONFIG
+#define PWM_CH1_CONFIG                   \
+    {                                    \
+        .ch = 1,                         \
+        .polarity_invert_mode = DISABLE, \
+        .period = 0,                     \
+        .threshold_low = 0,              \
+        .threshold_high = 0,             \
+        .it_pulse_count = 0,             \
+    }
+#endif
+#endif
+
+#if defined(BSP_USING_PWM_CH2)
+#ifndef PWM_CH2_CONFIG
+#define PWM_CH2_CONFIG                   \
+    {                                    \
+        .ch = 2,                         \
+        .polarity_invert_mode = DISABLE, \
+        .period = 0,                     \
+        .threshold_low = 0,              \
+        .threshold_high = 0,             \
+        .it_pulse_count = 0,             \
+    }
+#endif
+#endif
+
+#if defined(BSP_USING_PWM_CH3)
+#ifndef PWM_CH3_CONFIG
+#define PWM_CH3_CONFIG                   \
+    {                                    \
+        .ch = 3,                         \
+        .polarity_invert_mode = DISABLE, \
+        .period = 0,                     \
+        .threshold_low = 0,              \
+        .threshold_high = 0,             \
+        .it_pulse_count = 0,             \
+    }
+#endif
+#endif
+
+#if defined(BSP_USING_I2S0)
+#ifndef I2S0_CONFIG
+#define I2S0_CONFIG                              \
+    {                                            \
+        .id = 0,                                 \
+        .iis_mode = I2S_MODE_MASTER,             \
+        .interface_mode = I2S_MODE_LEFT,         \
+        .sampl_freq_hz = 16 * 1000,              \
+        .channel_num = I2S_FS_CHANNELS_NUM_MONO, \
+        .frame_size = I2S_FRAME_LEN_16,          \
+        .data_size = I2S_DATA_LEN_16,            \
+        .fifo_threshold = 8,                     \
+    }
+#endif
+#endif
+
+#if defined(BSP_USING_DMA0_CH0)
+#ifndef DMA0_CH0_CONFIG
+#define DMA0_CH0_CONFIG                        \
+    {                                          \
+        .id = 0,                               \
+        .ch = 0,                               \
+        .direction = DMA_MEMORY_TO_MEMORY,     \
+        .transfer_mode = DMA_LLI_ONCE_MODE,    \
+        .src_req = DMA_REQUEST_NONE,           \
+        .dst_req = DMA_REQUEST_NONE,           \
+        .src_width = DMA_TRANSFER_WIDTH_32BIT, \
+        .dst_width = DMA_TRANSFER_WIDTH_32BIT, \
+    }
+#endif
+#endif
+
+#if defined(BSP_USING_DMA0_CH1)
+#ifndef DMA0_CH1_CONFIG
+#define DMA0_CH1_CONFIG                        \
+    {                                          \
+        .id = 0,                               \
+        .ch = 1,                               \
+        .direction = DMA_MEMORY_TO_MEMORY,     \
+        .transfer_mode = DMA_LLI_ONCE_MODE,    \
+        .src_req = DMA_REQUEST_NONE,           \
+        .dst_req = DMA_REQUEST_NONE,           \
+        .src_width = DMA_TRANSFER_WIDTH_16BIT, \
+        .dst_width = DMA_TRANSFER_WIDTH_16BIT, \
+    }
+#endif
+#endif
+
+#if defined(BSP_USING_DMA0_CH2)
+#ifndef DMA0_CH2_CONFIG
+#define DMA0_CH2_CONFIG                       \
+    {                                         \
+        .id = 0,                              \
+        .ch = 2,                              \
+        .direction = DMA_MEMORY_TO_PERIPH,    \
+        .transfer_mode = DMA_LLI_ONCE_MODE,   \
+        .src_req = DMA_REQUEST_NONE,          \
+        .dst_req = DMA_REQUEST_UART1_TX,      \
+        .src_width = DMA_TRANSFER_WIDTH_8BIT, \
+        .dst_width = DMA_TRANSFER_WIDTH_8BIT, \
+    }
+#endif
+#endif
+
+#if defined(BSP_USING_DMA0_CH3)
+#ifndef DMA0_CH3_CONFIG
+#define DMA0_CH3_CONFIG                       \
+    {                                         \
+        .id = 0,                              \
+        .ch = 3,                              \
+        .direction = DMA_MEMORY_TO_PERIPH,    \
+        .transfer_mode = DMA_LLI_ONCE_MODE,   \
+        .src_req = DMA_REQUEST_NONE,          \
+        .dst_req = DMA_REQUEST_SPI0_TX,       \
+        .src_width = DMA_TRANSFER_WIDTH_8BIT, \
+        .dst_width = DMA_TRANSFER_WIDTH_8BIT, \
+    }
+#endif
+#endif
+
+#if defined(BSP_USING_DMA0_CH4)
+#ifndef DMA0_CH4_CONFIG
+#define DMA0_CH4_CONFIG                       \
+    {                                         \
+        .id = 0,                              \
+        .ch = 4,                              \
+        .direction = DMA_PERIPH_TO_MEMORY,    \
+        .transfer_mode = DMA_LLI_ONCE_MODE,   \
+        .src_req = DMA_REQUEST_SPI0_RX,       \
+        .dst_req = DMA_REQUEST_NONE,          \
+        .src_width = DMA_TRANSFER_WIDTH_8BIT, \
+        .dst_width = DMA_TRANSFER_WIDTH_8BIT, \
+    }
+#endif
+#endif
+
+#if defined(BSP_USING_DMA0_CH5)
+#ifndef DMA0_CH5_CONFIG
+#define DMA0_CH5_CONFIG                        \
+    {                                          \
+        .id = 0,                               \
+        .ch = 5,                               \
+        .direction = DMA_MEMORY_TO_PERIPH,     \
+        .transfer_mode = DMA_LLI_CYCLE_MODE,   \
+        .src_req = DMA_REQUEST_NONE,           \
+        .dst_req = DMA_REQUEST_I2S_TX,         \
+        .src_width = DMA_TRANSFER_WIDTH_16BIT, \
+        .dst_width = DMA_TRANSFER_WIDTH_16BIT, \
+    }
+#endif
+#endif
+
+#if defined(BSP_USING_DMA0_CH6)
+#ifndef DMA0_CH6_CONFIG
+#define DMA0_CH6_CONFIG                        \
+    {                                          \
+        .id = 0,                               \
+        .ch = 6,                               \
+        .direction = DMA_MEMORY_TO_PERIPH,     \
+        .transfer_mode = DMA_LLI_CYCLE_MODE,   \
+        .src_req = DMA_REQUEST_NONE,           \
+        .dst_req = DMA_REQUEST_I2S_TX,         \
+        .src_width = DMA_TRANSFER_WIDTH_16BIT, \
+        .dst_width = DMA_TRANSFER_WIDTH_16BIT, \
+    }
+#endif
+#endif
+
+#if defined(BSP_USING_DMA0_CH7)
+#ifndef DMA0_CH7_CONFIG
+#define DMA0_CH7_CONFIG                        \
+    {                                          \
+        .id = 0,                               \
+        .ch = 0,                               \
+        .direction = DMA_MEMORY_TO_MEMORY,     \
+        .transfer_mode = DMA_LLI_ONCE_MODE,    \
+        .src_req = DMA_REQUEST_NONE,           \
+        .dst_req = DMA_REQUEST_NONE,           \
+        .src_width = DMA_TRANSFER_WIDTH_32BIT, \
+        .dst_width = DMA_TRANSFER_WIDTH_32BIT, \
+    }
+#endif
+#endif
+
+#if defined(BSP_USING_I2C0)
+#ifndef I2C0_CONFIG
+#define I2C0_CONFIG          \
+    {                        \
+        .id = 0,             \
+        .mode = I2C_HW_MODE, \
+        .phase = 15,         \
+    }
+#endif
+#endif
+
+#if defined(BSP_USING_TIMER_CH0)
+#ifndef TIMER_CH0_CONFIG
+#define TIMER_CH0_CONFIG                    \
+    {                                       \
+        .id = 0,                            \
+        .ch = 0,                            \
+        .cnt_mode = TIMER_CNT_PRELOAD,      \
+        .pl_trig_src = TIMER_PL_TRIG_COMP0, \
+    }
+#endif
+#endif
+
+#if defined(BSP_USING_TIMER_CH1)
+#ifndef TIMER_CH1_CONFIG
+#define TIMER_CH1_CONFIG                    \
+    {                                       \
+        .id = 0,                            \
+        .ch = 1,                            \
+        .cnt_mode = TIMER_CNT_PRELOAD,      \
+        .pl_trig_src = TIMER_PL_TRIG_COMP2, \
+    }
+#endif
+#endif
+
+#endif
diff --git a/bsp/board/bl702/bl702_iot/pinmux_config.h b/bsp/board/bl702/bl702_iot/pinmux_config.h
new file mode 100644
index 00000000..654f979f
--- /dev/null
+++ b/bsp/board/bl702/bl702_iot/pinmux_config.h
@@ -0,0 +1,88 @@
+/**
+ * @file pinmux_config.h
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef _PINMUX_CONFIG_H
+#define _PINMUX_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <q> GPIO0 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+// <i> config gpio0 function
+#define CONFIG_GPIO0_FUNC GPIO_FUN_UNUSED
+
+// <q> GPIO1 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_CTS//GPIO_FUN_UART1_CTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+// <i> config gpio1 function
+#define CONFIG_GPIO1_FUNC GPIO_FUN_UNUSED
+
+// <q> GPIO2 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_TX//GPIO_FUN_UART1_TX//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+// <i> config gpio2 function
+#define CONFIG_GPIO2_FUNC GPIO_FUN_UNUSED
+
+// <q> GPIO7 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RX//GPIO_FUN_UART1_RX//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+// <i> config gpio7 function
+#define CONFIG_GPIO7_FUNC GPIO_FUN_USB
+
+// <q> GPIO8 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+// <i> config gpio8 function
+#define CONFIG_GPIO8_FUNC GPIO_FUN_USB
+
+// <q> GPIO9 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+// <i> config gpio9 function
+#define CONFIG_GPIO9_FUNC GPIO_FUN_UNUSED
+
+// <q> GPIO14 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+// <i> config gpio14 function
+#define CONFIG_GPIO14_FUNC GPIO_FUN_UART0_TX
+
+// <q> GPIO15 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+// <i> config gpio15 function
+#define CONFIG_GPIO15_FUNC GPIO_FUN_UART0_RX
+
+// <q> GPIO17 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+// <i> config gpio17 function
+#define CONFIG_GPIO17_FUNC GPIO_FUN_UNUSED
+
+// <q> GPIO23 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+// <i> config gpio23 function
+#define CONFIG_GPIO23_FUNC GPIO_FUN_UNUSED
+
+// <q> GPIO24 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+// <i> config gpio24 function
+#define CONFIG_GPIO24_FUNC GPIO_FUN_UNUSED
+
+// <q> GPIO25 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+// <i> config gpio25 function
+#define CONFIG_GPIO25_FUNC GPIO_FUN_UNUSED
+
+// <q> GPIO26 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+// <i> config gpio26 function
+#define CONFIG_GPIO26_FUNC GPIO_FUN_UNUSED
+
+// <q> GPIO27 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+// <i> config gpio27 function
+#define CONFIG_GPIO27_FUNC GPIO_FUN_UNUSED
+
+// <q> GPIO28 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
+// <i> config gpio28 function
+#define CONFIG_GPIO28_FUNC GPIO_FUN_UNUSED
+
+#endif