mirror of
https://github.com/Fishwaldo/bl_mcu_sdk.git
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356f258e83
* use nuttx libc, disable system libc * use tlsf as default * update lhal flash driver * add example readme * add flash ini for new flash tool * add fw header for new flash tool
152 lines
6.7 KiB
C
152 lines
6.7 KiB
C
/**
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******************************************************************************
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* @file bflb_spi_psram.h
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* @version V1.0
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* @date
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* @brief This file is the standard driver header file
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Bouffalo Lab nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#ifndef __BFLB_SPI_PSRAM_H__
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#define __BFLB_SPI_PSRAM_H__
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#include "sf_ctrl_reg.h"
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#include "bflb_common.h"
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#include "bflb_sf_ctrl.h"
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/** @addtogroup BFLB_Peripheral_Driver
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* @{
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*/
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/** @addtogroup PSRAM
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* @{
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*/
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/** @defgroup PSRAM_Public_Types
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* @{
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*/
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/**
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* @brief Psram drive strength type definition
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*/
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#define PSRAM_DRIVE_STRENGTH_50_OHMS 0 /*!< Drive strength 50 ohms(default) */
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#define PSRAM_DRIVE_STRENGTH_100_OHMS 1 /*!< Drive strength 100 ohms */
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#define PSRAM_DRIVE_STRENGTH_200_OHMS 2 /*!< Drive strength 200 ohms */
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/**
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* @brief Psram burst length size type definition
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*/
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#define PSRAM_BURST_LENGTH_16_BYTES 0 /*!< Burst Length 16 bytes */
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#define PSRAM_BURST_LENGTH_32_BYTES 1 /*!< Burst Length 32 bytes */
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#define PSRAM_BURST_LENGTH_64_BYTES 2 /*!< Burst Length 64 bytes */
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#define PSRAM_BURST_LENGTH_512_BYTES 3 /*!< Burst Length 512 bytes(default) */
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/**
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* @brief Psram ctrl mode type definition
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*/
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#define PSRAM_SPI_CTRL_MODE 0 /*!< Psram SPI ctrl mode */
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#define PSRAM_QPI_CTRL_MODE 1 /*!< Psram QPI ctrl mode */
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/**
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* @brief Psram ctrl configuration structure type definition
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*/
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struct spi_psram_cfg_type {
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uint8_t read_id_cmd; /*!< Read ID command */
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uint8_t read_id_dmy_clk; /*!< Read ID command dummy clock */
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uint8_t burst_toggle_cmd; /*!< Burst toggle length command */
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uint8_t reset_enable_cmd; /*!< Psram reset enable command */
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uint8_t reset_cmd; /*!< Psram reset command */
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uint8_t enter_quad_mode_cmd; /*!< Psram enter quad mode command */
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uint8_t exit_quad_mode_cmd; /*!< Psram exit quad mode command */
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uint8_t read_reg_cmd; /*!< Read register command */
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uint8_t read_reg_dmy_clk; /*!< Read register command dummy clock */
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uint8_t write_reg_cmd; /*!< Write register command */
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uint8_t read_cmd; /*!< Psram read command */
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uint8_t read_dmy_clk; /*!< Psram read command dummy clock */
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uint8_t f_read_cmd; /*!< Psram fast read command */
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uint8_t f_read_dmy_clk; /*!< Psram fast read command dummy clock */
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uint8_t f_read_quad_cmd; /*!< Psram fast read quad command */
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uint8_t f_read_quad_dmy_clk; /*!< Psram fast read quad command dummy clock */
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uint8_t write_cmd; /*!< Psram write command */
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uint8_t quad_write_cmd; /*!< Psram quad write command */
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uint16_t page_size; /*!< Psram page size */
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#if defined(BL702L)
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uint8_t burst_toggle_en; /*!< Psram burst toggle mode enable */
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#endif
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uint8_t ctrl_mode; /*!< Psram ctrl mode */
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uint8_t drive_strength; /*!< Psram drive strength */
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uint8_t burst_length; /*!< Psram burst length size */
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};
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/*@} end of group PSRAM_Public_Types */
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/** @defgroup PSRAM_Public_Constants
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* @{
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*/
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/*@} end of group PSRAM_Public_Constants */
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/** @defgroup PSRAM_Public_Macros
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* @{
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*/
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/*@} end of group PSRAM_Public_Macros */
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/** @defgroup PSRAM_Public_Functions
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* @{
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*/
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/**
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* @brief PSRAM Functions
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*/
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void bflb_psram_init(struct spi_psram_cfg_type *psram_cfg, struct sf_ctrl_cmds_cfg *cmds_cfg,
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struct sf_ctrl_psram_cfg *sf_ctrl_psram_cfg);
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void bflb_psram_readreg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value);
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void bflb_psram_writereg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value);
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int bflb_psram_setdrivestrength(struct spi_psram_cfg_type *psram_cfg);
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int bflb_psram_setburstwrap(struct spi_psram_cfg_type *psram_cfg);
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void bflb_psram_readid(struct spi_psram_cfg_type *psram_cfg, uint8_t *data);
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int bflb_psram_enterquadmode(struct spi_psram_cfg_type *psram_cfg);
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int bflb_psram_exitquadmode(struct spi_psram_cfg_type *psram_cfg);
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int bflb_psram_toggleburstlength(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode);
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int bflb_psram_softwarereset(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode);
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int bflb_psram_set_idbus_cfg(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint32_t addr, uint32_t len);
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int bflb_psram_cache_write_set(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint8_t wt_en,
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uint8_t wb_en, uint8_t wa_en);
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int bflb_psram_write(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len);
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int bflb_psram_read(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len);
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/*@} end of group PSRAM_Public_Functions */
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/*@} end of group PSRAM */
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/*@} end of group BFLB_Peripheral_Driver */
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#endif /* __BFLB_SPI_PSRAM_H__ */
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