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268 lines
13 KiB
C
268 lines
13 KiB
C
/**
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******************************************************************************
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* @file adc_reg.h
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* @version V1.0
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* @date 2022-08-05
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* @brief This file is the description of.IP register
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Bouffalo Lab nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#ifndef __HARDWARE_ADC_H__
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#define __HARDWARE_ADC_H__
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register offsets *********************************************************/
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/* gpip base */
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#define GPIP_GPADC_CONFIG_OFFSET (0x0) /* gpadc_config */
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#define GPIP_GPADC_DMA_RDATA_OFFSET (0x4) /* gpadc_dma_rdata */
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#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
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#define GPIP_GPADC_PIR_TRAIN_OFFSET (0x20) /* gpadc_pir_train */
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#endif
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/* aon base */
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#define AON_GPADC_REG_CMD_OFFSET (0x90C) /* gpadc_reg_cmd */
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#define AON_GPADC_REG_CONFIG1_OFFSET (0x910) /* gpadc_reg_config1 */
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#define AON_GPADC_REG_CONFIG2_OFFSET (0x914) /* gpadc_reg_config2 */
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#define AON_GPADC_REG_SCN_POS1_OFFSET (0x918) /* adc converation sequence 1 */
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#define AON_GPADC_REG_SCN_POS2_OFFSET (0x91C) /* adc converation sequence 2 */
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#define AON_GPADC_REG_SCN_NEG1_OFFSET (0x920) /* adc converation sequence 3 */
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#define AON_GPADC_REG_SCN_NEG2_OFFSET (0x924) /* adc converation sequence 4 */
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#define AON_GPADC_REG_STATUS_OFFSET (0x928) /* gpadc_reg_status */
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#define AON_GPADC_REG_ISR_OFFSET (0x92C) /* gpadc_reg_isr */
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#define AON_GPADC_REG_RESULT_OFFSET (0x930) /* gpadc_reg_result */
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#define AON_GPADC_REG_RAW_RESULT_OFFSET (0x934) /* gpadc_reg_raw_result */
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#define AON_GPADC_REG_DEFINE_OFFSET (0x938) /* gpadc_reg_define */
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/* Register Bitfield definitions *****************************************************/
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/* 0x0 : gpadc_config */
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#define GPIP_GPADC_DMA_EN (1 << 0U)
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#define GPIP_GPADC_FIFO_CLR (1 << 1U)
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#define GPIP_GPADC_FIFO_NE (1 << 2U)
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#define GPIP_GPADC_FIFO_FULL (1 << 3U)
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#define GPIP_GPADC_RDY (1 << 4U)
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#define GPIP_GPADC_FIFO_OVERRUN (1 << 5U)
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#define GPIP_GPADC_FIFO_UNDERRUN (1 << 6U)
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#if defined(BL702) || defined(BL702L)
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#define GPIP_GPADC_FIFO_RDY (1 << 7U)
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#endif
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#define GPIP_GPADC_RDY_CLR (1 << 8U)
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#define GPIP_GPADC_FIFO_OVERRUN_CLR (1 << 9U)
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#define GPIP_GPADC_FIFO_UNDERRUN_CLR (1 << 10U)
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#define GPIP_GPADC_RDY_MASK (1 << 12U)
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#define GPIP_GPADC_FIFO_OVERRUN_MASK (1 << 13U)
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#define GPIP_GPADC_FIFO_UNDERRUN_MASK (1 << 14U)
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#if defined(BL702) || defined(BL702L)
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#define GPIP_GPADC_FIFO_RDY_MASK (1 << 15U)
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#endif
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#define GPIP_GPADC_FIFO_DATA_COUNT_SHIFT (16U)
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#define GPIP_GPADC_FIFO_DATA_COUNT_MASK (0x3f << GPIP_GPADC_FIFO_DATA_COUNT_SHIFT)
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#define GPIP_GPADC_FIFO_THL_SHIFT (22U)
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#define GPIP_GPADC_FIFO_THL_MASK (0x3 << GPIP_GPADC_FIFO_THL_SHIFT)
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/* 0x4 : gpadc_dma_rdata */
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#define GPIP_GPADC_DMA_RDATA_SHIFT (0U)
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#define GPIP_GPADC_DMA_RDATA_MASK (0x3ffffff << GPIP_GPADC_DMA_RDATA_SHIFT)
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/* 0x20 : gpadc_pir_train */
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#define GPIP_PIR_EXTEND_SHIFT (0U)
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#define GPIP_PIR_EXTEND_MASK (0x1f << GPIP_PIR_EXTEND_SHIFT)
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#define GPIP_PIR_CNT_V_SHIFT (8U)
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#define GPIP_PIR_CNT_V_MASK (0x1f << GPIP_PIR_CNT_V_SHIFT)
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#define GPIP_PIR_TRAIN (1 << 16U)
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#define GPIP_PIR_STOP (1 << 17U)
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/* 0x90C : gpadc_reg_cmd */
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#define AON_GPADC_GLOBAL_EN (1 << 0U)
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#define AON_GPADC_CONV_START (1 << 1U)
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#define AON_GPADC_SOFT_RST (1 << 2U)
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#define AON_GPADC_NEG_SEL_SHIFT (3U)
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#define AON_GPADC_NEG_SEL_MASK (0x1f << AON_GPADC_NEG_SEL_SHIFT)
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#define AON_GPADC_POS_SEL_SHIFT (8U)
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#define AON_GPADC_POS_SEL_MASK (0x1f << AON_GPADC_POS_SEL_SHIFT)
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#define AON_GPADC_NEG_GND (1 << 13U)
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#define AON_GPADC_MICBIAS_EN (1 << 14U)
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#define AON_GPADC_MICPGA_EN (1 << 15U)
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#define AON_GPADC_BYP_MICBOOST (1 << 16U)
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#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
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#define AON_GPADC_RCAL_EN (1 << 17U)
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#endif
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#define AON_GPADC_DWA_EN (1 << 18U)
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#define AON_GPADC_MIC2_DIFF (1 << 19U)
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#define AON_GPADC_MIC1_DIFF (1 << 20U)
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#define AON_GPADC_MIC_PGA2_GAIN_SHIFT (21U)
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#define AON_GPADC_MIC_PGA2_GAIN_MASK (0x3 << AON_GPADC_MIC_PGA2_GAIN_SHIFT)
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#define AON_GPADC_MICBOOST_32DB_EN (1 << 23U)
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#define AON_GPADC_CHIP_SEN_PU (1 << 27U)
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#define AON_GPADC_SEN_SEL_SHIFT (28U)
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#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
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#define AON_GPADC_SEN_SEL_MASK (0x7 << AON_GPADC_SEN_SEL_SHIFT)
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#define AON_GPADC_SEN_TEST_EN (1 << 31U)
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#elif defined(BL702) || defined(BL602) || defined(BL702L)
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#define AON_GPADC_SEN_SEL_MASK (0x3 << AON_GPADC_SEN_SEL_SHIFT)
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#define AON_GPADC_SEN_TEST_EN (1 << 30U)
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#endif
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/* 0x910 : gpadc_reg_config1 */
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#define AON_GPADC_CAL_OS_EN (1 << 0U)
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#define AON_GPADC_CONT_CONV_EN (1 << 1U)
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#define AON_GPADC_RES_SEL_SHIFT (2U)
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#define AON_GPADC_RES_SEL_MASK (0x7 << AON_GPADC_RES_SEL_SHIFT)
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#define AON_GPADC_VCM_SEL_EN (1 << 8U)
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#define AON_GPADC_VCM_HYST_SEL (1 << 9U)
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#define AON_GPADC_LOWV_DET_EN (1 << 10U)
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#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
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#define AON_GPADC_PWM_TRG_EN (1 << 11U)
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#define AON_GPADC_CLK_ANA_DLY_SHIFT (12U)
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#define AON_GPADC_CLK_ANA_DLY_MASK (0xf << AON_GPADC_CLK_ANA_DLY_SHIFT)
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#define AON_GPADC_CLK_ANA_DLY_EN (1 << 16U)
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#endif
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#define AON_GPADC_CLK_ANA_INV (1 << 17U)
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#define AON_GPADC_CLK_DIV_RATIO_SHIFT (18U)
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#define AON_GPADC_CLK_DIV_RATIO_MASK (0x7 << AON_GPADC_CLK_DIV_RATIO_SHIFT)
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#define AON_GPADC_SCAN_LENGTH_SHIFT (21U)
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#define AON_GPADC_SCAN_LENGTH_MASK (0xf << AON_GPADC_SCAN_LENGTH_SHIFT)
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#define AON_GPADC_SCAN_EN (1 << 25U)
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#define AON_GPADC_DITHER_EN (1 << 26U)
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#define AON_GPADC_V11_SEL_SHIFT (27U)
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#define AON_GPADC_V11_SEL_MASK (0x3 << AON_GPADC_V11_SEL_SHIFT)
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#define AON_GPADC_V18_SEL_SHIFT (29U)
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#define AON_GPADC_V18_SEL_MASK (0x3 << AON_GPADC_V18_SEL_SHIFT)
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/* 0x914 : gpadc_reg_config2 */
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#define AON_GPADC_DIFF_MODE (1 << 2U)
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#define AON_GPADC_VREF_SEL (1 << 3U)
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#define AON_GPADC_VBAT_EN (1 << 4U)
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#define AON_GPADC_TSEXT_SEL (1 << 5U)
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#define AON_GPADC_TS_EN (1 << 6U)
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#define AON_GPADC_PGA_VCM_SHIFT (7U)
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#define AON_GPADC_PGA_VCM_MASK (0x3 << AON_GPADC_PGA_VCM_SHIFT)
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#define AON_GPADC_PGA_OS_CAL_SHIFT (9U)
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#define AON_GPADC_PGA_OS_CAL_MASK (0xf << AON_GPADC_PGA_OS_CAL_SHIFT)
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#define AON_GPADC_PGA_EN (1 << 13U)
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#define AON_GPADC_PGA_VCMI_EN (1 << 14U)
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#define AON_GPADC_CHOP_MODE_SHIFT (15U)
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#define AON_GPADC_CHOP_MODE_MASK (0x3 << AON_GPADC_CHOP_MODE_SHIFT)
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#define AON_GPADC_BIAS_SEL (1 << 17U)
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#define AON_GPADC_TEST_EN (1 << 18U)
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#define AON_GPADC_TEST_SEL_SHIFT (19U)
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#define AON_GPADC_TEST_SEL_MASK (0x7 << AON_GPADC_TEST_SEL_SHIFT)
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#define AON_GPADC_PGA2_GAIN_SHIFT (22U)
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#define AON_GPADC_PGA2_GAIN_MASK (0x7 << AON_GPADC_PGA2_GAIN_SHIFT)
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#define AON_GPADC_PGA1_GAIN_SHIFT (25U)
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#define AON_GPADC_PGA1_GAIN_MASK (0x7 << AON_GPADC_PGA1_GAIN_SHIFT)
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#define AON_GPADC_DLY_SEL_SHIFT (28U)
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#define AON_GPADC_DLY_SEL_MASK (0x7 << AON_GPADC_DLY_SEL_SHIFT)
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#define AON_GPADC_TSVBE_LOW (1 << 31U)
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/* 0x918 : adc converation sequence 1 */
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#define AON_GPADC_SCAN_POS_0_SHIFT (0U)
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#define AON_GPADC_SCAN_POS_0_MASK (0x1f << AON_GPADC_SCAN_POS_0_SHIFT)
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#define AON_GPADC_SCAN_POS_1_SHIFT (5U)
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#define AON_GPADC_SCAN_POS_1_MASK (0x1f << AON_GPADC_SCAN_POS_1_SHIFT)
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#define AON_GPADC_SCAN_POS_2_SHIFT (10U)
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#define AON_GPADC_SCAN_POS_2_MASK (0x1f << AON_GPADC_SCAN_POS_2_SHIFT)
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#define AON_GPADC_SCAN_POS_3_SHIFT (15U)
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#define AON_GPADC_SCAN_POS_3_MASK (0x1f << AON_GPADC_SCAN_POS_3_SHIFT)
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#define AON_GPADC_SCAN_POS_4_SHIFT (20U)
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#define AON_GPADC_SCAN_POS_4_MASK (0x1f << AON_GPADC_SCAN_POS_4_SHIFT)
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#define AON_GPADC_SCAN_POS_5_SHIFT (25U)
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#define AON_GPADC_SCAN_POS_5_MASK (0x1f << AON_GPADC_SCAN_POS_5_SHIFT)
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/* 0x91C : adc converation sequence 2 */
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#define AON_GPADC_SCAN_POS_6_SHIFT (0U)
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#define AON_GPADC_SCAN_POS_6_MASK (0x1f << AON_GPADC_SCAN_POS_6_SHIFT)
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#define AON_GPADC_SCAN_POS_7_SHIFT (5U)
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#define AON_GPADC_SCAN_POS_7_MASK (0x1f << AON_GPADC_SCAN_POS_7_SHIFT)
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#define AON_GPADC_SCAN_POS_8_SHIFT (10U)
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#define AON_GPADC_SCAN_POS_8_MASK (0x1f << AON_GPADC_SCAN_POS_8_SHIFT)
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#define AON_GPADC_SCAN_POS_9_SHIFT (15U)
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#define AON_GPADC_SCAN_POS_9_MASK (0x1f << AON_GPADC_SCAN_POS_9_SHIFT)
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#define AON_GPADC_SCAN_POS_10_SHIFT (20U)
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#define AON_GPADC_SCAN_POS_10_MASK (0x1f << AON_GPADC_SCAN_POS_10_SHIFT)
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#define AON_GPADC_SCAN_POS_11_SHIFT (25U)
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#define AON_GPADC_SCAN_POS_11_MASK (0x1f << AON_GPADC_SCAN_POS_11_SHIFT)
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/* 0x920 : adc converation sequence 3 */
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#define AON_GPADC_SCAN_NEG_0_SHIFT (0U)
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#define AON_GPADC_SCAN_NEG_0_MASK (0x1f << AON_GPADC_SCAN_NEG_0_SHIFT)
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#define AON_GPADC_SCAN_NEG_1_SHIFT (5U)
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#define AON_GPADC_SCAN_NEG_1_MASK (0x1f << AON_GPADC_SCAN_NEG_1_SHIFT)
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#define AON_GPADC_SCAN_NEG_2_SHIFT (10U)
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#define AON_GPADC_SCAN_NEG_2_MASK (0x1f << AON_GPADC_SCAN_NEG_2_SHIFT)
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#define AON_GPADC_SCAN_NEG_3_SHIFT (15U)
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#define AON_GPADC_SCAN_NEG_3_MASK (0x1f << AON_GPADC_SCAN_NEG_3_SHIFT)
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#define AON_GPADC_SCAN_NEG_4_SHIFT (20U)
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#define AON_GPADC_SCAN_NEG_4_MASK (0x1f << AON_GPADC_SCAN_NEG_4_SHIFT)
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#define AON_GPADC_SCAN_NEG_5_SHIFT (25U)
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#define AON_GPADC_SCAN_NEG_5_MASK (0x1f << AON_GPADC_SCAN_NEG_5_SHIFT)
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/* 0x924 : adc converation sequence 4 */
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#define AON_GPADC_SCAN_NEG_6_SHIFT (0U)
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#define AON_GPADC_SCAN_NEG_6_MASK (0x1f << AON_GPADC_SCAN_NEG_6_SHIFT)
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#define AON_GPADC_SCAN_NEG_7_SHIFT (5U)
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#define AON_GPADC_SCAN_NEG_7_MASK (0x1f << AON_GPADC_SCAN_NEG_7_SHIFT)
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#define AON_GPADC_SCAN_NEG_8_SHIFT (10U)
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#define AON_GPADC_SCAN_NEG_8_MASK (0x1f << AON_GPADC_SCAN_NEG_8_SHIFT)
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#define AON_GPADC_SCAN_NEG_9_SHIFT (15U)
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#define AON_GPADC_SCAN_NEG_9_MASK (0x1f << AON_GPADC_SCAN_NEG_9_SHIFT)
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#define AON_GPADC_SCAN_NEG_10_SHIFT (20U)
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#define AON_GPADC_SCAN_NEG_10_MASK (0x1f << AON_GPADC_SCAN_NEG_10_SHIFT)
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#define AON_GPADC_SCAN_NEG_11_SHIFT (25U)
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#define AON_GPADC_SCAN_NEG_11_MASK (0x1f << AON_GPADC_SCAN_NEG_11_SHIFT)
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/* 0x928 : gpadc_reg_status */
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#define AON_GPADC_DATA_RDY (1 << 0U)
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#define AON_GPADC_RESERVED_SHIFT (16U)
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#define AON_GPADC_RESERVED_MASK (0xffff << AON_GPADC_RESERVED_SHIFT)
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/* 0x92C : gpadc_reg_isr */
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#define AON_GPADC_NEG_SATUR (1 << 0U)
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#define AON_GPADC_POS_SATUR (1 << 1U)
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#define AON_GPADC_NEG_SATUR_CLR (1 << 4U)
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#define AON_GPADC_POS_SATUR_CLR (1 << 5U)
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#define AON_GPADC_NEG_SATUR_MASK (1 << 8U)
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#define AON_GPADC_POS_SATUR_MASK (1 << 9U)
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/* 0x930 : gpadc_reg_result */
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#define AON_GPADC_DATA_OUT_SHIFT (0U)
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#define AON_GPADC_DATA_OUT_MASK (0x3ffffff << AON_GPADC_DATA_OUT_SHIFT)
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/* 0x934 : gpadc_reg_raw_result */
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#define AON_GPADC_RAW_DATA_SHIFT (0U)
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#define AON_GPADC_RAW_DATA_MASK (0xfff << AON_GPADC_RAW_DATA_SHIFT)
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/* 0x938 : gpadc_reg_define */
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#define AON_GPADC_OS_CAL_DATA_SHIFT (0U)
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#define AON_GPADC_OS_CAL_DATA_MASK (0xffff << AON_GPADC_OS_CAL_DATA_SHIFT)
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#endif /* __HARDWARE_ADC_H__ */
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