mirror of
https://github.com/Fishwaldo/bl_mcu_sdk.git
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356f258e83
* use nuttx libc, disable system libc * use tlsf as default * update lhal flash driver * add example readme * add flash ini for new flash tool * add fw header for new flash tool
165 lines
7.1 KiB
C
165 lines
7.1 KiB
C
/**
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******************************************************************************
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* @file csi_reg.h
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* @version V1.0
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* @date 2022-12-13
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* @brief This file is the description of.IP register
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Bouffalo Lab nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#ifndef __HARDWARE_CSI_H__
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#define __HARDWARE_CSI_H__
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register offsets *********************************************************/
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#define CSI_MIPI_CONFIG_OFFSET (0x0)/* mipi_config */
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#define CSI_INT_STATUS_OFFSET (0x10)/* csi_int_status */
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#define CSI_INT_MASK_OFFSET (0x14)/* csi_int_mask */
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#define CSI_INT_CLEAR_OFFSET (0x18)/* csi_int_clear */
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#define CSI_INT_ENABLE_OFFSET (0x1C)/* csi_int_enable */
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#define CSI_GNR_BUF_STATUS_OFFSET (0x20)/* gnr_buf_status */
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#define CSI_GNR_BUF_RDATA_OFFSET (0x24)/* gnr_buf_rdata */
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#define CSI_DPHY_CONFIG_0_OFFSET (0x80)/* dphy_config_0 */
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#define CSI_DPHY_CONFIG_1_OFFSET (0x84)/* dphy_config_1 */
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#define CSI_DPHY_CONFIG_2_OFFSET (0x88)/* dphy_config_2 */
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#define CSI_DPHY_CONFIG_3_OFFSET (0x8C)/* dphy_config_3 */
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#define CSI_DPHY_CONFIG_4_OFFSET (0x90)/* dphy_config_4 */
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#define CSI_DPHY_CONFIG_5_OFFSET (0x94)/* dphy_config_5 */
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#define CSI_DUMMY_REG_OFFSET (0xFC)/* dummy_reg */
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/* Register Bitfield definitions *****************************************************/
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/* 0x0 : mipi_config */
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#define CSI_CR_CSI_EN (1<<0U)
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#define CSI_CR_LANE_NUM (1<<1U)
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#define CSI_CR_LANE_INV (1<<3U)
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#define CSI_CR_DATA_BIT_INV (1<<4U)
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#define CSI_CR_SYNC_SP_EN (1<<5U)
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#define CSI_CR_UNPACK_EN (1<<6U)
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#define CSI_CR_VC_DVP0_SHIFT (12U)
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#define CSI_CR_VC_DVP0_MASK (0x3<<CSI_CR_VC_DVP0_SHIFT)
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#define CSI_CR_VC_DVP1_SHIFT (14U)
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#define CSI_CR_VC_DVP1_MASK (0x3<<CSI_CR_VC_DVP1_SHIFT)
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/* 0x10 : csi_int_status */
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#define CSI_INT_STATUS_SHIFT (0U)
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#define CSI_INT_STATUS_MASK (0x3f<<CSI_INT_STATUS_SHIFT)
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/* 0x14 : csi_int_mask */
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#define CSI_INT_MASK_SHIFT (0U)
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#define CSI_INT_MASK_MASK (0x3f<<CSI_INT_MASK_SHIFT)
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/* 0x18 : csi_int_clear */
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#define CSI_INT_CLEAR_SHIFT (0U)
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#define CSI_INT_CLEAR_MASK (0x3f<<CSI_INT_CLEAR_SHIFT)
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/* 0x1C : csi_int_enable */
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#define CSI_INT_ENABLE_SHIFT (0U)
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#define CSI_INT_ENABLE_MASK (0x3f<<CSI_INT_ENABLE_SHIFT)
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/* 0x20 : gnr_buf_status */
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#define CSI_ST_GNR_FIFO_CNT_SHIFT (0U)
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#define CSI_ST_GNR_FIFO_CNT_MASK (0xf<<CSI_ST_GNR_FIFO_CNT_SHIFT)
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/* 0x24 : gnr_buf_rdata */
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#define CSI_GNR_BUF_RDATA_SHIFT (0U)
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#define CSI_GNR_BUF_RDATA_MASK (0xffffffff<<CSI_GNR_BUF_RDATA_SHIFT)
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/* 0x80 : dphy_config_0 */
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#define CSI_DL0_ENABLE (1<<0U)
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#define CSI_DL1_ENABLE (1<<1U)
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#define CSI_CL_ENABLE (1<<2U)
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#define CSI_DL0_STOPSTATE (1<<4U)
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#define CSI_DL1_STOPSTATE (1<<5U)
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#define CSI_CL_STOPSTATE (1<<6U)
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#define CSI_DL0_ULPSACTIVENOT (1<<8U)
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#define CSI_DL1_ULPSACTIVENOT (1<<9U)
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#define CSI_CL_ULPSACTIVENOT (1<<10U)
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#define CSI_DL0_FORCERXMODE (1<<12U)
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#define CSI_DL1_FORCERXMODE (1<<13U)
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#define CSI_CL_RXCLKACTIVEHS (1<<14U)
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#define CSI_CL_RXULPSCLKNOT (1<<15U)
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#define CSI_RESET_N (1<<31U)
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/* 0x84 : dphy_config_1 */
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#define CSI_REG_TIME_CK_SETTLE_SHIFT (0U)
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#define CSI_REG_TIME_CK_SETTLE_MASK (0xff<<CSI_REG_TIME_CK_SETTLE_SHIFT)
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#define CSI_REG_TIME_CK_TERM_EN_SHIFT (8U)
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#define CSI_REG_TIME_CK_TERM_EN_MASK (0xff<<CSI_REG_TIME_CK_TERM_EN_SHIFT)
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#define CSI_REG_TIME_HS_SETTLE_SHIFT (16U)
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#define CSI_REG_TIME_HS_SETTLE_MASK (0xff<<CSI_REG_TIME_HS_SETTLE_SHIFT)
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#define CSI_REG_TIME_HS_TERM_EN_SHIFT (24U)
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#define CSI_REG_TIME_HS_TERM_EN_MASK (0xff<<CSI_REG_TIME_HS_TERM_EN_SHIFT)
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/* 0x88 : dphy_config_2 */
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#define CSI_REG_ANA_LPRXEN_CLK (1<<0U)
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#define CSI_REG_ANA_HSRXEN_CLK (1<<1U)
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#define CSI_REG_ANA_HSRX_STOP_STATE_SHIFT (2U)
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#define CSI_REG_ANA_HSRX_STOP_STATE_MASK (0x3<<CSI_REG_ANA_HSRX_STOP_STATE_SHIFT)
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#define CSI_REG_ANA_HSRX_SYNC_EN_SHIFT (4U)
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#define CSI_REG_ANA_HSRX_SYNC_EN_MASK (0x3<<CSI_REG_ANA_HSRX_SYNC_EN_SHIFT)
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#define CSI_REG_ANA_LPRXEN_SHIFT (6U)
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#define CSI_REG_ANA_LPRXEN_MASK (0x3<<CSI_REG_ANA_LPRXEN_SHIFT)
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#define CSI_REG_ANA_HSRXEN_SHIFT (8U)
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#define CSI_REG_ANA_HSRXEN_MASK (0x3<<CSI_REG_ANA_HSRXEN_SHIFT)
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#define CSI_REG_ANA_TERM_EN_SHIFT (10U)
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#define CSI_REG_ANA_TERM_EN_MASK (0x1f<<CSI_REG_ANA_TERM_EN_SHIFT)
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#define CSI_REG_ANA_TEST_EN (1<<15U)
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#define CSI_REG_PT_LOCK_COUNTER_SHIFT (16U)
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#define CSI_REG_PT_LOCK_COUNTER_MASK (0xf<<CSI_REG_PT_LOCK_COUNTER_SHIFT)
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#define CSI_REG_PT_PRBS_OR_JITT (1<<20U)
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#define CSI_REG_PT_LP_MODE (1<<21U)
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#define CSI_REG_PT_EN (1<<22U)
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#define CSI_REG_PT_LOCK (1<<23U)
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#define CSI_REG_PT_PASS (1<<24U)
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/* 0x8C : dphy_config_3 */
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#define CSI_REG_CSI_ANA_1_SHIFT (0U)
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#define CSI_REG_CSI_ANA_1_MASK (0xffff<<CSI_REG_CSI_ANA_1_SHIFT)
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#define CSI_REG_CSI_ANA_0_SHIFT (16U)
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#define CSI_REG_CSI_ANA_0_MASK (0xffff<<CSI_REG_CSI_ANA_0_SHIFT)
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/* 0x90 : dphy_config_4 */
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#define CSI_REG_CSI_DC_TP_OUT_EN (1<<0U)
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#define CSI_REG_CSI_PW_AVDD1815 (1<<4U)
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/* 0x94 : dphy_config_5 */
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#define CSI_REG_CSI_BYTE_CLK_INV (1<<0U)
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#define CSI_REG_CSI_DDR_CLK_INV (1<<1U)
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/* 0xFC : dummy_reg */
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#define CSI_DUMMY_REG_SHIFT (0U)
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#define CSI_DUMMY_REG_MASK (0xffffffff<<CSI_DUMMY_REG_SHIFT)
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#endif /* __HARDWARE_CSI_H__ */
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