mirror of
https://github.com/Fishwaldo/bl_mcu_sdk.git
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356f258e83
* use nuttx libc, disable system libc * use tlsf as default * update lhal flash driver * add example readme * add flash ini for new flash tool * add fw header for new flash tool
135 lines
5.8 KiB
C
135 lines
5.8 KiB
C
/**
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******************************************************************************
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* @file i2s_reg.h
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* @version V1.0
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* @date 2023-01-03
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* @brief This file is the description of.IP register
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Bouffalo Lab nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#ifndef __I2S_REG_H__
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#define __I2S_REG_H__
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register offsets *********************************************************/
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#define I2S_CONFIG_OFFSET (0x0) /* i2s_config */
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#define I2S_INT_STS_OFFSET (0x4) /* i2s_int_sts */
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#define I2S_BCLK_CONFIG_OFFSET (0x10) /* i2s_bclk_config */
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#define I2S_FIFO_CONFIG_0_OFFSET (0x80) /* i2s_fifo_config_0 */
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#define I2S_FIFO_CONFIG_1_OFFSET (0x84) /* i2s_fifo_config_1 */
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#define I2S_FIFO_WDATA_OFFSET (0x88) /* i2s_fifo_wdata */
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#define I2S_FIFO_RDATA_OFFSET (0x8C) /* i2s_fifo_rdata */
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#define I2S_IO_CONFIG_OFFSET (0xFC) /* i2s_io_config */
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/* Register Bitfield definitions *****************************************************/
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/* 0x0 : i2s_config */
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#define I2S_CR_I2S_M_EN (1 << 0U)
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#define I2S_CR_I2S_S_EN (1 << 1U)
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#define I2S_CR_I2S_TXD_EN (1 << 2U)
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#define I2S_CR_I2S_RXD_EN (1 << 3U)
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#define I2S_CR_MONO_MODE (1 << 4U)
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#define I2S_CR_MUTE_MODE (1 << 5U)
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#define I2S_CR_FS_1T_MODE (1 << 6U)
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#define I2S_CR_FS_CH_CNT_SHIFT (7U)
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#define I2S_CR_FS_CH_CNT_MASK (0x3 << I2S_CR_FS_CH_CNT_SHIFT)
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#define I2S_CR_FRAME_SIZE_SHIFT (12U)
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#define I2S_CR_FRAME_SIZE_MASK (0x3 << I2S_CR_FRAME_SIZE_SHIFT)
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#define I2S_CR_DATA_SIZE_SHIFT (14U)
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#define I2S_CR_DATA_SIZE_MASK (0x3 << I2S_CR_DATA_SIZE_SHIFT)
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#define I2S_CR_I2S_MODE_SHIFT (16U)
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#define I2S_CR_I2S_MODE_MASK (0x3 << I2S_CR_I2S_MODE_SHIFT)
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#define I2S_CR_ENDIAN (1 << 18U)
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#define I2S_CR_MONO_RX_CH (1 << 19U)
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#define I2S_CR_OFS_CNT_SHIFT (20U)
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#define I2S_CR_OFS_CNT_MASK (0x1f << I2S_CR_OFS_CNT_SHIFT)
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#define I2S_CR_OFS_EN (1 << 25U)
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/* 0x4 : i2s_int_sts */
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#define I2S_TXF_INT (1 << 0U)
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#define I2S_RXF_INT (1 << 1U)
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#define I2S_FER_INT (1 << 2U)
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#define I2S_CR_I2S_TXF_MASK (1 << 8U)
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#define I2S_CR_I2S_RXF_MASK (1 << 9U)
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#define I2S_CR_I2S_FER_MASK (1 << 10U)
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#define I2S_CR_I2S_TXF_EN (1 << 24U)
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#define I2S_CR_I2S_RXF_EN (1 << 25U)
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#define I2S_CR_I2S_FER_EN (1 << 26U)
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/* 0x10 : i2s_bclk_config */
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#define I2S_CR_BCLK_DIV_L_SHIFT (0U)
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#define I2S_CR_BCLK_DIV_L_MASK (0xfff << I2S_CR_BCLK_DIV_L_SHIFT)
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#define I2S_CR_BCLK_DIV_H_SHIFT (16U)
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#define I2S_CR_BCLK_DIV_H_MASK (0xfff << I2S_CR_BCLK_DIV_H_SHIFT)
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/* 0x80 : i2s_fifo_config_0 */
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#define I2S_DMA_TX_EN (1 << 0U)
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#define I2S_DMA_RX_EN (1 << 1U)
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#define I2S_TX_FIFO_CLR (1 << 2U)
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#define I2S_RX_FIFO_CLR (1 << 3U)
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#define I2S_TX_FIFO_OVERFLOW (1 << 4U)
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#define I2S_TX_FIFO_UNDERFLOW (1 << 5U)
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#define I2S_RX_FIFO_OVERFLOW (1 << 6U)
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#define I2S_RX_FIFO_UNDERFLOW (1 << 7U)
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#define I2S_CR_FIFO_LR_MERGE (1 << 8U)
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#define I2S_CR_FIFO_LR_EXCHG (1 << 9U)
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#define I2S_CR_FIFO_24B_LJ (1 << 10U)
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/* 0x84 : i2s_fifo_config_1 */
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#define I2S_TX_FIFO_CNT_SHIFT (0U)
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#define I2S_TX_FIFO_CNT_MASK (0x1f << I2S_TX_FIFO_CNT_SHIFT)
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#define I2S_RX_FIFO_CNT_SHIFT (8U)
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#define I2S_RX_FIFO_CNT_MASK (0x1f << I2S_RX_FIFO_CNT_SHIFT)
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#define I2S_TX_FIFO_TH_SHIFT (16U)
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#define I2S_TX_FIFO_TH_MASK (0xf << I2S_TX_FIFO_TH_SHIFT)
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#define I2S_RX_FIFO_TH_SHIFT (24U)
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#define I2S_RX_FIFO_TH_MASK (0xf << I2S_RX_FIFO_TH_SHIFT)
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/* 0x88 : i2s_fifo_wdata */
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#define I2S_FIFO_WDATA_SHIFT (0U)
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#define I2S_FIFO_WDATA_MASK (0xffffffff << I2S_FIFO_WDATA_SHIFT)
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/* 0x8C : i2s_fifo_rdata */
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#define I2S_FIFO_RDATA_SHIFT (0U)
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#define I2S_FIFO_RDATA_MASK (0xffffffff << I2S_FIFO_RDATA_SHIFT)
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/* 0xFC : i2s_io_config */
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#define I2S_CR_I2S_TXD_INV (1 << 0U)
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#define I2S_CR_I2S_RXD_INV (1 << 1U)
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#define I2S_CR_I2S_FS_INV (1 << 2U)
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#define I2S_CR_I2S_BCLK_INV (1 << 3U)
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#define I2S_CR_DEG_CNT_SHIFT (4U)
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#define I2S_CR_DEG_CNT_MASK (0x7 << I2S_CR_DEG_CNT_SHIFT)
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#define I2S_CR_DEG_EN (1 << 7U)
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#endif /* __I2S_REG_H__ */
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