mirror of
https://github.com/Fishwaldo/bl_mcu_sdk.git
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370 lines
14 KiB
C
370 lines
14 KiB
C
/**
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******************************************************************************
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* @file uart_reg.h
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* @version V1.0
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* @date 2022-06-10
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* @brief This file is the description of.IP register
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Bouffalo Lab nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#ifndef __HARDWARE_UART_H__
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#define __HARDWARE_UART_H__
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register offsets *********************************************************/
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#define UART_UTX_CONFIG_OFFSET (0x0) /* utx_config */
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#define UART_URX_CONFIG_OFFSET (0x4) /* urx_config */
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#define UART_BIT_PRD_OFFSET (0x8) /* uart_bit_prd */
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#define UART_DATA_CONFIG_OFFSET (0xC) /* data_config */
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#if !defined(BL702L)
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#define UART_UTX_IR_POSITION_OFFSET (0x10) /* utx_ir_position */
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#define UART_URX_IR_POSITION_OFFSET (0x14) /* urx_ir_position */
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#endif
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#define UART_URX_RTO_TIMER_OFFSET (0x18) /* urx_rto_timer */
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#if !defined(BL602)
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#define UART_SW_MODE_OFFSET (0x1C) /* uart_sw_mode */
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#endif
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#define UART_INT_STS_OFFSET (0x20) /* UART interrupt status */
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#define UART_INT_MASK_OFFSET (0x24) /* UART interrupt mask */
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#define UART_INT_CLEAR_OFFSET (0x28) /* UART interrupt clear */
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#define UART_INT_EN_OFFSET (0x2C) /* UART interrupt enable */
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#define UART_STATUS_OFFSET (0x30) /* uart_status */
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#define UART_STS_URX_ABR_PRD_OFFSET (0x34) /* sts_urx_abr_prd */
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#if !defined(BL602) && !defined(BL702)
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#define UART_URX_ABR_PRD_B01_OFFSET (0x38) /* urx_abr_prd_b01 */
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#define UART_URX_ABR_PRD_B23_OFFSET (0x3C) /* urx_abr_prd_b23 */
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#define UART_URX_ABR_PRD_B45_OFFSET (0x40) /* urx_abr_prd_b45 */
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#define UART_URX_ABR_PRD_B67_OFFSET (0x44) /* urx_abr_prd_b67 */
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#define UART_URX_ABR_PW_TOL_OFFSET (0x48) /* urx_abr_pw_tol */
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#define UART_URX_BCR_INT_CFG_OFFSET (0x50) /* urx_bcr_int_cfg */
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#define UART_UTX_RS485_CFG_OFFSET (0x54) /* utx_rs485_cfg */
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#endif
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#define UART_FIFO_CONFIG_0_OFFSET (0x80) /* uart_fifo_config_0 */
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#define UART_FIFO_CONFIG_1_OFFSET (0x84) /* uart_fifo_config_1 */
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#define UART_FIFO_WDATA_OFFSET (0x88) /* uart_fifo_wdata */
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#define UART_FIFO_RDATA_OFFSET (0x8C) /* uart_fifo_rdata */
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/* Register Bitfield definitions *****************************************************/
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/* 0x0 : utx_config */
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#define UART_CR_UTX_EN (1 << 0U)
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#define UART_CR_UTX_CTS_EN (1 << 1U)
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#define UART_CR_UTX_FRM_EN (1 << 2U)
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#if !defined(BL602)
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#define UART_CR_UTX_LIN_EN (1 << 3U)
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#endif
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#define UART_CR_UTX_PRT_EN (1 << 4U)
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#define UART_CR_UTX_PRT_SEL (1 << 5U)
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#if !defined(BL702L)
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#define UART_CR_UTX_IR_EN (1 << 6U)
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#define UART_CR_UTX_IR_INV (1 << 7U)
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#endif
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#define UART_CR_UTX_BIT_CNT_D_SHIFT (8U)
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#define UART_CR_UTX_BIT_CNT_D_MASK (0x7 << UART_CR_UTX_BIT_CNT_D_SHIFT)
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#if defined(BL602)
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#define UART_CR_UTX_BIT_CNT_P_SHIFT (12U)
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#else
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#define UART_CR_UTX_BIT_CNT_P_SHIFT (11U)
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#endif
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#define UART_CR_UTX_BIT_CNT_P_MASK (0x3 << UART_CR_UTX_BIT_CNT_P_SHIFT)
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#if !defined(BL602)
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#define UART_CR_UTX_BIT_CNT_B_SHIFT (13U)
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#define UART_CR_UTX_BIT_CNT_B_MASK (0x7 << UART_CR_UTX_BIT_CNT_B_SHIFT)
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#endif
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#define UART_CR_UTX_LEN_SHIFT (16U)
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#define UART_CR_UTX_LEN_MASK (0xffff << UART_CR_UTX_LEN_SHIFT)
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/* 0x4 : urx_config */
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#define UART_CR_URX_EN (1 << 0U)
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#if defined(BL602)
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#define UART_CR_URX_RTS_SW_MODE (1 << 1U)
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#define UART_CR_URX_RTS_SW_VAL (1 << 2U)
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#define UART_CR_URX_ABR_EN (1 << 3U)
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#else
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#define UART_CR_URX_ABR_EN (1 << 1U)
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#define UART_CR_URX_LIN_EN (1 << 3U)
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#endif
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#define UART_CR_URX_PRT_EN (1 << 4U)
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#define UART_CR_URX_PRT_SEL (1 << 5U)
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#if !defined(BL702L)
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#define UART_CR_URX_IR_EN (1 << 6U)
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#define UART_CR_URX_IR_INV (1 << 7U)
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#endif
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#define UART_CR_URX_BIT_CNT_D_SHIFT (8U)
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#define UART_CR_URX_BIT_CNT_D_MASK (0x7 << UART_CR_URX_BIT_CNT_D_SHIFT)
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#define UART_CR_URX_DEG_EN (1 << 11U)
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#define UART_CR_URX_DEG_CNT_SHIFT (12U)
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#define UART_CR_URX_DEG_CNT_MASK (0xf << UART_CR_URX_DEG_CNT_SHIFT)
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#define UART_CR_URX_LEN_SHIFT (16U)
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#define UART_CR_URX_LEN_MASK (0xffff << UART_CR_URX_LEN_SHIFT)
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/* 0x8 : uart_bit_prd */
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#define UART_CR_UTX_BIT_PRD_SHIFT (0U)
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#define UART_CR_UTX_BIT_PRD_MASK (0xffff << UART_CR_UTX_BIT_PRD_SHIFT)
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#define UART_CR_URX_BIT_PRD_SHIFT (16U)
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#define UART_CR_URX_BIT_PRD_MASK (0xffff << UART_CR_URX_BIT_PRD_SHIFT)
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/* 0xC : data_config */
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#define UART_CR_UART_BIT_INV (1 << 0U)
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#if !defined(BL702L)
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/* 0x10 : utx_ir_position */
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#define UART_CR_UTX_IR_POS_S_SHIFT (0U)
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#define UART_CR_UTX_IR_POS_S_MASK (0xffff << UART_CR_UTX_IR_POS_S_SHIFT)
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#define UART_CR_UTX_IR_POS_P_SHIFT (16U)
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#define UART_CR_UTX_IR_POS_P_MASK (0xffff << UART_CR_UTX_IR_POS_P_SHIFT)
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/* 0x14 : urx_ir_position */
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#define UART_CR_URX_IR_POS_S_SHIFT (0U)
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#define UART_CR_URX_IR_POS_S_MASK (0xffff << UART_CR_URX_IR_POS_S_SHIFT)
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#endif
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/* 0x18 : urx_rto_timer */
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#define UART_CR_URX_RTO_VALUE_SHIFT (0U)
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#define UART_CR_URX_RTO_VALUE_MASK (0xff << UART_CR_URX_RTO_VALUE_SHIFT)
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#if !defined(BL602)
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/* 0x1C : uart_sw_mode */
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#define UART_CR_UTX_TXD_SW_MODE (1 << 0U)
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#define UART_CR_UTX_TXD_SW_VAL (1 << 1U)
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#define UART_CR_URX_RTS_SW_MODE (1 << 2U)
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#define UART_CR_URX_RTS_SW_VAL (1 << 3U)
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#endif
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/* 0x20 : UART interrupt status */
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#define UART_UTX_END_INT (1 << 0U)
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#define UART_URX_END_INT (1 << 1U)
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#define UART_UTX_FIFO_INT (1 << 2U)
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#define UART_URX_FIFO_INT (1 << 3U)
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#define UART_URX_RTO_INT (1 << 4U)
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#define UART_URX_PCE_INT (1 << 5U)
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#define UART_UTX_FER_INT (1 << 6U)
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#define UART_URX_FER_INT (1 << 7U)
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#if !defined(BL602)
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#define UART_URX_LSE_INT (1 << 8U)
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#endif
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#if !defined(BL602) && !defined(BL702)
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#define UART_URX_BCR_INT (1 << 9U)
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#define UART_URX_ADS_INT (1 << 10U)
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#define UART_URX_AD5_INT (1 << 11U)
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#endif
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/* 0x24 : UART interrupt mask */
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#define UART_CR_UTX_END_MASK (1 << 0U)
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#define UART_CR_URX_END_MASK (1 << 1U)
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#define UART_CR_UTX_FIFO_MASK (1 << 2U)
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#define UART_CR_URX_FIFO_MASK (1 << 3U)
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#define UART_CR_URX_RTO_MASK (1 << 4U)
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#define UART_CR_URX_PCE_MASK (1 << 5U)
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#define UART_CR_UTX_FER_MASK (1 << 6U)
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#define UART_CR_URX_FER_MASK (1 << 7U)
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#if !defined(BL602)
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#define UART_CR_URX_LSE_MASK (1 << 8U)
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#endif
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#if !defined(BL602) && !defined(BL702)
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#define UART_CR_URX_BCR_MASK (1 << 9U)
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#define UART_CR_URX_ADS_MASK (1 << 10U)
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#define UART_CR_URX_AD5_MASK (1 << 11U)
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#endif
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/* 0x28 : UART interrupt clear */
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#define UART_CR_UTX_END_CLR (1 << 0U)
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#define UART_CR_URX_END_CLR (1 << 1U)
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#define UART_CR_URX_RTO_CLR (1 << 4U)
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#define UART_CR_URX_PCE_CLR (1 << 5U)
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#if !defined(BL602)
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#define UART_CR_URX_LSE_CLR (1 << 8U)
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#endif
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#if !defined(BL602) && !defined(BL702)
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#define UART_CR_URX_BCR_CLR (1 << 9U)
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#define UART_CR_URX_ADS_CLR (1 << 10U)
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#define UART_CR_URX_AD5_CLR (1 << 11U)
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#endif
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/* 0x2C : UART interrupt enable */
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#define UART_CR_UTX_END_EN (1 << 0U)
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#define UART_CR_URX_END_EN (1 << 1U)
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#define UART_CR_UTX_FIFO_EN (1 << 2U)
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#define UART_CR_URX_FIFO_EN (1 << 3U)
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#define UART_CR_URX_RTO_EN (1 << 4U)
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#define UART_CR_URX_PCE_EN (1 << 5U)
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#define UART_CR_UTX_FER_EN (1 << 6U)
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#define UART_CR_URX_FER_EN (1 << 7U)
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#if !defined(BL602)
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#define UART_CR_URX_LSE_EN (1 << 8U)
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#endif
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#if !defined(BL602) && !defined(BL702)
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#define UART_CR_URX_BCR_EN (1 << 9U)
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#define UART_CR_URX_ADS_EN (1 << 10U)
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#define UART_CR_URX_AD5_EN (1 << 11U)
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#endif
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/* 0x30 : uart_status */
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#define UART_STS_UTX_BUS_BUSY (1 << 0U)
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#define UART_STS_URX_BUS_BUSY (1 << 1U)
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/* 0x34 : sts_urx_abr_prd */
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#define UART_STS_URX_ABR_PRD_START_SHIFT (0U)
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#define UART_STS_URX_ABR_PRD_START_MASK (0xffff << UART_STS_URX_ABR_PRD_START_SHIFT)
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#define UART_STS_URX_ABR_PRD_0X55_SHIFT (16U)
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#if defined(BL702L)
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#define UART_STS_URX_ABR_PRD_0X55_MASK (0x3ff << UART_STS_URX_ABR_PRD_0X55_SHIFT)
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#else
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#define UART_STS_URX_ABR_PRD_0X55_MASK (0xffff << UART_STS_URX_ABR_PRD_0X55_SHIFT)
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#endif
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#if !defined(BL602) && !defined(BL702)
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/* 0x38 : urx_abr_prd_b01 */
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#define UART_STS_URX_ABR_PRD_BIT0_SHIFT (0U)
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#if defined(BL702L)
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#define UART_STS_URX_ABR_PRD_BIT0_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT0_SHIFT)
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#else
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#define UART_STS_URX_ABR_PRD_BIT0_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT0_SHIFT)
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#endif
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#define UART_STS_URX_ABR_PRD_BIT1_SHIFT (16U)
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#if defined(BL702L)
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#define UART_STS_URX_ABR_PRD_BIT1_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT1_SHIFT)
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#else
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#define UART_STS_URX_ABR_PRD_BIT1_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT1_SHIFT)
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#endif
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/* 0x3C : urx_abr_prd_b23 */
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#define UART_STS_URX_ABR_PRD_BIT2_SHIFT (0U)
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#if defined(BL702L)
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#define UART_STS_URX_ABR_PRD_BIT2_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT2_SHIFT)
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#else
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#define UART_STS_URX_ABR_PRD_BIT2_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT2_SHIFT)
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#endif
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#define UART_STS_URX_ABR_PRD_BIT3_SHIFT (16U)
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#if defined(BL702L)
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#define UART_STS_URX_ABR_PRD_BIT3_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT3_SHIFT)
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#else
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#define UART_STS_URX_ABR_PRD_BIT3_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT3_SHIFT)
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#endif
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/* 0x40 : urx_abr_prd_b45 */
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#define UART_STS_URX_ABR_PRD_BIT4_SHIFT (0U)
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#if defined(BL702L)
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#define UART_STS_URX_ABR_PRD_BIT4_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT4_SHIFT)
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#else
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#define UART_STS_URX_ABR_PRD_BIT4_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT4_SHIFT)
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#endif
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#define UART_STS_URX_ABR_PRD_BIT5_SHIFT (16U)
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#if defined(BL702L)
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#define UART_STS_URX_ABR_PRD_BIT5_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT5_SHIFT)
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#else
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#define UART_STS_URX_ABR_PRD_BIT5_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT5_SHIFT)
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#endif
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/* 0x44 : urx_abr_prd_b67 */
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#define UART_STS_URX_ABR_PRD_BIT6_SHIFT (0U)
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#if defined(BL702L)
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#define UART_STS_URX_ABR_PRD_BIT6_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT6_SHIFT)
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#else
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#define UART_STS_URX_ABR_PRD_BIT6_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT6_SHIFT)
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#endif
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#define UART_STS_URX_ABR_PRD_BIT7_SHIFT (16U)
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#if defined(BL702L)
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#define UART_STS_URX_ABR_PRD_BIT7_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT7_SHIFT)
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#else
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#define UART_STS_URX_ABR_PRD_BIT7_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT7_SHIFT)
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#endif
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/* 0x48 : urx_abr_pw_tol */
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#define UART_CR_URX_ABR_PW_TOL_SHIFT (0U)
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#define UART_CR_URX_ABR_PW_TOL_MASK (0xff << UART_CR_URX_ABR_PW_TOL_SHIFT)
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/* 0x50 : urx_bcr_int_cfg */
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#define UART_CR_URX_BCR_VALUE_SHIFT (0U)
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#define UART_CR_URX_BCR_VALUE_MASK (0xffff << UART_CR_URX_BCR_VALUE_SHIFT)
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#define UART_STS_URX_BCR_COUNT_SHIFT (16U)
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#define UART_STS_URX_BCR_COUNT_MASK (0xffff << UART_STS_URX_BCR_COUNT_SHIFT)
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/* 0x54 : utx_rs485_cfg */
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#define UART_CR_UTX_RS485_EN (1 << 0U)
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#define UART_CR_UTX_RS485_POL (1 << 1U)
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#endif
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/* 0x80 : uart_fifo_config_0 */
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#define UART_DMA_TX_EN (1 << 0U)
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#define UART_DMA_RX_EN (1 << 1U)
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#define UART_TX_FIFO_CLR (1 << 2U)
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#define UART_RX_FIFO_CLR (1 << 3U)
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#define UART_TX_FIFO_OVERFLOW (1 << 4U)
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#define UART_TX_FIFO_UNDERFLOW (1 << 5U)
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#define UART_RX_FIFO_OVERFLOW (1 << 6U)
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#define UART_RX_FIFO_UNDERFLOW (1 << 7U)
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/* 0x84 : uart_fifo_config_1 */
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#define UART_TX_FIFO_CNT_SHIFT (0U)
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#if defined(BL702)
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#define UART_TX_FIFO_CNT_MASK (0xff << UART_TX_FIFO_CNT_SHIFT)
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#elif defined(BL702L)
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#define UART_TX_FIFO_CNT_MASK (0x1f << UART_TX_FIFO_CNT_SHIFT)
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#else
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#define UART_TX_FIFO_CNT_MASK (0x3f << UART_TX_FIFO_CNT_SHIFT)
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#endif
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#define UART_RX_FIFO_CNT_SHIFT (8U)
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#if defined(BL702)
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#define UART_RX_FIFO_CNT_MASK (0xff << UART_RX_FIFO_CNT_SHIFT)
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#elif defined(BL702L)
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#define UART_RX_FIFO_CNT_MASK (0x1f << UART_RX_FIFO_CNT_SHIFT)
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#else
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#define UART_RX_FIFO_CNT_MASK (0x3f << UART_RX_FIFO_CNT_SHIFT)
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#endif
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#define UART_TX_FIFO_TH_SHIFT (16U)
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#if defined(BL702)
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#define UART_TX_FIFO_TH_MASK (0x7f << UART_TX_FIFO_TH_SHIFT)
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#elif defined(BL702L)
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#define UART_TX_FIFO_TH_MASK (0xf << UART_TX_FIFO_TH_SHIFT)
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#else
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#define UART_TX_FIFO_TH_MASK (0x1f << UART_TX_FIFO_TH_SHIFT)
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#endif
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#define UART_RX_FIFO_TH_SHIFT (24U)
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#if defined(BL702)
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#define UART_RX_FIFO_TH_MASK (0x7f << UART_RX_FIFO_TH_SHIFT)
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#elif defined(BL702L)
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#define UART_RX_FIFO_TH_MASK (0xf << UART_RX_FIFO_TH_SHIFT)
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#else
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#define UART_RX_FIFO_TH_MASK (0x1f << UART_RX_FIFO_TH_SHIFT)
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#endif
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/* 0x88 : uart_fifo_wdata */
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#define UART_FIFO_WDATA_SHIFT (0U)
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#define UART_FIFO_WDATA_MASK (0xff << UART_FIFO_WDATA_SHIFT)
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/* 0x8C : uart_fifo_rdata */
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#define UART_FIFO_RDATA_SHIFT (0U)
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#define UART_FIFO_RDATA_MASK (0xff << UART_FIFO_RDATA_SHIFT)
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#endif /* __HARDWARE_UART_H__ */
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