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https://github.com/Fishwaldo/bl_mcu_sdk.git
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167 lines
7.6 KiB
C
167 lines
7.6 KiB
C
/**
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******************************************************************************
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* @file audac_reg.h
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* @version V1.0
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* @date 2022-12-03
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* @brief This file is the description of.IP register
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Bouffalo Lab nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#ifndef __AUDAC_REG_H__
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#define __AUDAC_REG_H__
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register offsets *********************************************************/
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#define AUDAC_0_OFFSET (0x000) /* audac_0 */
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#define AUDAC_STATUS_OFFSET (0x4) /* audac_status */
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#define AUDAC_S0_OFFSET (0x8) /* audac_s0 */
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#define AUDAC_S0_MISC_OFFSET (0xC) /* audac_s0_misc */
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#define AUDAC_ZD_0_OFFSET (0x10) /* audac_zd_0 */
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#define AUDAC_1_OFFSET (0x14) /* audac_1 */
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#define AUDAC_RSVD_OFFSET (0x18) /* audac_rsvd */
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#define AUDAC_TEST_0_OFFSET (0x1C) /* audac_test_0 */
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#define AUDAC_TEST_1_OFFSET (0x20) /* audac_test_1 */
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#define AUDAC_TEST_2_OFFSET (0x24) /* audac_test_2 */
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#define AUDAC_TEST_3_OFFSET (0x28) /* audac_test_3 */
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#define AUDAC_FIFO_CTRL_OFFSET (0x8C) /* audac_fifo_ctrl */
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#define AUDAC_FIFO_STATUS_OFFSET (0x90) /* audac_fifo_status */
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#define AUDAC_FIFO_DATA_OFFSET (0x94) /* audac_fifo_data */
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/* Register Bitfield definitions *****************************************************/
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/* 0x000 : audac_0 */
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#define AUDAC_DAC_0_EN (1 << 0U)
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#define AUDAC_DAC_ITF_EN (1 << 1U)
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#define AUDAC_CKG_ENA (1 << 27U)
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#define AUDAC_AU_PWM_MODE_SHIFT (28U)
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#define AUDAC_AU_PWM_MODE_MASK (0xf << AUDAC_AU_PWM_MODE_SHIFT)
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/* 0x4 : audac_status */
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#define AUDAC_DAC_H0_BUSY (1 << 12U)
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#define AUDAC_DAC_H0_MUTE_DONE (1 << 13U)
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#define AUDAC_DAC_S0_INT (1 << 16U)
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#define AUDAC_DAC_S0_INT_CLR (1 << 17U)
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#define AUDAC_ZD_AMUTE (1 << 23U)
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#define AUDAC_AUDIO_INT_ALL (1 << 24U)
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/* 0x8 : audac_s0 */
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#define AUDAC_DAC_S0_CTRL_RMP_RATE_SHIFT (2U)
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#define AUDAC_DAC_S0_CTRL_RMP_RATE_MASK (0xf << AUDAC_DAC_S0_CTRL_RMP_RATE_SHIFT)
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#define AUDAC_DAC_S0_CTRL_ZCD_RATE_SHIFT (6U)
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#define AUDAC_DAC_S0_CTRL_ZCD_RATE_MASK (0xf << AUDAC_DAC_S0_CTRL_ZCD_RATE_SHIFT)
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#define AUDAC_DAC_S0_CTRL_MODE_SHIFT (10U)
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#define AUDAC_DAC_S0_CTRL_MODE_MASK (0x3 << AUDAC_DAC_S0_CTRL_MODE_SHIFT)
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#define AUDAC_DAC_S0_VOLUME_UPDATE (1 << 12U)
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#define AUDAC_DAC_S0_VOLUME_SHIFT (13U)
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#define AUDAC_DAC_S0_VOLUME_MASK (0x1ff << AUDAC_DAC_S0_VOLUME_SHIFT)
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#define AUDAC_DAC_S0_MUTE_RMPUP_RATE_SHIFT (22U)
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#define AUDAC_DAC_S0_MUTE_RMPUP_RATE_MASK (0xf << AUDAC_DAC_S0_MUTE_RMPUP_RATE_SHIFT)
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#define AUDAC_DAC_S0_MUTE_RMPDN_RATE_SHIFT (26U)
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#define AUDAC_DAC_S0_MUTE_RMPDN_RATE_MASK (0xf << AUDAC_DAC_S0_MUTE_RMPDN_RATE_SHIFT)
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#define AUDAC_DAC_S0_MUTE_SOFTMODE (1 << 30U)
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#define AUDAC_DAC_S0_MUTE (1 << 31U)
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/* 0xC : audac_s0_misc */
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#define AUDAC_DAC_S0_CTRL_ZCD_TIMEOUT_SHIFT (28U)
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#define AUDAC_DAC_S0_CTRL_ZCD_TIMEOUT_MASK (0xf << AUDAC_DAC_S0_CTRL_ZCD_TIMEOUT_SHIFT)
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/* 0x10 : audac_zd_0 */
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#define AUDAC_ZD_TIME_SHIFT (0U)
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#define AUDAC_ZD_TIME_MASK (0x7fff << AUDAC_ZD_TIME_SHIFT)
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#define AUDAC_ZD_EN (1 << 16U)
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/* 0x14 : audac_1 */
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#define AUDAC_DAC_MIX_SEL_SHIFT (0U)
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#define AUDAC_DAC_MIX_SEL_MASK (0x3 << AUDAC_DAC_MIX_SEL_SHIFT)
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#define AUDAC_DAC_DSM_OUT_FMT (1 << 4U)
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#define AUDAC_DAC_DSM_ORDER_SHIFT (5U)
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#define AUDAC_DAC_DSM_ORDER_MASK (0x3 << AUDAC_DAC_DSM_ORDER_SHIFT)
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#define AUDAC_DAC_DSM_SCALING_MODE_SHIFT (7U)
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#define AUDAC_DAC_DSM_SCALING_MODE_MASK (0x3 << AUDAC_DAC_DSM_SCALING_MODE_SHIFT)
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#define AUDAC_DAC_DSM_SCALING_EN (1 << 10U)
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#define AUDAC_DAC_DSM_DITHER_AMP_SHIFT (11U)
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#define AUDAC_DAC_DSM_DITHER_AMP_MASK (0x7 << AUDAC_DAC_DSM_DITHER_AMP_SHIFT)
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#define AUDAC_DAC_DSM_DITHER_EN (1 << 14U)
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#define AUDAC_DAC_DSM_DITHER_PRBS_MODE_SHIFT (15U)
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#define AUDAC_DAC_DSM_DITHER_PRBS_MODE_MASK (0x3 << AUDAC_DAC_DSM_DITHER_PRBS_MODE_SHIFT)
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/* 0x18 : audac_rsvd */
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#define AUDAC_AU_PWM_RESERVED_SHIFT (0U)
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#define AUDAC_AU_PWM_RESERVED_MASK (0xffffffff << AUDAC_AU_PWM_RESERVED_SHIFT)
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/* 0x1C : audac_test_0 */
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#define AUDAC_DAC_IN_0_SHIFT (0U)
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#define AUDAC_DAC_IN_0_MASK (0xffff << AUDAC_DAC_IN_0_SHIFT)
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#define AUDAC_DAC_DPGA_0_SHIFT (16U)
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#define AUDAC_DAC_DPGA_0_MASK (0xffff << AUDAC_DAC_DPGA_0_SHIFT)
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/* 0x20 : audac_test_1 */
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#define AUDAC_DAC_FIR_0_SHIFT (0U)
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#define AUDAC_DAC_FIR_0_MASK (0x1ffff << AUDAC_DAC_FIR_0_SHIFT)
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/* 0x24 : audac_test_2 */
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#define AUDAC_DAC_SINC_0_SHIFT (0U)
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#define AUDAC_DAC_SINC_0_MASK (0xffff << AUDAC_DAC_SINC_0_SHIFT)
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/* 0x28 : audac_test_3 */
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#define AUDAC_AU_PWM_TEST_READ_SHIFT (0U)
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#define AUDAC_AU_PWM_TEST_READ_MASK (0xffffffff << AUDAC_AU_PWM_TEST_READ_SHIFT)
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/* 0x8C : audac_fifo_ctrl */
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#define AUDAC_TX_FIFO_FLUSH (1 << 0U)
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#define AUDAC_TXO_INT_EN (1 << 1U)
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#define AUDAC_TXU_INT_EN (1 << 2U)
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#define AUDAC_TXA_INT_EN (1 << 3U)
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#define AUDAC_TX_DRQ_EN (1 << 4U)
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#define AUDAC_TX_CH_EN_SHIFT (8U)
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#define AUDAC_TX_CH_EN_MASK (0x3 << AUDAC_TX_CH_EN_SHIFT)
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#define AUDAC_TX_DRQ_CNT_SHIFT (14U)
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#define AUDAC_TX_DRQ_CNT_MASK (0x3 << AUDAC_TX_DRQ_CNT_SHIFT)
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#define AUDAC_TX_TRG_LEVEL_SHIFT (16U)
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#define AUDAC_TX_TRG_LEVEL_MASK (0x1f << AUDAC_TX_TRG_LEVEL_SHIFT)
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#define AUDAC_TX_DATA_MODE_SHIFT (24U)
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#define AUDAC_TX_DATA_MODE_MASK (0x3 << AUDAC_TX_DATA_MODE_SHIFT)
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/* 0x90 : audac_fifo_status */
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#define AUDAC_TXO_INT (1 << 1U)
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#define AUDAC_TXU_INT (1 << 2U)
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#define AUDAC_TXA_INT (1 << 4U)
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#define AUDAC_TXA_CNT_SHIFT (16U)
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#define AUDAC_TXA_CNT_MASK (0x1f << AUDAC_TXA_CNT_SHIFT)
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#define AUDAC_TXA (1 << 24U)
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/* 0x94 : audac_fifo_data */
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#define AUDAC_TX_DATA_SHIFT (0U)
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#define AUDAC_TX_DATA_MASK (0xffffffff << AUDAC_TX_DATA_SHIFT)
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#endif /* __AUDAC_REG_H__ */
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