mirror of
https://github.com/Fishwaldo/bl_mcu_sdk.git
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144 lines
6.3 KiB
C
144 lines
6.3 KiB
C
/**
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******************************************************************************
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* @file dac_reg.h
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* @version V1.0
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* @date 2022-08-05
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* @brief This file is the description of.IP register
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Bouffalo Lab nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#ifndef __HARDWARE_DAC_H__
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#define __HARDWARE_DAC_H__
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register offsets *********************************************************/
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/* gpip base */
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#define GPIP_GPDAC_CONFIG_OFFSET (0x40) /* gpdac_config */
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#define GPIP_GPDAC_DMA_CONFIG_OFFSET (0x44) /* gpdac_dma_config */
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#define GPIP_GPDAC_DMA_WDATA_OFFSET (0x48) /* gpdac_dma_wdata */
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#define GPIP_GPDAC_TX_FIFO_STATUS_OFFSET (0x4C) /* gpdac_tx_fifo_status */
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/* glb base */
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#if defined(BL702)
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#define GLB_GPDAC_CTRL_OFFSET (0x308) /* gpdac_ctrl */
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#define GLB_GPDAC_ACTRL_OFFSET (0x30C) /* gpdac_actrl */
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#define GLB_GPDAC_BCTRL_OFFSET (0x310) /* gpdac_bctrl */
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#define GLB_GPDAC_DATA_OFFSET (0x314) /* gpdac_data */
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#else
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#define GLB_GPDAC_CTRL_OFFSET (0x120) /* gpdac_ctrl */
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#define GLB_GPDAC_ACTRL_OFFSET (0x124) /* gpdac_actrl */
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#define GLB_GPDAC_BCTRL_OFFSET (0x128) /* gpdac_bctrl */
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#define GLB_GPDAC_DATA_OFFSET (0x12C) /* gpdac_data */
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#endif
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/* Register Bitfield definitions *****************************************************/
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/* 0x40 : gpdac_config */
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#define GPIP_GPDAC_EN (1 << 0U)
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#if defined(BL702)
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#define GPIP_GPDAC_EN2 (1 << 1U)
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#define GPIP_DSM_MODE_SHIFT (4U)
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#define GPIP_DSM_MODE_MASK (0x3 << GPIP_DSM_MODE_SHIFT)
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#endif
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#define GPIP_GPDAC_MODE_SHIFT (8U)
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#define GPIP_GPDAC_MODE_MASK (0x7 << GPIP_GPDAC_MODE_SHIFT)
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#define GPIP_GPDAC_CH_A_SEL_SHIFT (16U)
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#define GPIP_GPDAC_CH_A_SEL_MASK (0xf << GPIP_GPDAC_CH_A_SEL_SHIFT)
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#define GPIP_GPDAC_CH_B_SEL_SHIFT (20U)
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#define GPIP_GPDAC_CH_B_SEL_MASK (0xf << GPIP_GPDAC_CH_B_SEL_SHIFT)
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/* 0x44 : gpdac_dma_config */
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#define GPIP_GPDAC_DMA_TX_EN (1 << 0U)
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#if defined(BL616) || defined(BL628) || defined(BL606P) || defined(BL808)
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#define GPIP_GPDAC_DMA_INV_MSB (1 << 1U)
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#endif
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#define GPIP_GPDAC_DMA_FORMAT_SHIFT (4U)
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#define GPIP_GPDAC_DMA_FORMAT_MASK (0x3 << GPIP_GPDAC_DMA_FORMAT_SHIFT)
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/* 0x48 : gpdac_dma_wdata */
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#define GPIP_GPDAC_DMA_WDATA_SHIFT (0U)
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#define GPIP_GPDAC_DMA_WDATA_MASK (0xffffffff << GPIP_GPDAC_DMA_WDATA_SHIFT)
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/* 0x4C : gpdac_tx_fifo_status */
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#define GPIP_TX_FIFO_EMPTY (1 << 0U)
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#define GPIP_TX_FIFO_FULL (1 << 1U)
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#define GPIP_TX_CS_SHIFT (2U)
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#define GPIP_TX_CS_MASK (0x3 << GPIP_TX_CS_SHIFT)
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#define GPIP_TXFIFORDPTR_SHIFT (4U)
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#define GPIP_TXFIFORDPTR_MASK (0x7 << GPIP_TXFIFORDPTR_SHIFT)
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#define GPIP_TXFIFOWRPTR_SHIFT (8U)
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#define GPIP_TXFIFOWRPTR_MASK (0x3 << GPIP_TXFIFOWRPTR_SHIFT)
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/* 0x308 : gpdac_ctrl */
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#define GLB_GPDACA_RSTN_ANA (1 << 0U)
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#define GLB_GPDACB_RSTN_ANA (1 << 1U)
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#define GLB_GPDAC_TEST_EN (1 << 7U)
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#define GLB_GPDAC_REF_SEL (1 << 8U)
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#define GLB_GPDAC_TEST_SEL_SHIFT (9U)
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#define GLB_GPDAC_TEST_SEL_MASK (0x7 << GLB_GPDAC_TEST_SEL_SHIFT)
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#if defined(BL616) || defined(BL628) || defined(BL606P) || defined(BL808)
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#define GLB_GPDAC_ANA_CLK_SEL (1 << 12U)
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#define GLB_GPDAC_DAT_CHA_SEL (1 << 13U)
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#define GLB_GPDAC_DAT_CHB_SEL (1 << 14U)
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#endif
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#define GLB_GPDAC_RESERVED_SHIFT (24U)
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#define GLB_GPDAC_RESERVED_MASK (0xff << GLB_GPDAC_RESERVED_SHIFT)
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/* 0x30C : gpdac_actrl */
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#define GLB_GPDAC_A_EN (1 << 0U)
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#define GLB_GPDAC_IOA_EN (1 << 1U)
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#define GLB_GPDAC_A_RNG_SHIFT (18U)
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#define GLB_GPDAC_A_RNG_MASK (0x3 << GLB_GPDAC_A_RNG_SHIFT)
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#define GLB_GPDAC_A_OUTMUX_SHIFT (20U)
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#define GLB_GPDAC_A_OUTMUX_MASK (0x7 << GLB_GPDAC_A_OUTMUX_SHIFT)
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/* 0x310 : gpdac_bctrl */
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#define GLB_GPDAC_B_EN (1 << 0U)
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#define GLB_GPDAC_IOB_EN (1 << 1U)
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#define GLB_GPDAC_B_RNG_SHIFT (18U)
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#define GLB_GPDAC_B_RNG_MASK (0x3 << GLB_GPDAC_B_RNG_SHIFT)
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#define GLB_GPDAC_B_OUTMUX_SHIFT (20U)
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#define GLB_GPDAC_B_OUTMUX_MASK (0x7 << GLB_GPDAC_B_OUTMUX_SHIFT)
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/* 0x314 : gpdac_data */
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#if defined(BL702) || defined(BL602) || defined(BL606P) || defined(BL808)
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#define GLB_GPDAC_B_DATA_SHIFT (0U)
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#define GLB_GPDAC_B_DATA_MASK (0x3ff << GLB_GPDAC_B_DATA_SHIFT)
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#define GLB_GPDAC_A_DATA_SHIFT (16U)
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#define GLB_GPDAC_A_DATA_MASK (0x3ff << GLB_GPDAC_A_DATA_SHIFT)
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#elif defined(BL616) || defined(BL628)
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#define GLB_GPDAC_B_DATA_SHIFT (0U)
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#define GLB_GPDAC_B_DATA_MASK (0x1fff << GLB_GPDAC_B_DATA_SHIFT)
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#define GLB_GPDAC_A_DATA_SHIFT (16U)
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#define GLB_GPDAC_A_DATA_MASK (0x1fff << GLB_GPDAC_A_DATA_SHIFT)
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#endif
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#endif /* __HARDWARE_DAC_H__ */
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