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237 lines
No EOL
9.5 KiB
C
237 lines
No EOL
9.5 KiB
C
/**
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******************************************************************************
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* @file emac_reg.h
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* @version V1.0
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* @date 2022-09-27
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* @brief This file is the description of.IP register
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2022 Bouffalo Lab</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Bouffalo Lab nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#ifndef __HARDWARE_EMAC_H__
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#define __HARDWARE_EMAC_H__
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register offsets *********************************************************/
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#define EMAC_MODE_OFFSET (0x0)
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#define EMAC_INT_SOURCE_OFFSET (0x4)
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#define EMAC_INT_MASK_OFFSET (0x8)
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#define EMAC_IPGT_OFFSET (0xC)
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#define EMAC_PACKETLEN_OFFSET (0x18)
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#define EMAC_COLLCONFIG_OFFSET (0x1C)
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#define EMAC_TX_BD_NUM_OFFSET (0x20)
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#define EMAC_MIIMODE_OFFSET (0x28)
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#define EMAC_MIICOMMAND_OFFSET (0x2C)
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#define EMAC_MIIADDRESS_OFFSET (0x30)
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#define EMAC_MIITX_DATA_OFFSET (0x34)
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#define EMAC_MIIRX_DATA_OFFSET (0x38)
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#define EMAC_MIISTATUS_OFFSET (0x3C)
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#define EMAC_MAC_ADDR0_OFFSET (0x40)
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#define EMAC_MAC_ADDR1_OFFSET (0x44)
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#define EMAC_HASH0_ADDR_OFFSET (0x48)
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#define EMAC_HASH1_ADDR_OFFSET (0x4C)
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#define EMAC_TXCTRL_OFFSET (0x50)
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#define EMAC_DMA_DESC_OFFSET (0x400)
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/* 0x0 : EMAC MODE config */
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#define EMAC_RX_EN (1 << 0U)
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#define EMAC_TX_EN (1 << 1U)
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#define EMAC_NOPRE (1 << 2U)
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#define EMAC_BRO (1 << 3U)
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#define EMAC_PRO (1 << 5U)
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#define EMAC_IFG (1 << 6U)
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#define EMAC_FULLD (1 << 10U)
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#define EMAC_CRCEN (1 << 13U)
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#define EMAC_HUGEN (1 << 14U)
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#define EMAC_PAD (1 << 15U)
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#define EMAC_RECSMALL (1 << 16U)
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#define EMAC_RMII_EN (1 << 17U)
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/* 0x4 : INT_SOURCE */
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#define EMAC_TXB (1 << 0U)
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#define EMAC_TXE (1 << 1U)
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#define EMAC_RXB (1 << 2U)
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#define EMAC_RXE (1 << 3U)
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#define EMAC_BUSY (1 << 4U)
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#define EMAC_TXC (1 << 5U)
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#define EMAC_RXC (1 << 6U)
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/* 0x8 : INT_MASK */
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#define EMAC_TXB_M (1 << 0U)
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#define EMAC_TXE_M (1 << 1U)
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#define EMAC_RXB_M (1 << 2U)
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#define EMAC_RXE_M (1 << 3U)
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#define EMAC_BUSY_M (1 << 4U)
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#define EMAC_TXC_M (1 << 5U)
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#define EMAC_RXC_M (1 << 6U)
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/* 0xC : IPGT */
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#define EMAC_IPGT_SHIFT (0U)
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#define EMAC_IPGT_MASK (0x7f << EMAC_IPGT_SHIFT)
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/* 0x18 : PACKETLEN */
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#define EMAC_MAXFL_SHIFT (0U)
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#define EMAC_MAXFL_MASK (0xffff << EMAC_MAXFL_SHIFT)
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#define EMAC_MINFL_SHIFT (16U)
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#define EMAC_MINFL_MASK (0xffff << EMAC_MINFL_SHIFT)
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/* 0x1C : COLLCONFIG */
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#define EMAC_COLLVALID_SHIFT (0U)
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#define EMAC_COLLVALID_MASK (0x3F << EMAC_COLLVALID_SHIFT)
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#define EMAC_MAXRET_SHIFT (16U)
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#define EMAC_MAXRET_MASK (0xF << EMAC_MAXRET_SHIFT)
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/* 0x20 : TX_BD_NUM */
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#define EMAC_TXBDNUM_SHIFT (0U)
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#define EMAC_TXBDNUM_MASK (0xff << EMAC_TXBDNUM_SHIFT)
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#define EMAC_TXBDPTR_SHIFT (16U)
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#define EMAC_TXBDPTR_MASK (0x7f << EMAC_TXBDPTR_SHIFT)
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#define EMAC_RXBDPTR_SHIFT (24U)
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#define EMAC_RXBDPTR_MASK (0x7f << EMAC_RXBDPTR_SHIFT)
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/* 0x28 : MIIMODE */
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#define EMAC_CLKDIV_SHIFT (0U)
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#define EMAC_CLKDIV_MASK (0xff << EMAC_CLKDIV_SHIFT)
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#define EMAC_MIINOPRE (1 << 8U)
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/* 0x2C : MIICOMMAND */
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#define EMAC_SCANSTAT (1 << 0U)
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#define EMAC_RSTAT (1 << 1U)
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#define EMAC_WCTRLDATA (1 << 2U)
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/* 0x30 : MIIADDRESS */
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#define EMAC_FIAD_SHIFT (0U)
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#define EMAC_FIAD_MASK (0x1f << EMAC_FIAD_SHIFT)
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#define EMAC_RGAD_SHIFT (8U)
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#define EMAC_RGAD_MASK (0x1f << EMAC_RGAD_SHIFT)
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/* 0x34 : MIITX_DATA */
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#define EMAC_CTRLDATA_SHIFT (0U)
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#define EMAC_CTRLDATA_MASK (0xffff << EMAC_CTRLDATA_SHIFT)
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/* 0x38 : MIIRX_DATA */
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#define EMAC_PRSD_SHIFT (0U)
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#define EMAC_PRSD_MASK (0xffff << EMAC_PRSD_SHIFT)
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/* 0x3C : MIISTATUS */
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#define EMAC_MIIM_LINKFAIL (1 << 0U)
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#define EMAC_MIIM_BUSY (1 << 1U)
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/* 0x40 : MAC_ADDR0 */
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#define EMAC_MAC_B5_SHIFT (0U)
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#define EMAC_MAC_B5_MASK (0xff << EMAC_MAC_B5_SHIFT)
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#define EMAC_MAC_B4_SHIFT (8U)
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#define EMAC_MAC_B4_MASK (0xff << EMAC_MAC_B4_SHIFT)
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#define EMAC_MAC_B3_SHIFT (16U)
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#define EMAC_MAC_B3_MASK (0xff << EMAC_MAC_B3_SHIFT)
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#define EMAC_MAC_B2_SHIFT (24U)
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#define EMAC_MAC_B2_MASK (0xff << EMAC_MAC_B2_SHIFT)
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/* 0x44 : MAC_ADDR1 */
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#define EMAC_MAC_B1_SHIFT (0U)
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#define EMAC_MAC_B1_MASK (0xff << EMAC_MAC_B1_SHIFT)
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#define EMAC_MAC_B0_SHIFT (8U)
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#define EMAC_MAC_B0_MASK (0xff << EMAC_MAC_B0_SHIFT)
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/* 0x48 : HASH0_ADDR */
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#define EMAC_HASH0_SHIFT (0U)
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#define EMAC_HASH0_MASK (0xffffffff << EMAC_HASH0_SHIFT)
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/* 0x4C : HASH1_ADDR */
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#define EMAC_HASH1_SHIFT (0U)
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#define EMAC_HASH1_MASK (0xffffffff << EMAC_HASH1_SHIFT)
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/* 0x50 : TXCTRL */
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#define EMAC_TXPAUSETV_SHIFT (0U)
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#define EMAC_TXPAUSETV_MASK (0xffff << EMAC_TXPAUSETV_SHIFT)
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#define EMAC_TXPAUSERQ_SHIFT (16U)
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#define EMAC_TXPAUSERQ_MASK (0x1 << EMAC_TXPAUSETV_SHIFT)
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/* 0x400 :EAMC DMA BD DESC */
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/* EMAC TX BD DESC BASE: (TX_BD_NUM * 8) */
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#define EMAC_BD_TX_CS_SHIFT (0) /*!< Carrier Sense Lost */
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#define EMAC_BD_TX_CS_MASK (1 << EMAC_BD_TX_CS_SHIFT)
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#define EMAC_BD_TX_DF_SHIFT (1) /*!< Defer Indication */
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#define EMAC_BD_TX_DF_MASK (1 << EMAC_BD_TX_DF_SHIFT)
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#define EMAC_BD_TX_LC_SHIFT (2) /*!< Late Collision */
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#define EMAC_BD_TX_LC_MASK (1 << EMAC_BD_TX_LC_SHIFT)
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#define EMAC_BD_TX_RL_SHIFT (3) /*!< Retransmission Limit */
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#define EMAC_BD_TX_RL_MASK (1 << EMAC_BD_TX_RL_SHIFT)
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#define EMAC_BD_TX_RTRY_SHIFT (4) /*!< Retry Count */
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#define EMAC_BD_TX_RTRY_MASK (4 << EMAC_BD_TX_RTRY_SHIFT)
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#define EMAC_BD_TX_UR_SHIFT (8) /*!< Underrun */
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#define EMAC_BD_TX_UR_MASK (1 << EMAC_BD_TX_UR_SHIFT)
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#define EMAC_BD_TX_EOF_SHIFT (10) /*!< EOF */
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#define EMAC_BD_TX_EOF_MASK (1 << EMAC_BD_TX_EOF_SHIFT)
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#define EMAC_BD_TX_CRC_SHIFT (11) /*!< CRC Enable */
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#define EMAC_BD_TX_CRC_MASK (1 << EMAC_BD_TX_CRC_SHIFT)
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#define EMAC_BD_TX_PAD_SHIFT (12) /*!< PAD enable */
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#define EMAC_BD_TX_PAD_MASK (1 << EMAC_BD_TX_PAD_SHIFT)
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#define EMAC_BD_TX_WR_SHIFT (13) /*!< Wrap */
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#define EMAC_BD_TX_WR_MASK (1 << EMAC_BD_TX_WR_SHIFT)
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#define EMAC_BD_TX_IRQ_SHIFT (14) /*!< Interrupt Request Enable */
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#define EMAC_BD_TX_IRQ_MASK (1 << EMAC_BD_TX_IRQ_SHIFT)
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#define EMAC_BD_TX_RD_SHIFT (15) /*!< The data buffer is ready for transmission or is currently being transmitted. You are not allowed to change it */
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#define EMAC_BD_TX_RD_MASK (1 << EMAC_BD_TX_RD_SHIFT)
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#define EMAC_BD_TX_LEN_SHIFT (16) /*!< TX Data buffer length */
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#define EMAC_BD_TX_LEN_MASK (0xffff << EMAC_BD_TX_LEN_SHIFT)
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/* RX BD DESC BASE: ((TX_BD_NUM + RX_BD_NUM) * 8) */
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#define EMAC_BD_RX_LC_SHIFT (0) /*!< Late Collision */
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#define EMAC_BD_RX_LC_MASK (1 << EMAC_BD_RX_LC_SHIFT)
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#define EMAC_BD_RX_CRC_SHIFT (1) /*!< RX CRC Error */
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#define EMAC_BD_RX_CRC_MASK (1 << EMAC_BD_RX_CRC_SHIFT)
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#define EMAC_BD_RX_SF_SHIFT (2) /*!< Short Frame */
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#define EMAC_BD_RX_SF_MASK (1 << EMAC_BD_RX_SF_SHIFT)
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#define EMAC_BD_RX_TL_SHIFT (3) /*!< Too Long */
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#define EMAC_BD_RX_TL_MASK (1 << EMAC_BD_RX_TL_SHIFT)
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#define EMAC_BD_RX_DN_SHIFT (4) /*!< Dribble Nibble */
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#define EMAC_BD_RX_DN_MASK (1 << EMAC_BD_RX_DN_SHIFT)
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#define EMAC_BD_RX_RE_SHIFT (5) /*!< Receive Error */
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#define EMAC_BD_RX_RE_MASK (1 << EMAC_BD_RX_RE_SHIFT)
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#define EMAC_BD_RX_OR_SHIFT (6) /*!< Overrun */
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#define EMAC_BD_RX_OR_MASK (1 << EMAC_BD_RX_OR_SHIFT)
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#define EMAC_BD_RX_M_SHIFT (7) /*!< Miss */
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#define EMAC_BD_RX_M_MASK (1 << EMAC_BD_RX_M_SHIFT)
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#define EMAC_BD_RX_CF_SHIFT (8) /*!< Control Frame Received */
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#define EMAC_BD_RX_CF_MASK (1 << EMAC_BD_RX_CF_SHIFT)
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#define EMAC_BD_RX_WR_SHIFT (13) /*!< Wrap */
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#define EMAC_BD_RX_WR_MASK (1 << EMAC_BD_RX_WR_SHIFT)
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#define EMAC_BD_RX_IRQ_SHIFT (14) /*!< Interrupt Request Enable */
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#define EMAC_BD_RX_IRQ_MASK (1 << EMAC_BD_RX_IRQ_SHIFT)
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#define EMAC_BD_RX_E_SHIFT (15) /*!< The data buffer is empty (and ready for receiving data) or currently receiving data */
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#define EMAC_BD_RX_E_MASK (1 << EMAC_BD_RX_E_SHIFT)
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#define EMAC_BD_RX_LEN_SHIFT (16) /*!< RX Data buffer length */
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#define EMAC_BD_RX_LEN_MASK (0xffff << EMAC_BD_RX_LEN_SHIFT)
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/* MAX BD DESC 0x7FF */
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#endif /* __HARDWARE_EMAC_H__ */ |