mirror of
https://github.com/Fishwaldo/bl_mcu_sdk.git
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356f258e83
* use nuttx libc, disable system libc * use tlsf as default * update lhal flash driver * add example readme * add flash ini for new flash tool * add fw header for new flash tool
139 lines
5.9 KiB
C
139 lines
5.9 KiB
C
/**
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******************************************************************************
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* @file sdio2.h
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* @version V1.0
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* @date 2022-08-03
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* @brief This file is the description of.IP register
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Bouffalo Lab nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#ifndef __HARDWARE_SDIO2_H__
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#define __HARDWARE_SDIO2_H__
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register offsets *********************************************************/
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#define SDIO2_IO_ENABLE_OFFSET (0x0002) /* SDIO I/O Enable */
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#define SDIO2_FN1_BLK_SIZE_0_OFFSET (0x0028) /* SDIO block size infor */
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#define SDIO2_FN1_BLK_SIZE_1_OFFSET (0x0029) /* SDIO block size infor */
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#define SDIO2_DEV_SLEEP_OFFSET (0x0092) /* SDIO Device Sleep */
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#define SDIO2_CCR_FUNC_OFFSET (0x0100) /* Address offset of CCR between two functions */
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#define SDIO2_HOST_TO_CARD_EVENT_OFFSET (0x0100)
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#define SDIO2_HOST_INT_CAUSE_OFFSET (0x0101)
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#define SDIO2_HOST_INT_MASK_OFFSET (0x0102)
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#define SDIO2_HOST_INT_STATUS_OFFSET (0x0103)
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#define SDIO2_RD_BIT_MAP_OFFSET (0x0104)
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#define SDIO2_WR_BIT_MAP_OFFSET (0x0106)
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#define SDIO2_RD_LEN_OFFSET (0x0108)
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#define SDIO2_HOST_TRANS_STATUS_OFFSET (0x0128)
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#define SDIO2_CARD_TO_HOST_EVENT_OFFSET (0x0130)
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#define SDIO2_CARD_INT_MASK_OFFSET (0x0134)
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#define SDIO2_CARD_INT_STATUS_OFFSET (0x0138)
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#define SDIO2_CARD_INT_MODE_OFFSET (0x013C)
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#define SDIO2_SQ_READ_BASE_OFFSET (0x0140)
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#define SDIO2_SQ_WRITE_BASE_OFFSET (0x0144)
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#define SDIO2_READ_INDEX_OFFSET (0x0148)
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#define SDIO2_WRITE_INDEX_OFFSET (0x0149)
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#define SDIO2_DNLD_QUEUE_WRPTR_OFFSET (0x014A)
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#define SDIO2_UPLD_QUEUE_WRPTR_OFFSET (0x014B)
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#define SDIO2_DNLD_QUEUE_OFFSET (0x014C)
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#define SDIO2_UPLD_QUEUE_OFFSET (0x0154)
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#define SDIO2_CHIP_VERSION_OFFSET (0x015C)
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#define SDIO2_IP_VERSION0_OFFSET (0x015E)
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#define SDIO2_IP_VERSION1_OFFSET (0x015F)
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#define SDIO2_SCRATCH2_OFFSET (0x0164)
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#define SDIO2_SCRATCH1_OFFSET (0x0166)
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#define SDIO2_OCR0_OFFSET (0x0168)
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#define SDIO2_OCR1_OFFSET (0x0169)
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#define SDIO2_OCR2_OFFSET (0x016A)
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#define SDIO2_CONFIG_OFFSET (0x016B)
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#define SDIO2_CONFIG2_OFFSET (0x016C)
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#define SDIO2_DEBUG_OFFSET (0x0170)
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#define SDIO2_DMA_ADDR_OFFSET (0x0174)
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#define SDIO2_IO_PORT_OFFSET (0x0178)
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// Bit Def. Scratch register 0
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#define SDIO2_SCRATCH_OFFSET (0x0160)
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// Bit Def. Block size 1 mask (Offset 0x29)
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#define SDIO2_FN1_BLK_SIZE_1_MASK 0x01
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// Bit Def. Host To Card Interrupt Event (Offset 0x100/200)
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#define SDIO2_HCR_CONFIG_HostPwrUp (1 << 1)
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// Bit Def. Host Transfer Status (Offset 0x128/228)
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#define SDIO2_CCR_HOST_INT_DnLdReStart (1 << 0)
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#define SDIO2_CCR_HOST_INT_UpLdReStart (1 << 1)
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#define SDIO2_CCR_HOST_INT_DnLdCRC_err (1 << 2)
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// Bit Def. Card To Host Interrupt Event (Offset 0x130/230)
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#define SDIO2_CCR_CS_DnLdRdy (1 << 0)
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#define SDIO2_CCR_CS_UpLdRdy (1 << 1)
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#define SDIO2_CCR_CS_ReadCISRdy (1 << 2)
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#define SDIO2_CCR_CS_IORdy (1 << 3)
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// Bit Def. Card Interrupt Mask (Offset 0x134/234)
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#define SDIO2_CCR_CIM_DnLdOvr (1 << 0)
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#define SDIO2_CCR_CIM_UpLdOvr (1 << 1)
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#define SDIO2_CCR_CIM_Abort (1 << 2)
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#define SDIO2_CCR_CIM_PwrDn (1 << 3)
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#define SDIO2_CCR_CIM_PwrUp (1 << 4)
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#define SDIO2_CCR_CIM_MASK 0x0007
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// Bit Def. Card Interrupt Status (Offset 0x138/238)
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#define SDIO2_CCR_CIC_DnLdOvr (1 << 0)
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#define SDIO2_CCR_CIC_UpLdOvr (1 << 1)
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#define SDIO2_CCR_CIC_Abort (1 << 2)
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#define SDIO2_CCR_CIC_PwrDn (1 << 3)
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#define SDIO2_CCR_CIC_PwrUp (1 << 4)
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#define SDIO2_CCR_CIC_MASK 0x001F
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// Bit Def. Card Interrupt RSR (Offset 0x13C/23C)
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#define SDIO2_CCR_CIO_DnLdOvr (1 << 0)
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#define SDIO2_CCR_CIO_UpLdOvr (1 << 1)
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#define SDIO2_CCR_CIO_Abort (1 << 2)
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#define SDIO2_CCR_CIO_PwrDn (1 << 3)
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#define SDIO2_CCR_CIO_PwrUp (1 << 4)
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#define SDIO2_CCR_CIO_MASK 0x001F
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//Config2 register mask
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#define SDIO2_CONFIG2_MSK 0x00000C00
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//CardIntMode register mask
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#define SDIO2_CARD_INT_MODE_MSK 0x00000003
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#define SDIO2_HOST_INT_MSK 0x00000002
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#endif /* __HARDWARE_SDIO2_H__ */
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