mirror of
https://github.com/Fishwaldo/bl_mcu_sdk.git
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285 lines
11 KiB
C
285 lines
11 KiB
C
/**
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******************************************************************************
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* @file timer_reg.h
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* @version V1.0
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* @date 2022-08-03
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* @brief This file is the description of.IP register
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Bouffalo Lab nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#ifndef __HARDWARE_TIMER_H__
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#define __HARDWARE_TIMER_H__
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register offsets *********************************************************/
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#define TIMER_TCCR_OFFSET (0x0) /* Timer Clock Source */
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#define TIMER_TMR0_0_OFFSET (0x10) /* Timer0 Match Value 0 */
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#define TIMER_TMR0_1_OFFSET (0x14) /* Timer0 Match Value 1 */
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#define TIMER_TMR0_2_OFFSET (0x18) /* Timer0 Match Value 2 */
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#define TIMER_TMR1_0_OFFSET (0x1C) /* Timer1 Match Value 0 */
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#define TIMER_TMR1_1_OFFSET (0x20) /* Timer1 Match Value 1 */
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#define TIMER_TMR1_2_OFFSET (0x24) /* Timer1 Match Value 2 */
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#define TIMER_TCR0_OFFSET (0x2C) /* Timer0 Counter Value */
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#define TIMER_TCR1_OFFSET (0x30) /* Timer1 Counter Value */
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#define TIMER_TSR0_OFFSET (0x38) /* Timer0 Match Status */
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#define TIMER_TSR1_OFFSET (0x3C) /* Timer1 Match Status */
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#define TIMER_TIER0_OFFSET (0x44) /* Timer0 Match Interrupt Enable */
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#define TIMER_TIER1_OFFSET (0x48) /* Timer1 Match Interrupt Enable */
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#define TIMER_TPLVR0_OFFSET (0x50) /* Timer0 Pre-Load Value */
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#define TIMER_TPLVR1_OFFSET (0x54) /* Timer1 Pre-Load Value */
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#define TIMER_TPLCR0_OFFSET (0x5C) /* Timer0 Pre-Load Control */
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#define TIMER_TPLCR1_OFFSET (0x60) /* Timer1 Pre-Load Control */
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#define TIMER_WMER_OFFSET (0x64) /* Watch-dog reset/interrupt Mode */
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#define TIMER_WMR_OFFSET (0x68) /* Watch-dog Match Value */
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#define TIMER_WVR_OFFSET (0x6C) /* Watch-dog Counter Value */
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#define TIMER_WSR_OFFSET (0x70) /* Watch-dog Reset Status */
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#define TIMER_TICR0_OFFSET (0x78) /* Timer0 Interrupt Clear */
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#define TIMER_TICR1_OFFSET (0x7C) /* Timer1 Interrupt Clear */
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#define TIMER_WICR_OFFSET (0x80) /* WDT Interrupt Clear */
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#define TIMER_TCER_OFFSET (0x84) /* Timer Counter Enable/Clear */
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#define TIMER_TCMR_OFFSET (0x88) /* Timer Counter Mode */
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#define TIMER_TILR0_OFFSET (0x90) /* Timer0 Match Interrupt Mode */
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#define TIMER_TILR1_OFFSET (0x94) /* Timer1 Match Interrupt Mode */
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#define TIMER_WCR_OFFSET (0x98) /* WDT Counter Reset */
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#define TIMER_WFAR_OFFSET (0x9C) /* WDT Access Key1 */
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#define TIMER_WSAR_OFFSET (0xA0) /* WDT Access Key2 */
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#define TIMER_TCVWR0_OFFSET (0xA8) /* Timer0 Counter Latch Value */
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#define TIMER_TCVWR1_OFFSET (0xAC) /* Timer1 Counter Latch Value */
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#define TIMER_TCVSYN0_OFFSET (0xB4) /* Timer0 Counter Sync Value */
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#define TIMER_TCVSYN1_OFFSET (0xB8) /* Timer1 Counter Sync Value */
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#define TIMER_TCDR_OFFSET (0xBC) /* Timer Division */
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#if !defined(BL702) || !defined(BL602)
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#define TIMER_GPIO_OFFSET (0xC0) /* GPIO Mode */
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#define TIMER_GPIO_LAT1_OFFSET (0xC4) /* GPIO Latch Value1 */
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#define TIMER_GPIO_LAT2_OFFSET (0xC8) /* GPIO Latch Value2 */
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#define TIMER_TCDR_FORCE_OFFSET (0xCC) /* Timer Division Force */
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#endif
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/* Register Bitfield definitions *****************************************************/
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/* 0x0 : Timer Clock Source */
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#if defined(BL702) || defined(BL602)
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#define TIMER_CS_0_SHIFT (2U)
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#define TIMER_CS_0_MASK (0x3 << TIMER_CS_0_SHIFT)
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#define TIMER_CS_1_SHIFT (5U)
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#define TIMER_CS_1_MASK (0x3 << TIMER_CS_1_SHIFT)
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#define TIMER_CS_WDT_SHIFT (8U)
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#define TIMER_CS_WDT_MASK (0x3 << TIMER_CS_WDT_SHIFT)
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#else
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#define TIMER_CS_0_SHIFT (0U)
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#define TIMER_CS_0_MASK (0xf << TIMER_CS_0_SHIFT)
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#define TIMER_CS_1_SHIFT (4U)
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#define TIMER_CS_1_MASK (0xf << TIMER_CS_1_SHIFT)
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#define TIMER_CS_WDT_SHIFT (8U)
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#define TIMER_CS_WDT_MASK (0xf << TIMER_CS_WDT_SHIFT)
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#define TIMER_ID_SHIFT (24U)
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#define TIMER_ID_MASK (0xff << TIMER_ID_SHIFT)
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#endif
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/* 0x10 : Timer0 Match Value 0 */
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#define TIMER_TMR0_0_SHIFT (0U)
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#define TIMER_TMR0_0_MASK (0xffffffff << TIMER_TMR0_0_SHIFT)
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/* 0x14 : Timer0 Match Value 1 */
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#define TIMER_TMR0_1_SHIFT (0U)
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#define TIMER_TMR0_1_MASK (0xffffffff << TIMER_TMR0_1_SHIFT)
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/* 0x18 : Timer0 Match Value 2 */
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#define TIMER_TMR0_2_SHIFT (0U)
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#define TIMER_TMR0_2_MASK (0xffffffff << TIMER_TMR0_2_SHIFT)
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/* 0x1C : Timer1 Match Value 0 */
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#define TIMER_TMR1_0_SHIFT (0U)
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#define TIMER_TMR1_0_MASK (0xffffffff << TIMER_TMR1_0_SHIFT)
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/* 0x20 : Timer1 Match Value 1 */
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#define TIMER_TMR1_1_SHIFT (0U)
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#define TIMER_TMR1_1_MASK (0xffffffff << TIMER_TMR1_1_SHIFT)
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/* 0x24 : Timer1 Match Value 2 */
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#define TIMER_TMR1_2_SHIFT (0U)
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#define TIMER_TMR1_2_MASK (0xffffffff << TIMER_TMR1_2_SHIFT)
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/* 0x2C : Timer0 Counter Value */
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#define TIMER_TCR0_CNT_SHIFT (0U)
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#define TIMER_TCR0_CNT_MASK (0xffffffff << TIMER_TCR0_CNT_SHIFT)
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/* 0x30 : Timer1 Counter Value */
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#define TIMER_TCR1_CNT_SHIFT (0U)
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#define TIMER_TCR1_CNT_MASK (0xffffffff << TIMER_TCR1_CNT_SHIFT)
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/* 0x38 : Timer0 Match Status */
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#define TIMER_TSR0_0 (1 << 0U)
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#define TIMER_TSR0_1 (1 << 1U)
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#define TIMER_TSR0_2 (1 << 2U)
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/* 0x3C : Timer1 Match Status */
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#define TIMER_TSR1_0 (1 << 0U)
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#define TIMER_TSR1_1 (1 << 1U)
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#define TIMER_TSR1_2 (1 << 2U)
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/* 0x44 : Timer0 Match Interrupt Enable */
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#define TIMER_TIER0_0 (1 << 0U)
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#define TIMER_TIER0_1 (1 << 1U)
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#define TIMER_TIER0_2 (1 << 2U)
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/* 0x48 : Timer1 Match Interrupt Enable */
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#define TIMER_TIER1_0 (1 << 0U)
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#define TIMER_TIER1_1 (1 << 1U)
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#define TIMER_TIER1_2 (1 << 2U)
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/* 0x50 : Timer0 Pre-Load Value */
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#define TIMER_TPLVR0_SHIFT (0U)
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#define TIMER_TPLVR0_MASK (0xffffffff << TIMER_TPLVR0_SHIFT)
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/* 0x54 : Timer1 Pre-Load Value */
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#define TIMER_TPLVR1_SHIFT (0U)
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#define TIMER_TPLVR1_MASK (0xffffffff << TIMER_TPLVR1_SHIFT)
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/* 0x5C : Timer0 Pre-Load Control */
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#define TIMER_TPLCR0_SHIFT (0U)
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#define TIMER_TPLCR0_MASK (0x3 << TIMER_TPLCR0_SHIFT)
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/* 0x60 : Timer1 Pre-Load Control */
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#define TIMER_TPLCR1_SHIFT (0U)
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#define TIMER_TPLCR1_MASK (0x3 << TIMER_TPLCR1_SHIFT)
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/* 0x64 : Watch-dog reset/interrupt Mode */
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#define TIMER_WE (1 << 0U)
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#define TIMER_WRIE (1 << 1U)
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/* 0x68 : Watch-dog Match Value */
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#define TIMER_WMR_SHIFT (0U)
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#define TIMER_WMR_MASK (0xffff << TIMER_WMR_SHIFT)
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#define TIMER_WDT_ALIGN (1 << 16U)
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/* 0x6C : Watch-dog Counter Value */
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#define TIMER_WDT_CNT_SHIFT (0U)
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#define TIMER_WDT_CNT_MASK (0xffff << TIMER_WDT_CNT_SHIFT)
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/* 0x70 : Watch-dog Reset Status */
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#define TIMER_WTS (1 << 0U)
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/* 0x78 : Timer0 Interrupt Clear */
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#define TIMER_TCLR0_0 (1 << 0U)
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#define TIMER_TCLR0_1 (1 << 1U)
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#define TIMER_TCLR0_2 (1 << 2U)
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/* 0x7C : Timer1 Interrupt Clear */
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#define TIMER_TCLR1_0 (1 << 0U)
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#define TIMER_TCLR1_1 (1 << 1U)
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#define TIMER_TCLR1_2 (1 << 2U)
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/* 0x80 : WDT Interrupt Clear */
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#define TIMER_WICLR (1 << 0U)
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/* 0x84 : Timer Counter Enable/Clear */
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#define TIMER0_EN (1 << 1U)
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#define TIMER1_EN (1 << 2U)
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#define TIMER_TCR0_CNT_CLR (1 << 5U)
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#define TIMER_TCR1_CNT_CLR (1 << 6U)
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/* 0x88 : Timer Counter Mode */
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#define TIMER0_MODE (1 << 1U)
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#define TIMER1_MODE (1 << 2U)
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#define TIMER0_ALIGN (1 << 5U)
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#define TIMER1_ALIGN (1 << 6U)
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/* 0x90 : Timer0 Match Interrupt Mode */
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#define TIMER_TILR0_0 (1 << 0U)
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#define TIMER_TILR0_1 (1 << 1U)
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#define TIMER_TILR0_2 (1 << 2U)
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/* 0x94 : Timer1 Match Interrupt Mode */
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#define TIMER_TILR1_0 (1 << 0U)
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#define TIMER_TILR1_1 (1 << 1U)
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#define TIMER_TILR1_2 (1 << 2U)
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/* 0x98 : WDT Counter Reset */
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#define TIMER_WCR (1 << 0U)
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/* 0x9C : WDT Access Key1 */
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#define TIMER_WFAR_SHIFT (0U)
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#define TIMER_WFAR_MASK (0xffff << TIMER_WFAR_SHIFT)
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/* 0xA0 : WDT Access Key2 */
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#define TIMER_WSAR_SHIFT (0U)
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#define TIMER_WSAR_MASK (0xffff << TIMER_WSAR_SHIFT)
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/* 0xA8 : Timer0 Counter Latch Value */
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#define TIMER_TCR0_CNT_LAT_SHIFT (0U)
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#define TIMER_TCR0_CNT_LAT_MASK (0xffffffff << TIMER_TCR0_CNT_LAT_SHIFT)
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/* 0xAC : Timer1 Counter Latch Value */
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#define TIMER_TCR1_CNT_LAT_SHIFT (0U)
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#define TIMER_TCR1_CNT_LAT_MASK (0xffffffff << TIMER_TCR1_CNT_LAT_SHIFT)
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/* 0xB4 : Timer0 Counter Sync Value */
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#define TIMER_TCR0_CNT_SYNC_SHIFT (0U)
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#define TIMER_TCR0_CNT_SYNC_MASK (0xffffffff << TIMER_TCR0_CNT_SYNC_SHIFT)
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/* 0xB8 : Timer1 Counter Sync Value */
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#define TIMER_TCR1_CNT_SYNC_SHIFT (0U)
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#define TIMER_TCR1_CNT_SYNC_MASK (0xffffffff << TIMER_TCR1_CNT_SYNC_SHIFT)
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/* 0xBC : Timer Division */
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#define TIMER_TCDR0_SHIFT (8U)
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#define TIMER_TCDR0_MASK (0xff << TIMER_TCDR0_SHIFT)
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#define TIMER_TCDR1_SHIFT (16U)
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#define TIMER_TCDR1_MASK (0xff << TIMER_TCDR1_SHIFT)
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#define TIMER_WCDR_SHIFT (24U)
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#define TIMER_WCDR_MASK (0xff << TIMER_WCDR_SHIFT)
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#if !defined(BL702) || !defined(BL602)
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/* 0xC0 : GPIO Mode */
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#define TIMER0_GPIO_EN (1 << 1U)
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#define TIMER0_GPIO_INV (1 << 5U)
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#define TIMER1_GPIO_INV (1 << 6U)
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#define TIMER_WDT_GPIO_INV (1 << 7U)
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#define TIMER_GPIO_LAT_OK (1 << 31U)
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/* 0xC4 : GPIO Latch Value1 */
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#define TIMER_GPIO_LAT1_SHIFT (0U)
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#define TIMER_GPIO_LAT1_MASK (0xffffffff << TIMER_GPIO_LAT1_SHIFT)
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/* 0xC8 : GPIO Latch Value2 */
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#define TIMER_GPIO_LAT2_SHIFT (0U)
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#define TIMER_GPIO_LAT2_MASK (0xffffffff << TIMER_GPIO_LAT2_SHIFT)
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/* 0xCC : Timer Division Force */
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#define TIMER_TCDR0_FORCE (1 << 1U)
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#define TIMER_TCDR1_FORCE (1 << 2U)
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#define TIMER_WCDR_FORCE (1 << 4U)
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#endif
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#endif /* __HARDWARE_TIMER_H__ */
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