mirror of
https://github.com/Fishwaldo/bl_mcu_sdk.git
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* Add flash driver and init in boards. * Add timeout for all poll wait apis * Add 808 d0 startup to bringup * Update lhal device tables * Update demos
139 lines
3.8 KiB
C
139 lines
3.8 KiB
C
#include "bflb_mtimer.h"
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#include "bflb_spi.h"
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#include "bflb_dma.h"
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#include "board.h"
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#define SPI_MASTER_CASE 0
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#define SPI_SLAVE_CASE 1
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#define SPI_CASE_SELECT SPI_MASTER_CASE
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struct bflb_device_s *spi0;
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struct bflb_device_s *dma0_ch0;
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struct bflb_device_s *dma0_ch1;
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static ATTR_NOCACHE_NOINIT_RAM_SECTION uint32_t tx_buffer[256];
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static ATTR_NOCACHE_NOINIT_RAM_SECTION uint32_t rx_buffer[256];
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static volatile uint8_t dma_tc_flag0 = 0;
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static volatile uint8_t dma_tc_flag1 = 0;
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void dma0_ch0_isr(void *arg)
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{
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dma_tc_flag0++;
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printf("tc done\r\n");
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}
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void dma0_ch1_isr(void *arg)
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{
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dma_tc_flag1++;
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printf("rx done\r\n");
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}
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void sram_init()
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{
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uint32_t i;
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for (i = 0; i < 256; i++) {
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tx_buffer[i] = i * 0x1010101;
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rx_buffer[i] = 0;
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}
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}
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int main(void)
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{
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struct bflb_dma_channel_lli_pool_s tx_llipool[1];
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struct bflb_dma_channel_lli_transfer_s tx_transfers[1];
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struct bflb_dma_channel_lli_pool_s rx_llipool[1];
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struct bflb_dma_channel_lli_transfer_s rx_transfers[1];
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struct bflb_spi_config_s spi_cfg = {
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#if (SPI_CASE_SELECT == SPI_MASTER_CASE)
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.freq = 1 * 1000 * 1000,
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.role = SPI_ROLE_MASTER,
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#else
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.freq = 32 * 1000 * 1000,
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.role = SPI_ROLE_SLAVE,
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#endif
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.mode = SPI_MODE3,
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.data_width = SPI_DATA_WIDTH_32BIT,
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.bit_order = SPI_BIT_MSB,
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.byte_order = SPI_BYTE_LSB,
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.tx_fifo_threshold = 0,
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.rx_fifo_threshold = 0,
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};
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struct bflb_dma_channel_config_s tx_config = {
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.direction = DMA_MEMORY_TO_PERIPH,
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.src_req = DMA_REQUEST_NONE,
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.dst_req = DMA_REQUEST_SPI0_TX,
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.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE,
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.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE,
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.src_burst_count = DMA_BURST_INCR1,
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.dst_burst_count = DMA_BURST_INCR1,
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.src_width = DMA_DATA_WIDTH_32BIT,
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.dst_width = DMA_DATA_WIDTH_32BIT,
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};
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struct bflb_dma_channel_config_s rx_config = {
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.direction = DMA_PERIPH_TO_MEMORY,
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.src_req = DMA_REQUEST_SPI0_RX,
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.dst_req = DMA_REQUEST_NONE,
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.src_addr_inc = DMA_ADDR_INCREMENT_DISABLE,
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.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE,
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.src_burst_count = DMA_BURST_INCR1,
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.dst_burst_count = DMA_BURST_INCR1,
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.src_width = DMA_DATA_WIDTH_32BIT,
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.dst_width = DMA_DATA_WIDTH_32BIT,
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};
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board_init();
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board_spi0_gpio_init();
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sram_init();
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spi0 = bflb_device_get_by_name("spi0");
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bflb_spi_init(spi0, &spi_cfg);
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bflb_spi_link_txdma(spi0, true);
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bflb_spi_link_rxdma(spi0, true);
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printf("\n\rspi dma test\n\r");
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dma0_ch0 = bflb_device_get_by_name("dma0_ch0");
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dma0_ch1 = bflb_device_get_by_name("dma0_ch1");
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bflb_dma_channel_init(dma0_ch0, &tx_config);
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bflb_dma_channel_init(dma0_ch1, &rx_config);
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bflb_dma_channel_irq_attach(dma0_ch0, dma0_ch0_isr, NULL);
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bflb_dma_channel_irq_attach(dma0_ch1, dma0_ch1_isr, NULL);
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tx_transfers[0].src_addr = (uint32_t)tx_buffer;
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tx_transfers[0].dst_addr = (uint32_t)DMA_ADDR_SPI0_TDR;
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tx_transfers[0].nbytes = 256 * 4;
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rx_transfers[0].src_addr = (uint32_t)DMA_ADDR_SPI0_RDR;
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rx_transfers[0].dst_addr = (uint32_t)rx_buffer;
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rx_transfers[0].nbytes = 256 * 4;
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bflb_dma_channel_lli_reload(dma0_ch0, tx_llipool, 1, tx_transfers, 1);
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bflb_dma_channel_lli_reload(dma0_ch1, rx_llipool, 1, rx_transfers, 1);
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bflb_dma_channel_start(dma0_ch0);
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bflb_dma_channel_start(dma0_ch1);
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while (dma_tc_flag0 != 1) {
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bflb_mtimer_delay_ms(1);
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}
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while (dma_tc_flag1 != 1) {
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bflb_mtimer_delay_ms(1);
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}
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for (uint32_t i = 0; i < 256; i++) {
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if (rx_buffer[i] != tx_buffer[i]) {
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printf("error! index %ld: send 0x%08lX but read 0x%08lX\n\r", i, tx_buffer[i], rx_buffer[i]);
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}
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}
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printf("\n\rtest end\n\r");
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while (1) {
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}
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}
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