mirror of
https://github.com/Fishwaldo/bl_mcu_sdk.git
synced 2025-07-23 21:29:17 +00:00
136 lines
4.1 KiB
C
136 lines
4.1 KiB
C
#include "bflb_mtimer.h"
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#include "bflb_dma.h"
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#include "bflb_uart.h"
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#include "bflb_l1c.h"
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#include "board.h"
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struct bflb_device_s *uart1;
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struct bflb_device_s *dma0_ch0;
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struct bflb_device_s *dma0_ch1;
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static ATTR_NOCACHE_RAM_SECTION uint8_t src_buffer[4100];
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static ATTR_NOCACHE_RAM_SECTION uint8_t src2_buffer[4100];
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static ATTR_NOCACHE_RAM_SECTION uint8_t src3_buffer[4100];
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static ATTR_NOCACHE_RAM_SECTION uint8_t receive_buffer[50] = { 0 };
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static volatile uint8_t dma_tc_flag0 = 0;
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static volatile uint8_t dma_tc_flag1 = 0;
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void dma0_ch0_isr(void *arg)
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{
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dma_tc_flag0++;
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printf("tc done\r\n");
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}
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void dma0_ch1_isr(void *arg)
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{
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dma_tc_flag1++;
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printf("rx done\r\n");
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}
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void sram_init()
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{
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memset(src_buffer, 'a', 4100);
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src_buffer[3999] = 'B';
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src_buffer[4095] = 'A';
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src_buffer[4096] = 'B';
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src_buffer[4097] = 'C';
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src_buffer[4098] = 'D';
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src_buffer[4099] = 'E';
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memset(src2_buffer, 'c', 4100);
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memset(src3_buffer, 'd', 4100);
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}
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int main(void)
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{
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board_init();
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board_uart1_gpio_init();
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sram_init();
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uart1 = bflb_device_get_by_name("uart1");
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struct bflb_uart_config_s cfg;
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cfg.baudrate = 2000000;
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cfg.data_bits = UART_DATA_BITS_8;
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cfg.stop_bits = UART_STOP_BITS_1;
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cfg.parity = UART_PARITY_NONE;
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cfg.flow_ctrl = 0;
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cfg.tx_fifo_threshold = 7;
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cfg.rx_fifo_threshold = 0;
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bflb_uart_init(uart1, &cfg);
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bflb_uart_link_txdma(uart1, true);
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bflb_uart_link_rxdma(uart1, true);
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dma0_ch0 = bflb_device_get_by_name("dma0_ch0");
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dma0_ch1 = bflb_device_get_by_name("dma0_ch1");
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struct bflb_dma_channel_config_s config;
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config.direction = DMA_MEMORY_TO_PERIPH;
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config.src_req = DMA_REQUEST_NONE;
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config.dst_req = DMA_REQUEST_UART1_TX;
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config.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
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config.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
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config.src_burst_count = DMA_BURST_INCR1;
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config.dst_burst_count = DMA_BURST_INCR1;
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config.src_width = DMA_DATA_WIDTH_8BIT;
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config.dst_width = DMA_DATA_WIDTH_8BIT;
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bflb_dma_channel_init(dma0_ch0, &config);
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struct bflb_dma_channel_config_s rxconfig;
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rxconfig.direction = DMA_PERIPH_TO_MEMORY;
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rxconfig.src_req = DMA_REQUEST_UART1_RX;
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rxconfig.dst_req = DMA_REQUEST_NONE;
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rxconfig.src_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
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rxconfig.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
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rxconfig.src_burst_count = DMA_BURST_INCR1;
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rxconfig.dst_burst_count = DMA_BURST_INCR1;
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rxconfig.src_width = DMA_DATA_WIDTH_8BIT;
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rxconfig.dst_width = DMA_DATA_WIDTH_8BIT;
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bflb_dma_channel_init(dma0_ch1, &rxconfig);
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bflb_dma_channel_irq_attach(dma0_ch0, dma0_ch0_isr, NULL);
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bflb_dma_channel_irq_attach(dma0_ch1, dma0_ch1_isr, NULL);
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struct bflb_dma_channel_lli_pool_s tx_llipool[20]; /* max trasnfer size 4064 * 20 */
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struct bflb_dma_channel_lli_transfer_s tx_transfers[3];
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tx_transfers[0].src_addr = (uint32_t)src_buffer;
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tx_transfers[0].dst_addr = (uint32_t)DMA_ADDR_UART1_TDR;
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tx_transfers[0].nbytes = 4100;
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tx_transfers[1].src_addr = (uint32_t)src2_buffer;
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tx_transfers[1].dst_addr = (uint32_t)DMA_ADDR_UART1_TDR;
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tx_transfers[1].nbytes = 4100;
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tx_transfers[2].src_addr = (uint32_t)src3_buffer;
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tx_transfers[2].dst_addr = (uint32_t)DMA_ADDR_UART1_TDR;
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tx_transfers[2].nbytes = 4100;
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struct bflb_dma_channel_lli_pool_s rx_llipool[20];
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struct bflb_dma_channel_lli_transfer_s rx_transfers[1];
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rx_transfers[0].src_addr = (uint32_t)DMA_ADDR_UART1_RDR;
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rx_transfers[0].dst_addr = (uint32_t)receive_buffer;
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rx_transfers[0].nbytes = 50;
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bflb_dma_channel_lli_reload(dma0_ch0, tx_llipool, 20, tx_transfers, 3);
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bflb_dma_channel_lli_reload(dma0_ch1, rx_llipool, 20, rx_transfers, 1);
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bflb_dma_channel_start(dma0_ch0);
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bflb_dma_channel_start(dma0_ch1);
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while (dma_tc_flag0 != 3) {
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bflb_mtimer_delay_ms(1);
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}
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while (dma_tc_flag1 == 0) {
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}
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for (uint8_t i = 0; i < 50; i++) {
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printf("receive data:%02x\r\n", receive_buffer[i]);
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}
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while (1) {
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printf("helloworld\r\n");
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bflb_mtimer_delay_ms(2000);
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}
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}
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