mirror of
https://github.com/Fishwaldo/bl_mcu_sdk.git
synced 2025-07-23 05:08:45 +00:00
88 lines
No EOL
2.7 KiB
C
88 lines
No EOL
2.7 KiB
C
#include "bl602.h"
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#include "bl602_glb.h"
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#include "bl602_hbn.h"
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/*----------------------------------------------------------------------------
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Define clocks
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*----------------------------------------------------------------------------*/
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#define SYSTEM_CLOCK (32000000UL)
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/*----------------------------------------------------------------------------
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Vector Table
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*----------------------------------------------------------------------------*/
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#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/*----------------------------------------------------------------------------
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System initialization function
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*----------------------------------------------------------------------------*/
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void system_bor_init(void)
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{
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HBN_BOR_CFG_Type borCfg = { 1 /* pu_bor */, 0 /* irq_bor_en */, 1 /* bor_vth */, 1 /* bor_sel */ };
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HBN_Set_BOR_Cfg(&borCfg);
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}
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void SystemInit(void)
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{
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uint32_t *p;
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uint32_t i = 0;
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uint32_t tmpVal = 0;
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__disable_irq();
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/* disable hardware_pullup_pull_down (reg_en_hw_pu_pd = 0) */
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tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
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tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
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BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
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/* GLB_Set_EM_Sel(GLB_EM_0KB); */
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tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC);
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tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, GLB_EM_0KB);
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BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal);
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/* Fix 26M xtal clkpll_sdmin */
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tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM);
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if (0x49D39D == BL_GET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN)) {
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tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x49D89E);
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BL_WR_REG(PDS_BASE, PDS_CLKPLL_SDM, tmpVal);
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}
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/* Restore default setting*/
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/* GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); */
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tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
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tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, UART_SIG_SWAP_NONE);
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BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
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/* GLB_JTAG_Sig_Swap_Set(JTAG_SIG_SWAP_NONE); */
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tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
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tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_JTAG_SWAP_SET, JTAG_SIG_SWAP_NONE);
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BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
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/* CLear all interrupt */
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p = (uint32_t *)(CLIC_HART0_ADDR + CLIC_INTIE);
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for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
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p[i] = 0;
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}
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p = (uint32_t *)(CLIC_HART0_ADDR + CLIC_INTIP);
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for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
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p[i] = 0;
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}
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/* init bor for all platform */
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system_bor_init();
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/* global IRQ enable */
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__enable_irq();
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}
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/*identify flash config automaticly*/
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extern BL_Err_Type flash_init(void);
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void System_Post_Init(void)
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{
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PDS_Trim_RC32M();
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HBN_Trim_RC32K();
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flash_init();
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} |