From 38c0944315a5e9e41cc864b31393aab8d022ca18 Mon Sep 17 00:00:00 2001 From: Justin Hammond Date: Fri, 8 Mar 2024 19:27:53 +0800 Subject: [PATCH] Config Boards --- .github/workflows/buildroot.yml | 1 + Config.in | 2 + README.md | 1 + .../dts/sg2002_licheervnano_sd.dts | 16 +- .../licheervnano/generated/cvi_board_memmap.h | 37 ---- board/sipeed/licheervnano/generated/cvipart.h | 3 - .../generated/uboot/cvi_board_init.c | 8 +- .../0001-fix-up-monitor-path.patch | 0 .../linux/0001-add-licheervnano-patches.patch | 78 ------- .../0001-add-licheervnano-patches.patch.old | 202 ------------------ ...5-fix-missing-power-pins-for-display.patch | 50 +++++ boot/Config.in | 2 +- boot/cvitek-fsbl/cvitek-fsbl.mk | 31 --- boot/{cvitek-fsbl => cvitekfsbl}/Config.in | 4 +- boot/cvitekfsbl/cvitekfsbl.mk | 31 +++ external.mk | 21 -- package/cvitekconfig/Config.in | 180 ++++++++++++++++ package/cvitekconfig/cvitekconfig.mk | 137 ++++++++++++ .../genconfig/licheervnano/memmap.py | 85 ++++++++ package/cvitekconfig/genconfig/mmap_conv.py | 131 ++++++++++++ 20 files changed, 628 insertions(+), 392 deletions(-) delete mode 100644 board/sipeed/licheervnano/generated/cvi_board_memmap.h rename board/sipeed/licheervnano/patches/{cvitek-fsbl => cvitekfsbl}/0001-fix-up-monitor-path.patch (100%) delete mode 100644 board/sipeed/licheervnano/patches/linux/0001-add-licheervnano-patches.patch delete mode 100644 board/sipeed/licheervnano/patches/uboot/0001-add-licheervnano-patches.patch.old create mode 100644 board/sipeed/licheervnano/patches/uboot/0005-fix-missing-power-pins-for-display.patch delete mode 100644 boot/cvitek-fsbl/cvitek-fsbl.mk rename boot/{cvitek-fsbl => cvitekfsbl}/Config.in (72%) create mode 100644 boot/cvitekfsbl/cvitekfsbl.mk create mode 100644 package/cvitekconfig/Config.in create mode 100644 package/cvitekconfig/cvitekconfig.mk create mode 100755 package/cvitekconfig/genconfig/licheervnano/memmap.py create mode 100755 package/cvitekconfig/genconfig/mmap_conv.py diff --git a/.github/workflows/buildroot.yml b/.github/workflows/buildroot.yml index 213fa71..09f6f7a 100644 --- a/.github/workflows/buildroot.yml +++ b/.github/workflows/buildroot.yml @@ -54,6 +54,7 @@ jobs: export BR_LICHEERVNANO_OVERLAY_PATH=$(pwd)/sg200x cd buildroot make BR2_EXTERNAL=$BR_LICHEERVNANO_OVERLAY_PATH ${{ matrix.target }} + make cvitekconfig make make ccache-stats - name: Pack diff --git a/Config.in b/Config.in index b6fa28f..951720a 100644 --- a/Config.in +++ b/Config.in @@ -1,3 +1,5 @@ +source "$BR2_EXTERNAL_LICHEERVNANO_BR_PATH/package/cvitekconfig/Config.in" + menu "Custom Packages" source "$BR2_EXTERNAL_LICHEERVNANO_BR_PATH/package/Config.in" endmenu diff --git a/README.md b/README.md index 7fde007..5d0a71e 100644 --- a/README.md +++ b/README.md @@ -9,6 +9,7 @@ git clone https://github.com/Fishwaldo/sg200x export BR_LICHEERVNANO_OVERLAY_PATH=$(pwd)/sg200x cd buildroot make BR2_EXTERNAL=$BR_LICHEERVNANO_OVERLAY_PATH sipeed_licheervnano_defconfig +make cvitekconfig make ``` diff --git a/board/sipeed/licheervnano/dts/sg2002_licheervnano_sd.dts b/board/sipeed/licheervnano/dts/sg2002_licheervnano_sd.dts index f9a9391..d8e6093 100644 --- a/board/sipeed/licheervnano/dts/sg2002_licheervnano_sd.dts +++ b/board/sipeed/licheervnano/dts/sg2002_licheervnano_sd.dts @@ -32,25 +32,15 @@ }; &cvi_vo { -#ifndef __UBOOT__ - /delete-property/ reset-gpio; -#else - // for uboot reset-gpio = <&porte 0 1>; -#endif - /delete-property/ pwm-gpio; + pwm-gpio = <&portb 0 1>; /delete-property/ power-ct-gpio; - + status = "okay"; }; &mipi_tx { - /delete-property/ pwm-gpio; -#ifndef __UBOOT__ - // for linux kernel reset-gpio = <&porte 0 1>; -#else - /delete-property/ reset-gpio; -#endif + pwm-gpio = <&porte 0 1>; /delete-property/ power-ct-gpio; status = "okay"; }; diff --git a/board/sipeed/licheervnano/generated/cvi_board_memmap.h b/board/sipeed/licheervnano/generated/cvi_board_memmap.h deleted file mode 100644 index 6f1e406..0000000 --- a/board/sipeed/licheervnano/generated/cvi_board_memmap.h +++ /dev/null @@ -1,37 +0,0 @@ -#ifndef __BOARD_MMAP__ab4bdb87__ -#define __BOARD_MMAP__ab4bdb87__ - -#define CONFIG_SYS_TEXT_BASE 0x80200000 /* offset 2.0MiB */ -#define CVIMMAP_ATF_SIZE 0x80000 /* 512.0KiB */ -#define CVIMMAP_BOOTLOGO_ADDR 0x8ab30000 /* offset 171.1875MiB */ -#define CVIMMAP_BOOTLOGO_SIZE 0x7d0000 /* 7.8125MiB */ -#define CVIMMAP_CONFIG_SYS_INIT_SP_ADDR 0x82800000 /* offset 40.0MiB */ -#define CVIMMAP_CVI_UPDATE_HEADER_ADDR 0x817ffc00 /* offset 23.9990234375MiB */ -#define CVIMMAP_CVI_UPDATE_HEADER_SIZE 0x400 /* 1.0KiB */ -#define CVIMMAP_DRAM_BASE 0x80000000 /* offset 0.0KiB */ -#define CVIMMAP_DRAM_SIZE 0x10000000 /* 256.0MiB */ -#define CVIMMAP_FRAMEBUFFER_ADDR 0x8ab30000 /* offset 171.1875MiB */ -#define CVIMMAP_FRAMEBUFFER_SIZE 0x7d0000 /* 7.8125MiB */ -#define CVIMMAP_FREERTOS_ADDR 0x8fe00000 /* offset 254.0MiB */ -#define CVIMMAP_FREERTOS_RESERVED_ION_SIZE 0x1600000 /* 22.0MiB */ -#define CVIMMAP_FREERTOS_SIZE 0x200000 /* 2.0MiB */ -#define CVIMMAP_FSBL_C906L_START_ADDR 0x8fe00000 /* offset 254.0MiB */ -#define CVIMMAP_FSBL_UNZIP_ADDR 0x81800000 /* offset 24.0MiB */ -#define CVIMMAP_FSBL_UNZIP_SIZE 0x1000000 /* 16.0MiB */ -#define CVIMMAP_H26X_BITSTREAM_ADDR 0x8b300000 /* offset 179.0MiB */ -#define CVIMMAP_H26X_BITSTREAM_SIZE 0x200000 /* 2.0MiB */ -#define CVIMMAP_H26X_ENC_BUFF_ADDR 0x8b500000 /* offset 181.0MiB */ -#define CVIMMAP_H26X_ENC_BUFF_SIZE 0x0 /* 0.0KiB */ -#define CVIMMAP_ION_ADDR 0x8b300000 /* offset 179.0MiB */ -#define CVIMMAP_ION_SIZE 0x4b00000 /* 75.0MiB */ -#define CVIMMAP_ISP_MEM_BASE_ADDR 0x8b500000 /* offset 181.0MiB */ -#define CVIMMAP_ISP_MEM_BASE_SIZE 0x1400000 /* 20.0MiB */ -#define CVIMMAP_KERNEL_MEMORY_ADDR 0x80000000 /* offset 0.0KiB */ -#define CVIMMAP_KERNEL_MEMORY_SIZE 0xfe00000 /* 254.0MiB */ -#define CVIMMAP_MONITOR_ADDR 0x80000000 /* offset 0.0KiB */ -#define CVIMMAP_OPENSBI_FDT_ADDR 0x80080000 /* offset 512.0KiB */ -#define CVIMMAP_OPENSBI_SIZE 0x80000 /* 512.0KiB */ -#define CVIMMAP_UIMAG_ADDR 0x81800000 /* offset 24.0MiB */ -#define CVIMMAP_UIMAG_SIZE 0x1000000 /* 16.0MiB */ - -#endif /* __BOARD_MMAP__ab4bdb87__ */ diff --git a/board/sipeed/licheervnano/generated/cvipart.h b/board/sipeed/licheervnano/generated/cvipart.h index 067fce6..219a02b 100644 --- a/board/sipeed/licheervnano/generated/cvipart.h +++ b/board/sipeed/licheervnano/generated/cvipart.h @@ -2,9 +2,6 @@ #ifndef CVIPART_H #define CVIPART_H -#ifndef CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_IS_NOWHERE -#endif #define CONFIG_ENV_SIZE 0x20000 #define PART_LAYOUT "" #define ROOTFS_DEV "/dev/mmcblk0p2" diff --git a/board/sipeed/licheervnano/generated/uboot/cvi_board_init.c b/board/sipeed/licheervnano/generated/uboot/cvi_board_init.c index d8bb55b..42455d8 100644 --- a/board/sipeed/licheervnano/generated/uboot/cvi_board_init.c +++ b/board/sipeed/licheervnano/generated/uboot/cvi_board_init.c @@ -57,10 +57,10 @@ int cvi_board_init(void) mmio_write_32(0x030010E4, 0x0); // CLK // uart bluetooth - mmio_write_32(0x03001070, 0x1); // GPIOA 28 UART1 TX - mmio_write_32(0x03001074, 0x1); // GPIOA 29 UART1 RX - mmio_write_32(0x03001068, 0x4); // GPIOA 18 UART1 CTS - mmio_write_32(0x03001064, 0x4); // GPIOA 19 UART1 RTS + //mmio_write_32(0x03001070, 0x1); // GPIOA 28 UART1 TX + //mmio_write_32(0x03001074, 0x1); // GPIOA 29 UART1 RX + //mmio_write_32(0x03001068, 0x4); // GPIOA 18 UART1 CTS + //mmio_write_32(0x03001064, 0x4); // GPIOA 19 UART1 RTS // PWM //mmio_write_32(0x03001068, 0x2); // GPIOA 18 PWM 6 diff --git a/board/sipeed/licheervnano/patches/cvitek-fsbl/0001-fix-up-monitor-path.patch b/board/sipeed/licheervnano/patches/cvitekfsbl/0001-fix-up-monitor-path.patch similarity index 100% rename from board/sipeed/licheervnano/patches/cvitek-fsbl/0001-fix-up-monitor-path.patch rename to board/sipeed/licheervnano/patches/cvitekfsbl/0001-fix-up-monitor-path.patch diff --git a/board/sipeed/licheervnano/patches/linux/0001-add-licheervnano-patches.patch b/board/sipeed/licheervnano/patches/linux/0001-add-licheervnano-patches.patch deleted file mode 100644 index 32d0f70..0000000 --- a/board/sipeed/licheervnano/patches/linux/0001-add-licheervnano-patches.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 83e8586b20da0e1a40ae96bdd88cfd7963b1e5e8 Mon Sep 17 00:00:00 2001 -From: Justin Hammond -Date: Tue, 5 Mar 2024 17:56:41 +0800 -Subject: [PATCH] add licheervnano patches - ---- - include/cvi_board_memmap.h | 37 +++++++++++ - include/cvipart.h | 13 ++++ - 4 files changed, 153 insertions(+), 1 deletion(-) - create mode 100644 include/cvi_board_memmap.h - create mode 100644 include/cvipart.h - -diff --git a/include/cvi_board_memmap.h b/include/cvi_board_memmap.h -new file mode 100644 -index 0000000000..6f1e4068d6 ---- /dev/null -+++ b/include/cvi_board_memmap.h -@@ -0,0 +1,37 @@ -+#ifndef __BOARD_MMAP__ab4bdb87__ -+#define __BOARD_MMAP__ab4bdb87__ -+ -+#define CONFIG_SYS_TEXT_BASE 0x80200000 /* offset 2.0MiB */ -+#define CVIMMAP_ATF_SIZE 0x80000 /* 512.0KiB */ -+#define CVIMMAP_BOOTLOGO_ADDR 0x8ab30000 /* offset 171.1875MiB */ -+#define CVIMMAP_BOOTLOGO_SIZE 0x7d0000 /* 7.8125MiB */ -+#define CVIMMAP_CONFIG_SYS_INIT_SP_ADDR 0x82800000 /* offset 40.0MiB */ -+#define CVIMMAP_CVI_UPDATE_HEADER_ADDR 0x817ffc00 /* offset 23.9990234375MiB */ -+#define CVIMMAP_CVI_UPDATE_HEADER_SIZE 0x400 /* 1.0KiB */ -+#define CVIMMAP_DRAM_BASE 0x80000000 /* offset 0.0KiB */ -+#define CVIMMAP_DRAM_SIZE 0x10000000 /* 256.0MiB */ -+#define CVIMMAP_FRAMEBUFFER_ADDR 0x8ab30000 /* offset 171.1875MiB */ -+#define CVIMMAP_FRAMEBUFFER_SIZE 0x7d0000 /* 7.8125MiB */ -+#define CVIMMAP_FREERTOS_ADDR 0x8fe00000 /* offset 254.0MiB */ -+#define CVIMMAP_FREERTOS_RESERVED_ION_SIZE 0x1600000 /* 22.0MiB */ -+#define CVIMMAP_FREERTOS_SIZE 0x200000 /* 2.0MiB */ -+#define CVIMMAP_FSBL_C906L_START_ADDR 0x8fe00000 /* offset 254.0MiB */ -+#define CVIMMAP_FSBL_UNZIP_ADDR 0x81800000 /* offset 24.0MiB */ -+#define CVIMMAP_FSBL_UNZIP_SIZE 0x1000000 /* 16.0MiB */ -+#define CVIMMAP_H26X_BITSTREAM_ADDR 0x8b300000 /* offset 179.0MiB */ -+#define CVIMMAP_H26X_BITSTREAM_SIZE 0x200000 /* 2.0MiB */ -+#define CVIMMAP_H26X_ENC_BUFF_ADDR 0x8b500000 /* offset 181.0MiB */ -+#define CVIMMAP_H26X_ENC_BUFF_SIZE 0x0 /* 0.0KiB */ -+#define CVIMMAP_ION_ADDR 0x8b300000 /* offset 179.0MiB */ -+#define CVIMMAP_ION_SIZE 0x4b00000 /* 75.0MiB */ -+#define CVIMMAP_ISP_MEM_BASE_ADDR 0x8b500000 /* offset 181.0MiB */ -+#define CVIMMAP_ISP_MEM_BASE_SIZE 0x1400000 /* 20.0MiB */ -+#define CVIMMAP_KERNEL_MEMORY_ADDR 0x80000000 /* offset 0.0KiB */ -+#define CVIMMAP_KERNEL_MEMORY_SIZE 0xfe00000 /* 254.0MiB */ -+#define CVIMMAP_MONITOR_ADDR 0x80000000 /* offset 0.0KiB */ -+#define CVIMMAP_OPENSBI_FDT_ADDR 0x80080000 /* offset 512.0KiB */ -+#define CVIMMAP_OPENSBI_SIZE 0x80000 /* 512.0KiB */ -+#define CVIMMAP_UIMAG_ADDR 0x81800000 /* offset 24.0MiB */ -+#define CVIMMAP_UIMAG_SIZE 0x1000000 /* 16.0MiB */ -+ -+#endif /* __BOARD_MMAP__ab4bdb87__ */ -diff --git a/include/cvipart.h b/include/cvipart.h -new file mode 100644 -index 0000000000..067fce6bda ---- /dev/null -+++ b/include/cvipart.h -@@ -0,0 +1,13 @@ -+/* this file should be generated by mkcvipart.py,please do not modify this file manually*/ -+ -+#ifndef CVIPART_H -+#define CVIPART_H -+#ifndef CONFIG_ENV_IS_NOWHERE -+#define CONFIG_ENV_IS_NOWHERE -+#endif -+#define CONFIG_ENV_SIZE 0x20000 -+#define PART_LAYOUT "" -+#define ROOTFS_DEV "/dev/mmcblk0p2" -+#define PARTS_OFFSET "" -+#define SPL_BOOT_PART_OFFSET 0x0 -+#endif -\ No newline at end of file --- -2.44.0 - diff --git a/board/sipeed/licheervnano/patches/uboot/0001-add-licheervnano-patches.patch.old b/board/sipeed/licheervnano/patches/uboot/0001-add-licheervnano-patches.patch.old deleted file mode 100644 index e9d5037..0000000 --- a/board/sipeed/licheervnano/patches/uboot/0001-add-licheervnano-patches.patch.old +++ /dev/null @@ -1,202 +0,0 @@ -From 83e8586b20da0e1a40ae96bdd88cfd7963b1e5e8 Mon Sep 17 00:00:00 2001 -From: Justin Hammond -Date: Tue, 5 Mar 2024 17:56:41 +0800 -Subject: [PATCH] add licheervnano patches - ---- - board/cvitek/mars/board.c | 2 +- - board/cvitek/mars/cvi_board_init.c | 102 +++++++++++++++++++++++++++++ - include/cvi_board_memmap.h | 37 +++++++++++ - include/cvipart.h | 13 ++++ - 4 files changed, 153 insertions(+), 1 deletion(-) - create mode 100644 board/cvitek/mars/cvi_board_init.c - create mode 100644 include/cvi_board_memmap.h - create mode 100644 include/cvipart.h - -diff --git a/board/cvitek/mars/board.c b/board/cvitek/mars/board.c -index 9c961ac149..2fac11353e 100644 ---- a/board/cvitek/mars/board.c -+++ b/board/cvitek/mars/board.c -@@ -152,7 +152,7 @@ void pinmux_config(int io_type) - } - } - --#include "../cvi_board_init.c" -+#include "cvi_board_init.c" - - #if defined(CONFIG_PHY_CVITEK) /* config cvitek cv181x eth internal phy on ASIC board */ - static void cv181x_ephy_id_init(void) -diff --git a/board/cvitek/mars/cvi_board_init.c b/board/cvitek/mars/cvi_board_init.c -new file mode 100644 -index 0000000000..d8bb55b693 ---- /dev/null -+++ b/board/cvitek/mars/cvi_board_init.c -@@ -0,0 +1,102 @@ -+__attribute__((optimize("O0"))) -+// 1.26ms -+void suck_loop(uint64_t loop) { -+ loop = loop * 50 * 100; -+ uint64_t a; -+ while (loop > 0) { -+ a = loop / (uint64_t)99; -+ a = loop / (uint64_t)77; -+ a = loop / (uint64_t)55; -+ a = loop / (uint64_t)33; -+ a = loop / (uint64_t)11; -+ a = loop / (uint64_t)999; -+ a = loop / (uint64_t)777; -+ a = loop / (uint64_t)555; -+ a = loop / (uint64_t)333; -+ a = loop / (uint64_t)111; -+ a = loop / (uint64_t)9999; -+ a = loop / (uint64_t)7777; -+ a = loop / (uint64_t)5555; -+ a = loop / (uint64_t)3333; -+ a = loop / (uint64_t)1111; -+ a = loop / (uint64_t)99999; -+ a = loop / (uint64_t)77777; -+ a = loop / (uint64_t)55555; -+ a = loop / (uint64_t)33333; -+ a = loop / (uint64_t)11111; -+ loop--; -+ } -+} -+ -+int cvi_board_init(void) -+{ -+ uint32_t val; -+ -+ // wifi power reset -+ mmio_write_32(0x0300104C, 0x3); // GPIOA 26 -+ val = mmio_read_32(0x03020004); // GPIOA DIR -+ val |= (1 << 26); // output -+ mmio_write_32(0x03020004, val); -+ -+ val = mmio_read_32(0x03020000); // signal level -+ val &= ~(1 << 26); // set level to low -+ mmio_write_32(0x03020000, val); -+ -+ suck_loop(200); -+ -+ val = mmio_read_32(0x03020000); // signal level -+ val |= (1 << 26); // set level to high -+ mmio_write_32(0x03020000, val); -+ -+ // wifi sdio pinmux -+ mmio_write_32(0x030010D0, 0x0); // D3 -+ mmio_write_32(0x030010D4, 0x0); // D2 -+ mmio_write_32(0x030010D8, 0x0); // D1 -+ mmio_write_32(0x030010DC, 0x0); // D0 -+ mmio_write_32(0x030010E0, 0x0); // CMD -+ mmio_write_32(0x030010E4, 0x0); // CLK -+ -+ // uart bluetooth -+ mmio_write_32(0x03001070, 0x1); // GPIOA 28 UART1 TX -+ mmio_write_32(0x03001074, 0x1); // GPIOA 29 UART1 RX -+ mmio_write_32(0x03001068, 0x4); // GPIOA 18 UART1 CTS -+ mmio_write_32(0x03001064, 0x4); // GPIOA 19 UART1 RTS -+ -+ // PWM -+ //mmio_write_32(0x03001068, 0x2); // GPIOA 18 PWM 6 -+ -+ // lcd reset -+ mmio_write_32(0x030010A4, 0x0); // PWRGPIO 0 GPIO_MODE -+ -+ // lcd backlight -+ //mmio_write_32(0x030010EC, 0x0); // GPIOB 0 PWM0_BUCK -+ mmio_write_32(0x030010EC, 0x3); // GPIOB 0 GPIO_MODE -+ val = mmio_read_32(0x03021004); // GPIOB DIR -+ val |= (1 << 0); // output -+ mmio_write_32(0x03021004, val); -+ val = mmio_read_32(0x03021000); // signal level -+ val |= (1 << 0); // set level to high -+ mmio_write_32(0x03021000, val); -+ -+ // camera function -+ mmio_write_32(0x0300116C, 0x5); // RX4N CAM_MCLK0 -+ -+ // camera/tp i2c -+ mmio_write_32(0x03001090, 0x5); // PWR_GPIO6 IIC4_SCL -+ mmio_write_32(0x03001098, 0x5); // PWR_GPIO8 IIC4_SDA -+ -+ // tp function -+ mmio_write_32(0x03001084, 0x3); // PWR_SEQ1 PWR_GPIO[3] -+ mmio_write_32(0x03001088, 0x3); // PWR_SEQ2 PWR_GPIO[4] -+ mmio_write_32(0x05027078, 0x11);// Unlock PWR_GPIO[3] -+ mmio_write_32(0x0502707c, 0x11);// Unlock PWR_GPIO[4] -+ -+ // bitbang i2c for maixcam -+#ifdef MAIXCAM -+ mmio_write_32(0x0300105C, 0x3);// GPIOA 23 GPIO_MODE -+ mmio_write_32(0x03001060, 0x3);// GPIOA 24 GPIO_MODE -+#endif -+ // wait hardware bootup -+ suck_loop(100); -+ return 0; -+} -diff --git a/include/cvi_board_memmap.h b/include/cvi_board_memmap.h -new file mode 100644 -index 0000000000..6f1e4068d6 ---- /dev/null -+++ b/include/cvi_board_memmap.h -@@ -0,0 +1,37 @@ -+#ifndef __BOARD_MMAP__ab4bdb87__ -+#define __BOARD_MMAP__ab4bdb87__ -+ -+#define CONFIG_SYS_TEXT_BASE 0x80200000 /* offset 2.0MiB */ -+#define CVIMMAP_ATF_SIZE 0x80000 /* 512.0KiB */ -+#define CVIMMAP_BOOTLOGO_ADDR 0x8ab30000 /* offset 171.1875MiB */ -+#define CVIMMAP_BOOTLOGO_SIZE 0x7d0000 /* 7.8125MiB */ -+#define CVIMMAP_CONFIG_SYS_INIT_SP_ADDR 0x82800000 /* offset 40.0MiB */ -+#define CVIMMAP_CVI_UPDATE_HEADER_ADDR 0x817ffc00 /* offset 23.9990234375MiB */ -+#define CVIMMAP_CVI_UPDATE_HEADER_SIZE 0x400 /* 1.0KiB */ -+#define CVIMMAP_DRAM_BASE 0x80000000 /* offset 0.0KiB */ -+#define CVIMMAP_DRAM_SIZE 0x10000000 /* 256.0MiB */ -+#define CVIMMAP_FRAMEBUFFER_ADDR 0x8ab30000 /* offset 171.1875MiB */ -+#define CVIMMAP_FRAMEBUFFER_SIZE 0x7d0000 /* 7.8125MiB */ -+#define CVIMMAP_FREERTOS_ADDR 0x8fe00000 /* offset 254.0MiB */ -+#define CVIMMAP_FREERTOS_RESERVED_ION_SIZE 0x1600000 /* 22.0MiB */ -+#define CVIMMAP_FREERTOS_SIZE 0x200000 /* 2.0MiB */ -+#define CVIMMAP_FSBL_C906L_START_ADDR 0x8fe00000 /* offset 254.0MiB */ -+#define CVIMMAP_FSBL_UNZIP_ADDR 0x81800000 /* offset 24.0MiB */ -+#define CVIMMAP_FSBL_UNZIP_SIZE 0x1000000 /* 16.0MiB */ -+#define CVIMMAP_H26X_BITSTREAM_ADDR 0x8b300000 /* offset 179.0MiB */ -+#define CVIMMAP_H26X_BITSTREAM_SIZE 0x200000 /* 2.0MiB */ -+#define CVIMMAP_H26X_ENC_BUFF_ADDR 0x8b500000 /* offset 181.0MiB */ -+#define CVIMMAP_H26X_ENC_BUFF_SIZE 0x0 /* 0.0KiB */ -+#define CVIMMAP_ION_ADDR 0x8b300000 /* offset 179.0MiB */ -+#define CVIMMAP_ION_SIZE 0x4b00000 /* 75.0MiB */ -+#define CVIMMAP_ISP_MEM_BASE_ADDR 0x8b500000 /* offset 181.0MiB */ -+#define CVIMMAP_ISP_MEM_BASE_SIZE 0x1400000 /* 20.0MiB */ -+#define CVIMMAP_KERNEL_MEMORY_ADDR 0x80000000 /* offset 0.0KiB */ -+#define CVIMMAP_KERNEL_MEMORY_SIZE 0xfe00000 /* 254.0MiB */ -+#define CVIMMAP_MONITOR_ADDR 0x80000000 /* offset 0.0KiB */ -+#define CVIMMAP_OPENSBI_FDT_ADDR 0x80080000 /* offset 512.0KiB */ -+#define CVIMMAP_OPENSBI_SIZE 0x80000 /* 512.0KiB */ -+#define CVIMMAP_UIMAG_ADDR 0x81800000 /* offset 24.0MiB */ -+#define CVIMMAP_UIMAG_SIZE 0x1000000 /* 16.0MiB */ -+ -+#endif /* __BOARD_MMAP__ab4bdb87__ */ -diff --git a/include/cvipart.h b/include/cvipart.h -new file mode 100644 -index 0000000000..067fce6bda ---- /dev/null -+++ b/include/cvipart.h -@@ -0,0 +1,13 @@ -+/* this file should be generated by mkcvipart.py,please do not modify this file manually*/ -+ -+#ifndef CVIPART_H -+#define CVIPART_H -+#ifndef CONFIG_ENV_IS_NOWHERE -+#define CONFIG_ENV_IS_NOWHERE -+#endif -+#define CONFIG_ENV_SIZE 0x20000 -+#define PART_LAYOUT "" -+#define ROOTFS_DEV "/dev/mmcblk0p2" -+#define PARTS_OFFSET "" -+#define SPL_BOOT_PART_OFFSET 0x0 -+#endif -\ No newline at end of file --- -2.44.0 - diff --git a/board/sipeed/licheervnano/patches/uboot/0005-fix-missing-power-pins-for-display.patch b/board/sipeed/licheervnano/patches/uboot/0005-fix-missing-power-pins-for-display.patch new file mode 100644 index 0000000..5a768d2 --- /dev/null +++ b/board/sipeed/licheervnano/patches/uboot/0005-fix-missing-power-pins-for-display.patch @@ -0,0 +1,50 @@ +From b44e15166faafac4df0955b1dce740db981b7f0a Mon Sep 17 00:00:00 2001 +From: Justin Hammond +Date: Fri, 8 Mar 2024 17:55:06 +0800 +Subject: [PATCH] fix missing power pins for display + +--- + drivers/video/cvitek/cvi_disp.c | 3 +++ + drivers/video/cvitek/cvi_mipi.c | 3 +++ + 2 files changed, 6 insertions(+) + +diff --git a/drivers/video/cvitek/cvi_disp.c b/drivers/video/cvitek/cvi_disp.c +index 23ce46b149..e0215a212d 100644 +--- a/drivers/video/cvitek/cvi_disp.c ++++ b/drivers/video/cvitek/cvi_disp.c +@@ -97,11 +97,14 @@ static int cvi_vo_probe(struct udevice *dev) + } + ret = gpio_request_by_name(dev, "power-ct-gpio", 0, &priv->ctrl_gpios.disp_power_ct_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); ++#if 0 ++ /* ignore errors if the power control pin is missing */ + if (ret) { + printf("%s: Warning: cannot get power GPIO: ret=%d\n", __func__, ret); + if (ret != -ENOENT) + return ret; + } ++#endif + set_disp_ctrl_gpios(&priv->ctrl_gpios); + + video_set_flush_dcache(dev, 1); +diff --git a/drivers/video/cvitek/cvi_mipi.c b/drivers/video/cvitek/cvi_mipi.c +index 3a04573517..75b3590641 100644 +--- a/drivers/video/cvitek/cvi_mipi.c ++++ b/drivers/video/cvitek/cvi_mipi.c +@@ -150,10 +150,13 @@ int mipi_tx_set_combo_dev_cfg(const struct combo_dev_cfg_s *dev_cfg) + + ret = dm_gpio_set_value(&ctrl_gpios.disp_power_ct_gpio, + ctrl_gpios.disp_power_ct_gpio.flags & GPIOD_ACTIVE_LOW ? 0 : 1); ++#if 0 ++/* ignore errors if the power control pin is missing/invalid */ + if (ret < 0) { + printf("dm_gpio_set_value(disp_power_ct_gpio, deassert) failed: %d", ret); + return ret; + } ++#endif + ret = dm_gpio_set_value(&ctrl_gpios.disp_pwm_gpio, + ctrl_gpios.disp_pwm_gpio.flags & GPIOD_ACTIVE_LOW ? 0 : 1); + if (ret < 0) { +-- +2.44.0 + diff --git a/boot/Config.in b/boot/Config.in index bd1eac6..72b9cef 100644 --- a/boot/Config.in +++ b/boot/Config.in @@ -1 +1 @@ -source "$BR2_EXTERNAL_LICHEERVNANO_BR_PATH/boot/cvitek-fsbl/Config.in" \ No newline at end of file +source "$BR2_EXTERNAL_LICHEERVNANO_BR_PATH/boot/cvitekfsbl/Config.in" \ No newline at end of file diff --git a/boot/cvitek-fsbl/cvitek-fsbl.mk b/boot/cvitek-fsbl/cvitek-fsbl.mk deleted file mode 100644 index 10dcd65..0000000 --- a/boot/cvitek-fsbl/cvitek-fsbl.mk +++ /dev/null @@ -1,31 +0,0 @@ -################################################################################ -# -# cvitek-fsbl -# -################################################################################ - -CVITEK_FSBL_VERSION = 415722ebd855abef2ba11e9cba3d80106d250eff -CVITEK_FSBL_SITE = $(call github,sophgo,fsbl,$(CVITEK_FSBL_VERSION)) -CVITEK_FSBL_LICENSE = GPL-2.0 -CVITEK_FSBL_DEPENDENCIES = linux opensbi uboot -CVITEK_FSBL_INSTALL_IMAGES = YES - - -CVITEK_FSBL_MAKE_ENV = \ - CROSS_COMPILE=$(TARGET_CROSS) \ - CROSS_COMPILE_GLIBC_RISCV64=$(TARGET_CROSS) \ - CHIP_ARCH=sg200x \ - ARCH=riscv \ - DDR_CFG=ddr3_1866_x16 \ - FW_DYNAMIC=$(BINARIES_DIR)/fw_dynamic.bin - - -define CVITEK_FSBL_BUILD_CMDS - $(CVITEK_FSBL_MAKE_ENV) $(MAKE) -C $(@D) CFLAGS="-fno-stack-protector" LOADER_2ND_PATH=$(BINARIES_DIR)/u-boot.bin -endef - -define CVITEK_FSBL_INSTALL_IMAGES_CMDS - $(INSTALL) -D -m 0755 $(@D)/build/sg200x/fip.bin $(BINARIES_DIR)/fip.bin -endef - -$(eval $(generic-package)) diff --git a/boot/cvitek-fsbl/Config.in b/boot/cvitekfsbl/Config.in similarity index 72% rename from boot/cvitek-fsbl/Config.in rename to boot/cvitekfsbl/Config.in index de2737d..0190846 100644 --- a/boot/cvitek-fsbl/Config.in +++ b/boot/cvitekfsbl/Config.in @@ -1,10 +1,10 @@ comment "cvitek FSBL options" depends on !BR2_LINUX_KERNEL -config BR2_PACKAGE_CVITEK_FSBL +config BR2_TARGET_CVITEKFSBL bool "cvitek FSBL" depends on BR2_LINUX_KERNEL depends on BR2_TARGET_OPENSBI depends on BR2_TARGET_UBOOT help - First Stage Boot Loader + First Stage Boot Loader for cvitek diff --git a/boot/cvitekfsbl/cvitekfsbl.mk b/boot/cvitekfsbl/cvitekfsbl.mk new file mode 100644 index 0000000..c9a3258 --- /dev/null +++ b/boot/cvitekfsbl/cvitekfsbl.mk @@ -0,0 +1,31 @@ +################################################################################ +# +# cvitek-fsbl +# +################################################################################ + +CVITEKFSBL_VERSION = 415722ebd855abef2ba11e9cba3d80106d250eff +CVITEKFSBL_SITE = $(call github,sophgo,fsbl,$(CVITEKFSBL_VERSION)) +CVITEKFSBL_LICENSE = GPL-2.0 +CVITEKFSBL_DEPENDENCIES = opensbi uboot +CVITEKFSBL_INSTALL_IMAGES = YES + + +CVITEKFSBL_MAKE_ENV = \ + CROSS_COMPILE=$(TARGET_CROSS) \ + CROSS_COMPILE_GLIBC_RISCV64=$(TARGET_CROSS) \ + CHIP_ARCH=$(BR2_PACKAGE_CVITEKCONFIG_CHIP_ARCH) \ + ARCH=$(BR2_PACKAGE_CVITEKCONFIG_ARCH) \ + DDR_CFG=$(BR2_PACKAGE_CVITEKCONFIG_DDR) \ + FW_DYNAMIC=$(BINARIES_DIR)/fw_dynamic.bin + + +define CVITEKFSBL_BUILD_CMDS + $(CVITEKFSBL_MAKE_ENV) $(MAKE) -C $(@D) CFLAGS="-fno-stack-protector" LOADER_2ND_PATH=$(BINARIES_DIR)/u-boot.bin +endef + +define CVITEKFSBL_INSTALL_IMAGES_CMDS + $(INSTALL) -D -m 0755 $(@D)/build/$(BR2_PACKAGE_CVITEKCONFIG_CHIP_ARCH)/fip.bin $(BINARIES_DIR)/fip.bin +endef + +$(eval $(generic-package)) diff --git a/external.mk b/external.mk index c8c6dee..964b57f 100644 --- a/external.mk +++ b/external.mk @@ -1,24 +1,3 @@ include $(sort $(wildcard $(BR2_EXTERNAL_LICHEERVNANO_BR_PATH)/package/*/*.mk)) include $(sort $(wildcard $(BR2_EXTERNAL_LICHEERVNANO_BR_PATH)/boot/*/*.mk)) -UBOOT_POST_PATCH_HOOKS += UBOOT_APPLY_SG2002_CONFIG_HOOK -LINUX_POST_PATCH_HOOKS += LINUX_APPLY_SG2002_CONFIG_HOOK -CVITEK_FSBL_POST_PATCH_HOOKS += CVITEK_FSBL_APPLY_SG2002_CONFIG_HOOK - -define UBOOT_APPLY_SG2002_CONFIG_HOOK - @echo "Applying SG2002 Generated Config" - @cp $(BR2_GLOBAL_PATCH_DIR)../generated/cvi_board_memmap.h $(@D)/include/cvi_board_memmap.h - @cp $(BR2_GLOBAL_PATCH_DIR)../generated/cvipart.h $(@D)/include/cvipart.h - @cp $(BR2_GLOBAL_PATCH_DIR)../generated/uboot/cvi_board_init.c $(@D)/board/cvitek/ -endef - -define LINUX_APPLY_SG2002_CONFIG_HOOK - @echo "Applying SG2002 Generated Config" - @cp $(BR2_GLOBAL_PATCH_DIR)../generated/cvi_board_memmap.h $(@D)/include/cvi_board_memmap.h - @cp $(BR2_GLOBAL_PATCH_DIR)../generated/cvipart.h $(@D)/include/cvipart.h -endef - -define CVITEK_FSBL_APPLY_SG2002_CONFIG_HOOK - @echo "Applying SG2002 Generated Config" - @cp $(BR2_GLOBAL_PATCH_DIR)../generated/cvi_board_memmap.h $(@D)/include/cvi_board_memmap.h -endef diff --git a/package/cvitekconfig/Config.in b/package/cvitekconfig/Config.in new file mode 100644 index 0000000..d3c3a01 --- /dev/null +++ b/package/cvitekconfig/Config.in @@ -0,0 +1,180 @@ +comment "Config For cvitek based boards" + depends on !BR2_LINUX_KERNEL + +config BR2_PACKAGE_CVITEKCONFIG + bool + default y + +menu "CVITEK Configuration" + +choice BR2_PACKAGE_CVITEK_BOARD + prompt "Board" + + config BR2_PACKAGE_CVITEKCONFIG_BOARD_LICHEERVNANO + bool "LicheeRV Nano" + help + Select this option if you are using a LicheeRV Nano board. + + config BR2_PACKAGE_CVITEKCONFIG_BOARD_TEST + bool "Test" + help + Select this option if you are using a test board. +endchoice + +config BR2_PACKAGE_CVITEKCONFIG_ALLOCATE_FREERTOS_HEAP + int "Memory to allocate for FreeRTOS heap" + default 2 + range 0 256 + help + Allocate FreeRTOS heap from the end of the RAM. + +config BR2_PACKAGE_CVITEKCONFIG_ALLOCATE_ION_HEAP + int "Memory to allocate for ION heap" + default 75 + range 0 256 + help + Allocate ION heap from the end of the RAM. + +config BR2_PACKAGE_CVITEKCONFIG_ALLOCATE_H26X_BITSTREAM_HEAP + int "Memory to allocate for H26X BitStream heap" + default 2 + range 0 BR2_PACKAGE_CVITEKCONFIG_ALLOCATE_ION_HEAP + help + Allocate H264 Bitstream heap from the end of the RAM. + It Must fit in the ION Heap Size (including what is allocated for ISP Heap) + +config BR2_PACKAGE_CVITEKCONFIG_ALLOCATE_ISP_HEAP + int "Memory to allocate for ISP heap" + default 20 + range 0 BR2_PACKAGE_CVITEKCONFIG_ALLOCATE_ION_HEAP + help + Allocate ISP heap from the end of the RAM. + It Must fit in the ION Heap Size (including what is allocated for H26X Heap) + + + +choice BR2_PACKAGE_CVITEKCONFIG_PANEL + prompt "Panel Configured" + + config BR2_PACKAGE_CVITEKCONFIG_PANEL_NONE + bool "None" + help + Select this option if you are not using any panel. + + config BR2_PACKAGE_CVITEKCONFIG_PANEL_ZCT2133V1 + bool "zct2133v1" + help + Select this option if you are using a zct2133v1 panel. + + config BR2_PACKAGE_CVITEKCONFIG_PANEL_HX8394 + bool "hx8394" + help + Select this option if you are using a hx8394-720x1280 panel. + + config BR2_PACKAGE_CVITEKCONFIG_PANEL_ILI9881C + bool "ili9881c" + help + Select this option if you are using a ili9881c panel. + + config BR2_PACKAGE_CVITEKCONFIG_PANEL_ILI9881D + bool "ili9881d" + help + Select this option if you are using a ili9881d panel. + + config BR2_PACKAGE_CVITEKCONFIG_PANEL_JD9366AB + bool "jd9366ab" + help + Select this option if you are using a jd9366ab panel. + + config BR2_PACKAGE_CVITEKCONFIG_PANEL_NT35521 + bool "nt35521" + help + Select this option if you are using a nt35521 panel. + + config BR2_PACKAGE_CVITEKCONFIG_PANEL_OTA7290B + bool "ota7290b" + help + Select this option if you are using a ota7290b panel. + + config BR2_PACKAGE_CVITEKCONFIG_PANEL_ST7701_D300FPC9307A + bool "st7701_d300fpc9307a" + help + Select this option if you are using a st7701_d300fpc9307a panel. + + config BR2_PACKAGE_CVITEKCONFIG_PANEL_OTA7290B + bool "ota7290b" + help + Select this option if you are using a ota7290b panel. + + config BR2_PACKAGE_CVITEKCONFIG_PANEL_ICN9707 + bool "icn9707" + help + Select this option if you are using a icn9707 panel. + + config BR2_PACKAGE_CVITEKCONFIG_PANEL_ST7701_DXQ5D0019B480854 + bool "st7701_dxq5d0019b480854" + help + Select this option if you are using a st7701_dxq5d0019b480854 panel. + + config BR2_PACKAGE_CVITEKCONFIG_PANEL_3AML069LP01G + bool "3aml069lp01g" + help + Select this option if you are using a 3aml069lp01g panel. + + config BR2_PACKAGE_CVITEKCONFIG_PANEL_ST7701 + bool "st7701 480x800" + help + Select this option if you are using a st7701 panel. + + config BR2_PACKAGE_CVITEKCONFIG_PANEL_ST7701_HD228001C31 + bool "st7701_hd228001c31 - 368x552" + help + Select this option if you are using a st7701_hd228001c31 panel. + + config BR2_PACKAGE_CVITEKCONFIG_PANEL_ST7785M + bool "st7785m" + help + Select this option if you are using a st7785m panel. + + config BR2_PACKAGE_CVITEKCONFIG_PANEL_ST7789V + bool "st7789v" + help + Select this option if you are using a st7789v panel. + + config BR2_PACKAGE_CVITEKCONFIG_PANEL_EK79202 + bool "ek79202" + help + Select this option if you are using a ek79202 panel. + +endchoice + +if BR2_PACKAGE_CVITEKCONFIG_BOARD_LICHEERVNANO + + config BR2_PACKAGE_CVITEKCONFIG_DDR + string + default "ddr3_1866_x16" + + config BR2_PACKAGE_CVITEKCONFIG_CHIP + string + default "sg2002" + + config BR2_PACKAGE_CVITEKCONFIG_CHIP_ARCH + string + default "sg200x" + + config BR2_PACKAGE_CVITEKCONFIG_ARCH + string + default "riscv" + + config BR2_PACKAGE_CVITEKCONFIG_BOARD_NAME + string + default "licheervnano" + + config BR2_PACKAGE_CVITEKCONFIG_STORAGE + string + default "sd" + + +endif + +endmenu diff --git a/package/cvitekconfig/cvitekconfig.mk b/package/cvitekconfig/cvitekconfig.mk new file mode 100644 index 0000000..051447f --- /dev/null +++ b/package/cvitekconfig/cvitekconfig.mk @@ -0,0 +1,137 @@ +################################################################################ +# +# cvitek-config +# +################################################################################ + +#CVITEKFSBL_VERSION = 415722ebd855abef2ba11e9cba3d80106d250eff +CVITEKCONFIG_SITE = $(BR2_EXTERNAL_LICHEERVNANO_BR_PATH)/package/cvitekconfig/genconfig +CVITEKCONFIG_SITE_METHOD = local +CVITEKCONFIG_LICENSE = GPL-2.0 +CVITEKCONFIG_DEPENDENCIES = host-python3 + +ifeq ($(BR2_PACKAGE_CVITEKCONFIG_BOARD_LICHEERVNANO),y) + CVITEKCONFIG_BOARD = licheervnano +else ifeq ($(BR2_PACKAGE_CVITEKCONFIG_BOARD_TEST),y) + CVITEKCONFIG_BOARD = test +endif + +ifdef BR2_PACKAGE_CVITEKCONFIG_ALLOCATE_FREERTOS_HEAP +define CVITEKCONFIG_SETFREERTOS + @echo "set FREERTOS_SIZE to $(BR2_PACKAGE_CVITEKCONFIG_ALLOCATE_FREERTOS_HEAP)" + @$(SED) 's/FREERTOS_SIZE = [[:digit:]]\+ \* SIZE_1M/FREERTOS_SIZE = $(BR2_PACKAGE_CVITEKCONFIG_ALLOCATE_FREERTOS_HEAP) \* SIZE_1M/g' $(@D)//memmap.py +endef +endif + +ifdef BR2_PACKAGE_CVITEKCONFIG_ALLOCATE_ION_HEAP +define CVITEKCONFIG_SETION + @echo "set ION_SIZE to $(BR2_PACKAGE_CVITEKCONFIG_ALLOCATE_ION_HEAP)" + @$(SED) 's/ION_SIZE = [[:digit:]]\+ \* SIZE_1M/ION_SIZE = $(BR2_PACKAGE_CVITEKCONFIG_ALLOCATE_ION_HEAP) \* SIZE_1M/g' $(@D)//memmap.py +endef +endif + +ifdef BR2_PACKAGE_CVITEKCONFIG_ALLOCATE_H26X_BITSTREAM_HEAP +define CVITEKCONFIG_SETH26X + @echo "set H26X_BITSTREAM_SIZE to $(BR2_PACKAGE_CVITEKCONFIG_ALLOCATE_H26X_BITSTREAM_HEAP)" + @$(SED) 's/H26X_BITSTREAM_SIZE = [[:digit:]]\+ \* SIZE_1M/H26X_BITSTREAM_SIZE = $(BR2_PACKAGE_CVITEKCONFIG_ALLOCATE_H26X_BITSTREAM_HEAP) \* SIZE_1M/g' $(@D)//memmap.py +endef +endif + +ifdef BR2_PACKAGE_CVITEKCONFIG_ALLOCATE_ISP_HEAP +define CVITEKCONFIG_SETISP + @echo "set ISP_MEM_BASE_SIZE to $(BR2_PACKAGE_CVITEKCONFIG_ALLOCATE_ISP_HEAP)" + @$(SED) 's/ISP_MEM_BASE_SIZE = [[:digit:]]\+ \* SIZE_1M/ISP_MEM_BASE_SIZE = $(BR2_PACKAGE_CVITEKCONFIG_ALLOCATE_ISP_HEAP) \* SIZE_1M/g' $(@D)//memmap.py +endef +endif + +define CVITEKCONFIG_BUILD_CMDS + @echo "CVITEKCONFIG_BUILD_CMDS - $(CVITEKCONFIG_BOARD)" + @cp $(@D)/$(CVITEKCONFIG_BOARD)/memmap.py $(@D)/memmap.py + $(CVITEKCONFIG_SETFREERTOS) + $(CVITEKCONFIG_SETION) + $(CVITEKCONFIG_SETH26X) + $(CVITEKCONFIG_SETISP) + @$(PYTHON) $(@D)/mmap_conv.py --type h $(@D)/memmap.py $(@D)/cvi_board_memmap.h + @$(PYTHON) $(@D)/mmap_conv.py --type ld $(@D)/memmap.py $(@D)/cvi_board_memmap.ld + @$(PYTHON) $(@D)/mmap_conv.py --type conf $(@D)/memmap.py $(@D)/cvi_board_memmap.conf +endef + +define CVITEKCONFIG_INSTALL_TARGET_CMDS + $(INSTALL) -D -m 0644 $(@D)/cvi_board_memmap.h $(TARGET_DIR)/include/cvi_board_memmap.h + $(INSTALL) -D -m 0644 $(@D)/cvi_board_memmap.ld $(TARGET_DIR)/include/cvi_board_memmap.ld + $(INSTALL) -D -m 0644 $(@D)/cvi_board_memmap.conf $(TARGET_DIR)/include/cvi_board_memmap.conf +endef + + +ifeq ($(BR2_PACKAGE_CVITEKCONFIG_PANEL_ZCT2133V1),y) + UBOOT_PANEL_TUNING_PARM=MIPI_PANEL_ZCT2133V1 +else ifeq ($(BR2_PACKAGE_CVITEKCONFIG_PANEL_HX8394),y) + UBOOT_PANEL_TUNING_PARM=MIPI_PANEL_HX8394 +else ifeq ($(BR2_PACKAGE_CVITEKCONFIG_PANEL_ILI9881C),y) + UBOOT_PANEL_TUNING_PARM=MIPI_PANEL_ILI9881C +else ifeq ($(BR2_PACKAGE_CVITEKCONFIG_PANEL_ILI9881D),y) + UBOOT_PANEL_TUNING_PARM=MIPI_PANEL_ILI9881D +else ifeq ($(BR2_PACKAGE_CVITEKCONFIG_PANEL_JD9366AB),y) + UBOOT_PANEL_TUNING_PARM=MIPI_PANEL_JD9366AB +else ifeq ($(BR2_PACKAGE_CVITEKCONFIG_PANEL_NT35521),y) + UBOOT_PANEL_TUNING_PARM=MIPI_PANEL_NT35521 +else ifeq ($(BR2_PACKAGE_CVITEKCONFIG_PANEL_OTA7290B),y) + UBOOT_PANEL_TUNING_PARM=MIPI_PANEL_OTA7290B +else ifeq ($(BR2_PACKAGE_CVITEKCONFIG_PANEL_ST7701_D300FPC9307A),y) + UBOOT_PANEL_TUNING_PARM=MIPI_PANEL_ST7701_D300FPC9307A +else ifeq ($(BR2_PACKAGE_CVITEKCONFIG_PANEL_OTA7290B_1920)) + UBOOT_PANEL_TUNING_PARM=MIPI_PANEL_OTA7290B_1920 +else ifeq ($(BR2_PACKAGE_CVITEKCONFIG_PANEL_ICN9707),y) + UBOOT_PANEL_TUNING_PARM=MIPI_PANEL_ICN9707 +else ifeq ($(BR2_PACKAGE_CVITEKCONFIG_PANEL_ST7701_DXQ5D0019B480854),y) + UBOOT_PANEL_TUNING_PARM=MIPI_PANEL_ST7701_DXQ5D0019B480854 +else ifeq ($(BR2_PACKAGE_CVITEKCONFIG_PANEL_3AML069LP01G),y) + UBOOT_PANEL_TUNING_PARM=MIPI_PANEL_3AML069LP01G +else ifeq ($(BR2_PACKAGE_CVITEKCONFIG_PANEL_ST7701 ),y) + UBOOT_PANEL_TUNING_PARM=MIPI_PANEL_ST7701 +else ifeq ($(BR2_PACKAGE_CVITEKCONFIG_PANEL_ST7701_HD228001C31),y) + UBOOT_PANEL_TUNING_PARM=MIPI_PANEL_ST7701_HD228001C31 +else ifeq ($(BR2_PACKAGE_CVITEKCONFIG_PANEL_ST7785M),y) + UBOOT_PANEL_TUNING_PARM=MIPI_PANEL_ST7785M +else ifeq ($(BR2_PACKAGE_CVITEKCONFIG_PANEL_ST7789V),y) + UBOOT_PANEL_TUNING_PARM=I80_PANEL_ST7789V +else ifeq ($(BR2_PACKAGE_CVITEKCONFIG_PANEL_EK79202),y) + UBOOT_PANEL_TUNING_PARM=LVDS_PANEL_EK79202 +endif + + + + +#hook into the other builds. Dependancies don't really work, so we must make cvitekconfig as the first command. + +UBOOT_POST_PATCH_HOOKS += UBOOT_APPLY_CVITEK_CONFIG_HOOK +UBOOT_DEPENDENCIES += cvitekconfig +LINUX_POST_PATCH_HOOKS += LINUX_APPLY_CVITEK_CONFIG_HOOK +LINUX_DEPENDENCIES += cvitekconfig +CVITEKFSBL_POST_PATCH_HOOKS += CVITEKFSBL_APPLY_CVITEK_CONFIG_HOOK +CVITEKFSBL_DEPENDENCIES += cvitekconfig + +define UBOOT_APPLY_CVITEK_CONFIG_HOOK + @echo "Applying CVITEK Generated Config" + $(INSTALL) -D -m 0644 $(TARGET_DIR)/include/cvi_board_memmap.h $(@D)/include/cvi_board_memmap.h + @cp $(BR2_GLOBAL_PATCH_DIR)../generated/cvipart.h $(@D)/include/cvipart.h + @cp $(BR2_GLOBAL_PATCH_DIR)../generated/uboot/cvi_board_init.c $(@D)/board/cvitek/ +endef + +define LINUX_APPLY_CVITEK_CONFIG_HOOK + @echo "Applying SG2002 Generated Config" + $(INSTALL) -D -m 0644 $(TARGET_DIR)/include/cvi_board_memmap.h $(@D)/include/cvi_board_memmap.h + #@cp $(BR2_GLOBAL_PATCH_DIR)../generated/cvi_board_memmap.h $(@D)/include/cvi_board_memmap.h + @cp $(BR2_GLOBAL_PATCH_DIR)../generated/cvipart.h $(@D)/include/cvipart.h +endef + +define CVITEKFSBL_APPLY_CVITEK_CONFIG_HOOK + @echo "Applying SG2002 Generated Config" + $(INSTALL) -D -m 0644 $(TARGET_DIR)/include/cvi_board_memmap.h $(@D)/include/cvi_board_memmap.h + #@cp $(BR2_GLOBAL_PATCH_DIR)../generated/cvi_board_memmap.h $(@D)/include/cvi_board_memmap.h +endef + + + + +$(eval $(generic-package)) diff --git a/package/cvitekconfig/genconfig/licheervnano/memmap.py b/package/cvitekconfig/genconfig/licheervnano/memmap.py new file mode 100755 index 0000000..4c676f0 --- /dev/null +++ b/package/cvitekconfig/genconfig/licheervnano/memmap.py @@ -0,0 +1,85 @@ +SIZE_1M = 0x100000 +SIZE_1K = 1024 + + +# Only attributes in class MemoryMap are generated to .h +class MemoryMap: + # No prefix "CVIMMAP_" for the items in _no_prefix[] + _no_prefix = [ + "CONFIG_SYS_TEXT_BASE" # u-boot's CONFIG_SYS_TEXT_BASE is used without CPP. + ] + + DRAM_BASE = 0x80000000 + DRAM_SIZE = 256 * SIZE_1M + + # ============== + # C906L FreeRTOS + # ============== + FREERTOS_SIZE = 2 * SIZE_1M + # FreeRTOS is at the end of DRAM + FREERTOS_ADDR = DRAM_BASE + DRAM_SIZE - FREERTOS_SIZE + FSBL_C906L_START_ADDR = FREERTOS_ADDR + + # ============================== + # OpenSBI | arm-trusted-firmware + # ============================== + # Monitor is at the begining of DRAM + MONITOR_ADDR = DRAM_BASE + + ATF_SIZE = 512 * SIZE_1K + OPENSBI_SIZE = 512 * SIZE_1K + OPENSBI_FDT_ADDR = MONITOR_ADDR + OPENSBI_SIZE + + # ========================= + # memory@DRAM_BASE in .dts. + # ========================= + # Ignore the area of FreeRTOS in u-boot and kernel + KERNEL_MEMORY_ADDR = DRAM_BASE + KERNEL_MEMORY_SIZE = DRAM_SIZE - FREERTOS_SIZE + + # ================= + # Multimedia buffer. Used by u-boot/kernel/FreeRTOS + # ================= + ION_SIZE = 75 * SIZE_1M + H26X_BITSTREAM_SIZE = 2 * SIZE_1M + H26X_ENC_BUFF_SIZE = 0 + ISP_MEM_BASE_SIZE = 20 * SIZE_1M + FREERTOS_RESERVED_ION_SIZE = H26X_BITSTREAM_SIZE + H26X_ENC_BUFF_SIZE + ISP_MEM_BASE_SIZE + + # ION after FreeRTOS + ION_ADDR = FREERTOS_ADDR - ION_SIZE + + # Buffers of the fast image are inside the ION buffer + H26X_BITSTREAM_ADDR = ION_ADDR + H26X_ENC_BUFF_ADDR = H26X_BITSTREAM_ADDR + H26X_BITSTREAM_SIZE + ISP_MEM_BASE_ADDR = H26X_ENC_BUFF_ADDR + H26X_ENC_BUFF_SIZE + + assert ISP_MEM_BASE_ADDR + ISP_MEM_BASE_SIZE <= ION_ADDR + ION_SIZE + + # Boot logo is after the ION buffer + # Framebuffer uses boot logo's reserved memory + BOOTLOGO_SIZE = 8000 * SIZE_1K + BOOTLOGO_ADDR = ION_ADDR - BOOTLOGO_SIZE + FRAMEBUFFER_SIZE = BOOTLOGO_SIZE + FRAMEBUFFER_ADDR = BOOTLOGO_ADDR + + # =================== + # FSBL and u-boot-2021 + # =================== + CVI_UPDATE_HEADER_SIZE = SIZE_1K + UIMAG_SIZE = 16 * SIZE_1M + + # kernel image loading buffer + UIMAG_ADDR = DRAM_BASE + 24 * SIZE_1M + CVI_UPDATE_HEADER_ADDR = UIMAG_ADDR - CVI_UPDATE_HEADER_SIZE + + # FSBL decompress buffer + FSBL_UNZIP_ADDR = UIMAG_ADDR + FSBL_UNZIP_SIZE = UIMAG_SIZE + + assert UIMAG_ADDR + UIMAG_SIZE <= BOOTLOGO_ADDR + + # u-boot's run address and entry point + CONFIG_SYS_TEXT_BASE = DRAM_BASE + 2 * SIZE_1M + # u-boot's init stack point is only used before board_init_f() + CONFIG_SYS_INIT_SP_ADDR = UIMAG_ADDR + UIMAG_SIZE diff --git a/package/cvitekconfig/genconfig/mmap_conv.py b/package/cvitekconfig/genconfig/mmap_conv.py new file mode 100755 index 0000000..1d7ef73 --- /dev/null +++ b/package/cvitekconfig/genconfig/mmap_conv.py @@ -0,0 +1,131 @@ +#!/usr/bin/env python3 + +import logging +import argparse +import importlib.util +from os.path import basename, splitext, abspath +from collections import OrderedDict +import random + + +MEMMAP_PREFIX = "CVIMMAP_" + + +def sort_mmap(mlist): + base = mlist.get("CVIMMAP_DRAM_BASE") + if not base: + base = 0 + + mm = mlist.items() + + mm = sorted(mm, key=lambda x: x[1]) + mm = sorted(mm, key=lambda x: x[0]) + + return OrderedDict(mm) + + +def parse_mmap(mmap_module): + try: + mmap = mmap_module.MemoryMap + except AttributeError: + logging.error("Memory map file must have 'class MemoryMap'") + raise + + no_prefix = getattr(mmap_module.MemoryMap, "_no_prefix", []) + + mlist = OrderedDict() + + for attr in mmap.__dict__: + if attr.startswith("_"): + continue + + value = getattr(mmap, attr) + if attr not in no_prefix: + attr = MEMMAP_PREFIX + attr + mlist[attr] = int(value) + + return sort_mmap(mlist) + + +def int_to_si(n): + off = "" + + for i in [0x80000000, 0x100000000]: + if n >= i: + off = "offset " + n -= i + break + + if n < 1024 * 1024: + s = "{0}KiB".format(n / 1024) + else: + s = "{0}MiB".format(n / (1024 * 1024)) + + return off + s + + +def mmap_to_ld(mlist): + mlist = ["{0:s} = {1:#x};".format(a, v) for a, v in mlist.items()] + + conf = "\n".join(mlist) + return conf + + +def mmap_to_conf(mlist): + mlist = ["{0:s}={1:#x}".format(a, v) for a, v in mlist.items()] + + conf = "\n".join(mlist) + return conf + + +def mmap_to_h(mlist): + mlist = ["#define {0:s} {1:#x} /* {2} */".format(a, v, int_to_si(v)) for a, v in mlist.items()] + + r = random.randint(0x80000000, 0xFFFFFFFF) + + conf = ( + "#ifndef __BOARD_MMAP__{0:08x}__\n" + "#define __BOARD_MMAP__{0:08x}__\n\n" + "{1}\n\n" + "#endif /* __BOARD_MMAP__{0:08x}__ */\n".format(r, "\n".join(mlist)) + ) + return conf + + +def main(): + logging.basicConfig( + format="%(levelname)8s:%(module)s: %(message)s", level=logging.NOTSET + ) + + parser = argparse.ArgumentParser(description="Generate mmap.h") + parser.add_argument("--type", choices=["h", "conf", "ld"], required=True) + parser.add_argument("MAP_FILE", type=str, nargs=1) + parser.add_argument("OUTPUT", type=str, nargs=1) + args = parser.parse_args() + + map_file_path = args.MAP_FILE[0] + logging.info("map_file_path is at %s", map_file_path) + map_name = splitext(basename(map_file_path))[0] + + # Load map_file as python module + spec = importlib.util.spec_from_file_location(map_name, map_file_path) + mmap_module = importlib.util.module_from_spec(spec) + spec.loader.exec_module(mmap_module) + + mlist = parse_mmap(mmap_module) + + if args.type == "h": + out = mmap_to_h(mlist) + elif args.type == "conf": + out = mmap_to_conf(mlist) + elif args.type == "ld": + out = mmap_to_ld(mlist) + + out_path = abspath(args.OUTPUT[0]) + logging.info("Generate to %s", out_path) + with open(out_path, "w") as fp: + fp.write(out) + + +if __name__ == "__main__": + main()