mirror of
https://github.com/Fishwaldo/br_sg200x.git
synced 2025-03-15 19:31:43 +00:00
first commit
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e190546d1f
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92
.github/workflows/buildroot.yml
vendored
Normal file
92
.github/workflows/buildroot.yml
vendored
Normal file
|
|
@ -0,0 +1,92 @@
|
|||
name: build-all
|
||||
|
||||
on:
|
||||
workflow_dispatch:
|
||||
push:
|
||||
branches: [ main ]
|
||||
paths-ignore:
|
||||
- '.github/**'
|
||||
tags:
|
||||
- "v*.*.*"
|
||||
pull_request:
|
||||
branches: [ main ]
|
||||
paths-ignore:
|
||||
- '.github/**'
|
||||
|
||||
jobs:
|
||||
buildroot:
|
||||
strategy:
|
||||
fail-fast: true
|
||||
matrix:
|
||||
target: [ sipeed_licheervnano_defconfig ]
|
||||
runs-on: ubuntu-22.04
|
||||
steps:
|
||||
- name: install dependencies
|
||||
run: |
|
||||
sudo apt-get install -y make gcc g++ unzip git bc python3 device-tree-compiler mtd-utils xz-utils
|
||||
- name: Checkout Buildroot sources
|
||||
uses: actions/checkout@v3
|
||||
with:
|
||||
repository: buildroot/buildroot
|
||||
ref: 2023.11.2
|
||||
path: buildroot
|
||||
- name: Checkout SG200x Buildroot
|
||||
uses: actions/checkout@v3
|
||||
with:
|
||||
path: sg200x
|
||||
- name: buildroot ccache
|
||||
id: br-ccache
|
||||
uses: actions/cache@v3
|
||||
env:
|
||||
cache-name: br-ccache
|
||||
with:
|
||||
path: /home/runner/.buildroot-ccache
|
||||
key: ${{ runner.os }}-build-${{ env.cache-name }}-${{ matrix.target }}
|
||||
- name: buildroot download cache
|
||||
uses: actions/cache@v3
|
||||
env:
|
||||
cache-name: cache-download-files
|
||||
with:
|
||||
path: ${{ github.workspace }}/buildroot/dl/
|
||||
key: ${{ runner.os }}-build-${{ env.cache-name }}-downloads
|
||||
- name: Build
|
||||
run: |
|
||||
export BR_LICHEERVNANO_OVERLAY_PATH=$(pwd)/sg200x
|
||||
cd buildroot
|
||||
make BR2_EXTERNAL=$BR_LICHEERVNANO_OVERLAY_PATH ${{ matrix.target }}
|
||||
make
|
||||
make ccache-stats
|
||||
- name: Pack
|
||||
run: |
|
||||
cd ${{ github.workspace }}/buildroot/output/images/
|
||||
ls -lah
|
||||
if [ -f sdcard.img ]; then
|
||||
xz -z sdcard.img
|
||||
mv sdcard.img.xz sdcard-${{ matrix.target }}.img.xz
|
||||
fi
|
||||
echo "PACKAGE=${{ github.workspace }}/buildroot/output/images/sdcard-${{ matrix.target }}.img.xz" >> $GITHUB_ENV
|
||||
echo "BRSDK=${{ github.workspace }}/buildroot/output/images/riscv*.tar.gz" >> $GITHUB_ENV
|
||||
- name: Upload package
|
||||
uses: actions/upload-artifact@master
|
||||
with:
|
||||
name: build-images
|
||||
path: |
|
||||
${{env.PACKAGE}}
|
||||
|
||||
release:
|
||||
if: startsWith(github.ref, 'refs/tags/')
|
||||
runs-on: ubuntu-22.04
|
||||
needs: [buildroot]
|
||||
permissions: write-all
|
||||
steps:
|
||||
- name: download firmware
|
||||
uses: actions/download-artifact@v3
|
||||
- name: Create images
|
||||
run: |
|
||||
ls -lah *
|
||||
- name: publish artifacts
|
||||
uses: softprops/action-gh-release@v1
|
||||
with:
|
||||
append_body: true
|
||||
files: |
|
||||
build-images/*.xz
|
||||
12
Config.in
Normal file
12
Config.in
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
menu "Custom Packages"
|
||||
source "$BR2_EXTERNAL_LICHEERVNANO_BR_PATH/package/Config.in"
|
||||
endmenu
|
||||
|
||||
menu "BootLoaders"
|
||||
source "$BR2_EXTERNAL_LICHEERVNANO_BR_PATH/boot/Config.in"
|
||||
endmenu
|
||||
|
||||
#menu "Host Packages"
|
||||
#source "$BR2_EXTERNAL_LICHEERVNANO_BR_PATH/package/Config.in.host"
|
||||
#endmenu
|
||||
|
||||
18
README.md
Normal file
18
README.md
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
# Buildroot overlay for SG200x based Boards
|
||||
|
||||
## Usage
|
||||
|
||||
```
|
||||
mkdir br_sg200x && cd br_sg200x
|
||||
git clone --depth 1 --branch 2023.11.2 https://github.com/buildroot/buildroot
|
||||
git clone https://github.com/Fishwaldo/sg200x
|
||||
export BR_LICHEERVNANO_OVERLAY_PATH=$(pwd)/sg200x
|
||||
cd buildroot
|
||||
make BR2_EXTERNAL=$BR_LICHEERVNANO_OVERLAY_PATH sipeed_licheervnano_defconfig
|
||||
make
|
||||
```
|
||||
|
||||
## Prebuilt images
|
||||
|
||||
Prebuilt images are available on the releases page (for tested images) or development images are available via the github actions page
|
||||
|
||||
10
board/sipeed/licheervnano/dts/sg2000_duo_sd.dts
Normal file
10
board/sipeed/licheervnano/dts/sg2000_duo_sd.dts
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/dts-v1/;
|
||||
#include "soph_base_riscv.dtsi"
|
||||
#include "soph_asic_bga.dtsi"
|
||||
#include "soph_asic_emmc.dtsi"
|
||||
#include "soph_default_memmap.dtsi"
|
||||
|
||||
/ {
|
||||
|
||||
};
|
||||
|
||||
9
board/sipeed/licheervnano/dts/sg2002_duo_sd.dts
Normal file
9
board/sipeed/licheervnano/dts/sg2002_duo_sd.dts
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
/dts-v1/;
|
||||
#include "soph_base_riscv.dtsi"
|
||||
#include "soph_asic_qfn.dtsi"
|
||||
#include "soph_asic_sd.dtsi"
|
||||
#include "soph_default_memmap.dtsi"
|
||||
|
||||
/ {
|
||||
|
||||
};
|
||||
170
board/sipeed/licheervnano/dts/sg2002_licheervnano_sd.dts
Normal file
170
board/sipeed/licheervnano/dts/sg2002_licheervnano_sd.dts
Normal file
|
|
@ -0,0 +1,170 @@
|
|||
/dts-v1/;
|
||||
#include "soph_base_riscv.dtsi"
|
||||
#include "soph_asic_qfn.dtsi"
|
||||
#include "soph_asic_sd.dtsi"
|
||||
#include "soph_default_memmap.dtsi"
|
||||
|
||||
#include <dt-bindings/input/linux-event-codes.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
&i2c0 {
|
||||
status = "disabled";
|
||||
/delete-property/ scl-pinmux;
|
||||
/delete-property/ sda-pinmux;
|
||||
/delete-property/ scl-gpios;
|
||||
/delete-property/ sda-gpios;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "disabled";
|
||||
/delete-property/ scl-pinmux;
|
||||
/delete-property/ sda-pinmux;
|
||||
/delete-property/ scl-gpios;
|
||||
/delete-property/ sda-gpios;
|
||||
};
|
||||
|
||||
&sd {
|
||||
min-frequency = <400000>; // 400Khz
|
||||
//max-frequency = <50000000>; // 50Mhz
|
||||
max-frequency = <25000000>; // 25Mhz
|
||||
//max-frequency = <10000000>; // 10Mhz
|
||||
//max-frequency = <5000000>; // 5Mhz
|
||||
};
|
||||
|
||||
&cvi_vo {
|
||||
#ifndef __UBOOT__
|
||||
/delete-property/ reset-gpio;
|
||||
#else
|
||||
// for uboot
|
||||
reset-gpio = <&porte 0 1>;
|
||||
#endif
|
||||
/delete-property/ pwm-gpio;
|
||||
/delete-property/ power-ct-gpio;
|
||||
|
||||
};
|
||||
|
||||
&mipi_tx {
|
||||
/delete-property/ pwm-gpio;
|
||||
#ifndef __UBOOT__
|
||||
// for linux kernel
|
||||
reset-gpio = <&porte 0 1>;
|
||||
#else
|
||||
/delete-property/ reset-gpio;
|
||||
#endif
|
||||
/delete-property/ power-ct-gpio;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "disabled";
|
||||
/delete-property/ scl-pinmux;
|
||||
/delete-property/ sda-pinmux;
|
||||
/delete-property/ scl-gpios;
|
||||
/delete-property/ sda-gpios;
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "disabled";
|
||||
/delete-property/ scl-pinmux;
|
||||
/delete-property/ sda-pinmux;
|
||||
/delete-property/ scl-gpios;
|
||||
/delete-property/ sda-gpios;
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
statuc = "okay";
|
||||
gt9xx: gt9xx@14 {
|
||||
compatible = "goodix,gt911";
|
||||
reg = <0x14>;
|
||||
interrupts = <3 0 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-parent = <&porte>;
|
||||
irq-gpios= <&porte 3 0>;
|
||||
reset-gpios = <&porte 4 0>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&dac {
|
||||
status = "okay";
|
||||
/delete-property/ mute-gpio-r;
|
||||
};
|
||||
|
||||
&fb_reserved {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cvi_fb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mipi_rx {
|
||||
snsr-reset = <&porte 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
/ {
|
||||
model = "LicheeRv Nano";
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
key-user {
|
||||
label = "User Key";
|
||||
linux,code = <KEY_DISPLAYTOGGLE>;
|
||||
debounce-interval = <1>;
|
||||
gpios = <&porta 30 1>;
|
||||
};
|
||||
};
|
||||
|
||||
wifisd:wifi-sd@4320000 {
|
||||
compatible = "cvitek,cv181x-sdio";
|
||||
bus-width = <4>;
|
||||
reg = <0x0 0x4320000 0x0 0x1000>;
|
||||
reg_names = "core_mem";
|
||||
src-frequency = <375000000>;
|
||||
min-frequency = <400000>; // 400Khz
|
||||
//max-frequency = <50000000>; // 50Mhz
|
||||
//max-frequency = <45000000>; // 45Mhz
|
||||
//max-frequency = <40000000>; // 40Mhz
|
||||
//max-frequency = <35000000>; // 35Mhz
|
||||
//max-frequency = <30000000>; // 30Mhz
|
||||
max-frequency = <25000000>; // 25Mhz
|
||||
//max-frequency = <20000000>; // 20Mhz
|
||||
//max-frequency = <15000000>; // 15Mhz
|
||||
//max-frequency = <10000000>; // 10Mhz
|
||||
//max-frequency = <5000000>; // 5Mhz
|
||||
64_addressing;
|
||||
reset_tx_rx_phy;
|
||||
non-removable;
|
||||
pll_index = <0x7>;
|
||||
pll_reg = <0x300207C>;
|
||||
no-mmc;
|
||||
no-sd;
|
||||
status = "okay";
|
||||
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
// for maixcam
|
||||
i2c5: i2c-gpio-a24-a23 {
|
||||
compatible = "i2c-gpio";
|
||||
scl-gpios = <&porta 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
sda-gpios = <&porta 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
i2c-gpio,delay-us = <5>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
16
board/sipeed/licheervnano/dts/soph_asic_bga.dtsi
Normal file
16
board/sipeed/licheervnano/dts/soph_asic_bga.dtsi
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
&dac{
|
||||
mute-gpio-l = <&porta 15 GPIO_ACTIVE_LOW>;
|
||||
mute-gpio-r = <&porta 30 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/ {
|
||||
/delete-node/ i2s@04110000;
|
||||
/delete-node/ i2s@04120000;
|
||||
/delete-node/ sound_ext1;
|
||||
/delete-node/ sound_ext2;
|
||||
/delete-node/ sound_PDM;
|
||||
};
|
||||
4
board/sipeed/licheervnano/dts/soph_asic_emmc.dtsi
Normal file
4
board/sipeed/licheervnano/dts/soph_asic_emmc.dtsi
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
/ {
|
||||
/delete-node/ cvi-spif@10000000;
|
||||
/delete-node/ cv-spinf@4060000;
|
||||
};
|
||||
118
board/sipeed/licheervnano/dts/soph_asic_qfn.dtsi
Normal file
118
board/sipeed/licheervnano/dts/soph_asic_qfn.dtsi
Normal file
|
|
@ -0,0 +1,118 @@
|
|||
&sd {
|
||||
no-1-8-v;
|
||||
};
|
||||
|
||||
&mipi_rx{
|
||||
snsr-reset = <&portc 13 GPIO_ACTIVE_LOW>, <&portc 13 GPIO_ACTIVE_LOW>, <&portc 13 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&mipi_tx {
|
||||
reset-gpio = <&porta 15 GPIO_ACTIVE_LOW>;
|
||||
pwm-gpio = <&porta 18 GPIO_ACTIVE_HIGH>;
|
||||
power-ct-gpio = <&porta 19 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&dac{
|
||||
mute-gpio-r = <&porte 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "disabled";
|
||||
num-cs = <1>;
|
||||
spidev@0 {
|
||||
compatible = "rohm,dh2228fv";
|
||||
spi-max-frequency = <1000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "disabled";
|
||||
num-cs = <1>;
|
||||
spidev@0 {
|
||||
compatible = "rohm,dh2228fv";
|
||||
spi-max-frequency = <1000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi2 {
|
||||
status = "disabled";
|
||||
num-cs = <1>;
|
||||
spidev@0 {
|
||||
compatible = "rohm,dh2228fv";
|
||||
spi-max-frequency = <1000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi3 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
spidev@0 {
|
||||
compatible = "rohm,dh2228fv";
|
||||
spi-max-frequency = <1000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
|
||||
scl-pinmux = <0x03001070 0x0 0x3>; // IIC0_SCL/IIC0_SCL/XGPIOA[28]
|
||||
sda-pinmux = <0x03001074 0x0 0x3>; // IIC0_SDA/IIC0_SDA/XGPIOA[29]
|
||||
/* gpio port */
|
||||
scl-gpios = <&porta 28 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&porta 29 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
|
||||
scl-pinmux = <0x03009408 0x2 0x3>; // SPI1_MOSI/IIC1_SCL/XGPIOB[7]
|
||||
sda-pinmux = <0x0300940c 0x2 0x3>; // SPI1_MISO/IIC1_SDA/XGPIOB[8]
|
||||
/* gpio port */
|
||||
scl-gpios = <&portb 7 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&portb 8 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
|
||||
scl-pinmux = <0x030011a0 0x4 0x3>; // PAD_MIPI_TXP1/IIC2_SCL/XGPIOC[15]
|
||||
sda-pinmux = <0x0300119c 0x4 0x3>; // PAD_MIPI_TXM1/IIC2_SDA/XGPIOC[14]
|
||||
/* gpio port */
|
||||
scl-gpios = <&portc 15 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&portc 14 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
|
||||
scl-pinmux = <0x03001014 0x0 0x3>; // IIC3_SCL/IIC3_SCL/XGPIOA[5]
|
||||
sda-pinmux = <0x03001018 0x0 0x3>; // IIC3_SDA/IIC3_SDA/XGPIOA[6]
|
||||
/* gpio port */
|
||||
scl-gpios = <&porta 5 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&porta 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
|
||||
scl-pinmux = <0x030010f0 0x2 0x3>; // ADC3/IIC4_SCL/XGPIOB[1]
|
||||
sda-pinmux = <0x030010f4 0x2 0x3>; // ADC2/IIC4_SDA/XGPIOB[2]
|
||||
/* gpio port */
|
||||
scl-gpios = <&portb 1 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&portb 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
/ {
|
||||
/delete-node/ wifi-sd@4320000;
|
||||
/delete-node/ i2s@04110000;
|
||||
/delete-node/ i2s@04120000;
|
||||
/delete-node/ sound_ext1;
|
||||
/delete-node/ sound_ext2;
|
||||
/delete-node/ sound_PDM;
|
||||
|
||||
wifi_pin {
|
||||
compatible = "cvitek,wifi-pin";
|
||||
poweron-gpio = <&porte 2 GPIO_ACTIVE_HIGH>;
|
||||
wakeup-gpio = <&porte 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
};
|
||||
4
board/sipeed/licheervnano/dts/soph_asic_sd.dtsi
Normal file
4
board/sipeed/licheervnano/dts/soph_asic_sd.dtsi
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
/ {
|
||||
/delete-node/ cv-emmc@4300000;
|
||||
/delete-node/ cv-spinf@4060000;
|
||||
};
|
||||
5
board/sipeed/licheervnano/dts/soph_asic_spinand.dtsi
Normal file
5
board/sipeed/licheervnano/dts/soph_asic_spinand.dtsi
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
/ {
|
||||
/delete-node/ cvi-spif@10000000;
|
||||
/delete-node/ cv-emmc@4300000;
|
||||
};
|
||||
|
||||
5
board/sipeed/licheervnano/dts/soph_asic_spinor.dtsi
Normal file
5
board/sipeed/licheervnano/dts/soph_asic_spinor.dtsi
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
/ {
|
||||
/delete-node/ cv-emmc@4300000;
|
||||
/delete-node/ cv-spinf@4060000;
|
||||
};
|
||||
|
||||
932
board/sipeed/licheervnano/dts/soph_base.dtsi
Normal file
932
board/sipeed/licheervnano/dts/soph_base.dtsi
Normal file
|
|
@ -0,0 +1,932 @@
|
|||
|
||||
/ {
|
||||
compatible = "cvitek,cv181x";
|
||||
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
|
||||
top_misc:top_misc_ctrl@3000000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0 0x03000000 0x0 0x8000>;
|
||||
};
|
||||
|
||||
clk_rst: clk-reset-controller {
|
||||
#reset-cells = <1>;
|
||||
compatible = "cvitek,clk-reset";
|
||||
reg = <0x0 0x03002000 0x0 0x8>;
|
||||
};
|
||||
|
||||
osc: oscillator {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "osc";
|
||||
};
|
||||
|
||||
clk: clock-controller {
|
||||
compatible = "cvitek,cv181x-clk";
|
||||
reg = <0x0 0x03002000 0x0 0x1000>;
|
||||
clocks = <&osc>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
rst: reset-controller {
|
||||
#reset-cells = <1>;
|
||||
compatible = "cvitek,reset";
|
||||
reg = <0x0 0x03003000 0x0 0x10>;
|
||||
};
|
||||
|
||||
restart: restart-controller {
|
||||
compatible = "cvitek,restart";
|
||||
reg = <0x0 0x05025000 0x0 0x2000>;
|
||||
};
|
||||
|
||||
tpu {
|
||||
compatible = "cvitek,tpu";
|
||||
reg-names = "tdma", "tiu";
|
||||
reg = <0x0 0x0C100000 0x0 0x1000>,
|
||||
<0x0 0x0C101000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_TPU>, <&clk CV181X_CLK_TPU_FAB>;
|
||||
clock-names = "clk_tpu_axi", "clk_tpu_fab";
|
||||
resets = <&rst RST_TDMA>, <&rst RST_TPU>, <&rst RST_TPUSYS>;
|
||||
reset-names = "res_tdma", "res_tpu", "res_tpusys";
|
||||
};
|
||||
|
||||
mon {
|
||||
compatible = "cvitek,mon";
|
||||
reg-names = "pcmon", "ddr_ctrl", "ddr_phyd", "ddr_aximon", "ddr_top";
|
||||
reg = <0x0 0x01040000 0x0 0x1000>,
|
||||
<0x0 0x08004000 0x0 0x1000>,
|
||||
<0x0 0x08006000 0x0 0x1000>,
|
||||
<0x0 0x08008000 0x0 0x1000>,
|
||||
<0x0 0x0800A000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
wiegand0 {
|
||||
compatible = "cvitek,wiegand";
|
||||
reg-names = "wiegand";
|
||||
reg = <0x0 0x03030000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_WGN>, <&clk CV181X_CLK_WGN0>;
|
||||
clock-names = "clk_wgn", "clk_wgn1";
|
||||
resets = <&rst RST_WGN0>;
|
||||
reset-names = "res_wgn";
|
||||
};
|
||||
|
||||
wiegand1 {
|
||||
compatible = "cvitek,wiegand";
|
||||
reg-names = "wiegand";
|
||||
reg = <0x0 0x03031000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_WGN>, <&clk CV181X_CLK_WGN1>;
|
||||
clock-names = "clk_wgn", "clk_wgn1";
|
||||
resets = <&rst RST_WGN1>;
|
||||
reset-names = "res_wgn";
|
||||
};
|
||||
|
||||
wiegand2 {
|
||||
compatible = "cvitek,wiegand";
|
||||
reg-names = "wiegand";
|
||||
reg = <0x0 0x03032000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_WGN>, <&clk CV181X_CLK_WGN2>;
|
||||
clock-names = "clk_wgn", "clk_wgn1";
|
||||
resets = <&rst RST_WGN2>;
|
||||
reset-names = "res_wgn";
|
||||
};
|
||||
|
||||
saradc {
|
||||
compatible = "cvitek,saradc";
|
||||
reg-names = "top_domain_saradc", "rtc_domain_saradc";
|
||||
reg = <0x0 0x030F0000 0x0 0x1000>, <0x0 0x0502c000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_SARADC>;
|
||||
clock-names = "clk_saradc";
|
||||
resets = <&rst RST_SARADC>;
|
||||
reset-names = "res_saradc";
|
||||
};
|
||||
|
||||
rtc {
|
||||
compatible = "cvitek,rtc";
|
||||
reg = <0x0 0x05026000 0x0 0x1000>,<0x0 0x05025000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_RTC_25M>;
|
||||
clock-names = "clk_rtc";
|
||||
};
|
||||
|
||||
cvitek-ion {
|
||||
compatible = "cvitek,cvitek-ion";
|
||||
|
||||
heap_carveout@0 {
|
||||
compatible = "cvitek,carveout";
|
||||
memory-region = <&ion_reserved>;
|
||||
};
|
||||
};
|
||||
|
||||
sysdma_remap {
|
||||
compatible = "cvitek,sysdma_remap";
|
||||
reg = <0x0 0x03000154 0x0 0x10>;
|
||||
ch-remap = <CVI_I2S0_RX CVI_I2S2_TX CVI_I2S1_RX CVI_I2S1_TX
|
||||
CVI_SPI_NAND CVI_SPI_NAND CVI_I2S2_RX CVI_I2S3_TX>;
|
||||
int_mux_base = <0x03000298>;
|
||||
};
|
||||
|
||||
dmac: dma@0x4330000 {
|
||||
compatible = "snps,dmac-bm";
|
||||
reg = <0x0 0x04330000 0x0 0x1000>;
|
||||
clock-names = "clk_sdma_axi";
|
||||
clocks = <&clk CV181X_CLK_SDMA_AXI>;
|
||||
|
||||
dma-channels = /bits/ 8 <8>;
|
||||
#dma-cells = <3>;
|
||||
dma-requests = /bits/ 8 <16>;
|
||||
chan_allocation_order = /bits/ 8 <0>;
|
||||
chan_priority = /bits/ 8 <1>;
|
||||
block_size = <1024>;
|
||||
dma-masters = /bits/ 8 <2>;
|
||||
data-width = <4 4>; /* bytes */
|
||||
axi_tr_width = <4>; /* bytes */
|
||||
block-ts = <15>;
|
||||
};
|
||||
|
||||
|
||||
watchdog0: cv-wd@0x3010000 {
|
||||
compatible = "snps,dw-wdt";
|
||||
reg = <0x0 0x03010000 0x0 0x1000>;
|
||||
resets = <&rst RST_WDT>;
|
||||
clocks = <&pclk>;
|
||||
};
|
||||
|
||||
pwm0: pwm@3060000 {
|
||||
compatible = "cvitek,cvi-pwm";
|
||||
reg = <0x0 0x3060000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_PWM>;
|
||||
#pwm-cells = <1>;
|
||||
};
|
||||
|
||||
pwm1: pwm@3061000 {
|
||||
compatible = "cvitek,cvi-pwm";
|
||||
reg = <0x0 0x3061000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_PWM>;
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
|
||||
pwm2: pwm@3062000 {
|
||||
compatible = "cvitek,cvi-pwm";
|
||||
reg = <0x0 0x3062000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_PWM>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
pwm3: pwm@3063000 {
|
||||
compatible = "cvitek,cvi-pwm";
|
||||
reg = <0x0 0x3063000 0x0 0x1000>;
|
||||
clocks = <&clk CV181X_CLK_PWM>;
|
||||
#pwm-cells = <4>;
|
||||
};
|
||||
|
||||
pclk: pclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
spinand:cv-spinf@4060000 {
|
||||
compatible = "cvitek,cv1835-spinf";
|
||||
reg = <0x0 0x4060000 0x0 0x1000>;
|
||||
reg-names = "core_mem";
|
||||
bus-width = <4>;
|
||||
dmas = <&dmac 4 1 1
|
||||
&dmac 5 1 1>;
|
||||
dma-names = "rx","tx";
|
||||
};
|
||||
|
||||
spif:cvi-spif@10000000 {
|
||||
compatible = "cvitek,cvi-spif";
|
||||
bus-num = <0>;
|
||||
reg = <0x0 0x10000000 0x0 0x10000000>;
|
||||
reg-names = "spif";
|
||||
sck-div = <3>;
|
||||
sck_mhz = <300>;
|
||||
spi-max-frequency = <75000000>;
|
||||
spiflash {
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
spi0:spi0@04180000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
reg = <0x0 0x04180000 0x0 0x10000>;
|
||||
clocks = <&clk CV181X_CLK_SPI>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi1:spi1@04190000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
reg = <0x0 0x04190000 0x0 0x10000>;
|
||||
clocks = <&clk CV181X_CLK_SPI>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi2:spi2@041A0000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
reg = <0x0 0x041A0000 0x0 0x10000>;
|
||||
clocks = <&clk CV181X_CLK_SPI>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi3:spi3@041B0000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
reg = <0x0 0x041B0000 0x0 0x10000>;
|
||||
clocks = <&clk CV181X_CLK_SPI>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#if 0
|
||||
dmas = <&dmac 2 1 1
|
||||
&dmac 3 1 1>;
|
||||
dma-names = "rx", "tx";
|
||||
capability = "txrx";
|
||||
#endif
|
||||
};
|
||||
|
||||
uart0: serial@04140000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x04140000 0x0 0x1000>;
|
||||
clock-frequency = <25000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart1: serial@04150000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x04150000 0x0 0x1000>;
|
||||
clock-frequency = <25000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@04160000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x04160000 0x0 0x1000>;
|
||||
clock-frequency = <25000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@04170000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x04170000 0x0 0x1000>;
|
||||
clock-frequency = <25000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@041C0000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x041C0000 0x0 0x1000>;
|
||||
clock-frequency = <25000000>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio0: gpio@03020000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x03020000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
porta: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
bank-name = "porta";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio1: gpio@03021000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x03021000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portb: gpio-controller@1 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
bank-name = "portb";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio2: gpio@03022000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x03022000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portc: gpio-controller@2 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
bank-name = "portc";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio3: gpio@03023000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x03023000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portd: gpio-controller@3 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
bank-name = "portd";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio4: gpio@05021000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x05021000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
porte: gpio-controller@4 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
bank-name = "porte";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0: i2c@04000000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
clocks = <&clk CV181X_CLK_I2C>;
|
||||
reg = <0x0 0x04000000 0x0 0x1000>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
#size-cells = <0x0>;
|
||||
#address-cells = <0x1>;
|
||||
resets = <&rst RST_I2C0>;
|
||||
reset-names = "i2c0";
|
||||
};
|
||||
|
||||
i2c1: i2c@04010000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
clocks = <&clk CV181X_CLK_I2C>;
|
||||
reg = <0x0 0x04010000 0x0 0x1000>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
#size-cells = <0x0>;
|
||||
#address-cells = <0x1>;
|
||||
resets = <&rst RST_I2C1>;
|
||||
reset-names = "i2c1";
|
||||
};
|
||||
|
||||
i2c2: i2c@04020000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
clocks = <&clk CV181X_CLK_I2C>;
|
||||
reg = <0x0 0x04020000 0x0 0x1000>;
|
||||
clock-frequency = <100000>;
|
||||
resets = <&rst RST_I2C2>;
|
||||
reset-names = "i2c2";
|
||||
};
|
||||
|
||||
i2c3: i2c@04030000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
clocks = <&clk CV181X_CLK_I2C>;
|
||||
reg = <0x0 0x04030000 0x0 0x1000>;
|
||||
clock-frequency = <400000>;
|
||||
resets = <&rst RST_I2C3>;
|
||||
reset-names = "i2c3";
|
||||
};
|
||||
|
||||
i2c4: i2c@04040000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
clocks = <&clk CV181X_CLK_I2C>;
|
||||
reg = <0x0 0x04040000 0x0 0x1000>;
|
||||
clock-frequency = <400000>;
|
||||
resets = <&rst RST_I2C4>;
|
||||
reset-names = "i2c4";
|
||||
};
|
||||
|
||||
eth_csrclk: eth_csrclk {
|
||||
clock-output-names = "eth_csrclk";
|
||||
clock-frequency = <250000000>;
|
||||
#clock-cells = <0x0>;
|
||||
compatible = "fixed-clock";
|
||||
};
|
||||
|
||||
eth_ptpclk: eth_ptpclk {
|
||||
clock-output-names = "eth_ptpclk";
|
||||
clock-frequency = <50000000>;
|
||||
#clock-cells = <0x0>;
|
||||
compatible = "fixed-clock";
|
||||
};
|
||||
|
||||
stmmac_axi_setup: stmmac-axi-config {
|
||||
snps,wr_osr_lmt = <1>;
|
||||
snps,rd_osr_lmt = <2>;
|
||||
snps,blen = <4 8 16 0 0 0 0>;
|
||||
};
|
||||
|
||||
mtl_rx_setup: rx-queues-config {
|
||||
snps,rx-queues-to-use = <1>;
|
||||
queue0 {};
|
||||
};
|
||||
|
||||
mtl_tx_setup: tx-queues-config {
|
||||
snps,tx-queues-to-use = <1>;
|
||||
queue0 {};
|
||||
};
|
||||
|
||||
ethernet0: ethernet@4070000 {
|
||||
compatible = "cvitek,ethernet";
|
||||
reg = <0x0 0x04070000 0x0 0x10000>;
|
||||
clock-names = "stmmaceth", "ptp_ref";
|
||||
clocks = <ð_csrclk>, <ð_ptpclk>;
|
||||
//phy-reset-gpios = <&porta 26 0>;
|
||||
|
||||
tx-fifo-depth = <8192>;
|
||||
rx-fifo-depth = <8192>;
|
||||
/* no hash filter and perfect filter support */
|
||||
snps,multicast-filter-bins = <0>;
|
||||
snps,perfect-filter-entries = <1>;
|
||||
|
||||
snps,txpbl = <8>;
|
||||
snps,rxpbl = <8>;
|
||||
snps,aal;
|
||||
|
||||
snps,axi-config = <&stmmac_axi_setup>;
|
||||
snps,mtl-rx-config = <&mtl_rx_setup>;
|
||||
snps,mtl-tx-config = <&mtl_tx_setup>;
|
||||
|
||||
phy-mode = "rmii";
|
||||
};
|
||||
|
||||
emmc:cv-emmc@4300000 {
|
||||
compatible = "cvitek,cv181x-emmc";
|
||||
reg = <0x0 0x4300000 0x0 0x1000>;
|
||||
reg-names = "core_mem";
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
no-sdio;
|
||||
no-sd;
|
||||
src-frequency = <375000000>;
|
||||
min-frequency = <400000>;
|
||||
max-frequency = <200000000>;
|
||||
64_addressing;
|
||||
reset_tx_rx_phy;
|
||||
pll_index = <0x5>;
|
||||
pll_reg = <0x3002064>;
|
||||
};
|
||||
|
||||
sd:cv-sd@4310000 {
|
||||
compatible = "cvitek,cv181x-sd";
|
||||
reg = <0x0 0x4310000 0x0 0x1000>;
|
||||
reg-names = "core_mem";
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
/*no-1-8-v;*/
|
||||
src-frequency = <375000000>;
|
||||
min-frequency = <400000>;
|
||||
max-frequency = <200000000>;
|
||||
64_addressing;
|
||||
reset_tx_rx_phy;
|
||||
reset-names = "sdhci";
|
||||
pll_index = <0x6>;
|
||||
pll_reg = <0x3002070>;
|
||||
cvi-cd-gpios = <&porta 13 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wifisd:wifi-sd@4320000 {
|
||||
compatible = "cvitek,cv181x-sdio";
|
||||
bus-width = <4>;
|
||||
reg = <0x0 0x4320000 0x0 0x1000>;
|
||||
reg_names = "core_mem";
|
||||
src-frequency = <375000000>;
|
||||
min-frequency = <400000>;
|
||||
max-frequency = <50000000>;
|
||||
64_addressing;
|
||||
reset_tx_rx_phy;
|
||||
non-removable;
|
||||
pll_index = <0x7>;
|
||||
pll_reg = <0x300207C>;
|
||||
no-mmc;
|
||||
no-sd;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2s_mclk: i2s_mclk {
|
||||
clock-output-names = "i2s_mclk";
|
||||
clock-frequency = <24576000>;
|
||||
#clock-cells = <0x0>;
|
||||
compatible = "fixed-clock";
|
||||
};
|
||||
|
||||
i2s_subsys {
|
||||
compatible = "cvitek,i2s_tdm_subsys";
|
||||
reg = <0x0 0x04108000 0x0 0x100>;
|
||||
clocks = <&i2s_mclk>, <&clk CV181X_CLK_A0PLL>,
|
||||
<&clk CV181X_CLK_SDMA_AUD0>, <&clk CV181X_CLK_SDMA_AUD1>,
|
||||
<&clk CV181X_CLK_SDMA_AUD2>, <&clk CV181X_CLK_SDMA_AUD3>;
|
||||
clock-names = "i2sclk", "clk_a0pll",
|
||||
"clk_sdma_aud0", "clk_sdma_aud1",
|
||||
"clk_sdma_aud2", "clk_sdma_aud3";
|
||||
master_base = <0x04110000>; /* I2S1 is master, only useful while using multi I2S IPs work on same IO */
|
||||
};
|
||||
|
||||
i2s0: i2s@04100000 {
|
||||
compatible = "cvitek,cv1835-i2s";
|
||||
reg = <0x0 0x04100000 0x0 0x2000>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
dev-id = <0>;
|
||||
#sound-dai-cells = <0>;
|
||||
dmas = <&dmac 0 1 1>; /* read channel */
|
||||
dma-names = "rx";
|
||||
capability = "rx"; /* I2S0 connect to internal ADC as RX */
|
||||
mclk_out = "false";
|
||||
};
|
||||
|
||||
i2s1: i2s@04110000 {
|
||||
compatible = "cvitek,cv1835-i2s";
|
||||
reg = <0x0 0x04110000 0x0 0x2000>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
dev-id = <1>;
|
||||
#sound-dai-cells = <0>;
|
||||
dmas = <&dmac 2 1 1 /* read channel */
|
||||
&dmac 3 1 1>; /* write channel */
|
||||
dma-names = "rx", "tx";
|
||||
capability = "txrx";
|
||||
mclk_out = "false";
|
||||
};
|
||||
|
||||
i2s2: i2s@04120000 {
|
||||
compatible = "cvitek,cv1835-i2s";
|
||||
reg = <0x0 0x04120000 0x0 0x2000>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
dev-id = <2>;
|
||||
#sound-dai-cells = <0>;
|
||||
dmas = <&dmac 6 1 1 /* read channel */
|
||||
&dmac 1 1 1>; /* write channel */
|
||||
dma-names = "rx", "tx";
|
||||
capability = "txrx";
|
||||
mclk_out = "false";
|
||||
|
||||
};
|
||||
|
||||
i2s3: i2s@04130000 {
|
||||
compatible = "cvitek,cv1835-i2s";
|
||||
reg = <0x0 0x04130000 0x0 0x2000>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
dev-id = <3>;
|
||||
#sound-dai-cells = <0>;
|
||||
dmas = <&dmac 7 1 1>; /* write channel */
|
||||
dma-names = "tx";
|
||||
capability = "tx"; /* I2S3 connect to internal DAC as TX */
|
||||
mclk_out = "true";
|
||||
};
|
||||
|
||||
adc: adc@0300A100 {
|
||||
compatible = "cvitek,cv182xaadc";
|
||||
reg = <0x0 0x0300A100 0x0 0x100>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
clk_source = <0x04130000>; /* MCLK source is I2S3 */
|
||||
};
|
||||
|
||||
dac: dac@0300A000 {
|
||||
compatible = "cvitek,cv182xadac";
|
||||
reg = <0x0 0x0300A000 0x0 0x100>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
};
|
||||
|
||||
pdm: pdm@0x041D0C00 {
|
||||
compatible = "cvitek,cv1835pdm";
|
||||
reg = <0x0 0x041D0C00 0x0 0x100>;
|
||||
clocks = <&i2s_mclk 0>;
|
||||
clock-names = "i2sclk";
|
||||
};
|
||||
|
||||
sound_adc {
|
||||
compatible = "cvitek,cv182xa-adc";
|
||||
cvi,model = "CV182XA";
|
||||
cvi,card_name = "cv182xa_adc";
|
||||
};
|
||||
|
||||
sound_dac {
|
||||
compatible = "cvitek,cv182xa-dac";
|
||||
cvi,model = "CV182XA";
|
||||
cvi,card_name = "cv182xa_dac";
|
||||
};
|
||||
|
||||
sound_PDM {
|
||||
compatible = "cvitek,cv182x-pdm";
|
||||
cvi,model = "CV182X";
|
||||
cvi,card_name = "cv182x_internal_PDM";
|
||||
};
|
||||
|
||||
wifi_pin {
|
||||
compatible = "cvitek,wifi-pin";
|
||||
poweron-gpio = <&porta 18 GPIO_ACTIVE_HIGH>;
|
||||
wakeup-gpio = <&porte 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
bt_pin {
|
||||
compatible = "cvitek,bt-pin";
|
||||
poweron-gpio = <&porte 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
mipi_rx: cif {
|
||||
compatible = "cvitek,cif";
|
||||
reg = <0x0 0x0a0c2000 0x0 0x2000>, <0x0 0x0a0d0000 0x0 0x1000>,
|
||||
<0x0 0x0a0c4000 0x0 0x2000>, <0x0 0x0a0c6000 0x0 0x2000>,
|
||||
<0x0 0x03001c30 0x0 0x30>;
|
||||
reg-names = "csi_mac0", "csi_wrap0", "csi_mac1", "csi_mac2", "pad_ctrl";
|
||||
snsr-reset = <&porta 2 GPIO_ACTIVE_LOW>, <&porta 2 GPIO_ACTIVE_LOW>, <&porta 2 GPIO_ACTIVE_LOW>;
|
||||
resets = <&rst RST_CSIPHY0>, <&rst RST_CSIPHY1>,
|
||||
<&rst RST_CSIPHY0RST_APB>, <&rst RST_CSIPHY1RST_APB>;
|
||||
reset-names = "phy0", "phy1", "phy-apb0", "phy-apb1";
|
||||
clocks = <&clk CV181X_CLK_CAM0>, <&clk CV181X_CLK_CAM1>, <&clk CV181X_CLK_SRC_VIP_SYS_2>,
|
||||
<&clk CV181X_CLK_MIPIMPLL>, <&clk CV181X_CLK_DISPPLL>, <&clk CV181X_CLK_FPLL>;
|
||||
clock-names = "clk_cam0", "clk_cam1", "clk_sys_2",
|
||||
"clk_mipimpll", "clk_disppll", "clk_fpll";
|
||||
};
|
||||
|
||||
mipi_tx: mipi_tx {
|
||||
compatible = "cvitek,mipi_tx";
|
||||
reset-gpio = <&porte 2 GPIO_ACTIVE_LOW>;
|
||||
pwm-gpio = <&porte 0 GPIO_ACTIVE_HIGH>;
|
||||
power-ct-gpio = <&porte 1 GPIO_ACTIVE_HIGH>;
|
||||
clocks = <&clk CV181X_CLK_DISP_VIP>, <&clk CV181X_CLK_DSI_MAC_VIP>;
|
||||
clock-names = "clk_disp", "clk_dsi";
|
||||
};
|
||||
|
||||
sys {
|
||||
compatible = "cvitek,sys";
|
||||
};
|
||||
|
||||
base {
|
||||
compatible = "cvitek,base";
|
||||
reg = <0x0 0x0a0c8000 0x0 0x20>;
|
||||
reg-names = "vip_sys";
|
||||
};
|
||||
|
||||
vi {
|
||||
compatible = "cvitek,vi";
|
||||
reg = <0x0 0x0a000000 0x0 0x80000>;
|
||||
clocks = <&clk CV181X_CLK_SRC_VIP_SYS_0>, <&clk CV181X_CLK_SRC_VIP_SYS_1>,
|
||||
<&clk CV181X_CLK_SRC_VIP_SYS_2>, <&clk CV181X_CLK_SRC_VIP_SYS_3>,
|
||||
<&clk CV181X_CLK_AXI_VIP>, <&clk CV181X_CLK_CSI_BE_VIP>,
|
||||
<&clk CV181X_CLK_RAW_VIP>, <&clk CV181X_CLK_ISP_TOP_VIP>,
|
||||
<&clk CV181X_CLK_CSI_MAC0_VIP>, <&clk CV181X_CLK_CSI_MAC1_VIP>,
|
||||
<&clk CV181X_CLK_CSI_MAC2_VIP>;
|
||||
clock-names = "clk_sys_0", "clk_sys_1", "clk_sys_2", "clk_sys_3",
|
||||
"clk_axi", "clk_csi_be", "clk_raw", "clk_isp_top",
|
||||
"clk_csi_mac0", "clk_csi_mac1", "clk_csi_mac2";
|
||||
clock-freq-vip-sys1 = <300000000>;
|
||||
};
|
||||
|
||||
vpss {
|
||||
compatible = "cvitek,vpss";
|
||||
reg = <0x0 0x0a080000 0x0 0x10000>, <0x0 0x0a0d1000 0x0 0x100>;
|
||||
reg-names = "sc";
|
||||
clocks = <&clk CV181X_CLK_SRC_VIP_SYS_0>, <&clk CV181X_CLK_SRC_VIP_SYS_1>,
|
||||
<&clk CV181X_CLK_SRC_VIP_SYS_2>, <&clk CV181X_CLK_IMG_D_VIP>,
|
||||
<&clk CV181X_CLK_IMG_V_VIP>, <&clk CV181X_CLK_SC_TOP_VIP>,
|
||||
<&clk CV181X_CLK_SC_D_VIP>, <&clk CV181X_CLK_SC_V1_VIP>,
|
||||
<&clk CV181X_CLK_SC_V2_VIP>, <&clk CV181X_CLK_SC_V3_VIP>;
|
||||
clock-names = "clk_sys_0", "clk_sys_1",
|
||||
"clk_sys_2", "clk_img_d",
|
||||
"clk_img_v", "clk_sc_top",
|
||||
"clk_sc_d", "clk_sc_v1",
|
||||
"clk_sc_v2", "clk_sc_v3";
|
||||
clock-freq-vip-sys1 = <300000000>;
|
||||
};
|
||||
|
||||
ive {
|
||||
compatible = "cvitek,ive";
|
||||
reg = <0x0 0x0A0A0000 0x0 0x3100>;
|
||||
reg-names = "ive_base";
|
||||
};
|
||||
|
||||
cvi_vo: vo {
|
||||
compatible = "cvitek,vo";
|
||||
reg = <0x0 0x0a080000 0x0 0x10000>, <0x0 0x0a0c8000 0x0 0xa0>, <0x0 0x0a0d1000 0x0 0x100>;
|
||||
reg-names = "sc", "vip_sys", "dphy";
|
||||
clocks = <&clk CV181X_CLK_DISP_VIP>, <&clk CV181X_CLK_DSI_MAC_VIP>, <&clk CV181X_CLK_BT_VIP>;
|
||||
reset-gpio = <&porte 2 GPIO_ACTIVE_LOW>;
|
||||
pwm-gpio = <&porte 0 GPIO_ACTIVE_HIGH>;
|
||||
power-ct-gpio = <&porte 1 GPIO_ACTIVE_HIGH>;
|
||||
clock-names = "clk_disp", "clk_dsi", "clk_bt";
|
||||
};
|
||||
|
||||
#if (CVIMMAP_FRAMEBUFFER_SIZE > 0)
|
||||
reserved-memory {
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
ranges;
|
||||
|
||||
fb_reserved: cvifb {
|
||||
alloc-ranges = <0x0 CVIMMAP_FRAMEBUFFER_ADDR 0 CVIMMAP_FRAMEBUFFER_SIZE>;
|
||||
size = <0x0 CVIMMAP_FRAMEBUFFER_SIZE>;
|
||||
};
|
||||
};
|
||||
|
||||
cvi_fb: cvifb {
|
||||
compatible = "cvitek,fb";
|
||||
memory-region = <&fb_reserved>;
|
||||
reg = <0x0 0x0a088000 0x0 0x1000>;
|
||||
reg-names = "disp";
|
||||
};
|
||||
#endif
|
||||
dwa {
|
||||
compatible = "cvitek,dwa";
|
||||
reg = <0x0 0x0a0c0000 0x0 0x1000>;
|
||||
reg-names = "dwa";
|
||||
clocks = <&clk CV181X_CLK_SRC_VIP_SYS_0>, <&clk CV181X_CLK_SRC_VIP_SYS_1>,
|
||||
<&clk CV181X_CLK_SRC_VIP_SYS_2>, <&clk CV181X_CLK_SRC_VIP_SYS_3>,
|
||||
<&clk CV181X_CLK_SRC_VIP_SYS_4>, <&clk CV181X_CLK_DWA_VIP>;
|
||||
clock-names = "clk_sys_0", "clk_sys_1",
|
||||
"clk_sys_2", "clk_sys_3",
|
||||
"clk_sys_4", "clk_dwa";
|
||||
clock-freq-vip-sys1 = <300000000>;
|
||||
};
|
||||
|
||||
rgn {
|
||||
compatible = "cvitek,rgn";
|
||||
};
|
||||
|
||||
vcodec {
|
||||
compatible = "cvitek,asic-vcodec";
|
||||
reg = <0x0 0x0B020000 0x0 0x10000>,<0x0 0x0B010000 0x0 0x10000>,<0x0 0x0B030000 0x0 0x100>,
|
||||
<0x0 0x0B058000 0x0 0x100>,<0x0 0x0B050000 0x0 0x400>;
|
||||
reg-names = "h265","h264","vc_ctrl","vc_sbm","vc_addr_remap";
|
||||
clocks = <&clk CV181X_CLK_AXI_VIDEO_CODEC>,
|
||||
<&clk CV181X_CLK_H264C>, <&clk CV181X_CLK_APB_H264C>,
|
||||
<&clk CV181X_CLK_H265C>, <&clk CV181X_CLK_APB_H265C>,
|
||||
<&clk CV181X_CLK_VC_SRC0>, <&clk CV181X_CLK_VC_SRC1>,
|
||||
<&clk CV181X_CLK_VC_SRC2>, <&clk CV181X_CLK_CFG_REG_VC>;
|
||||
clock-names = "clk_axi_video_codec",
|
||||
"clk_h264c", "clk_apb_h264c",
|
||||
"clk_h265c", "clk_apb_h265c",
|
||||
"clk_vc_src0", "clk_vc_src1",
|
||||
"clk_vc_src2", "clk_cfg_reg_vc";
|
||||
};
|
||||
|
||||
jpu {
|
||||
compatible = "cvitek,asic-jpeg";
|
||||
reg = <0x0 0x0B000000 0x0 0x300>,<0x0 0x0B030000 0x0 0x100>,<0x0 0x0B058000 0x0 0x100>;
|
||||
reg-names = "jpeg","vc_ctrl","vc_sbm";
|
||||
clocks = <&clk CV181X_CLK_AXI_VIDEO_CODEC>,
|
||||
<&clk CV181X_CLK_JPEG>, <&clk CV181X_CLK_APB_JPEG>,
|
||||
<&clk CV181X_CLK_VC_SRC0>, <&clk CV181X_CLK_VC_SRC1>,
|
||||
<&clk CV181X_CLK_VC_SRC2>, <&clk CV181X_CLK_CFG_REG_VC>;
|
||||
clock-names = "clk_axi_video_codec",
|
||||
"clk_jpeg", "clk_apb_jpeg",
|
||||
"clk_vc_src0", "clk_vc_src1",
|
||||
"clk_vc_src2", "clk_cfg_reg_vc";
|
||||
resets = <&rst RST_JPEG>;
|
||||
reset-names = "jpeg";
|
||||
};
|
||||
|
||||
cvi_vc_drv {
|
||||
compatible = "cvitek,cvi_vc_drv";
|
||||
reg = <0x0 0x0B030000 0x0 0x100>,<0x0 0x0B058000 0x0 0x100>,<0x0 0x0B050000 0x0 0x400>;
|
||||
reg-names = "vc_ctrl","vc_sbm","vc_addr_remap";
|
||||
};
|
||||
|
||||
rtos_cmdqu {
|
||||
compatible = "cvitek,rtos_cmdqu";
|
||||
reg = <0x0 0x01900000 0x0 0x1000>;
|
||||
reg-names = "mailbox";
|
||||
};
|
||||
|
||||
usb: usb@04340000 {
|
||||
compatible = "cvitek,cv182x-usb";
|
||||
reg = <0x0 0x04340000 0x0 0x10000>,
|
||||
<0x0 0x03006000 0x0 0x58>; //USB 2.0 PHY
|
||||
dr_mode = "otg";
|
||||
g-use-dma;
|
||||
g-rx-fifo-size = <536>;
|
||||
g-np-tx-fifo-size = <32>;
|
||||
g-tx-fifo-size = <768 512 512 384 128 128>;
|
||||
clocks = <&clk CV181X_CLK_AXI4_USB>,
|
||||
<&clk CV181X_CLK_APB_USB>,
|
||||
<&clk CV181X_CLK_125M_USB>,
|
||||
<&clk CV181X_CLK_33K_USB>,
|
||||
<&clk CV181X_CLK_12M_USB>;
|
||||
clock-names = "clk_axi", "clk_apb", "clk_125m", "clk_33k", "clk_12m";
|
||||
vbus-gpio = <&portb 6 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal:thermal@030E0000 {
|
||||
compatible = "cvitek,cv181x-thermal";
|
||||
reg = <0x0 0x030E0000 0x0 0x10000>;
|
||||
clocks = <&clk CV181X_CLK_TEMPSEN>;
|
||||
clock-names = "clk_tempsen";
|
||||
reset-names = "tempsen";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
soc_thermal_0: soc_thermal_0 {
|
||||
polling-delay-passive = <1000>; /* milliseconds */
|
||||
polling-delay = <1000>; /* milliseconds */
|
||||
thermal-sensors = <&thermal 0>;
|
||||
|
||||
trips {
|
||||
soc_thermal_trip_0: soc_thermal_trip_0 {
|
||||
temperature = <100000>; /* millicelsius */
|
||||
hysteresis = <5000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
soc_thermal_trip_1: soc_thermal_trip_1 {
|
||||
temperature = <110000>; /* millicelsius */
|
||||
hysteresis = <5000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
soc_thermal_crtical_0: soc_thermal_crtical_0 {
|
||||
temperature = <130000>; /* millicelsius */
|
||||
hysteresis = <0>; /* millicelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#if 0
|
||||
cvipctrl: pinctrl@3001000 {
|
||||
compatible = "cvitek,pinctrl-cv182x";
|
||||
reg = <0 0x03001000 0 0x1000>;
|
||||
};
|
||||
#endif
|
||||
|
||||
cviaudio_core {
|
||||
compatible = "cvitek,audio";
|
||||
};
|
||||
|
||||
audio_clock: audio_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
#if 0
|
||||
clock-frequency = <12288000>;
|
||||
#else
|
||||
clock-frequency = <24576000>;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
//spi0 = &spi0;
|
||||
//spi1 = &spi1;
|
||||
//spi2 = &spi2;
|
||||
//spi3 = &spi3;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
serial4 = &uart4;
|
||||
ethernet0 = ðernet0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0";
|
||||
};
|
||||
};
|
||||
|
||||
320
board/sipeed/licheervnano/dts/soph_base_arm.dtsi
Normal file
320
board/sipeed/licheervnano/dts/soph_base_arm.dtsi
Normal file
|
|
@ -0,0 +1,320 @@
|
|||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/reset/cv181x-resets.h>
|
||||
#include <dt-bindings/clock/cv181x-clock.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
#include <dt-bindings/dma/cv181x-dmamap.h>
|
||||
#include "cvi_board_memmap.h"
|
||||
|
||||
/memreserve/ CVIMMAP_MONITOR_ADDR CVIMMAP_ATF_SIZE; // ATF (BL31 + BL32) 512KB
|
||||
|
||||
#include "soph_base.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SOPHGO ASIC. ARM.";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
|
||||
gic: interrupt-controller {
|
||||
compatible = "arm,cortex-a15-gic";
|
||||
ranges;
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <0x3>;
|
||||
reg = <0x0 0x01F01000 0x0 0x1000>,
|
||||
<0x0 0x01F02000 0x0 0x2000>;
|
||||
};
|
||||
|
||||
pmu_a53 {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&A53_0>;
|
||||
};
|
||||
|
||||
psci {
|
||||
migrate = <0xc4000005>;
|
||||
cpu_on = <0xc4000003>;
|
||||
cpu_off = <0x84000002>;
|
||||
cpu_suspend = <0xc4000001>;
|
||||
sys_poweroff = <0x84000008>;
|
||||
sys_reset = <0x84000009>;
|
||||
method = "smc";
|
||||
compatible = "arm,psci-0.2", "arm,psci";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#size-cells = <0x0>;
|
||||
#address-cells = <0x1>;
|
||||
|
||||
A53_0: cpu@0 {
|
||||
reg = <0x0>;
|
||||
enable-method = "psci";
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&CA53_L2>;
|
||||
};
|
||||
|
||||
CA53_L2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
always-on;
|
||||
clock-frequency = <25000000>;
|
||||
compatible = "arm,armv8-timer";
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
cooling:cooling {
|
||||
clocks = <&clk CV181X_CLK_A53>, <&clk CV181X_CLK_TPU>;
|
||||
clock-names = "clk_cpu", "clk_tpu_axi";
|
||||
dev-freqs = <800000000 500000000>,
|
||||
<400000000 375000000>,
|
||||
<400000000 300000000>;
|
||||
compatible = "sophgo,cooling";
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
tpu {
|
||||
interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 60 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
mon {
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
wiegand0 {
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
wiegand1 {
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
wiegand2 {
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
saradc {
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
rtc {
|
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sysdma_remap {
|
||||
int_mux = <0x1FF>; /* enable bit [0..8] for CPU0(CA53) */
|
||||
};
|
||||
|
||||
dmac: dma@0x4330000 {
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
#if 0
|
||||
watchdog0: cv-wd@0x3010000 {
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
#endif
|
||||
|
||||
spinand:cv-spinf@4060000 {
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spif:cvi-spif@10000000 {
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spi0:spi0@04180000 {
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spi1:spi1@04190000 {
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spi2:spi2@041A0000 {
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spi3:spi3@041B0000 {
|
||||
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart0: serial@04140000 {
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart1: serial@04150000 {
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart2: serial@04160000 {
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart3: serial@04170000 {
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart4: serial@041C0000 {
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpio0: gpio@03020000 {
|
||||
porta: gpio-controller@0 {
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio1: gpio@03021000 {
|
||||
portb: gpio-controller@1 {
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio2: gpio@03022000 {
|
||||
portc: gpio-controller@2 {
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio3: gpio@03023000 {
|
||||
portd: gpio-controller@3 {
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio4: gpio@05021000 {
|
||||
porte: gpio-controller@4 {
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0: i2c@04000000 {
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2c1: i2c@04010000 {
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2c2: i2c@04020000 {
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2c3: i2c@04030000 {
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2c4: i2c@04040000 {
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
ethernet0: ethernet@4070000 {
|
||||
interrupt-names = "macirq";
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
emmc:cv-emmc@4300000 {
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sd:cv-sd@4310000 {
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2s0: i2s@04100000 {
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2s1: i2s@04110000 {
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2s2: i2s@04120000 {
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2s3: i2s@04130000 {
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
wifisd:wifi-sd@4320000 {
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
mipi_rx: cif {
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "csi0", "csi1";
|
||||
};
|
||||
|
||||
vi {
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "isp";
|
||||
};
|
||||
|
||||
ive {
|
||||
interrupt-names = "ive_irq";
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
vpss {
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "sc";
|
||||
};
|
||||
|
||||
dwa {
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "dwa";
|
||||
};
|
||||
|
||||
vcodec {
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "h265","h264","sbm";
|
||||
};
|
||||
|
||||
jpu {
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "jpeg";
|
||||
};
|
||||
|
||||
rtos_cmdqu {
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "mailbox";
|
||||
};
|
||||
|
||||
usb: usb@04340000 {
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
thermal:thermal@030E0000 {
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tempsen";
|
||||
};
|
||||
|
||||
};
|
||||
377
board/sipeed/licheervnano/dts/soph_base_riscv.dtsi
Normal file
377
board/sipeed/licheervnano/dts/soph_base_riscv.dtsi
Normal file
|
|
@ -0,0 +1,377 @@
|
|||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/reset/cv181x-resets.h>
|
||||
#include <dt-bindings/clock/cv181x-clock.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
#include <dt-bindings/dma/cv181x-dmamap.h>
|
||||
#include "cvi_board_memmap.h"
|
||||
|
||||
/*
|
||||
* OpenSBI will add below subnode into reserved memory automatically
|
||||
* mmode_resv0@80000000 {
|
||||
* reg = <0x00 0x80000000 0x00 0x20000>;
|
||||
* phandle = <0x0d>;
|
||||
* };
|
||||
* Skip below to avoid lmb region reseved conflict in uboot.
|
||||
*
|
||||
*/
|
||||
#ifndef __UBOOT__
|
||||
/memreserve/ CVIMMAP_MONITOR_ADDR CVIMMAP_OPENSBI_SIZE; // OpenSBI
|
||||
#endif
|
||||
|
||||
#include "soph_base.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SOPHGO ASIC. C906.";
|
||||
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <0x01>;
|
||||
#size-cells = <0x00>;
|
||||
timebase-frequency = <25000000>;
|
||||
|
||||
cpu-map {
|
||||
|
||||
cluster0 {
|
||||
|
||||
core0 {
|
||||
cpu = <0x01>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x00>;
|
||||
status = "okay";
|
||||
compatible = "riscv";
|
||||
riscv,isa = "rv64imafdvcsu";
|
||||
mmu-type = "riscv,sv39";
|
||||
clock-frequency = <25000000>;
|
||||
|
||||
cpu0_intc: interrupt-controller {
|
||||
#interrupt-cells = <0x01>;
|
||||
interrupt-controller;
|
||||
compatible = "riscv,cpu-intc";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <0x02>;
|
||||
#size-cells = <0x02>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
plic0: interrupt-controller@70000000 {
|
||||
riscv,ndev = <101>;
|
||||
riscv,max-priority = <0x07>;
|
||||
reg-names = "control";
|
||||
reg = <0x00 0x70000000 0x00 0x4000000>;
|
||||
interrupts-extended = <&cpu0_intc 0xffffffff &cpu0_intc 0x09>;
|
||||
interrupt-controller;
|
||||
compatible = "riscv,plic0";
|
||||
#interrupt-cells = <0x02>;
|
||||
#address-cells = <0x00>;
|
||||
};
|
||||
|
||||
clint@74000000 {
|
||||
interrupts-extended = <&cpu0_intc 0x03 &cpu0_intc 0x07>;
|
||||
reg = <0x00 0x74000000 0x00 0x10000>;
|
||||
compatible = "riscv,clint0";
|
||||
clint,has-no-64bit-mmio;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
cooling:cooling {
|
||||
clocks = <&clk CV181X_CLK_C906_0>, <&clk CV181X_CLK_TPU>;
|
||||
clock-names = "clk_cpu", "clk_tpu_axi";
|
||||
dev-freqs = <850000000 500000000>,
|
||||
<425000000 375000000>,
|
||||
<425000000 300000000>;
|
||||
compatible = "sophgo,cooling";
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
tpu {
|
||||
interrupts = <75 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tiu_irq", "tdma_irq";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
mon {
|
||||
interrupts = <93 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "mon_irq";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
wiegand0 {
|
||||
interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
wiegand1 {
|
||||
interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
wiegand2 {
|
||||
interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
saradc {
|
||||
interrupts = <100 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
rtc {
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
sysdma_remap {
|
||||
int_mux = <0x7FC00>; /* enable bit [10..18] for CPU1(906B) */
|
||||
};
|
||||
|
||||
dmac: dma@0x4330000 {
|
||||
interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
watchdog0: cv-wd@0x3010000 {
|
||||
interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spinand:cv-spinf@4060000 {
|
||||
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
spif:cvi-spif@10000000 {
|
||||
interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
spi0:spi0@04180000 {
|
||||
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
spi1:spi1@04190000 {
|
||||
interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
spi2:spi2@041A0000 {
|
||||
interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
spi3:spi3@041B0000 {
|
||||
interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
uart0: serial@04140000 {
|
||||
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
uart1: serial@04150000 {
|
||||
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
uart2: serial@04160000 {
|
||||
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
uart3: serial@04170000 {
|
||||
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
uart4: serial@041C0000 {
|
||||
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
gpio0: gpio@03020000 {
|
||||
porta: gpio-controller@0 {
|
||||
interrupt-controller;
|
||||
interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio1: gpio@03021000 {
|
||||
portb: gpio-controller@1 {
|
||||
interrupt-controller;
|
||||
interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio2: gpio@03022000 {
|
||||
portc: gpio-controller@2 {
|
||||
interrupt-controller;
|
||||
interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio3: gpio@03023000 {
|
||||
portd: gpio-controller@3 {
|
||||
interrupt-controller;
|
||||
interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio4: gpio@05021000 {
|
||||
porte: gpio-controller@4 {
|
||||
interrupt-controller;
|
||||
interrupts = <70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0: i2c@04000000 {
|
||||
interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2c1: i2c@04010000 {
|
||||
interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2c2: i2c@04020000 {
|
||||
interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2c3: i2c@04030000 {
|
||||
interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2c4: i2c@04040000 {
|
||||
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
ethernet0: ethernet@4070000 {
|
||||
interrupt-names = "macirq";
|
||||
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
emmc:cv-emmc@4300000 {
|
||||
interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
sd:cv-sd@4310000 {
|
||||
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2s0: i2s@04100000 {
|
||||
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2s1: i2s@04110000 {
|
||||
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2s2: i2s@04120000 {
|
||||
interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
i2s3: i2s@04130000 {
|
||||
interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
vi {
|
||||
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
interrupt-names = "isp";
|
||||
};
|
||||
|
||||
vcodec {
|
||||
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<21 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "h265","h264","sbm";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
jpu {
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "jpeg";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
rtos_cmdqu {
|
||||
interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "mailbox";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
wifisd:wifi-sd@4320000 {
|
||||
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
mipi_rx: cif {
|
||||
interrupts = <26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "csi0", "csi1";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
ive {
|
||||
interrupt-names = "ive_irq";
|
||||
interrupt-parent = <&plic0>;
|
||||
interrupts = <97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
vpss {
|
||||
interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "sc";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
dwa {
|
||||
interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "dwa";
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
usb: usb@04340000 {
|
||||
interrupts = <30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&plic0>;
|
||||
};
|
||||
|
||||
thermal:thermal@030E0000 {
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tempsen";
|
||||
};
|
||||
|
||||
};
|
||||
25
board/sipeed/licheervnano/dts/soph_default_memmap.dtsi
Normal file
25
board/sipeed/licheervnano/dts/soph_default_memmap.dtsi
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/ {
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00 CVIMMAP_KERNEL_MEMORY_ADDR 0x00 CVIMMAP_KERNEL_MEMORY_SIZE>;
|
||||
};
|
||||
|
||||
|
||||
fast_image {
|
||||
compatible = "cvitek,rtos_image";
|
||||
reg-names = "rtos_region";
|
||||
reg = <0x0 CVIMMAP_FREERTOS_ADDR 0x0 CVIMMAP_FREERTOS_SIZE>;
|
||||
ion-size = <CVIMMAP_FREERTOS_RESERVED_ION_SIZE>; //reserved ion size for freertos
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#size-cells = <0x2>;
|
||||
#address-cells = <0x2>;
|
||||
ranges;
|
||||
|
||||
ion_reserved: ion {
|
||||
compatible = "ion-region";
|
||||
size = <0x0 CVIMMAP_ION_SIZE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
52
board/sipeed/licheervnano/fit-image.its
Normal file
52
board/sipeed/licheervnano/fit-image.its
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
description = "Kernel";
|
||||
#address-cells = <2>;
|
||||
|
||||
images {
|
||||
kernel@1 {
|
||||
description = "Kernel";
|
||||
data = /incbin/("./Image.gz");
|
||||
type = "kernel";
|
||||
arch = "riscv";
|
||||
os = "linux";
|
||||
compression = "gzip";
|
||||
load = <0x0 0x80200000>;
|
||||
entry = <0x0 0x80200000>;
|
||||
hash@1 {
|
||||
algo = "sha1";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
dtb@1 {
|
||||
description = "Device tree";
|
||||
data = /incbin/("./sg2002_licheervnano_sd.dtb");
|
||||
type = "flat_dt";
|
||||
arch = "riscv";
|
||||
compression = "none";
|
||||
hash@1 {
|
||||
algo = "sha1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/*CFG*/
|
||||
configurations {
|
||||
default = "config-sg2002_licheervnano_sd";
|
||||
|
||||
config-sg2002_licheervnano_sd {
|
||||
description = "boot sg2002_licheervnano_sd";
|
||||
kernel = "kernel@1";
|
||||
fdt = "dtb@1";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
|
||||
};
|
||||
37
board/sipeed/licheervnano/generated/cvi_board_memmap.h
Normal file
37
board/sipeed/licheervnano/generated/cvi_board_memmap.h
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
#ifndef __BOARD_MMAP__ab4bdb87__
|
||||
#define __BOARD_MMAP__ab4bdb87__
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x80200000 /* offset 2.0MiB */
|
||||
#define CVIMMAP_ATF_SIZE 0x80000 /* 512.0KiB */
|
||||
#define CVIMMAP_BOOTLOGO_ADDR 0x8ab30000 /* offset 171.1875MiB */
|
||||
#define CVIMMAP_BOOTLOGO_SIZE 0x7d0000 /* 7.8125MiB */
|
||||
#define CVIMMAP_CONFIG_SYS_INIT_SP_ADDR 0x82800000 /* offset 40.0MiB */
|
||||
#define CVIMMAP_CVI_UPDATE_HEADER_ADDR 0x817ffc00 /* offset 23.9990234375MiB */
|
||||
#define CVIMMAP_CVI_UPDATE_HEADER_SIZE 0x400 /* 1.0KiB */
|
||||
#define CVIMMAP_DRAM_BASE 0x80000000 /* offset 0.0KiB */
|
||||
#define CVIMMAP_DRAM_SIZE 0x10000000 /* 256.0MiB */
|
||||
#define CVIMMAP_FRAMEBUFFER_ADDR 0x8ab30000 /* offset 171.1875MiB */
|
||||
#define CVIMMAP_FRAMEBUFFER_SIZE 0x7d0000 /* 7.8125MiB */
|
||||
#define CVIMMAP_FREERTOS_ADDR 0x8fe00000 /* offset 254.0MiB */
|
||||
#define CVIMMAP_FREERTOS_RESERVED_ION_SIZE 0x1600000 /* 22.0MiB */
|
||||
#define CVIMMAP_FREERTOS_SIZE 0x200000 /* 2.0MiB */
|
||||
#define CVIMMAP_FSBL_C906L_START_ADDR 0x8fe00000 /* offset 254.0MiB */
|
||||
#define CVIMMAP_FSBL_UNZIP_ADDR 0x81800000 /* offset 24.0MiB */
|
||||
#define CVIMMAP_FSBL_UNZIP_SIZE 0x1000000 /* 16.0MiB */
|
||||
#define CVIMMAP_H26X_BITSTREAM_ADDR 0x8b300000 /* offset 179.0MiB */
|
||||
#define CVIMMAP_H26X_BITSTREAM_SIZE 0x200000 /* 2.0MiB */
|
||||
#define CVIMMAP_H26X_ENC_BUFF_ADDR 0x8b500000 /* offset 181.0MiB */
|
||||
#define CVIMMAP_H26X_ENC_BUFF_SIZE 0x0 /* 0.0KiB */
|
||||
#define CVIMMAP_ION_ADDR 0x8b300000 /* offset 179.0MiB */
|
||||
#define CVIMMAP_ION_SIZE 0x4b00000 /* 75.0MiB */
|
||||
#define CVIMMAP_ISP_MEM_BASE_ADDR 0x8b500000 /* offset 181.0MiB */
|
||||
#define CVIMMAP_ISP_MEM_BASE_SIZE 0x1400000 /* 20.0MiB */
|
||||
#define CVIMMAP_KERNEL_MEMORY_ADDR 0x80000000 /* offset 0.0KiB */
|
||||
#define CVIMMAP_KERNEL_MEMORY_SIZE 0xfe00000 /* 254.0MiB */
|
||||
#define CVIMMAP_MONITOR_ADDR 0x80000000 /* offset 0.0KiB */
|
||||
#define CVIMMAP_OPENSBI_FDT_ADDR 0x80080000 /* offset 512.0KiB */
|
||||
#define CVIMMAP_OPENSBI_SIZE 0x80000 /* 512.0KiB */
|
||||
#define CVIMMAP_UIMAG_ADDR 0x81800000 /* offset 24.0MiB */
|
||||
#define CVIMMAP_UIMAG_SIZE 0x1000000 /* 16.0MiB */
|
||||
|
||||
#endif /* __BOARD_MMAP__ab4bdb87__ */
|
||||
13
board/sipeed/licheervnano/generated/cvipart.h
Normal file
13
board/sipeed/licheervnano/generated/cvipart.h
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/* this file should be generated by mkcvipart.py,please do not modify this file manually*/
|
||||
|
||||
#ifndef CVIPART_H
|
||||
#define CVIPART_H
|
||||
#ifndef CONFIG_ENV_IS_NOWHERE
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
#endif
|
||||
#define CONFIG_ENV_SIZE 0x20000
|
||||
#define PART_LAYOUT ""
|
||||
#define ROOTFS_DEV "/dev/mmcblk0p2"
|
||||
#define PARTS_OFFSET ""
|
||||
#define SPL_BOOT_PART_OFFSET 0x0
|
||||
#endif
|
||||
102
board/sipeed/licheervnano/generated/uboot/cvi_board_init.c
Normal file
102
board/sipeed/licheervnano/generated/uboot/cvi_board_init.c
Normal file
|
|
@ -0,0 +1,102 @@
|
|||
__attribute__((optimize("O0")))
|
||||
// 1.26ms
|
||||
void suck_loop(uint64_t loop) {
|
||||
loop = loop * 50 * 100;
|
||||
uint64_t a;
|
||||
while (loop > 0) {
|
||||
a = loop / (uint64_t)99;
|
||||
a = loop / (uint64_t)77;
|
||||
a = loop / (uint64_t)55;
|
||||
a = loop / (uint64_t)33;
|
||||
a = loop / (uint64_t)11;
|
||||
a = loop / (uint64_t)999;
|
||||
a = loop / (uint64_t)777;
|
||||
a = loop / (uint64_t)555;
|
||||
a = loop / (uint64_t)333;
|
||||
a = loop / (uint64_t)111;
|
||||
a = loop / (uint64_t)9999;
|
||||
a = loop / (uint64_t)7777;
|
||||
a = loop / (uint64_t)5555;
|
||||
a = loop / (uint64_t)3333;
|
||||
a = loop / (uint64_t)1111;
|
||||
a = loop / (uint64_t)99999;
|
||||
a = loop / (uint64_t)77777;
|
||||
a = loop / (uint64_t)55555;
|
||||
a = loop / (uint64_t)33333;
|
||||
a = loop / (uint64_t)11111;
|
||||
loop--;
|
||||
}
|
||||
}
|
||||
|
||||
int cvi_board_init(void)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
// wifi power reset
|
||||
mmio_write_32(0x0300104C, 0x3); // GPIOA 26
|
||||
val = mmio_read_32(0x03020004); // GPIOA DIR
|
||||
val |= (1 << 26); // output
|
||||
mmio_write_32(0x03020004, val);
|
||||
|
||||
val = mmio_read_32(0x03020000); // signal level
|
||||
val &= ~(1 << 26); // set level to low
|
||||
mmio_write_32(0x03020000, val);
|
||||
|
||||
suck_loop(200);
|
||||
|
||||
val = mmio_read_32(0x03020000); // signal level
|
||||
val |= (1 << 26); // set level to high
|
||||
mmio_write_32(0x03020000, val);
|
||||
|
||||
// wifi sdio pinmux
|
||||
mmio_write_32(0x030010D0, 0x0); // D3
|
||||
mmio_write_32(0x030010D4, 0x0); // D2
|
||||
mmio_write_32(0x030010D8, 0x0); // D1
|
||||
mmio_write_32(0x030010DC, 0x0); // D0
|
||||
mmio_write_32(0x030010E0, 0x0); // CMD
|
||||
mmio_write_32(0x030010E4, 0x0); // CLK
|
||||
|
||||
// uart bluetooth
|
||||
mmio_write_32(0x03001070, 0x1); // GPIOA 28 UART1 TX
|
||||
mmio_write_32(0x03001074, 0x1); // GPIOA 29 UART1 RX
|
||||
mmio_write_32(0x03001068, 0x4); // GPIOA 18 UART1 CTS
|
||||
mmio_write_32(0x03001064, 0x4); // GPIOA 19 UART1 RTS
|
||||
|
||||
// PWM
|
||||
//mmio_write_32(0x03001068, 0x2); // GPIOA 18 PWM 6
|
||||
|
||||
// lcd reset
|
||||
mmio_write_32(0x030010A4, 0x0); // PWRGPIO 0 GPIO_MODE
|
||||
|
||||
// lcd backlight
|
||||
//mmio_write_32(0x030010EC, 0x0); // GPIOB 0 PWM0_BUCK
|
||||
mmio_write_32(0x030010EC, 0x3); // GPIOB 0 GPIO_MODE
|
||||
val = mmio_read_32(0x03021004); // GPIOB DIR
|
||||
val |= (1 << 0); // output
|
||||
mmio_write_32(0x03021004, val);
|
||||
val = mmio_read_32(0x03021000); // signal level
|
||||
val |= (1 << 0); // set level to high
|
||||
mmio_write_32(0x03021000, val);
|
||||
|
||||
// camera function
|
||||
mmio_write_32(0x0300116C, 0x5); // RX4N CAM_MCLK0
|
||||
|
||||
// camera/tp i2c
|
||||
mmio_write_32(0x03001090, 0x5); // PWR_GPIO6 IIC4_SCL
|
||||
mmio_write_32(0x03001098, 0x5); // PWR_GPIO8 IIC4_SDA
|
||||
|
||||
// tp function
|
||||
mmio_write_32(0x03001084, 0x3); // PWR_SEQ1 PWR_GPIO[3]
|
||||
mmio_write_32(0x03001088, 0x3); // PWR_SEQ2 PWR_GPIO[4]
|
||||
mmio_write_32(0x05027078, 0x11);// Unlock PWR_GPIO[3]
|
||||
mmio_write_32(0x0502707c, 0x11);// Unlock PWR_GPIO[4]
|
||||
|
||||
// bitbang i2c for maixcam
|
||||
#ifdef MAIXCAM
|
||||
mmio_write_32(0x0300105C, 0x3);// GPIOA 23 GPIO_MODE
|
||||
mmio_write_32(0x03001060, 0x3);// GPIOA 24 GPIO_MODE
|
||||
#endif
|
||||
// wait hardware bootup
|
||||
suck_loop(100);
|
||||
return 0;
|
||||
}
|
||||
31
board/sipeed/licheervnano/genimage.cfg
Normal file
31
board/sipeed/licheervnano/genimage.cfg
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
image boot.vfat {
|
||||
vfat {
|
||||
label = "boot"
|
||||
files = {
|
||||
"fip.bin",
|
||||
"boot.sd"
|
||||
}
|
||||
}
|
||||
size = 16M
|
||||
}
|
||||
|
||||
image sdcard.img {
|
||||
hdimage {
|
||||
partition-table-type = mbr
|
||||
}
|
||||
|
||||
partition boot {
|
||||
partition-type = 0x0C
|
||||
#partition-type-uuid = F
|
||||
bootable = "true"
|
||||
image = "boot.vfat"
|
||||
}
|
||||
|
||||
partition rootfs {
|
||||
partition-type = 0x83
|
||||
#partition-type-uuid = L
|
||||
image = "rootfs.ext4"
|
||||
size = 512M
|
||||
}
|
||||
}
|
||||
|
||||
501
board/sipeed/licheervnano/linux_defconfig
Normal file
501
board/sipeed/licheervnano/linux_defconfig
Normal file
|
|
@ -0,0 +1,501 @@
|
|||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=15
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_MEMCG=y
|
||||
CONFIG_BLK_CGROUP=y
|
||||
CONFIG_CGROUP_SCHED=y
|
||||
CONFIG_CFS_BANDWIDTH=y
|
||||
CONFIG_RT_GROUP_SCHED=y
|
||||
CONFIG_CGROUP_PIDS=y
|
||||
CONFIG_CGROUP_DEVICE=y
|
||||
CONFIG_NAMESPACES=y
|
||||
CONFIG_USER_NS=y
|
||||
CONFIG_CHECKPOINT_RESTORE=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
# CONFIG_SYSFS_SYSCALL is not set
|
||||
# CONFIG_FHANDLE is not set
|
||||
# CONFIG_BUG is not set
|
||||
# CONFIG_BASE_FULL is not set
|
||||
# CONFIG_EPOLL is not set
|
||||
# CONFIG_SIGNALFD is not set
|
||||
# CONFIG_TIMERFD is not set
|
||||
# CONFIG_AIO is not set
|
||||
# CONFIG_IO_URING is not set
|
||||
# CONFIG_ADVISE_SYSCALLS is not set
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_SLUB_DEBUG is not set
|
||||
CONFIG_FORCE_MAX_ZONEORDER=10
|
||||
CONFIG_ARCH_CVITEK=y
|
||||
CONFIG_SOC_THEAD=y
|
||||
# CONFIG_RISCV_SWIOTLB is not set
|
||||
CONFIG_VECTOR=y
|
||||
CONFIG_VECTOR_0_7=y
|
||||
# CONFIG_COMPAT is not set
|
||||
CONFIG_ARCH_CVITEK_CHIP="mars"
|
||||
CONFIG_ARCH_CV181X_ASIC=y
|
||||
CONFIG_COMPAT_32BIT_TIME=y
|
||||
# CONFIG_STRICT_KERNEL_RWX is not set
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_FORCE_LOAD=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
# CONFIG_EFI_PARTITION is not set
|
||||
CONFIG_CMDLINE_PARTITION=y
|
||||
# CONFIG_MQ_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_MQ_IOSCHED_KYBER is not set
|
||||
CONFIG_CMA=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_PACKET_DIAG=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_UNIX_DIAG=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_NET_IPIP=y
|
||||
CONFIG_INET_UDP_DIAG=y
|
||||
CONFIG_INET_RAW_DIAG=y
|
||||
CONFIG_INET_DIAG_DESTROY=y
|
||||
CONFIG_TCP_CONG_ADVANCED=y
|
||||
# CONFIG_IPV6_SIT is not set
|
||||
CONFIG_NETFILTER=y
|
||||
CONFIG_NETFILTER_NETLINK_ACCT=y
|
||||
CONFIG_NETFILTER_NETLINK_QUEUE=y
|
||||
CONFIG_NETFILTER_NETLINK_LOG=y
|
||||
CONFIG_NF_CONNTRACK=y
|
||||
CONFIG_NF_LOG_NETDEV=y
|
||||
CONFIG_NF_CONNTRACK_ZONES=y
|
||||
CONFIG_NF_CONNTRACK_EVENTS=y
|
||||
CONFIG_NF_CONNTRACK_TIMEOUT=y
|
||||
CONFIG_NF_CONNTRACK_TIMESTAMP=y
|
||||
CONFIG_NF_CONNTRACK_LABELS=y
|
||||
CONFIG_NF_CT_NETLINK=y
|
||||
CONFIG_NF_CT_NETLINK_TIMEOUT=y
|
||||
CONFIG_NF_CT_NETLINK_HELPER=y
|
||||
CONFIG_NETFILTER_NETLINK_GLUE_CT=y
|
||||
CONFIG_NF_TABLES=y
|
||||
CONFIG_NF_TABLES_INET=y
|
||||
CONFIG_NF_TABLES_NETDEV=y
|
||||
CONFIG_NFT_NUMGEN=y
|
||||
CONFIG_NFT_CT=y
|
||||
CONFIG_NFT_COUNTER=y
|
||||
CONFIG_NFT_CONNLIMIT=y
|
||||
CONFIG_NFT_LOG=y
|
||||
CONFIG_NFT_LIMIT=y
|
||||
CONFIG_NFT_MASQ=y
|
||||
CONFIG_NFT_REDIR=y
|
||||
CONFIG_NFT_NAT=y
|
||||
CONFIG_NFT_TUNNEL=y
|
||||
CONFIG_NFT_OBJREF=y
|
||||
CONFIG_NFT_QUEUE=y
|
||||
CONFIG_NFT_QUOTA=y
|
||||
CONFIG_NFT_REJECT=y
|
||||
CONFIG_NFT_COMPAT=y
|
||||
CONFIG_NFT_HASH=y
|
||||
CONFIG_NFT_SOCKET=y
|
||||
CONFIG_NFT_OSF=y
|
||||
CONFIG_NFT_TPROXY=y
|
||||
CONFIG_NFT_SYNPROXY=y
|
||||
CONFIG_NFT_DUP_NETDEV=y
|
||||
CONFIG_NFT_FWD_NETDEV=y
|
||||
CONFIG_NF_FLOW_TABLE_INET=y
|
||||
CONFIG_NF_FLOW_TABLE=y
|
||||
CONFIG_NFT_DUP_IPV4=y
|
||||
CONFIG_NFT_FIB_IPV4=y
|
||||
CONFIG_NF_TABLES_ARP=y
|
||||
CONFIG_NF_FLOW_TABLE_IPV4=y
|
||||
CONFIG_NF_LOG_ARP=y
|
||||
CONFIG_NF_LOG_IPV4=y
|
||||
CONFIG_IP_NF_IPTABLES=y
|
||||
CONFIG_IP_NF_FILTER=y
|
||||
CONFIG_IP_NF_TARGET_REJECT=y
|
||||
CONFIG_IP_NF_TARGET_SYNPROXY=y
|
||||
CONFIG_IP_NF_NAT=y
|
||||
CONFIG_IP_NF_TARGET_MASQUERADE=y
|
||||
CONFIG_IP_NF_TARGET_NETMAP=y
|
||||
CONFIG_IP_NF_TARGET_REDIRECT=y
|
||||
CONFIG_IP_NF_MANGLE=y
|
||||
CONFIG_IP_NF_TARGET_CLUSTERIP=y
|
||||
CONFIG_IP_NF_TARGET_ECN=y
|
||||
CONFIG_IP_NF_TARGET_TTL=y
|
||||
CONFIG_IP_NF_RAW=y
|
||||
CONFIG_IP_NF_ARPTABLES=y
|
||||
CONFIG_IP_NF_ARPFILTER=y
|
||||
CONFIG_IP_NF_ARP_MANGLE=y
|
||||
CONFIG_NFT_DUP_IPV6=y
|
||||
CONFIG_NFT_FIB_IPV6=y
|
||||
CONFIG_IP6_NF_IPTABLES=y
|
||||
CONFIG_IP6_NF_FILTER=y
|
||||
CONFIG_IP6_NF_TARGET_REJECT=y
|
||||
CONFIG_IP6_NF_TARGET_SYNPROXY=y
|
||||
CONFIG_IP6_NF_MANGLE=y
|
||||
CONFIG_IP6_NF_RAW=y
|
||||
CONFIG_IP6_NF_NAT=y
|
||||
CONFIG_IP6_NF_TARGET_MASQUERADE=y
|
||||
CONFIG_IP6_NF_TARGET_NPT=y
|
||||
CONFIG_NF_CONNTRACK_BRIDGE=y
|
||||
CONFIG_BRIDGE=y
|
||||
CONFIG_NETLINK_DIAG=y
|
||||
CONFIG_BT=y
|
||||
CONFIG_BT_RFCOMM=y
|
||||
CONFIG_BT_RFCOMM_TTY=y
|
||||
CONFIG_BT_BNEP=y
|
||||
CONFIG_BT_HIDP=y
|
||||
CONFIG_BT_HS=y
|
||||
CONFIG_BT_HCIUART=y
|
||||
CONFIG_BT_HCIUART_BCSP=y
|
||||
CONFIG_CFG80211=m
|
||||
CONFIG_MAC80211=m
|
||||
CONFIG_RFKILL=y
|
||||
CONFIG_UEVENT_HELPER=y
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_ALLOW_DEV_COREDUMP is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
# CONFIG_MTD_OF_PARTS is not set
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_BLOCK=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_WIREGUARD=y
|
||||
CONFIG_TUN=y
|
||||
# CONFIG_NET_VENDOR_ALACRITECH is not set
|
||||
# CONFIG_NET_VENDOR_AMAZON is not set
|
||||
# CONFIG_NET_VENDOR_AQUANTIA is not set
|
||||
# CONFIG_NET_VENDOR_ARC is not set
|
||||
# CONFIG_NET_VENDOR_AURORA is not set
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
# CONFIG_NET_VENDOR_CADENCE is not set
|
||||
# CONFIG_NET_VENDOR_CAVIUM is not set
|
||||
# CONFIG_NET_VENDOR_CORTINA is not set
|
||||
# CONFIG_NET_VENDOR_EZCHIP is not set
|
||||
# CONFIG_NET_VENDOR_HUAWEI is not set
|
||||
# CONFIG_NET_VENDOR_INTEL is not set
|
||||
# CONFIG_NET_VENDOR_MARVELL is not set
|
||||
# CONFIG_NET_VENDOR_MICREL is not set
|
||||
# CONFIG_NET_VENDOR_MICROCHIP is not set
|
||||
# CONFIG_NET_VENDOR_MICROSEMI is not set
|
||||
# CONFIG_NET_VENDOR_NATSEMI is not set
|
||||
# CONFIG_NET_VENDOR_NETRONOME is not set
|
||||
# CONFIG_NET_VENDOR_NI is not set
|
||||
# CONFIG_NET_VENDOR_QUALCOMM is not set
|
||||
# CONFIG_NET_VENDOR_RENESAS is not set
|
||||
# CONFIG_NET_VENDOR_ROCKER is not set
|
||||
# CONFIG_NET_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_NET_VENDOR_SEEQ is not set
|
||||
# CONFIG_NET_VENDOR_SOLARFLARE is not set
|
||||
# CONFIG_NET_VENDOR_SOCIONEXT is not set
|
||||
CONFIG_STMMAC_ETH=y
|
||||
# CONFIG_DWMAC_GENERIC is not set
|
||||
# CONFIG_NET_VENDOR_SYNOPSYS is not set
|
||||
# CONFIG_NET_VENDOR_VIA is not set
|
||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
||||
CONFIG_CVITEK_PHY=y
|
||||
CONFIG_PPP=y
|
||||
CONFIG_PPPOE=y
|
||||
CONFIG_PPP_ASYNC=y
|
||||
CONFIG_PPP_SYNC_TTY=y
|
||||
CONFIG_SLIP=y
|
||||
# CONFIG_USB_NET_DRIVERS is not set
|
||||
# CONFIG_WLAN_VENDOR_ADMTEK is not set
|
||||
# CONFIG_WLAN_VENDOR_ATH is not set
|
||||
# CONFIG_WLAN_VENDOR_ATMEL is not set
|
||||
# CONFIG_WLAN_VENDOR_BROADCOM is not set
|
||||
# CONFIG_WLAN_VENDOR_CISCO is not set
|
||||
# CONFIG_WLAN_VENDOR_INTEL is not set
|
||||
# CONFIG_WLAN_VENDOR_INTERSIL is not set
|
||||
# CONFIG_WLAN_VENDOR_MARVELL is not set
|
||||
# CONFIG_WLAN_VENDOR_MEDIATEK is not set
|
||||
# CONFIG_WLAN_VENDOR_RALINK is not set
|
||||
# CONFIG_WLAN_VENDOR_RSI is not set
|
||||
# CONFIG_WLAN_VENDOR_ST is not set
|
||||
# CONFIG_WLAN_VENDOR_TI is not set
|
||||
# CONFIG_WLAN_VENDOR_ZYDAS is not set
|
||||
CONFIG_INPUT_MOUSEDEV=y
|
||||
CONFIG_INPUT_MOUSEDEV_PSAUX=y
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_KEYBOARD_GPIO=y
|
||||
CONFIG_INPUT_TOUCHSCREEN=y
|
||||
CONFIG_TOUCHSCREEN_GOODIX=y
|
||||
# CONFIG_VT is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=5
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=5
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
|
||||
CONFIG_SERIAL_DEV_BUS=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_DESIGNWARE_PLATFORM=y
|
||||
# CONFIG_PTP_1588_CLOCK is not set
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_CVITEK_PINCTRL_CV1835=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_DWAPB=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_NETLINK=y
|
||||
CONFIG_THERMAL_WRITABLE_TRIPS=y
|
||||
CONFIG_THERMAL_EMULATION=y
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
CONFIG_VIDEO_V4L2_SUBDEV_API=y
|
||||
# CONFIG_DVB_NET is not set
|
||||
# CONFIG_DVB_DYNAMIC_MINORS is not set
|
||||
CONFIG_V4L_PLATFORM_DRIVERS=y
|
||||
CONFIG_V4L_MEM2MEM_DRIVERS=y
|
||||
CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
|
||||
CONFIG_VIDEO_CVITEK_CIF=m
|
||||
CONFIG_VIDEO_CVITEK_SNS_I2C=m
|
||||
# CONFIG_MEDIA_TUNER_SIMPLE is not set
|
||||
# CONFIG_MEDIA_TUNER_TDA18250 is not set
|
||||
# CONFIG_MEDIA_TUNER_TDA8290 is not set
|
||||
# CONFIG_MEDIA_TUNER_TDA827X is not set
|
||||
# CONFIG_MEDIA_TUNER_TDA18271 is not set
|
||||
# CONFIG_MEDIA_TUNER_TDA9887 is not set
|
||||
# CONFIG_MEDIA_TUNER_TEA5761 is not set
|
||||
# CONFIG_MEDIA_TUNER_TEA5767 is not set
|
||||
# CONFIG_MEDIA_TUNER_MT20XX is not set
|
||||
# CONFIG_MEDIA_TUNER_MT2060 is not set
|
||||
# CONFIG_MEDIA_TUNER_MT2063 is not set
|
||||
# CONFIG_MEDIA_TUNER_MT2266 is not set
|
||||
# CONFIG_MEDIA_TUNER_MT2131 is not set
|
||||
# CONFIG_MEDIA_TUNER_QT1010 is not set
|
||||
# CONFIG_MEDIA_TUNER_XC2028 is not set
|
||||
# CONFIG_MEDIA_TUNER_XC5000 is not set
|
||||
# CONFIG_MEDIA_TUNER_XC4000 is not set
|
||||
# CONFIG_MEDIA_TUNER_MXL5005S is not set
|
||||
# CONFIG_MEDIA_TUNER_MXL5007T is not set
|
||||
# CONFIG_MEDIA_TUNER_MC44S803 is not set
|
||||
# CONFIG_MEDIA_TUNER_MAX2165 is not set
|
||||
# CONFIG_MEDIA_TUNER_TDA18218 is not set
|
||||
# CONFIG_MEDIA_TUNER_FC0011 is not set
|
||||
# CONFIG_MEDIA_TUNER_FC0012 is not set
|
||||
# CONFIG_MEDIA_TUNER_FC0013 is not set
|
||||
# CONFIG_MEDIA_TUNER_TDA18212 is not set
|
||||
# CONFIG_MEDIA_TUNER_E4000 is not set
|
||||
# CONFIG_MEDIA_TUNER_FC2580 is not set
|
||||
# CONFIG_MEDIA_TUNER_M88RS6000T is not set
|
||||
# CONFIG_MEDIA_TUNER_TUA9001 is not set
|
||||
# CONFIG_MEDIA_TUNER_SI2157 is not set
|
||||
# CONFIG_MEDIA_TUNER_IT913X is not set
|
||||
# CONFIG_MEDIA_TUNER_R820T is not set
|
||||
# CONFIG_MEDIA_TUNER_MXL301RF is not set
|
||||
# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set
|
||||
# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set
|
||||
# CONFIG_DVB_STB0899 is not set
|
||||
# CONFIG_DVB_STB6100 is not set
|
||||
# CONFIG_DVB_STV090x is not set
|
||||
# CONFIG_DVB_STV0910 is not set
|
||||
# CONFIG_DVB_STV6110x is not set
|
||||
# CONFIG_DVB_STV6111 is not set
|
||||
# CONFIG_DVB_MXL5XX is not set
|
||||
# CONFIG_DVB_M88DS3103 is not set
|
||||
# CONFIG_DVB_DRXK is not set
|
||||
# CONFIG_DVB_TDA18271C2DD is not set
|
||||
# CONFIG_DVB_SI2165 is not set
|
||||
# CONFIG_DVB_MN88472 is not set
|
||||
# CONFIG_DVB_MN88473 is not set
|
||||
# CONFIG_DVB_CX24110 is not set
|
||||
# CONFIG_DVB_CX24123 is not set
|
||||
# CONFIG_DVB_MT312 is not set
|
||||
# CONFIG_DVB_ZL10036 is not set
|
||||
# CONFIG_DVB_ZL10039 is not set
|
||||
# CONFIG_DVB_S5H1420 is not set
|
||||
# CONFIG_DVB_STV0288 is not set
|
||||
# CONFIG_DVB_STB6000 is not set
|
||||
# CONFIG_DVB_STV0299 is not set
|
||||
# CONFIG_DVB_STV6110 is not set
|
||||
# CONFIG_DVB_STV0900 is not set
|
||||
# CONFIG_DVB_TDA8083 is not set
|
||||
# CONFIG_DVB_TDA10086 is not set
|
||||
# CONFIG_DVB_TDA8261 is not set
|
||||
# CONFIG_DVB_VES1X93 is not set
|
||||
# CONFIG_DVB_TUNER_ITD1000 is not set
|
||||
# CONFIG_DVB_TUNER_CX24113 is not set
|
||||
# CONFIG_DVB_TDA826X is not set
|
||||
# CONFIG_DVB_TUA6100 is not set
|
||||
# CONFIG_DVB_CX24116 is not set
|
||||
# CONFIG_DVB_CX24117 is not set
|
||||
# CONFIG_DVB_CX24120 is not set
|
||||
# CONFIG_DVB_SI21XX is not set
|
||||
# CONFIG_DVB_TS2020 is not set
|
||||
# CONFIG_DVB_DS3000 is not set
|
||||
# CONFIG_DVB_MB86A16 is not set
|
||||
# CONFIG_DVB_TDA10071 is not set
|
||||
# CONFIG_DVB_SP8870 is not set
|
||||
# CONFIG_DVB_SP887X is not set
|
||||
# CONFIG_DVB_CX22700 is not set
|
||||
# CONFIG_DVB_CX22702 is not set
|
||||
# CONFIG_DVB_S5H1432 is not set
|
||||
# CONFIG_DVB_DRXD is not set
|
||||
# CONFIG_DVB_L64781 is not set
|
||||
# CONFIG_DVB_TDA1004X is not set
|
||||
# CONFIG_DVB_NXT6000 is not set
|
||||
# CONFIG_DVB_MT352 is not set
|
||||
# CONFIG_DVB_ZL10353 is not set
|
||||
# CONFIG_DVB_DIB3000MB is not set
|
||||
# CONFIG_DVB_DIB3000MC is not set
|
||||
# CONFIG_DVB_DIB7000M is not set
|
||||
# CONFIG_DVB_DIB7000P is not set
|
||||
# CONFIG_DVB_DIB9000 is not set
|
||||
# CONFIG_DVB_TDA10048 is not set
|
||||
# CONFIG_DVB_AF9013 is not set
|
||||
# CONFIG_DVB_EC100 is not set
|
||||
# CONFIG_DVB_STV0367 is not set
|
||||
# CONFIG_DVB_CXD2820R is not set
|
||||
# CONFIG_DVB_CXD2841ER is not set
|
||||
# CONFIG_DVB_RTL2830 is not set
|
||||
# CONFIG_DVB_RTL2832 is not set
|
||||
# CONFIG_DVB_RTL2832_SDR is not set
|
||||
# CONFIG_DVB_SI2168 is not set
|
||||
# CONFIG_DVB_ZD1301_DEMOD is not set
|
||||
# CONFIG_DVB_VES1820 is not set
|
||||
# CONFIG_DVB_TDA10021 is not set
|
||||
# CONFIG_DVB_TDA10023 is not set
|
||||
# CONFIG_DVB_STV0297 is not set
|
||||
# CONFIG_DVB_NXT200X is not set
|
||||
# CONFIG_DVB_OR51211 is not set
|
||||
# CONFIG_DVB_OR51132 is not set
|
||||
# CONFIG_DVB_BCM3510 is not set
|
||||
# CONFIG_DVB_LGDT330X is not set
|
||||
# CONFIG_DVB_LGDT3305 is not set
|
||||
# CONFIG_DVB_LGDT3306A is not set
|
||||
# CONFIG_DVB_LG2160 is not set
|
||||
# CONFIG_DVB_S5H1409 is not set
|
||||
# CONFIG_DVB_AU8522_DTV is not set
|
||||
# CONFIG_DVB_AU8522_V4L is not set
|
||||
# CONFIG_DVB_S5H1411 is not set
|
||||
# CONFIG_DVB_S921 is not set
|
||||
# CONFIG_DVB_DIB8000 is not set
|
||||
# CONFIG_DVB_MB86A20S is not set
|
||||
# CONFIG_DVB_TC90522 is not set
|
||||
# CONFIG_DVB_MN88443X is not set
|
||||
# CONFIG_DVB_PLL is not set
|
||||
# CONFIG_DVB_TUNER_DIB0070 is not set
|
||||
# CONFIG_DVB_TUNER_DIB0090 is not set
|
||||
# CONFIG_DVB_DRX39XYJ is not set
|
||||
# CONFIG_DVB_LNBH25 is not set
|
||||
# CONFIG_DVB_LNBH29 is not set
|
||||
# CONFIG_DVB_LNBP21 is not set
|
||||
# CONFIG_DVB_LNBP22 is not set
|
||||
# CONFIG_DVB_ISL6405 is not set
|
||||
# CONFIG_DVB_ISL6421 is not set
|
||||
# CONFIG_DVB_ISL6423 is not set
|
||||
# CONFIG_DVB_A8293 is not set
|
||||
# CONFIG_DVB_LGS8GL5 is not set
|
||||
# CONFIG_DVB_LGS8GXX is not set
|
||||
# CONFIG_DVB_ATBM8830 is not set
|
||||
# CONFIG_DVB_TDA665x is not set
|
||||
# CONFIG_DVB_IX2505V is not set
|
||||
# CONFIG_DVB_M88RS2000 is not set
|
||||
# CONFIG_DVB_AF9033 is not set
|
||||
# CONFIG_DVB_HORUS3A is not set
|
||||
# CONFIG_DVB_ASCOT2E is not set
|
||||
# CONFIG_DVB_HELENE is not set
|
||||
# CONFIG_DVB_CXD2099 is not set
|
||||
# CONFIG_DVB_SP2 is not set
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_SIMPLE=y
|
||||
CONFIG_FB_CVITEK=m
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
# CONFIG_SND_SUPPORT_OLD_API is not set
|
||||
# CONFIG_SND_DRIVERS is not set
|
||||
CONFIG_SND_HDA_PREALLOC_SIZE=1
|
||||
# CONFIG_SND_USB is not set
|
||||
CONFIG_SND_SOC=y
|
||||
CONFIG_SND_SOC_CV182XA_CV182XAADC=y
|
||||
CONFIG_SND_SOC_CV182XA_CV182XADAC=y
|
||||
CONFIG_SND_CV1835_I2S=y
|
||||
CONFIG_SND_SOC_CV182XAADC=y
|
||||
CONFIG_SND_SOC_CV182XADAC=y
|
||||
CONFIG_SND_SOC_CV1835_USE_AUDIO_PLL=y
|
||||
CONFIG_CV1835_I2S_SUBSYS=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_DWC2=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_VBUS_DRAW=500
|
||||
CONFIG_U_SERIAL_CONSOLE=y
|
||||
CONFIG_USB_CONFIGFS=y
|
||||
CONFIG_USB_CONFIGFS_SERIAL=y
|
||||
CONFIG_USB_CONFIGFS_ACM=y
|
||||
CONFIG_USB_CONFIGFS_ECM=y
|
||||
CONFIG_USB_CONFIGFS_RNDIS=y
|
||||
CONFIG_USB_CONFIGFS_EEM=y
|
||||
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
|
||||
CONFIG_USB_CONFIGFS_F_FS=y
|
||||
CONFIG_USB_CONFIGFS_F_UAC1=y
|
||||
CONFIG_USB_CONFIGFS_F_UVC=y
|
||||
CONFIG_USB_ROLE_SWITCH=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MMC_SDHCI_CVI=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_DW_DMAC_CVITEK=y
|
||||
# CONFIG_VIRTIO_MENU is not set
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_ION=y
|
||||
CONFIG_ION_SYSTEM_HEAP=y
|
||||
CONFIG_ION_CARVEOUT_HEAP=y
|
||||
CONFIG_ION_CMA_HEAP=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_CV1835_SYSDMA_REMAP=y
|
||||
CONFIG_PWM=y
|
||||
CONFIG_SIFIVE_PLIC=y
|
||||
CONFIG_ANDROID=y
|
||||
CONFIG_EXT4_FS=y
|
||||
# CONFIG_MANDATORY_FILE_LOCKING is not set
|
||||
CONFIG_FUSE_FS=y
|
||||
CONFIG_CUSE=y
|
||||
CONFIG_OVERLAY_FS=y
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
# CONFIG_PROC_PAGE_MONITOR is not set
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_JFFS2_FS_WBUF_VERIFY=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
CONFIG_SQUASHFS=y
|
||||
# CONFIG_SQUASHFS_ZLIB is not set
|
||||
CONFIG_SQUASHFS_LZ4=y
|
||||
CONFIG_SQUASHFS_XZ=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NLS_ISO8859_2=y
|
||||
CONFIG_NLS_ISO8859_3=y
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
# CONFIG_XZ_DEC_X86 is not set
|
||||
# CONFIG_XZ_DEC_POWERPC is not set
|
||||
# CONFIG_XZ_DEC_IA64 is not set
|
||||
# CONFIG_XZ_DEC_ARMTHUMB is not set
|
||||
# CONFIG_XZ_DEC_SPARC is not set
|
||||
CONFIG_DMA_CMA=y
|
||||
CONFIG_CMA_SIZE_MBYTES=0
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_DYNAMIC_DEBUG=y
|
||||
# CONFIG_ENABLE_MUST_CHECK is not set
|
||||
# CONFIG_FRAME_POINTER is not set
|
||||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_DEBUG_MISC is not set
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
# CONFIG_DEBUG_PREEMPT is not set
|
||||
# CONFIG_RCU_TRACE is not set
|
||||
# CONFIG_FTRACE is not set
|
||||
# CONFIG_RUNTIME_TESTING_MENU is not set
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
From b14006687e8039270be43bdbc1b272495edea681 Mon Sep 17 00:00:00 2001
|
||||
From: Justin Hammond <justin@dynam.ac>
|
||||
Date: Wed, 6 Mar 2024 00:12:58 +0800
|
||||
Subject: [PATCH] fix up monitor path
|
||||
|
||||
---
|
||||
make_helpers/fip.mk | 3 ++-
|
||||
1 file changed, 2 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/make_helpers/fip.mk b/make_helpers/fip.mk
|
||||
index e314c57..3c5a7cc 100644
|
||||
--- a/make_helpers/fip.mk
|
||||
+++ b/make_helpers/fip.mk
|
||||
@@ -11,7 +11,8 @@ CHIP_CONF_PATH = ${BUILD_PLAT}/chip_conf.bin
|
||||
ifeq (${BOOT_CPU},aarch64)
|
||||
MONITOR_PATH = plat/${CHIP_ARCH}/prebuilt/bl31.bin
|
||||
else ifeq (${BOOT_CPU},riscv)
|
||||
-MONITOR_PATH = ../opensbi/build/platform/generic/firmware/fw_dynamic.bin
|
||||
+#MONITOR_PATH = ../opensbi/build/platform/generic/firmware/fw_dynamic.bin
|
||||
+MONITOR_PATH = ${FW_DYNAMIC}
|
||||
endif
|
||||
|
||||
fip%: export BLCP_IMG_RUNADDR=0x05200200
|
||||
--
|
||||
2.44.0
|
||||
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,25 @@
|
|||
From 2c68482a1dd3a3e7181d290224f8056e1f37c350 Mon Sep 17 00:00:00 2001
|
||||
From: Lu <gravitydiv10@protonmail.com>
|
||||
Date: Mon, 19 Feb 2024 22:24:55 +0800
|
||||
Subject: [PATCH 3/4] interdrv: v2: fb: default enable double buffer
|
||||
|
||||
---
|
||||
interdrv/v2/fb/fb.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/interdrv/v2/fb/fb.c b/interdrv/v2/fb/fb.c
|
||||
index 90591b1..11cf5e0 100644
|
||||
--- a/interdrv/v2/fb/fb.c
|
||||
+++ b/interdrv/v2/fb/fb.c
|
||||
@@ -46,7 +46,7 @@ static bool double_buffer;
|
||||
static int scale;
|
||||
static bool fb_on_sc;
|
||||
static int rdma_window;
|
||||
-static int option;
|
||||
+static int option = 1; // default enable double buffer
|
||||
|
||||
static const struct fb_fix_screeninfo cvifb_fix = {
|
||||
.id = "cvifb",
|
||||
--
|
||||
2.35.8
|
||||
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
From beef50ac736ad25ee1683bcf3bb263e9625f4051 Mon Sep 17 00:00:00 2001
|
||||
From: Lu <gravitydiv10@protonmail.com>
|
||||
Date: Mon, 19 Feb 2024 22:50:05 +0800
|
||||
Subject: [PATCH 4/4] interdrv: v2: fb: fix pixel format for licheervnao, add
|
||||
param for bpp select
|
||||
|
||||
---
|
||||
interdrv/v2/fb/fb.c | 30 +++++++++++++++++++++++-------
|
||||
1 file changed, 23 insertions(+), 7 deletions(-)
|
||||
|
||||
diff --git a/interdrv/v2/fb/fb.c b/interdrv/v2/fb/fb.c
|
||||
index 11cf5e0..93f18ad 100644
|
||||
--- a/interdrv/v2/fb/fb.c
|
||||
+++ b/interdrv/v2/fb/fb.c
|
||||
@@ -47,6 +47,7 @@ static int scale;
|
||||
static bool fb_on_sc;
|
||||
static int rdma_window;
|
||||
static int option = 1; // default enable double buffer
|
||||
+static int opt_bpp = 32;
|
||||
|
||||
static const struct fb_fix_screeninfo cvifb_fix = {
|
||||
.id = "cvifb",
|
||||
@@ -333,20 +334,20 @@ static int cvifb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
|
||||
var->blue.offset = 0;
|
||||
var->transp.length = var->red.length = var->green.length = var->blue.length = 4;
|
||||
} else {
|
||||
- // ARGB1555
|
||||
+ // ABGR1555
|
||||
var->transp.offset = 15;
|
||||
- var->red.offset = 10;
|
||||
+ var->blue.offset = 10;
|
||||
var->green.offset = 5;
|
||||
- var->blue.offset = 0;
|
||||
+ var->red.offset = 0;
|
||||
var->transp.length = 1;
|
||||
var->red.length = var->green.length = var->blue.length = 5;
|
||||
}
|
||||
break;
|
||||
- case 32: // ARGB8888
|
||||
+ case 32: // ABGR8888
|
||||
var->transp.offset = 24;
|
||||
- var->red.offset = 16;
|
||||
+ var->blue.offset = 16;
|
||||
var->green.offset = 8;
|
||||
- var->blue.offset = 0;
|
||||
+ var->red.offset = 0;
|
||||
var->transp.length = 8;
|
||||
var->red.length = var->green.length = var->blue.length = 8;
|
||||
break;
|
||||
@@ -722,7 +723,15 @@ int cvifb_probe(struct platform_device *pdev)
|
||||
sclr_disp_get_hw_timing(&timing);
|
||||
info->var.xres = timing.hfde_end - timing.hfde_start + 1;
|
||||
info->var.yres = timing.vfde_end - timing.vfde_start + 1;
|
||||
- info->var.bits_per_pixel = 16;
|
||||
+ switch (opt_bpp) {
|
||||
+ case 16: case 32:
|
||||
+ info->var.bits_per_pixel = opt_bpp;
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_err(info->device, "bpp %d not support, fallback to 32\n", opt_bpp);
|
||||
+ info->var.bits_per_pixel = 32;
|
||||
+ break;
|
||||
+ }
|
||||
info->var.xres_virtual = VXRES_SIZE(info->var.xres, info->var.bits_per_pixel);
|
||||
info->var.yres_virtual =
|
||||
double_buffer ? (info->var.yres * 2) : info->var.yres;
|
||||
@@ -859,6 +868,13 @@ module_param(rdma_window, int, 0444);
|
||||
* - bit[1]: if true, fb on vpss not vo
|
||||
*/
|
||||
module_param(option, int, 0444);
|
||||
+
|
||||
+/* opt_bpp:
|
||||
+ * - 16: ABGR 1555
|
||||
+ * - 32: ABGR 8888
|
||||
+ */
|
||||
+module_param(opt_bpp, int, 0444);
|
||||
+
|
||||
MODULE_PARM_DESC(mode_option, "Default video mode (320x240-32@60', etc)");
|
||||
MODULE_PARM_DESC(scale, "scale up of the fb canvas");
|
||||
|
||||
--
|
||||
2.35.8
|
||||
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
From 83e8586b20da0e1a40ae96bdd88cfd7963b1e5e8 Mon Sep 17 00:00:00 2001
|
||||
From: Justin Hammond <justin@dynam.ac>
|
||||
Date: Tue, 5 Mar 2024 17:56:41 +0800
|
||||
Subject: [PATCH] add licheervnano patches
|
||||
|
||||
---
|
||||
include/cvi_board_memmap.h | 37 +++++++++++
|
||||
include/cvipart.h | 13 ++++
|
||||
4 files changed, 153 insertions(+), 1 deletion(-)
|
||||
create mode 100644 include/cvi_board_memmap.h
|
||||
create mode 100644 include/cvipart.h
|
||||
|
||||
diff --git a/include/cvi_board_memmap.h b/include/cvi_board_memmap.h
|
||||
new file mode 100644
|
||||
index 0000000000..6f1e4068d6
|
||||
--- /dev/null
|
||||
+++ b/include/cvi_board_memmap.h
|
||||
@@ -0,0 +1,37 @@
|
||||
+#ifndef __BOARD_MMAP__ab4bdb87__
|
||||
+#define __BOARD_MMAP__ab4bdb87__
|
||||
+
|
||||
+#define CONFIG_SYS_TEXT_BASE 0x80200000 /* offset 2.0MiB */
|
||||
+#define CVIMMAP_ATF_SIZE 0x80000 /* 512.0KiB */
|
||||
+#define CVIMMAP_BOOTLOGO_ADDR 0x8ab30000 /* offset 171.1875MiB */
|
||||
+#define CVIMMAP_BOOTLOGO_SIZE 0x7d0000 /* 7.8125MiB */
|
||||
+#define CVIMMAP_CONFIG_SYS_INIT_SP_ADDR 0x82800000 /* offset 40.0MiB */
|
||||
+#define CVIMMAP_CVI_UPDATE_HEADER_ADDR 0x817ffc00 /* offset 23.9990234375MiB */
|
||||
+#define CVIMMAP_CVI_UPDATE_HEADER_SIZE 0x400 /* 1.0KiB */
|
||||
+#define CVIMMAP_DRAM_BASE 0x80000000 /* offset 0.0KiB */
|
||||
+#define CVIMMAP_DRAM_SIZE 0x10000000 /* 256.0MiB */
|
||||
+#define CVIMMAP_FRAMEBUFFER_ADDR 0x8ab30000 /* offset 171.1875MiB */
|
||||
+#define CVIMMAP_FRAMEBUFFER_SIZE 0x7d0000 /* 7.8125MiB */
|
||||
+#define CVIMMAP_FREERTOS_ADDR 0x8fe00000 /* offset 254.0MiB */
|
||||
+#define CVIMMAP_FREERTOS_RESERVED_ION_SIZE 0x1600000 /* 22.0MiB */
|
||||
+#define CVIMMAP_FREERTOS_SIZE 0x200000 /* 2.0MiB */
|
||||
+#define CVIMMAP_FSBL_C906L_START_ADDR 0x8fe00000 /* offset 254.0MiB */
|
||||
+#define CVIMMAP_FSBL_UNZIP_ADDR 0x81800000 /* offset 24.0MiB */
|
||||
+#define CVIMMAP_FSBL_UNZIP_SIZE 0x1000000 /* 16.0MiB */
|
||||
+#define CVIMMAP_H26X_BITSTREAM_ADDR 0x8b300000 /* offset 179.0MiB */
|
||||
+#define CVIMMAP_H26X_BITSTREAM_SIZE 0x200000 /* 2.0MiB */
|
||||
+#define CVIMMAP_H26X_ENC_BUFF_ADDR 0x8b500000 /* offset 181.0MiB */
|
||||
+#define CVIMMAP_H26X_ENC_BUFF_SIZE 0x0 /* 0.0KiB */
|
||||
+#define CVIMMAP_ION_ADDR 0x8b300000 /* offset 179.0MiB */
|
||||
+#define CVIMMAP_ION_SIZE 0x4b00000 /* 75.0MiB */
|
||||
+#define CVIMMAP_ISP_MEM_BASE_ADDR 0x8b500000 /* offset 181.0MiB */
|
||||
+#define CVIMMAP_ISP_MEM_BASE_SIZE 0x1400000 /* 20.0MiB */
|
||||
+#define CVIMMAP_KERNEL_MEMORY_ADDR 0x80000000 /* offset 0.0KiB */
|
||||
+#define CVIMMAP_KERNEL_MEMORY_SIZE 0xfe00000 /* 254.0MiB */
|
||||
+#define CVIMMAP_MONITOR_ADDR 0x80000000 /* offset 0.0KiB */
|
||||
+#define CVIMMAP_OPENSBI_FDT_ADDR 0x80080000 /* offset 512.0KiB */
|
||||
+#define CVIMMAP_OPENSBI_SIZE 0x80000 /* 512.0KiB */
|
||||
+#define CVIMMAP_UIMAG_ADDR 0x81800000 /* offset 24.0MiB */
|
||||
+#define CVIMMAP_UIMAG_SIZE 0x1000000 /* 16.0MiB */
|
||||
+
|
||||
+#endif /* __BOARD_MMAP__ab4bdb87__ */
|
||||
diff --git a/include/cvipart.h b/include/cvipart.h
|
||||
new file mode 100644
|
||||
index 0000000000..067fce6bda
|
||||
--- /dev/null
|
||||
+++ b/include/cvipart.h
|
||||
@@ -0,0 +1,13 @@
|
||||
+/* this file should be generated by mkcvipart.py,please do not modify this file manually*/
|
||||
+
|
||||
+#ifndef CVIPART_H
|
||||
+#define CVIPART_H
|
||||
+#ifndef CONFIG_ENV_IS_NOWHERE
|
||||
+#define CONFIG_ENV_IS_NOWHERE
|
||||
+#endif
|
||||
+#define CONFIG_ENV_SIZE 0x20000
|
||||
+#define PART_LAYOUT ""
|
||||
+#define ROOTFS_DEV "/dev/mmcblk0p2"
|
||||
+#define PARTS_OFFSET ""
|
||||
+#define SPL_BOOT_PART_OFFSET 0x0
|
||||
+#endif
|
||||
\ No newline at end of file
|
||||
--
|
||||
2.44.0
|
||||
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
From 86730361403e82f549246b3cdc66cdf461d52835 Mon Sep 17 00:00:00 2001
|
||||
From: Lu Hui <luhui@sipeed.com>
|
||||
Date: Tue, 20 Feb 2024 16:30:48 +0800
|
||||
Subject: [PATCH 3/3] sound/soc/cvitek/cv181x*: adc/dac default volume is too
|
||||
low, so modify it
|
||||
|
||||
---
|
||||
sound/soc/cvitek/cv181xadc.c | 64 +++++++++++++++++++++---------------
|
||||
sound/soc/cvitek/cv181xdac.c | 28 ++++++++++------
|
||||
2 files changed, 55 insertions(+), 37 deletions(-)
|
||||
|
||||
diff --git a/sound/soc/cvitek/cv181xadc.c b/sound/soc/cvitek/cv181xadc.c
|
||||
index 91d101b62ea9..51fd19fb9b16 100644
|
||||
--- a/sound/soc/cvitek/cv181xadc.c
|
||||
+++ b/sound/soc/cvitek/cv181xadc.c
|
||||
@@ -445,6 +445,39 @@ static struct cv181xadc *file_adc_dev(struct file *file)
|
||||
return container_of(file->private_data, struct cv181xadc, miscdev);
|
||||
}
|
||||
|
||||
+static void adc_set_volume(struct cv181xadc *adc, u32 val) {
|
||||
+ u32 temp;
|
||||
+ u32 val2;
|
||||
+
|
||||
+ pr_info("adc: set volume %d\n", val);
|
||||
+ pr_debug("adc: ACODEC_SET_INPUT_VOL\n");
|
||||
+ if ((val < 0) | (val > 24))
|
||||
+ pr_err("Only support range 0 [0dB] ~ 24 [48dB]\n");
|
||||
+ else if (val == 0) {
|
||||
+ /* set mute */
|
||||
+ temp = adc_read_reg(adc->adc_base, AUDIO_PHY_RXADC_ANA2)
|
||||
+ | AUDIO_PHY_REG_MUTEL_ON
|
||||
+ | AUDIO_PHY_REG_MUTER_ON;
|
||||
+ adc_write_reg(adc->adc_base, AUDIO_PHY_RXADC_ANA2, temp);
|
||||
+ temp = (adc_vol_list[val] | (adc_vol_list[val] << 16));
|
||||
+ adc_write_reg(adc->adc_base, AUDIO_PHY_RXADC_ANA0, temp);
|
||||
+ } else {
|
||||
+ val2 = (adc_read_reg(adc->adc_base, AUDIO_PHY_RXADC_ANA0) & AUDIO_PHY_REG_ADC_VOLL_MASK);
|
||||
+ for (temp = 0; temp < 25; temp++) {
|
||||
+ if (val2 == adc_vol_list[temp])
|
||||
+ break;
|
||||
+ }
|
||||
+ if (temp == 0) {
|
||||
+ /* unmute */
|
||||
+ temp = adc_read_reg(adc->adc_base, AUDIO_PHY_RXADC_ANA2)
|
||||
+ & AUDIO_PHY_REG_MUTEL_OFF
|
||||
+ & AUDIO_PHY_REG_MUTEL_OFF;
|
||||
+ adc_write_reg(adc->adc_base, AUDIO_PHY_RXADC_ANA2, temp);
|
||||
+ }
|
||||
+ temp = (adc_vol_list[val] | (adc_vol_list[val] << 16));
|
||||
+ adc_write_reg(adc->adc_base, AUDIO_PHY_RXADC_ANA0, temp);
|
||||
+ }
|
||||
+};
|
||||
|
||||
static long adc_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
@@ -473,33 +506,7 @@ static long adc_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
||||
break;
|
||||
|
||||
case ACODEC_SET_INPUT_VOL:
|
||||
- pr_debug("adc: ACODEC_SET_INPUT_VOL\n");
|
||||
- if ((val < 0) | (val > 24))
|
||||
- pr_err("Only support range 0 [0dB] ~ 24 [48dB]\n");
|
||||
- else if (val == 0) {
|
||||
- /* set mute */
|
||||
- temp = adc_read_reg(adc->adc_base, AUDIO_PHY_RXADC_ANA2)
|
||||
- | AUDIO_PHY_REG_MUTEL_ON
|
||||
- | AUDIO_PHY_REG_MUTER_ON;
|
||||
- adc_write_reg(adc->adc_base, AUDIO_PHY_RXADC_ANA2, temp);
|
||||
- temp = (adc_vol_list[val] | (adc_vol_list[val] << 16));
|
||||
- adc_write_reg(adc->adc_base, AUDIO_PHY_RXADC_ANA0, temp);
|
||||
- } else {
|
||||
- val2 = (adc_read_reg(adc->adc_base, AUDIO_PHY_RXADC_ANA0) & AUDIO_PHY_REG_ADC_VOLL_MASK);
|
||||
- for (temp = 0; temp < 25; temp++) {
|
||||
- if (val2 == adc_vol_list[temp])
|
||||
- break;
|
||||
- }
|
||||
- if (temp == 0) {
|
||||
- /* unmute */
|
||||
- temp = adc_read_reg(adc->adc_base, AUDIO_PHY_RXADC_ANA2)
|
||||
- & AUDIO_PHY_REG_MUTEL_OFF
|
||||
- & AUDIO_PHY_REG_MUTEL_OFF;
|
||||
- adc_write_reg(adc->adc_base, AUDIO_PHY_RXADC_ANA2, temp);
|
||||
- }
|
||||
- temp = (adc_vol_list[val] | (adc_vol_list[val] << 16));
|
||||
- adc_write_reg(adc->adc_base, AUDIO_PHY_RXADC_ANA0, temp);
|
||||
- }
|
||||
+ adc_set_volume(adc, val);
|
||||
break;
|
||||
|
||||
case ACODEC_GET_INPUT_VOL:
|
||||
@@ -883,6 +890,9 @@ static int cv181xadc_probe(struct platform_device *pdev)
|
||||
ctrl1 = adc_read_reg(adc->adc_base, AUDIO_PHY_RXADC_CTRL1);
|
||||
adc_write_reg(adc->adc_base, AUDIO_PHY_RXADC_CTRL1, ctrl1 | AUDIO_ADC_IGR_INIT_EN);
|
||||
|
||||
+ /* default input volume is 20 */
|
||||
+ adc_set_volume(adc, 20);
|
||||
+
|
||||
return devm_snd_soc_register_component(&pdev->dev, &soc_component_dev_cv181xadc,
|
||||
&cv181xadc_dai, 1);
|
||||
}
|
||||
diff --git a/sound/soc/cvitek/cv181xdac.c b/sound/soc/cvitek/cv181xdac.c
|
||||
index 6c8b520cc40e..d75140dbe592 100644
|
||||
--- a/sound/soc/cvitek/cv181xdac.c
|
||||
+++ b/sound/soc/cvitek/cv181xdac.c
|
||||
@@ -311,6 +311,19 @@ static struct cv181xdac *file_dac_dev(struct file *file)
|
||||
return container_of(file->private_data, struct cv181xdac, miscdev);
|
||||
}
|
||||
|
||||
+static void dac_set_volume(struct cv181xdac *dac, u32 val) {
|
||||
+ u32 temp;
|
||||
+ pr_debug("dac: ACODEC_SET_OUTPUT_VOL with val=%d\n", val);
|
||||
+ if ((val < 0) | (val > 32))
|
||||
+ pr_err("Only support range 0 [mute] ~ 32 [maximum]\n");
|
||||
+ else {
|
||||
+ temp = dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_AFE1)
|
||||
+ & ~(AUDIO_PHY_REG_TXDAC_GAIN_UB_0_MASK | AUDIO_PHY_REG_TXDAC_GAIN_UB_1_MASK);
|
||||
+ temp |= DAC_VOL_L(val) | DAC_VOL_R(val);
|
||||
+ dac_write_reg(dac->dac_base, AUDIO_PHY_TXDAC_AFE1, temp);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
static long dac_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
|
||||
@@ -336,16 +349,7 @@ static long dac_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
||||
break;
|
||||
|
||||
case ACODEC_SET_OUTPUT_VOL:
|
||||
- pr_debug("dac: ACODEC_SET_OUTPUT_VOL with val=%d\n", val);
|
||||
-
|
||||
- if ((val < 0) | (val > 32))
|
||||
- pr_err("Only support range 0 [mute] ~ 32 [maximum]\n");
|
||||
- else {
|
||||
- temp = dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_AFE1)
|
||||
- & ~(AUDIO_PHY_REG_TXDAC_GAIN_UB_0_MASK | AUDIO_PHY_REG_TXDAC_GAIN_UB_1_MASK);
|
||||
- temp |= DAC_VOL_L(val) | DAC_VOL_R(val);
|
||||
- dac_write_reg(dac->dac_base, AUDIO_PHY_TXDAC_AFE1, temp);
|
||||
- }
|
||||
+ dac_set_volume(dac, val);
|
||||
break;
|
||||
|
||||
case ACODEC_GET_OUTPUT_VOL:
|
||||
@@ -654,6 +658,10 @@ static int cv181xdac_probe(struct platform_device *pdev)
|
||||
gpio_direction_output(mute_pin_r, 1);
|
||||
gpio_set_value(mute_pin_r, 0);
|
||||
}
|
||||
+
|
||||
+
|
||||
+ /* default volume 15 */
|
||||
+ dac_set_volume(dac, 15);
|
||||
return devm_snd_soc_register_component(&pdev->dev, &soc_component_dev_cv181xdac,
|
||||
&cv181xdac_dai, 1);
|
||||
}
|
||||
--
|
||||
2.40.1
|
||||
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,25 @@
|
|||
From 979cdbace41bb1891fa920382471af76f4798d7f Mon Sep 17 00:00:00 2001
|
||||
From: Lu Hui <luhui@sipeed.com>
|
||||
Date: Wed, 28 Feb 2024 16:28:28 +0800
|
||||
Subject: [PATCH 5/5] hynitron_core.c: disable CLEAR_POINT message
|
||||
|
||||
---
|
||||
drivers/input/touchscreen/hynitron/hynitron_core.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/input/touchscreen/hynitron/hynitron_core.c b/drivers/input/touchscreen/hynitron/hynitron_core.c
|
||||
index bb09fd27828d..dfcca64616cd 100644
|
||||
--- a/drivers/input/touchscreen/hynitron/hynitron_core.c
|
||||
+++ b/drivers/input/touchscreen/hynitron/hynitron_core.c
|
||||
@@ -1046,7 +1046,7 @@ static void cst3xx_touch_report(struct work_struct *work)
|
||||
goto END;
|
||||
|
||||
CLR_POINT:
|
||||
- HYN_ERROR(" CLEAR POINT.\n");
|
||||
+ //HYN_ERROR(" CLEAR POINT.\n");
|
||||
#if HYN_MT_PROTOCOL_B_EN
|
||||
for(i=0; i<=10; i++) {
|
||||
input_mt_slot(hyn_ts_data->input_dev, i);
|
||||
--
|
||||
2.40.1
|
||||
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
From 164ab544efaeda73354bd93662e8ba4e44ab719b Mon Sep 17 00:00:00 2001
|
||||
From: Justin Hammond <justin@dynam.ac>
|
||||
Date: Tue, 5 Mar 2024 21:49:42 +0800
|
||||
Subject: [PATCH] add no-stack-protector to build flags
|
||||
|
||||
---
|
||||
Makefile | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/Makefile b/Makefile
|
||||
index eeffe6b..6b64205 100644
|
||||
--- a/Makefile
|
||||
+++ b/Makefile
|
||||
@@ -203,7 +203,7 @@ GENFLAGS += $(libsbiutils-genflags-y)
|
||||
GENFLAGS += $(platform-genflags-y)
|
||||
GENFLAGS += $(firmware-genflags-y)
|
||||
|
||||
-CFLAGS = -g -Wall -Werror -ffreestanding -nostdlib -fno-strict-aliasing -O2
|
||||
+CFLAGS = -g -Wall -Werror -ffreestanding -nostdlib -fno-stack-protector -fno-strict-aliasing -O2
|
||||
CFLAGS += -fno-omit-frame-pointer -fno-optimize-sibling-calls
|
||||
CFLAGS += -mno-save-restore -mstrict-align
|
||||
CFLAGS += -mabi=$(PLATFORM_RISCV_ABI) -march=$(PLATFORM_RISCV_ISA)
|
||||
--
|
||||
2.44.0
|
||||
|
||||
|
|
@ -0,0 +1,202 @@
|
|||
From 83e8586b20da0e1a40ae96bdd88cfd7963b1e5e8 Mon Sep 17 00:00:00 2001
|
||||
From: Justin Hammond <justin@dynam.ac>
|
||||
Date: Tue, 5 Mar 2024 17:56:41 +0800
|
||||
Subject: [PATCH] add licheervnano patches
|
||||
|
||||
---
|
||||
board/cvitek/mars/board.c | 2 +-
|
||||
board/cvitek/mars/cvi_board_init.c | 102 +++++++++++++++++++++++++++++
|
||||
include/cvi_board_memmap.h | 37 +++++++++++
|
||||
include/cvipart.h | 13 ++++
|
||||
4 files changed, 153 insertions(+), 1 deletion(-)
|
||||
create mode 100644 board/cvitek/mars/cvi_board_init.c
|
||||
create mode 100644 include/cvi_board_memmap.h
|
||||
create mode 100644 include/cvipart.h
|
||||
|
||||
diff --git a/board/cvitek/mars/board.c b/board/cvitek/mars/board.c
|
||||
index 9c961ac149..2fac11353e 100644
|
||||
--- a/board/cvitek/mars/board.c
|
||||
+++ b/board/cvitek/mars/board.c
|
||||
@@ -152,7 +152,7 @@ void pinmux_config(int io_type)
|
||||
}
|
||||
}
|
||||
|
||||
-#include "../cvi_board_init.c"
|
||||
+#include "cvi_board_init.c"
|
||||
|
||||
#if defined(CONFIG_PHY_CVITEK) /* config cvitek cv181x eth internal phy on ASIC board */
|
||||
static void cv181x_ephy_id_init(void)
|
||||
diff --git a/board/cvitek/mars/cvi_board_init.c b/board/cvitek/mars/cvi_board_init.c
|
||||
new file mode 100644
|
||||
index 0000000000..d8bb55b693
|
||||
--- /dev/null
|
||||
+++ b/board/cvitek/mars/cvi_board_init.c
|
||||
@@ -0,0 +1,102 @@
|
||||
+__attribute__((optimize("O0")))
|
||||
+// 1.26ms
|
||||
+void suck_loop(uint64_t loop) {
|
||||
+ loop = loop * 50 * 100;
|
||||
+ uint64_t a;
|
||||
+ while (loop > 0) {
|
||||
+ a = loop / (uint64_t)99;
|
||||
+ a = loop / (uint64_t)77;
|
||||
+ a = loop / (uint64_t)55;
|
||||
+ a = loop / (uint64_t)33;
|
||||
+ a = loop / (uint64_t)11;
|
||||
+ a = loop / (uint64_t)999;
|
||||
+ a = loop / (uint64_t)777;
|
||||
+ a = loop / (uint64_t)555;
|
||||
+ a = loop / (uint64_t)333;
|
||||
+ a = loop / (uint64_t)111;
|
||||
+ a = loop / (uint64_t)9999;
|
||||
+ a = loop / (uint64_t)7777;
|
||||
+ a = loop / (uint64_t)5555;
|
||||
+ a = loop / (uint64_t)3333;
|
||||
+ a = loop / (uint64_t)1111;
|
||||
+ a = loop / (uint64_t)99999;
|
||||
+ a = loop / (uint64_t)77777;
|
||||
+ a = loop / (uint64_t)55555;
|
||||
+ a = loop / (uint64_t)33333;
|
||||
+ a = loop / (uint64_t)11111;
|
||||
+ loop--;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+int cvi_board_init(void)
|
||||
+{
|
||||
+ uint32_t val;
|
||||
+
|
||||
+ // wifi power reset
|
||||
+ mmio_write_32(0x0300104C, 0x3); // GPIOA 26
|
||||
+ val = mmio_read_32(0x03020004); // GPIOA DIR
|
||||
+ val |= (1 << 26); // output
|
||||
+ mmio_write_32(0x03020004, val);
|
||||
+
|
||||
+ val = mmio_read_32(0x03020000); // signal level
|
||||
+ val &= ~(1 << 26); // set level to low
|
||||
+ mmio_write_32(0x03020000, val);
|
||||
+
|
||||
+ suck_loop(200);
|
||||
+
|
||||
+ val = mmio_read_32(0x03020000); // signal level
|
||||
+ val |= (1 << 26); // set level to high
|
||||
+ mmio_write_32(0x03020000, val);
|
||||
+
|
||||
+ // wifi sdio pinmux
|
||||
+ mmio_write_32(0x030010D0, 0x0); // D3
|
||||
+ mmio_write_32(0x030010D4, 0x0); // D2
|
||||
+ mmio_write_32(0x030010D8, 0x0); // D1
|
||||
+ mmio_write_32(0x030010DC, 0x0); // D0
|
||||
+ mmio_write_32(0x030010E0, 0x0); // CMD
|
||||
+ mmio_write_32(0x030010E4, 0x0); // CLK
|
||||
+
|
||||
+ // uart bluetooth
|
||||
+ mmio_write_32(0x03001070, 0x1); // GPIOA 28 UART1 TX
|
||||
+ mmio_write_32(0x03001074, 0x1); // GPIOA 29 UART1 RX
|
||||
+ mmio_write_32(0x03001068, 0x4); // GPIOA 18 UART1 CTS
|
||||
+ mmio_write_32(0x03001064, 0x4); // GPIOA 19 UART1 RTS
|
||||
+
|
||||
+ // PWM
|
||||
+ //mmio_write_32(0x03001068, 0x2); // GPIOA 18 PWM 6
|
||||
+
|
||||
+ // lcd reset
|
||||
+ mmio_write_32(0x030010A4, 0x0); // PWRGPIO 0 GPIO_MODE
|
||||
+
|
||||
+ // lcd backlight
|
||||
+ //mmio_write_32(0x030010EC, 0x0); // GPIOB 0 PWM0_BUCK
|
||||
+ mmio_write_32(0x030010EC, 0x3); // GPIOB 0 GPIO_MODE
|
||||
+ val = mmio_read_32(0x03021004); // GPIOB DIR
|
||||
+ val |= (1 << 0); // output
|
||||
+ mmio_write_32(0x03021004, val);
|
||||
+ val = mmio_read_32(0x03021000); // signal level
|
||||
+ val |= (1 << 0); // set level to high
|
||||
+ mmio_write_32(0x03021000, val);
|
||||
+
|
||||
+ // camera function
|
||||
+ mmio_write_32(0x0300116C, 0x5); // RX4N CAM_MCLK0
|
||||
+
|
||||
+ // camera/tp i2c
|
||||
+ mmio_write_32(0x03001090, 0x5); // PWR_GPIO6 IIC4_SCL
|
||||
+ mmio_write_32(0x03001098, 0x5); // PWR_GPIO8 IIC4_SDA
|
||||
+
|
||||
+ // tp function
|
||||
+ mmio_write_32(0x03001084, 0x3); // PWR_SEQ1 PWR_GPIO[3]
|
||||
+ mmio_write_32(0x03001088, 0x3); // PWR_SEQ2 PWR_GPIO[4]
|
||||
+ mmio_write_32(0x05027078, 0x11);// Unlock PWR_GPIO[3]
|
||||
+ mmio_write_32(0x0502707c, 0x11);// Unlock PWR_GPIO[4]
|
||||
+
|
||||
+ // bitbang i2c for maixcam
|
||||
+#ifdef MAIXCAM
|
||||
+ mmio_write_32(0x0300105C, 0x3);// GPIOA 23 GPIO_MODE
|
||||
+ mmio_write_32(0x03001060, 0x3);// GPIOA 24 GPIO_MODE
|
||||
+#endif
|
||||
+ // wait hardware bootup
|
||||
+ suck_loop(100);
|
||||
+ return 0;
|
||||
+}
|
||||
diff --git a/include/cvi_board_memmap.h b/include/cvi_board_memmap.h
|
||||
new file mode 100644
|
||||
index 0000000000..6f1e4068d6
|
||||
--- /dev/null
|
||||
+++ b/include/cvi_board_memmap.h
|
||||
@@ -0,0 +1,37 @@
|
||||
+#ifndef __BOARD_MMAP__ab4bdb87__
|
||||
+#define __BOARD_MMAP__ab4bdb87__
|
||||
+
|
||||
+#define CONFIG_SYS_TEXT_BASE 0x80200000 /* offset 2.0MiB */
|
||||
+#define CVIMMAP_ATF_SIZE 0x80000 /* 512.0KiB */
|
||||
+#define CVIMMAP_BOOTLOGO_ADDR 0x8ab30000 /* offset 171.1875MiB */
|
||||
+#define CVIMMAP_BOOTLOGO_SIZE 0x7d0000 /* 7.8125MiB */
|
||||
+#define CVIMMAP_CONFIG_SYS_INIT_SP_ADDR 0x82800000 /* offset 40.0MiB */
|
||||
+#define CVIMMAP_CVI_UPDATE_HEADER_ADDR 0x817ffc00 /* offset 23.9990234375MiB */
|
||||
+#define CVIMMAP_CVI_UPDATE_HEADER_SIZE 0x400 /* 1.0KiB */
|
||||
+#define CVIMMAP_DRAM_BASE 0x80000000 /* offset 0.0KiB */
|
||||
+#define CVIMMAP_DRAM_SIZE 0x10000000 /* 256.0MiB */
|
||||
+#define CVIMMAP_FRAMEBUFFER_ADDR 0x8ab30000 /* offset 171.1875MiB */
|
||||
+#define CVIMMAP_FRAMEBUFFER_SIZE 0x7d0000 /* 7.8125MiB */
|
||||
+#define CVIMMAP_FREERTOS_ADDR 0x8fe00000 /* offset 254.0MiB */
|
||||
+#define CVIMMAP_FREERTOS_RESERVED_ION_SIZE 0x1600000 /* 22.0MiB */
|
||||
+#define CVIMMAP_FREERTOS_SIZE 0x200000 /* 2.0MiB */
|
||||
+#define CVIMMAP_FSBL_C906L_START_ADDR 0x8fe00000 /* offset 254.0MiB */
|
||||
+#define CVIMMAP_FSBL_UNZIP_ADDR 0x81800000 /* offset 24.0MiB */
|
||||
+#define CVIMMAP_FSBL_UNZIP_SIZE 0x1000000 /* 16.0MiB */
|
||||
+#define CVIMMAP_H26X_BITSTREAM_ADDR 0x8b300000 /* offset 179.0MiB */
|
||||
+#define CVIMMAP_H26X_BITSTREAM_SIZE 0x200000 /* 2.0MiB */
|
||||
+#define CVIMMAP_H26X_ENC_BUFF_ADDR 0x8b500000 /* offset 181.0MiB */
|
||||
+#define CVIMMAP_H26X_ENC_BUFF_SIZE 0x0 /* 0.0KiB */
|
||||
+#define CVIMMAP_ION_ADDR 0x8b300000 /* offset 179.0MiB */
|
||||
+#define CVIMMAP_ION_SIZE 0x4b00000 /* 75.0MiB */
|
||||
+#define CVIMMAP_ISP_MEM_BASE_ADDR 0x8b500000 /* offset 181.0MiB */
|
||||
+#define CVIMMAP_ISP_MEM_BASE_SIZE 0x1400000 /* 20.0MiB */
|
||||
+#define CVIMMAP_KERNEL_MEMORY_ADDR 0x80000000 /* offset 0.0KiB */
|
||||
+#define CVIMMAP_KERNEL_MEMORY_SIZE 0xfe00000 /* 254.0MiB */
|
||||
+#define CVIMMAP_MONITOR_ADDR 0x80000000 /* offset 0.0KiB */
|
||||
+#define CVIMMAP_OPENSBI_FDT_ADDR 0x80080000 /* offset 512.0KiB */
|
||||
+#define CVIMMAP_OPENSBI_SIZE 0x80000 /* 512.0KiB */
|
||||
+#define CVIMMAP_UIMAG_ADDR 0x81800000 /* offset 24.0MiB */
|
||||
+#define CVIMMAP_UIMAG_SIZE 0x1000000 /* 16.0MiB */
|
||||
+
|
||||
+#endif /* __BOARD_MMAP__ab4bdb87__ */
|
||||
diff --git a/include/cvipart.h b/include/cvipart.h
|
||||
new file mode 100644
|
||||
index 0000000000..067fce6bda
|
||||
--- /dev/null
|
||||
+++ b/include/cvipart.h
|
||||
@@ -0,0 +1,13 @@
|
||||
+/* this file should be generated by mkcvipart.py,please do not modify this file manually*/
|
||||
+
|
||||
+#ifndef CVIPART_H
|
||||
+#define CVIPART_H
|
||||
+#ifndef CONFIG_ENV_IS_NOWHERE
|
||||
+#define CONFIG_ENV_IS_NOWHERE
|
||||
+#endif
|
||||
+#define CONFIG_ENV_SIZE 0x20000
|
||||
+#define PART_LAYOUT ""
|
||||
+#define ROOTFS_DEV "/dev/mmcblk0p2"
|
||||
+#define PARTS_OFFSET ""
|
||||
+#define SPL_BOOT_PART_OFFSET 0x0
|
||||
+#endif
|
||||
\ No newline at end of file
|
||||
--
|
||||
2.44.0
|
||||
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
From 8ab57b457674714d692c9fd57a9ff4f54d9827e2 Mon Sep 17 00:00:00 2001
|
||||
From: Justin Hammond <justin@dynam.ac>
|
||||
Date: Thu, 7 Mar 2024 12:26:37 +0800
|
||||
Subject: [PATCH] fix compile errors
|
||||
|
||||
---
|
||||
common/splash_source.c | 6 +++---
|
||||
include/configs/cv181x-asic.h | 1 +
|
||||
2 files changed, 4 insertions(+), 3 deletions(-)
|
||||
|
||||
diff --git a/common/splash_source.c b/common/splash_source.c
|
||||
index d05670f5ee..ff0a0ebd2d 100644
|
||||
--- a/common/splash_source.c
|
||||
+++ b/common/splash_source.c
|
||||
@@ -323,7 +323,7 @@ static int splash_load_fit(struct splash_location *location, u32 bmp_load_addr)
|
||||
if (res < 0)
|
||||
return res;
|
||||
|
||||
- img_header = (struct image_header *)bmp_load_addr;
|
||||
+ img_header = (struct image_header *)(uintptr_t)bmp_load_addr;
|
||||
if (image_get_magic(img_header) != FDT_MAGIC) {
|
||||
printf("Could not find FDT magic\n");
|
||||
return -EINVAL;
|
||||
@@ -333,7 +333,7 @@ static int splash_load_fit(struct splash_location *location, u32 bmp_load_addr)
|
||||
|
||||
/* Read in entire FIT */
|
||||
fit_header = (const u32 *)(bmp_load_addr + header_size);
|
||||
- res = splash_storage_read_raw(location, (u32)fit_header, fit_size);
|
||||
+ res = splash_storage_read_raw(location, (uintptr_t)fit_header, fit_size);
|
||||
if (res < 0)
|
||||
return res;
|
||||
|
||||
@@ -358,7 +358,7 @@ static int splash_load_fit(struct splash_location *location, u32 bmp_load_addr)
|
||||
/* Extract the splash data from FIT */
|
||||
/* 1. Test if splash is in FIT internal data. */
|
||||
if (!fit_image_get_data(fit_header, node_offset, &internal_splash_data, &internal_splash_size))
|
||||
- memmove((void *)bmp_load_addr, internal_splash_data, internal_splash_size);
|
||||
+ memmove((void *)(uintptr_t)bmp_load_addr, internal_splash_data, internal_splash_size);
|
||||
/* 2. Test if splash is in FIT external data with fixed position. */
|
||||
else if (!fit_image_get_data_position(fit_header, node_offset, &external_splash_addr))
|
||||
is_splash_external = true;
|
||||
diff --git a/include/configs/mars-asic.h b/include/configs/mars-asic.h
|
||||
index 12cdefac84..9fea234ba0 100644
|
||||
--- a/include/configs/mars-asic.h
|
||||
+++ b/include/configs/mars-asic.h
|
||||
@@ -181,6 +181,8 @@
|
||||
#define CONFIG_GATEWAYIP 192.168.0.11
|
||||
#define CONFIG_SERVERIP 192.168.56.101
|
||||
|
||||
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (6 * 1024 * 1024)
|
||||
+
|
||||
#ifdef CONFIG_USE_DEFAULT_ENV
|
||||
/* The following Settings are chip dependent */
|
||||
/******************************************************************************/
|
||||
--
|
||||
2.44.0
|
||||
|
||||
|
|
@ -0,0 +1,967 @@
|
|||
From afc08b2050cc6c8e49b130b773845c507cc73ec7 Mon Sep 17 00:00:00 2001
|
||||
From: Justin Hammond <justin@dynam.ac>
|
||||
Date: Wed, 6 Mar 2024 21:18:31 +0800
|
||||
Subject: [PATCH] add panel drivers
|
||||
|
||||
---
|
||||
include/cvitek/cvi_panels/cvi_panels.h | 45 ++++
|
||||
.../cvi_panels/dsi_st7701_d300fpc9307a.h | 162 +++++++++++++
|
||||
.../cvi_panels/dsi_st7701_dxq5d0019b480854.h | 190 +++++++++++++++
|
||||
.../cvi_panels/dsi_st7701_hd228001c31.h | 185 +++++++++++++++
|
||||
.../cvi_panels/dsi_st7701_hd228001c31_alt0.h | 224 ++++++++++++++++++
|
||||
include/cvitek/cvi_panels/dsi_zct2133v1.h | 77 ++++++
|
||||
6 files changed, 883 insertions(+)
|
||||
create mode 100644 include/cvitek/cvi_panels/dsi_st7701_d300fpc9307a.h
|
||||
create mode 100644 include/cvitek/cvi_panels/dsi_st7701_dxq5d0019b480854.h
|
||||
create mode 100644 include/cvitek/cvi_panels/dsi_st7701_hd228001c31.h
|
||||
create mode 100644 include/cvitek/cvi_panels/dsi_st7701_hd228001c31_alt0.h
|
||||
create mode 100644 include/cvitek/cvi_panels/dsi_zct2133v1.h
|
||||
|
||||
diff --git a/include/cvitek/cvi_panels/cvi_panels.h b/include/cvitek/cvi_panels/cvi_panels.h
|
||||
index d74bcd8c2b..23c436d7bf 100644
|
||||
--- a/include/cvitek/cvi_panels/cvi_panels.h
|
||||
+++ b/include/cvitek/cvi_panels/cvi_panels.h
|
||||
@@ -78,6 +78,15 @@ static struct panel_desc_s panel_desc = {
|
||||
.dsi_init_cmds = dsi_init_cmds_ota7290b_320x1280,
|
||||
.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_ota7290b_320x1280)
|
||||
};
|
||||
+#elif defined(MIPI_PANEL_ST7701_D300FPC9307A)
|
||||
+#include "dsi_st7701_d300fpc9307a.h"
|
||||
+static struct panel_desc_s panel_desc = {
|
||||
+ .panel_name = "ST7701-480x854",
|
||||
+ .dev_cfg = &dev_cfg_st7701_480x854,
|
||||
+ .hs_timing_cfg = &hs_timing_cfg_st7701_480x854,
|
||||
+ .dsi_init_cmds = dsi_init_cmds_st7701_480x854,
|
||||
+ .dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_st7701_480x854)
|
||||
+};
|
||||
#elif defined(MIPI_PANEL_OTA7290B_1920)
|
||||
#include "dsi_ota7290b_1920.h"
|
||||
static struct panel_desc_s panel_desc = {
|
||||
@@ -96,6 +105,15 @@ static struct panel_desc_s panel_desc = {
|
||||
.dsi_init_cmds = dsi_init_cmds_icn9707_480x1920,
|
||||
.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_icn9707_480x1920)
|
||||
};
|
||||
+#elif defined(MIPI_PANEL_ST7701_DXQ5D0019B480854)
|
||||
+#include "dsi_st7701_dxq5d0019b480854.h"
|
||||
+static struct panel_desc_s panel_desc = {
|
||||
+ .panel_name = "ST7701-480x854dxq",
|
||||
+ .dev_cfg = &dev_cfg_st7701_480x854dxq,
|
||||
+ .hs_timing_cfg = &hs_timing_cfg_st7701_480x854dxq,
|
||||
+ .dsi_init_cmds = dsi_init_cmds_st7701_480x854dxq,
|
||||
+ .dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_st7701_480x854dxq)
|
||||
+};
|
||||
#elif defined(MIPI_PANEL_3AML069LP01G)
|
||||
#include "dsi_3aml069lp01g.h"
|
||||
static struct panel_desc_s panel_desc = {
|
||||
@@ -114,6 +132,24 @@ static struct panel_desc_s panel_desc = {
|
||||
.dsi_init_cmds = dsi_init_cmds_st7701_480x800,
|
||||
.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_st7701_480x800)
|
||||
};
|
||||
+#elif defined(MIPI_PANEL_ST7701_HD228001C31)
|
||||
+#include "dsi_st7701_hd228001c31.h"
|
||||
+static struct panel_desc_s panel_desc = {
|
||||
+ .panel_name = "ST7701-368x552",
|
||||
+ .dev_cfg = &dev_cfg_st7701_368x552,
|
||||
+ .hs_timing_cfg = &hs_timing_cfg_st7701_368x552,
|
||||
+ .dsi_init_cmds = dsi_init_cmds_st7701_368x552,
|
||||
+ .dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_st7701_368x552)
|
||||
+};
|
||||
+#elif defined(MIPI_PANEL_ST7701_HD228001C31)
|
||||
+#include "dsi_st7701_hd228001c31_alt0.h"
|
||||
+static struct panel_desc_s panel_desc = {
|
||||
+ .panel_name = "ST7701-368x552-alt0",
|
||||
+ .dev_cfg = &dev_cfg_st7701_368x552_alt0,
|
||||
+ .hs_timing_cfg = &hs_timing_cfg_st7701_368x552_alt0,
|
||||
+ .dsi_init_cmds = dsi_init_cmds_st7701_368x552_alt0,
|
||||
+ .dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_st7701_368x552_alt0)
|
||||
+};
|
||||
#elif defined(MIPI_PANEL_ST7785M)
|
||||
#include "dsi_st7785m.h"
|
||||
static struct panel_desc_s panel_desc = {
|
||||
@@ -123,6 +159,15 @@ static struct panel_desc_s panel_desc = {
|
||||
.dsi_init_cmds = dsi_init_cmds_st7785m_240x320,
|
||||
.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_st7785m_240x320)
|
||||
};
|
||||
+#elif defined(MIPI_PANEL_ZCT2133V1)
|
||||
+#include "dsi_zct2133v1.h"
|
||||
+static struct panel_desc_s panel_desc = {
|
||||
+ .panel_name = "zct2133v1-800x1280",
|
||||
+ .dev_cfg = &dev_cfg_zct2133v1_800x1280,
|
||||
+ .hs_timing_cfg = &hs_timing_cfg_zct2133v1_800x1280,
|
||||
+ .dsi_init_cmds = dsi_init_cmds_zct2133v1_800x1280,
|
||||
+ .dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_zct2133v1_800x1280)
|
||||
+};
|
||||
#elif defined(I80_PANEL_ST7789V)
|
||||
#include "i80_st7789v.h"
|
||||
static struct panel_desc_s panel_desc = {
|
||||
diff --git a/include/cvitek/cvi_panels/dsi_st7701_d300fpc9307a.h b/include/cvitek/cvi_panels/dsi_st7701_d300fpc9307a.h
|
||||
new file mode 100644
|
||||
index 0000000000..059f52a57f
|
||||
--- /dev/null
|
||||
+++ b/include/cvitek/cvi_panels/dsi_st7701_d300fpc9307a.h
|
||||
@@ -0,0 +1,162 @@
|
||||
+#ifndef _MIPI_TX_PARAM_ST_7701_D300FPC9307A_H_
|
||||
+#define _MIPI_TX_PARAM_ST_7701_D300FPC9307A_H_
|
||||
+
|
||||
+#ifndef __UBOOT__
|
||||
+#include <linux/vo_mipi_tx.h>
|
||||
+#include <linux/cvi_comm_mipi_tx.h>
|
||||
+#else
|
||||
+#include <cvi_mipi.h>
|
||||
+#endif
|
||||
+
|
||||
+#define ST7701_D300FPC9307A_VACT 854
|
||||
+#define ST7701_D300FPC9307A_VSA 10
|
||||
+#define ST7701_D300FPC9307A_VBP 12
|
||||
+#define ST7701_D300FPC9307A_VFP 3
|
||||
+
|
||||
+#define ST7701_D300FPC9307A_HACT 480
|
||||
+#define ST7701_D300FPC9307A_HSA 32
|
||||
+#define ST7701_D300FPC9307A_HBP 80
|
||||
+#define ST7701_D300FPC9307A_HFP 48
|
||||
+
|
||||
+/*
|
||||
+#define ST7701_D300FPC9307A_VACT 854
|
||||
+#define ST7701_D300FPC9307A_VSA 10
|
||||
+#define ST7701_D300FPC9307A_VBP 42
|
||||
+#define ST7701_D300FPC9307A_VFP 4
|
||||
+
|
||||
+#define ST7701_D300FPC9307A_HACT 480
|
||||
+#define ST7701_D300FPC9307A_HSA 2
|
||||
+#define ST7701_D300FPC9307A_HBP 43
|
||||
+#define ST7701_D300FPC9307A_HFP 8
|
||||
+*/
|
||||
+
|
||||
+#define D300_PIXEL_CLK(x) ((x##_VACT + x##_VSA + x##_VBP + x##_VFP) \
|
||||
+ * (x##_HACT + x##_HSA + x##_HBP + x##_HFP) * 60 / 1000)
|
||||
+
|
||||
+struct combo_dev_cfg_s dev_cfg_st7701_480x854 = {
|
||||
+ .devno = 0,
|
||||
+ .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_CLK, MIPI_TX_LANE_1, -1, -1},
|
||||
+ .lane_pn_swap = {false, false, false, false, false},
|
||||
+ .output_mode = OUTPUT_MODE_DSI_VIDEO,
|
||||
+ .video_mode = BURST_MODE,
|
||||
+ .output_format = OUT_FORMAT_RGB_24_BIT,
|
||||
+ .sync_info = {
|
||||
+ .vid_hsa_pixels = ST7701_D300FPC9307A_HSA,
|
||||
+ .vid_hbp_pixels = ST7701_D300FPC9307A_HBP,
|
||||
+ .vid_hfp_pixels = ST7701_D300FPC9307A_HFP,
|
||||
+ .vid_hline_pixels = ST7701_D300FPC9307A_HACT,
|
||||
+ .vid_vsa_lines = ST7701_D300FPC9307A_VSA,
|
||||
+ .vid_vbp_lines = ST7701_D300FPC9307A_VBP,
|
||||
+ .vid_vfp_lines = ST7701_D300FPC9307A_VFP,
|
||||
+ .vid_active_lines = ST7701_D300FPC9307A_VACT,
|
||||
+ .vid_vsa_pos_polarity = true,
|
||||
+ .vid_hsa_pos_polarity = false,
|
||||
+ },
|
||||
+ .pixel_clk = D300_PIXEL_CLK(ST7701_D300FPC9307A),
|
||||
+};
|
||||
+
|
||||
+const struct hs_settle_s hs_timing_cfg_st7701_480x854 = { .prepare = 6, .zero = 32, .trail = 1 };
|
||||
+
|
||||
+#ifndef CVI_U8
|
||||
+#define CVI_U8 unsigned char
|
||||
+#endif
|
||||
+
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_0[] = {0x11, 0x00 }; // turn off sleep mode
|
||||
+ //{REGFLAG_DELAY, 60, {} },
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_1[] = {0xff, 0x77, 0x01, 0x00, 0x00, 0x13 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_2[] = {0xef, 0x08 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_3[] = {0xff, 0x77, 0x01, 0x00, 0x00, 0x10 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_4[] = {0xc0, 0xe9, 0x03 }; // display line setting, set to 854
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_5[] = {0xc1, 0x10, 0x0c }; // vbp
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_6[] = {0xc2, 0x20, 0x0a }; //
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_7[] = {0xcc, 0x10 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_8[] = {0xb0, 0x00, 0x23, 0x2a, 0x0a, 0x0e, 0x03, 0x12, 0x06,
|
||||
+ 0x06, 0x2a, 0x00, 0x10, 0x0f, 0x2d, 0x34, 0x1f };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_9[] = {0xb1, 0x00, 0x24, 0x2b, 0x0f, 0x12, 0x07, 0x15, 0x0a,
|
||||
+ 0x0a, 0x2b, 0x08, 0x13, 0x10, 0x2d, 0x33, 0x1f };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_10[] = {0xff, 0x77, 0x01, 0x00, 0x00, 0x11 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_11[] = {0xb0, 0x4d };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_12[] = {0xb1, 0x48 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_13[] = {0xb2, 0x84 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_14[] = {0xb3, 0x80 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_15[] = {0xb5, 0x45 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_16[] = {0xb7, 0x85 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_17[] = {0xb8, 0x33 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_18[] = {0xc1, 0x78 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_19[] = {0xc2, 0x78 };
|
||||
+//{REGFLAG_DELAY, 50, {} },
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_20[] = {0xd0, 0x88 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_21[] = {0xe0, 0x00, 0x00, 0x02 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_22[] = {0xe1, 0x06, 0xa0, 0x08, 0xa0, 0x05, 0xa0, 0x07, 0xa0, 0x00, 0x44, 0x44 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_23[] = {0xe2, 0x30, 0x30, 0x44, 0x44, 0x6e, 0xa0, 0x00, 0x00, 0x6e, 0xa0, 0x00, 0x00 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_24[] = {0xe3, 0x00, 0x00, 0x33, 0x33 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_25[] = {0xe4, 0x44, 0x44 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_26[] = {0xe5, 0x0D, 0x69, 0x0a, 0xa0, 0x0f, 0x6b, 0x0a, 0xa0, 0x09,
|
||||
+ 0x65, 0x0a, 0xa0, 0x0b, 0x67, 0x0a, 0xa0 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_27[] = {0xe6, 0x00, 0x00, 0x33, 0x33 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_28[] = {0xe7, 0x44, 0x44 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_29[] = {0xe8, 0x0C, 0x68, 0x0a, 0xa0, 0x0e, 0x6a, 0x0a, 0xa0, 0x08, 0x64,
|
||||
+ 0x0a, 0xa0, 0x0a, 0x66, 0x0a, 0xa0 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_30[] = {0xe9, 0x36, 0x00 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_31[] = {0xeb, 0x00, 0x01, 0xe4, 0xe4, 0x44, 0x88, 0x40 };
|
||||
+//{0xec, 0x3c, 0x01 },
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_32[] = {0xed, 0xff, 0x45, 0x67, 0xfa, 0x01, 0x2b, 0xcf, 0xff, 0xff, 0xfc, 0xb2,
|
||||
+ 0x10, 0xaf, 0x76, 0x54, 0xff };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_33[] = {0xef, 0x10, 0x0d, 0x04, 0x08, 0x3f, 0x1f };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_34[] = {0x11 };
|
||||
+//{0xff, 0x77, 0x01, 0x00, 0x00, 0x00 },
|
||||
+//{REGFLAG_DELAY, 50, {} },
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_35[] = {0x3a, 0x55 };
|
||||
+static CVI_U8 data_st7701_d300fpc9307a_36[] = {0x29, 0x00 };
|
||||
+//{REGFLAG_END_OF_TABLE, 0x00, {} }
|
||||
+
|
||||
+
|
||||
+// len == 1 , type 0x05
|
||||
+// len == 2 , type 0x15 or type 23
|
||||
+// len >= 3 , type 0x29 or type 0x39
|
||||
+#define TYPE1 0x05
|
||||
+#define TYPE2 0x15
|
||||
+#define TYPE3 0x29
|
||||
+const struct dsc_instr dsi_init_cmds_st7701_480x854[] = {
|
||||
+ {.delay = 60, .data_type = TYPE2, .size = 2, .data = data_st7701_d300fpc9307a_0 },
|
||||
+ {.delay = 0, .data_type = TYPE3, .size = 6, .data = data_st7701_d300fpc9307a_1 },
|
||||
+ {.delay = 0, .data_type = TYPE2, .size = 2, .data = data_st7701_d300fpc9307a_2 },
|
||||
+ {.delay = 0, .data_type = TYPE3, .size = 6, .data = data_st7701_d300fpc9307a_3 },
|
||||
+ {.delay = 0, .data_type = TYPE3, .size = 3, .data = data_st7701_d300fpc9307a_4 },
|
||||
+ {.delay = 0, .data_type = TYPE3, .size = 3, .data = data_st7701_d300fpc9307a_5 },
|
||||
+ {.delay = 0, .data_type = TYPE3, .size = 3, .data = data_st7701_d300fpc9307a_6 },
|
||||
+ {.delay = 0, .data_type = TYPE2, .size = 2, .data = data_st7701_d300fpc9307a_7 },
|
||||
+ {.delay = 0, .data_type = TYPE3, .size = 17, .data = data_st7701_d300fpc9307a_8 },
|
||||
+ {.delay = 0, .data_type = TYPE3, .size = 17, .data = data_st7701_d300fpc9307a_9 },
|
||||
+ {.delay = 0, .data_type = TYPE3, .size = 6, .data = data_st7701_d300fpc9307a_10 },
|
||||
+ {.delay = 0, .data_type = TYPE2, .size = 2, .data = data_st7701_d300fpc9307a_11 },
|
||||
+ {.delay = 0, .data_type = TYPE2, .size = 2, .data = data_st7701_d300fpc9307a_12 },
|
||||
+ {.delay = 0, .data_type = TYPE2, .size = 2, .data = data_st7701_d300fpc9307a_13 },
|
||||
+ {.delay = 0, .data_type = TYPE2, .size = 2, .data = data_st7701_d300fpc9307a_14 },
|
||||
+ {.delay = 0, .data_type = TYPE2, .size = 2, .data = data_st7701_d300fpc9307a_15 },
|
||||
+ {.delay = 0, .data_type = TYPE2, .size = 2, .data = data_st7701_d300fpc9307a_16 },
|
||||
+ {.delay = 0, .data_type = TYPE2, .size = 2, .data = data_st7701_d300fpc9307a_17 },
|
||||
+ {.delay = 0, .data_type = TYPE2, .size = 2, .data = data_st7701_d300fpc9307a_18 },
|
||||
+ {.delay = 50, .data_type = TYPE2, .size = 2, .data = data_st7701_d300fpc9307a_19 },
|
||||
+ {.delay = 0, .data_type = TYPE2, .size = 2, .data = data_st7701_d300fpc9307a_20 },
|
||||
+ {.delay = 0, .data_type = TYPE3, .size = 4, .data = data_st7701_d300fpc9307a_21 },
|
||||
+ {.delay = 0, .data_type = TYPE3, .size = 12, .data = data_st7701_d300fpc9307a_22 },
|
||||
+ {.delay = 0, .data_type = TYPE3, .size = 13, .data = data_st7701_d300fpc9307a_23 },
|
||||
+ {.delay = 0, .data_type = TYPE3, .size = 5, .data = data_st7701_d300fpc9307a_24 },
|
||||
+ {.delay = 0, .data_type = TYPE3, .size = 3, .data = data_st7701_d300fpc9307a_25 },
|
||||
+ {.delay = 0, .data_type = TYPE3, .size = 17, .data = data_st7701_d300fpc9307a_26 },
|
||||
+ {.delay = 0, .data_type = TYPE3, .size = 5, .data = data_st7701_d300fpc9307a_27 },
|
||||
+ {.delay = 0, .data_type = TYPE3, .size = 3, .data = data_st7701_d300fpc9307a_28 },
|
||||
+ {.delay = 0, .data_type = TYPE3, .size = 17, .data = data_st7701_d300fpc9307a_29 },
|
||||
+ {.delay = 0, .data_type = TYPE3, .size = 3, .data = data_st7701_d300fpc9307a_30 },
|
||||
+ {.delay = 0, .data_type = TYPE3, .size = 8, .data = data_st7701_d300fpc9307a_31 },
|
||||
+ {.delay = 0, .data_type = TYPE3, .size = 17, .data = data_st7701_d300fpc9307a_32 },
|
||||
+ {.delay = 50, .data_type = TYPE3, .size = 7, .data = data_st7701_d300fpc9307a_33 },
|
||||
+ {.delay = 0, .data_type = TYPE1, .size = 1, .data = data_st7701_d300fpc9307a_34 },
|
||||
+ {.delay = 0, .data_type = TYPE2, .size = 2, .data = data_st7701_d300fpc9307a_35 },
|
||||
+ {.delay = 0, .data_type = TYPE2, .size = 2, .data = data_st7701_d300fpc9307a_36 },
|
||||
+};
|
||||
+
|
||||
+#else
|
||||
+#error "MIPI_TX_PARAM multi-delcaration!!"
|
||||
+#endif
|
||||
diff --git a/include/cvitek/cvi_panels/dsi_st7701_dxq5d0019b480854.h b/include/cvitek/cvi_panels/dsi_st7701_dxq5d0019b480854.h
|
||||
new file mode 100644
|
||||
index 0000000000..58c3194a69
|
||||
--- /dev/null
|
||||
+++ b/include/cvitek/cvi_panels/dsi_st7701_dxq5d0019b480854.h
|
||||
@@ -0,0 +1,190 @@
|
||||
+#ifndef _MIPI_TX_PARAM_ST_7701_DXQ5D0019B480854_H_
|
||||
+#define _MIPI_TX_PARAM_ST_7701_DXQ5D0019B480854_H_
|
||||
+
|
||||
+#ifndef __UBOOT__
|
||||
+#include <linux/vo_mipi_tx.h>
|
||||
+#include <linux/cvi_comm_mipi_tx.h>
|
||||
+#else
|
||||
+#include <cvi_mipi.h>
|
||||
+#endif
|
||||
+
|
||||
+/*
|
||||
+#define ST7701_DXQ5D0019B480854_VACT 854
|
||||
+#define ST7701_DXQ5D0019B480854_VSA 2
|
||||
+#define ST7701_DXQ5D0019B480854_VBP 20
|
||||
+#define ST7701_DXQ5D0019B480854_VFP 20
|
||||
+
|
||||
+#define ST7701_DXQ5D0019B480854_HACT 480
|
||||
+#define ST7701_DXQ5D0019B480854_HSA 10
|
||||
+#define ST7701_DXQ5D0019B480854_HBP 40
|
||||
+#define ST7701_DXQ5D0019B480854_HFP 40
|
||||
+*/
|
||||
+
|
||||
+#define ST7701_DXQ5D0019B480854_VACT 854
|
||||
+#define ST7701_DXQ5D0019B480854_VSA 10
|
||||
+#define ST7701_DXQ5D0019B480854_VBP 20
|
||||
+#define ST7701_DXQ5D0019B480854_VFP 3
|
||||
+
|
||||
+#define ST7701_DXQ5D0019B480854_HACT 480
|
||||
+#define ST7701_DXQ5D0019B480854_HSA 48
|
||||
+#define ST7701_DXQ5D0019B480854_HBP 72
|
||||
+#define ST7701_DXQ5D0019B480854_HFP 24
|
||||
+
|
||||
+#define DXQ_PIXEL_CLK(x) ((x##_VACT + x##_VSA + x##_VBP + x##_VFP) \
|
||||
+ * (x##_HACT + x##_HSA + x##_HBP + x##_HFP) * 60 / 1000)
|
||||
+
|
||||
+struct combo_dev_cfg_s dev_cfg_st7701_480x854dxq = {
|
||||
+ .devno = 0,
|
||||
+ .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_CLK, MIPI_TX_LANE_1, -1, -1},
|
||||
+ .lane_pn_swap = {false, false, false, false, false},
|
||||
+ .output_mode = OUTPUT_MODE_DSI_VIDEO,
|
||||
+ .video_mode = BURST_MODE,
|
||||
+ .output_format = OUT_FORMAT_RGB_24_BIT,
|
||||
+ .sync_info = {
|
||||
+ .vid_hsa_pixels = ST7701_DXQ5D0019B480854_HSA,
|
||||
+ .vid_hbp_pixels = ST7701_DXQ5D0019B480854_HBP,
|
||||
+ .vid_hfp_pixels = ST7701_DXQ5D0019B480854_HFP,
|
||||
+ .vid_hline_pixels = ST7701_DXQ5D0019B480854_HACT,
|
||||
+ .vid_vsa_lines = ST7701_DXQ5D0019B480854_VSA,
|
||||
+ .vid_vbp_lines = ST7701_DXQ5D0019B480854_VBP,
|
||||
+ .vid_vfp_lines = ST7701_DXQ5D0019B480854_VFP,
|
||||
+ .vid_active_lines = ST7701_DXQ5D0019B480854_VACT,
|
||||
+ .vid_vsa_pos_polarity = true,
|
||||
+ .vid_hsa_pos_polarity = false,
|
||||
+ },
|
||||
+ .pixel_clk = DXQ_PIXEL_CLK(ST7701_DXQ5D0019B480854),
|
||||
+};
|
||||
+
|
||||
+const struct hs_settle_s hs_timing_cfg_st7701_480x854dxq = { .prepare = 6, .zero = 32, .trail = 1 };
|
||||
+
|
||||
+#ifndef CVI_U8
|
||||
+#define CVI_U8 unsigned char
|
||||
+#endif
|
||||
+
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_0[] = {0x11, 0x00 }; // turn off sleep mode
|
||||
+//{REGFLAG_DELAY, 60, {} },
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_1[] = {0xff,0x77,0x01,0x00,0x00,0x10};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_2[] = {0xC0,0xE9,0x03};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_3[] = {0xC1,0x08,0x02};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_4[] = {0xC2,0x31,0x08};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_5[] = {0xCC,0x10};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_6[] = {0xB0,0x00,0x0B,0x10,0x0D,0x11,0x06,0x01,0x08,0x08,0x1D,0x04,0x10,0x10,0x27,0x30,0x19};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_7[] = {0xB1,0x00,0x0B,0x14,0x0C,0x11,0x05,0x03,0x08,0x08,0x20,0x04,0x13,0x10,0x28,0x30,0x19};
|
||||
+//------------------------------------End Gamma etting------------------------------------------//
|
||||
+//-------------------------------End Display Control setting------------------------------------//
|
||||
+//-------------------------------------Bank0 Setting End-----------------------------------------//
|
||||
+//---------------------------------------Bank1 setting----------------------------------------------//
|
||||
+//---------------------------- Power Control Registers Initial ---------------------------------//
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_8[] = {0xff,0x77,0x01,0x00,0x00,0x11};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_9[] = {0xB0,0x35};
|
||||
+//---------------------------------------Vcom setting----------------------------------------------//
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_10[] = {0xB1,0x38};
|
||||
+//-----------------------------------End Vcom Setting---------------------------------------------//
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_11[] = {0xB2,0x02};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_12[] = {0xB3,0x80};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_13[] = {0xB5,0x4E};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_14[] = {0xB7,0x85};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_15[] = {0xB8,0x20};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_16[] = {0xB9,0x10};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_17[] = {0xC1,0x78};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_18[] = {0xC2,0x78};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_19[] = {0xD0,0x88};
|
||||
+//-----------------------------End Power Control Registers Initial ----------------------------//
|
||||
+//Delayms (100);
|
||||
+//-------------------------------------GIP Setting-------------------------------------------------//
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_20[] = {0xE0,0x00,0x00,0x02};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_21[] = {0xE1,0x05,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x20,0x20};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_22[] = {0xE2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_23[] = {0xE3,0x00,0x00,0x33,0x00};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_24[] = {0xE4,0x22,0x00};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_25[] = {0xE5,0x07,0x34,0xA0,0xA0,0x05,0x34,0xA0,0xA0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_26[] = {0xE6,0x00,0x00,0x33,0x00};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_27[] = {0xE7,0x22,0x00};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_28[] = {0xE8,0x06,0x34,0xA0,0xA0,0x04,0x34,0xA0,0xA0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_29[] = {0xEB,0x02,0x00,0x10,0x10,0x00,0x00,0x00};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_30[] = {0xEC,0x02,0x00};
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_31[] = {0xED,0xAA,0x54,0x0B,0xBF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFB,0xB0,0x45,0xAA};
|
||||
+//-----------------------------------------End GIP Setting-----------------------------------------//
|
||||
+//--------------------------- Power Control Registers Initial End------------------------------//
|
||||
+//-------------------------------------Bank1 Setting------------------------------------------------//
|
||||
+//-----------------------------------//
|
||||
+// Example 1: Read - Direct Procedure
|
||||
+//-----------------------------------//
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_32[] = {0xFF,0x77,0x01,0x00,0x00,0x11};
|
||||
+//DCS_Long_Read_NP(0xA1,3,BUFFER+0);
|
||||
+//DCS_Long_Read_NP(0xDA,1,BUFFER+0);
|
||||
+//DCS_Long_Read_NP(0xDB,1,BUFFER+1);
|
||||
+//DCS_Long_Read_NP(0xDC,1,BUFFER+2);
|
||||
+
|
||||
+//DCS_Short_Write_1P(0x00);
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_33[] = {0x00};
|
||||
+//Delay(500);
|
||||
+//bist模式
|
||||
+//彩条
|
||||
+//static CVI_U8 data_st7701_dxq5d0019b480854_34[] = {0xFF,0x77,0x01,0x00,0x00,0x12};
|
||||
+//static CVI_U8 data_st7701_dxq5d0019b480854_35[] = {0xd1,0x81,0x10,0x03,0x03,0x08,0x01,0xA0,0x01,0xe0,0xB0,0x01,0xe0,0x03,0x20};
|
||||
+//static CVI_U8 data_st7701_dxq5d0019b480854_36[] = {0xd2,0x08};///彩条
|
||||
+//static CVI_U8 data_st7701_dxq5d0019b480854_37[] = {0xFF,0x77,0x01,0x00,0x00,0x10};
|
||||
+//static CVI_U8 data_st7701_dxq5d0019b480854_38[] = {0xC2,0x31,0x08};
|
||||
+//DCS_Short_Write_1P(0x29,0x00);
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_39[] = {0x29,0x00};
|
||||
+//Delay(100);
|
||||
+static CVI_U8 data_st7701_dxq5d0019b480854_40[] = {0x35,0x00};
|
||||
+
|
||||
+// len == 1 , type 0x05
|
||||
+// len == 2 , type 0x15 or type 23
|
||||
+// len >= 3 , type 0x29 or type 0x39
|
||||
+#define TYPE1_DCS_SHORT_WRITE 0x05
|
||||
+#define TYPE2_DCS_SHORT_WRITE 0x15
|
||||
+#define TYPE3_DCS_LONG_WRITE 0x39
|
||||
+#define TYPE3_GENERIC_LONG_WRITE 0x29
|
||||
+const struct dsc_instr dsi_init_cmds_st7701_480x854dxq[] = {
|
||||
+ {.delay = 60, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_dxq5d0019b480854_0 },
|
||||
+ {.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 6, .data = data_st7701_dxq5d0019b480854_1 },
|
||||
+ {.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 3, .data = data_st7701_dxq5d0019b480854_2 },
|
||||
+ {.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 3, .data = data_st7701_dxq5d0019b480854_3 },
|
||||
+ {.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 3, .data = data_st7701_dxq5d0019b480854_4 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_dxq5d0019b480854_5 },
|
||||
+ {.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 17, .data = data_st7701_dxq5d0019b480854_6 },
|
||||
+ {.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 17, .data = data_st7701_dxq5d0019b480854_7 },
|
||||
+ {.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 6, .data = data_st7701_dxq5d0019b480854_8 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_dxq5d0019b480854_9 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_dxq5d0019b480854_10 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_dxq5d0019b480854_11 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_dxq5d0019b480854_12 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_dxq5d0019b480854_13 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_dxq5d0019b480854_14 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_dxq5d0019b480854_15 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_dxq5d0019b480854_16 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_dxq5d0019b480854_17 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_dxq5d0019b480854_18 },
|
||||
+ {.delay = 100, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_dxq5d0019b480854_19 },
|
||||
+ {.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 4, .data = data_st7701_dxq5d0019b480854_20 },
|
||||
+ {.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 12, .data = data_st7701_dxq5d0019b480854_21 },
|
||||
+ {.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 14, .data = data_st7701_dxq5d0019b480854_22 },
|
||||
+ {.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 5, .data = data_st7701_dxq5d0019b480854_23 },
|
||||
+ {.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 3, .data = data_st7701_dxq5d0019b480854_24 },
|
||||
+ {.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 17, .data = data_st7701_dxq5d0019b480854_25 },
|
||||
+ {.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 5, .data = data_st7701_dxq5d0019b480854_26 },
|
||||
+ {.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 3, .data = data_st7701_dxq5d0019b480854_27 },
|
||||
+ {.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 17, .data = data_st7701_dxq5d0019b480854_28 },
|
||||
+ {.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 8, .data = data_st7701_dxq5d0019b480854_29 },
|
||||
+ {.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 3, .data = data_st7701_dxq5d0019b480854_30 },
|
||||
+ {.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 17, .data = data_st7701_dxq5d0019b480854_31 },
|
||||
+ {.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 6, .data = data_st7701_dxq5d0019b480854_32 },
|
||||
+ {.delay = 255, .data_type = TYPE1_DCS_SHORT_WRITE, .size = 1, .data = data_st7701_dxq5d0019b480854_33 },
|
||||
+/* bist mode vvv */
|
||||
+ //{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 6, .data = data_st7701_dxq5d0019b480854_34 },
|
||||
+ //{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 15, .data = data_st7701_dxq5d0019b480854_35 },
|
||||
+ //{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_dxq5d0019b480854_36 },
|
||||
+ //{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 6, .data = data_st7701_dxq5d0019b480854_37 },
|
||||
+ //{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 3, .data = data_st7701_dxq5d0019b480854_38 },
|
||||
+ //{.delay = 0, .data_type = TYPE3_DCS_LONG_WRITE, .size = 3, .data = data_st7701_dxq5d0019b480854_38 },
|
||||
+/* bist mode ^^^ */
|
||||
+ {.delay = 100, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_dxq5d0019b480854_39 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_dxq5d0019b480854_40 },
|
||||
+};
|
||||
+
|
||||
+#else
|
||||
+#error "MIPI_TX_PARAM multi-delcaration!!"
|
||||
+#endif
|
||||
diff --git a/include/cvitek/cvi_panels/dsi_st7701_hd228001c31.h b/include/cvitek/cvi_panels/dsi_st7701_hd228001c31.h
|
||||
new file mode 100644
|
||||
index 0000000000..cd70353db3
|
||||
--- /dev/null
|
||||
+++ b/include/cvitek/cvi_panels/dsi_st7701_hd228001c31.h
|
||||
@@ -0,0 +1,185 @@
|
||||
+#ifndef _MIPI_TX_PARAM_ST_7701_HD228001C31_H_
|
||||
+#define _MIPI_TX_PARAM_ST_7701_HD228001C31_H_
|
||||
+
|
||||
+#ifndef __UBOOT__
|
||||
+#include <linux/vo_mipi_tx.h>
|
||||
+#include <linux/cvi_comm_mipi_tx.h>
|
||||
+#else
|
||||
+#include <cvi_mipi.h>
|
||||
+#endif
|
||||
+
|
||||
+// vendor
|
||||
+/*
|
||||
+#define ST7701_HD228001C31_VACT 552
|
||||
+#define ST7701_HD228001C31_VSA 2
|
||||
+#define ST7701_HD228001C31_VBP 20
|
||||
+#define ST7701_HD228001C31_VFP 20
|
||||
+
|
||||
+#define ST7701_HD228001C31_HACT 368
|
||||
+#define ST7701_HD228001C31_HSA 8
|
||||
+#define ST7701_HD228001C31_HBP 160
|
||||
+#define ST7701_HD228001C31_HFP 160
|
||||
+*/
|
||||
+
|
||||
+// calc 2
|
||||
+#define ST7701_HD228001C31_VACT 552
|
||||
+#define ST7701_HD228001C31_VSA 10
|
||||
+#define ST7701_HD228001C31_VBP 20
|
||||
+#define ST7701_HD228001C31_VFP 20
|
||||
+
|
||||
+#define ST7701_HD228001C31_HACT 368
|
||||
+#define ST7701_HD228001C31_HSA 8
|
||||
+#define ST7701_HD228001C31_HBP 160
|
||||
+#define ST7701_HD228001C31_HFP 160
|
||||
+
|
||||
+
|
||||
+
|
||||
+
|
||||
+// calc
|
||||
+/*
|
||||
+#define ST7701_HD228001C31_VACT 552
|
||||
+#define ST7701_HD228001C31_VSA 10
|
||||
+#define ST7701_HD228001C31_VBP 6
|
||||
+#define ST7701_HD228001C31_VFP 3
|
||||
+
|
||||
+#define ST7701_HD228001C31_HACT 368
|
||||
+#define ST7701_HD228001C31_HSA 32
|
||||
+#define ST7701_HD228001C31_HBP 80
|
||||
+#define ST7701_HD228001C31_HFP 48
|
||||
+*/
|
||||
+
|
||||
+#define HD22_PIXEL_CLK(x) ((x##_VACT + x##_VSA + x##_VBP + x##_VFP) \
|
||||
+ * (x##_HACT + x##_HSA + x##_HBP + x##_HFP) * 75 / 1000)
|
||||
+
|
||||
+struct combo_dev_cfg_s dev_cfg_st7701_368x552 = {
|
||||
+ .devno = 0,
|
||||
+ .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_CLK, MIPI_TX_LANE_1, -1, -1},
|
||||
+ .lane_pn_swap = {false, false, false, false, false},
|
||||
+ .output_mode = OUTPUT_MODE_DSI_VIDEO,
|
||||
+ .video_mode = BURST_MODE,
|
||||
+ .output_format = OUT_FORMAT_RGB_24_BIT,
|
||||
+ .sync_info = {
|
||||
+ .vid_hsa_pixels = ST7701_HD228001C31_HSA,
|
||||
+ .vid_hbp_pixels = ST7701_HD228001C31_HBP,
|
||||
+ .vid_hfp_pixels = ST7701_HD228001C31_HFP,
|
||||
+ .vid_hline_pixels = ST7701_HD228001C31_HACT,
|
||||
+ .vid_vsa_lines = ST7701_HD228001C31_VSA,
|
||||
+ .vid_vbp_lines = ST7701_HD228001C31_VBP,
|
||||
+ .vid_vfp_lines = ST7701_HD228001C31_VFP,
|
||||
+ .vid_active_lines = ST7701_HD228001C31_VACT,
|
||||
+ .vid_vsa_pos_polarity = true,
|
||||
+ .vid_hsa_pos_polarity = false,
|
||||
+ },
|
||||
+ .pixel_clk = HD22_PIXEL_CLK(ST7701_HD228001C31),
|
||||
+};
|
||||
+
|
||||
+const struct hs_settle_s hs_timing_cfg_st7701_368x552 = { .prepare = 6, .zero = 32, .trail = 1 };
|
||||
+
|
||||
+#ifndef CVI_U8
|
||||
+#define CVI_U8 unsigned char
|
||||
+#endif
|
||||
+
|
||||
+static CVI_U8 data_st7701_hd228001c31_1[] = { 0xff, 0x77,0x01,0x00,0x00,0x13 }; // 6
|
||||
+static CVI_U8 data_st7701_hd228001c31_2[] = { 0xef, 0x08 }; // 2
|
||||
+static CVI_U8 data_st7701_hd228001c31_3[] = { 0xff, 0x77,0x01,0x00,0x00,0x10 }; // 6
|
||||
+static CVI_U8 data_st7701_hd228001c31_4[] = { 0xc0, 0x44, 0x00 }; // 3
|
||||
+static CVI_U8 data_st7701_hd228001c31_5[] = { 0xc1, 0x0b, 0x02 }; // 3
|
||||
+static CVI_U8 data_st7701_hd228001c31_6[] = { 0xc2, 0x07, 0x1f }; // 3
|
||||
+static CVI_U8 data_st7701_hd228001c31_7[] = { 0xcc, 0x10 }; // 2
|
||||
+static CVI_U8 data_st7701_hd228001c31_8[] = { 0xb0, 0x0F,0x1E,0x25,0x0D,0x11,0x06,0x12,0x08,0x08,0x2A,0x05,0x12,0x10,0x2B,0x32,0x1F }; // 17
|
||||
+static CVI_U8 data_st7701_hd228001c31_9[] = { 0xb1, 0x0F,0x1E,0x25,0x0D,0x11,0x05,0x12,0x08,0x08,0x2B,0x05,0x12,0x10,0x2B,0x32,0x1F }; // 17
|
||||
+static CVI_U8 data_st7701_hd228001c31_10[] = { 0xff, 0x77,0x01,0x00,0x00,0x11 }; // 6
|
||||
+static CVI_U8 data_st7701_hd228001c31_11[] = { 0xb0, 0x35 }; // 2
|
||||
+static CVI_U8 data_st7701_hd228001c31_12[] = { 0xb1, 0x45 }; // 2
|
||||
+static CVI_U8 data_st7701_hd228001c31_13[] = { 0xb2, 0x87 }; // 2
|
||||
+static CVI_U8 data_st7701_hd228001c31_14[] = { 0xb3, 0x80 }; // 2
|
||||
+static CVI_U8 data_st7701_hd228001c31_15[] = { 0xb5, 0x80 }; // 2
|
||||
+static CVI_U8 data_st7701_hd228001c31_16[] = { 0xb7, 0x85 }; // 2
|
||||
+static CVI_U8 data_st7701_hd228001c31_17[] = { 0xb8, 0x11 }; // 2
|
||||
+static CVI_U8 data_st7701_hd228001c31_18[] = { 0xbb, 0x03 }; // 2
|
||||
+static CVI_U8 data_st7701_hd228001c31_19[] = { 0xc0, 0x07 }; // 2
|
||||
+static CVI_U8 data_st7701_hd228001c31_20[] = { 0xc1, 0x78 }; // 2
|
||||
+static CVI_U8 data_st7701_hd228001c31_21[] = { 0xc2, 0x78 }; // 2
|
||||
+static CVI_U8 data_st7701_hd228001c31_22[] = { 0xd0, 0x88 }; // 2
|
||||
+// 23 delay 100 ms
|
||||
+static CVI_U8 data_st7701_hd228001c31_24[] = { 0xe0, 0x00, 0x00, 0x02}; // 4
|
||||
+static CVI_U8 data_st7701_hd228001c31_25[] = { 0xe1, 0x03,0x30,0x07,0x30,0x02,0x30,0x06,0x30,0x00,0x44,0x44 }; //12
|
||||
+static CVI_U8 data_st7701_hd228001c31_26[] = { 0xe2, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }; //12
|
||||
+static CVI_U8 data_st7701_hd228001c31_27[] = { 0xe3, 0x00,0x00,0x22,0x00 }; // 5
|
||||
+static CVI_U8 data_st7701_hd228001c31_28[] = { 0xe4, 0x22, 0x00 }; // 3
|
||||
+static CVI_U8 data_st7701_hd228001c31_29[] = { 0xe5, 0x0A,0x34,0x30,0xE0,0x08,0x32,0x30,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }; // 17
|
||||
+static CVI_U8 data_st7701_hd228001c31_30[] = { 0xe6, 0x00, 0x00, 0x22, 0x00 }; // 5
|
||||
+static CVI_U8 data_st7701_hd228001c31_31[] = { 0xe7, 0x22, 0x00 }; // 3
|
||||
+static CVI_U8 data_st7701_hd228001c31_32[] = { 0xe8, 0x09,0x33,0x30,0xE0,0x07,0x31,0x30,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }; // 17
|
||||
+static CVI_U8 data_st7701_hd228001c31_33[] = { 0xeb, 0x00,0x01,0x10,0x10,0x11,0x00,0x00 }; // 8
|
||||
+static CVI_U8 data_st7701_hd228001c31_34[] = { 0xed, 0xFF,0xFF,0xF0,0x45,0xBA,0x2F,0xFF,0xFF,0xFF,0xFF,0xF2,0xAB,0x54,0x0F,0xFF,0xFF }; // 17
|
||||
+static CVI_U8 data_st7701_hd228001c31_35[] = { 0xef, 0x08,0x08,0x08,0x45,0x3F,0x54 }; // 7
|
||||
+static CVI_U8 data_st7701_hd228001c31_36[] = { 0xff, 0x77,0x01,0x00,0x00,0x13 }; // 6
|
||||
+static CVI_U8 data_st7701_hd228001c31_37[] = { 0xe8, 0x00, 0x0e }; // 3
|
||||
+static CVI_U8 data_st7701_hd228001c31_38[] = { 0x11 }; // 1
|
||||
+// 39 delay 120 ms
|
||||
+static CVI_U8 data_st7701_hd228001c31_40[] = { 0xe8, 0x00, 0x0c }; // 3
|
||||
+// 41 delay 10 ms
|
||||
+static CVI_U8 data_st7701_hd228001c31_42[] = { 0xe8, 0x00, 0x00 }; // 3
|
||||
+static CVI_U8 data_st7701_hd228001c31_43[] = { 0xff, 0x77,0x01,0x00,0x00,0x00 }; // 6
|
||||
+static CVI_U8 data_st7701_hd228001c31_44[] = { 0x29 }; // 1
|
||||
+// 45 delay 50 ms
|
||||
+
|
||||
+
|
||||
+// len == 1 , type 0x05
|
||||
+// len == 2 , type 0x15 or type 23
|
||||
+// len >= 3 , type 0x29 or type 0x39
|
||||
+#define TYPE1_DCS_SHORT_WRITE 0x05
|
||||
+#define TYPE2_DCS_SHORT_WRITE 0x15
|
||||
+#define TYPE3_DCS_LONG_WRITE 0x39
|
||||
+#define TYPE3_GENERIC_LONG_WRITE 0x29
|
||||
+const struct dsc_instr dsi_init_cmds_st7701_368x552[] = {
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 6, .data = data_st7701_hd228001c31_1 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_2 },
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 6, .data = data_st7701_hd228001c31_3 },
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 3, .data = data_st7701_hd228001c31_4 },
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 3, .data = data_st7701_hd228001c31_5 },
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 3, .data = data_st7701_hd228001c31_6 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_7 },
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 17, .data = data_st7701_hd228001c31_8 },
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 17, .data = data_st7701_hd228001c31_9 },
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 6, .data = data_st7701_hd228001c31_10 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_11 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_12 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_13 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_14 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_15 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_16 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_17 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_18 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_19 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_20 },
|
||||
+ {.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_21 },
|
||||
+ {.delay = 100, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_22 },
|
||||
+ // 23 is delay 100ms
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 4, .data = data_st7701_hd228001c31_24 },
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 12, .data = data_st7701_hd228001c31_25 },
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 12, .data = data_st7701_hd228001c31_26 },
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 5, .data = data_st7701_hd228001c31_27 },
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 3, .data = data_st7701_hd228001c31_28 },
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 17, .data = data_st7701_hd228001c31_29 },
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 5, .data = data_st7701_hd228001c31_30 },
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 3, .data = data_st7701_hd228001c31_31 },
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 17, .data = data_st7701_hd228001c31_32 },
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 8, .data = data_st7701_hd228001c31_33 },
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 17, .data = data_st7701_hd228001c31_34 },
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 7, .data = data_st7701_hd228001c31_35 },
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 6, .data = data_st7701_hd228001c31_36 },
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 3, .data = data_st7701_hd228001c31_37 },
|
||||
+ {.delay = 120, .data_type = TYPE1_DCS_SHORT_WRITE, .size = 1, .data = data_st7701_hd228001c31_38 },
|
||||
+ // 39 is delay 120ms
|
||||
+ {.delay = 10, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 3, .data = data_st7701_hd228001c31_40 },
|
||||
+ // 41 is delay 10ms
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 3, .data = data_st7701_hd228001c31_42 },
|
||||
+ {.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 6, .data = data_st7701_hd228001c31_43 },
|
||||
+ {.delay = 50, .data_type = TYPE1_DCS_SHORT_WRITE, .size = 1, .data = data_st7701_hd228001c31_44 },
|
||||
+};
|
||||
+
|
||||
+#else
|
||||
+#error "MIPI_TX_PARAM multi-delcaration!!"
|
||||
+#endif // _MIPI_TX_PARAM_ST_7701_HD22801C31_H_
|
||||
diff --git a/include/cvitek/cvi_panels/dsi_st7701_hd228001c31_alt0.h b/include/cvitek/cvi_panels/dsi_st7701_hd228001c31_alt0.h
|
||||
new file mode 100644
|
||||
index 0000000000..2d6dd875ec
|
||||
--- /dev/null
|
||||
+++ b/include/cvitek/cvi_panels/dsi_st7701_hd228001c31_alt0.h
|
||||
@@ -0,0 +1,224 @@
|
||||
+#ifndef _MIPI_TX_PARAM_ST_7701_HD228001C31_ALT0_H_
|
||||
+#define _MIPI_TX_PARAM_ST_7701_HD228001C31_ALT0_H_
|
||||
+
|
||||
+#ifndef __UBOOT__
|
||||
+#include <linux/vo_mipi_tx.h>
|
||||
+#include <linux/cvi_comm_mipi_tx.h>
|
||||
+#else
|
||||
+#include <cvi_mipi.h>
|
||||
+#endif
|
||||
+
|
||||
+// vendor
|
||||
+#define ST7701_HD228001C31_ALT0_VACT 552
|
||||
+#define ST7701_HD228001C31_ALT0_VSA 2
|
||||
+#define ST7701_HD228001C31_ALT0_VBP 20
|
||||
+#define ST7701_HD228001C31_ALT0_VFP 20
|
||||
+
|
||||
+#define ST7701_HD228001C31_ALT0_HACT 368
|
||||
+#define ST7701_HD228001C31_ALT0_HSA 8
|
||||
+#define ST7701_HD228001C31_ALT0_HBP 160
|
||||
+#define ST7701_HD228001C31_ALT0_HFP 160
|
||||
+
|
||||
+
|
||||
+// calc
|
||||
+/*
|
||||
+#define ST7701_HD228001C31_ALT0_VACT 552
|
||||
+#define ST7701_HD228001C31_ALT0_VSA 10
|
||||
+#define ST7701_HD228001C31_ALT0_VBP 6
|
||||
+#define ST7701_HD228001C31_ALT0_VFP 3
|
||||
+
|
||||
+#define ST7701_HD228001C31_ALT0_HACT 368
|
||||
+#define ST7701_HD228001C31_ALT0_HSA 32
|
||||
+#define ST7701_HD228001C31_ALT0_HBP 80
|
||||
+#define ST7701_HD228001C31_ALT0_HFP 48
|
||||
+*/
|
||||
+
|
||||
+#define HD22_ALT0_PIXEL_CLK(x) ((x##_VACT + x##_VSA + x##_VBP + x##_VFP) \
|
||||
+ * (x##_HACT + x##_HSA + x##_HBP + x##_HFP) * 75 / 1000)
|
||||
+
|
||||
+struct combo_dev_cfg_s dev_cfg_st7701_368x552_alt0 = {
|
||||
+ .devno = 0,
|
||||
+ .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_CLK, MIPI_TX_LANE_1, -1, -1},
|
||||
+ .lane_pn_swap = {false, false, false, false, false},
|
||||
+ .output_mode = OUTPUT_MODE_DSI_VIDEO,
|
||||
+ .video_mode = BURST_MODE,
|
||||
+ .output_format = OUT_FORMAT_RGB_24_BIT,
|
||||
+ .sync_info = {
|
||||
+ .vid_hsa_pixels = ST7701_HD228001C31_ALT0_HSA,
|
||||
+ .vid_hbp_pixels = ST7701_HD228001C31_ALT0_HBP,
|
||||
+ .vid_hfp_pixels = ST7701_HD228001C31_ALT0_HFP,
|
||||
+ .vid_hline_pixels = ST7701_HD228001C31_ALT0_HACT,
|
||||
+ .vid_vsa_lines = ST7701_HD228001C31_ALT0_VSA,
|
||||
+ .vid_vbp_lines = ST7701_HD228001C31_ALT0_VBP,
|
||||
+ .vid_vfp_lines = ST7701_HD228001C31_ALT0_VFP,
|
||||
+ .vid_active_lines = ST7701_HD228001C31_ALT0_VACT,
|
||||
+ .vid_vsa_pos_polarity = true,
|
||||
+ .vid_hsa_pos_polarity = false,
|
||||
+ },
|
||||
+ .pixel_clk = HD22_ALT0_PIXEL_CLK(ST7701_HD228001C31_ALT0),
|
||||
+};
|
||||
+
|
||||
+const struct hs_settle_s hs_timing_cfg_st7701_368x552_alt0 = { .prepare = 6, .zero = 32, .trail = 1 };
|
||||
+
|
||||
+#ifndef CVI_U8
|
||||
+#define CVI_U8 unsigned char
|
||||
+#endif
|
||||
+
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_0[] = { 0x11 }; // 1
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_1[] = { 0xff, 0x77, 0x01, 0x00, 0x00, 0x13 }; // 6
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_2[] = { 0xef, 0x08 }; // 2
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_3[] = { 0xff, 0x77, 0x01, 0x00, 0x00, 0x10 }; // 6
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_4[] = { 0xc0, 0x44, 0x00 }; // 3
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_5[] = { 0xc1, 0x14, 0x06 }; // 3
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_6[] = { 0xc2, 0x07, 0x1f }; // 3
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_7[] = { 0xcc, 0x30 }; // 2
|
||||
+
|
||||
+
|
||||
+// gamma setting
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_8[] = { 0xb0, 0x0f, 0x16, 0x1a, 0x07, 0x0d, 0x05, 0x02, 0x09,
|
||||
+ 0x08, 0x1f, 0x05, 0x13, 0x10, 0x2b, 0x33, 0x1f }; // 17
|
||||
+
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_9[] = { 0xb1, 0x0f, 0x12, 0x17, 0x0e ,0x0e ,0x04, 0x00, 0x06,
|
||||
+ 0x06, 0x1d, 0x05, 0x13, 0x11, 0x26, 0x2d, 0x1f }; // 17
|
||||
+
|
||||
+
|
||||
+// power control
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_10[] = { 0xff, 0x77, 0x01, 0x00, 0x00, 0x11 }; // 6
|
||||
+
|
||||
+// vcom setting
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_11[] = { 0xb1, 0x7c }; // 2
|
||||
+// vcom setting end
|
||||
+
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_12[] = { 0xb2, 0x87 }; // 2
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_13[] = { 0xb3, 0x80 }; // 2
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_14[] = { 0xb5, 0x49 }; // 2
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_15[] = { 0xb7, 0x85 }; // 2
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_16[] = { 0xb8, 0x20 }; // 2
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_17[] = { 0xc0, 0x07 }; // 2
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_18[] = { 0xc1, 0x08 }; // 2
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_19[] = { 0xc2, 0x08 }; // 2
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_20[] = { 0xd0, 0x88 }; // 2
|
||||
+// power control end
|
||||
+
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_21[] = { 0xB1, 0x0F, 0x12, 0x17, 0x0E, 0x0E, 0x04,
|
||||
+ 0x00, 0x06, 0x06, 0x1D, 0x05, 0x13, 0x11, 0x26, 0x2D, 0x1F}; // 17
|
||||
+
|
||||
+
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_22[] = { 0xB5, 0x49 };
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_23[] = { 0xB7, 0x85 };
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_24[] = { 0xB8, 0x20 };
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_25[] = { 0xC0, 0x07 };
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_26[] = { 0xC1, 0x08 };
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_27[] = { 0xC2, 0x08 };
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_28[] = { 0xD0, 0x88 };
|
||||
+
|
||||
+
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_29[] = { 0xe0, 0x00, 0x02 };
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_30[] = { 0xE1, 0x0A, 0xA0, 0x0C, 0xA0, 0x09, 0xA0, 0x0B,
|
||||
+ 0xA0, 0x00, 0x44, 0x44 }; // 12
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_31[] = { 0xE2, 0x00, 0x00, 0x44, 0x44, 0x05, 0xA0, 0x00,
|
||||
+ 0x00, 0x05, 0xA0, 0x00, 0x00 }; // 13
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_32[] = { 0xE3, 0x00, 0x00, 0x22, 0x22 }; // 5
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_33[] = { 0xe4, 0x44, 0x44 }; // 3
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_34[] = { 0xE5, 0x11, 0x3D, 0x0A, 0xC0, 0x13, 0x3F, 0x0A,
|
||||
+ 0xC0, 0x0D, 0x39, 0x0A, 0xC0, 0x0F, 0x3B, 0x0A, 0xC0 }; // 17
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_35[] = { 0xE6, 0x00, 0x00, 0x22, 0x22 }; // 5
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_36[] = { 0xE7, 0x44, 0x44 }; // 3
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_37[] = { 0xE8, 0x10, 0x3C, 0x0A, 0xC0, 0x12, 0x3E, 0x0A,
|
||||
+ 0xC0, 0x0C, 0x38, 0x0A, 0xC0, 0x0E, 0x3A, 0x0A, 0xC0 }; // 17
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_38[] = { 0xEB, 0x00, 0x01, 0xE4, 0xE4, 0x44, 0x88, 0x40 }; // 8
|
||||
+
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_39[] = { 0xED, 0x55, 0x44, 0x77, 0x66, 0xF0, 0xFC, 0x1A,
|
||||
+ 0x2B, 0xB2, 0xA1, 0xCF, 0x0F, 0x66, 0x77, 0x44, 0x55 }; //17
|
||||
+
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_40[] = { 0xEF, 0x10, 0x0D, 0x04, 0x08, 0x3F, 0x1F }; // 7
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_41[] = { 0xFF, 0x77, 0x01, 0x00, 0x00, 0x13 }; // 6
|
||||
+
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_42[] = { 0xE8, 0x00, 0x0E }; // 3
|
||||
+
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_43[] = { 0x11 }; // 1
|
||||
+//delay 120 ms
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_44[] = { 0xE8, 0x00, 0x0c }; // 3
|
||||
+//delay 10 ms
|
||||
+
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_45[] = { 0xE8, 0x00, 0x00 }; // 3
|
||||
+
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_46[] = { 0xff, 0x77, 0x01, 0x00, 0x00, 0x00}; // 6
|
||||
+
|
||||
+static CVI_U8 data_st7701_hd228001c31_alt0_47[] = { 0x29 }; // 1
|
||||
+//delay 50 ms
|
||||
+
|
||||
+
|
||||
+// len == 1 , type 0x05
|
||||
+// len == 2 , type 0x15 or type 23
|
||||
+// len >= 3 , type 0x29 or type 0x39
|
||||
+#define TYPE1_DCS_SHORT_WRITE 0x05
|
||||
+#define TYPE2_DCS_SHORT_WRITE 0x15
|
||||
+#define TYPE3_DCS_LONG_WRITE 0x39
|
||||
+#define TYPE3_GENERIC_LONG_WRITE 0x29
|
||||
+const struct dsc_instr dsi_init_cmds_st7701_368x552_alt0[] = {
|
||||
+{.delay = 0, .data_type = TYPE1_DCS_SHORT_WRITE, .size = 1, .data = data_st7701_hd228001c31_alt0_0 },
|
||||
+{.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 6, .data = data_st7701_hd228001c31_alt0_1 },
|
||||
+{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_alt0_2 },
|
||||
+{.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 6, .data = data_st7701_hd228001c31_alt0_3 },
|
||||
+{.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 3, .data = data_st7701_hd228001c31_alt0_4 },
|
||||
+{.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 3, .data = data_st7701_hd228001c31_alt0_5 },
|
||||
+{.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 3, .data = data_st7701_hd228001c31_alt0_6 },
|
||||
+{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_alt0_7 },
|
||||
+
|
||||
+
|
||||
+// gamma cluster setting
|
||||
+{.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 17, .data = data_st7701_hd228001c31_alt0_8 },
|
||||
+{.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 17, .data = data_st7701_hd228001c31_alt0_9 },
|
||||
+
|
||||
+// power control
|
||||
+{.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 6, .data = data_st7701_hd228001c31_alt0_10 },
|
||||
+// vcom setting
|
||||
+{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_alt0_11 },
|
||||
+// vcom setting end
|
||||
+
|
||||
+{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_alt0_11 },
|
||||
+{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_alt0_12 },
|
||||
+{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_alt0_13 },
|
||||
+{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_alt0_14 },
|
||||
+{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_alt0_15 },
|
||||
+{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_alt0_16 },
|
||||
+{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_alt0_17 },
|
||||
+{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_alt0_18 },
|
||||
+{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_alt0_19 },
|
||||
+{.delay = 100, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_alt0_20 },
|
||||
+// power control end
|
||||
+
|
||||
+{.delay = 100, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 17, .data = data_st7701_hd228001c31_alt0_21 },
|
||||
+{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_alt0_22 },
|
||||
+{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_alt0_23 },
|
||||
+{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_alt0_24 },
|
||||
+{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_alt0_25 },
|
||||
+{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_alt0_26 },
|
||||
+{.delay = 0, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_alt0_27 },
|
||||
+{.delay = 100, .data_type = TYPE2_DCS_SHORT_WRITE, .size = 2, .data = data_st7701_hd228001c31_alt0_28 },
|
||||
+
|
||||
+{.delay = 100, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 4, .data = data_st7701_hd228001c31_alt0_29 },
|
||||
+{.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 12, .data = data_st7701_hd228001c31_alt0_30 },
|
||||
+{.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 13, .data = data_st7701_hd228001c31_alt0_31 },
|
||||
+{.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 5, .data = data_st7701_hd228001c31_alt0_32 },
|
||||
+{.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 3, .data = data_st7701_hd228001c31_alt0_33 },
|
||||
+{.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 17, .data = data_st7701_hd228001c31_alt0_34 },
|
||||
+{.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 5, .data = data_st7701_hd228001c31_alt0_35 },
|
||||
+{.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 6, .data = data_st7701_hd228001c31_alt0_36 },
|
||||
+{.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 17, .data = data_st7701_hd228001c31_alt0_37 },
|
||||
+{.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 8, .data = data_st7701_hd228001c31_alt0_38 },
|
||||
+{.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 17, .data = data_st7701_hd228001c31_alt0_39 },
|
||||
+{.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 7, .data = data_st7701_hd228001c31_alt0_40 },
|
||||
+{.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 6, .data = data_st7701_hd228001c31_alt0_41 },
|
||||
+{.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 3, .data = data_st7701_hd228001c31_alt0_42 },
|
||||
+{.delay = 120, .data_type = TYPE1_DCS_SHORT_WRITE, .size = 1, .data = data_st7701_hd228001c31_alt0_43 },
|
||||
+{.delay = 120, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 3, .data = data_st7701_hd228001c31_alt0_44 },
|
||||
+{.delay = 10, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 3, .data = data_st7701_hd228001c31_alt0_45 },
|
||||
+{.delay = 0, .data_type = TYPE3_GENERIC_LONG_WRITE, .size = 6, .data = data_st7701_hd228001c31_alt0_46 },
|
||||
+{.delay = 50, .data_type = TYPE1_DCS_SHORT_WRITE, .size = 1, .data = data_st7701_hd228001c31_alt0_47 },
|
||||
+};
|
||||
+
|
||||
+#else
|
||||
+#error "MIPI_TX_PARAM multi-delcaration!!"
|
||||
+#endif // _MIPI_TX_PARAM_ST_7701_HD22801C31_H_
|
||||
diff --git a/include/cvitek/cvi_panels/dsi_zct2133v1.h b/include/cvitek/cvi_panels/dsi_zct2133v1.h
|
||||
new file mode 100644
|
||||
index 0000000000..56549dde6a
|
||||
--- /dev/null
|
||||
+++ b/include/cvitek/cvi_panels/dsi_zct2133v1.h
|
||||
@@ -0,0 +1,77 @@
|
||||
+#ifndef _MIPI_TX_PARAM_ZCT2133V1_H_
|
||||
+#define _MIPI_TX_PARAM_ZCT2133V1_H_
|
||||
+
|
||||
+#ifndef __UBOOT__
|
||||
+#include <linux/vo_mipi_tx.h>
|
||||
+#include <linux/cvi_comm_mipi_tx.h>
|
||||
+#else
|
||||
+#include <cvi_mipi.h>
|
||||
+#endif
|
||||
+
|
||||
+#define ZCT2133V1_VACT 1280
|
||||
+#define ZCT2133V1_VSA 10
|
||||
+#define ZCT2133V1_VBP 34
|
||||
+#define ZCT2133V1_VFP 3
|
||||
+
|
||||
+#define ZCT2133V1_HACT 800
|
||||
+#define ZCT2133V1_HSA 80
|
||||
+#define ZCT2133V1_HBP 136
|
||||
+#define ZCT2133V1_HFP 56
|
||||
+
|
||||
+#define ZCT_PIXEL_CLK(x) ((x##_VACT + x##_VSA + x##_VBP + x##_VFP) \
|
||||
+ * (x##_HACT + x##_HSA + x##_HBP + x##_HFP) * 60 / 1000)
|
||||
+
|
||||
+struct combo_dev_cfg_s dev_cfg_zct2133v1_800x1280 = {
|
||||
+ .devno = 0,
|
||||
+ .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_CLK, MIPI_TX_LANE_1, -1, -1},
|
||||
+ .lane_pn_swap = {false, false, false, false, false},
|
||||
+ .output_mode = OUTPUT_MODE_DSI_VIDEO,
|
||||
+ .video_mode = BURST_MODE,
|
||||
+ .output_format = OUT_FORMAT_RGB_24_BIT,
|
||||
+ .sync_info = {
|
||||
+ .vid_hsa_pixels = ZCT2133V1_HSA,
|
||||
+ .vid_hbp_pixels = ZCT2133V1_HBP,
|
||||
+ .vid_hfp_pixels = ZCT2133V1_HFP,
|
||||
+ .vid_hline_pixels = ZCT2133V1_HACT,
|
||||
+ .vid_vsa_lines = ZCT2133V1_VSA,
|
||||
+ .vid_vbp_lines = ZCT2133V1_VBP,
|
||||
+ .vid_vfp_lines = ZCT2133V1_VFP,
|
||||
+ .vid_active_lines = ZCT2133V1_VACT,
|
||||
+ .vid_vsa_pos_polarity = true,
|
||||
+ .vid_hsa_pos_polarity = false,
|
||||
+ },
|
||||
+ .pixel_clk = ZCT_PIXEL_CLK(ZCT2133V1),
|
||||
+};
|
||||
+
|
||||
+const struct hs_settle_s hs_timing_cfg_zct2133v1_800x1280 = { .prepare = 6, .zero = 32, .trail = 1 };
|
||||
+
|
||||
+#ifndef CVI_U8
|
||||
+#define CVI_U8 unsigned char
|
||||
+#endif
|
||||
+
|
||||
+static CVI_U8 data_zct2133v1_0[] = { 0xE1, 0x93 };
|
||||
+static CVI_U8 data_zct2133v1_1[] = { 0xE2, 0x65 };
|
||||
+static CVI_U8 data_zct2133v1_2[] = { 0xE3, 0xF8 };
|
||||
+static CVI_U8 data_zct2133v1_3[] = { 0x80, 0x01 };
|
||||
+static CVI_U8 data_zct2133v1_4[] = { 0x11 };
|
||||
+static CVI_U8 data_zct2133v1_5[] = { 0x29 };
|
||||
+
|
||||
+// len == 1 , type 0x05
|
||||
+// len == 2 , type 0x15 or type 23
|
||||
+// len >= 3 , type 0x29 or type 0x39
|
||||
+#define TYPE1 0x05
|
||||
+#define TYPE2 0x15
|
||||
+#define TYPE3 0x29
|
||||
+
|
||||
+const struct dsc_instr dsi_init_cmds_zct2133v1_800x1280[] = {
|
||||
+ {.delay = 0, .data_type = TYPE2, .size = 2, .data = data_zct2133v1_0 },
|
||||
+ {.delay = 0, .data_type = TYPE2, .size = 2, .data = data_zct2133v1_1 },
|
||||
+ {.delay = 0, .data_type = TYPE2, .size = 2, .data = data_zct2133v1_2 },
|
||||
+ {.delay = 0, .data_type = TYPE2, .size = 2, .data = data_zct2133v1_3 },
|
||||
+ {.delay = 0, .data_type = TYPE1, .size = 1, .data = data_zct2133v1_4 },
|
||||
+ {.delay = 0, .data_type = TYPE1, .size = 1, .data = data_zct2133v1_5 },
|
||||
+};
|
||||
+
|
||||
+#else
|
||||
+#error "MIPI_TX_PARAM multi-delcaration!!"
|
||||
+#endif // _MIPI_TX_PARAM_ZCT2133V1_H_
|
||||
--
|
||||
2.44.0
|
||||
|
||||
10988
board/sipeed/licheervnano/patches/uboot/0003-add-jpeg-driver.patch
Normal file
10988
board/sipeed/licheervnano/patches/uboot/0003-add-jpeg-driver.patch
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,69 @@
|
|||
From 59992a8a4466a67c1a20779b5b411626397b51e9 Mon Sep 17 00:00:00 2001
|
||||
From: Justin Hammond <justin@dynam.ac>
|
||||
Date: Thu, 7 Mar 2024 12:43:40 +0800
|
||||
Subject: [PATCH] add cvi_jpeg command
|
||||
|
||||
---
|
||||
cmd/cvi_jpeg.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 50 insertions(+)
|
||||
create mode 100644 cvi_jpeg.c
|
||||
|
||||
diff --git a/cmd/cvi_jpeg.c b/cmd/cvi_jpeg.c
|
||||
new file mode 100644
|
||||
index 0000000000..6cfe1b98a7
|
||||
--- /dev/null
|
||||
+++ b/cmd/cvi_jpeg.c
|
||||
@@ -0,0 +1,50 @@
|
||||
+#include <stdlib.h>
|
||||
+#include <common.h>
|
||||
+#include <command.h>
|
||||
+
|
||||
+extern int jpeg_decoder(void *bs_addr, void *yuv_addr, int size);
|
||||
+extern int get_jpeg_size(int *width_addr, int *height_addr);
|
||||
+
|
||||
+static int do_cvi_jpeg_dec(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
|
||||
+{
|
||||
+ char *bs_addr = NULL;
|
||||
+ char *yuv_addr = NULL;
|
||||
+ int size = 0;
|
||||
+
|
||||
+
|
||||
+ if (argc != 4) {
|
||||
+ printf("Usage:\n%s\n", cmdtp->usage);
|
||||
+ return 1;
|
||||
+ }
|
||||
+
|
||||
+ bs_addr = (char *)simple_strtol(argv[1], NULL, 16);
|
||||
+
|
||||
+ if (!bs_addr) {
|
||||
+ printf("Usage:\n%s\n", cmdtp->usage);
|
||||
+ return 1;
|
||||
+ }
|
||||
+
|
||||
+ yuv_addr = (char *)simple_strtol(argv[2], NULL, 16);
|
||||
+
|
||||
+ if (!yuv_addr) {
|
||||
+ printf("Usage:\n%s\n", cmdtp->usage);
|
||||
+ return 1;
|
||||
+ }
|
||||
+
|
||||
+ size = (int)simple_strtol(argv[3], NULL, 16);
|
||||
+
|
||||
+ if (!size) {
|
||||
+ printf("Usage:\n%s\n", cmdtp->usage);
|
||||
+ return 1;
|
||||
+ }
|
||||
+
|
||||
+ printf("\nstart jpeg dec task!, bs_addr %p, yuv_addr %p, size %d\n", bs_addr, yuv_addr, size);
|
||||
+
|
||||
+ jpeg_decoder(bs_addr, yuv_addr, size);
|
||||
+ get_jpeg_size((int *)(bs_addr + size - 8), (int *)(bs_addr + size - 4));
|
||||
+
|
||||
+ return CMD_RET_SUCCESS;
|
||||
+}
|
||||
+
|
||||
+U_BOOT_CMD(cvi_jpeg_dec, 4, 0, do_cvi_jpeg_dec, "Jpeg decoder ", "\n"
|
||||
+);
|
||||
--
|
||||
2.44.0
|
||||
|
||||
9
board/sipeed/licheervnano/postinstall.sh
Executable file
9
board/sipeed/licheervnano/postinstall.sh
Executable file
|
|
@ -0,0 +1,9 @@
|
|||
#!/bin/sh
|
||||
echo "Creating Filesystem Image"
|
||||
cd $BINARIES_DIR
|
||||
rm sdcard.img
|
||||
cp $BR2_EXTERNAL_LICHEERVNANO_BR_PATH/board/sipeed/licheervnano/fit-image.its $BINARIES_DIR/fit-image.its
|
||||
$BINARIES_DIR/../host/bin/mkimage -f fit-image.its $BINARIES_DIR/boot.sd
|
||||
echo "Creating Filesystem Image"
|
||||
$BASE_DIR/../support/scripts/genimage.sh -c $BR2_EXTERNAL_LICHEERVNANO_BR_PATH/board/sipeed/licheervnano/genimage.cfg
|
||||
echo "Completed - Images are at $BINARIES_DIR"
|
||||
2
board/sipeed/licheervnano/preimage.sh
Executable file
2
board/sipeed/licheervnano/preimage.sh
Executable file
|
|
@ -0,0 +1,2 @@
|
|||
#!/bin/sh
|
||||
chmod -x $1/etc/init.d/S50postgresql
|
||||
11
board/sipeed/licheervnano/rootfs-overlay/etc/fstab
Normal file
11
board/sipeed/licheervnano/rootfs-overlay/etc/fstab
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
# <file system> <mount pt> <type> <options> <dump> <pass>
|
||||
/dev/root / ext4 rw,noauto 0 1
|
||||
proc /proc proc defaults 0 0
|
||||
devpts /dev/pts devpts defaults,gid=5,mode=620,ptmxmode=0666 0 0
|
||||
tmpfs /dev/shm tmpfs mode=0777 0 0
|
||||
tmpfs /tmp tmpfs mode=1777 0 0
|
||||
tmpfs /run tmpfs mode=0755,nosuid,nodev 0 0
|
||||
sysfs /sys sysfs defaults 0 0
|
||||
/dev/mmcblk0p1 /boot vfat defaults 0 0
|
||||
debugfs /sys/kernel/debug debugfs defaults 0 0
|
||||
|
||||
44
board/sipeed/licheervnano/rootfs-overlay/etc/init.d/S01growfs
Executable file
44
board/sipeed/licheervnano/rootfs-overlay/etc/init.d/S01growfs
Executable file
|
|
@ -0,0 +1,44 @@
|
|||
#!/bin/sh
|
||||
|
||||
|
||||
start() {
|
||||
if [ -f "/.growfsran" ]; then
|
||||
echo "Root Partition Already resized"
|
||||
return 1
|
||||
fi
|
||||
echo 'Resizing Rootfs'
|
||||
growpart /dev/mmcblk0 2
|
||||
status=$?
|
||||
if [ "$status" -eq 0 ]; then
|
||||
echo "Partition Resized"
|
||||
else
|
||||
echo "Partit Resize Failed"
|
||||
return "$status"
|
||||
fi
|
||||
resize2fs /dev/mmcblk0p2
|
||||
status=$?
|
||||
if [ "$status" -eq 0 ]; then
|
||||
echo "Rootfs Resized"
|
||||
else
|
||||
echo "rootfs Resize Failed"
|
||||
fi
|
||||
#echo "Running mkswap"
|
||||
#mkswap /dev/mmcblk0p1
|
||||
#status=$?
|
||||
#if [ "$status" -eq 0 ]; then
|
||||
# swapon -a
|
||||
# echo "Swap Partition Formatted"
|
||||
#else
|
||||
# echo "Swap Partition Format Failed"
|
||||
#fi
|
||||
touch /.growfsran
|
||||
return "$status"
|
||||
}
|
||||
|
||||
case "$1" in
|
||||
start)
|
||||
"$1";;
|
||||
*)
|
||||
echo "Usage: $0 {start}"
|
||||
exit 1
|
||||
esac
|
||||
97
board/sipeed/licheervnano/uboot_defconfig
Normal file
97
board/sipeed/licheervnano/uboot_defconfig
Normal file
|
|
@ -0,0 +1,97 @@
|
|||
CONFIG_RISCV=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="soph_asic"
|
||||
CONFIG_IDENT_STRING="LicheeRVNano"
|
||||
CONFIG_ARCH_RV64I=y
|
||||
CONFIG_RISCV_SMODE=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_SD_BOOT=y
|
||||
CONFIG_BOOTDELAY=1
|
||||
CONFIG_LOGLEVEL=10
|
||||
# CONFIG_SYS_DEVICE_NULLDEV is not set
|
||||
CONFIG_DISPLAY_CPUINFO=y
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SYS_PROMPT="soph# "
|
||||
CONFIG_CMD_CONFIG=y
|
||||
CONFIG_CMD_SBI=y
|
||||
CONFIG_CMD_BOOTMENU=y
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_CRC32 is not set
|
||||
CONFIG_CMD_MEMINFO=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_SYS_ALT_MEMTEST=y
|
||||
# CONFIG_CMD_LZMADEC is not set
|
||||
# CONFIG_CMD_UNLZ4 is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DM=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
# CONFIG_RANDOM_UUID is not set
|
||||
CONFIG_BOOTLOGO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_LSBLK=y
|
||||
CONFIG_CMD_MBR=y
|
||||
CONFIG_CMD_MMC=y
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
CONFIG_CMD_DNS=y
|
||||
CONFIG_CMD_BMP=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_CLS=y
|
||||
CONFIG_CMD_DIAG=y
|
||||
CONFIG_CMD_LOG=y
|
||||
CONFIG_CMD_CVI_VO=y
|
||||
CONFIG_CMD_CVISOUND=y
|
||||
# CONFIG_CMD_CVI_UPDATE is not set
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
CONFIG_ENV_IS_NOWHERE=y
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
CONFIG_ENV_FAT_DEVICE_AND_PART="1"
|
||||
CONFIG_BOOTP_SEND_HOSTNAME=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_BUTTON=y
|
||||
CONFIG_BUTTON_GPIO=y
|
||||
CONFIG_UDP_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_BUF_ADDR=0x81800000
|
||||
CONFIG_FASTBOOT_BUF_SIZE=0x1000000
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_DWAPB_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_DW=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_BLINK=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_CVITEK=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_PHY_CVITEK=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_CVI_SOUND_DRIVERS=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_VIDEO=y
|
||||
CONFIG_BACKLIGHT_GPIO=y
|
||||
CONFIG_VIDEO_MIPI_DSI=y
|
||||
CONFIG_SYS_WHITE_ON_BLACK=y
|
||||
CONFIG_DISPLAY=y
|
||||
CONFIG_SPLASH_SCREEN=y
|
||||
CONFIG_SPLASHIMAGE_GUARD=y
|
||||
CONFIG_SPLASH_SCREEN_ALIGN=y
|
||||
CONFIG_SPLASH_SOURCE=y
|
||||
CONFIG_VIDEO_BMP_GZIP=y
|
||||
CONFIG_VIDEO_BMP_RLE8=y
|
||||
CONFIG_BMP_16BPP=y
|
||||
CONFIG_BMP_24BPP=y
|
||||
CONFIG_BMP_32BPP=y
|
||||
CONFIG_LZ4=y
|
||||
CONFIG_LZMA=y
|
||||
# CONFIG_TOOLS_LIBCRYPTO is not set
|
||||
1
boot/Config.in
Normal file
1
boot/Config.in
Normal file
|
|
@ -0,0 +1 @@
|
|||
source "$BR2_EXTERNAL_LICHEERVNANO_BR_PATH/boot/cvitek-fsbl/Config.in"
|
||||
10
boot/cvitek-fsbl/Config.in
Normal file
10
boot/cvitek-fsbl/Config.in
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
comment "cvitek FSBL options"
|
||||
depends on !BR2_LINUX_KERNEL
|
||||
|
||||
config BR2_PACKAGE_CVITEK_FSBL
|
||||
bool "cvitek FSBL"
|
||||
depends on BR2_LINUX_KERNEL
|
||||
depends on BR2_TARGET_OPENSBI
|
||||
depends on BR2_TARGET_UBOOT
|
||||
help
|
||||
First Stage Boot Loader
|
||||
31
boot/cvitek-fsbl/cvitek-fsbl.mk
Normal file
31
boot/cvitek-fsbl/cvitek-fsbl.mk
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
################################################################################
|
||||
#
|
||||
# cvitek-fsbl
|
||||
#
|
||||
################################################################################
|
||||
|
||||
CVITEK_FSBL_VERSION = 415722ebd855abef2ba11e9cba3d80106d250eff
|
||||
CVITEK_FSBL_SITE = $(call github,sophgo,fsbl,$(CVITEK_FSBL_VERSION))
|
||||
CVITEK_FSBL_LICENSE = GPL-2.0
|
||||
CVITEK_FSBL_DEPENDENCIES = linux opensbi uboot
|
||||
CVITEK_FSBL_INSTALL_IMAGES = YES
|
||||
|
||||
|
||||
CVITEK_FSBL_MAKE_ENV = \
|
||||
CROSS_COMPILE=$(TARGET_CROSS) \
|
||||
CROSS_COMPILE_GLIBC_RISCV64=$(TARGET_CROSS) \
|
||||
CHIP_ARCH=sg200x \
|
||||
ARCH=riscv \
|
||||
DDR_CFG=ddr3_1866_x16 \
|
||||
FW_DYNAMIC=$(BINARIES_DIR)/fw_dynamic.bin
|
||||
|
||||
|
||||
define CVITEK_FSBL_BUILD_CMDS
|
||||
$(CVITEK_FSBL_MAKE_ENV) $(MAKE) -C $(@D) CFLAGS="-fno-stack-protector" LOADER_2ND_PATH=$(BINARIES_DIR)/u-boot.bin
|
||||
endef
|
||||
|
||||
define CVITEK_FSBL_INSTALL_IMAGES_CMDS
|
||||
$(INSTALL) -D -m 0755 $(@D)/build/sg200x/fip.bin $(BINARIES_DIR)/fip.bin
|
||||
endef
|
||||
|
||||
$(eval $(generic-package))
|
||||
258
configs/sipeed_licheervnano_defconfig
Normal file
258
configs/sipeed_licheervnano_defconfig
Normal file
|
|
@ -0,0 +1,258 @@
|
|||
BR2_riscv=y
|
||||
BR2_riscv_custom=y
|
||||
BR2_RISCV_ISA_RVM=y
|
||||
BR2_RISCV_ISA_RVA=y
|
||||
BR2_RISCV_ISA_RVF=y
|
||||
BR2_RISCV_ISA_RVD=y
|
||||
BR2_RISCV_ISA_RVC=y
|
||||
BR2_TOOLCHAIN_EXTERNAL=y
|
||||
BR2_TOOLCHAIN_EXTERNAL_DOWNLOAD=y
|
||||
BR2_TOOLCHAIN_EXTERNAL_URL="https://github.com/sophgo/host-tools/archive/9c032cf5ff951c26a0747b738c7c6291513ac8d7.tar.gz"
|
||||
BR2_TOOLCHAIN_EXTERNAL_REL_BIN_PATH="gcc/riscv64-linux-musl-x86_64/bin/"
|
||||
BR2_TOOLCHAIN_EXTERNAL_CUSTOM_PREFIX="riscv64-unknown-linux-musl"
|
||||
BR2_TOOLCHAIN_EXTERNAL_GCC_10=y
|
||||
BR2_TOOLCHAIN_EXTERNAL_HEADERS_5_10=y
|
||||
BR2_TOOLCHAIN_EXTERNAL_CUSTOM_MUSL=y
|
||||
BR2_TOOLCHAIN_EXTERNAL_CXX=y
|
||||
BR2_TOOLCHAIN_EXTERNAL_OPENMP=y
|
||||
BR2_TARGET_LDFLAGS="-latomic"
|
||||
BR2_CPAN_MIRROR="http://cpan.metacpan.org"
|
||||
BR2_CCACHE=y
|
||||
BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_LICHEERVNANO_BR_PATH)/board/sipeed/licheervnano/patches/"
|
||||
BR2_TARGET_GENERIC_HOSTNAME="licheervnano"
|
||||
BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_MDEV=y
|
||||
BR2_SYSTEM_DHCP="eth0 wlan0"
|
||||
BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_LICHEERVNANO_BR_PATH)/board/sipeed/licheervnano/rootfs-overlay"
|
||||
BR2_ROOTFS_POST_FAKEROOT_SCRIPT="$(BR2_EXTERNAL_LICHEERVNANO_BR_PATH)/board/sipeed/licheervnano/preimage.sh"
|
||||
BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_LICHEERVNANO_BR_PATH)/board/sipeed/licheervnano/postinstall.sh"
|
||||
BR2_LINUX_KERNEL=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_GIT=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_REPO_URL="https://github.com/sophgo/linux_5.10.git"
|
||||
BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="15b85495e9fc947d0b7216fde7f245c0d6b4c9d0"
|
||||
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_LICHEERVNANO_BR_PATH)/board/sipeed/licheervnano/linux_defconfig"
|
||||
BR2_LINUX_KERNEL_IMAGEGZ=y
|
||||
BR2_LINUX_KERNEL_DTS_SUPPORT=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_DTS_PATH="$(BR2_EXTERNAL_LICHEERVNANO_BR_PATH)/board/sipeed/licheervnano/dts/sg2002_licheervnano_sd.dts $(BR2_EXTERNAL_LICHEERVNANO_BR_PATH)/board/sipeed/licheervnano/dts/*.dtsi $(BR2_EXTERNAL_LICHEERVNANO_BR_PATH)/board/sipeed/licheervnano/generated/cvi_board_memmap.h"
|
||||
BR2_LINUX_KERNEL_DTB_OVERLAY_SUPPORT=y
|
||||
BR2_LINUX_KERNEL_INSTALL_TARGET=y
|
||||
BR2_PACKAGE_LINUX_TOOLS_GPIO=y
|
||||
BR2_PACKAGE_LINUX_TOOLS_IIO=y
|
||||
BR2_PACKAGE_BUSYBOX_SHOW_OTHERS=y
|
||||
BR2_PACKAGE_ALSA_UTILS=y
|
||||
BR2_PACKAGE_ALSA_UTILS_ALSACONF=y
|
||||
BR2_PACKAGE_ALSA_UTILS_ALSAUCM=y
|
||||
BR2_PACKAGE_ALSA_UTILS_AMIDI=y
|
||||
BR2_PACKAGE_ALSA_UTILS_AMIXER=y
|
||||
BR2_PACKAGE_ALSA_UTILS_APLAY=y
|
||||
BR2_PACKAGE_ALSA_UTILS_APLAYMIDI=y
|
||||
BR2_PACKAGE_ALSA_UTILS_ARECORDMIDI=y
|
||||
BR2_PACKAGE_ALSA_UTILS_SPEAKER_TEST=y
|
||||
BR2_PACKAGE_FFMPEG=y
|
||||
BR2_PACKAGE_FFMPEG_GPL=y
|
||||
# BR2_PACKAGE_FFMPEG_FFMPEG is not set
|
||||
BR2_PACKAGE_FFMPEG_SWSCALE=y
|
||||
BR2_PACKAGE_GSTREAMER1=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BASE_INSTALL_TOOLS=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BASE_PLUGIN_ADDER=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BASE_PLUGIN_APP=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BASE_PLUGIN_AUDIOMIXER=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BASE_PLUGIN_AUDIORATE=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BASE_PLUGIN_AUDIOTESTSRC=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BASE_PLUGIN_COMPOSITOR=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BASE_PLUGIN_ENCODING=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BASE_PLUGIN_GIO=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BASE_PLUGIN_GIO_TYPEFINDER=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BASE_PLUGIN_OVERLAYCOMPOSITION=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BASE_PLUGIN_RAWPARSE=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BASE_PLUGIN_SUBPARSE=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BASE_PLUGIN_TCP=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BASE_PLUGIN_VIDEOTESTSRC=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BASE_PLUGIN_VIDEORATE=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BASE_PLUGIN_ALSA=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BASE_PLUGIN_TREMOR=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BASE_PLUGIN_OGG=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BASE_PLUGIN_OPUS=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BASE_PLUGIN_PANGO=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BASE_PLUGIN_THEORA=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BASE_PLUGIN_VORBIS=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_GOOD=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_GOOD_JPEG=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_GOOD_PNG=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_BAD=y
|
||||
BR2_PACKAGE_GST1_PLUGINS_UGLY=y
|
||||
BR2_PACKAGE_GZIP=y
|
||||
BR2_PACKAGE_LRZIP=y
|
||||
BR2_PACKAGE_LZIP=y
|
||||
BR2_PACKAGE_LZOP=y
|
||||
BR2_PACKAGE_UNRAR=y
|
||||
BR2_PACKAGE_UNZIP=y
|
||||
BR2_PACKAGE_XZ=y
|
||||
BR2_PACKAGE_ZIP=y
|
||||
BR2_PACKAGE_ZSTD=y
|
||||
BR2_PACKAGE_DOSFSTOOLS=y
|
||||
BR2_PACKAGE_DOSFSTOOLS_FATLABEL=y
|
||||
BR2_PACKAGE_DOSFSTOOLS_FSCK_FAT=y
|
||||
BR2_PACKAGE_DOSFSTOOLS_MKFS_FAT=y
|
||||
BR2_PACKAGE_E2FSPROGS_RESIZE2FS=y
|
||||
BR2_PACKAGE_E2TOOLS=y
|
||||
BR2_PACKAGE_EXFAT_UTILS=y
|
||||
BR2_PACKAGE_EXFATPROGS=y
|
||||
BR2_PACKAGE_FB_TEST_APP=y
|
||||
BR2_PACKAGE_FBDUMP=y
|
||||
BR2_PACKAGE_FBGRAB=y
|
||||
BR2_PACKAGE_FBSET=y
|
||||
BR2_PACKAGE_FBTERM=y
|
||||
BR2_PACKAGE_QT5=y
|
||||
BR2_PACKAGE_QT5BASE_EXAMPLES=y
|
||||
BR2_PACKAGE_QT5BASE_CONCURRENT=y
|
||||
BR2_PACKAGE_QT5BASE_MYSQL=y
|
||||
BR2_PACKAGE_QT5BASE_PSQL=y
|
||||
BR2_PACKAGE_QT5BASE_SQLITE_SYSTEM=y
|
||||
BR2_PACKAGE_QT5BASE_DEFAULT_QPA="linuxfb"
|
||||
BR2_PACKAGE_QT5BASE_FONTCONFIG=y
|
||||
BR2_PACKAGE_QT5BASE_HARFBUZZ=y
|
||||
BR2_PACKAGE_QT5BASE_GIF=y
|
||||
BR2_PACKAGE_QT5BASE_JPEG=y
|
||||
BR2_PACKAGE_QT5BASE_SYSLOG=y
|
||||
BR2_PACKAGE_QT5BASE_DBUS=y
|
||||
BR2_PACKAGE_QT5BASE_TSLIB=y
|
||||
BR2_PACKAGE_QT5CHARTS=y
|
||||
BR2_PACKAGE_QT5COAP=y
|
||||
BR2_PACKAGE_QT5IMAGEFORMATS=y
|
||||
BR2_PACKAGE_QT5MQTT=y
|
||||
BR2_PACKAGE_QT5MULTIMEDIA=y
|
||||
BR2_PACKAGE_QT5REMOTEOBJECTS=y
|
||||
BR2_PACKAGE_QT5SENSORS=y
|
||||
BR2_PACKAGE_QT5SERIALBUS=y
|
||||
BR2_PACKAGE_QT5SPEECH=y
|
||||
BR2_PACKAGE_QT5SVG=y
|
||||
BR2_PACKAGE_QT5TOOLS=y
|
||||
BR2_PACKAGE_QT5TOOLS_LINGUIST_TOOLS=y
|
||||
BR2_PACKAGE_QT5TOOLS_QDOC_TOOL=y
|
||||
BR2_PACKAGE_QT5TOOLS_PIXELTOOL=y
|
||||
BR2_PACKAGE_QT5TOOLS_QTDIAG=y
|
||||
BR2_PACKAGE_QT5TOOLS_QTPATHS=y
|
||||
BR2_PACKAGE_QT5TOOLS_QTPLUGININFO=y
|
||||
BR2_PACKAGE_QT5WEBCHANNEL=y
|
||||
BR2_PACKAGE_QT5XMLPATTERNS=y
|
||||
BR2_PACKAGE_EVTEST=y
|
||||
BR2_PACKAGE_GPTFDISK=y
|
||||
BR2_PACKAGE_GPTFDISK_SGDISK=y
|
||||
BR2_PACKAGE_I2C_TOOLS=y
|
||||
BR2_PACKAGE_LM_SENSORS=y
|
||||
BR2_PACKAGE_LSHW=y
|
||||
BR2_PACKAGE_MEMTESTER=y
|
||||
BR2_PACKAGE_MEMTOOL=y
|
||||
BR2_PACKAGE_MINICOM=y
|
||||
BR2_PACKAGE_PARTED=y
|
||||
BR2_PACKAGE_PICOCOM=y
|
||||
BR2_PACKAGE_RTC_TOOLS=y
|
||||
BR2_PACKAGE_SETSERIAL=y
|
||||
BR2_PACKAGE_SPI_TOOLS=y
|
||||
BR2_PACKAGE_TIO=y
|
||||
BR2_PACKAGE_UBOOT_TOOLS=y
|
||||
BR2_PACKAGE_UBOOT_TOOLS_FIT_SUPPORT=y
|
||||
BR2_PACKAGE_UBOOT_TOOLS_MKIMAGE=y
|
||||
BR2_PACKAGE_UBOOT_TOOLS_MKEFICAPSULE=y
|
||||
BR2_PACKAGE_UBOOT_TOOLS_MKENVIMAGE=y
|
||||
BR2_PACKAGE_UBOOT_TOOLS_DUMPIMAGE=y
|
||||
BR2_PACKAGE_LUA=y
|
||||
BR2_PACKAGE_LUA_LINENOISE=y
|
||||
BR2_PACKAGE_PYTHON3=y
|
||||
BR2_PACKAGE_PYTHON3_PY_PYC=y
|
||||
BR2_PACKAGE_MARIADB=y
|
||||
BR2_PACKAGE_SQLITE_STAT4=y
|
||||
BR2_PACKAGE_SQLITE_ENABLE_FTS3=y
|
||||
BR2_PACKAGE_SQLITE_ENABLE_JSON1=y
|
||||
BR2_PACKAGE_SQLITE_ENABLE_UNLOCK_NOTIFY=y
|
||||
BR2_PACKAGE_LIBGPIOD=y
|
||||
BR2_PACKAGE_LIBGPIOD_TOOLS=y
|
||||
BR2_PACKAGE_PCRE=y
|
||||
BR2_PACKAGE_AVAHI=y
|
||||
BR2_PACKAGE_AVAHI_DAEMON=y
|
||||
BR2_PACKAGE_AVAHI_DEFAULT_SERVICES=y
|
||||
BR2_PACKAGE_DHCPCD=y
|
||||
BR2_PACKAGE_DROPBEAR=y
|
||||
BR2_PACKAGE_DROPBEAR_WTMP=y
|
||||
BR2_PACKAGE_DROPBEAR_LASTLOG=y
|
||||
BR2_PACKAGE_ETHTOOL=y
|
||||
BR2_PACKAGE_IPERF3=y
|
||||
BR2_PACKAGE_IPTABLES=y
|
||||
BR2_PACKAGE_NET_TOOLS=y
|
||||
BR2_PACKAGE_NFTABLES=y
|
||||
BR2_PACKAGE_NTP=y
|
||||
BR2_PACKAGE_NTP_SNTP=y
|
||||
BR2_PACKAGE_NTP_NTPDATE=y
|
||||
BR2_PACKAGE_NTP_NTPDC=y
|
||||
BR2_PACKAGE_NTP_NTPQ=y
|
||||
BR2_PACKAGE_NTP_NTPTIME=y
|
||||
BR2_PACKAGE_NTP_TICKADJ=y
|
||||
BR2_PACKAGE_PPPD=y
|
||||
BR2_PACKAGE_RSYNC=y
|
||||
BR2_PACKAGE_TCPDUMP=y
|
||||
BR2_PACKAGE_TRACEROUTE=y
|
||||
BR2_PACKAGE_WGET=y
|
||||
BR2_PACKAGE_WIREGUARD_TOOLS=y
|
||||
BR2_PACKAGE_WIRELESS_TOOLS=y
|
||||
BR2_PACKAGE_WPA_SUPPLICANT=y
|
||||
BR2_PACKAGE_WPA_SUPPLICANT_AP_SUPPORT=y
|
||||
BR2_PACKAGE_WPA_SUPPLICANT_EAP=y
|
||||
BR2_PACKAGE_WPA_SUPPLICANT_DEBUG_SYSLOG=y
|
||||
BR2_PACKAGE_WPA_SUPPLICANT_CLI=y
|
||||
BR2_PACKAGE_WPA_SUPPLICANT_WPA_CLIENT_SO=y
|
||||
BR2_PACKAGE_WPA_SUPPLICANT_PASSPHRASE=y
|
||||
BR2_PACKAGE_WPA_SUPPLICANT_DBUS=y
|
||||
BR2_PACKAGE_ZSH=y
|
||||
BR2_PACKAGE_BASH_COMPLETION=y
|
||||
BR2_PACKAGE_DIALOG=y
|
||||
BR2_PACKAGE_FILE=y
|
||||
BR2_PACKAGE_LOGROTATE=y
|
||||
BR2_PACKAGE_NEOFETCH=y
|
||||
BR2_PACKAGE_SCREEN=y
|
||||
BR2_PACKAGE_SUDO=y
|
||||
BR2_PACKAGE_TIME=y
|
||||
BR2_PACKAGE_TMUX=y
|
||||
BR2_PACKAGE_TTYD=y
|
||||
BR2_PACKAGE_ACL=y
|
||||
BR2_PACKAGE_ATOP=y
|
||||
BR2_PACKAGE_HTOP=y
|
||||
BR2_PACKAGE_IOTOP=y
|
||||
BR2_PACKAGE_PSMISC=y
|
||||
BR2_PACKAGE_UTIL_LINUX_PARTX=y
|
||||
BR2_PACKAGE_WATCHDOG=y
|
||||
BR2_PACKAGE_WATCHDOGD=y
|
||||
BR2_PACKAGE_JOE=y
|
||||
BR2_PACKAGE_MC=y
|
||||
BR2_PACKAGE_NANO=y
|
||||
BR2_PACKAGE_VIM=y
|
||||
BR2_TARGET_ROOTFS_EXT2=y
|
||||
BR2_TARGET_ROOTFS_EXT2_4=y
|
||||
BR2_TARGET_ROOTFS_EXT2_SIZE="512M"
|
||||
BR2_TARGET_OPENSBI=y
|
||||
BR2_TARGET_OPENSBI_CUSTOM_GIT=y
|
||||
BR2_TARGET_OPENSBI_CUSTOM_REPO_URL="https://github.com/sophgo/opensbi.git"
|
||||
BR2_TARGET_OPENSBI_CUSTOM_REPO_VERSION="216793f112543151ae6b01595d4ba20ee58f4f7c"
|
||||
BR2_TARGET_OPENSBI_PLAT="generic"
|
||||
BR2_TARGET_OPENSBI_UBOOT_PAYLOAD=y
|
||||
BR2_TARGET_OPENSBI_FW_FDT_PATH=y
|
||||
BR2_TARGET_UBOOT=y
|
||||
BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y
|
||||
BR2_TARGET_UBOOT_CUSTOM_GIT=y
|
||||
BR2_TARGET_UBOOT_CUSTOM_REPO_URL="https://github.com/sophgo/u-boot-2021.10.git"
|
||||
BR2_TARGET_UBOOT_CUSTOM_REPO_VERSION="a57aa1f29bb62dd9bc0c5f22b74520b8225d321f"
|
||||
BR2_TARGET_UBOOT_USE_CUSTOM_CONFIG=y
|
||||
BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_LICHEERVNANO_BR_PATH)/board/sipeed/licheervnano/uboot_defconfig"
|
||||
BR2_TARGET_UBOOT_CUSTOM_DTS_PATH="$(BR2_EXTERNAL_LICHEERVNANO_BR_PATH)/board/sipeed/licheervnano/dts/*"
|
||||
BR2_TARGET_UBOOT_CUSTOM_MAKEOPTS="CVIBOARD=licheervnano_sd CHIP=sg2002 STORAGE_TYPE=sd CONFIG_USE_DEFAULT_ENV=y PANEL_TUNING_PARAM=MIPI_PANEL_ZCT2133V1"
|
||||
BR2_PACKAGE_HOST_DOSFSTOOLS=y
|
||||
BR2_PACKAGE_HOST_ENVIRONMENT_SETUP=y
|
||||
BR2_PACKAGE_HOST_GENIMAGE=y
|
||||
BR2_PACKAGE_HOST_MTOOLS=y
|
||||
BR2_PACKAGE_HOST_PYTHON3=y
|
||||
BR2_PACKAGE_HOST_UBOOT_TOOLS=y
|
||||
BR2_PACKAGE_HOST_UBOOT_TOOLS_FIT_SUPPORT=y
|
||||
BR2_PACKAGE_AIC_FIRMWARE=y
|
||||
BR2_PACKAGE_CLOUDUTILS=y
|
||||
BR2_PACKAGE_CVITEK_MODULES=y
|
||||
BR2_PACKAGE_CVITEK_FSBL=y
|
||||
2
external.desc
Normal file
2
external.desc
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
name: LICHEERVNANO_BR
|
||||
desc: Buildroot for SG200x Chips (including LicheeRV Nano)
|
||||
24
external.mk
Normal file
24
external.mk
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
include $(sort $(wildcard $(BR2_EXTERNAL_LICHEERVNANO_BR_PATH)/package/*/*.mk))
|
||||
include $(sort $(wildcard $(BR2_EXTERNAL_LICHEERVNANO_BR_PATH)/boot/*/*.mk))
|
||||
|
||||
UBOOT_POST_PATCH_HOOKS += UBOOT_APPLY_SG2002_CONFIG_HOOK
|
||||
LINUX_POST_PATCH_HOOKS += LINUX_APPLY_SG2002_CONFIG_HOOK
|
||||
CVITEK_FSBL_POST_PATCH_HOOKS += CVITEK_FSBL_APPLY_SG2002_CONFIG_HOOK
|
||||
|
||||
define UBOOT_APPLY_SG2002_CONFIG_HOOK
|
||||
@echo "Applying SG2002 Generated Config"
|
||||
@cp $(BR2_GLOBAL_PATCH_DIR)../generated/cvi_board_memmap.h $(@D)/include/cvi_board_memmap.h
|
||||
@cp $(BR2_GLOBAL_PATCH_DIR)../generated/cvipart.h $(@D)/include/cvipart.h
|
||||
@cp $(BR2_GLOBAL_PATCH_DIR)../generated/uboot/cvi_board_init.c $(@D)/board/cvitek/
|
||||
endef
|
||||
|
||||
define LINUX_APPLY_SG2002_CONFIG_HOOK
|
||||
@echo "Applying SG2002 Generated Config"
|
||||
@cp $(BR2_GLOBAL_PATCH_DIR)../generated/cvi_board_memmap.h $(@D)/include/cvi_board_memmap.h
|
||||
@cp $(BR2_GLOBAL_PATCH_DIR)../generated/cvipart.h $(@D)/include/cvipart.h
|
||||
endef
|
||||
|
||||
define CVITEK_FSBL_APPLY_SG2002_CONFIG_HOOK
|
||||
@echo "Applying SG2002 Generated Config"
|
||||
@cp $(BR2_GLOBAL_PATCH_DIR)../generated/cvi_board_memmap.h $(@D)/include/cvi_board_memmap.h
|
||||
endef
|
||||
3
package/Config.in
Normal file
3
package/Config.in
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
source "$BR2_EXTERNAL_LICHEERVNANO_BR_PATH/package/aic-firmware/Config.in"
|
||||
source "$BR2_EXTERNAL_LICHEERVNANO_BR_PATH/package/cloudutils/Config.in"
|
||||
source "$BR2_EXTERNAL_LICHEERVNANO_BR_PATH/package/cvitek-modules/Config.in"
|
||||
1
package/Config.in.host
Normal file
1
package/Config.in.host
Normal file
|
|
@ -0,0 +1 @@
|
|||
#source "$BR2_EXTERNAL_LICHEERVNANO_BR_PATH/package/riscv-unknown-elf-gcc/Config.in.host"
|
||||
8
package/aic-firmware/Config.in
Normal file
8
package/aic-firmware/Config.in
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
config BR2_PACKAGE_AIC_FIRMWARE
|
||||
bool "AIC-firmware"
|
||||
help
|
||||
This package enables access to aic wireless firmware
|
||||
blobs from the armbian firmware repository.
|
||||
|
||||
https://github.com/armbian/firmware
|
||||
|
||||
2
package/aic-firmware/aic-firmware.hash
Normal file
2
package/aic-firmware/aic-firmware.hash
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
# Locally calculated
|
||||
sha256 4e82bdb23ddd0f4e35e2bdee62cb7dc95e199f103595d1e565a370a78c79ad77 aic-firmware-4354d9a-br1.tar.gz
|
||||
18
package/aic-firmware/aic-firmware.mk
Normal file
18
package/aic-firmware/aic-firmware.mk
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
################################################################################
|
||||
#
|
||||
# AIC-firmware
|
||||
#
|
||||
################################################################################
|
||||
|
||||
AIC_FIRMWARE_VERSION = 4354d9a
|
||||
AIC_FIRMWARE_SITE = https://github.com/armbian/firmware
|
||||
AIC_FIRMWARE_SITE_METHOD = git
|
||||
|
||||
|
||||
|
||||
define AIC_FIRMWARE_INSTALL_TARGET_CMDS
|
||||
mkdir -p $(TARGET_DIR)/lib/firmware/aic8800
|
||||
cp -a $(@D)/aic8800/SDIO/aic8800/ $(TARGET_DIR)/lib/firmware/
|
||||
endef
|
||||
|
||||
$(eval $(generic-package))
|
||||
7
package/cloudutils/Config.in
Normal file
7
package/cloudutils/Config.in
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
config BR2_PACKAGE_CLOUDUTILS
|
||||
bool "cloudutils"
|
||||
depends on BR2_PACKAGE_UTIL_LINUX_PARTX
|
||||
depends on BR2_PACKAGE_GPTFDISK_SGDISK
|
||||
help
|
||||
cloud-utils is a set of utilities for interacting with cloud images.
|
||||
|
||||
10
package/cloudutils/cloudutils.mk
Normal file
10
package/cloudutils/cloudutils.mk
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
CLOUDUTILS_VERSION = 0.33
|
||||
CLOUDUTILS_SITE = $(call github,canonical,cloud-utils,$(CLOUDUTILS_VERSION))
|
||||
CLOUDUTILS_LICENSE = GPL-3.0
|
||||
CLOUDUTILS_DEPENDENCIES =
|
||||
|
||||
define CLOUDUTILS_INSTALL_TARGET_CMDS
|
||||
$(TARGET_MAKE_ENV) $(CLOUDUTILS_MAKE_ENV) $(MAKE) -C $(@D) DESTDIR=$(TARGET_DIR) install
|
||||
endef
|
||||
|
||||
$(eval $(generic-package))
|
||||
8
package/cvitek-modules/Config.in
Normal file
8
package/cvitek-modules/Config.in
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
comment "cvi-tek Kernel Modules"
|
||||
depends on !BR2_LINUX_KERNEL
|
||||
|
||||
config BR2_PACKAGE_CVITEK_MODULES
|
||||
bool "cvi-tek Kernel Modules"
|
||||
depends on BR2_LINUX_KERNEL
|
||||
help
|
||||
Kernel Modules for cvi-tek devices.
|
||||
53
package/cvitek-modules/cvitek-modules.mk
Normal file
53
package/cvitek-modules/cvitek-modules.mk
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
################################################################################
|
||||
#
|
||||
# blwnet_xram
|
||||
#
|
||||
################################################################################
|
||||
|
||||
CVITEK_MODULES_VERSION = 5637fbf
|
||||
CVITEK_MODULES_SITE = $(call github,sophgo,osdrv,$(CVITEK_MODULES_VERSION))
|
||||
CVITEK_MODULES_LICENSE = GPL-2.0(kernel driver), Apache 2.0(userspace)
|
||||
|
||||
CVITEK_MODULES_MODULE_MAKE_OPTS = CHIP_CODE=mars V=1
|
||||
|
||||
CVITEK_MODULES_MODULE_SUBDIRS = interdrv/v2/sys
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += interdrv/v2/base
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += interdrv/v2/vcodec
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += interdrv/v2/jpeg
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += interdrv/v2/pwm
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += interdrv/v2/rtc
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += interdrv/v2/wdt
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += interdrv/v2/tpu
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += interdrv/v2/mon
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += interdrv/v2/clock_cooling
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += interdrv/v2/saradc
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += interdrv/v2/wiegand
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += interdrv/v2/vi
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += interdrv/v2/snsr_i2c
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += interdrv/v2/cif
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += interdrv/v2/vpss
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += interdrv/v2/dwa
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += interdrv/v2/rgn
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += interdrv/v2/vo
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += interdrv/v2/rtos_cmdqu
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += interdrv/v2/fast_image
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += interdrv/v2/cvi_vc_drv
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += interdrv/v2/ive
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += interdrv/v2/fb
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += extdrv/tp/ts_gsl
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += extdrv/tp/ts_gt9xx
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += extdrv/wiegand-gpio
|
||||
#CVITEK_MODULES_MODULE_SUBDIRS += extdrv/gyro_i2c
|
||||
#CVITEK_MODULES_MODULE_SUBDIRS += extdrv/wireless/broadcom/bcmdhd
|
||||
#CVITEK_MODULES_MODULE_SUBDIRS += extdrv/wireless/icommsemi/sv6115
|
||||
#CVITEK_MODULES_MODULE_SUBDIRS += extdrv/wireless/mediatek/mt7603
|
||||
#CVITEK_MODULES_MODULE_SUBDIRS += extdrv/wireless/realtek/rtl8188f
|
||||
#CVITEK_MODULES_MODULE_SUBDIRS += extdrv/wireless/realtek/rtl8189fs
|
||||
#CVITEK_MODULES_MODULE_SUBDIRS += extdrv/wireless/realtek/rtl8723ds
|
||||
#CVITEK_MODULES_MODULE_SUBDIRS += extdrv/wireless/realtek/rtl8821cs
|
||||
CVITEK_MODULES_MODULE_SUBDIRS += extdrv/wireless/aic8800/
|
||||
|
||||
|
||||
|
||||
$(eval $(kernel-module))
|
||||
$(eval $(generic-package))
|
||||
Loading…
Add table
Reference in a new issue