diff --git a/patch/kernel/sunxi64-dev/add-smc-mailbox-docs.patch b/patch/kernel/sunxi64-dev/add-smc-mailbox-docs.patch deleted file mode 100644 index ff2b1becd..000000000 --- a/patch/kernel/sunxi64-dev/add-smc-mailbox-docs.patch +++ /dev/null @@ -1,78 +0,0 @@ -Add binding documentation for the generic ARM SMC mailbox. -This is not describing hardware, but a firmware interface. - -Signed-off-by: Andre Przywara ---- - .../devicetree/bindings/mailbox/arm-smc.txt | 61 ++++++++++++++++++++++ - 1 file changed, 61 insertions(+) - create mode 100644 Documentation/devicetree/bindings/mailbox/arm-smc.txt - -diff --git a/Documentation/devicetree/bindings/mailbox/arm-smc.txt b/Documentation/devicetree/bindings/mailbox/arm-smc.txt -new file mode 100644 -index 0000000..90c5926 ---- /dev/null -+++ b/Documentation/devicetree/bindings/mailbox/arm-smc.txt -@@ -0,0 +1,61 @@ -+ARM SMC Mailbox Driver -+====================== -+ -+This mailbox uses the ARM smc (secure monitor call) instruction to -+trigger a mailbox-connected activity in firmware, executing on the very same -+core as the caller. By nature this operation is synchronous and this -+mailbox provides no way for asynchronous messages to be delivered the other -+way round, from firmware to the OS. However the value of r0/w0/x0 the firmware -+returns after the smc call is delivered as a received message to the -+mailbox framework, so a synchronous communication can be established. -+ -+One use case of this mailbox is the SCP interface, which uses shared memory -+to transfer commands and parameters, and a mailbox to trigger a function -+call. This allows SoCs without a separate management processor (or -+when such a processor is not available or used) to use this standardized -+interface anyway. -+ -+This binding describes no hardware, but establishes a firmware interface. -+The communication follows the ARM SMC calling convention[1]. -+Any core which supports the SMC or HVC instruction can be used, as long as -+a firmware component running in EL3 or EL2 is handling these calls. -+ -+Mailbox Device Node: -+==================== -+ -+Required properties: -+-------------------- -+- compatible: Shall be "arm,smc-mbox" -+- #mbox-cells Shall be 1 - the index of the channel needed. -+- arm,smc-func-ids An array of 32-bit values specifying the function -+ IDs used by each mailbox channel. Those function IDs -+ follow the ARM SMC calling convention standard [1]. -+ There is one identifier per channel and the number -+ of supported channels is determined by the length -+ of this array. -+ -+Optional properties: -+-------------------- -+- method: A string, either: -+ "hvc": if the driver shall use an HVC call, or -+ "smc": if the driver shall use an SMC call -+ If omitted, defaults to an SMC call. -+ -+Example: -+-------- -+ -+ mailbox: smc_mbox { -+ #mbox-cells = <1>; -+ compatible = "arm,smc-mbox"; -+ identifiers = <0x82000001>, <0x82000002>; -+ }; -+ -+ scpi { -+ compatible = "arm,scpi"; -+ mboxes = <&mailbox 0>; -+ shmem = <&cpu_scp_shmem>; -+ }; -+ -+ -+[1] -+http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0028a/index.html --- -2.9.0 diff --git a/patch/kernel/sunxi64-dev/add-smc-mailbox-driver.patch b/patch/kernel/sunxi64-dev/add-smc-mailbox-driver.patch deleted file mode 100644 index ccbf10375..000000000 --- a/patch/kernel/sunxi64-dev/add-smc-mailbox-driver.patch +++ /dev/null @@ -1,225 +0,0 @@ -This mailbox driver implements a mailbox which signals transmitted data -via an ARM smc (secure monitor call) instruction. The mailbox receiver -is implemented in firmware and can synchronously return data when it -returns execution to the non-secure world again. -An asynchronous receive path is not implemented. -This allows the usage of a mailbox to trigger firmware actions on SoCs -which either don't have a separate management processor or on which such -a core is not available. A user of this mailbox could be the SCP -interface. - -Signed-off-by: Andre Przywara ---- - drivers/mailbox/Kconfig | 8 ++ - drivers/mailbox/Makefile | 2 + - drivers/mailbox/arm-smc-mailbox.c | 172 ++++++++++++++++++++++++++++++++++++++ - 3 files changed, 182 insertions(+) - create mode 100644 drivers/mailbox/arm-smc-mailbox.c - -diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig -index c5731e5..5664b7f 100644 ---- a/drivers/mailbox/Kconfig -+++ b/drivers/mailbox/Kconfig -@@ -170,4 +170,12 @@ config BCM_FLEXRM_MBOX - Mailbox implementation of the Broadcom FlexRM ring manager, - which provides access to various offload engines on Broadcom - SoCs. Say Y here if you want to use the Broadcom FlexRM. -+ -+config ARM_SMC_MBOX -+ tristate "Generic ARM smc mailbox" -+ depends on OF && HAVE_ARM_SMCCC -+ help -+ Generic mailbox driver which uses ARM smc calls to call into -+ firmware for triggering mailboxes. -+ - endif -diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile -index d54e412..8ec6869 100644 ---- a/drivers/mailbox/Makefile -+++ b/drivers/mailbox/Makefile -@@ -35,3 +35,5 @@ obj-$(CONFIG_BCM_FLEXRM_MBOX) += bcm-flexrm-mailbox.o - obj-$(CONFIG_QCOM_APCS_IPC) += qcom-apcs-ipc-mailbox.o - - obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o -+ -+obj-$(CONFIG_ARM_SMC_MBOX) += arm-smc-mailbox.o -diff --git a/drivers/mailbox/arm-smc-mailbox.c b/drivers/mailbox/arm-smc-mailbox.c -new file mode 100644 -index 0000000..578aed2 ---- /dev/null -+++ b/drivers/mailbox/arm-smc-mailbox.c -@@ -0,0 +1,172 @@ -+/* -+ * Copyright (C) 2016,2017 ARM Ltd. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This device provides a mechanism for emulating a mailbox by using -+ * smc calls, allowing a "mailbox" consumer to sit in firmware running -+ * on the same core. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define ARM_SMC_MBOX_SMC (0 << 0) -+#define ARM_SMC_MBOX_HVC (1 << 0) -+#define ARM_SMC_MBOX_METHOD_MASK (1 << 0) -+ -+struct arm_smc_chan_data { -+ u32 function_id; -+ u32 flags; -+}; -+ -+static int arm_smc_send_data(struct mbox_chan *link, void *data) -+{ -+ struct arm_smc_chan_data *chan_data = link->con_priv; -+ u32 function_id = chan_data->function_id; -+ struct arm_smccc_res res; -+ u32 msg = *(u32 *)data; -+ -+ if ((chan_data->flags & ARM_SMC_MBOX_METHOD_MASK) == ARM_SMC_MBOX_SMC) -+ arm_smccc_smc(function_id, msg, 0, 0, 0, 0, 0, 0, &res); -+ else -+ arm_smccc_hvc(function_id, msg, 0, 0, 0, 0, 0, 0, &res); -+ -+ mbox_chan_received_data(link, (void *)res.a0); -+ -+ return 0; -+} -+ -+static int arm_smc_startup(struct mbox_chan *link) -+{ -+ return 0; -+} -+ -+static void arm_smc_shutdown(struct mbox_chan *link) -+{ -+} -+ -+/* This mailbox is synchronous, so we are always done. */ -+static bool arm_smc_last_tx_done(struct mbox_chan *link) -+{ -+ return true; -+} -+ -+static const struct mbox_chan_ops arm_smc_mbox_chan_ops = { -+ .send_data = arm_smc_send_data, -+ .startup = arm_smc_startup, -+ .shutdown = arm_smc_shutdown, -+ .last_tx_done = arm_smc_last_tx_done -+}; -+ -+static int arm_smc_mbox_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct mbox_controller *mbox; -+ struct arm_smc_chan_data *chan_data; -+ const char *method; -+ bool use_hvc = false; -+ int ret = 0, i; -+ -+ ret = of_property_count_elems_of_size(dev->of_node, "arm,smc-func-ids", -+ sizeof(u32)); -+ if (ret < 0) -+ return ret; -+ -+ if (!of_property_read_string(dev->of_node, "method", &method)) { -+ if (!strcmp("hvc", method)) { -+ use_hvc = true; -+ } else if (!strcmp("smc", method)) { -+ use_hvc = false; -+ } else { -+ dev_warn(dev, "invalid \"method\" property: %s\n", -+ method); -+ -+ return -EINVAL; -+ } -+ } -+ -+ mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); -+ if (!mbox) -+ return -ENOMEM; -+ -+ mbox->num_chans = ret; -+ mbox->chans = devm_kcalloc(dev, mbox->num_chans, sizeof(*mbox->chans), -+ GFP_KERNEL); -+ if (!mbox->chans) -+ return -ENOMEM; -+ -+ chan_data = devm_kcalloc(dev, mbox->num_chans, sizeof(*chan_data), -+ GFP_KERNEL); -+ if (!chan_data) -+ return -ENOMEM; -+ -+ for (i = 0; i < mbox->num_chans; i++) { -+ u32 function_id; -+ -+ ret = of_property_read_u32_index(dev->of_node, -+ "arm,smc-func-ids", i, -+ &function_id); -+ if (ret) -+ return ret; -+ -+ chan_data[i].function_id = function_id; -+ if (use_hvc) -+ chan_data[i].flags |= ARM_SMC_MBOX_HVC; -+ mbox->chans[i].con_priv = &chan_data[i]; -+ } -+ -+ mbox->txdone_poll = true; -+ mbox->txdone_irq = false; -+ mbox->txpoll_period = 1; -+ mbox->ops = &arm_smc_mbox_chan_ops; -+ mbox->dev = dev; -+ -+ ret = mbox_controller_register(mbox); -+ if (ret) -+ return ret; -+ -+ platform_set_drvdata(pdev, mbox); -+ dev_info(dev, "ARM SMC mailbox enabled with %d chan%s.\n", -+ mbox->num_chans, mbox->num_chans == 1 ? "" : "s"); -+ -+ return ret; -+} -+ -+static int arm_smc_mbox_remove(struct platform_device *pdev) -+{ -+ struct mbox_controller *mbox = platform_get_drvdata(pdev); -+ -+ mbox_controller_unregister(mbox); -+ return 0; -+} -+ -+static const struct of_device_id arm_smc_mbox_of_match[] = { -+ { .compatible = "arm,smc-mbox", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, arm_smc_mbox_of_match); -+ -+static struct platform_driver arm_smc_mbox_driver = { -+ .driver = { -+ .name = "arm-smc-mbox", -+ .of_match_table = arm_smc_mbox_of_match, -+ }, -+ .probe = arm_smc_mbox_probe, -+ .remove = arm_smc_mbox_remove, -+}; -+module_platform_driver(arm_smc_mbox_driver); -+ -+MODULE_AUTHOR("Andre Przywara "); -+MODULE_DESCRIPTION("Generic ARM smc mailbox driver"); -+MODULE_LICENSE("GPL v2"); --- -2.9.0 diff --git a/patch/kernel/sunxi64-dev/scpi/add-smc-mailbox-a64-DT-01.patch b/patch/kernel/sunxi64-dev/scpi/add-smc-mailbox-a64-DT-01.patch deleted file mode 100644 index f15d358a4..000000000 --- a/patch/kernel/sunxi64-dev/scpi/add-smc-mailbox-a64-DT-01.patch +++ /dev/null @@ -1,50 +0,0 @@ -This adds support for the SCPI protocol using an SMC mailbox and some -shared memory in SRAM. -The SCPI provider is implemented in the ARM Trusted Firmware layer -(running in EL3 on the application processor cores), triggered by an smc -call. - -Signed-off-by: Andre Przywara ---- - arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 26 ++++++++++++++++++++++++++ - 1 file changed, 26 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -index 9d00622..ef6f10e 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -@@ -124,6 +124,32 @@ - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - -+ mailbox: mbox@0 { -+ compatible = "arm,smc-mbox"; -+ #mbox-cells = <1>; -+ arm,smc-func-ids = <0x82000001>; -+ }; -+ -+ sram: sram@10000{ -+ compatible = "mmio-sram"; -+ reg = <0x10000 0x8000>; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0x10000 0x8000>; -+ -+ cpu_scp_mem: scp-shmem@7e00 { -+ compatible = "mmio-sram"; -+ reg = <0x7e00 0x200>; -+ }; -+ }; -+ -+ scpi { -+ compatible = "arm,scpi"; -+ mboxes = <&mailbox 0>; -+ shmem = <&cpu_scp_mem>; -+ }; -+ - soc { - compatible = "simple-bus"; - #address-cells = <1>; --- -2.9.0 diff --git a/patch/kernel/sunxi64-dev/scpi/add-smc-mailbox-a64-DT-02.patch b/patch/kernel/sunxi64-dev/scpi/add-smc-mailbox-a64-DT-02.patch deleted file mode 100644 index c1a139aa1..000000000 --- a/patch/kernel/sunxi64-dev/scpi/add-smc-mailbox-a64-DT-02.patch +++ /dev/null @@ -1,67 +0,0 @@ -One functionality provided by the SCPI handler is frequency scaling, -which allows to switch the one CPU cluster between several operating -points, each specifying a matching frequency and CPU voltage. -The actual table is specified in firmware and can be queried by Linux -using standardised SCPI calls. - -Signed-off-by: Andre Przywara ---- - arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -index ef6f10e..58c3675 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -@@ -61,6 +61,7 @@ - device_type = "cpu"; - reg = <0>; - enable-method = "psci"; -+ clocks = <&scpi_dvfs 0>; - }; - - cpu1: cpu@1 { -@@ -68,6 +69,7 @@ - device_type = "cpu"; - reg = <1>; - enable-method = "psci"; -+ clocks = <&scpi_dvfs 0>; - }; - - cpu2: cpu@2 { -@@ -75,6 +77,7 @@ - device_type = "cpu"; - reg = <2>; - enable-method = "psci"; -+ clocks = <&scpi_dvfs 0>; - }; - - cpu3: cpu@3 { -@@ -82,6 +85,7 @@ - device_type = "cpu"; - reg = <3>; - enable-method = "psci"; -+ clocks = <&scpi_dvfs 0>; - }; - }; - -@@ -148,6 +152,17 @@ - compatible = "arm,scpi"; - mboxes = <&mailbox 0>; - shmem = <&cpu_scp_mem>; -+ -+ scpi-clocks { -+ compatible = "arm,scpi-clocks"; -+ -+ scpi_dvfs: scpi_dvfs_clocks { -+ compatible = "arm,scpi-dvfs-clocks"; -+ #clock-cells = <1>; -+ clock-indices = <0>; -+ clock-output-names = "cpu_clk"; -+ }; -+ }; - }; - - soc { --- -2.9.0 diff --git a/patch/kernel/sunxi64-dev/scpi/add-smc-mailbox-a64-DT-03.patch b/patch/kernel/sunxi64-dev/scpi/add-smc-mailbox-a64-DT-03.patch deleted file mode 100644 index 9d72d2be8..000000000 --- a/patch/kernel/sunxi64-dev/scpi/add-smc-mailbox-a64-DT-03.patch +++ /dev/null @@ -1,40 +0,0 @@ -The SCPI protocol allows various sensors to be exposed to the OS. The -list of supported sensors (and their kind) is provided by the SCPI -provider, which is in ARM Trusted Firmware. The current implementation -exports the temperature sensors, for instance. -Since the temperature sensor requires a clock to be running, we set -a fixed clock rate for this particular clock to prevent the Linux driver -from turning it off. - -Signed-off-by: Andre Przywara ---- - arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -index 58c3675..7cb1b04 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -@@ -163,6 +163,11 @@ - clock-output-names = "cpu_clk"; - }; - }; -+ -+ scpi_sensors0: sensors { -+ compatible = "arm,scpi-sensors"; -+ #thermal-sensor-cells = <1>; -+ }; - }; - - soc { -@@ -307,6 +312,8 @@ - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; -+ assigned-clocks = <&ccu CLK_THS>; -+ assigned-clock-rates = <4000000>; - }; - - pio: pinctrl@1c20800 { --- -2.9.0