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Additional patches for Armada Clearfog

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This commit is contained in:
Igor Pecovnik 2016-01-24 15:47:33 +01:00
parent 1f9e0a75c1
commit 07b6285bd0
6 changed files with 1930 additions and 0 deletions
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1395
patch/kernel/marvell-dev/check_and_merge/0014-sfp-add-phylink-based-SFP-module-support.patch Normal file
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318
patch/kernel/marvell-dev/check_and_merge/0040-updates.patch Normal file
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@ -0,0 +1,318 @@
From f8da22c0f81995de80f1f31f96e8748bb4f96ece Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Mon, 28 Dec 2015 13:55:13 +0100
Subject: [PATCH] updates
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/boot/dts/armada-388-clearfog.dts | 36 +++++-----
drivers/pci/host/pci-mvebu.c | 109 ++++++++++++++++++++++++++++--
drivers/pci/pcie/aspm.c | 2 +
drivers/pci/pcie/portdrv_core.c | 2 +
4 files changed, 126 insertions(+), 23 deletions(-)
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts
index db52a8e..df8557c 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
@@ -479,13 +479,13 @@
};
/*
-+#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x10460011
-MPP18: gpio ?
-MPP19: gpio ?
-MPP20: ua1:txd ?
++#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
+MPP18: gpio ? (pca9655 int?)
+MPP19: gpio ? (clkreq?)
+MPP20: gpio ? (sd0 detect)
MPP21: sd0:cmd x sd0
MPP22: gpio x mikro int
-MPP23: spi0:sck ?
+MPP23: gpio x switch irq
+#define A38x_CUSTOMER_BOARD_1_MPP24_31 0x22043333
MPP24: ua1:rxd x mikro rx
MPP25: ua1:txd x mikro tx
@@ -493,15 +493,15 @@ MPP26: i2c1:sck x mikro sck
MPP27: i2c1:sda x mikro sda
MPP28: sd0:clk x sd0
MPP29: gpio x mikro rst
-MPP30: ge1:txd2
-MPP31: ge1:txd3
+MPP30: ge1:txd2 ? (config)
+MPP31: ge1:txd3 ? (config)
+#define A38x_CUSTOMER_BOARD_1_MPP32_39 0x44400002
-MPP32: ge1:txctl
-MPP33: gpio ?
-MPP34: gpio x rear button
-MPP35: gpio ?
-MPP36: gpio ?
-MPP37: sd0:d3 ??
+MPP32: ge1:txctl ? (unused)
+MPP33: gpio ? (pic_com0)
+MPP34: gpio x rear button (pic_com1)
+MPP35: gpio ? (pic_com2)
+MPP36: gpio ? (unused)
+MPP37: sd0:d3 x sd0
MPP38: sd0:d0 x sd0
MPP39: sd0:d1 x sd0
+#define A38x_CUSTOMER_BOARD_1_MPP40_47 0x41144004
@@ -509,18 +509,18 @@ MPP40: sd0:d2 x sd0
MPP41: gpio x switch reset
MPP42: gpio ? sw1-1
MPP43: spi1:cs2 x mikro cs
-MPP44: sata3:prsnt
+MPP44: sata3:prsnt ? (unused)
MPP45: ref:clk_out0 ?
-MPP46: ref:clk_out1 ?
-MPP47: 4 ??
-+#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x45333333
+MPP46: ref:clk_out1 x switch clk
+MPP47: 4 ? (unused)
++#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x40333333
MPP48: tdm:pclk
MPP49: tdm:fsync
MPP50: tdm:drx
MPP51: tdm:dtx
MPP52: tdm:int
MPP53: tdm:rst
-MPP54: sd0:d3 ??
+MPP54: gpio ? (pwm)
MPP55: spi1:cs1 x slic
+#define A38x_CUSTOMER_BOARD_1_MPP56_63 0x00004444
MPP56: spi1:mosi x mikro mosi
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index 53b79c5..7980be0 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -51,7 +51,14 @@
PCIE_CONF_ADDR_EN)
#define PCIE_CONF_DATA_OFF 0x18fc
#define PCIE_MASK_OFF 0x1910
+#define PCIE_MASK_PM_PME BIT(28)
#define PCIE_MASK_ENABLE_INTS 0x0f000000
+#define PCIE_MASK_ERR_COR BIT(18)
+#define PCIE_MASK_ERR_NONFATAL BIT(17)
+#define PCIE_MASK_ERR_FATAL BIT(16)
+#define PCIE_MASK_FERR_DET BIT(10)
+#define PCIE_MASK_NFERR_DET BIT(9)
+#define PCIE_MASK_CORERR_DET BIT(8)
#define PCIE_CTRL_OFF 0x1a00
#define PCIE_CTRL_X1_MODE 0x0001
#define PCIE_STAT_OFF 0x1a04
@@ -455,6 +462,54 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
MVEBU_MBUS_NO_REMAP);
}
+static void mvebu_pcie_handle_irq_change(struct mvebu_pcie_port *port)
+{
+ u32 reg, old;
+ u16 devctl, rtctl;
+
+ /*
+ * Errors from downstream devices:
+ * bridge control register SERR: enables reception of errors
+ * Errors from this device, or received errors:
+ * command SERR: enables ERR_NONFATAL and ERR_FATAL messages
+ * => when enabled, these conditions also flag SERR in status register
+ * devctl CERE: enables ERR_CORR messages
+ * devctl NFERE: enables ERR_NONFATAL messages
+ * devctl FERE: enables ERR_FATAL messages
+ * Enabled messages then have three paths:
+ * 1. rtctl: enables system error indication
+ * 2. root error status register updated
+ * 3. root error command register: forwarding via MSI
+ */
+ old = mvebu_readl(port, PCIE_MASK_OFF);
+ reg = old & ~(PCIE_MASK_PM_PME | PCIE_MASK_FERR_DET |
+ PCIE_MASK_NFERR_DET | PCIE_MASK_CORERR_DET |
+ PCIE_MASK_ERR_COR | PCIE_MASK_ERR_NONFATAL |
+ PCIE_MASK_ERR_FATAL);
+
+ devctl = port->bridge.pcie_devctl;
+ if (devctl & PCI_EXP_DEVCTL_FERE)
+ reg |= PCIE_MASK_FERR_DET | PCIE_MASK_ERR_FATAL;
+ if (devctl & PCI_EXP_DEVCTL_NFERE)
+ reg |= PCIE_MASK_NFERR_DET | PCIE_MASK_ERR_NONFATAL;
+ if (devctl & PCI_EXP_DEVCTL_CERE)
+ reg |= PCIE_MASK_CORERR_DET | PCIE_MASK_ERR_COR;
+ if (port->bridge.command & PCI_COMMAND_SERR)
+ reg |= PCIE_MASK_FERR_DET | PCIE_MASK_NFERR_DET |
+ PCIE_MASK_ERR_FATAL | PCIE_MASK_ERR_NONFATAL;
+
+ if (!(port->bridge.bridgectrl & PCI_BRIDGE_CTL_SERR))
+ reg &= ~(PCIE_MASK_ERR_COR | PCIE_MASK_ERR_NONFATAL |
+ PCIE_MASK_ERR_FATAL);
+
+ rtctl = port->bridge.pcie_rtctl;
+ if (rtctl & PCI_EXP_RTCTL_PMEIE)
+ reg |= PCIE_MASK_PM_PME;
+
+ if (old != reg)
+ mvebu_writel(port, reg, PCIE_MASK_OFF);
+}
+
/*
* Initialize the configuration space of the PCI-to-PCI bridge
* associated with the given PCIe interface.
@@ -478,6 +533,7 @@ static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
/* Add capabilities */
bridge->status = PCI_STATUS_CAP_LIST;
+ bridge->bridgectrl = PCI_BRIDGE_CTL_SERR;
}
/*
@@ -550,7 +606,7 @@ static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
case PCI_INTERRUPT_LINE:
/* LINE PIN MIN_GNT MAX_LAT */
- *value = 0;
+ *value = bridge->bridgectrl << 16;
break;
case PCISWCAP_EXP_LIST_ID:
@@ -599,6 +655,16 @@ static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
*value = mvebu_readl(port, PCIE_RC_RTSTA);
break;
+ case 0x100 ... 0x128:
+ *value = mvebu_readl(port, where & ~3);
+ break;
+
+ case 0x100 + PCI_ERR_ROOT_COMMAND:
+ case 0x100 + PCI_ERR_ROOT_STATUS:
+ case 0x100 + PCI_ERR_ROOT_ERR_SRC:
+ *value = 0;
+ break;
+
/* PCIe requires the v2 fields to be hard-wired to zero */
case PCISWCAP_EXP_DEVCAP2:
case PCISWCAP_EXP_DEVCTL2:
@@ -629,7 +695,7 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
unsigned int where, int size, u32 value)
{
struct mvebu_sw_pci_bridge *bridge = &port->bridge;
- u32 mask, reg;
+ u32 mask, reg, old;
int err;
if (size == 4)
@@ -649,8 +715,7 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
switch (where & ~3) {
case PCI_COMMAND:
- {
- u32 old = bridge->command;
+ old = bridge->command;
if (!mvebu_has_ioport(port))
value &= ~PCI_COMMAND_IO;
@@ -660,8 +725,9 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
mvebu_pcie_handle_iobase_change(port);
if ((old ^ bridge->command) & PCI_COMMAND_MEMORY)
mvebu_pcie_handle_membase_change(port);
+ if ((old ^ bridge->command) & PCI_COMMAND_SERR)
+ mvebu_pcie_handle_irq_change(port);
break;
- }
case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
@@ -690,6 +756,17 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
mvebu_pcie_handle_iobase_change(port);
break;
+ case PCI_INTERRUPT_LINE:
+ value >>= 16;
+ old = bridge->bridgectrl;
+ /* PCIe only has three bits here */
+ bridge->bridgectrl = value & (PCI_BRIDGE_CTL_BUS_RESET |
+ PCI_BRIDGE_CTL_SERR |
+ PCI_BRIDGE_CTL_PARITY);
+ if ((old ^ bridge->bridgectrl) & PCI_BRIDGE_CTL_SERR)
+ mvebu_pcie_handle_irq_change(port);
+ break;
+
case PCI_PRIMARY_BUS:
bridge->primary_bus = value & 0xff;
bridge->secondary_bus = (value >> 8) & 0xff;
@@ -699,6 +776,14 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
break;
case PCISWCAP_EXP_DEVCTL:
+ old = bridge->pcie_devctl;
+ bridge->pcie_devctl = value & (PCI_EXP_DEVCTL_FERE |
+ PCI_EXP_DEVCTL_NFERE |
+ PCI_EXP_DEVCTL_CERE |
+ PCI_EXP_DEVCTL_URRE);
+ if (bridge->pcie_devctl ^ old)
+ mvebu_pcie_handle_irq_change(port);
+
/*
* Armada370 data says these bits must always
* be zero when in root complex mode.
@@ -739,10 +824,24 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
break;
+ case PCISWCAP_EXP_RTCTL:
+ old = bridge->pcie_rtctl;
+ bridge->pcie_rtctl = value & (PCI_EXP_RTCTL_SECEE |
+ PCI_EXP_RTCTL_SENFEE |
+ PCI_EXP_RTCTL_SEFEE |
+ PCI_EXP_RTCTL_PMEIE);
+ if (bridge->pcie_rtctl ^ old)
+ mvebu_pcie_handle_irq_change(port);
+ break;
+
case PCISWCAP_EXP_RTSTA:
mvebu_writel(port, value, PCIE_RC_RTSTA);
break;
+ case 0x100 ... 0x128:
+ mvebu_writel(port, value, where & ~3);
+ break;
+
default:
break;
}
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 317e355..f1de057 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -356,8 +356,10 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
/* Get upstream/downstream components' register state */
pcie_get_aspm_reg(parent, &upreg);
+dev_info(&parent->dev, "up support %x enabled %x\n", upreg.support, upreg.enabled);
child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
pcie_get_aspm_reg(child, &dwreg);
+dev_info(&parent->dev, "dn support %x enabled %x\n", dwreg.support, dwreg.enabled);
/*
* Setup L0s state
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index 88122dc..bd14993 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -372,6 +372,7 @@ int pcie_port_device_register(struct pci_dev *dev)
/* Get and check PCI Express port services */
capabilities = get_port_device_capability(dev);
+dev_info(&dev->dev, "PCIe capabilities: 0x%x\n", capabilities);
if (!capabilities)
return 0;
@@ -384,6 +385,7 @@ int pcie_port_device_register(struct pci_dev *dev)
* if that is to be used.
*/
status = init_service_irqs(dev, irqs, capabilities);
+dev_info(&dev->dev, "init_service_irqs: %d\n", status);
if (status) {
capabilities &= PCIE_PORT_SERVICE_VC | PCIE_PORT_SERVICE_HP;
if (!capabilities)
--
1.9.1

67
patch/kernel/marvell-dev/check_and_merge/0041-implement-slot-capabilities-SSPL.patch Normal file
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@ -0,0 +1,67 @@
From ae07b208fe4e228068282ad76cfd69ab9e96dc9f Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Mon, 28 Dec 2015 13:55:13 +0100
Subject: [PATCH] implement slot capabilities (SSPL)
---
drivers/pci/host/pci-mvebu.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index 7980be0..0e9b820 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -65,6 +65,12 @@
#define PCIE_STAT_BUS 0xff00
#define PCIE_STAT_DEV 0x1f0000
#define PCIE_STAT_LINK_DOWN BIT(0)
+#define PCIE_SSPL 0x1a0c
+#define PCIE_SSPL_MSGEN BIT(14)
+#define PCIE_SSPL_SPLS(x) (((x) & 3) << 8)
+#define PCIE_SSPL_SPLS_VAL(x) (((x) >> 8) & 3)
+#define PCIE_SSPL_SPLV(x) ((x) & 0xff)
+#define PCIE_SSPL_SPLV_VAL(x) ((x) & 0xff)
#define PCIE_RC_RTSTA 0x1a14
#define PCIE_DEBUG_CTRL 0x1a60
#define PCIE_DEBUG_SOFT_RESET BIT(20)
@@ -119,7 +125,6 @@ struct mvebu_sw_pci_bridge {
u16 bridgectrl;
/* PCI express capability */
- u32 pcie_sltcap;
u16 pcie_devctl;
u16 pcie_rtctl;
};
@@ -640,8 +645,12 @@ static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
break;
case PCISWCAP_EXP_SLTCAP:
- *value = bridge->pcie_sltcap;
+ {
+ u32 tmp = mvebu_readl(port, PCIE_SSPL);
+ *value = PCIE_SSPL_SPLS_VAL(tmp) << 15 |
+ PCIE_SSPL_SPLV_VAL(tmp) << 7;
break;
+ }
case PCISWCAP_EXP_SLTCTL:
*value = PCI_EXP_SLTSTA_PDS << 16;
@@ -824,6 +833,15 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
break;
+ case PCISWCAP_EXP_SLTCAP:
+ {
+ u32 sspl = PCIE_SSPL_SPLV((value & PCI_EXP_SLTCAP_SPLV) >> 7) |
+ PCIE_SSPL_SPLS((value & PCI_EXP_SLTCAP_SPLS) >> 15) |
+ PCIE_SSPL_MSGEN;
+ mvebu_writel(port, sspl, PCIE_SSPL);
+ break;
+ }
+
case PCISWCAP_EXP_RTCTL:
old = bridge->pcie_rtctl;
bridge->pcie_rtctl = value & (PCI_EXP_RTCTL_SECEE |
--
1.9.1

47
patch/kernel/marvell-dev/check_and_merge/0042-sfp-reduce-debug-to-debug-level.patch Normal file
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@ -0,0 +1,47 @@
From d097cf47631054f868fefaab250278737cb68f23 Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Mon, 28 Dec 2015 14:00:26 +0100
Subject: [PATCH] sfp: reduce debug to debug level
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
drivers/net/phy/sfp.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/net/phy/sfp.c b/drivers/net/phy/sfp.c
index 7bb742a..feb5f70 100644
--- a/drivers/net/phy/sfp.c
+++ b/drivers/net/phy/sfp.c
@@ -425,14 +425,16 @@ static const char *sfp_encoding(unsigned int encoding)
/* Helpers */
static void sfp_module_tx_disable(struct sfp *sfp)
{
-dev_info(sfp->dev, "tx disable %u -> %u\n", sfp->state & SFP_F_TX_DISABLE ? 1 : 0, 1);
+ dev_dbg(sfp->dev, "tx disable %u -> %u\n",
+ sfp->state & SFP_F_TX_DISABLE ? 1 : 0, 1);
sfp->state |= SFP_F_TX_DISABLE;
sfp_set_state(sfp, sfp->state);
}
static void sfp_module_tx_enable(struct sfp *sfp)
{
-dev_info(sfp->dev, "tx disable %u -> %u\n", sfp->state & SFP_F_TX_DISABLE ? 1 : 0, 0);
+ dev_dbg(sfp->dev, "tx disable %u -> %u\n",
+ sfp->state & SFP_F_TX_DISABLE ? 1 : 0, 0);
sfp->state &= ~SFP_F_TX_DISABLE;
sfp_set_state(sfp, sfp->state);
}
@@ -972,8 +974,8 @@ static void sfp_check_state(struct sfp *sfp)
for (i = 0; i < GPIO_MAX; i++)
if (changed & BIT(i))
- dev_info(sfp->dev, "%s %u -> %u\n", gpio_of_names[i],
- !!(sfp->state & BIT(i)), !!(state & BIT(i)));
+ dev_dbg(sfp->dev, "%s %u -> %u\n", gpio_of_names[i],
+ !!(sfp->state & BIT(i)), !!(state & BIT(i)));
state |= sfp->state & (SFP_F_TX_DISABLE | SFP_F_RATE_SELECT);
sfp->state = state;
--
1.9.1

55
patch/kernel/marvell-dev/check_and_merge/0043-sfp-removal-of-defs.patch Normal file
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@ -0,0 +1,55 @@
From a816442ff796080b1856222f1f6adf0836ebc84f Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Mon, 28 Dec 2015 14:00:25 +0100
Subject: [PATCH] sfp: removal of defs
---
include/linux/sfp.h | 32 --------------------------------
1 file changed, 32 deletions(-)
diff --git a/include/linux/sfp.h b/include/linux/sfp.h
index 15be090..58c03fa 100644
--- a/include/linux/sfp.h
+++ b/include/linux/sfp.h
@@ -188,38 +188,6 @@ struct __packed sfp_eeprom_id {
/* SFP EEPROM registers */
enum {
- SFP_PHYS_ID = 0x00,
- SFP_PHYS_EXT_ID = 0x01,
- SFP_CONNECTOR = 0x02,
- SFP_COMPLIANCE = 0x03,
- SFP_ENCODING = 0x0b,
- SFP_BR_NOMINAL = 0x0c,
- SFP_RATE_ID = 0x0d,
- SFP_LINK_LEN_SM_KM = 0x0e,
- SFP_LINK_LEN_SM_100M = 0x0f,
- SFP_LINK_LEN_50UM_OM2_10M = 0x10,
- SFP_LINK_LEN_62_5UM_OM1_10M = 0x11,
- SFP_LINK_LEN_COPPER_1M = 0x12,
- SFP_LINK_LEN_50UM_OM4_10M = 0x12,
- SFP_LINK_LEN_50UM_OM3_10M = 0x13,
- SFP_VENDOR_NAME = 0x14,
- SFP_VENDOR_OUI = 0x25,
- SFP_VENDOR_PN = 0x28,
- SFP_VENDOR_REV = 0x38,
- SFP_OPTICAL_WAVELENGTH_MSB = 0x3c,
- SFP_OPTICAL_WAVELENGTH_LSB = 0x3d,
- SFP_CABLE_SPEC = 0x3c,
- SFP_CC_BASE = 0x3f,
- SFP_OPTIONS = 0x40, /* 2 bytes, MSB, LSB */
- SFP_BR_MAX = 0x42,
- SFP_BR_MIN = 0x43,
- SFP_VENDOR_SN = 0x44,
- SFP_DATECODE = 0x54,
- SFP_DIAGMON = 0x5c,
- SFP_ENHOPTS = 0x5d,
- SFP_SFF8472_COMPLIANCE = 0x5e,
- SFP_CC_EXT = 0x5f,
-
SFP_PHYS_ID_SFP = 0x03,
SFP_PHYS_EXT_ID_SFP = 0x04,
SFP_CONNECTOR_UNSPEC = 0x00,
--
1.9.1

48
patch/kernel/marvell-dev/check_and_merge/0044-gpio-report-all-gpios-in-debugfs.patch Normal file
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@ -0,0 +1,48 @@
From d737953ac85dde91eeb0340b5ac999eb48b73b04 Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Mon, 28 Dec 2015 13:55:13 +0100
Subject: [PATCH] gpio: report all gpios in debugfs
---
drivers/gpio/gpio-mvebu.c | 4 ++--
drivers/gpio/gpiolib.c | 3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index d428b97..fe172b7 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -514,8 +514,8 @@ static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
bool is_out;
label = gpiochip_is_requested(chip, i);
- if (!label)
- continue;
+// if (!label)
+// continue;
msk = 1 << i;
is_out = !(io_conf & msk);
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 4e4c308..96ac8c1 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -2438,13 +2438,14 @@ static void gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
int is_irq;
for (i = 0; i < chip->ngpio; i++, gpio++, gdesc++) {
- if (!test_bit(FLAG_REQUESTED, &gdesc->flags)) {
+/* if (!test_bit(FLAG_REQUESTED, &gdesc->flags)) {
if (gdesc->name) {
seq_printf(s, " gpio-%-3d (%-20.20s)\n",
gpio, gdesc->name);
}
continue;
}
+*/
gpiod_get_direction(gdesc);
is_out = test_bit(FLAG_IS_OUT, &gdesc->flags);
--
1.9.1