From 55641dffc58aaf6ce71b40fac7d4e8512bd534de Mon Sep 17 00:00:00 2001 From: Igor Pecovnik Date: Sun, 24 Nov 2019 19:53:28 +0100 Subject: [PATCH 1/5] Adding CPU_MIN variable back to rockchip64 family config --- config/sources/families/include/rockchip64_common.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/config/sources/families/include/rockchip64_common.inc b/config/sources/families/include/rockchip64_common.inc index a48b4fb05..65b0e9e2f 100644 --- a/config/sources/families/include/rockchip64_common.inc +++ b/config/sources/families/include/rockchip64_common.inc @@ -15,6 +15,7 @@ ATFBRANCH='branch:rockchip' ATF_USE_GCC='> 6.3' GOVERNOR="ondemand" CPUMAX="2016000" +CPUMIN="600000" if [[ $BOOTCONFIG == *3328* ]]; then From 8f4b6bfc99d972f08d154ca3bc2835eaaf65abe7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Igor=20Pe=C4=8Dovnik?= Date: Sun, 24 Nov 2019 19:57:57 +0100 Subject: [PATCH 2/5] Create patches directory structure under USERPATCHES_PATH (#1628) Closes [AR-74] --- lib/general.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/lib/general.sh b/lib/general.sh index d19b8d759..707463de9 100644 --- a/lib/general.sh +++ b/lib/general.sh @@ -808,6 +808,9 @@ prepare_host() fi mkdir -p $DEST/debs-beta/extra $DEST/debs/extra $DEST/{config,debug,patch} $USERPATCHES_PATH/overlay $SRC/cache/{sources,toolchains,utility,rootfs} $SRC/.tmp + # create patches directory structure under USERPATCHES_PATH + find $SRC/patch -maxdepth 2 -type d ! -name . | sed "s%/.*patch%/$USERPATCHES_PATH%" | xargs mkdir -p + display_alert "Checking for external GCC compilers" "" "info" # download external Linaro compiler and missing special dependencies since they are needed for certain sources From 924c2140c2d24c52b45576b5adbdcf12c7b51bef Mon Sep 17 00:00:00 2001 From: Piotr Szczepanik Date: Sun, 24 Nov 2019 21:21:48 +0100 Subject: [PATCH 3/5] Added a lot of net modules in Rock Pi S kernel config (#1629) --- config/kernel/linux-rockpis-legacy.config | 599 +++++++++++++++++++--- 1 file changed, 524 insertions(+), 75 deletions(-) diff --git a/config/kernel/linux-rockpis-legacy.config b/config/kernel/linux-rockpis-legacy.config index dadbf160e..b01defda2 100644 --- a/config/kernel/linux-rockpis-legacy.config +++ b/config/kernel/linux-rockpis-legacy.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 4.4.189 Kernel Configuration +# Linux/arm64 4.4.198 Kernel Configuration # CONFIG_ARM64=y CONFIG_64BIT=y @@ -543,6 +543,7 @@ CONFIG_CPUFREQ_DT=y CONFIG_ARM_ROCKCHIP_CPUFREQ=y CONFIG_NET=y CONFIG_COMPAT_NETLINK_MESSAGES=y +CONFIG_NET_INGRESS=y # # Networking options @@ -550,76 +551,456 @@ CONFIG_COMPAT_NETLINK_MESSAGES=y CONFIG_PACKET=y # CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y -# CONFIG_UNIX_DIAG is not set +CONFIG_UNIX_DIAG=y CONFIG_XFRM=y CONFIG_XFRM_ALGO=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -CONFIG_NET_KEY=y -# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_XFRM_USER=y +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_MIGRATE=y +CONFIG_XFRM_STATISTICS=y +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y -CONFIG_WIREGUARD=m -# CONFIG_WIREGUARD_DEBUG is not set -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -# CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_FIB_TRIE_STATS=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_ROUTE_CLASSID=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IP_TUNNEL=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m CONFIG_NET_UDP_TUNNEL=m -# CONFIG_NET_FOU is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set +CONFIG_NET_FOU=m +# CONFIG_NET_FOU_IP_TUNNELS is not set +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=m +CONFIG_INET_XFRM_MODE_TUNNEL=m +CONFIG_INET_XFRM_MODE_BEET=m +CONFIG_INET_LRO=m +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +CONFIG_INET_UDP_DIAG=m +# CONFIG_INET_DIAG_DESTROY is not set +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CUBIC=m +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_CDG=m +CONFIG_DEFAULT_RENO=y +CONFIG_DEFAULT_TCP_CONG="reno" +CONFIG_TCP_MD5SIG=y CONFIG_IPV6=y # CONFIG_IPV6_ROUTER_PREF is not set # CONFIG_IPV6_OPTIMISTIC_DAD is not set -# CONFIG_INET6_AH is not set -# CONFIG_INET6_ESP is not set -# CONFIG_INET6_IPCOMP is not set -# CONFIG_IPV6_MIP6 is not set -# CONFIG_IPV6_ILA is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET6_XFRM_MODE_TUNNEL is not set -# CONFIG_INET6_XFRM_MODE_BEET is not set -# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set -# CONFIG_IPV6_SIT is not set -# CONFIG_IPV6_TUNNEL is not set -# CONFIG_IPV6_GRE is not set -# CONFIG_IPV6_MULTIPLE_TABLES is not set +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_ILA=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_GRE=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y # CONFIG_IPV6_MROUTE is not set # CONFIG_ANDROID_PARANOID_NETWORK is not set -# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETWORK_SECMARK=y CONFIG_NET_PTP_CLASSIFY=y -# CONFIG_NETWORK_PHY_TIMESTAMPING is not set -# CONFIG_NETFILTER is not set +CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=m + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_ACCT=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_COMMON=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_LABELS=y +CONFIG_NF_CT_PROTO_DCCP=m +CONFIG_NF_CT_PROTO_GRE=m +CONFIG_NF_CT_PROTO_SCTP=m +CONFIG_NF_CT_PROTO_UDPLITE=m +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_BROADCAST=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NF_NAT=m +CONFIG_NF_NAT_NEEDED=y +CONFIG_NF_NAT_PROTO_DCCP=m +CONFIG_NF_NAT_PROTO_UDPLITE=m +CONFIG_NF_NAT_PROTO_SCTP=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_SIP=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_NAT_REDIRECT=m +CONFIG_NETFILTER_SYNPROXY=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=m +CONFIG_NF_TABLES_NETDEV=m +CONFIG_NFT_EXTHDR=m +CONFIG_NFT_META=m +CONFIG_NFT_CT=m +CONFIG_NFT_RBTREE=m +CONFIG_NFT_HASH=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_REJECT_INET=m +CONFIG_NFT_COMPAT=m +CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m +CONFIG_NETFILTER_XT_SET=m + +# +# Xtables targets +# +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_NAT=m +CONFIG_NETFILTER_XT_TARGET_NETMAP=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_REDIRECT=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_QUOTA2=m +CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_MAX=256 +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS SH scheduler +# +CONFIG_IP_VS_SH_TAB_BITS=8 + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_NFCT=y +CONFIG_IP_VS_PE_SIP=m + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_CONNTRACK_IPV4=m +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +CONFIG_NF_TABLES_IPV4=m +CONFIG_NFT_CHAIN_ROUTE_IPV4=m +CONFIG_NFT_REJECT_IPV4=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NF_TABLES_ARP=m +CONFIG_NF_DUP_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_REJECT_IPV4=m +CONFIG_NF_NAT_IPV4=m +CONFIG_NFT_CHAIN_NAT_IPV4=m +CONFIG_NF_NAT_MASQUERADE_IPV4=m +CONFIG_NFT_MASQ_IPV4=m +CONFIG_NFT_REDIR_IPV4=m +CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_PROTO_GRE=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV6=m +CONFIG_NF_CONNTRACK_IPV6=m +CONFIG_NF_TABLES_IPV6=m +CONFIG_NFT_CHAIN_ROUTE_IPV6=m +CONFIG_NFT_REJECT_IPV6=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NF_DUP_IPV6=m +CONFIG_NF_REJECT_IPV6=m +CONFIG_NF_LOG_IPV6=m +CONFIG_NF_NAT_IPV6=m +CONFIG_NFT_CHAIN_NAT_IPV6=m +CONFIG_NF_NAT_MASQUERADE_IPV6=m +CONFIG_NFT_MASQ_IPV6=m +CONFIG_NFT_REDIR_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_LOG_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m # CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_OBJCNT is not set +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set +CONFIG_SCTP_COOKIE_HMAC_MD5=y +# CONFIG_SCTP_COOKIE_HMAC_SHA1 is not set # CONFIG_RDS is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set -# CONFIG_L2TP is not set -# CONFIG_BRIDGE is not set +CONFIG_L2TP=m +# CONFIG_L2TP_DEBUGFS is not set +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_STP=m +CONFIG_GARP=m +CONFIG_MRP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_BRIDGE_VLAN_FILTERING=y CONFIG_HAVE_NET_DSA=y -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set +CONFIG_NET_DSA=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y # CONFIG_DECNET is not set +CONFIG_LLC=m # CONFIG_LLC2 is not set # CONFIG_IPX is not set # CONFIG_ATALK is not set @@ -628,25 +1009,82 @@ CONFIG_HAVE_NET_DSA=y # CONFIG_PHONET is not set # CONFIG_6LOWPAN is not set # CONFIG_IEEE802154 is not set -# CONFIG_NET_SCHED is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=y +CONFIG_NET_SCH_FQ_CODEL=y +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_PLUG=m + +# +# Classification +# +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_FW is not set +CONFIG_NET_CLS_U32=y +# CONFIG_CLS_U32_PERF is not set +CONFIG_CLS_U32_MARK=y +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_FLOW is not set +CONFIG_NET_CLS_CGROUP=y +# CONFIG_NET_CLS_BPF is not set +# CONFIG_NET_CLS_FLOWER is not set +# CONFIG_NET_EMATCH is not set +# CONFIG_NET_CLS_ACT is not set +# CONFIG_NET_CLS_IND is not set +CONFIG_NET_SCH_FIFO=y # CONFIG_DCB is not set -CONFIG_DNS_RESOLVER=m -# CONFIG_BATMAN_ADV is not set -# CONFIG_OPENVSWITCH is not set -# CONFIG_VSOCKETS is not set -# CONFIG_NETLINK_DIAG is not set -# CONFIG_MPLS is not set -# CONFIG_HSR is not set -# CONFIG_NET_SWITCHDEV is not set -# CONFIG_NET_L3_MASTER_DEV is not set +CONFIG_DNS_RESOLVER=y +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_BLA=y +CONFIG_BATMAN_ADV_DAT=y +CONFIG_BATMAN_ADV_NC=y +CONFIG_BATMAN_ADV_MCAST=y +# CONFIG_BATMAN_ADV_DEBUG is not set +CONFIG_OPENVSWITCH=m +CONFIG_OPENVSWITCH_GRE=m +CONFIG_VSOCKETS=m +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +# CONFIG_MPLS_ROUTING is not set +CONFIG_HSR=m +CONFIG_NET_SWITCHDEV=y +CONFIG_NET_L3_MASTER_DEV=y CONFIG_RPS=y CONFIG_RFS_ACCEL=y CONFIG_XPS=y -# CONFIG_CGROUP_NET_PRIO is not set -# CONFIG_CGROUP_NET_CLASSID is not set +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_NET_CLASSID=y CONFIG_NET_RX_BUSY_POLL=y CONFIG_BQL=y -# CONFIG_BPF_JIT is not set +CONFIG_BPF_JIT=y CONFIG_NET_FLOW_LIMIT=y # @@ -680,6 +1118,7 @@ CONFIG_BT_HCIVHCI=y CONFIG_BT_MRVL=y CONFIG_BT_MRVL_SDIO=y # CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y CONFIG_WIRELESS=y CONFIG_WIRELESS_EXT=y CONFIG_WEXT_CORE=y @@ -718,9 +1157,11 @@ CONFIG_RFKILL_LEDS=y # CONFIG_RFKILL_GPIO is not set # CONFIG_NET_9P is not set # CONFIG_CAIF is not set -# CONFIG_CEPH_LIB is not set +CONFIG_CEPH_LIB=m +# CONFIG_CEPH_LIB_PRETTYDEBUG is not set +# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set # CONFIG_NFC is not set -# CONFIG_LWTUNNEL is not set +CONFIG_LWTUNNEL=y CONFIG_DST_CACHE=y CONFIG_HAVE_BPF_JIT=y CONFIG_HAVE_EBPF_JIT=y @@ -934,7 +1375,13 @@ CONFIG_MII=y # Distributed Switch Architecture drivers # # CONFIG_NET_DSA_MV88E6XXX is not set +# CONFIG_NET_DSA_MV88E6060 is not set # CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set +# CONFIG_NET_DSA_MV88E6131 is not set +# CONFIG_NET_DSA_MV88E6123_61_65 is not set +# CONFIG_NET_DSA_MV88E6171 is not set +# CONFIG_NET_DSA_MV88E6352 is not set +# CONFIG_NET_DSA_BCM_SF2 is not set CONFIG_ETHERNET=y # CONFIG_ALTERA_TSE is not set CONFIG_NET_VENDOR_AMD=y @@ -1092,8 +1539,6 @@ CONFIG_RTL8723DS=y # # CONFIG_SSV6051 is not set # CONFIG_WL_TI is not set -CONFIG_RTL8822BU=m -CONFIG_RTL8812AU=m # CONFIG_ZD1211RW is not set # CONFIG_MWIFIEX is not set # CONFIG_CW1200 is not set @@ -1103,6 +1548,7 @@ CONFIG_RTL8812AU=m # Enable WiMAX (Networking options) to see the WiMAX drivers # # CONFIG_WAN is not set +# CONFIG_LTE is not set # CONFIG_ISDN is not set # CONFIG_NVM is not set @@ -1205,6 +1651,7 @@ CONFIG_TOUCHSCREEN_ADS7846=m # CONFIG_TOUCHSCREEN_FT6236 is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GOODIX is not set +# CONFIG_TOUCHSCREEN_GSLX6801 is not set # CONFIG_TOUCHSCREEN_GSLX680A is not set # CONFIG_TOUCHSCREEN_GSLX680_D708 is not set # CONFIG_TOUCHSCREEN_GSLX680_PAD is not set @@ -1476,10 +1923,7 @@ CONFIG_PPS=y # PTP clock support # CONFIG_PTP_1588_CLOCK=y - -# -# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. -# +# CONFIG_DP83640_PHY is not set CONFIG_PINCTRL=y # @@ -2400,7 +2844,6 @@ CONFIG_USB_SERIAL_DEBUG=m # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set # CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set # CONFIG_USB_LED is not set @@ -3288,6 +3731,7 @@ CONFIG_RK_FLASH=y # CONFIG_RK_NANDC_NAND=y CONFIG_RK_SFC_NAND=y +# CONFIG_RK_SFC_NAND_MTD is not set CONFIG_RK_SFC_NOR=y # CONFIG_RK_SFC_NOR_MTD is not set # CONFIG_RK_NAND is not set @@ -3674,6 +4118,7 @@ CONFIG_TRACING_SUPPORT=y # CONFIG_TEST_KSTRTOX is not set # CONFIG_TEST_PRINTF is not set # CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set # CONFIG_DMA_API_DEBUG is not set # CONFIG_TEST_LKM is not set # CONFIG_TEST_USER_COPY is not set @@ -3935,6 +4380,10 @@ CONFIG_GENERIC_ALLOCATOR=y CONFIG_REED_SOLOMON=y CONFIG_REED_SOLOMON_ENC8=y CONFIG_REED_SOLOMON_DEC8=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_DMA=y From d12249d69f3ea75478dc3c4014a7bda86202fe29 Mon Sep 17 00:00:00 2001 From: Igor Pecovnik Date: Sun, 24 Nov 2019 21:54:16 +0100 Subject: [PATCH 4/5] Adjust Orangepi RK3399 board name --- config/boards/orangepi-rk3399.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/boards/orangepi-rk3399.conf b/config/boards/orangepi-rk3399.conf index 2328a4414..7b88740a2 100644 --- a/config/boards/orangepi-rk3399.conf +++ b/config/boards/orangepi-rk3399.conf @@ -1,5 +1,5 @@ # RK3399 hexa core 2G/4GB RAM SoC GBE eMMC mPCI USB3 WiFi/BT -BOARD_NAME="OrangePiRK3399" +BOARD_NAME="Orange Pi RK3399" BOARDFAMILY="rk3399" BOOTCONFIG="orangepi-rk3399_defconfig" KERNEL_TARGET="legacy,current,dev" From 1c9ef0872bfdda69e66de11f0e97b6b43218f73c Mon Sep 17 00:00:00 2001 From: Piotr Szczepanik Date: Sun, 24 Nov 2019 22:07:46 +0100 Subject: [PATCH 5/5] Multiple bootloader creation options for rk3399 (#1614) * Updated rockchip64-dev to u-boot v2019.10 and BL31 v1.30 (rk3399 boards) * Updated rk3399 to u-boot v2019.10 and BL31 v1.30 * Revert changes to renegade u-boot patches * Moved renegade u-boot patches into board dir * Added debug info for RockPro64 and switched sdmmc to fifo-mode * Disabled regulators in SPL for RockPro64 * Re-enabled sd vcc regulator in SPL for RockPro64 * Some device tree and config changes for OrangePi RK3399 * Fixed Rock Pi 4A's $BOOTCONFIG * Let some boards use mainline atf instead of the one in rkbin For example, roc-rk3399-pc can just boot the kernel using the mainline atf. * Add roc-rk3399-pc * Fixed reset in mainline ATF * Attached ATF version to v2.2 tag * WIP: sdmmc fifo-mode in SPL only * Renamed source config files * Reverted changes to rockchip64 sources config * Reverted patch moves * Add missing trust.ini patch to rk3399 u-boot * Reinstated tpl/spl patches in rk3399 family * Added $RKBIN_DIR prefix in rk3399 sources * Add demonstration of boards bootloader assignment in rk3399 --- config/boards/roc-rk3399-pc.csc | 14 + .../families/include/rockchip64_common.inc | 17 +- config/sources/families/rk3399.conf | 93 +- config/templates/customize-image.sh.template | 2 +- patch/atf/atf-rk3399/fix-reset-in-v2.2.patch | 56 + ...switch-power-domains-on-before-reset.patch | 63 + .../kernel/rk3399-default/roc-rk3399-pc.patch | 1567 +++++++++++++++++ patch/kernel/rk3399-legacy/firefly-dts.patch | 2 +- .../board-roc-rk3399-pc-fix-regulator.patch | 24 + .../u-boot/u-boot-rk3399/add-trust-ini.patch | 21 + .../rk3399-disable-iram-reservation.patch | 191 ++ .../rk3399-update-spl-max-size.patch | 59 + .../rk3399-update-spl-stack-r-addr.patch | 255 +++ .../sdmmc-force-fifo-mode-in-spl.patch | 22 + 14 files changed, 2371 insertions(+), 15 deletions(-) create mode 100644 config/boards/roc-rk3399-pc.csc create mode 100644 patch/atf/atf-rk3399/fix-reset-in-v2.2.patch create mode 100644 patch/atf/atf-rk3399/switch-power-domains-on-before-reset.patch create mode 100644 patch/kernel/rk3399-default/roc-rk3399-pc.patch create mode 100644 patch/kernel/rockchip64-dev/board-roc-rk3399-pc-fix-regulator.patch create mode 100644 patch/u-boot/u-boot-rk3399/add-trust-ini.patch create mode 100644 patch/u-boot/u-boot-rk3399/rk3399-disable-iram-reservation.patch create mode 100644 patch/u-boot/u-boot-rk3399/rk3399-update-spl-max-size.patch create mode 100644 patch/u-boot/u-boot-rk3399/rk3399-update-spl-stack-r-addr.patch create mode 100644 patch/u-boot/u-boot-rk3399/sdmmc-force-fifo-mode-in-spl.patch diff --git a/config/boards/roc-rk3399-pc.csc b/config/boards/roc-rk3399-pc.csc new file mode 100644 index 000000000..a2dd3cab7 --- /dev/null +++ b/config/boards/roc-rk3399-pc.csc @@ -0,0 +1,14 @@ +# RK3399 hexa core 4GB DDR4 SoC eMMC GBE USB3 +BOARD_NAME="ROC-RK3399-PC" +BOARDFAMILY="rk3399" +BOOTCONFIG="roc-rk3399-pc_defconfig" +# +MODULES="" +MODULES_NEXT="" +# +KERNEL_TARGET="default,dev" +CLI_TARGET="buster,bionic:default" +DESKTOP_TARGET="buster,bionic:default" +# +CLI_BETA_TARGET="buster,bionic:dev" +DESKTOP_BETA_TARGET="" diff --git a/config/sources/families/include/rockchip64_common.inc b/config/sources/families/include/rockchip64_common.inc index 65b0e9e2f..08d363edb 100644 --- a/config/sources/families/include/rockchip64_common.inc +++ b/config/sources/families/include/rockchip64_common.inc @@ -18,8 +18,8 @@ CPUMAX="2016000" CPUMIN="600000" if [[ $BOOTCONFIG == *3328* ]]; then - - ATF_TARGET_MAP='PLAT=rk322xh DEBUG=1 bl31;;trust.bin' + + ATF_TARGET_MAP='PLAT=rk322xh DEBUG=1 bl31;;trust.bin' CPUMAX="1390000" elif [[ $BOARD == rockpro64 ]] || [[ $BOARD == rockpi-4* ]]; then @@ -55,9 +55,9 @@ case $BRANCH in KERNELPATCHDIR='rockchip64-'$BRANCH LINUXFAMILY=rockchip64 LINUXCONFIG='linux-rockchip64-'$BRANCH - + ;; - + esac @@ -106,12 +106,13 @@ atf_custom_postprocess() family_tweaks() { + [[ $BOARD == firefly-rk3399 ]] && echo "fdtfile=rockchip/rk3399-firefly.dtb" >> $SDCARD/boot/armbianEnv.txt [[ $BOARD == nanopct4 ]] && echo "fdtfile=rockchip/rk3399-nanopc-t4.dtb" >> $SDCARD/boot/armbianEnv.txt [[ $BOARD == nanopim4 ]] && echo "fdtfile=rockchip/rk3399-nanopi-m4.dtb" >> $SDCARD/boot/armbianEnv.txt [[ $BOARD == nanopim4v2 ]] && echo "fdtfile=rockchip/rk3399-nanopi-m4.dtb" >> $SDCARD/boot/armbianEnv.txt [[ $BOARD == nanopineo4 ]] && echo "fdtfile=rockchip/rk3399-nanopi-neo4.dtb" >> $SDCARD/boot/armbianEnv.txt [[ $BOARD == orangepi-rk3399 ]] && echo "fdtfile=rockchip/rk3399-orangepi.dtb" >> $SDCARD/boot/armbianEnv.txt - [[ $BOARD == firefly-rk3399 ]] && echo "fdtfile=rockchip/rk3399-firefly.dtb" >> $SDCARD/boot/armbianEnv.txt + [[ $BOARD == roc-rk3399-pc ]] && echo "fdtfile=rockchip/rk3399-roc-pc.dtb" >> $SDCARD/boot/armbianEnv.txt if [[ $BOARD == z28pro ]]; then @@ -121,8 +122,8 @@ family_tweaks() elif [[ -f $SDCARD/lib/systemd/system/rk3399-bluetooth.service ]]; then # install and enable Bluetooth - chroot $SDCARD /bin/bash -c "apt-get -y -qq install rfkill bluetooth bluez bluez-tools" - chroot $SDCARD /bin/bash -c "systemctl --no-reload enable rk3399-bluetooth.service >/dev/null 2>&1" + chroot $SDCARD /bin/bash -c "apt-get -y -qq install rfkill bluetooth bluez bluez-tools" + chroot $SDCARD /bin/bash -c "systemctl --no-reload enable rk3399-bluetooth.service >/dev/null 2>&1" fi @@ -141,7 +142,7 @@ family_tweaks_bsp() install -m 755 $SRC/packages/bsp/rk3328/z28pro/start_bt.sh $destination/usr/local/bin cp $SRC/packages/bsp/rk3328/z28pro/z28pro-bluetooth.service $destination/lib/systemd/system/ - elif [[ $BOARD == rockpi-4b || $BOARD == nanop* || $BOARD == orangepi* || BOARD == firefly* ]]; then + elif [[ $BOARD == rockpi-4b || $BOARD == nanop* || $BOARD == orangepi* || $BOARD == firefly* || $BOARD == roc-rk3399-pc ]]; then # Bluetooth for most of others install -m 755 $SRC/packages/bsp/rk3399/brcm_patchram_plus_rk3399 $destination/usr/bin diff --git a/config/sources/families/rk3399.conf b/config/sources/families/rk3399.conf index 32a0956f3..b1c2a8a97 100644 --- a/config/sources/families/rk3399.conf +++ b/config/sources/families/rk3399.conf @@ -16,11 +16,94 @@ case $BRANCH in esac +RKBIN_DIR="$SRC/cache/sources/rkbin-tools" + +if [[ $BOARD == roc-rk3399-pc ]]; then + + BOOT_USE_MAINLINE_ATF=yes + +elif [[ $BOARD == rockpi-4* ]]; then + + BOOT_USE_TPL_SPL_BLOB=yes + BL31_BLOB='rk33/rk3399_bl31_v1.30.elf' + +elif [[ $BOARD == nanopim4v2 ]]; then + + BOOT_USE_BLOBS=yes + DDR_BLOB='rk33/rk3399_ddr_933MHz_v1.24.bin' + MINILOADER_BLOB='rk33/rk3399_miniloader_v1.19.bin' + BL31_BLOB='rk33/rk3399_bl31_v1.30.elf' + +else + + BOOT_USE_BLOBS=yes + DDR_BLOB='rk33/rk3399_ddr_800MHz_v1.24.bin' + MINILOADER_BLOB='rk33/rk3399_miniloader_v1.19.bin' + BL31_BLOB='rk33/rk3399_bl31_v1.30.elf' + +fi + +if [[ $BOOT_USE_MAINLINE_ATF == yes ]]; then + + UBOOT_TARGET_MAP="BL31=bl31.bin idbloader.img u-boot.itb;;idbloader.img u-boot.itb" + ATFSOURCE='https://github.com/ARM-software/arm-trusted-firmware' + ATFDIR='arm-trusted-firmware' + ATFBRANCH='tag:v2.2' + ATF_USE_GCC='> 6.3' + ATF_TARGET_MAP='M0_CROSS_COMPILE=arm-linux-gnueabi- PLAT=rk3399 bl31;;build/rk3399/release/bl31/bl31.elf:bl31.bin' + ATF_TOOLCHAIN2="arm-linux-gnueabi-:> 5.0" + +elif [[ $BOOT_USE_TPL_SPL_BLOB == yes ]]; then + + UBOOT_TARGET_MAP="BL31=$RKBIN_DIR/$BL31_BLOB idbloader.img u-boot.itb;;idbloader.img u-boot.itb" + ATFSOURCE='' + ATF_COMPILE='no' + +elif [[ $BOOT_USE_BLOBS == yes ]]; then + + UBOOT_TARGET_MAP="u-boot-dtb.bin;;idbloader.bin uboot.img trust.bin" + ATFSOURCE='' + ATF_COMPILE='no' + +fi + +write_uboot_platform() +{ + if [[ $BOOT_USE_MAINLINE_ATF == yes || $BOOT_USE_TPL_SPL_BLOB == yes ]]; then + + dd if=$1/idbloader.img of=$2 seek=64 conv=notrunc status=none >/dev/null 2>&1 + dd if=$1/u-boot.itb of=$2 seek=16384 conv=notrunc status=none >/dev/null 2>&1 + + elif [[ $BOOT_USE_BLOBS == yes ]] ; then + + dd if=$1/idbloader.bin of=$2 seek=64 conv=notrunc status=none >/dev/null 2>&1 + dd if=$1/uboot.img of=$2 seek=16384 conv=notrunc status=none >/dev/null 2>&1 + dd if=$1/trust.bin of=$2 seek=24576 conv=notrunc status=none >/dev/null 2>&1 + + else + echo "Unsupported u-boot processing configuration!" + exit 1 + + fi + +} + uboot_custom_postprocess() { - # bootloader image - local tempfile=$(mktemp) - tools/mkimage -n rk3399 -T rksd -d $SRC/cache/sources/rkbin-tools/rk33/rk3399_ddr_800MHz_v1.14.bin idbloader.bin - cat $SRC/cache/sources/rkbin-tools/rk33/rk3399_miniloader_v1.15.bin >> idbloader.bin - loaderimage --pack --uboot ./u-boot-dtb.bin uboot.img 0x200000 + if [[ $BOOT_USE_MAINLINE_ATF == yes || $BOOT_USE_TPL_SPL_BLOB == yes ]]; then + + : + + elif [[ $BOOT_USE_BLOBS == yes ]]; then + + local tempfile=$(mktemp) + tools/mkimage -n rk3399 -T rksd -d $RKBIN_DIR/$DDR_BLOB idbloader.bin + cat $RKBIN_DIR/$MINILOADER_BLOB >> idbloader.bin + loaderimage --pack --uboot ./u-boot-dtb.bin uboot.img 0x200000 + trust_merger --replace ./build/rk3399/debug/bl31/bl31.elf $RKBIN_DIR/$BL31_BLOB trust.ini + + else + echo "Unsupported u-boot processing configuration!" + exit 1 + fi } diff --git a/config/templates/customize-image.sh.template b/config/templates/customize-image.sh.template index 51b05d5b8..7873ec0e0 100644 --- a/config/templates/customize-image.sh.template +++ b/config/templates/customize-image.sh.template @@ -183,7 +183,7 @@ InstallOpenMediaVault() { bananapim3|nanopifire3|nanopct3plus|nanopim3) HMP_Fix='; taskset -c -p 4-7 $i ' ;; - edge*|ficus|firefly-rk3399|nanopct4|nanopim4|nanopineo4|renegade-elite|rockpro64) + edge*|ficus|firefly-rk3399|nanopct4|nanopim4|nanopineo4|renegade-elite|roc-rk3399-pc|rockpro64) HMP_Fix='; taskset -c -p 4-5 $i ' ;; esac diff --git a/patch/atf/atf-rk3399/fix-reset-in-v2.2.patch b/patch/atf/atf-rk3399/fix-reset-in-v2.2.patch new file mode 100644 index 000000000..107fc5a10 --- /dev/null +++ b/patch/atf/atf-rk3399/fix-reset-in-v2.2.patch @@ -0,0 +1,56 @@ +From f4707a3c40bfc752a24c427263f7cbe8d7adfcd6 Mon Sep 17 00:00:00 2001 +From: Vasily Khoruzhick +Date: Fri, 15 Nov 2019 08:25:02 -0800 +Subject: [PATCH] plat/rockchip: initialize reset and poweroff GPIOs with known + invalid value + +And return NULL if we didn't get them in bl aux params otherwise reset and poweroff +will be broken on platforms that do not have reset and poweroff GPIOs. + +Fixes: c1185ffde17c ("plat/rockchip: Switch to use new common BL aux parameter library") +Signed-off-by: Vasily Khoruzhick +--- + plat/rockchip/common/params_setup.c | 11 +++++++++-- + 1 file changed, 9 insertions(+), 2 deletions(-) + +diff --git a/plat/rockchip/common/params_setup.c b/plat/rockchip/common/params_setup.c +index 8c2e5e911b..b2fd2011e4 100644 +--- a/plat/rockchip/common/params_setup.c ++++ b/plat/rockchip/common/params_setup.c +@@ -6,6 +6,7 @@ + + #include + #include ++#include + #include + + #include +@@ -21,8 +22,8 @@ + #include + #include + +-static struct bl_aux_gpio_info rst_gpio; +-static struct bl_aux_gpio_info poweroff_gpio; ++static struct bl_aux_gpio_info rst_gpio = { .index = UINT_MAX } ; ++static struct bl_aux_gpio_info poweroff_gpio = { .index = UINT_MAX }; + static struct bl_aux_gpio_info suspend_gpio[10]; + uint32_t suspend_gpio_cnt; + static struct bl_aux_rk_apio_info suspend_apio; +@@ -174,11 +175,17 @@ uint32_t rockchip_get_uart_clock(void) + + struct bl_aux_gpio_info *plat_get_rockchip_gpio_reset(void) + { ++ if (rst_gpio.index == UINT_MAX) ++ return NULL; ++ + return &rst_gpio; + } + + struct bl_aux_gpio_info *plat_get_rockchip_gpio_poweroff(void) + { ++ if (poweroff_gpio.index == UINT_MAX) ++ return NULL; ++ + return &poweroff_gpio; + } + diff --git a/patch/atf/atf-rk3399/switch-power-domains-on-before-reset.patch b/patch/atf/atf-rk3399/switch-power-domains-on-before-reset.patch new file mode 100644 index 000000000..b0a784f16 --- /dev/null +++ b/patch/atf/atf-rk3399/switch-power-domains-on-before-reset.patch @@ -0,0 +1,63 @@ +diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c +index 42589b9..8f2a419 100644 +--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c ++++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c +@@ -400,7 +400,26 @@ static void pmu_power_domains_resume(void) + clk_gate_con_restore(); + } + +-void rk3399_flush_l2_b(void) ++void pmu_power_domains_on(void) ++{ ++ clk_gate_con_disable(); ++ pmu_set_power_domain(PD_VDU, pmu_pd_on); ++ pmu_set_power_domain(PD_VCODEC, pmu_pd_on); ++ pmu_set_power_domain(PD_RGA, pmu_pd_on); ++ pmu_set_power_domain(PD_IEP, pmu_pd_on); ++ pmu_set_power_domain(PD_EDP, pmu_pd_on); ++ pmu_set_power_domain(PD_GMAC, pmu_pd_on); ++ pmu_set_power_domain(PD_SDIOAUDIO, pmu_pd_on); ++ pmu_set_power_domain(PD_HDCP, pmu_pd_on); ++ pmu_set_power_domain(PD_ISP1, pmu_pd_on); ++ pmu_set_power_domain(PD_ISP0, pmu_pd_on); ++ pmu_set_power_domain(PD_VO, pmu_pd_on); ++ pmu_set_power_domain(PD_TCPD1, pmu_pd_on); ++ pmu_set_power_domain(PD_TCPD0, pmu_pd_on); ++ pmu_set_power_domain(PD_GPU, pmu_pd_on); ++} ++ ++void rk3399_flush_l2_b(void) + { + uint32_t wait_cnt = 0; + +diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.h b/plat/rockchip/rk3399/drivers/pmu/pmu.h +index e1ba410..27a453b 100644 +--- a/plat/rockchip/rk3399/drivers/pmu/pmu.h ++++ b/plat/rockchip/rk3399/drivers/pmu/pmu.h +@@ -136,5 +136,6 @@ struct pmu_slpdata_s { + extern uint32_t clst_warmboot_data[PLATFORM_CLUSTER_COUNT]; + + extern void sram_func_set_ddrctl_pll(uint32_t pll_src); ++void pmu_power_domains_on(void); + + #endif /* PMU_H */ +diff --git a/plat/rockchip/rk3399/drivers/soc/soc.c b/plat/rockchip/rk3399/drivers/soc/soc.c +index c877dbd..98b5ad6 100644 +--- a/plat/rockchip/rk3399/drivers/soc/soc.c ++++ b/plat/rockchip/rk3399/drivers/soc/soc.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -327,6 +328,7 @@ void soc_global_soft_reset_init(void) + + void __dead2 soc_global_soft_reset(void) + { ++ pmu_power_domains_on(); + set_pll_slow_mode(VPLL_ID); + set_pll_slow_mode(NPLL_ID); + set_pll_slow_mode(GPLL_ID); diff --git a/patch/kernel/rk3399-default/roc-rk3399-pc.patch b/patch/kernel/rk3399-default/roc-rk3399-pc.patch new file mode 100644 index 000000000..294a281c7 --- /dev/null +++ b/patch/kernel/rk3399-default/roc-rk3399-pc.patch @@ -0,0 +1,1567 @@ +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -8,7 +8,8 @@ + rk3399-nanopi4-rev07.dtb \ + rk3399-nanopi4-rev21.dtb \ + rk3399-nanopi4-rev22.dtb \ +- rk3399-firefly.dtb ++ rk3399-firefly.dtb \ ++ rk3399-roc-pc.dtb + + else + +@@ -109,6 +110,7 @@ + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin-r1.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-mid-818-android-6.0.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-mid-818-android.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960-ab.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rv1-android.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-exp.dts +@@ -0,0 +1,20 @@ ++/dts-v1/; ++#include "rk3399-roc-pc.dtsi" ++ ++/ { ++ model = "Firefly roc-rk3399-pc"; ++ compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; ++}; ++ ++&wireless_wlan { ++ status = "okay"; ++}; ++ ++&wireless_bluetooth { ++ status = "okay"; ++}; ++ ++&usb_charge { ++ status = "okay"; ++}; ++ +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mipi.dts +@@ -0,0 +1,78 @@ ++/dts-v1/; ++#include "rk3399-roc-pc.dtsi" ++ ++/ { ++ model = "Firefly roc-rk3399-pc"; ++ compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; ++ ++}; ++ ++&pinctrl { ++ vcc_dis { ++ vcc_dis_en0: vcc-dis-en0 { ++ rockchip,pins = ++ <2 6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++//mipi ++&dsi { ++ status = "okay"; ++ //status = "okay"; ++ dsi_panel: panel { ++ compatible ="simple-panel-dsi"; ++ reg = <0>; ++ backlight = <&backlight>; ++ power-supply = <&vcc_lcd>; ++ dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST)>; ++ dsi,format = ; ++ bus-format = ; ++ dsi,lanes = <4>; ++ reset-delay-ms = <20>; ++ init-delay-ms = <20>; ++ enable-delay-ms = <120>; ++ prepare-delay-ms = <120>; ++ status = "okay"; ++ ++ panel-init-sequence = [ ++ 05 20 01 29 ++ 05 96 01 11 ++ ]; ++ ++ panel-exit-sequence = [ ++ 05 05 01 28 ++ 05 78 01 10 ++ ]; ++ ++ disp_timings: display-timings { ++ native-mode = <&timing0>; ++ ++ timing0: timing0 { ++ clock-frequency = <80000000>; ++ hactive = <768>; ++ vactive = <1024>; ++ hsync-len = <20>; ++ hback-porch = <110>; ++ hfront-porch = <170>; ++ vsync-len = <40>; ++ vback-porch = <130>; ++ vfront-porch = <136>; ++ hsync-active = <0>; ++ vsync-active = <0>; ++ de-active = <0>; ++ pixelclk-active = <0>; ++ }; ++ }; ++ }; ++}; ++ ++//TF ++&gsl3680 { ++ status = "okay"; ++}; ++ ++//boot logo for MIPI screen ++&route_dsi { ++ status = "disabled"; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts +@@ -0,0 +1,7 @@ ++/dts-v1/; ++#include "rk3399-roc-pc.dtsi" ++ ++/ { ++ model = "Firefly roc-rk3399-pc"; ++ compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; ++}; +\ No newline at end of file +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +@@ -0,0 +1,1419 @@ ++#include "dt-bindings/pwm/pwm.h" ++#include "rk3399.dtsi" ++#include "rk3399-opp.dtsi" ++#include "rk3399-linux.dtsi" ++#include ++#include ++//#include "include/uapi/drm/drm_mode.h" ++ ++/ { ++ compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; ++ ++ backlight: backlight { ++ status = "okay"; ++ compatible = "pwm-backlight"; ++ pwms = <&pwm1 0 25000 0>; ++ brightness-levels = < ++ 0 1 2 3 4 5 6 7 ++ 8 9 10 11 12 13 14 15 ++ 16 17 18 19 20 21 22 23 ++ 24 25 26 27 28 29 30 31 ++ 32 33 34 35 36 37 38 39 ++ 40 41 42 43 44 45 46 47 ++ 48 49 50 51 52 53 54 55 ++ 56 57 58 59 60 61 62 63 ++ 64 65 66 67 68 69 70 71 ++ 72 73 74 75 76 77 78 79 ++ 80 81 82 83 84 85 86 87 ++ 88 89 90 91 92 93 94 95 ++ 96 97 98 99 100 101 102 103 ++ 104 105 106 107 108 109 110 111 ++ 112 113 114 115 116 117 118 119 ++ 120 121 122 123 124 125 126 127 ++ 128 129 130 131 132 133 134 135 ++ 136 137 138 139 140 141 142 143 ++ 144 145 146 147 148 149 150 151 ++ 152 153 154 155 156 157 158 159 ++ 160 161 162 163 164 165 166 167 ++ 168 169 170 171 172 173 174 175 ++ 176 177 178 179 180 181 182 183 ++ 184 185 186 187 188 189 190 191 ++ 192 193 194 195 196 197 198 199 ++ 200 201 202 203 204 205 206 207 ++ 208 209 210 211 212 213 214 215 ++ 216 217 218 219 220 221 222 223 ++ 224 225 226 227 228 229 230 231 ++ 232 233 234 235 236 237 238 239 ++ 240 241 242 243 244 245 246 247 ++ 248 249 250 251 252 253 254 255>; ++ default-brightness-level = <200>; ++ }; ++ ++ /* first 64k(0xff8c0000~0xff8d0000) for ddr and suspend */ ++ ++ iram: sram@ff8d0000 { ++ compatible = "mmio-sram"; ++ reg = <0x0 0xff8d0000 0x0 0x20000>; /* 128k */ ++ }; ++ ++ clkin_gmac: external-gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "clkin_gmac"; ++ #clock-cells = <0>; ++ }; ++ ++ hdmi_sound: hdmi-sound { ++ status = "disabled"; ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,mclk-fs = <256>; ++ simple-audio-card,name = "rockchip,hdmi"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s2>; ++ }; ++ simple-audio-card,codec { ++ sound-dai = <&hdmi>; ++ }; ++ }; ++ ++ vccadc_ref: vccadc-ref { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc1v8_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ vcc5v0_host: vcc5v0-host-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&host_vbus_drv>; ++ regulator-name = "vcc5v0_host"; ++ regulator-always-on; ++ }; ++ ++ vcc_hub_en: vcc_hub_en-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hub_rst_en>; ++ regulator-name = "vcc_hub_en"; ++ regulator-always-on; ++ }; ++ ++ vcc_wifi: vcc-wifi { ++ status = "okay"; ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_wifi"; ++ enable-active-high; ++ gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc_wifi_h>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc_pcie: vcc-pcie { ++ status = "okay"; ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_pcie"; ++ enable-active-high; ++ gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc_pcie_h>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc_chargen: vcc-chargen { ++ status = "disabled"; ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_chargen"; ++ enable-active-high; ++ gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc_chargen_h>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc_sd: vcc-sd { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc_sd_h>; ++ regulator-name = "vcc_sd"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc_phy: vcc-phy-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_phy"; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vdd_log: vdd-log { ++ compatible = "pwm-regulator"; ++ pwms = <&pwm2 0 25000 1>; ++ regulator-name = "vdd_log"; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ /* for rockchip boot on */ ++ rockchip,pwm_id= <2>; ++ rockchip,pwm_voltage = <1000000>; ++ }; ++ ++ vcc_lcd: vcc-lcd-regulator { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ enable-active-high; ++ gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lcd_en>; ++ regulator-name = "vcc_lcd"; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk808 1>; ++ clock-names = "ext_clock"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_enable_h>; ++ ++ /* ++ * On the module itself this is one of these (depending ++ * on the actual card populated): ++ * - SDIO_RESET_L_WL_REG_ON ++ * - PDN (power down when low) ++ */ ++ reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */ ++ }; ++ ++ wireless_wlan: wireless-wlan { ++ compatible = "wlan-platdata"; ++ rockchip,grf = <&grf>; ++ wifi_chip_type = "ap6354"; ++ sdio_vref = <1800>; ++ WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */ ++ status = "disabled"; ++ }; ++ ++ wireless_bluetooth: wireless-bluetooth { ++ compatible = "bluetooth-platdata"; ++ //wifi-bt-power-toggle; ++ clocks = <&rk808 1>; ++ clock-name = "ext_clock"; ++ uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */ ++ pinctrl-names = "default", "rts_gpio"; ++ pinctrl-0 = <&uart0_rts>; ++ pinctrl-1 = <&uart0_gpios>; ++ //BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */ ++ BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */ ++ BT,wake_gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */ ++ BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */ ++ status = "disabled"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ power { ++ label = "firefly:blue:power"; ++ linux,default-trigger = "ir-power-click"; ++ default-state = "on"; ++ gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default";pinctrl-0 = <&led_power>; ++ }; ++ user { ++ label = "firefly:yellow:user"; ++ linux,default-trigger = "ir-user-click"; ++ default-state = "off"; ++ gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_user>; ++ }; ++ }; ++ ++ adc-keys { ++ compatible = "adc-keys"; ++ io-channels = <&saradc 1>; ++ io-channel-names = "buttons"; ++ poll-interval = <300>; ++ keyup-threshold-microvolt = <1800000>; ++ ++ esc-key { ++ linux,code = ; ++ label = "esc"; ++ press-threshold-microvolt = <0>; ++ }; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ autorepeat; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwrbtn>; ++ ++ button@0 { ++ gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ label = "GPIO Key Power"; ++ linux,input-type = <1>; ++ gpio-key,wakeup = <1>; ++ debounce-interval = <100>; ++ }; ++ }; ++ ++ usb_charge: usb-charge { ++ compatible = "usb-ext-charge"; ++ status = "disabled"; ++ io-channels = <&saradc 0>; ++ extcon = <&fusb0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc_chargen_h &bat_int_h &cur_ctl_h &poe_det_h>; ++ bat-int = <&gpio2 28 IRQ_TYPE_EDGE_RISING>; ++ charge-en-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; ++ cur-ctl-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; ++ poe-state-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; ++ //cap-led-gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ dp_sound: dp-sound { ++ status = "disabled"; ++ compatible = "rockchip,cdndp-sound"; ++ rockchip,cpu = <&spdif>; ++ rockchip,codec = <&cdn_dp 1>; ++ }; ++ ++ vcc_mipi: vcc_mipi { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&dvp_pwr>; ++ regulator-name = "vcc_mipi"; ++ status = "disabled"; ++ }; ++ ++ dvdd_1v2: dvdd-1v2 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cif_pwr>; ++ regulator-name = "dvdd_1v2"; ++ status = "disabled"; ++ }; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&display_subsystem { ++ status = "okay"; ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&gmac { ++ phy-supply = <&vcc_phy>; ++ phy-mode = "rgmii"; ++ clock_in_out = "input"; ++ snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 50000>; ++ assigned-clocks = <&cru SCLK_RMII_SRC>; ++ assigned-clock-parents = <&clkin_gmac>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmii_pins>; ++ tx_delay = <0x2e>; ++ rx_delay = <0x13>; ++ status = "okay"; ++}; ++ ++&gpu { ++ status = "okay"; ++ mali-supply = <&vdd_gpu>; ++}; ++ ++&hdmi { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #sound-dai-cells = <0>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ i2c-scl-rising-time-ns = <168>; ++ i2c-scl-falling-time-ns = <4>; ++ clock-frequency = <400000>; ++ ++ vdd_cpu_b: syr827@40 { ++ compatible = "silergy,syr827"; ++ reg = <0x40>; ++ vin-supply = <&vcc5v0_sys>; ++ regulator-compatible = "fan53555-reg"; ++ regulator-name = "vdd_cpu_b"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ pinctrl-0 = <&vsel1_gpio>; ++ vsel-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-state = <3>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: syr828@41 { ++ compatible = "silergy,syr828"; ++ reg = <0x41>; ++ vin-supply = <&vcc5v0_sys>; ++ pinctrl-0 = <&vsel2_gpio>; ++ vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; ++ regulator-compatible = "fan53555-reg"; ++ regulator-name = "vdd_gpu"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-state = <3>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk808: pmic@1b { ++ compatible = "rockchip,rk808"; ++ reg = <0x1b>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; ++ pinctrl-names = "default"; ++ //pinctrl-0 = <&pmic_int_l &pmic_dvs2>; ++ pinctrl-0 = <&pmic_int_l &pmic_dvs2 &vcc_5v0_h>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk808-clkout2"; ++ ++ pmic,hold-gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; ++ ++ //vin-supply = <&sys_12v>; ++ ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ vcc10-supply = <&vcc3v3_sys>; ++ vcc11-supply = <&vcc3v3_sys>; ++ vcc12-supply = <&vcc3v3_sys>; ++ vddio-supply = <&vcc1v8_pmu>; ++ ++ regulators { ++ vdd_center: DCDC_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ regulator-name = "vdd_center"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_l: DCDC_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ regulator-name = "vdd_cpu_l"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vcc_ddr"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_codec: LDO_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcca1v8_codec"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc1v8_hdmi: LDO_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc1v8_hdmi"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc1v8_pmu: LDO_REG3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc1v8_pmu"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vccio_sd"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcca3v0_codec: LDO_REG5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcca3v0_codec"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v5: LDO_REG6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-name = "vcc_1v5"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1500000>; ++ }; ++ }; ++ ++ vcca0v9_hdmi: LDO_REG7 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-name = "vcca0v9_hdmi"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v0: LDO_REG8 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc_3v0"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcc3v3_s3: SWITCH_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vcc3v3_s3"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_s0: SWITCH_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vcc3v3_s0"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ i2c-scl-rising-time-ns = <300>; ++ i2c-scl-falling-time-ns = <15>; ++ clock-frequency = <100000>; ++ ++ ov13850: ov13850@36 { ++ compatible = "ovti,ov13850"; ++ status = "disabled"; ++ reg = <0x36>; ++ clocks = <&cru SCLK_CIF_OUT>; ++ clock-names = "xvclk"; ++ ++ /* conflict with csi-ctl-gpios */ ++ reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; /*GPIO0_B0 MIP_RST*/ ++ pwdn-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; /*GPIO2_A2 DVP_PDN0*/ ++ pinctrl-names = "rockchip,camera_default", "rockchip,camera_sleep"; ++ //pinctrl-0 = <&cif_clkout>; ++ pinctrl-0 = <&pwdn_cam0 &mipi_rst>; ++ pinctrl-1 = <&cam0_default_pins>; ++ pinctrl-2 = <&cam0_sleep_pins>; ++ rockchip,camera-module-index = <0>; ++ rockchip,camera-module-facing = "back"; ++ rockchip,camera-module-name = "CMK-CT0116"; ++ rockchip,camera-module-lens-name = "Largan-50013A1"; ++ ++ avdd-supply = <&vcc_mipi>; /* GPIO1_C6 CIF_PWR AGND*/ ++ dovdd-supply = <&vcc_mipi>; /* GPIO1_C6 CIF_PWR AGND */ ++ dvdd-supply = <&dvdd_1v2>; /* GPIO1_C7 DVP_PWR DVDD_1V2 */ ++ ++ port { ++ ucam_out0: endpoint { ++ remote-endpoint = <&mipi_in_ucam0>; ++ data-lanes = <1 2>; ++ }; ++ }; ++ }; ++ ++ ov13850_1: ov13850@46 { ++ compatible = "ovti,ov13850"; ++ status = "disabled"; ++ reg = <0x46>; ++ clocks = <&cru SCLK_CIF_OUT>; ++ clock-names = "xvclk"; ++ ++ /* conflict with csi-ctl-gpios */ ++ reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; /*GPIO0_B0 MIP_RST*/ ++ pwdn-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; /*GPIO2_A3 DVP_PDN0*/ ++ pinctrl-names = "rockchip,camera_default", "rockchip,camera_sleep"; ++ //pinctrl-0 = <&cif_clkout>; ++ pinctrl-0 = <&pwdn_cam1>; ++ pinctrl-1 = <&cam0_default_pins>; ++ pinctrl-2 = <&cam0_sleep_pins>; ++ rockchip,camera-module-index = <1>; ++ rockchip,camera-module-facing = "back"; ++ rockchip,camera-module-name = "CMK-CT0116"; ++ rockchip,camera-module-lens-name = "Largan-50013A1"; ++ ++ avdd-supply = <&vcc_mipi>; /* VCC28_MIPI */ ++ dovdd-supply = <&vcc_mipi>; /* VCC18_MIPI */ ++ dvdd-supply = <&dvdd_1v2>; /* DVDD_1V2 */ ++ ++ port { ++ ucam_out1: endpoint { ++ remote-endpoint = <&mipi_in_ucam1>; ++ data-lanes = <1 2>; ++ }; ++ }; ++ }; ++}; ++ ++&i2c2 { ++ status = "okay"; ++ cw2015@62 { ++ status = "okay"; ++ compatible = "cw201x"; ++ reg = <0x62>; ++ bat_config_info = <0x15 0x42 0x60 0x59 0x52 0x58 0x4D 0x48 ++ 0x48 0x44 0x44 0x46 0x49 0x48 0x32 0x24 ++ 0x20 0x17 0x13 0x0F 0x19 0x3E 0x51 0x45 ++ 0x08 0x76 0x0B 0x85 0x0E 0x1C 0x2E 0x3E ++ 0x4D 0x52 0x52 0x57 0x3D 0x1B 0x6A 0x2D ++ 0x25 0x43 0x52 0x87 0x8F 0x91 0x94 0x52 ++ 0x82 0x8C 0x92 0x96 0xFF 0x7B 0xBB 0xCB ++ 0x2F 0x7D 0x72 0xA5 0xB5 0xC1 0x46 0xAE>; ++ monitor_sec = <5>; ++ virtual_power = <0>; ++ }; ++}; ++ ++&i2c4 { ++ status = "okay"; ++ i2c-scl-rising-time-ns = <475>; ++ i2c-scl-falling-time-ns = <26>; ++ ++ gsl3680: gsl3680@40 { ++ status = "disabled"; ++ compatible = "gslX680"; ++ reg = <0x40>; ++ screen_max_x = <1536>; ++ screen_max_y = <2048>; ++ revert_xy = <0>; ++ revert_x = <0>; ++ revert_y = <0>; ++ touch-gpio = <&gpio4 28 IRQ_TYPE_LEVEL_LOW>; ++ reset-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ fusb1: fusb30x@22 { ++ compatible = "fairchild,fusb302"; ++ reg = <0x22>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&fusb1_int &typec1_vbus_drv>; ++ int-n-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; ++ vbus-5v-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ }; ++ ++}; ++ ++&i2c7 { ++ status = "okay"; ++ i2c-scl-rising-time-ns = <345>; ++ i2c-scl-falling-time-ns = <11>; ++ clock-frequency = <400000>; ++ ++ fusb0: fusb30x@22 { ++ compatible = "fairchild,fusb302"; ++ reg = <0x22>; ++ //charge-dev = <&mp8859>; ++ power-dev = <&mp8859>; ++ pinctrl-names = "default"; ++ //pinctrl-0 = <&fusb0_int &vcc_chargen_h>; ++ pinctrl-0 = <&fusb0_int>; ++ int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; ++ //charge-en-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ }; ++ ++ mp8859: mp8859@66 { ++ compatible = "mps,mp8859"; ++ reg = <0x66>; ++ status = "okay"; ++ extcon = <&fusb0>; ++ max-input-voltage = <15000000>; ++ max-input-current = <3000000>; ++ //charge-en-gpios =<&gpio0 1 GPIO_ACTIVE_HIGH>; ++ //pinctrl-names = "default"; ++ //pinctrl-0 = <&vcc_chargen_h>; ++ //mp,register-power-supply; ++ ++ regulators { ++ sys_12v: mp8859_dcdc1 { ++ regulator-name = "sys_12v"; ++ regulator-min-microvolt = <12300000>; ++ regulator-max-microvolt = <12300000>; ++ regulator-ramp-delay = <8000>; ++ //regulator-always-on; ++ //regulator-boot-on; ++ }; ++ }; ++ }; ++}; ++ ++&i2s1 { ++ status = "okay"; ++ rockchip,i2s-broken-burst-len; ++ rockchip,playback-channels = <2>; ++ rockchip,capture-channels = <2>; ++ #sound-dai-cells = <0>; ++ assigned-clocks = <&cru SCLK_I2S1_DIV>, <&cru SCLK_I2S_8CH>; ++ assigned-clock-parents = <&cru PLL_GPLL>, <&cru SCLK_I2S1_8CH>; ++}; ++ ++&i2s2 { ++ #sound-dai-cells = <0>; ++ dmas = <&dmac_bus 4>; ++ dma-names = "tx"; ++ status = "okay"; ++}; ++ ++&io_domains { ++ status = "okay"; ++ bt656-supply = <&vcc_3v0>; /* bt656_gpio2ab_ms */ ++ audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */ ++ sdmmc-supply = <&vccio_sd>; /* sdmmc_gpio4b_ms */ ++ gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ ++}; ++ ++&pcie_phy { ++ status = "okay"; ++}; ++ ++ ++&pcie0 { ++ ep-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; ++ num-lanes = <4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_clkreqn_cpm>; ++ status = "okay"; ++}; ++ ++&pmu_io_domains { ++ status = "okay"; ++ pmu1830-supply = <&vcc_3v0>; ++}; ++ ++&pinctrl { ++ cam0 { ++ cif_pwr: cif-pwr { ++ rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ dvp_pwr: dvp-pwr { ++ rockchip,pins = <1 22 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ lcd-panel { ++ lcd_panel_reset: lcd-panel-reset { ++ rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ lcd_en: lcd-en { ++ rockchip,pins = <1 24 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ pmic { ++ vsel1_gpio: vsel1-gpio { ++ rockchip,pins = ++ <1 18 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ vsel2_gpio: vsel2-gpio { ++ rockchip,pins = ++ <1 14 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ leds { ++ led_power: led-power { ++ rockchip,pins = ++ <2 27 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ led_user: led-user { ++ rockchip,pins = ++ <0 13 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = ++ <1 21 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ pmic_dvs2: pmic-dvs2 { ++ rockchip,pins = ++ <1 18 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ }; ++ ++ sdio-pwrseq { ++ wifi_enable_h: wifi-enable-h { ++ rockchip,pins = ++ <0 10 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ wireless-bluetooth { ++ uart0_gpios: uart0-gpios { ++ rockchip,pins = ++ <2 19 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ ++ ++ usb2 { ++ host_vbus_drv: host-vbus-drv { ++ rockchip,pins = ++ <1 0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ hub_rst_en: hub-rst-en { ++ rockchip,pins = ++ <2 4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ fusb30x { ++ fusb1_int: fusb1-int { ++ rockchip,pins = <1 1 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ fusb0_int: fusb0-int { ++ rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ typec1_vbus_drv: typec1-vbus-drv { ++ rockchip,pins = <1 13 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ vcc5v0_sys { ++ vcc_5v0_h: vcc-5v0-h { ++ rockchip,pins = <2 6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ vcc_sd { ++ vcc_sd_h: vcc-sd-h { ++ rockchip,pins = <4 30 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ wifi { ++ vcc_wifi_h: vcc-wifi-h { ++ rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie { ++ vcc_pcie_h: vcc-pcie-h { ++ rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ buttons { ++ pwrbtn: pwrbtn { ++ rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ chargen { ++ vcc_chargen_h: vcc-chargen-h { ++ rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ bat_int_h: bat-int-h { ++ rockchip,pins = <2 28 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ cur_ctl_h: cur-ctl-h { ++ rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none_20ma>; ++ }; ++ poe_det_h: poe-det-h { ++ rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ cam_pins { ++ cam0_default_pins: cam0-default-pins { ++ rockchip,pins = ++ // <4 27 RK_FUNC_GPIO &pcfg_pull_none>, ++ <2 11 RK_FUNC_3 &pcfg_pull_none>; ++ }; ++ ++ cam0_sleep_pins: cam0-sleep-pins { ++ rockchip,pins = ++ <4 27 RK_FUNC_3 &pcfg_pull_none>, ++ <2 11 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pwdn_cam0: pwdn-cma0 { ++ rockchip,pins = ++ <2 2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pwdn_cam1: pwdn-cma1 { ++ rockchip,pins = ++ <2 3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ mipi_rst: mipi-rst { ++ rockchip,pins = ++ <0 8 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pwm0 { ++ status = "okay"; ++}; ++ ++&pwm1 { ++ status = "okay"; ++}; ++ ++&pwm2 { ++ status = "okay"; ++ pinctrl-names = "active"; ++ pinctrl-0 = <&pwm2_pin_pull_down>; ++}; ++ ++&rkvdec { ++ status = "okay"; ++}; ++ ++&rockchip_suspend { ++ rockchip,power-ctrl = ++ <&gpio1 18 GPIO_ACTIVE_LOW>, ++ <&gpio1 14 GPIO_ACTIVE_HIGH>; ++}; ++ ++&route_hdmi { ++ status = "okay"; ++}; ++ ++&dp_sound { ++ status = "okay"; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&cdn_dp { ++ status = "okay"; ++ extcon = <&fusb0 &fusb1>; ++ phys = <&tcphy0_dp &tcphy1_dp>; ++}; ++ ++&hdmi_in_vopl { ++ status = "disabled"; ++}; ++ ++&dp_in_vopb { ++ status = "okay"; ++}; ++ ++&dp_in_vopl { ++ status = "disabled"; ++}; ++ ++&saradc { ++ status = "okay"; ++ vref-supply = <&vccadc_ref>; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ keep-power-in-suspend; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ non-removable; ++ status = "okay"; ++ supports-emmc; ++}; ++ ++&sdmmc { ++ //max-frequncy = <150000000>; ++ clock-frequency = <150000000>; ++ clock-freq-min-max = <100000 150000000>; ++ supports-sd; ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ num-slots = <1>; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_sd>; ++ vqmmc-supply = <&vccio_sd>; ++ //vqmmc-supply = <&vcc_sd>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; ++ status = "okay"; ++}; ++ ++&sdio0 { ++ max-frequency = <100000000>; ++ supports-sdio; ++ bus-width = <4>; ++ disable-wp; ++ cap-sd-highspeed; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ non-removable; ++ num-slots = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; ++ ++&tcphy0 { ++ extcon = <&fusb0>; ++ status = "okay"; ++}; ++ ++&tcphy1 { ++ extcon = <&fusb1>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ /* tshut mode 0:CRU 1:GPIO */ ++ rockchip,hw-tshut-mode = <1>; ++ /* tshut polarity 0:LOW 1:HIGH */ ++ rockchip,hw-tshut-polarity = <1>; ++ status = "okay"; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++ extcon = <&fusb0>; ++ ++ u2phy0_otg: otg-port { ++ status = "okay"; ++ }; ++ ++ u2phy0_host: host-port { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++ }; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++ extcon = <&fusb1>; ++ ++ u2phy1_otg: otg-port { ++ status = "okay"; ++ }; ++ ++ u2phy1_host: host-port { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_xfer &uart0_cts>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "disabled"; ++}; ++ ++&usbdrd3_0 { ++ status = "okay"; ++ extcon = <&fusb0>; ++}; ++ ++&usbdrd3_1 { ++ status = "okay"; ++ extcon = <&fusb1>; ++}; ++ ++&usbdrd_dwc3_0 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_1 { ++ status = "okay"; ++ dr_mode = "host"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++ pinctrl-names = "default"; ++}; ++ ++&spi1 { ++ status = "okay"; ++ max-freq = <48000000>; ++ dev-port = <0>; ++ ++ spidev0: spidev@00 { ++ status = "okay"; ++ //compatible = "linux,spidev"; ++ compatible = "jedec,spi-nor"; ++ reg = <0x00>; ++ spi-max-frequency = <48000000>; ++ }; ++}; ++ ++&pwm3 { ++ status = "okay"; ++ interrupts = ; ++ compatible = "rockchip,remotectl-pwm"; ++ pinctrl-names = "default"; ++ remote_pwm_id = <3>; ++ handle_cpu_id = <0>; ++ remote_support_psci = <1>; ++ ++ ir_key1{ ++ rockchip,usercode = <0xff00>; ++ rockchip,key_table = ++ <0xeb KEY_POWER>, ++ <0xec KEY_MENU>, ++ <0xfe KEY_BACK>, ++ <0xb7 KEY_HOME>, ++ <0xa3 KEY_WWW>, ++ <0xf4 KEY_VOLUMEUP>, ++ <0xa7 KEY_VOLUMEDOWN>, ++ <0xf8 KEY_REPLY>, ++ <0xfc KEY_UP>, ++ <0xfd KEY_DOWN>, ++ <0xf1 KEY_LEFT>, ++ <0xe5 KEY_RIGHT>; ++ }; ++}; ++ ++&vopb { ++ status = "okay"; ++}; ++&vopb_mmu { ++ status = "okay"; ++}; ++&vopl { ++ status = "okay"; ++}; ++&vopl_mmu { ++ status = "okay"; ++}; ++&vpu { ++ status = "okay"; ++}; ++ ++&spdif { ++ status = "okay"; ++ pinctrl-0 = <&spdif_bus_1>; ++ i2c-scl-rising-time-ns = <450>; ++ i2c-scl-falling-time-ns = <15>; ++ #sound-dai-cells = <0>; ++}; ++ ++&mipi_dphy_rx0 { ++ status = "okay"; ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ mipi_in_ucam0: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&ucam_out0>; ++ data-lanes = <1 2>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ dphy_rx0_out: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&isp0_mipi_in>; ++ }; ++ }; ++ }; ++}; ++ ++&mipi_dphy_tx1rx1 { ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ mipi_in_ucam1: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&ucam_out1>; ++ data-lanes = <1 2>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ dphy_tx1rx1_out: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&isp1_mipi_in>; ++ }; ++ }; ++ }; ++}; ++ ++ ++&rkisp1_0 { ++ status = "disabled"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ isp0_mipi_in: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&dphy_rx0_out>; ++ }; ++ }; ++}; ++ ++&rkisp1_1 { ++ status = "disabled"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ isp1_mipi_in: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&dphy_tx1rx1_out>; ++ }; ++ }; ++}; ++ ++&cam0_default_pins { ++ rockchip,pins = ++ <2 11 RK_FUNC_3 &pcfg_pull_none>; ++}; ++ ++&vcc_mipi { ++ status = "okay"; ++}; ++ ++&dvdd_1v2 { ++ status = "okay"; ++}; ++ ++&ov13850 { ++ status = "okay"; ++}; ++ ++&ov13850_1 { ++ status = "okay"; ++}; ++ ++&rkisp1_0 { ++ status = "okay"; ++}; ++ ++&mipi_dphy_rx0 { ++ status = "okay"; ++}; ++ ++&isp0_mmu { ++ status = "okay"; ++}; ++ ++&rkisp1_1 { ++ status = "okay"; ++}; ++ ++&mipi_dphy_tx1rx1 { ++ status = "okay"; ++}; ++ ++&isp1_mmu { ++ status = "okay"; ++}; +--- a/include/dt-bindings/clock/rk3399-cru.h ++++ b/include/dt-bindings/clock/rk3399-cru.h +@@ -31,6 +31,7 @@ + + /* sclk gates (special clocks) */ + #define SCLK_I2SOUT_SRC 64 ++#define SCLK_I2S_8CH SCLK_I2SOUT_SRC + #define SCLK_I2C1 65 + #define SCLK_I2C2 66 + #define SCLK_I2C3 67 diff --git a/patch/kernel/rk3399-legacy/firefly-dts.patch b/patch/kernel/rk3399-legacy/firefly-dts.patch index 542d8ed33..fd9d34cdc 100644 --- a/patch/kernel/rk3399-legacy/firefly-dts.patch +++ b/patch/kernel/rk3399-legacy/firefly-dts.patch @@ -2,7 +2,7 @@ diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchi index 244272a3..8da63ea9 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -8,7 +8,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ +@@ -7,7 +7,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3399-nanopi4-rev06.dtb \ rk3399-nanopi4-rev07.dtb \ rk3399-nanopi4-rev21.dtb \ diff --git a/patch/kernel/rockchip64-dev/board-roc-rk3399-pc-fix-regulator.patch b/patch/kernel/rockchip64-dev/board-roc-rk3399-pc-fix-regulator.patch new file mode 100644 index 000000000..da812d144 --- /dev/null +++ b/patch/kernel/rockchip64-dev/board-roc-rk3399-pc-fix-regulator.patch @@ -0,0 +1,24 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts +@@ -113,6 +113,10 @@ + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc_sys_en>; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; +@@ -521,6 +525,10 @@ + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + ++ vcc_sys_en: vcc-sys-en { ++ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ + hub_rst: hub-rst { + rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_output_high>; + }; diff --git a/patch/u-boot/u-boot-rk3399/add-trust-ini.patch b/patch/u-boot/u-boot-rk3399/add-trust-ini.patch new file mode 100644 index 000000000..528ec5570 --- /dev/null +++ b/patch/u-boot/u-boot-rk3399/add-trust-ini.patch @@ -0,0 +1,21 @@ +diff --git a/trust.ini b/trust.ini +new file mode 100644 +index 0000000..4af021a +--- /dev/null ++++ b/trust.ini +@@ -0,0 +1,15 @@ ++[VERSION] ++MAJOR=1 ++MINOR=0 ++[BL30_OPTION] ++SEC=0 ++[BL31_OPTION] ++SEC=1 ++PATH=./build/rk3399/debug/bl31/bl31.elf ++ADDR=0x10000 ++[BL32_OPTION] ++SEC=0 ++[BL33_OPTION] ++SEC=0 ++[OUTPUT] ++PATH=trust.bin diff --git a/patch/u-boot/u-boot-rk3399/rk3399-disable-iram-reservation.patch b/patch/u-boot/u-boot-rk3399/rk3399-disable-iram-reservation.patch new file mode 100644 index 000000000..72bd4abc7 --- /dev/null +++ b/patch/u-boot/u-boot-rk3399/rk3399-disable-iram-reservation.patch @@ -0,0 +1,191 @@ +Patch adapted to disable leez config for now + +From 45f412fc2dcdf00873444eb4c78769b1571b0237 Mon Sep 17 00:00:00 2001 +From: Kever Yang +Date: Fri, 18 Oct 2019 15:54:14 +0800 +Subject: [PATCH] rockchip: rk3399: defconfig: no need to reserve IRAM for SPL + +We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code, +and when we introduce the TPL, the SPL space is in DRAM, we reserve +space to avoid SPL text overlap with ATF bl31. + +Now we decide to move ATF entry point to 0x40000 instead of 0x1000, +so that the SPL can have 0x4000 as code size and no need to reserve +space or relocate before loading ATF. + +The mainline ATF has update since: +0aad563c rockchip: Update BL31_BASE to 0x40000 + +Signed-off-by: Kever Yang +--- + configs/evb-rk3399_defconfig | 1 - + configs/firefly-rk3399_defconfig | 1 - + configs/khadas-edge-captain-rk3399_defconfig | 1 - + configs/khadas-edge-rk3399_defconfig | 1 - + configs/khadas-edge-v-rk3399_defconfig | 1 - + configs/leez-rk3399_defconfig | 1 - + configs/nanopc-t4-rk3399_defconfig | 1 - + configs/nanopi-m4-rk3399_defconfig | 1 - + configs/nanopi-neo4-rk3399_defconfig | 1 - + configs/orangepi-rk3399_defconfig | 1 - + configs/roc-rk3399-pc_defconfig | 1 - + configs/rock-pi-4-rk3399_defconfig | 1 - + configs/rockpro64-rk3399_defconfig | 1 - + 13 files changed, 13 deletions(-) + +diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig +index a0d215a5f18..48836c7b887 100644 +--- a/configs/evb-rk3399_defconfig ++++ b/configs/evb-rk3399_defconfig +@@ -2,7 +2,6 @@ CONFIG_ARM=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y +-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 +diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig +index d0226314651..4828f0ccaca 100644 +--- a/configs/firefly-rk3399_defconfig ++++ b/configs/firefly-rk3399_defconfig +@@ -2,7 +2,6 @@ CONFIG_ARM=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y +-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 +diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig +index acfd91dbe7a..19e13502852 100644 +--- a/configs/khadas-edge-captain-rk3399_defconfig ++++ b/configs/khadas-edge-captain-rk3399_defconfig +@@ -2,7 +2,6 @@ CONFIG_ARM=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y +-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 +diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig +index b71fd3a286e..c10f710b42c 100644 +--- a/configs/khadas-edge-rk3399_defconfig ++++ b/configs/khadas-edge-rk3399_defconfig +@@ -2,7 +2,6 @@ CONFIG_ARM=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y +-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 +diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig +index 0a789872dc3..9b3b6bf634a 100644 +--- a/configs/khadas-edge-v-rk3399_defconfig ++++ b/configs/khadas-edge-v-rk3399_defconfig +@@ -2,7 +2,6 @@ CONFIG_ARM=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y +-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 +#diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig +#index 4757aaaec44..35f3a8cfd84 100644 +#--- a/configs/leez-rk3399_defconfig +#+++ b/configs/leez-rk3399_defconfig +#@@ -2,7 +2,6 @@ CONFIG_ARM=y +# CONFIG_ARCH_ROCKCHIP=y +# CONFIG_SYS_TEXT_BASE=0x00200000 +# CONFIG_ROCKCHIP_RK3399=y +#-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 +# CONFIG_NR_DRAM_BANKS=1 +# CONFIG_SPL_STACK_R_ADDR=0x80000 +# CONFIG_DEBUG_UART_BASE=0xFF1A0000 +diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig +index 1d4c8f8a024..b266b3ff419 100644 +--- a/configs/nanopc-t4-rk3399_defconfig ++++ b/configs/nanopc-t4-rk3399_defconfig +@@ -2,7 +2,6 @@ CONFIG_ARM=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y +-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 +diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig +index 7375b758a27..c78dd106e8c 100644 +--- a/configs/nanopi-m4-rk3399_defconfig ++++ b/configs/nanopi-m4-rk3399_defconfig +@@ -2,7 +2,6 @@ CONFIG_ARM=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y +-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 +diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig +index 874ee5efb61..48413cfe61d 100644 +--- a/configs/nanopi-neo4-rk3399_defconfig ++++ b/configs/nanopi-neo4-rk3399_defconfig +@@ -2,7 +2,6 @@ CONFIG_ARM=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y +-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 +diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig +index 7b02c59f08d..28f5ae18b17 100644 +--- a/configs/orangepi-rk3399_defconfig ++++ b/configs/orangepi-rk3399_defconfig +@@ -2,7 +2,6 @@ CONFIG_ARM=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y +-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 +diff --git a/configs/roc-rk3399-pc_defconfig b/configs/roc-rk3399-pc_defconfig +index 28b18333d78..79c128a9292 100644 +--- a/configs/roc-rk3399-pc_defconfig ++++ b/configs/roc-rk3399-pc_defconfig +@@ -2,7 +2,6 @@ CONFIG_ARM=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y +-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 +diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig +index 554945dd190..dbff125bf1d 100644 +--- a/configs/rock-pi-4-rk3399_defconfig ++++ b/configs/rock-pi-4-rk3399_defconfig +@@ -2,7 +2,6 @@ CONFIG_ARM=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y +-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 +diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig +index 22b8bc503b4..e8765333049 100644 +--- a/configs/rockpro64-rk3399_defconfig ++++ b/configs/rockpro64-rk3399_defconfig +@@ -2,7 +2,6 @@ CONFIG_ARM=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y +-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 diff --git a/patch/u-boot/u-boot-rk3399/rk3399-update-spl-max-size.patch b/patch/u-boot/u-boot-rk3399/rk3399-update-spl-max-size.patch new file mode 100644 index 000000000..50a87f5d5 --- /dev/null +++ b/patch/u-boot/u-boot-rk3399/rk3399-update-spl-max-size.patch @@ -0,0 +1,59 @@ +Patch adaped to exclude rk3288 and rk3328 for now + +From 5c0e65007979a743a5776440b06ae9ae5a475e84 Mon Sep 17 00:00:00 2001 +From: Kever Yang +Date: Fri, 18 Oct 2019 15:54:16 +0800 +Subject: [PATCH] rockchip: config: update CONFIG_SPL_MAX_SIZE for 64bit CPUs + +Since we move the ATF bl31 entry for 64bit CPUs to 0x40000, we need to +limit the SPL size in 0x40000(start from 0) so that we don't need to do +the relocate for ATF loading. +Note that there will be separate BSS, STACK and MALLOC heap, so the size +0x40000(256KB) should be enough for SPL text. + +Signed-off-by: Kever Yang +--- + include/configs/rk3328_common.h | 2 +- + include/configs/rk3368_common.h | 2 +- + include/configs/rk3399_common.h | 2 +- + 3 files changed, 3 insertions(+), 3 deletions(-) + +#diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h +#index 3ff3331c808..e51e1b0e0e7 100644 +#--- a/include/configs/rk3328_common.h +#+++ b/include/configs/rk3328_common.h +#@@ -18,7 +18,7 @@ +# #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 +# #define CONFIG_SYS_LOAD_ADDR 0x00800800 +# #define CONFIG_SPL_STACK 0x00400000 +#-#define CONFIG_SPL_MAX_SIZE 0x100000 +#+#define CONFIG_SPL_MAX_SIZE 0x40000 +# #define CONFIG_SPL_BSS_START_ADDR 0x2000000 +# #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 +# +#diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h +#index e4b2114a0dd..e57d0efa7f9 100644 +#--- a/include/configs/rk3368_common.h +#+++ b/include/configs/rk3368_common.h +#@@ -27,7 +27,7 @@ +# #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 +# #define CONFIG_SYS_LOAD_ADDR 0x00280000 +# +#-#define CONFIG_SPL_MAX_SIZE 0x60000 +#+#define CONFIG_SPL_MAX_SIZE 0x40000 +# #define CONFIG_SPL_BSS_START_ADDR 0x400000 +# #define CONFIG_SPL_BSS_MAX_SIZE 0x20000 +# #define CONFIG_SPL_STACK 0x00188000 +diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h +index 126c34763ea..7331c6dc026 100644 +--- a/include/configs/rk3399_common.h ++++ b/include/configs/rk3399_common.h +@@ -21,7 +21,7 @@ + + #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT) + #define CONFIG_SPL_STACK 0x00400000 +-#define CONFIG_SPL_MAX_SIZE 0x100000 ++#define CONFIG_SPL_MAX_SIZE 0x40000 + #define CONFIG_SPL_BSS_START_ADDR 0x00400000 + #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 + #else diff --git a/patch/u-boot/u-boot-rk3399/rk3399-update-spl-stack-r-addr.patch b/patch/u-boot/u-boot-rk3399/rk3399-update-spl-stack-r-addr.patch new file mode 100644 index 000000000..11c16fdfb --- /dev/null +++ b/patch/u-boot/u-boot-rk3399/rk3399-update-spl-stack-r-addr.patch @@ -0,0 +1,255 @@ +Patch adapted to disable leez config for now + +From 9ff5697175953fcb3d623ec3579a5a0d2b433b69 Mon Sep 17 00:00:00 2001 +From: Kever Yang +Date: Fri, 18 Oct 2019 15:54:15 +0800 +Subject: [PATCH] rockchip: rk3399: update SPL_STACK_R_ADDR + +Use the same SPL_STACK_R_ADDR in Kconfig instead of each board config; +default to 0x4000000(64MB) instead of 0x80000(512KB) for this address +can support all the SoCs including those may have only 64MB memory, and +also reserve enough space for atf, kernel(in falcon mode) loading. + +After the ATF entry move to 0x40000, the stack from 0x80000 may be override +when loading ATF bl31. + +Signed-off-by: Kever Yang +--- + arch/arm/mach-rockchip/rk3399/Kconfig | 3 +++ + configs/chromebook_bob_defconfig | 1 - + configs/evb-rk3399_defconfig | 1 - + configs/ficus-rk3399_defconfig | 1 - + configs/firefly-rk3399_defconfig | 1 - + configs/khadas-edge-captain-rk3399_defconfig | 1 - + configs/khadas-edge-rk3399_defconfig | 1 - + configs/khadas-edge-v-rk3399_defconfig | 1 - + configs/leez-rk3399_defconfig | 1 - + configs/nanopc-t4-rk3399_defconfig | 1 - + configs/nanopi-m4-rk3399_defconfig | 1 - + configs/nanopi-neo4-rk3399_defconfig | 1 - + configs/orangepi-rk3399_defconfig | 1 - + configs/puma-rk3399_defconfig | 1 - + configs/roc-rk3399-pc_defconfig | 1 - + configs/rock-pi-4-rk3399_defconfig | 1 - + configs/rock960-rk3399_defconfig | 1 - + configs/rockpro64-rk3399_defconfig | 1 - + 18 files changed, 3 insertions(+), 17 deletions(-) + +diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig +index 6660d05349b..f781eacd163 100644 +--- a/arch/arm/mach-rockchip/rk3399/Kconfig ++++ b/arch/arm/mach-rockchip/rk3399/Kconfig +@@ -91,6 +91,9 @@ config TPL_STACK + config TPL_TEXT_BASE + default 0xff8c2000 + ++config SPL_STACK_R_ADDR ++ default 0x04000000 ++ + source "board/rockchip/evb_rk3399/Kconfig" + source "board/theobroma-systems/puma_rk3399/Kconfig" + source "board/vamrs/rock960_rk3399/Kconfig" +diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig +index 8059c633cec..b6e31a4c499 100644 +--- a/configs/chromebook_bob_defconfig ++++ b/configs/chromebook_bob_defconfig +@@ -8,7 +8,6 @@ CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 + # CONFIG_SPL_MMC_SUPPORT is not set + CONFIG_TARGET_CHROMEBOOK_BOB=y + CONFIG_NR_DRAM_BANKS=1 +-CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xff1a0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig +index 48836c7b887..c1d7d613a9e 100644 +--- a/configs/evb-rk3399_defconfig ++++ b/configs/evb-rk3399_defconfig +@@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y + CONFIG_NR_DRAM_BANKS=1 +-CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y +diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig +index 05bbfbf381a..0dcc9a760d6 100644 +--- a/configs/ficus-rk3399_defconfig ++++ b/configs/ficus-rk3399_defconfig +@@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y + CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 + CONFIG_TARGET_ROCK960_RK3399=y +-CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y +diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig +index 4828f0ccaca..ba57fbd5278 100644 +--- a/configs/firefly-rk3399_defconfig ++++ b/configs/firefly-rk3399_defconfig +@@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y + CONFIG_NR_DRAM_BANKS=1 +-CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y +diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig +index 19e13502852..80d92e1aad3 100644 +--- a/configs/khadas-edge-captain-rk3399_defconfig ++++ b/configs/khadas-edge-captain-rk3399_defconfig +@@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y + CONFIG_NR_DRAM_BANKS=1 +-CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y +diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig +index c10f710b42c..9ba25b7d57c 100644 +--- a/configs/khadas-edge-rk3399_defconfig ++++ b/configs/khadas-edge-rk3399_defconfig +@@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y + CONFIG_NR_DRAM_BANKS=1 +-CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y +diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig +index 9b3b6bf634a..424dec1fbac 100644 +--- a/configs/khadas-edge-v-rk3399_defconfig ++++ b/configs/khadas-edge-v-rk3399_defconfig +@@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y + CONFIG_NR_DRAM_BANKS=1 +-CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y +#diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig +#index 35f3a8cfd84..c671879d9a7 100644 +#--- a/configs/leez-rk3399_defconfig +#+++ b/configs/leez-rk3399_defconfig +#@@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y +# CONFIG_SYS_TEXT_BASE=0x00200000 +# CONFIG_ROCKCHIP_RK3399=y +# CONFIG_NR_DRAM_BANKS=1 +#-CONFIG_SPL_STACK_R_ADDR=0x80000 +# CONFIG_DEBUG_UART_BASE=0xFF1A0000 +# CONFIG_DEBUG_UART_CLOCK=24000000 +# CONFIG_DEBUG_UART=y +diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig +index b266b3ff419..ae09273a486 100644 +--- a/configs/nanopc-t4-rk3399_defconfig ++++ b/configs/nanopc-t4-rk3399_defconfig +@@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y + CONFIG_NR_DRAM_BANKS=1 +-CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y +diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig +index c78dd106e8c..e1a61e5a574 100644 +--- a/configs/nanopi-m4-rk3399_defconfig ++++ b/configs/nanopi-m4-rk3399_defconfig +@@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y + CONFIG_NR_DRAM_BANKS=1 +-CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y +diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig +index 48413cfe61d..c3a592d8fe9 100644 +--- a/configs/nanopi-neo4-rk3399_defconfig ++++ b/configs/nanopi-neo4-rk3399_defconfig +@@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y + CONFIG_NR_DRAM_BANKS=1 +-CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y +diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig +index 28f5ae18b17..296fd5f0a0f 100644 +--- a/configs/orangepi-rk3399_defconfig ++++ b/configs/orangepi-rk3399_defconfig +@@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y + CONFIG_NR_DRAM_BANKS=1 +-CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y +diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig +index 30b0f4ac6c6..351b0ea3d0d 100644 +--- a/configs/puma-rk3399_defconfig ++++ b/configs/puma-rk3399_defconfig +@@ -6,7 +6,6 @@ CONFIG_ROCKCHIP_RK3399=y + CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0 + CONFIG_TARGET_PUMA_RK3399=y + CONFIG_NR_DRAM_BANKS=1 +-CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF180000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y +diff --git a/configs/roc-rk3399-pc_defconfig b/configs/roc-rk3399-pc_defconfig +index 79c128a9292..809f5222368 100644 +--- a/configs/roc-rk3399-pc_defconfig ++++ b/configs/roc-rk3399-pc_defconfig +@@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y + CONFIG_NR_DRAM_BANKS=1 +-CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y +diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig +index dbff125bf1d..f4bb3818cea 100644 +--- a/configs/rock-pi-4-rk3399_defconfig ++++ b/configs/rock-pi-4-rk3399_defconfig +@@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y + CONFIG_NR_DRAM_BANKS=1 +-CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y +diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig +index cb3c68db6bd..0d6c55ce745 100644 +--- a/configs/rock960-rk3399_defconfig ++++ b/configs/rock960-rk3399_defconfig +@@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y + CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 + CONFIG_TARGET_ROCK960_RK3399=y +-CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y +diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig +index e8765333049..68f0dca7b2c 100644 +--- a/configs/rockpro64-rk3399_defconfig ++++ b/configs/rockpro64-rk3399_defconfig +@@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_ROCKCHIP_RK3399=y + CONFIG_NR_DRAM_BANKS=1 +-CONFIG_SPL_STACK_R_ADDR=0x80000 + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y diff --git a/patch/u-boot/u-boot-rk3399/sdmmc-force-fifo-mode-in-spl.patch b/patch/u-boot/u-boot-rk3399/sdmmc-force-fifo-mode-in-spl.patch new file mode 100644 index 000000000..9b7354f97 --- /dev/null +++ b/patch/u-boot/u-boot-rk3399/sdmmc-force-fifo-mode-in-spl.patch @@ -0,0 +1,22 @@ +From b0693aeb9ceab57ffc9d9f4ceca610bd82d5ca07 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Kamil=20Trzci=C5=84ski?= +Date: Mon, 21 May 2018 02:00:19 +0200 +Subject: [PATCH] ayufan: rock64: for SPL build always use fifo-mode + +Change-Id: I9ac012ce4aaf03a151f7c5c818829d631efdd7ed +diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c +index fc0f0fad76..d1f26e41fe 100644 +--- a/drivers/mmc/rockchip_dw_mmc.c ++++ b/drivers/mmc/rockchip_dw_mmc.c +@@ -70,7 +70,11 @@ static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev) + + if (priv->fifo_depth < 0) + return -EINVAL; ++#ifdef CONFIG_SPL_BUILD ++ priv->fifo_mode = true; // always force fifo mode ++#else + priv->fifo_mode = dev_read_bool(dev, "fifo-mode"); ++#endif + + /* + * 'clock-freq-min-max' is deprecated