From 195de287f2fe68baf510ce77b28b4a129aa4d24e Mon Sep 17 00:00:00 2001 From: zador-blood-stained Date: Mon, 12 Sep 2016 21:22:32 +0300 Subject: [PATCH] Update mainline u-boot version to v2016.09 --- config/boards/orangepilite.conf | 2 +- config/boards/orangepipcplus.conf | 2 +- config/boards/orangepiplus2e.conf | 2 +- configuration.sh | 11 +++- .../u-boot-default/add-emmc-orangepi.patch | 12 ---- ...-boot-02-support-cheap-mmc.patch.disabled} | 0 ...une-h3-dram-pll-to-improve-lock-time.patch | 44 --------------- .../u-boot/u-boot-dev/add-emmc-orangepi.patch | 55 ------------------- .../u-boot-02-support-cheap-mmc.patch | 12 ---- ...une-h3-dram-pll-to-improve-lock-time.patch | 44 --------------- 10 files changed, 13 insertions(+), 171 deletions(-) delete mode 100644 patch/u-boot/u-boot-default/add-emmc-orangepi.patch rename patch/u-boot/u-boot-default/{u-boot-02-support-cheap-mmc.patch => u-boot-02-support-cheap-mmc.patch.disabled} (100%) delete mode 100644 patch/u-boot/u-boot-default/u-boot-98-tune-h3-dram-pll-to-improve-lock-time.patch delete mode 100644 patch/u-boot/u-boot-dev/add-emmc-orangepi.patch delete mode 100644 patch/u-boot/u-boot-dev/u-boot-02-support-cheap-mmc.patch delete mode 100644 patch/u-boot/u-boot-dev/u-boot-98-tune-h3-dram-pll-to-improve-lock-time.patch diff --git a/config/boards/orangepilite.conf b/config/boards/orangepilite.conf index 5950d239c..3205d87bf 100644 --- a/config/boards/orangepilite.conf +++ b/config/boards/orangepilite.conf @@ -1,7 +1,7 @@ # H3 quad core 512MB RAM WiFi BOARD_NAME="Orange Pi Lite" LINUXFAMILY=sun8i -BOOTCONFIG=orangepi_one_defconfig +BOOTCONFIG=orangepi_lite_defconfig MODULES="8189fs #gpio_sunxi #w1-sunxi #w1-gpio #w1-therm #gc2035 #vfe_v4l2 sunxi-cir g_serial" MODULES_NEXT="8189fs" CPUMIN=480000 diff --git a/config/boards/orangepipcplus.conf b/config/boards/orangepipcplus.conf index 73bb30c25..da8a4aade 100644 --- a/config/boards/orangepipcplus.conf +++ b/config/boards/orangepipcplus.conf @@ -1,7 +1,7 @@ # H3 quad core 1GB RAM WiFi eMMC BOARD_NAME="Orange Pi PC +" LINUXFAMILY=sun8i -BOOTCONFIG=orangepi_pc_defconfig +BOOTCONFIG=orangepi_pc_plus_defconfig MODULES="8189fs #gpio_sunxi #w1-sunxi #w1-gpio #w1-therm #gc2035 #vfe_v4l2 #sunxi-cir" MODULES_NEXT="8189fs" CPUMIN=480000 diff --git a/config/boards/orangepiplus2e.conf b/config/boards/orangepiplus2e.conf index 06c585829..97e796a98 100644 --- a/config/boards/orangepiplus2e.conf +++ b/config/boards/orangepiplus2e.conf @@ -1,7 +1,7 @@ # H3 quad core 2GB RAM WiFi eMMC BOARD_NAME="Orange Pi+ 2E" LINUXFAMILY=sun8i -BOOTCONFIG=orangepi_pc_defconfig +BOOTCONFIG=orangepi_plus2e_defconfig MODULES="8189fs #gpio_sunxi #w1-sunxi #w1-gpio #w1-therm #gc2035 #vfe_v4l2 #sunxi-cir" MODULES_NEXT="8189fs" CPUMIN=480000 diff --git a/configuration.sh b/configuration.sh index f4b82ec1e..a99bdd464 100644 --- a/configuration.sh +++ b/configuration.sh @@ -34,7 +34,7 @@ MAINLINE_KERNEL_DIR='linux-vanilla' MAINLINE_UBOOT_SOURCE='git://git.denx.de/u-boot.git' #MAINLINE_UBOOT_BRANCH="v$(git ls-remote git://git.denx.de/u-boot.git | grep -v rc | grep -v '\^' | tail -1 | cut -d'v' -f 2)" -MAINLINE_UBOOT_BRANCH='tag:v2016.07' +MAINLINE_UBOOT_BRANCH='tag:v2016.09' MAINLINE_UBOOT_DIR='u-boot' # Let's set defalt data if not defined in board configuration above @@ -149,7 +149,16 @@ PACKAGE_LIST="$PACKAGE_LIST $PACKAGE_LIST_RELEASE $PACKAGE_LIST_ADDITIONAL" # debug cat <<-EOF >> $DEST/debug/output.log +## BUILD SCRIPT ENVIRONMENT + +Version: $(cd $SRC/lib; git rev-parse @) + ## BUILD CONFIGURATION + +Build target: +Board: $BOARD +Branch: $BRANCH + Kernel configuration: Repository: $KERNELSOURCE Branch: $KERNELBRANCH diff --git a/patch/u-boot/u-boot-default/add-emmc-orangepi.patch b/patch/u-boot/u-boot-default/add-emmc-orangepi.patch deleted file mode 100644 index 6ae4911c6..000000000 --- a/patch/u-boot/u-boot-default/add-emmc-orangepi.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig ---- a/configs/orangepi_pc_defconfig -+++ b/configs/orangepi_pc_defconfig -@@ -4,6 +4,8 @@ CONFIG_MACH_SUN8I_H3=y - CONFIG_DRAM_CLK=624 - CONFIG_DRAM_ZQ=3881979 - CONFIG_DRAM_ODT_EN=y -+CONFIG_MMC0_CD_PIN="PF6" -+CONFIG_MMC_SUNXI_SLOT_EXTRA=2 - # CONFIG_VIDEO is not set - CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc" - # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/patch/u-boot/u-boot-default/u-boot-02-support-cheap-mmc.patch b/patch/u-boot/u-boot-default/u-boot-02-support-cheap-mmc.patch.disabled similarity index 100% rename from patch/u-boot/u-boot-default/u-boot-02-support-cheap-mmc.patch rename to patch/u-boot/u-boot-default/u-boot-02-support-cheap-mmc.patch.disabled diff --git a/patch/u-boot/u-boot-default/u-boot-98-tune-h3-dram-pll-to-improve-lock-time.patch b/patch/u-boot/u-boot-default/u-boot-98-tune-h3-dram-pll-to-improve-lock-time.patch deleted file mode 100644 index 61b75193c..000000000 --- a/patch/u-boot/u-boot-default/u-boot-98-tune-h3-dram-pll-to-improve-lock-time.patch +++ /dev/null @@ -1,44 +0,0 @@ -diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h -index d4dff1e..be9fcfd 100644 ---- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h -+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h -@@ -116,7 +116,9 @@ struct sunxi_ccm_reg { - u32 mipi_bias_cfg; /* 0x240 MIPI Bias config */ - u32 pll9_bias_cfg; /* 0x244 PLL9 Bias config */ - u32 pll10_bias_cfg; /* 0x248 PLL10 Bias config */ -- u32 reserved21[13]; -+ u32 reserved21[5]; -+ u32 pll5_tuning_cfg; /* 0x260 PLL5 Tuning config */ -+ u32 reserved21_5[7]; - u32 pll1_pattern_cfg; /* 0x280 PLL1 Pattern config */ - u32 pll2_pattern_cfg; /* 0x284 PLL2 Pattern config */ - u32 pll3_pattern_cfg; /* 0x288 PLL3 Pattern config */ -@@ -223,6 +225,11 @@ struct sunxi_ccm_reg { - #define CCM_PLL11_CTRL_UPD (0x1 << 30) - #define CCM_PLL11_CTRL_EN (0x1 << 31) - -+#define CCM_PLL5_TUN_LOCK_TIME(x) (((x) & 0x7) << 24) -+#define CCM_PLL5_TUN_LOCK_TIME_MASK CCM_PLL5_TUN_LOCK_TIME(0x7) -+#define CCM_PLL5_TUN_INIT_FREQ(x) (((x) & 0x7f) << 16) -+#define CCM_PLL5_TUN_INIT_FREQ_MASK CCM_PLL5_TUN_INIT_FREQ(0x7f) -+ - #if defined(CONFIG_MACH_SUN50I) - /* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */ - #define AHB1_ABP1_DIV_DEFAULT 0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */ -diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c -index 15272c9..ed8cd9b 100644 ---- a/arch/arm/mach-sunxi/clock_sun6i.c -+++ b/arch/arm/mach-sunxi/clock_sun6i.c -@@ -148,6 +148,12 @@ void clock_set_pll5(unsigned int clk, bool sigma_delta_enable) - const int max_n = 32; - int k = 1, m = 2; - -+#ifdef CONFIG_MACH_SUN8I_H3 -+ clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK | -+ CCM_PLL5_TUN_INIT_FREQ_MASK, -+ CCM_PLL5_TUN_LOCK_TIME(2) | CCM_PLL5_TUN_INIT_FREQ(16)); -+#endif -+ - if (sigma_delta_enable) - writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg); - diff --git a/patch/u-boot/u-boot-dev/add-emmc-orangepi.patch b/patch/u-boot/u-boot-dev/add-emmc-orangepi.patch deleted file mode 100644 index fe0fbc1a8..000000000 --- a/patch/u-boot/u-boot-dev/add-emmc-orangepi.patch +++ /dev/null @@ -1,55 +0,0 @@ -diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/dts/sun8i-h3-orangepi-pc.dts -index 30ccca0..6475652 100644 ---- a/arch/arm/dts/sun8i-h3-orangepi-pc.dts -+++ b/arch/arm/dts/sun8i-h3-orangepi-pc.dts -@@ -126,6 +126,15 @@ - status = "okay"; - }; - -+&mmc2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc2_8bit_pins>; -+ vmmc-supply = <®_vcc3v0>; -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -+ - &ohci1 { - status = "okay"; - }; -diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi -index c2f63c5..4a4926b 100644 ---- a/arch/arm/dts/sun8i-h3.dtsi -+++ b/arch/arm/dts/sun8i-h3.dtsi -@@ -530,6 +530,16 @@ - allwinner,drive = ; - allwinner,pull = ; - }; -+ -+ mmc2_8bit_pins: mmc2_8bit { -+ allwinner,pins = "PC5", "PC6", "PC8", -+ "PC9", "PC10", "PC11", -+ "PC12", "PC13", "PC14", -+ "PC15", "PC16"; -+ allwinner,function = "mmc2"; -+ allwinner,drive = ; -+ allwinner,pull = ; -+ }; - }; - - ahb_rst: reset@01c202c0 { -diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig -index 7eaa795..cca89ec 100644 ---- a/configs/orangepi_pc_defconfig -+++ b/configs/orangepi_pc_defconfig -@@ -7,6 +7,9 @@ CONFIG_DRAM_ODT_EN=y - # CONFIG_VIDEO is not set - CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc" - # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -+CONFIG_CMD_MMC=y -+CONFIG_MMC0_CD_PIN="PF6" -+CONFIG_MMC_SUNXI_SLOT_EXTRA=2 - CONFIG_SPL=y - # CONFIG_CMD_IMLS is not set - # CONFIG_CMD_FLASH is not set diff --git a/patch/u-boot/u-boot-dev/u-boot-02-support-cheap-mmc.patch b/patch/u-boot/u-boot-dev/u-boot-02-support-cheap-mmc.patch deleted file mode 100644 index 678dff164..000000000 --- a/patch/u-boot/u-boot-dev/u-boot-02-support-cheap-mmc.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -Nur a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c ---- a/drivers/mmc/sunxi_mmc.c 2016-02-25 10:30:30.000000000 +0800 -+++ b//drivers/mmc/sunxi_mmc.c 2016-02-25 10:46:07.723851155 +0800 - -@@ -269,6 +269,6 @@ - unsigned i; - unsigned *buff = (unsigned int *)(reading ? data->dest : data->src); - unsigned byte_cnt = data->blocksize * data->blocks; -- unsigned timeout_msecs = byte_cnt >> 8; -+ unsigned timeout_msecs = byte_cnt >> 6; - if (timeout_msecs < 2000) - timeout_msecs = 2000; \ No newline at end of file diff --git a/patch/u-boot/u-boot-dev/u-boot-98-tune-h3-dram-pll-to-improve-lock-time.patch b/patch/u-boot/u-boot-dev/u-boot-98-tune-h3-dram-pll-to-improve-lock-time.patch deleted file mode 100644 index 61b75193c..000000000 --- a/patch/u-boot/u-boot-dev/u-boot-98-tune-h3-dram-pll-to-improve-lock-time.patch +++ /dev/null @@ -1,44 +0,0 @@ -diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h -index d4dff1e..be9fcfd 100644 ---- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h -+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h -@@ -116,7 +116,9 @@ struct sunxi_ccm_reg { - u32 mipi_bias_cfg; /* 0x240 MIPI Bias config */ - u32 pll9_bias_cfg; /* 0x244 PLL9 Bias config */ - u32 pll10_bias_cfg; /* 0x248 PLL10 Bias config */ -- u32 reserved21[13]; -+ u32 reserved21[5]; -+ u32 pll5_tuning_cfg; /* 0x260 PLL5 Tuning config */ -+ u32 reserved21_5[7]; - u32 pll1_pattern_cfg; /* 0x280 PLL1 Pattern config */ - u32 pll2_pattern_cfg; /* 0x284 PLL2 Pattern config */ - u32 pll3_pattern_cfg; /* 0x288 PLL3 Pattern config */ -@@ -223,6 +225,11 @@ struct sunxi_ccm_reg { - #define CCM_PLL11_CTRL_UPD (0x1 << 30) - #define CCM_PLL11_CTRL_EN (0x1 << 31) - -+#define CCM_PLL5_TUN_LOCK_TIME(x) (((x) & 0x7) << 24) -+#define CCM_PLL5_TUN_LOCK_TIME_MASK CCM_PLL5_TUN_LOCK_TIME(0x7) -+#define CCM_PLL5_TUN_INIT_FREQ(x) (((x) & 0x7f) << 16) -+#define CCM_PLL5_TUN_INIT_FREQ_MASK CCM_PLL5_TUN_INIT_FREQ(0x7f) -+ - #if defined(CONFIG_MACH_SUN50I) - /* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */ - #define AHB1_ABP1_DIV_DEFAULT 0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */ -diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c -index 15272c9..ed8cd9b 100644 ---- a/arch/arm/mach-sunxi/clock_sun6i.c -+++ b/arch/arm/mach-sunxi/clock_sun6i.c -@@ -148,6 +148,12 @@ void clock_set_pll5(unsigned int clk, bool sigma_delta_enable) - const int max_n = 32; - int k = 1, m = 2; - -+#ifdef CONFIG_MACH_SUN8I_H3 -+ clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK | -+ CCM_PLL5_TUN_INIT_FREQ_MASK, -+ CCM_PLL5_TUN_LOCK_TIME(2) | CCM_PLL5_TUN_INIT_FREQ(16)); -+#endif -+ - if (sigma_delta_enable) - writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg); -