diff --git a/config/sources/cubox.conf b/config/sources/cubox.conf
index dc6ee6bc8..e05595d3f 100644
--- a/config/sources/cubox.conf
+++ b/config/sources/cubox.conf
@@ -4,6 +4,7 @@ BOOTBRANCH='imx6'
 BOOTSOURCE='u-boot-cubox'
 
 UBOOT_NEEDS_GCC='< 5.0'
+KERNEL_NEEDS_GCC='< 5.0'
 
 case $BRANCH in
 	default)
diff --git a/patch/u-boot/u-boot-cubox-default/broken_uboot.patch b/patch/u-boot/u-boot-cubox-default/broken_uboot.patch
new file mode 100644
index 000000000..21def986c
--- /dev/null
+++ b/patch/u-boot/u-boot-cubox-default/broken_uboot.patch
@@ -0,0 +1,100 @@
+diff --git a/board/solidrun/mx6_cubox-i/mx6_cubox-i.c b/board/solidrun/mx6_cubox-i/mx6_cubox-i.c
+old mode 100644
+new mode 100755
+index 7c49f4e..6c92c1d
+--- a/board/solidrun/mx6_cubox-i/mx6_cubox-i.c
++++ b/board/solidrun/mx6_cubox-i/mx6_cubox-i.c
+@@ -78,9 +78,85 @@ DECLARE_GLOBAL_DATA_PTR;
+ 
+ int hb_cuboxi_ = 0; /* 2 is HummingBoard2, 1 is HummingBoard, 0 is CuBox-i */
+ 
++/*
++ * Check memory range for valid RAM. A simple memory test determines
++ * the actually available RAM size between addresses `base' and
++ * `base + maxsize'.
++ * This algorithm uses value MEM_STRIDE (like 128MByte) steps instead of the one bit right shift
++ * algorithm originally used in get_ram_size() since a 4GByte memory setup in
++ * a 32bit architecture forbids addressing all the memory, so right shift
++ * algorithm that assumes total memory size is exponents of 2 would fail.
++ */
++#define MEM_STRIDE 0x04000000
++static u32 get_ram_size_stride_test(u32 *base, u32 maxsize)
++{
++	volatile u32 *addr;
++	u32            save[64];
++	u32            cnt;
++	long           size;
++	u32		size_tmp;
++	int            i = 0;
++	cnt = maxsize;
++	/* First save the data */
++	for (cnt = 0; cnt < maxsize; cnt += MEM_STRIDE) {
++		addr = (volatile u32 *)((u32)base + cnt);	/* pointer arith! */
++		sync ();
++		save[i] = *addr;
++		i++;
++		sync ();
++	}
++	/* First write a signature */
++	* (volatile u32 *) base = 0x12345678;
++	for (size_tmp = MEM_STRIDE; size_tmp < (u32)maxsize; size_tmp += MEM_STRIDE) {
++		long tmp;
++		* (volatile u32 *)((u32)base + (u32)size_tmp) = (u32)size_tmp;
++		sync ();
++		tmp = * (volatile u32 *)((u32)base + (u32)size);
++		if (tmp == size_tmp) { /* Looks we reached overlapping address */
++			break;
++		}
++	}
++	/* Resotre the data */
++	for (cnt = (maxsize - MEM_STRIDE); i > 0; cnt -= MEM_STRIDE) {
++		i--;
++		addr = (volatile u32 *)((u32)base + cnt);	/* pointer arith! */
++		sync ();
++		* addr = save[i];
++		sync ();
++	}
++	maxsize = size_tmp;
++
++	return (maxsize);
++}
++
+ int dram_init(void)
+ {
+-	gd->ram_size = imx_ddr_size();
++	uint cpurev, imxtype;
++	u32 sdram_size;
++
++	cpurev = get_cpu_rev();
++	imxtype = (cpurev & 0xFF000) >> 12;
++
++	switch (imxtype){
++	case MXC_CPU_MX6SOLO:
++		sdram_size = 0x20000000;
++		break;
++	case MXC_CPU_MX6Q:
++	{
++		/* Read first the snoop control unit config register */
++		u32 scu_config = *(u32 *)(SCU_BASE_ADDR + 0x4);
++		if ((scu_config & 0x3) == 0x3) /* Quad core */
++			sdram_size = 0xf0000000;
++		else /* Dual core */
++			sdram_size = 0x40000000;
++		break;
++	}
++	case MXC_CPU_MX6DL:
++	default:
++		sdram_size = 0x40000000;
++		break;
++	}
++	gd->ram_size = get_ram_size_stride_test((void *)PHYS_SDRAM, sdram_size);
+ 
+ 	return 0;
+ }
+@@ -624,4 +700,4 @@ int board_late_init(void)
+ #endif
+ 
+ 	return 0;
+-}
++}
+\ No newline at end of file
diff --git a/patch/u-boot/u-boot-cubox-dev/broken_uboot.patch b/patch/u-boot/u-boot-cubox-dev/broken_uboot.patch
new file mode 100644
index 000000000..21def986c
--- /dev/null
+++ b/patch/u-boot/u-boot-cubox-dev/broken_uboot.patch
@@ -0,0 +1,100 @@
+diff --git a/board/solidrun/mx6_cubox-i/mx6_cubox-i.c b/board/solidrun/mx6_cubox-i/mx6_cubox-i.c
+old mode 100644
+new mode 100755
+index 7c49f4e..6c92c1d
+--- a/board/solidrun/mx6_cubox-i/mx6_cubox-i.c
++++ b/board/solidrun/mx6_cubox-i/mx6_cubox-i.c
+@@ -78,9 +78,85 @@ DECLARE_GLOBAL_DATA_PTR;
+ 
+ int hb_cuboxi_ = 0; /* 2 is HummingBoard2, 1 is HummingBoard, 0 is CuBox-i */
+ 
++/*
++ * Check memory range for valid RAM. A simple memory test determines
++ * the actually available RAM size between addresses `base' and
++ * `base + maxsize'.
++ * This algorithm uses value MEM_STRIDE (like 128MByte) steps instead of the one bit right shift
++ * algorithm originally used in get_ram_size() since a 4GByte memory setup in
++ * a 32bit architecture forbids addressing all the memory, so right shift
++ * algorithm that assumes total memory size is exponents of 2 would fail.
++ */
++#define MEM_STRIDE 0x04000000
++static u32 get_ram_size_stride_test(u32 *base, u32 maxsize)
++{
++	volatile u32 *addr;
++	u32            save[64];
++	u32            cnt;
++	long           size;
++	u32		size_tmp;
++	int            i = 0;
++	cnt = maxsize;
++	/* First save the data */
++	for (cnt = 0; cnt < maxsize; cnt += MEM_STRIDE) {
++		addr = (volatile u32 *)((u32)base + cnt);	/* pointer arith! */
++		sync ();
++		save[i] = *addr;
++		i++;
++		sync ();
++	}
++	/* First write a signature */
++	* (volatile u32 *) base = 0x12345678;
++	for (size_tmp = MEM_STRIDE; size_tmp < (u32)maxsize; size_tmp += MEM_STRIDE) {
++		long tmp;
++		* (volatile u32 *)((u32)base + (u32)size_tmp) = (u32)size_tmp;
++		sync ();
++		tmp = * (volatile u32 *)((u32)base + (u32)size);
++		if (tmp == size_tmp) { /* Looks we reached overlapping address */
++			break;
++		}
++	}
++	/* Resotre the data */
++	for (cnt = (maxsize - MEM_STRIDE); i > 0; cnt -= MEM_STRIDE) {
++		i--;
++		addr = (volatile u32 *)((u32)base + cnt);	/* pointer arith! */
++		sync ();
++		* addr = save[i];
++		sync ();
++	}
++	maxsize = size_tmp;
++
++	return (maxsize);
++}
++
+ int dram_init(void)
+ {
+-	gd->ram_size = imx_ddr_size();
++	uint cpurev, imxtype;
++	u32 sdram_size;
++
++	cpurev = get_cpu_rev();
++	imxtype = (cpurev & 0xFF000) >> 12;
++
++	switch (imxtype){
++	case MXC_CPU_MX6SOLO:
++		sdram_size = 0x20000000;
++		break;
++	case MXC_CPU_MX6Q:
++	{
++		/* Read first the snoop control unit config register */
++		u32 scu_config = *(u32 *)(SCU_BASE_ADDR + 0x4);
++		if ((scu_config & 0x3) == 0x3) /* Quad core */
++			sdram_size = 0xf0000000;
++		else /* Dual core */
++			sdram_size = 0x40000000;
++		break;
++	}
++	case MXC_CPU_MX6DL:
++	default:
++		sdram_size = 0x40000000;
++		break;
++	}
++	gd->ram_size = get_ram_size_stride_test((void *)PHYS_SDRAM, sdram_size);
+ 
+ 	return 0;
+ }
+@@ -624,4 +700,4 @@ int board_late_init(void)
+ #endif
+ 
+ 	return 0;
+-}
++}
+\ No newline at end of file
diff --git a/patch/u-boot/u-boot-cubox-next/broken_uboot.patch b/patch/u-boot/u-boot-cubox-next/broken_uboot.patch
new file mode 100644
index 000000000..21def986c
--- /dev/null
+++ b/patch/u-boot/u-boot-cubox-next/broken_uboot.patch
@@ -0,0 +1,100 @@
+diff --git a/board/solidrun/mx6_cubox-i/mx6_cubox-i.c b/board/solidrun/mx6_cubox-i/mx6_cubox-i.c
+old mode 100644
+new mode 100755
+index 7c49f4e..6c92c1d
+--- a/board/solidrun/mx6_cubox-i/mx6_cubox-i.c
++++ b/board/solidrun/mx6_cubox-i/mx6_cubox-i.c
+@@ -78,9 +78,85 @@ DECLARE_GLOBAL_DATA_PTR;
+ 
+ int hb_cuboxi_ = 0; /* 2 is HummingBoard2, 1 is HummingBoard, 0 is CuBox-i */
+ 
++/*
++ * Check memory range for valid RAM. A simple memory test determines
++ * the actually available RAM size between addresses `base' and
++ * `base + maxsize'.
++ * This algorithm uses value MEM_STRIDE (like 128MByte) steps instead of the one bit right shift
++ * algorithm originally used in get_ram_size() since a 4GByte memory setup in
++ * a 32bit architecture forbids addressing all the memory, so right shift
++ * algorithm that assumes total memory size is exponents of 2 would fail.
++ */
++#define MEM_STRIDE 0x04000000
++static u32 get_ram_size_stride_test(u32 *base, u32 maxsize)
++{
++	volatile u32 *addr;
++	u32            save[64];
++	u32            cnt;
++	long           size;
++	u32		size_tmp;
++	int            i = 0;
++	cnt = maxsize;
++	/* First save the data */
++	for (cnt = 0; cnt < maxsize; cnt += MEM_STRIDE) {
++		addr = (volatile u32 *)((u32)base + cnt);	/* pointer arith! */
++		sync ();
++		save[i] = *addr;
++		i++;
++		sync ();
++	}
++	/* First write a signature */
++	* (volatile u32 *) base = 0x12345678;
++	for (size_tmp = MEM_STRIDE; size_tmp < (u32)maxsize; size_tmp += MEM_STRIDE) {
++		long tmp;
++		* (volatile u32 *)((u32)base + (u32)size_tmp) = (u32)size_tmp;
++		sync ();
++		tmp = * (volatile u32 *)((u32)base + (u32)size);
++		if (tmp == size_tmp) { /* Looks we reached overlapping address */
++			break;
++		}
++	}
++	/* Resotre the data */
++	for (cnt = (maxsize - MEM_STRIDE); i > 0; cnt -= MEM_STRIDE) {
++		i--;
++		addr = (volatile u32 *)((u32)base + cnt);	/* pointer arith! */
++		sync ();
++		* addr = save[i];
++		sync ();
++	}
++	maxsize = size_tmp;
++
++	return (maxsize);
++}
++
+ int dram_init(void)
+ {
+-	gd->ram_size = imx_ddr_size();
++	uint cpurev, imxtype;
++	u32 sdram_size;
++
++	cpurev = get_cpu_rev();
++	imxtype = (cpurev & 0xFF000) >> 12;
++
++	switch (imxtype){
++	case MXC_CPU_MX6SOLO:
++		sdram_size = 0x20000000;
++		break;
++	case MXC_CPU_MX6Q:
++	{
++		/* Read first the snoop control unit config register */
++		u32 scu_config = *(u32 *)(SCU_BASE_ADDR + 0x4);
++		if ((scu_config & 0x3) == 0x3) /* Quad core */
++			sdram_size = 0xf0000000;
++		else /* Dual core */
++			sdram_size = 0x40000000;
++		break;
++	}
++	case MXC_CPU_MX6DL:
++	default:
++		sdram_size = 0x40000000;
++		break;
++	}
++	gd->ram_size = get_ram_size_stride_test((void *)PHYS_SDRAM, sdram_size);
+ 
+ 	return 0;
+ }
+@@ -624,4 +700,4 @@ int board_late_init(void)
+ #endif
+ 
+ 	return 0;
+-}
++}
+\ No newline at end of file