mirror of
https://github.com/Fishwaldo/build.git
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Meson64 / Le Potato updates and fixes. Tnx to Neil
https://github.com/armbian/build/issues/780
This commit is contained in:
Igor Pecovnik
parent
f2f087b526
commit
1ed1c9f889
7 changed files with 510 additions and 0 deletions
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@ -0,0 +1,260 @@
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From 7c57ab968fdc0c40140f30e47bdae338c8f4dc63 Mon Sep 17 00:00:00 2001
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From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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Date: Sat, 26 Nov 2016 15:56:32 +0100
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Subject: [PATCH 61/67] phy: meson: add USB3 PHY support for Meson GXL
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This adds USB3 PHY driver found on Meson GXL and GXM SoCs.
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Unfortunately there are no datasheets available for any of these PHYs.
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Both drivers were written by reading the reference drivers provided by
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Amlogic and analyzing the registers on the kernel that was shipped with
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my board.
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Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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---
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drivers/phy/amlogic/Kconfig | 13 ++
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drivers/phy/amlogic/Makefile | 1 +
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drivers/phy/amlogic/phy-meson-gxl-usb3.c | 198 +++++++++++++++++++++++++++++++
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3 files changed, 212 insertions(+)
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create mode 100644 drivers/phy/amlogic/phy-meson-gxl-usb3.c
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diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig
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index cb8f450..5d11a3e 100644
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--- a/drivers/phy/amlogic/Kconfig
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+++ b/drivers/phy/amlogic/Kconfig
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@@ -13,6 +13,19 @@ config PHY_MESON8B_USB2
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Meson8b and GXBB SoCs.
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If unsure, say N.
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+config PHY_MESON_GXL_USB3
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+ tristate "Meson GXL and GXM USB3 PHY drivers"
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+ default ARCH_MESON
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+ depends on OF && (ARCH_MESON || COMPILE_TEST)
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+ depends on USB_SUPPORT
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+ select USB_COMMON
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+ select GENERIC_PHY
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+ select REGMAP_MMIO
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+ help
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+ Enable this to support the Meson USB3 PHY found in Meson
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+ GXL and GXM SoCs.
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+ If unsure, say N.
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+
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config PHY_MESON_GXL_USB2
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tristate "Meson GXL and GXM USB2 PHY drivers"
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default ARCH_MESON
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diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile
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index cfdc987..4fd8848 100644
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--- a/drivers/phy/amlogic/Makefile
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+++ b/drivers/phy/amlogic/Makefile
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@@ -1,2 +1,3 @@
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obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o
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obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o
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+obj-$(CONFIG_PHY_MESON_GXL_USB3) += phy-meson-gxl-usb3.o
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diff --git a/drivers/phy/amlogic/phy-meson-gxl-usb3.c b/drivers/phy/amlogic/phy-meson-gxl-usb3.c
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new file mode 100644
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index 0000000..9af5222
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--- /dev/null
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+++ b/drivers/phy/amlogic/phy-meson-gxl-usb3.c
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@@ -0,0 +1,198 @@
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+/*
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+ * Meson GXL USB3 PHY driver
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+ *
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+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
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+ */
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+
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+#include <linux/clk.h>
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+#include <linux/delay.h>
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+#include <linux/io.h>
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+#include <linux/module.h>
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+#include <linux/of_device.h>
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+#include <linux/reset.h>
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+#include <linux/regmap.h>
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+#include <linux/phy/phy.h>
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+#include <linux/platform_device.h>
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+#include <linux/usb/of.h>
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+#include <linux/workqueue.h>
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+
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+#define USB_R0 0x00
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+ #define USB_R0_P30_FSEL_SHIFT 0
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+ #define USB_R0_P30_FSEL_MASK GENMASK(5, 0)
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+ #define USB_R0_P30_PHY_RESET BIT(6)
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+ #define USB_R0_P30_TEST_POWERDOWN_HSP BIT(7)
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+ #define USB_R0_P30_TEST_POWERDOWN_SSP BIT(8)
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+ #define USB_R0_P30_ACJT_LEVEL_SHIFT 9
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+ #define USB_R0_P30_ACJT_LEVEL_MASK GENMASK(13, 9)
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+ #define USB_R0_P30_TX_BOOST_LEVEL_SHIFT 14
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+ #define USB_R0_P30_TX_BOOST_LEVEL_MASK GENMASK(16, 14)
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+ #define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17)
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+ #define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18)
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+ #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_SHIFT 19
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+ #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19)
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+ #define USB_R0_U2D_SS_SCALEDOWN_MODE_SHIFT 29
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+ #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29)
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+ #define USB_R0_U2D_ACT BIT(31)
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+
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+#define USB_R1 0x04
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+ #define USB_R1_U3H_BIGENDIAN_GS BIT(0)
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+ #define USB_R1_U3H_PME_ENABLE BIT(1)
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+ #define USB_R1_U3H_HUB_PORT_OVERCURRENT_SHIFT 2
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+ #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(6, 2)
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+ #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_SHIFT 7
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+ #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(11, 7)
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+ #define USB_R1_U3H_HOST_U2_PORT_DISABLE_SHIFT 12
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+ #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(15, 12)
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+ #define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16)
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+ #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17)
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+ #define USB_R1_U3H_HOST_MSI_ENABLE BIT(18)
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+ #define USB_R1_U3H_FLADJ_30MHZ_REG_SHIFT 19
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+ #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19)
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+ #define USB_R1_P30_PCS_TX_SWING_FULL_SHIFT 25
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+ #define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25)
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+
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+#define USB_R2 0x08
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+ #define USB_R2_P30_CR_DATA_IN_SHIFT 0
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+ #define USB_R2_P30_CR_DATA_IN_MASK GENMASK(15, 0)
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+ #define USB_R2_P30_CR_READ BIT(16)
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+ #define USB_R2_P30_CR_WRITE BIT(17)
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+ #define USB_R2_P30_CR_CAP_ADDR BIT(18)
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+ #define USB_R2_P30_CR_CAP_DATA BIT(19)
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+ #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_SHIFT 20
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+ #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20)
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+ #define USB_R2_P30_PCS_TX_DEEMPH_6DB_SHIFT 26
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+ #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26)
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+
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+#define USB_R3 0x0c
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+ #define USB_R3_P30_SSC_ENABLE BIT(0)
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+ #define USB_R3_P30_SSC_RANGE_SHIFT 1
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+ #define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1)
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+ #define USB_R3_P30_SSC_REF_CLK_SEL_SHIFT 4
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+ #define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4)
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+ #define USB_R3_P30_REF_SSP_EN BIT(13)
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+ #define USB_R3_P30_LOS_BIAS_SHIFT 16
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+ #define USB_R3_P30_LOS_BIAS_MASK GENMASK(18, 16)
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+ #define USB_R3_P30_LOS_LEVEL_SHIFT 19
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+ #define USB_R3_P30_LOS_LEVEL_MASK GENMASK(23, 19)
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+ #define USB_R3_P30_MPLL_MULTIPLIER_SHIFT 24
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+ #define USB_R3_P30_MPLL_MULTIPLIER_MASK GENMASK(30, 24)
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+
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+#define USB_R4 0x10
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+ #define USB_R4_P21_PORT_RESET_0 BIT(0)
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+ #define USB_R4_P21_SLEEP_M0 BIT(1)
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+ #define USB_R4_MEM_PD_SHIFT 2
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+ #define USB_R4_MEM_PD_MASK GENMASK(3, 2)
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+ #define USB_R4_P21_ONLY BIT(4)
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+
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+#define USB_R5 0x14
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+ #define USB_R5_ID_DIG_SYNC BIT(0)
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+ #define USB_R5_ID_DIG_REG BIT(1)
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+ #define USB_R5_ID_DIG_CFG_SHIFT 2
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+ #define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2)
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+ #define USB_R5_ID_DIG_EN_0 BIT(4)
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+ #define USB_R5_ID_DIG_EN_1 BIT(5)
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+ #define USB_R5_ID_DIG_CURR BIT(6)
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+ #define USB_R5_ID_DIG_IRQ BIT(7)
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+ #define USB_R5_ID_DIG_TH_SHIFT 8
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+ #define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8)
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+ #define USB_R5_ID_DIG_CNT_SHIFT 16
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+ #define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16)
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+
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+/* read-only register */
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+#define USB_R6 0x18
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+ #define USB_R6_P30_CR_DATA_OUT_SHIFT 0
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+ #define USB_R6_P30_CR_DATA_OUT_MASK GENMASK(15, 0)
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+ #define USB_R6_P30_CR_ACK BIT(16)
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+
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+#define RESET_COMPLETE_TIME 500
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+
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+struct phy_meson_gxl_usb3_priv {
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+ struct regmap *regmap;
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+ struct phy *this_phy;
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+};
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+
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+static const struct regmap_config phy_meson_gxl_usb3_regmap_conf = {
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+ .reg_bits = 32,
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+ .val_bits = 32,
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+ .reg_stride = 4,
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+ .max_register = USB_R6,
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+};
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+
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+static int phy_meson_gxl_usb3_power_on(struct phy *phy)
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+{
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+ struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy);
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+
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+ regmap_update_bits(priv->regmap, USB_R1,
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+ USB_R1_U3H_FLADJ_30MHZ_REG_MASK,
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+ 0x20 << USB_R1_U3H_FLADJ_30MHZ_REG_SHIFT);
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+
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+ return 0;
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+}
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+
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+static const struct phy_ops phy_meson_gxl_usb3_ops = {
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+ .power_on = phy_meson_gxl_usb3_power_on,
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+ .owner = THIS_MODULE,
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+};
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+
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+static int phy_meson_gxl_usb3_probe(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ struct device_node *np = dev->of_node;
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+ struct phy_meson_gxl_usb3_priv *priv;
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+ struct resource *res;
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+ struct phy *phy;
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+ struct phy_provider *phy_provider;
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+ void __iomem *base;
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+
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+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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+ if (!priv)
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+ return -ENOMEM;
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+
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ base = devm_ioremap_resource(dev, res);
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+ if (IS_ERR(base))
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+ return PTR_ERR(base);
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+
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+ priv->regmap = devm_regmap_init_mmio(dev, base,
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+ &phy_meson_gxl_usb3_regmap_conf);
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+ if (IS_ERR(priv->regmap))
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+ return PTR_ERR(priv->regmap);
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+
|
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+ phy = devm_phy_create(dev, np, &phy_meson_gxl_usb3_ops);
|
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+ if (IS_ERR(phy)) {
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+ dev_err(dev, "failed to create PHY\n");
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+ return PTR_ERR(phy);
|
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+ }
|
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+
|
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+ phy_set_drvdata(phy, priv);
|
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+
|
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+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
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+
|
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+ return PTR_ERR_OR_ZERO(phy_provider);
|
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+}
|
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+
|
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+static const struct of_device_id phy_meson_gxl_usb3_of_match[] = {
|
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+ { .compatible = "amlogic,meson-gxl-usb3-phy", },
|
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+ { },
|
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+};
|
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+MODULE_DEVICE_TABLE(of, phy_meson_gxl_usb3_of_match);
|
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+
|
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+static struct platform_driver phy_meson_gxl_usb3_driver = {
|
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+ .probe = phy_meson_gxl_usb3_probe,
|
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+ .driver = {
|
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+ .name = "phy-meson-gxl-usb3",
|
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+ .of_match_table = phy_meson_gxl_usb3_of_match,
|
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+ },
|
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+};
|
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+module_platform_driver(phy_meson_gxl_usb3_driver);
|
||||
+
|
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+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
|
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+MODULE_DESCRIPTION("Meson GXL USB3 PHY driver");
|
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+MODULE_LICENSE("GPL");
|
||||
--
|
||||
1.9.1
|
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|
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|
|
@ -0,0 +1,47 @@
|
|||
From 2a16bb3d60c31dfc80635682a0db531bef184545 Mon Sep 17 00:00:00 2001
|
||||
From: Jerome Brunet <jbrunet@baylibre.com>
|
||||
Date: Tue, 5 Sep 2017 19:09:55 +0200
|
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Subject: [PATCH 63/67] ARM64: dts: meson-gxl-libretech-cc: enable saradc
|
||||
|
||||
Enable saradc and add the reference 1.8v regulator required.
|
||||
The libretech-cc has saradc channel 0 and 2 available on the 2 first
|
||||
pins of 2J3 header
|
||||
|
||||
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
|
||||
---
|
||||
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts | 12 ++++++++++++
|
||||
1 file changed, 12 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
|
||||
index 1d1bc3d..4951355 100644
|
||||
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
|
||||
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
|
||||
@@ -93,6 +93,13 @@
|
||||
<1800000 1>;
|
||||
};
|
||||
|
||||
+ vddio_ao18: regulator-vddio_ao18 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "VDDIO_AO18";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ };
|
||||
+
|
||||
vddio_boot: regulator-vddio_boot {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDDIO_BOOT";
|
||||
@@ -186,6 +193,11 @@
|
||||
"7J1 Header Pin15";
|
||||
};
|
||||
|
||||
+&saradc {
|
||||
+ status = "okay";
|
||||
+ vref-supply = <&vddio_ao18>;
|
||||
+};
|
||||
+
|
||||
/* SD card */
|
||||
&sd_emmc_b {
|
||||
status = "okay";
|
||||
--
|
||||
1.9.1
|
||||
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
From b214cf8dbf6b70d5629302543c4d0a734609561f Mon Sep 17 00:00:00 2001
|
||||
From: Jerome Brunet <jbrunet@baylibre.com>
|
||||
Date: Wed, 6 Sep 2017 14:25:47 +0200
|
||||
Subject: [PATCH 64/67] ARM64: dts: meson-gxl-libretech-cc: enable internal phy
|
||||
leds
|
||||
|
||||
Enable the internal phy ACT and LINK leds pinmux
|
||||
|
||||
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
|
||||
---
|
||||
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts | 5 +++++
|
||||
1 file changed, 5 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
|
||||
index 4951355..d5dcac7 100644
|
||||
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
|
||||
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
|
||||
@@ -118,6 +118,11 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&internal_phy {
|
||||
+ pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+};
|
||||
+
|
||||
&ir {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&remote_input_ao_pins>;
|
||||
--
|
||||
1.9.1
|
||||
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
From 4dc2c7ca99c52b4de87f77b9f2de242cbd885278 Mon Sep 17 00:00:00 2001
|
||||
From: Neil Armstrong <narmstrong@baylibre.com>
|
||||
Date: Tue, 25 Jul 2017 07:40:13 +0000
|
||||
Subject: [PATCH 65/67] ARM64: dts: meson-gxl-s905x-libretech-cc: Enable USB
|
||||
|
||||
---
|
||||
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts | 4 ++++
|
||||
1 file changed, 4 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
|
||||
index d5dcac7..2797f03 100644
|
||||
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
|
||||
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
|
||||
@@ -243,3 +243,7 @@
|
||||
pinctrl-0 = <&uart_ao_a_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
+
|
||||
+&usb0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
--
|
||||
1.9.1
|
||||
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
From 1306a81053c2e2d48e285b2d0861bb855bd60ea1 Mon Sep 17 00:00:00 2001
|
||||
From: Jerome Brunet <jbrunet@baylibre.com>
|
||||
Date: Wed, 20 Sep 2017 18:10:08 +0200
|
||||
Subject: [PATCH 66/67] ARM64: dts: meson: activate hdmi audio on libretech
|
||||
|
||||
This patch activate audio over HDMI on the libretech-cc
|
||||
|
||||
Please note that this audio support is based on WIP changes
|
||||
This should be considered as preview and it does not reflect
|
||||
the audio I expect to see merged
|
||||
|
||||
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
|
||||
---
|
||||
.../dts/amlogic/meson-gxl-s905x-libretech-cc.dts | 37 ++++++++++++++++++++++
|
||||
1 file changed, 37 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
|
||||
index 2797f03..238af46 100644
|
||||
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
|
||||
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
|
||||
@@ -72,6 +72,31 @@
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
+ sound {
|
||||
+ compatible = "simple-audio-card";
|
||||
+ simple-audio-card,name = "meson-gxl-preview";
|
||||
+ status = "okay";
|
||||
+
|
||||
+ simple-audio-card,dai-link@0 {
|
||||
+ /* HDMI Output */
|
||||
+ format = "i2s";
|
||||
+ mclk-fs = <256>;
|
||||
+ bitclock-master = <&i2s_dai>;
|
||||
+ frame-master = <&i2s_dai>;
|
||||
+ plat {
|
||||
+ sound-dai = <&aiu_i2s_dma>;
|
||||
+ };
|
||||
+
|
||||
+ cpu {
|
||||
+ sound-dai = <&i2s_dai>;
|
||||
+ };
|
||||
+
|
||||
+ codec {
|
||||
+ sound-dai = <&hdmi_tx>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
vcc_3v3: regulator-vcc_3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_3V3";
|
||||
@@ -108,6 +133,18 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&audio {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&aiu_i2s_dma {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2s_dai {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&cvbs_vdac_port {
|
||||
cvbs_vdac_out: endpoint {
|
||||
remote-endpoint = <&cvbs_connector_in>;
|
||||
--
|
||||
1.9.1
|
||||
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
From 704f3c8fd86bc84bea587a3bbe4d23fafe8c2f08 Mon Sep 17 00:00:00 2001
|
||||
From: Neil Armstrong <narmstrong@baylibre.com>
|
||||
Date: Tue, 30 May 2017 16:46:16 +0200
|
||||
Subject: [PATCH 67/67] ARM64: dts: meson-gx: Add AO CEC nodes for libretech-cc
|
||||
|
||||
This patch adds the AO CEC node for libretech-cc
|
||||
|
||||
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
|
||||
---
|
||||
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts | 7 +++++++
|
||||
1 file changed, 7 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
|
||||
index 238af46..af3e970 100644
|
||||
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
|
||||
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
|
||||
@@ -145,6 +145,13 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&cec_AO {
|
||||
+ status = "okay";
|
||||
+ pinctrl-0 = <&ao_cec_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ hdmi-phandle = <&hdmi_tx>;
|
||||
+};
|
||||
+
|
||||
&cvbs_vdac_port {
|
||||
cvbs_vdac_out: endpoint {
|
||||
remote-endpoint = <&cvbs_connector_in>;
|
||||
--
|
||||
1.9.1
|
||||
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
From 71204f8b6e69af6fc0de926e02c8a04d886064b2 Mon Sep 17 00:00:00 2001
|
||||
From: Neil Armstrong <narmstrong@baylibre.com>
|
||||
Date: Thu, 21 Sep 2017 11:58:43 +0200
|
||||
Subject: [PATCH 62/67] ARM64: dts: meson-gxl: Add USB3 PHY Node
|
||||
|
||||
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
|
||||
---
|
||||
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 9 +++++++++
|
||||
1 file changed, 9 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
|
||||
index d53352f..d5d3c2f 100644
|
||||
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
|
||||
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
|
||||
@@ -61,6 +61,8 @@
|
||||
dr_mode = "host";
|
||||
maximum-speed = "high-speed";
|
||||
snps,dis_u2_susphy_quirk;
|
||||
+ phys = <&usb3_phy0>;
|
||||
+ phy-names = "usb3-phy";
|
||||
status = "disabled";
|
||||
|
||||
dwc3_roothub: roothub@0 {
|
||||
@@ -99,6 +101,13 @@
|
||||
reg = <0x0 0x78020 0x0 0x20>;
|
||||
status = "okay";
|
||||
};
|
||||
+
|
||||
+ usb3_phy0: phy@78080 {
|
||||
+ compatible = "amlogic,meson-gxl-usb3-phy";
|
||||
+ #phy-cells = <0>;
|
||||
+ reg = <0x0 0x78080 0x0 0x20>;
|
||||
+ status = "okay";
|
||||
+ };
|
||||
};
|
||||
|
||||
ðmac {
|
||||
--
|
||||
1.9.1
|
||||
|
||||
Loading…
Add table
Reference in a new issue