remove useless patches for current 4.20.12

patch/kernel/sunxi-dev/fix-H6-irq-banks.patch

@@ -1,13 +0,0 @@
-diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
-index aa8b58125568..ef4268cc6227 100644
---- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
-+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
-@@ -588,7 +588,7 @@ static const unsigned int h6_irq_bank_map[] = { 1, 5, 6, 7 };
- static const struct sunxi_pinctrl_desc h6_pinctrl_data = {
- 	.pins = h6_pins,
- 	.npins = ARRAY_SIZE(h6_pins),
--	.irq_banks = 3,
-+	.irq_banks = 4,
- 	.irq_bank_map = h6_irq_bank_map,
- 	.irq_read_needs_mux = true,
- };

patch/kernel/sunxi-dev/mmc-sunxi-Fix-eMMC-usage-on-H5-boards.patch

@@ -1,59 +0,0 @@
-Subject: [PATCH v2 1/3] mmc: sunxi: Disable HS-DDR mode for H5 eMMC controller by default
-
-Some H5 boards seem to not have proper trace lengths for eMMC to be able
-to use the default setting for the delay chains under HS-DDR mode. These
-include the Bananapi M2+ H5 and NanoPi NEO Core2. However the Libre
-Computer ALL-H3-CC-H5 works just fine.
-
-For the H5 (at least for now), default to not enabling HS-DDR modes in
-the driver, and expect the device tree to signal HS-DDR capability on
-boards that work.
----
- drivers/mmc/host/sunxi-mmc.c | 11 ++++++++++-
- 1 file changed, 10 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
-index 279e326e397e..7415af8c8ff6 100644
---- a/drivers/mmc/host/sunxi-mmc.c
-+++ b/drivers/mmc/host/sunxi-mmc.c
-@@ -1399,7 +1399,16 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
- 	mmc->caps	       |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
- 				  MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
-
--	if (host->cfg->clk_delays || host->use_new_timings)
-+	/*
-+	 * Some H5 devices do not have signal traces precise enough to
-+	 * use HS DDR mode for their eMMC chips.
-+	 *
-+	 * We still enable HS DDR modes for all the other controller
-+	 * variants that support them.
-+	 */
-+	if ((host->cfg->clk_delays || host->use_new_timings) &&
-+	    !of_device_is_compatible(pdev->dev.of_node,
-+				     "allwinner,sun50i-h5-emmc"))
- 		mmc->caps      |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
-
- 	ret = mmc_of_parse(mmc);
-
-Subject: [PATCH v2 3/3] arm64: dts: allwinner: h5: libretech-all-h3-cc: Mark eMMC HS-DDR 3.3V capable
-
-The Libre Computer ALL-H3-CC H5 is one of the few boards that can have
-its eMMC run at HS-DDR speed mode. Mark it as such.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- .../boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts      | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts
-index 95e113ce8699..d68bdfea2271 100644
---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts
-@@ -12,3 +12,7 @@
- 	model = "Libre Computer Board ALL-H3-CC H5";
- 	compatible = "libretech,all-h3-cc-h5", "allwinner,sun50i-h5";
- };
-+
-+&mmc2 {
-+	mmc-ddr-3_3v;
-+};