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rockchip-current: return hdmi patches and rework it for 5.9.y kernel (#2471)

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rockchip-current: return hdmi patches and rework it for 5.9.y kernel
This commit is contained in:
q4a 2020-12-18 20:50:47 +03:00 • committed by GitHub
parent 3f1baa0601
commit 2b627cb36b
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GPG key ID: 4AEE18F83AFDEB23
4 changed files with 51 additions and 49 deletions
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2
patch/kernel/rockchip-current/4005-drm-rockchip-dw_hdmi-Set-cur_ctr-to-0-always.patch.disabled → patch/kernel/rockchip-current/4005-drm-rockchip-dw_hdmi-Set-cur_ctr-to-0-always.patch
View file

@ -37,7 +37,7 @@ index 7f56d8c34..7d7ee5b26 100644
- 148500000, { 0x0000, 0x0038, 0x0038 },
- }, {
+ 600000000, { 0x0000, 0x0000, 0x0000 },
+ }, {
+ }, {
~0UL, { 0x0000, 0x0000, 0x0000},
}
};

0
patch/kernel/rockchip-current/4007-drm-rockchip-dw_hdmi-Use-auto-generated-tables.patch.disabled → patch/kernel/rockchip-current/4007-drm-rockchip-dw_hdmi-Use-auto-generated-tables.patch
View file

50
patch/kernel/rockchip-current/4009-drm-rockchip-dw-hdmi-limit-tmds-to-340mhz.patch Normal file
View file

@ -0,0 +1,50 @@
From f83d188f49bd11d085c3f4160b208cb8194daff4 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Wed, 8 Jan 2020 21:07:52 +0000
Subject: [PATCH] drm/rockchip: dw-hdmi: limit tmds to 340mhz
RK3228/RK3328 does not provide a stable hdmi signal at TMDS rates
above 371.25MHz (340MHz pixel clock).
Limit the pixel clock rate to 340MHz to provide a stable signal.
Also limit the pixel clock to the display reported max tmds clock.
This also enables use of pixel clocks up to 340MHz on RK3288/RK3399.
And limit resolution to 3840x2160
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++------------
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index b5d2cdaa24fa..5f7ab8e6bb72 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -221,19 +221,11 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data,
const struct drm_display_info *info,
const struct drm_display_mode *mode)
{
- const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
- int pclk = mode->clock * 1000;
- bool valid = false;
- int i;
+ if (mode->clock > 340000 ||
+ (info->max_tmds_clock && mode->clock > info->max_tmds_clock))
+ return MODE_CLOCK_HIGH;
- for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
- if (pclk == mpll_cfg[i].mpixelclock) {
- valid = true;
- break;
- }
- }
-
- return (valid) ? MODE_OK : MODE_BAD;
+ return drm_mode_validate_size(mode, 3840, 2160);
}
static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
--
2.26.2

48
patch/kernel/rockchip-current/4009-drm-rockchip-dw-hdmi-limit-tmds-to-340mhz.patch.disabled
View file

@ -1,48 +0,0 @@
From 13fe05c1a6a0b7b81d7c6768eef9fbc618b75f30 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 3 May 2020 17:09:41 +0000
Subject: [PATCH 10/14] drm/rockchip: dw-hdmi: limit tmds to 340mhz
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 23 ++++++++++-----------
1 file changed, 11 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 1a047f9d0..955fc3cf4 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -219,19 +219,18 @@ static enum drm_mode_status
dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
const struct drm_display_mode *mode)
{
- const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
- int pclk = mode->clock * 1000;
- bool valid = false;
- int i;
-
- for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
- if (pclk == mpll_cfg[i].mpixelclock) {
- valid = true;
- break;
- }
- }
+ struct drm_display_info *info = &connector->display_info;
+ int max_tmds_clock = max(info->max_tmds_clock, 165000);
+ int clock = mode->clock;
+
+ if (connector->ycbcr_420_allowed && drm_mode_is_420(info, mode) &&
+ (info->color_formats & DRM_COLOR_FORMAT_YCRCB420))
+ clock /= 2;
+
+ if (clock > max_tmds_clock || clock > 340000)
+ return MODE_CLOCK_HIGH;
- return (valid) ? MODE_OK : MODE_BAD;
+ return MODE_OK;
}
static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = {
--
2.26.2