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Update Clearfog Base DT
This commit is contained in:
zador-blood-stained
parent
f21a443ae7
commit
2d6fc7c3f1
1 changed files with 26 additions and 82 deletions
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@ -1,10 +1,8 @@
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diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
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old mode 100644
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new mode 100755
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index 414b427..3d89ee1
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index faacd52..f5eab46 100644
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -859,6 +859,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
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@@ -886,6 +886,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
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armada-385-linksys-caiman.dtb \
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armada-385-linksys-cobra.dtb \
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armada-388-clearfog.dtb \
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@ -13,11 +11,11 @@ index 414b427..3d89ee1
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armada-388-gp.dtb \
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armada-388-rd.dtb
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diff --git a/arch/arm/boot/dts/armada-388-clearfog-base.dts b/arch/arm/boot/dts/armada-388-clearfog-base.dts
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new file mode 100755
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index 0000000..b441e98
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new file mode 100644
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index 0000000..92c6ddf
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--- /dev/null
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+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
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@@ -0,0 +1,411 @@
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@@ -0,0 +1,357 @@
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+/*
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+ * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
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+ *
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@ -99,18 +97,31 @@ index 0000000..b441e98
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+ ethernet@30000 {
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+ phy = <&phy1>;
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+ phy-mode = "sgmii";
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+ buffer-manager = <&bm>;
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+ bm,pool-long = <2>;
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+ bm,pool-short = <1>;
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+ status = "okay";
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+ };
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+
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+ ethernet@34000 {
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+ managed = "in-band-status";
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+ phy-mode = "sgmii";
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+ status = "okay";
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+ };
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+ };
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+
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+ mdio@72004 {
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+ phy1: ethernet-phy@1 { /* Marvell 88E1512 */
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+ reg = <1>;
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+ /*
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+ * Annoyingly, the marvell phy driver
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+ * configures the LED register, rather
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+ * than preserving reset-loaded setting.
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+ * We undo that rubbish here.
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+ */
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+ marvell,reg-init = <3 16 0 0x101e>;
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+ reg = <1>;
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+ };
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+ };
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+
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+ i2c@11000 {
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+ /* Is there anything on this? */
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+ clock-frequency = <100000>;
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@ -221,14 +232,6 @@ index 0000000..b441e98
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+ };
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+
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+ pinctrl@18000 {
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+ clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
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+ marvell,pins = "mpp46";
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+ marvell,function = "ref";
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+ };
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+ clearfog_dsa0_pins: clearfog-dsa0-pins {
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+ marvell,pins = "mpp23", "mpp41";
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+ marvell,function = "gpio";
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+ };
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+ clearfog_i2c1_pins: i2c1-pins {
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+ /* SFP, PCIe, mSATA, mikrobus */
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+ marvell,pins = "mpp26", "mpp27";
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@ -321,37 +324,28 @@ index 0000000..b441e98
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+ };
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+
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+ usb@58000 {
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+ /* CON3, nearest power. */
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+ /* miniPCIe */
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+ status = "okay";
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+ };
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+
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+ usb3@f0000 {
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+ /* CON2, nearest CPU, USB2 only. */
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+ /* M.2 */
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+ status = "okay";
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+ };
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+
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+ usb3@f8000 {
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+ /* CON7 */
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+ /* CON2 */
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+ status = "okay";
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+ };
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+ };
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+
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+ pcie-controller {
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+ status = "okay";
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+ /*
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+ * The two PCIe units are accessible through
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+ * the mini-PCIe connectors on the board.
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+ */
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+ pcie@2,0 {
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+ /* Port 1, Lane 0. CON3, nearest power. */
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+ /* Port 1, Lane 0. */
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+ reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
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+ status = "okay";
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+ };
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+ pcie@3,0 {
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+ /* Port 2, Lane 0. CON2, nearest CPU. */
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+ reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
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+ status = "okay";
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+ };
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+ };
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+ };
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+
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@ -363,8 +357,8 @@ index 0000000..b441e98
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+ sfp,ethernet = <ð2>;
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+ tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
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+ tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ };
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+
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+ gpio-keys {
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+ compatible = "gpio-keys";
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+ pinctrl-0 = <&rear_button_pins>;
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@ -379,53 +373,3 @@ index 0000000..b441e98
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+ };
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+ };
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+};
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+/*
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++#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
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+MPP18: gpio ? (pca9655 int?)
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+MPP19: gpio ? (clkreq?)
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+MPP20: gpio ? (sd0 detect)
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+MPP21: sd0:cmd x sd0
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+MPP22: gpio x mikro int
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+MPP23: gpio x switch irq
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++#define A38x_CUSTOMER_BOARD_1_MPP24_31 0x22043333
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+MPP24: ua1:rxd x mikro rx
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+MPP25: ua1:txd x mikro tx
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+MPP26: i2c1:sck x mikro sck
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+MPP27: i2c1:sda x mikro sda
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+MPP28: sd0:clk x sd0
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+MPP29: gpio x mikro rst
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+MPP30: ge1:txd2 ? (config)
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+MPP31: ge1:txd3 ? (config)
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++#define A38x_CUSTOMER_BOARD_1_MPP32_39 0x44400002
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+MPP32: ge1:txctl ? (unused)
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+MPP33: gpio ? (pic_com0)
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+MPP34: gpio x rear button (pic_com1)
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+MPP35: gpio ? (pic_com2)
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+MPP36: gpio ? (unused)
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+MPP37: sd0:d3 x sd0
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+MPP38: sd0:d0 x sd0
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+MPP39: sd0:d1 x sd0
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++#define A38x_CUSTOMER_BOARD_1_MPP40_47 0x41144004
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+MPP40: sd0:d2 x sd0
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+MPP41: gpio x switch reset
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+MPP42: gpio ? sw1-1
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+MPP43: spi1:cs2 x mikro cs
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+MPP44: sata3:prsnt ? (unused)
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+MPP45: ref:clk_out0 ?
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+MPP46: ref:clk_out1 x switch clk
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+MPP47: 4 ? (unused)
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++#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x40333333
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+MPP48: tdm:pclk
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+MPP49: tdm:fsync
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+MPP50: tdm:drx
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+MPP51: tdm:dtx
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+MPP52: tdm:int
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+MPP53: tdm:rst
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+MPP54: gpio ? (pwm)
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+MPP55: spi1:cs1 x slic
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++#define A38x_CUSTOMER_BOARD_1_MPP56_63 0x00004444
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+MPP56: spi1:mosi x mikro mosi
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+MPP57: spi1:sck x mikro sck
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+MPP58: spi1:miso x mikro miso
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+MPP59: spi1:cs0 x w25q32
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+*/
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