From 2ef50673fbed3073ae42acd1a33ef1b170b3ccd5 Mon Sep 17 00:00:00 2001 From: Martin Ayotte Date: Fri, 22 Jul 2016 17:24:47 -0400 Subject: [PATCH] add new add_missing_UARTs_and_I2Cs_for-H3.patch --- .../add_missing_UARTs_and_I2Cs_for-H3.patch | 93 +++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 patch/kernel/sun8i-dev/add_missing_UARTs_and_I2Cs_for-H3.patch diff --git a/patch/kernel/sun8i-dev/add_missing_UARTs_and_I2Cs_for-H3.patch b/patch/kernel/sun8i-dev/add_missing_UARTs_and_I2Cs_for-H3.patch new file mode 100644 index 000000000..5cb314bc5 --- /dev/null +++ b/patch/kernel/sun8i-dev/add_missing_UARTs_and_I2Cs_for-H3.patch @@ -0,0 +1,93 @@ +diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi +index 8e7d38c..21fe601 100644 +--- a/arch/arm/boot/dts/sun8i-h3.dtsi ++++ b/arch/arm/boot/dts/sun8i-h3.dtsi +@@ -541,6 +541,48 @@ + allwinner,pull = ; + }; + ++ uart1_pins_a: uart1@0 { ++ allwinner,pins = "PG6", "PG7"; ++ allwinner,function = "uart1"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ uart2_pins_a: uart2@0 { ++ allwinner,pins = "PA0", "PA1"; ++ allwinner,function = "uart2"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ uart3_pins_a: uart3@0 { ++ allwinner,pins = "PA13", "PA14"; ++ allwinner,function = "uart3"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ i2c0_pins_a: i2c0@0 { ++ allwinner,pins = "PA11", "PA12"; ++ allwinner,function = "i2c0"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ i2c1_pins_a: i2c1@0 { ++ allwinner,pins = "PA18", "PA19"; ++ allwinner,function = "i2c1"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ i2c2_pins_a: i2c2@0 { ++ allwinner,pins = "PE12", "PE13"; ++ allwinner,function = "i2c2"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; +@@ -699,6 +741,39 @@ + status = "disabled"; + }; + ++ i2c0: i2c@01c2ac00 { ++ compatible = "allwinner,sun6i-a31-i2c"; ++ reg = <0x01c2ac00 0x400>; ++ interrupts = ; ++ clocks = <&bus_gates 96>; ++ resets = <&apb2_rst 0>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ i2c1: i2c@01c2b000 { ++ compatible = "allwinner,sun6i-a31-i2c"; ++ reg = <0x01c2b000 0x400>; ++ interrupts = ; ++ clocks = <&bus_gates 97>; ++ resets = <&apb2_rst 1>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ i2c2: i2c@01c2b400 { ++ compatible = "allwinner,sun6i-a31-i2c"; ++ reg = <0x01c2b400 0x400>; ++ interrupts = ; ++ clocks = <&bus_gates 98>; ++ resets = <&apb2_rst 2>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>,