GitHub-Mirror/build
2
0
Fork 0
mirror of https://github.com/Fishwaldo/build.git synced 2025-03-16 11:51:36 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

add station legacy (#2521)

Browse source
This commit is contained in:
Oleg 2021-01-04 03:01:16 +03:00 • committed by GitHub
parent 30558096a9
commit 2fe4d7039d
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
13 changed files with 15170 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6417
config/kernel/linux-station-m1-legacy.config Normal file
View file

File diff suppressed because it is too large Load diff

6387
config/kernel/linux-station-p1-legacy.config Normal file
View file

File diff suppressed because it is too large Load diff

9
config/sources/families/include/rockchip64_common.inc
View file

@ -58,6 +58,15 @@ elif [[ $BOARD == rockpi-4* ]]; then
MINILOADER_BLOB='rk33/rk3399_miniloader_v1.19.bin'
BL31_BLOB='rk33/rk3399_bl31_v1.30.elf'
elif [[ $BOARD == station-p1 ]]; then
BOOT_USE_BLOBS=yes
BOOT_SUPPORT_SPI=yes
BOOT_SOC=rk3399
DDR_BLOB='rk33/rk3399_ddr_933MHz_v1.24.bin'
MINILOADER_BLOB='rk33/rk3399_miniloader_v1.19.bin'
BL31_BLOB='rk33/rk3399_bl31_v1.30.elf'
elif [[ $BOARD == rockpro64 ]]; then
BOOT_USE_TPL_SPL_BLOB=yes

2
config/sources/families/rk3399.conf
View file

@ -31,7 +31,7 @@ elif [[ $BOARD == helios64 ]]; then
BOOT_USE_MAINLINE_ATF=yes
fi
elif [[ $BOARD == nanopim4v2 || $BOARD == orangepi4 || $BOARD == station-p1 ]]; then
elif [[ $BOARD == nanopim4v2 || $BOARD == orangepi4 ]]; then
BOOT_USE_BLOBS=yes
DDR_BLOB='rk33/rk3399_ddr_933MHz_v1.24.bin'

9
config/sources/families/rockchip64.conf
View file

@ -8,6 +8,15 @@ case $BRANCH in
KERNELSOURCE='https://github.com/ayufan-rock64/linux-kernel'
KERNELBRANCH='tag:4.4.202-1237-rockchip-ayufan'
KERNELDIR='linux-rockchip64'
KERNELPATCHDIR='rockchip64-'$BRANCH
if [[ $BOARD == station-p1 ]]; then
LINUXCONFIG='linux-station-p1-'$BRANCH
LINUXFAMILY=station-p1
elif [[ $BOARD == station-m1 ]]; then
LINUXCONFIG='linux-station-m1-'$BRANCH
LINUXFAMILY=station-m1
fi
;;

3
lib/compilation-prepare.sh
View file

@ -61,7 +61,8 @@ compilation_prepare()
process_patch_file "${SRC}/patch/misc/general-packaging-4.4.y-rk3399.patch" "applying"
fi
if [[ "${version}" == "4.4."* ]] && [[ "$LINUXFAMILY" == rockchip64 ]]; then
if [[ "${version}" == "4.4."* ]] && \
[[ "$LINUXFAMILY" == rockchip64 ]] || [[ "$LINUXFAMILY" == station* ]]; then
display_alert "Adjustin" "packaging" "info"
cd "$kerneldir" || exit
process_patch_file "${SRC}/patch/misc/general-packaging-4.4.y-rockchip64.patch" "applying"

459
patch/kernel/rockchip64-legacy/zz-add-rk3328-firefly-core-dtsi.patch Normal file
View file

@ -0,0 +1,459 @@
new file mode 100644
index 0000000..7b82b78
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-firefly-core.dtsi
@@ -0,0 +1,453 @@
+/*
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "rk3328.dtsi"
+#include "rk3328-linux.dtsi"
+#include <dt-bindings/input/input.h>
+#include "rk3328-box-plus-dram-timing.dtsi"
+
+/ {
+ compatible = "firefly,rk3328-firefly-core", "rockchip,rk3328";
+
+ chosen {
+ bootargs = "rockchip_jtag earlyprintk=uart8250-32bit,0xff130000 swiotlb=1 kpti=0 console=ttyFIQ0 ro root=PARTLABEL=rootfs rootfstype=ext4 rootwait overlayroot=device:dev=PARTLABEL=userdata,fstype=ext4,mkfs=1 systemd.gpt_auto=0 cgroup_enable=memory swapaccount=1";
+ stdout-path = "serial2:1500000n8";
+ };
+
+ fiq-debugger {
+ compatible = "rockchip,fiq-debugger";
+ rockchip,serial-id = <2>;
+ rockchip,signal-irq = <159>;
+ rockchip,wake-irq = <0>;
+ /* If enable uart uses irq instead of fiq */
+ rockchip,irq-mode-enable = <0>;
+ rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
+ status = "okay";
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0m1_gpio>;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vccio_sd: sdmmcio-regulator {
+ compatible = "regulator-gpio";
+ gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ //pinctrl-names = "default";
+ //pinctrl-0 = <&sd_pwr_1800_sel>;
+ regulator-name = "vccio_sd";
+ regulator-type = "voltage";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ status="okay";
+ };
+
+ vcc_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&dfi {
+ status = "okay";
+};
+
+&dmc {
+ status = "okay";
+ center-supply = <&vdd_logic>;
+};
+
+&dmc_opp_table {
+ status = "okay";
+};
+
+&cpu0_opp_table {
+
+ rockchip,leakage-voltage-sel = <
+ 1 8 0
+ 9 254 1
+ >;
+ nvmem-cells = <&cpu_leakage>;
+ nvmem-cell-names = "cpu_leakage";
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <975000>;
+ opp-microvolt-L0 = <975000>;
+ opp-microvolt-L1 = <950000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <975000>;
+ opp-microvolt-L0 = <975000>;
+ opp-microvolt-L1 = <950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1025000>;
+ opp-microvolt-L0 = <1025000>;
+ opp-microvolt-L1 = <1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1125000>;
+ opp-microvolt-L0 = <1125000>;
+ opp-microvolt-L1 = <1100000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1250000>;
+ opp-microvolt-L0 = <1250000>;
+ opp-microvolt-L1 = <1225000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1296000000 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-microvolt = <1325000>;
+ opp-microvolt-L0 = <1325000>;
+ opp-microvolt-L1 = <1300000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1392000000 {
+ opp-hz = /bits/ 64 <1392000000>;
+ opp-microvolt = <1350000>;
+ opp-microvolt-L0 = <1350000>;
+ opp-microvolt-L1 = <1325000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1512000000 {
+ status = "disabled";
+ opp-hz = /bits/ 64 <1512000000>;
+ opp-microvolt = <1350000>;
+ opp-microvolt-L0 = <1350000>;
+ opp-microvolt-L1 = <1325000>;
+ clock-latency-ns = <40000>;
+ };
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ supports-emmc;
+ disable-wp;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc_18emmc>;
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+ mali-supply = <&vdd_logic>;
+};
+
+&gpu_opp_table {
+
+ rockchip,leakage-voltage-sel = <
+ 1 8 0
+ 9 254 1
+ >;
+ nvmem-cells = <&logic_leakage>;
+ nvmem-cell-names = "gpu_leakage";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <1050000>;
+ opp-microvolt-L0 = <1050000>;
+ opp-microvolt-L1 = <1025000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1050000>;
+ opp-microvolt-L0 = <1050000>;
+ opp-microvolt-L1 = <1025000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1050000>;
+ opp-microvolt-L0 = <1050000>;
+ opp-microvolt-L1 = <1025000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1125000>;
+ opp-microvolt-L0 = <1125000>;
+ opp-microvolt-L1 = <1100000>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ rk805: rk805@18 {
+ compatible = "rockchip,rk805";
+ status = "okay";
+ reg = <0x18>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk805-clkout2";
+
+ rtc {
+ status = "okay";
+ };
+
+ pwrkey {
+ status = "disabled";
+ };
+
+ gpio {
+ status = "okay";
+ };
+
+ regulators {
+ compatible = "rk805-regulator";
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_logic: RK805_DCDC1@0 {
+ regulator-compatible = "RK805_DCDC1";
+ regulator-name = "vdd_logic";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-initial-mode = <0x1>;
+ regulator-ramp-delay = <12500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-mode = <0x2>;
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vdd_arm: RK805_DCDC2@1 {
+ regulator-compatible = "RK805_DCDC2";
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-initial-mode = <0x1>;
+ regulator-ramp-delay = <12500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-mode = <0x2>;
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: RK805_DCDC3@2 {
+ regulator-compatible = "RK805_DCDC3";
+ regulator-name = "vcc_ddr";
+ regulator-initial-mode = <0x1>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-mode = <0x2>;
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: RK805_DCDC4@3 {
+ regulator-compatible = "RK805_DCDC4";
+ regulator-name = "vcc_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <0x1>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-mode = <0x2>;
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vdd_18: RK805_LDO1@4 {
+ regulator-compatible = "RK805_LDO1";
+ regulator-name = "vdd_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_18emmc: RK805_LDO2@5 {
+ regulator-compatible = "RK805_LDO2";
+ regulator-name = "vcc_18emmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_11: RK805_LDO3@6 {
+ regulator-compatible = "RK805_LDO3";
+ regulator-name = "vdd_11";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1100000>;
+ };
+ };
+ };
+ };
+};
+
+&h265e {
+ status = "okay";
+};
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc_18emmc>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vdd_18>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_io>;
+ pmuio-supply = <&vcc_io>;
+};
+
+&pinctrl {
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins =
+ <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; /* gpio1_d0 */
+ };
+ };
+
+};
+
+&rkvdec {
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ sd-uhs-sdr104;
+ clock-freq-min-max = <400000 80000000>;
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+ supports-sd;
+ status = "okay";
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vccio_sd>;
+};
+
+&tsadc {
+ status = "okay";
+};
+

383
patch/kernel/rockchip64-legacy/zz-add-rk3328-firefly-port-dtsi.patch Normal file
View file

@ -0,0 +1,383 @@
new file mode 100644
index 0000000..7b82b78
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-firefly-port.dtsi
@@ -0,0 +1,377 @@
+
+#include "rk3328-firefly-core.dtsi"
+
+/ {
+ compatible = "firefly,rk3328-firefly-port", "rockchip,rk3328";
+
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,name = "rockchip,rk3328";
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&codec>;
+ };
+ };
+
+ hdmi-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <128>;
+ simple-audio-card,name = "rockchip,hdmi";
+ simple-audio-card,cpu {
+ sound-dai = <&i2s0>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&hdmi>;
+ };
+ };
+
+ spdif-sound {
+ status = "disabled";
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "rockchip,spdif";
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&spdif_out>;
+ };
+ };
+
+ spdif_out: spdif-out {
+ status = "disabled";
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+ };
+
+ vcc_host_5v: vcc-host-5v-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_host_drv>;
+ regulator-name = "vcc_host_5v";
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power {
+ label = "firefly:blue:power";
+ linux,default-trigger = "ir-power-click";
+ gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ mode = <0x23>;
+ };
+
+ user {
+ label = "firefly:yellow:user";
+ linux,default-trigger = "ir-user-click";
+ gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ mode = <0x05>;
+ };
+
+ ir {
+ status = "disabled";
+ /* gpios = <&gpio2 GPIO_C2 GPIO_ACTIVE_HIGH>; */
+ linux,default-trigger = "ir";
+ default-state = "off";
+ mode = <0x00>;
+ };
+ };
+
+ adc-keys {
+ u-boot,dm-pre-reloc;
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ };
+};
+
+&saradc {
+ vref-supply = <&vdd_18>;
+ status = "okay";
+};
+
+&codec {
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
+&display_subsystem {
+ status = "okay";
+};
+
+&route_hdmi {
+ status = "okay";
+};
+
+&gmac2io {
+ phy-supply = <&vcc_phy>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,force_thresh_dma_mode;
+ snps,reset-delays-us = <0 10000 50000>;
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmiim1_pins>;
+ tx_delay = <0x28>;
+ rx_delay = <0x16>;
+ status = "okay";
+};
+
+&gmac2phy {
+ phy-supply = <&vcc_phy>;
+ clock_in_out = "output";
+ assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
+ assigned-clock-rate = <50000000>;
+ assigned-clocks = <&cru SCLK_MAC2PHY>;
+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
+ status = "disabled";
+};
+
+&hdmi {
+ #sound-dai-cells = <0>;
+ ddc-i2c-scl-high-time-ns = <9625>;
+ ddc-i2c-scl-low-time-ns = <10000>;
+ status = "okay";
+};
+
+&hdmiphy {
+ status = "okay";
+};
+
+&i2s0 {
+ #sound-dai-cells = <0>;
+ rockchip,bclk-fs = <128>;
+ status = "okay";
+};
+
+&i2s1 {
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
+&pinctrl {
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins =
+ <1 18 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ usb_host_drv: usb-host-drv {
+ rockchip,pins =
+ <0 0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+};
+
+&sdio {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ max-frequency = <150000000>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+ supports-sdio;
+ status = "disabled";
+};
+
+&spdif {
+ #sound-dai-cells = <0>;
+ status = "disabled";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer>;
+ status = "okay";
+};
+
+&u2phy {
+ status = "okay";
+};
+
+&u2phy_host {
+ phy-supply = <&vcc_host_5v>;
+ status = "okay";
+};
+
+&u2phy_otg {
+ status = "okay";
+};
+
+&u3phy {
+ phy-supply = <&vcc_host_5v>;
+ status = "okay";
+};
+
+&u3phy_utmi {
+ status = "okay";
+};
+
+&u3phy_pipe {
+ status = "okay";
+};
+
+&usb20_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usbdrd3 {
+ status = "okay";
+};
+
+&usbdrd_dwc3 {
+ status = "okay";
+};
+
+&vepu {
+ status = "okay";
+};
+
+&vop {
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vpu_service {
+ status = "okay";
+};
+
+&pwm3 {
+ status = "okay";
+ compatible = "rockchip,remotectl-pwm";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwmir_pin>;
+ remote_pwm_id = <3>;
+ handle_cpu_id = <1>;
+ remote_support_psci = <1>;
+
+ ir_key1 {
+ rockchip,usercode = <0x4040>;
+ rockchip,key_table =
+ <0xf2 KEY_REPLY>,
+ <0xba KEY_BACK>,
+ <0xf4 KEY_UP>,
+ <0xf1 KEY_DOWN>,
+ <0xef KEY_LEFT>,
+ <0xee KEY_RIGHT>,
+ <0xbd KEY_HOME>,
+ <0xea KEY_VOLUMEUP>,
+ <0xe3 KEY_VOLUMEDOWN>,
+ <0xe2 KEY_SEARCH>,
+ <0xb2 KEY_POWER>,
+ <0xbc KEY_MUTE>,
+ <0xec KEY_MENU>,
+ <0xbf 0x190>,
+ <0xe0 0x191>,
+ <0xe1 0x192>,
+ <0xe9 183>,
+ <0xe6 248>,
+ <0xe8 185>,
+ <0xe7 186>,
+ <0xf0 388>,
+ <0xbe 0x175>;
+ };
+
+ ir_key2 {
+ rockchip,usercode = <0xff00>;
+ rockchip,key_table =
+ <0xeb KEY_POWER>,
+ <0xec KEY_COMPOSE>,
+ <0xfe KEY_BACK>,
+ <0xb7 KEY_HOME>,
+ <0xa3 KEY_WWW>,
+ <0xf4 KEY_VOLUMEUP>,
+ <0xa7 KEY_VOLUMEDOWN>,
+ <0xf8 KEY_ENTER>,
+ <0xfc KEY_UP>,
+ <0xfd KEY_DOWN>,
+ <0xf1 KEY_LEFT>,
+ <0xe5 KEY_RIGHT>;
+ };
+
+ ir_key3 {
+ rockchip,usercode = <0x1dcc>;
+ rockchip,key_table =
+ <0xee KEY_REPLY>,
+ <0xf0 KEY_BACK>,
+ <0xf8 KEY_UP>,
+ <0xbb KEY_DOWN>,
+ <0xef KEY_LEFT>,
+ <0xed KEY_RIGHT>,
+ <0xfc KEY_HOME>,
+ <0xf1 KEY_VOLUMEUP>,
+ <0xfd KEY_VOLUMEDOWN>,
+ <0xb7 KEY_SEARCH>,
+ <0xff KEY_POWER>,
+ <0xf3 KEY_MUTE>,
+ <0xbf KEY_MENU>,
+ <0xf9 0x191>,
+ <0xf5 0x192>,
+ <0xb3 388>,
+ <0xbe KEY_1>,
+ <0xba KEY_2>,
+ <0xb2 KEY_3>,
+ <0xbd KEY_4>,
+ <0xf9 KEY_5>,
+ <0xb1 KEY_6>,
+ <0xfc KEY_7>,
+ <0xf8 KEY_8>,
+ <0xb0 KEY_9>,
+ <0xb6 KEY_0>,
+ <0xb5 KEY_BACKSPACE>;
+ };
+};

47
patch/kernel/rockchip64-legacy/zz-add-rk3328-linux-dtsi.patch Normal file
View file

@ -0,0 +1,47 @@
new file mode 100644
index 0000000..7b82b78
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-linux.dtsi
@@ -0,0 +1,41 @@
+/ {
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ drm_logo: drm-logo@00000000 {
+ compatible = "rockchip,drm-logo";
+ reg = <0x0 0x0 0x0 0x0>;
+ };
+ };
+};
+
+&display_subsystem {
+ logo-memory-region = <&drm_logo>;
+ status = "okay";
+ route {
+ route_hdmi: route-hdmi {
+ status = "disabled";
+ logo,uboot = "logo.bmp";
+ logo,kernel = "logo_kernel.bmp";
+ logo,mode = "center";
+ charge_logo,mode = "center";
+ connect = <&vop_out_hdmi>;
+ };
+
+ route_tve: route-tve {
+ status = "okay";
+ logo,uboot = "logo.bmp";
+ logo,kernel = "logo_kernel.bmp";
+ logo,mode = "fullscreen";
+ charge_logo,mode = "fullscreen";
+ connect = <&vop_out_tve>;
+ };
+ };
+};
+
+&rga {
+ status = "okay";
+};

127
patch/kernel/rockchip64-legacy/zz-add-rk3328-roc-pc-dts.patch Normal file
View file

@ -0,0 +1,127 @@
new file mode 100644
index 0000000..7b82b78
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts
@@ -0,0 +1,121 @@
+/dts-v1/;
+#include "rk3328-firefly-port.dtsi"
+
+/ {
+ model = "Firefly ROC-RK3328-PC";
+ compatible = "firefly,roc-rk3328-pc", "rockchip,rk3328";
+
+ fiq-debugger {
+ status = "disabled";
+ };
+
+ wireless-bluetooth {
+ compatible = "bluetooth-platdata";
+ clocks = <&cru SCLK_RTC32K>;
+ clock-names = "ext_clock";
+ BT,power_gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; //GPIO1_D0
+ BT,wake_host_irq = <&gpio1 26 GPIO_ACTIVE_HIGH>;//GPIO1_D2
+ status = "okay";
+ };
+
+ wireless-wlan {
+ compatible = "wlan-platdata";
+ clocks = <&cru SCLK_RTC32K>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&clock_wifi>;
+ rockchip,grf = <&grf>;
+ wifi_chip_type = "rtl8723ds";
+ sdio_vref = <1800>;
+ WIFI,host_wake_irq = <&gpio3 1 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+};
+
+&codec {
+ rk3328-codec-hp-gpiomute;
+};
+
+&rk805 {
+
+ interrupt-parent = <&gpio0>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+
+ pwrkey {
+ status = "okay";
+ };
+};
+
+&sdio_pwrseq {
+ reset-gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
+};
+
+&vccio_sd {
+ gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
+};
+
+&pinctrl {
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <3 8 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wireless-wlan {
+ clock_wifi: clock-wifi {
+ rockchip,pins = <1 28 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+};
+
+&uart1 {
+ status = "disabled";
+};
+
+&uart2 {
+ dma-names = "tx", "rx";
+ status = "okay";
+};
+
+&usb20_otg {
+ dr_mode = "device";
+};
+
+&sdmmc_ext {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ max-frequency = <100000000>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ num-slots = <1>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0ext_clk &sdmmc0ext_cmd &sdmmc0ext_bus4>;
+ supports-sdio;
+ sd-uhs-sdr104;
+ status = "okay";
+ vmmc-supply = <&vcc_io>;
+};
+
+&dmc {
+ system-status-freq = <
+ /*system status freq(KHz)*/
+ SYS_STATUS_NORMAL 786000
+ SYS_STATUS_REBOOT 786000
+ SYS_STATUS_SUSPEND 786000
+ SYS_STATUS_VIDEO_1080P 786000
+ SYS_STATUS_VIDEO_4K 786000
+ SYS_STATUS_VIDEO_4K_10B 786000
+ SYS_STATUS_PERFORMANCE 786000
+ SYS_STATUS_BOOST 786000
+ >;
+};

11
patch/kernel/rockchip64-legacy/zz-add-rk3328-roc-pc-make.patch Normal file
View file

@ -0,0 +1,11 @@
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -45,6 +45,7 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb-android.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb-android-avb.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-pc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64-android.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64-android-avb.dtb

11
patch/kernel/rockchip64-legacy/zz-add-rk3399-roc-pc-make.patch Normal file
View file

@ -0,0 +1,11 @@
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -86,6 +86,7 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb-rev3-cros.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly-android.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly-linux.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-fpga.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-gru.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin-r0.dtb

1307
patch/kernel/rockchip64-legacy/zz-add-rk3399-roc-pc-mezzanine-dts.patch Normal file
View file

File diff suppressed because it is too large Load diff