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Espressobin. Yet another cleanup - remove deprecated patches
Tested booting. @lanefu
This commit is contained in:
Igor Pecovnik
parent
26c685e973
commit
429668c9ba
7 changed files with 1117 additions and 768 deletions
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@ -1,138 +0,0 @@
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From patchwork Thu Sep 28 12:58:34 2017
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v2,
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3/7] PCI: aardvark: set host and device to the same MAX payload size
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X-Patchwork-Submitter: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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X-Patchwork-Id: 819587
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Message-Id: <20170928125838.11887-4-thomas.petazzoni@free-electrons.com>
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To: Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org
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Cc: Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
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Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Gregory Clement
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<gregory.clement@free-electrons.com>,
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Nadav Haklai <nadavh@marvell.com>, Hanna Hawa <hannah@marvell.com>,
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Yehuda Yitschak <yehuday@marvell.com>,
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linux-arm-kernel@lists.infradead.org, Antoine Tenart
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<antoine.tenart@free-electrons.com>, =?utf-8?q?Miqu=C3=A8l_Raynal?=
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<miquel.raynal@free-electrons.com>, Victor Gu <xigu@marvell.com>,
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Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Date: Thu, 28 Sep 2017 14:58:34 +0200
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From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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List-Id: <linux-pci.vger.kernel.org>
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From: Victor Gu <xigu@marvell.com>
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Since the Aardvark does not implement a PCIe root bus, the Linux PCIe
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subsystem will not align the MAX payload size between the host and the
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device. This patch ensures that the host and device have the same MAX
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payload size, fixing a number of problems with various PCIe devices.
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This is part of fixing bug
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https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
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reported as the user to be important to get a Intel 7260 mini-PCIe
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WiFi card working.
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Fixes: Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
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Signed-off-by: Victor Gu <xigu@marvell.com>
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Reviewed-by: Evan Wang <xswang@marvell.com>
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Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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[Thomas: tweak commit log.]
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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---
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drivers/pci/controller/pci-aardvark.c | 60 ++++++++++++++++++++++++++++++++++++++++-
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1 file changed, 59 insertions(+), 1 deletion(-)
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--- a/drivers/pci/controller/pci-aardvark.c
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+++ b/drivers/pci/controller/pci-aardvark.c
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@@ -29,9 +29,11 @@
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#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
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#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
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#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
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+#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2
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#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
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#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
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#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2
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+#define PCIE_CORE_MPS_UNIT_BYTE 128
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#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
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#define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
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#define PCIE_CORE_LINK_TRAINING BIT(5)
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@@ -253,7 +255,8 @@ static void advk_pcie_setup_hw(struct ad
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/* Set PCIe Device Control and Status 1 PF0 register */
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reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
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- (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
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+ (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ <<
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+ PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
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PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
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(PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
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PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
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@@ -838,6 +841,58 @@ out_release_res:
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return err;
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}
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+static int advk_pcie_find_smpss(struct pci_dev *dev, void *data)
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+{
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+ u8 *smpss = data;
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+
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+ if (!dev)
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+ return 0;
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+
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+ if (!pci_is_pcie(dev))
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+ return 0;
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+
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+ if (*smpss > dev->pcie_mpss)
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+ *smpss = dev->pcie_mpss;
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+
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+ return 0;
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+}
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+
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+static int advk_pcie_bus_configure_mps(struct pci_dev *dev, void *data)
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+{
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+ int mps;
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+
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+ if (!dev)
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+ return 0;
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+
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+ if (!pci_is_pcie(dev))
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+ return 0;
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+
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+ mps = PCIE_CORE_MPS_UNIT_BYTE << *(u8 *)data;
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+ pcie_set_mps(dev, mps);
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+
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+ return 0;
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+}
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+
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+static void advk_pcie_configure_mps(struct pci_bus *bus, struct advk_pcie *pcie)
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+{
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+ u8 smpss = PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ;
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+ u32 reg;
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+
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+ /* Find the minimal supported MAX payload size */
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+ advk_pcie_find_smpss(bus->self, &smpss);
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+ pci_walk_bus(bus, advk_pcie_find_smpss, &smpss);
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+
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+ /* Configure RC MAX payload size */
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+ reg = advk_readl(pcie, PCIE_CORE_DEV_CTRL_STATS_REG);
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+ reg &= ~PCI_EXP_DEVCTL_PAYLOAD;
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+ reg |= smpss << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT;
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+ advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
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+
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+ /* Configure device MAX payload size */
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+ advk_pcie_bus_configure_mps(bus->self, &smpss);
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+ pci_walk_bus(bus, advk_pcie_bus_configure_mps, &smpss);
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+}
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+
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static int advk_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@@ -912,6 +967,9 @@ static int advk_pcie_probe(struct platfo
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list_for_each_entry(child, &bus->children, node)
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pcie_bus_configure_settings(child);
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+ /* Configure the MAX pay load size */
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+ advk_pcie_configure_mps(bus, pcie);
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+
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pci_bus_add_devices(bus);
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return 0;
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}
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@ -1,43 +0,0 @@
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From f70b629e488cc3f2a325ac35476f4f7ae502c5d0 Mon Sep 17 00:00:00 2001
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From: Tomasz Maciej Nowak <tmn505@gmail.com>
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Date: Thu, 14 Jun 2018 14:24:40 +0200
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Subject: [PATCH 1/2] PCI: aardvark: allow to specify link capability
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Use DT of_pci_get_max_link_speed() facility to allow specifying link
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capability. If none or unspecified value is given it falls back to gen2,
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which is default for Armada 3700 SoC.
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Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
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---
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drivers/pci/controller/pci-aardvark.c | 11 +++++++++--
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1 file changed, 9 insertions(+), 2 deletions(-)
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--- a/drivers/pci/controller/pci-aardvark.c
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+++ b/drivers/pci/controller/pci-aardvark.c
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@@ -233,6 +233,8 @@ static int advk_pcie_wait_for_link(struc
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static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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{
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+ struct device *dev = &pcie->pdev->dev;
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+ struct device_node *node = dev->of_node;
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u32 reg;
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/* Set to Direct mode */
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@@ -267,10 +269,15 @@ static void advk_pcie_setup_hw(struct ad
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PCIE_CORE_CTRL2_TD_ENABLE;
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advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
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- /* Set GEN2 */
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+ /* Set GEN */
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reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
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reg &= ~PCIE_GEN_SEL_MSK;
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- reg |= SPEED_GEN_2;
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+ if (of_pci_get_max_link_speed(node) == 1)
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+ reg |= SPEED_GEN_1;
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+ else if (of_pci_get_max_link_speed(node) == 3)
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+ reg |= SPEED_GEN_3;
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+ else
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+ reg |= SPEED_GEN_2;
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advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
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/* Set lane X1 */
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@ -1,80 +0,0 @@
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diff --git a/drivers/cpufreq/armada-37xx-cpufreq.c b/drivers/cpufreq/armada-37xx-cpufreq.c
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index 75491fc84..c2adf380b 100644
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--- a/drivers/cpufreq/armada-37xx-cpufreq.c
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+++ b/drivers/cpufreq/armada-37xx-cpufreq.c
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@@ -162,11 +162,25 @@ static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
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}
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/*
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- * Set cpu clock source, for all the level we keep the same
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- * clock source that the one already configured. For this one
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- * we need to use the clock framework
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- */
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+ * Set CPU clock source, for all the level we keep the same
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+ * clock source that the one already configured with DVS
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+ * disabled. For this one we need to use the clock framewor
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+ */
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parent = clk_get_parent(clk);
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+
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+ /*
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+ * Unset parent clock to force the clock framework setting again
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+ * the clock parent
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+ */
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+ clk_set_parent(clk, NULL);
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+
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+ /*
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+ * For the Armada 37xx CPU clocks, setting the parent will
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+ * actually configure the parent when DVFS is enabled. At
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+ * hardware level it will be a different register from the one
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+ * read when doing clk_get_parent that will be set with
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+ * clk_set_parent.
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+ */
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clk_set_parent(clk, parent);
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}
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@@ -359,11 +373,11 @@ static int __init armada37xx_cpufreq_driver_init(void)
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struct armada_37xx_dvfs *dvfs;
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struct platform_device *pdev;
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unsigned long freq;
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- unsigned int cur_frequency;
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+ unsigned int cur_frequency, base_frequency;
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struct regmap *nb_pm_base, *avs_base;
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struct device *cpu_dev;
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int load_lvl, ret;
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- struct clk *clk;
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+ struct clk *clk, *parent;
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nb_pm_base =
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syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
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@@ -399,6 +413,22 @@ static int __init armada37xx_cpufreq_driver_init(void)
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return PTR_ERR(clk);
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}
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+ parent = clk_get_parent(clk);
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+ if (IS_ERR(parent)) {
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+ dev_err(cpu_dev, "Cannot get parent clock for CPU0\n");
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+ clk_put(clk);
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+ return PTR_ERR(parent);
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+ }
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+
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+ /* Get parent CPU frequency */
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+ base_frequency = clk_get_rate(parent);
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+
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+ if (!base_frequency) {
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+ dev_err(cpu_dev, "Failed to get parent clock rate for CPU\n");
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+ clk_put(clk);
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+ return -EINVAL;
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+ }
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+
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/* Get nominal (current) CPU frequency */
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cur_frequency = clk_get_rate(clk);
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if (!cur_frequency) {
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@@ -431,7 +461,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
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for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
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load_lvl++) {
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unsigned long u_volt = avs_map[dvfs->avs[load_lvl]] * 1000;
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- freq = cur_frequency / dvfs->divider[load_lvl];
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+ freq = base_frequency / dvfs->divider[load_lvl];
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ret = dev_pm_opp_add(cpu_dev, freq, u_volt);
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if (ret)
|
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goto remove_opp;
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|
|
@ -1,57 +0,0 @@
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From 8fe9a4c4a024a6353e810a1dbb5e4bc78bff60a8 Mon Sep 17 00:00:00 2001
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From: FlashBurnGitHub <33546258+FlashBurnGitHub@users.noreply.github.com>
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Date: Wed, 6 Mar 2019 17:25:46 +0100
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Subject: [PATCH] Fix problem with cpu scaling not working
|
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This fixes a problem that the cpu scaling is not working.
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First one needs to first unset the parent clock, before setting the same old parent clock again. This solves the problem that the wrong TBG clock source was used for the cpu.
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|
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Also one needs to multiply the current cpu frequency with the used divider so that the right cpu frequency gets calculated when applying the dividers. This was need for a 600MHz final cpu frequency to work
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---
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drivers/cpufreq/armada-37xx-cpufreq.c | 11 ++++++++++-
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1 file changed, 10 insertions(+), 1 deletion(-)
|
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|
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diff --git a/drivers/cpufreq/armada-37xx-cpufreq.c b/drivers/cpufreq/armada-37xx-cpufreq.c
|
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index 75491fc841a6..5c744092f819 100644
|
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--- a/drivers/cpufreq/armada-37xx-cpufreq.c
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+++ b/drivers/cpufreq/armada-37xx-cpufreq.c
|
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@@ -167,6 +167,11 @@ static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
|
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* we need to use the clock framework
|
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*/
|
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parent = clk_get_parent(clk);
|
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+
|
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+ /* Unset parent clock */
|
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+ clk_set_parent(clk, NULL);
|
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+
|
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+ /* set old parent; this triggers setting needed values for right CPU clock in hardware regs */
|
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clk_set_parent(clk, parent);
|
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}
|
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|
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@@ -360,6 +365,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
|
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struct platform_device *pdev;
|
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unsigned long freq;
|
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unsigned int cur_frequency;
|
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+ unsigned int base_frequency;
|
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struct regmap *nb_pm_base, *avs_base;
|
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struct device *cpu_dev;
|
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int load_lvl, ret;
|
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@@ -412,6 +418,9 @@ static int __init armada37xx_cpufreq_driver_init(void)
|
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clk_put(clk);
|
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return -EINVAL;
|
||||
}
|
||||
+
|
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+ /* Get base CPU frequency without divider */
|
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+ base_frequency = cur_frequency * dvfs->divider[ARMADA_37XX_DVFS_LOAD_0];
|
||||
|
||||
armada37xx_cpufreq_state = kmalloc(sizeof(*armada37xx_cpufreq_state),
|
||||
GFP_KERNEL);
|
||||
@@ -431,7 +440,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
|
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for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
|
||||
load_lvl++) {
|
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unsigned long u_volt = avs_map[dvfs->avs[load_lvl]] * 1000;
|
||||
- freq = cur_frequency / dvfs->divider[load_lvl];
|
||||
+ freq = base_frequency / dvfs->divider[load_lvl];
|
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ret = dev_pm_opp_add(cpu_dev, freq, u_volt);
|
||||
if (ret)
|
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goto remove_opp;
|
||||
|
|
@ -1,72 +0,0 @@
|
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diff --git a/drivers/net/wireless/ath/regd.c b/drivers/net/wireless/ath/regd.c
|
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index ccc4c71..71a4d00 100644
|
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--- a/drivers/net/wireless/ath/regd.c
|
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+++ b/drivers/net/wireless/ath/regd.c
|
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@@ -49,12 +49,9 @@ static int __ath_regd_init(struct ath_regulatory *reg);
|
||||
#define ATH9K_5GHZ_5725_5850 REG_RULE(5725-10, 5850+10, 40, 0, 30,\
|
||||
NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
|
||||
|
||||
-#define ATH9K_2GHZ_ALL ATH9K_2GHZ_CH01_11, \
|
||||
- ATH9K_2GHZ_CH12_13, \
|
||||
- ATH9K_2GHZ_CH14
|
||||
+#define ATH9K_2GHZ_ALL REG_RULE(2400, 2483, 40, 0, 30, 0)
|
||||
|
||||
-#define ATH9K_5GHZ_ALL ATH9K_5GHZ_5150_5350, \
|
||||
- ATH9K_5GHZ_5470_5850
|
||||
+#define ATH9K_5GHZ_ALL REG_RULE(5140, 5860, 40, 0, 30, 0)
|
||||
|
||||
/* This one skips what we call "mid band" */
|
||||
#define ATH9K_5GHZ_NO_MIDBAND ATH9K_5GHZ_5150_5350, \
|
||||
@@ -76,9 +73,8 @@ static const struct ieee80211_regdomain ath_world_regdom_63_65 = {
|
||||
.n_reg_rules = 4,
|
||||
.alpha2 = "99",
|
||||
.reg_rules = {
|
||||
- ATH9K_2GHZ_CH01_11,
|
||||
- ATH9K_2GHZ_CH12_13,
|
||||
- ATH9K_5GHZ_NO_MIDBAND,
|
||||
+ ATH9K_2GHZ_ALL,
|
||||
+ ATH9K_5GHZ_ALL,
|
||||
}
|
||||
};
|
||||
|
||||
@@ -87,8 +83,8 @@ static const struct ieee80211_regdomain ath_world_regdom_64 = {
|
||||
.n_reg_rules = 3,
|
||||
.alpha2 = "99",
|
||||
.reg_rules = {
|
||||
- ATH9K_2GHZ_CH01_11,
|
||||
- ATH9K_5GHZ_NO_MIDBAND,
|
||||
+ ATH9K_2GHZ_ALL,
|
||||
+ ATH9K_5GHZ_ALL,
|
||||
}
|
||||
};
|
||||
|
||||
@@ -97,7 +93,7 @@ static const struct ieee80211_regdomain ath_world_regdom_66_69 = {
|
||||
.n_reg_rules = 3,
|
||||
.alpha2 = "99",
|
||||
.reg_rules = {
|
||||
- ATH9K_2GHZ_CH01_11,
|
||||
+ ATH9K_2GHZ_ALL,
|
||||
ATH9K_5GHZ_ALL,
|
||||
}
|
||||
};
|
||||
@@ -107,8 +103,7 @@ static const struct ieee80211_regdomain ath_world_regdom_67_68_6A_6C = {
|
||||
.n_reg_rules = 4,
|
||||
.alpha2 = "99",
|
||||
.reg_rules = {
|
||||
- ATH9K_2GHZ_CH01_11,
|
||||
- ATH9K_2GHZ_CH12_13,
|
||||
+ ATH9K_2GHZ_ALL,
|
||||
ATH9K_5GHZ_ALL,
|
||||
}
|
||||
};
|
||||
@@ -253,9 +253,7 @@ static bool ath_is_radar_freq(u16 center_freq,
|
||||
struct ath_regulatory *reg)
|
||||
|
||||
{
|
||||
- if (reg->country_code == CTRY_INDIA)
|
||||
- return (center_freq >= 5500 && center_freq <= 5700);
|
||||
- return (center_freq >= 5260 && center_freq <= 5700);
|
||||
+ return false;
|
||||
}
|
||||
|
||||
static void ath_force_clear_no_ir_chan(struct wiphy *wiphy,
|
||||
Loading…
Add table
Add a link
Reference in a new issue