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Merge pull request #1722 from armbian/clearfog-legacy-4.14
Check & Rework remaining patches for mvebu (sfp on legacy, and pcie on current)
This commit is contained in:
Jannis
GitHub
commit
43075a04b5
18 changed files with 111 additions and 345 deletions
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@ -1,60 +0,0 @@
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From 287b9df160b6159f8d385424904f8bac501280c1 Mon Sep 17 00:00:00 2001
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From: Russell King <rmk+kernel@armlinux.org.uk>
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Date: Sat, 9 Jul 2016 10:58:16 +0100
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Subject: pci: mvebu: time out reset on link up
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If the port reports that the link is up while we are resetting, there's
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little point in waiting for the full duration.
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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---
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drivers/pci/controller/pci-mvebu.c | 20 ++++++++++++++------
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1 file changed, 14 insertions(+), 6 deletions(-)
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--- a/drivers/pci/controller/pci-mvebu.c
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+++ b/drivers/pci/controller/pci-mvebu.c
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@@ -1167,6 +1167,7 @@ static int mvebu_pcie_powerup(struct mve
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if (port->reset_gpio) {
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u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
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+ unsigned int i;
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of_property_read_u32(port->dn, "reset-delay-us",
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&reset_udelay);
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@@ -1174,7 +1175,13 @@ static int mvebu_pcie_powerup(struct mve
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udelay(100);
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gpiod_set_value_cansleep(port->reset_gpio, 0);
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- msleep(reset_udelay / 1000);
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+ for (i = 0; i < reset_udelay; i += 1000) {
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+ if (mvebu_pcie_link_up(port))
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+ break;
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+ msleep(1);
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+ }
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+
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+ printk("%s: reset completed in %dus\n", port->name, i);
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}
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return 0;
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@@ -1261,15 +1268,16 @@ static int mvebu_pcie_probe(struct platf
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if (!child)
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continue;
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- ret = mvebu_pcie_powerup(port);
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- if (ret < 0)
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- continue;
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-
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port->base = mvebu_pcie_map_registers(pdev, child, port);
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if (IS_ERR(port->base)) {
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dev_err(dev, "%s: cannot map registers\n", port->name);
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port->base = NULL;
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- mvebu_pcie_powerdown(port);
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+ continue;
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+ }
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+
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+ ret = mvebu_pcie_powerup(port);
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+ if (ret < 0) {
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+ port->base = NULL;
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continue;
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}
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@ -1,8 +1,8 @@
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diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
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index 53b79c5..7980be0 100644
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index c7588caf0..d82069511 100644
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--- a/drivers/pci/controller/pci-mvebu.c
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+++ b/drivers/pci/controller/pci-mvebu.c
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@@ -51,7 +51,14 @@
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@@ -53,13 +53,26 @@
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PCIE_CONF_ADDR_EN)
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#define PCIE_CONF_DATA_OFF 0x18fc
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#define PCIE_MASK_OFF 0x1910
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@ -17,15 +17,30 @@ index 53b79c5..7980be0 100644
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#define PCIE_CTRL_OFF 0x1a00
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#define PCIE_CTRL_X1_MODE 0x0001
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#define PCIE_STAT_OFF 0x1a04
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@@ -455,6 +462,54 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
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MVEBU_MBUS_NO_REMAP);
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#define PCIE_STAT_BUS 0xff00
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#define PCIE_STAT_DEV 0x1f0000
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#define PCIE_STAT_LINK_DOWN BIT(0)
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+#define PCIE_SSPL 0x1a0c
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+#define PCIE_SSPL_MSGEN BIT(14)
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+#define PCIE_SSPL_SPLS(x) (((x) & 3) << 8)
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+#define PCIE_SSPL_SPLS_VAL(x) (((x) >> 8) & 3)
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+#define PCIE_SSPL_SPLV(x) ((x) & 0xff)
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+#define PCIE_SSPL_SPLV_VAL(x) ((x) & 0xff)
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#define PCIE_RC_RTSTA 0x1a14
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#define PCIE_DEBUG_CTRL 0x1a60
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#define PCIE_DEBUG_SOFT_RESET BIT(20)
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@@ -424,6 +437,60 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
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&port->memwin);
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}
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+static void mvebu_pcie_handle_irq_change(struct mvebu_pcie_port *port)
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+{
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+ u32 reg, old;
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+ u16 devctl, rtctl;
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+
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+ struct pci_bridge_emul_conf *conf = &port->bridge.conf;
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+ struct pci_bridge_emul_pcie_conf *pcie_conf = &port->bridge.pcie_conf;
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+
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+ /*
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+ * Errors from downstream devices:
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+ * bridge control register SERR: enables reception of errors
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@ -40,28 +55,31 @@ index 53b79c5..7980be0 100644
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+ * 2. root error status register updated
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+ * 3. root error command register: forwarding via MSI
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+ */
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+
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+
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+ old = mvebu_readl(port, PCIE_MASK_OFF);
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+ reg = old & ~(PCIE_MASK_PM_PME | PCIE_MASK_FERR_DET |
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+ PCIE_MASK_NFERR_DET | PCIE_MASK_CORERR_DET |
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+ PCIE_MASK_ERR_COR | PCIE_MASK_ERR_NONFATAL |
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+ PCIE_MASK_ERR_FATAL);
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+
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+ devctl = port->bridge.pcie_devctl;
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+ devctl = pcie_conf->devctl;//port->bridge.pcie_conf;
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+ if (devctl & PCI_EXP_DEVCTL_FERE)
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+ reg |= PCIE_MASK_FERR_DET | PCIE_MASK_ERR_FATAL;
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+ if (devctl & PCI_EXP_DEVCTL_NFERE)
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+ reg |= PCIE_MASK_NFERR_DET | PCIE_MASK_ERR_NONFATAL;
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+ if (devctl & PCI_EXP_DEVCTL_CERE)
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+ reg |= PCIE_MASK_CORERR_DET | PCIE_MASK_ERR_COR;
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+ if (port->bridge.command & PCI_COMMAND_SERR)
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+
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+ if (conf->command & PCI_COMMAND_SERR)
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+ reg |= PCIE_MASK_FERR_DET | PCIE_MASK_NFERR_DET |
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+ PCIE_MASK_ERR_FATAL | PCIE_MASK_ERR_NONFATAL;
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+
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+ if (!(port->bridge.bridgectrl & PCI_BRIDGE_CTL_SERR))
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+ if (!(conf->bridgectrl & PCI_BRIDGE_CTL_SERR))
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+ reg &= ~(PCIE_MASK_ERR_COR | PCIE_MASK_ERR_NONFATAL |
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+ PCIE_MASK_ERR_FATAL);
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+
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+ rtctl = port->bridge.pcie_rtctl;
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+ rtctl = pcie_conf->rootctl;//port->bridge.pcie_rtctl;
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+ if (rtctl & PCI_EXP_RTCTL_PMEIE)
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+ reg |= PCIE_MASK_PM_PME;
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+
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@ -69,32 +87,15 @@ index 53b79c5..7980be0 100644
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+ mvebu_writel(port, reg, PCIE_MASK_OFF);
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+}
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+
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/*
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* Initialize the configuration space of the PCI-to-PCI bridge
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* associated with the given PCIe interface.
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@@ -478,6 +533,7 @@ static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
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/* Add capabilities */
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bridge->status = PCI_STATUS_CAP_LIST;
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+ bridge->bridgectrl = PCI_BRIDGE_CTL_SERR;
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}
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/*
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@@ -550,7 +606,7 @@ static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
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case PCI_INTERRUPT_LINE:
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/* LINE PIN MIN_GNT MAX_LAT */
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- *value = 0;
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+ *value = bridge->bridgectrl << 16;
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break;
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case PCISWCAP_EXP_LIST_ID:
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@@ -599,6 +655,16 @@ static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
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static pci_bridge_emul_read_status_t
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mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
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int reg, u32 *value)
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@@ -462,6 +529,29 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
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*value = mvebu_readl(port, PCIE_RC_RTSTA);
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break;
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+ case 0x100 ... 0x128:
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+ *value = mvebu_readl(port, where & ~3);
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+ *value = mvebu_readl(port, reg);
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+ break;
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+
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+ case 0x100 + PCI_ERR_ROOT_COMMAND:
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@ -103,94 +104,96 @@ index 53b79c5..7980be0 100644
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+ *value = 0;
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+ break;
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+
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/* PCIe requires the v2 fields to be hard-wired to zero */
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case PCISWCAP_EXP_DEVCAP2:
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case PCISWCAP_EXP_DEVCTL2:
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@@ -629,7 +695,7 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
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unsigned int where, int size, u32 value)
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{
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struct mvebu_sw_pci_bridge *bridge = &port->bridge;
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- u32 mask, reg;
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+ u32 mask, reg, old;
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int err;
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if (size == 4)
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@@ -649,8 +715,7 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
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switch (where & ~3) {
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case PCI_COMMAND:
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- {
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- u32 old = bridge->command;
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+ old = bridge->command;
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if (!mvebu_has_ioport(port))
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value &= ~PCI_COMMAND_IO;
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@@ -660,8 +725,9 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
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+ case PCI_EXP_SLTCAP:
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+ {
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+ u32 tmp = mvebu_readl(port, PCIE_SSPL);
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+ *value = PCIE_SSPL_SPLS_VAL(tmp) << 15 |
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+ PCIE_SSPL_SPLV_VAL(tmp) << 7;
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+ break;
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+ }
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+
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+ case PCI_INTERRUPT_LINE:
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+ /* LINE PIN MIN_GNT MAX_LAT */
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+ *value = bridge->conf.bridgectrl << 16;
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+ break;
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+
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default:
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return PCI_BRIDGE_EMUL_NOT_HANDLED;
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}
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@@ -486,7 +576,8 @@ mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
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mvebu_pcie_handle_iobase_change(port);
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if ((old ^ bridge->command) & PCI_COMMAND_MEMORY)
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if ((old ^ new) & PCI_COMMAND_MEMORY)
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mvebu_pcie_handle_membase_change(port);
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+ if ((old ^ bridge->command) & PCI_COMMAND_SERR)
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-
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+ if ((old ^ new) & PCI_COMMAND_SERR)
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+ mvebu_pcie_handle_irq_change(port);
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break;
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- }
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case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
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bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
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@@ -690,6 +756,17 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
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}
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@@ -509,6 +600,16 @@ mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
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mvebu_pcie_handle_iobase_change(port);
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break;
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+ case PCI_INTERRUPT_LINE:
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+ value >>= 16;
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+ old = bridge->bridgectrl;
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+ new >>= 16;
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+ /* PCIe only has three bits here */
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+ bridge->bridgectrl = value & (PCI_BRIDGE_CTL_BUS_RESET |
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+ conf->bridgectrl = new & (PCI_BRIDGE_CTL_BUS_RESET |
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+ PCI_BRIDGE_CTL_SERR |
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+ PCI_BRIDGE_CTL_PARITY);
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+ if ((old ^ bridge->bridgectrl) & PCI_BRIDGE_CTL_SERR)
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+ if ((old ^ conf->bridgectrl) & PCI_BRIDGE_CTL_SERR)
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+ mvebu_pcie_handle_irq_change(port);
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+ break;
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+
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case PCI_PRIMARY_BUS:
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bridge->primary_bus = value & 0xff;
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bridge->secondary_bus = (value >> 8) & 0xff;
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@@ -699,6 +776,14 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
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mvebu_pcie_set_local_bus_nr(port, conf->secondary_bus);
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break;
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case PCISWCAP_EXP_DEVCTL:
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+ old = bridge->pcie_devctl;
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+ bridge->pcie_devctl = value & (PCI_EXP_DEVCTL_FERE |
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@@ -526,6 +627,13 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
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switch (reg) {
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case PCI_EXP_DEVCTL:
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+ bridge->pcie_conf.devctl = new & (PCI_EXP_DEVCTL_FERE |
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+ PCI_EXP_DEVCTL_NFERE |
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+ PCI_EXP_DEVCTL_CERE |
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+ PCI_EXP_DEVCTL_URRE);
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+ if (bridge->pcie_devctl ^ old)
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+ if (bridge->pcie_conf.devctl ^ old)
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+ mvebu_pcie_handle_irq_change(port);
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+
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/*
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* Armada370 data says these bits must always
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* be zero when in root complex mode.
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@@ -739,10 +824,24 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
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mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
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@@ -551,6 +659,27 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
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case PCI_EXP_RTSTA:
|
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mvebu_writel(port, new, PCIE_RC_RTSTA);
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break;
|
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|
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+ case PCISWCAP_EXP_RTCTL:
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+ old = bridge->pcie_rtctl;
|
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+ bridge->pcie_rtctl = value & (PCI_EXP_RTCTL_SECEE |
|
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+
|
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+ case PCI_EXP_SLTCAP:
|
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+ {
|
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+ u32 sspl = PCIE_SSPL_SPLV((new & PCI_EXP_SLTCAP_SPLV) >> 7) |
|
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+ PCIE_SSPL_SPLS((new & PCI_EXP_SLTCAP_SPLS) >> 15) |
|
||||
+ PCIE_SSPL_MSGEN;
|
||||
+ mvebu_writel(port, sspl, PCIE_SSPL);
|
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+ break;
|
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+ }
|
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+
|
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+ case PCI_EXP_RTCTL:
|
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+ bridge->pcie_conf.rootctl = new & (PCI_EXP_RTCTL_SECEE |
|
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+ PCI_EXP_RTCTL_SENFEE |
|
||||
+ PCI_EXP_RTCTL_SEFEE |
|
||||
+ PCI_EXP_RTCTL_PMEIE);
|
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+ if (bridge->pcie_rtctl ^ old)
|
||||
+ if (bridge->pcie_conf.rootctl ^ old)
|
||||
+ mvebu_pcie_handle_irq_change(port);
|
||||
+ break;
|
||||
+
|
||||
case PCISWCAP_EXP_RTSTA:
|
||||
mvebu_writel(port, value, PCIE_RC_RTSTA);
|
||||
break;
|
||||
|
||||
+ case 0x100 ... 0x128:
|
||||
+ mvebu_writel(port, value, where & ~3);
|
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+ mvebu_writel(port, new, reg);
|
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+ break;
|
||||
+
|
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default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -579,6 +708,7 @@ static void mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port)
|
||||
bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
|
||||
}
|
||||
|
||||
+ bridge->conf.bridgectrl = PCI_BRIDGE_CTL_SERR;
|
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bridge->has_pcie = true;
|
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bridge->data = port;
|
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bridge->ops = &mvebu_pci_bridge_emul_ops;
|
||||
|
|
@ -1,60 +0,0 @@
|
|||
From 287b9df160b6159f8d385424904f8bac501280c1 Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
Date: Sat, 9 Jul 2016 10:58:16 +0100
|
||||
Subject: pci: mvebu: time out reset on link up
|
||||
|
||||
If the port reports that the link is up while we are resetting, there's
|
||||
little point in waiting for the full duration.
|
||||
|
||||
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
---
|
||||
drivers/pci/controller/pci-mvebu.c | 20 ++++++++++++++------
|
||||
1 file changed, 14 insertions(+), 6 deletions(-)
|
||||
|
||||
--- a/drivers/pci/controller/pci-mvebu.c
|
||||
+++ b/drivers/pci/controller/pci-mvebu.c
|
||||
@@ -1167,6 +1167,7 @@ static int mvebu_pcie_powerup(struct mve
|
||||
|
||||
if (port->reset_gpio) {
|
||||
u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
|
||||
+ unsigned int i;
|
||||
|
||||
of_property_read_u32(port->dn, "reset-delay-us",
|
||||
&reset_udelay);
|
||||
@@ -1174,7 +1175,13 @@ static int mvebu_pcie_powerup(struct mve
|
||||
udelay(100);
|
||||
|
||||
gpiod_set_value_cansleep(port->reset_gpio, 0);
|
||||
- msleep(reset_udelay / 1000);
|
||||
+ for (i = 0; i < reset_udelay; i += 1000) {
|
||||
+ if (mvebu_pcie_link_up(port))
|
||||
+ break;
|
||||
+ msleep(1);
|
||||
+ }
|
||||
+
|
||||
+ printk("%s: reset completed in %dus\n", port->name, i);
|
||||
}
|
||||
|
||||
return 0;
|
||||
@@ -1261,15 +1268,16 @@ static int mvebu_pcie_probe(struct platf
|
||||
if (!child)
|
||||
continue;
|
||||
|
||||
- ret = mvebu_pcie_powerup(port);
|
||||
- if (ret < 0)
|
||||
- continue;
|
||||
-
|
||||
port->base = mvebu_pcie_map_registers(pdev, child, port);
|
||||
if (IS_ERR(port->base)) {
|
||||
dev_err(dev, "%s: cannot map registers\n", port->name);
|
||||
port->base = NULL;
|
||||
- mvebu_pcie_powerdown(port);
|
||||
+ continue;
|
||||
+ }
|
||||
+
|
||||
+ ret = mvebu_pcie_powerup(port);
|
||||
+ if (ret < 0) {
|
||||
+ port->base = NULL;
|
||||
continue;
|
||||
}
|
||||
|
||||
|
|
@ -1,67 +0,0 @@
|
|||
From ae07b208fe4e228068282ad76cfd69ab9e96dc9f Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
Date: Mon, 28 Dec 2015 13:55:13 +0100
|
||||
Subject: [PATCH] implement slot capabilities (SSPL)
|
||||
|
||||
---
|
||||
drivers/pci/controller/pci-mvebu.c | 22 ++++++++++++++++++++--
|
||||
1 file changed, 20 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
|
||||
index 7980be0..0e9b820 100644
|
||||
--- a/drivers/pci/controller/pci-mvebu.c
|
||||
+++ b/drivers/pci/controller/pci-mvebu.c
|
||||
@@ -65,6 +65,12 @@
|
||||
#define PCIE_STAT_BUS 0xff00
|
||||
#define PCIE_STAT_DEV 0x1f0000
|
||||
#define PCIE_STAT_LINK_DOWN BIT(0)
|
||||
+#define PCIE_SSPL 0x1a0c
|
||||
+#define PCIE_SSPL_MSGEN BIT(14)
|
||||
+#define PCIE_SSPL_SPLS(x) (((x) & 3) << 8)
|
||||
+#define PCIE_SSPL_SPLS_VAL(x) (((x) >> 8) & 3)
|
||||
+#define PCIE_SSPL_SPLV(x) ((x) & 0xff)
|
||||
+#define PCIE_SSPL_SPLV_VAL(x) ((x) & 0xff)
|
||||
#define PCIE_RC_RTSTA 0x1a14
|
||||
#define PCIE_DEBUG_CTRL 0x1a60
|
||||
#define PCIE_DEBUG_SOFT_RESET BIT(20)
|
||||
@@ -119,7 +125,6 @@ struct mvebu_sw_pci_bridge {
|
||||
u16 bridgectrl;
|
||||
|
||||
/* PCI express capability */
|
||||
- u32 pcie_sltcap;
|
||||
u16 pcie_devctl;
|
||||
u16 pcie_rtctl;
|
||||
};
|
||||
@@ -640,8 +645,12 @@ static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
|
||||
break;
|
||||
|
||||
case PCISWCAP_EXP_SLTCAP:
|
||||
- *value = bridge->pcie_sltcap;
|
||||
+ {
|
||||
+ u32 tmp = mvebu_readl(port, PCIE_SSPL);
|
||||
+ *value = PCIE_SSPL_SPLS_VAL(tmp) << 15 |
|
||||
+ PCIE_SSPL_SPLV_VAL(tmp) << 7;
|
||||
break;
|
||||
+ }
|
||||
|
||||
case PCISWCAP_EXP_SLTCTL:
|
||||
*value = PCI_EXP_SLTSTA_PDS << 16;
|
||||
@@ -824,6 +833,15 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
|
||||
mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
|
||||
break;
|
||||
|
||||
+ case PCISWCAP_EXP_SLTCAP:
|
||||
+ {
|
||||
+ u32 sspl = PCIE_SSPL_SPLV((value & PCI_EXP_SLTCAP_SPLV) >> 7) |
|
||||
+ PCIE_SSPL_SPLS((value & PCI_EXP_SLTCAP_SPLS) >> 15) |
|
||||
+ PCIE_SSPL_MSGEN;
|
||||
+ mvebu_writel(port, sspl, PCIE_SSPL);
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
case PCISWCAP_EXP_RTCTL:
|
||||
old = bridge->pcie_rtctl;
|
||||
bridge->pcie_rtctl = value & (PCI_EXP_RTCTL_SECEE |
|
||||
--
|
||||
1.9.1
|
||||
|
||||
|
|
@ -928,10 +928,11 @@ Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
|||
return 0;
|
||||
|
||||
err_netdev:
|
||||
@@ -4386,16 +4492,14 @@ err_netdev:
|
||||
1 << pp->id);
|
||||
}
|
||||
err_free_stats:
|
||||
@@ -4385,16 +4491,15 @@ err_netdev:
|
||||
mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
|
||||
1 << pp->id);
|
||||
}
|
||||
+err_free_stats:
|
||||
+ if (pp->phylink)
|
||||
+ phylink_destroy(pp->phylink);
|
||||
free_percpu(pp->stats);
|
||||
|
|
@ -38,7 +38,7 @@ Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
|||
static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg,
|
||||
u16 mask, u16 bits)
|
||||
{
|
||||
@@ -56,17 +63,52 @@ static int mv3310_modify(struct phy_devi
|
||||
@@ -66,28 +66,52 @@ static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg,
|
||||
return ret < 0 ? ret : 1;
|
||||
}
|
||||
|
||||
|
|
@ -62,21 +62,30 @@ Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
|||
{
|
||||
+ struct mv3310_priv *priv;
|
||||
u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
|
||||
- int ret;
|
||||
|
||||
if (!phydev->is_c45 ||
|
||||
(phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
|
||||
return -ENODEV;
|
||||
|
||||
- ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT);
|
||||
- if (ret < 0)
|
||||
- return ret;
|
||||
+ priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
|
||||
+ if (!priv)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
|
||||
- if (ret & MV_PMA_BOOT_FATAL) {
|
||||
- dev_warn(&phydev->mdio.dev,
|
||||
- "PHY failed to boot firmware, status=%04x\n", ret);
|
||||
- return -ENODEV;
|
||||
- }
|
||||
+ dev_set_drvdata(&phydev->mdio.dev, priv);
|
||||
+
|
||||
+ if (phydev->mdio.dev.of_node)
|
||||
+ priv->sfp_node = of_parse_phandle(phydev->mdio.dev.of_node,
|
||||
+ "sfp", 0);
|
||||
+
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1,60 +0,0 @@
|
|||
From 287b9df160b6159f8d385424904f8bac501280c1 Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
Date: Sat, 9 Jul 2016 10:58:16 +0100
|
||||
Subject: pci: mvebu: time out reset on link up
|
||||
|
||||
If the port reports that the link is up while we are resetting, there's
|
||||
little point in waiting for the full duration.
|
||||
|
||||
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
---
|
||||
drivers/pci/host/pci-mvebu.c | 20 ++++++++++++++------
|
||||
1 file changed, 14 insertions(+), 6 deletions(-)
|
||||
|
||||
--- a/drivers/pci/host/pci-mvebu.c
|
||||
+++ b/drivers/pci/host/pci-mvebu.c
|
||||
@@ -1167,6 +1167,7 @@ static int mvebu_pcie_powerup(struct mve
|
||||
|
||||
if (port->reset_gpio) {
|
||||
u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
|
||||
+ unsigned int i;
|
||||
|
||||
of_property_read_u32(port->dn, "reset-delay-us",
|
||||
&reset_udelay);
|
||||
@@ -1174,7 +1175,13 @@ static int mvebu_pcie_powerup(struct mve
|
||||
udelay(100);
|
||||
|
||||
gpiod_set_value_cansleep(port->reset_gpio, 0);
|
||||
- msleep(reset_udelay / 1000);
|
||||
+ for (i = 0; i < reset_udelay; i += 1000) {
|
||||
+ if (mvebu_pcie_link_up(port))
|
||||
+ break;
|
||||
+ msleep(1);
|
||||
+ }
|
||||
+
|
||||
+ printk("%s: reset completed in %dus\n", port->name, i);
|
||||
}
|
||||
|
||||
return 0;
|
||||
@@ -1261,15 +1268,16 @@ static int mvebu_pcie_probe(struct platf
|
||||
if (!child)
|
||||
continue;
|
||||
|
||||
- ret = mvebu_pcie_powerup(port);
|
||||
- if (ret < 0)
|
||||
- continue;
|
||||
-
|
||||
port->base = mvebu_pcie_map_registers(pdev, child, port);
|
||||
if (IS_ERR(port->base)) {
|
||||
dev_err(dev, "%s: cannot map registers\n", port->name);
|
||||
port->base = NULL;
|
||||
- mvebu_pcie_powerdown(port);
|
||||
+ continue;
|
||||
+ }
|
||||
+
|
||||
+ ret = mvebu_pcie_powerup(port);
|
||||
+ if (ret < 0) {
|
||||
+ port->base = NULL;
|
||||
continue;
|
||||
}
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue