[ sunxi-dev ] Adjust patches, remove deprecated, build tested on Pine H6

lib/compilation-prepare.sh

@@ -159,7 +159,7 @@ compilation_prepare()
 	fi
 
 	# Wireless drivers for Xradio XR819 chipsets
-	if linux-version compare $version ge 4.19 && [ "$LINUXFAMILY" == sunxi ] && [ "$EXTRAWIFI" == yes ]; then
+	if linux-version compare $version ge 4.19 && [[ "$LINUXFAMILY" == sunxi* ]] && [[ "$EXTRAWIFI" == yes ]]; then
 
 		display_alert "Adding" "Wireless drivers for Xradio XR819 chipsets" "info"
 

patch/kernel/sunxi-dev/0009-dt-bindings-update-the-Allwinner-GPADC-device-tree-b.patch

@@ -1,95 +0,0 @@
-From 92e5c7876cef2b53ed3d1701169fcd93b73e0e33 Mon Sep 17 00:00:00 2001
-From: Philipp Rossak <embed3d@gmail.com>
-Date: Sat, 20 Jan 2018 13:25:21 +0100
-Subject: [PATCH 009/146] dt-bindings: update the Allwinner GPADC device tree
- binding for H3 & A83T
-
-Allwinner H3 features a thermal sensor like the one in A33, but has its
-register re-arranged, the clock divider moved to CCU (originally the
-clock divider is in ADC) and added a pair of bus clock and reset.
-
-Allwinner A83T features a thermal sensor similar to the H3, the ths clock,
-the bus clock and the reset was removed from the CCU. The THS in A83T
-has a clock that is directly connected and runs with 24 MHz.
-
-Update the binding document to cover H3 and A83T.
-
-Signed-off-by: Philipp Rossak <embed3d@gmail.com>
----
- .../devicetree/bindings/mfd/sun4i-gpadc.txt   | 50 +++++++++++++++++--
- 1 file changed, 47 insertions(+), 3 deletions(-)
-
-diff --git a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
-index 86dd8191b04c..f6b939617a6d 100644
---- a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
-+++ b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
-@@ -4,12 +4,35 @@ The Allwinner SoCs all have an ADC that can also act as a thermal sensor
- and sometimes as a touchscreen controller.
- 
- Required properties:
--  - compatible: "allwinner,sun8i-a33-ths",
-+  - compatible: must contain one of the following compatibles:
-+		- "allwinner,sun8i-a33-ths"
-+		- "allwinner,sun8i-h3-ths"
-+		- "allwinner,sun8i-a83t-ths"
-   - reg: mmio address range of the chip,
--  - #thermal-sensor-cells: shall be 0,
-+  - #thermal-sensor-cells: shall be 0 or 1,
-   - #io-channel-cells: shall be 0,
- 
--Example:
-+Required properties for the following compatibles:
-+		- "allwinner,sun8i-h3-ths"
-+		- "allwinner,sun8i-a83t-ths"
-+  - interrupts: the sampling interrupt of the ADC,
-+
-+Required properties for the following compatibles:
-+		- "allwinner,sun8i-h3-ths"
-+  - clocks: the bus clock and the input clock of the ADC,
-+  - clock-names: should be "bus" and "mod",
-+  - resets: the bus reset of the ADC,
-+
-+Optional properties for the following compatibles:
-+		- "allwinner,sun8i-h3-ths"
-+  - nvmem-cells: A phandle to the calibration data provided by a nvmem device.
-+		If unspecified default values shall be used. The size should
-+		be 0x4 or 0x8, depending on the amount of CDATA registers.
-+  - nvmem-cell-names: Should be "calibration".
-+
-+Details see: bindings/nvmem/nvmem.txt
-+
-+Example for A33:
- 	ths: ths@1c25000 {
- 		compatible = "allwinner,sun8i-a33-ths";
- 		reg = <0x01c25000 0x100>;
-@@ -17,6 +40,27 @@ Example:
- 		#io-channel-cells = <0>;
- 	};
- 
-+Example for H3:
-+	ths: thermal-sensor@1c25000 {
-+		compatible = "allwinner,sun8i-h3-ths";
-+		reg = <0x01c25000 0x400>;
-+		clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
-+		clock-names = "bus", "mod";
-+		resets = <&ccu RST_BUS_THS>;
-+		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-+		#thermal-sensor-cells = <0>;
-+		#io-channel-cells = <0>;
-+	};
-+
-+Example for A83T:
-+	ths: thermal-sensor@1f04000 {
-+		compatible = "allwinner,sun8i-a83t-ths";
-+		reg = <0x01f04000 0x100>;
-+		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
-+		#thermal-sensor-cells = <1>;
-+		#io-channel-cells = <0>;
-+	};
-+
- sun4i, sun5i and sun6i SoCs are also supported via the older binding:
- 
- sun4i resistive touchscreen controller
--- 
-2.17.1
-

patch/kernel/sunxi-dev/0012-general-h6-new-opp-table.patch

@@ -1,72 +0,0 @@
-diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
-index 141fd186b..4d4dcf8eb 100644
---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
-@@ -67,61 +67,62 @@
- 		};
- 	};
- 
-+	/* axp80,DCDC-A: 0.6~1.1V, 10mV/Step, 51 steps; 1.12~1.52V, 20mV/Step, 21 Steps */
- 	cpu_opp_table: opp_table {
- 		compatible = "operating-points-v2";
- 		opp-shared;
- 
- 		opp@480000000 {
- 			opp-hz = /bits/ 64 <480000000>;
- 			opp-microvolt = <880000 880000 880000>;
- 			clock-latency-ns = <244144>; /* 8 32k periods */
- 		};
- 
- 		opp@720000000 {
- 			opp-hz = /bits/ 64 <720000000>;
- 			opp-microvolt = <880000 880000 880000>;
- 			clock-latency-ns = <244144>; /* 8 32k periods */
- 		};
- 
- 		opp@816000000 {
- 			opp-hz = /bits/ 64 <816000000>;
- 			opp-microvolt = <880000 880000 880000>;
- 			clock-latency-ns = <244144>; /* 8 32k periods */
- 		};
- 
- 		opp@888000000 {
- 			opp-hz = /bits/ 64 <888000000>;
- 			opp-microvolt = <880000 880000 880000>;
- 			clock-latency-ns = <244144>; /* 8 32k periods */
- 		};
- 
- 		opp@1080000000 {
- 			opp-hz = /bits/ 64 <1080000000>;
--			opp-microvolt = <940000 940000 940000>;
-+			opp-microvolt = <880000 880000 940000>;
- 			clock-latency-ns = <244144>; /* 8 32k periods */
- 		};
- 
- 		opp@1320000000 {
- 			opp-hz = /bits/ 64 <1320000000>;
--			opp-microvolt = <1000000 1000000 1000000>;
-+			opp-microvolt = <880000 880000 1000000>;
- 			clock-latency-ns = <244144>; /* 8 32k periods */
- 		};
- 
- 		opp@1488000000 {
- 			opp-hz = /bits/ 64 <1488000000>;
--			opp-microvolt = <1060000 1060000 1060000>;
-+			opp-microvolt = <940000 940000 1060000>;
- 			clock-latency-ns = <244144>; /* 8 32k periods */
- 		};
- 
- 		opp@1640000000 {
- 			opp-hz = /bits/ 64 <1640000000>;
--			opp-microvolt = <1160000 1160000 1160000>;
-+			opp-microvolt = <990000 990000 1160000>;
- 			clock-latency-ns = <244144>; /* 8 32k periods */
- 		};
- 
- 		opp@1800000000 {
- 			opp-hz = /bits/ 64 <1800000000>;
--			opp-microvolt = <1160000 1160000 1160000>;
-+			opp-microvolt = <1050000 1050000 1160000>;
- 			clock-latency-ns = <244144>; /* 8 32k periods */
- 		};
- 	};

patch/kernel/sunxi-dev/0039-dt-bindings-add-switch-delay-property-for-mali-utgar.patch

@@ -1,29 +0,0 @@
-From 93a9dff30ace06dceba2a84eb709433d5e08c7bc Mon Sep 17 00:00:00 2001
-From: Qiang Yu <yuq825@gmail.com>
-Date: Wed, 21 Mar 2018 14:58:02 +0800
-Subject: [PATCH 039/146] dt-bindings: add switch-delay property for
- mali-utgard
-
-Signed-off-by: Qiang Yu <yuq825@gmail.com>
----
- Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
-index 63cd91176a68..3e2590162d4f 100644
---- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
-+++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
-@@ -58,6 +58,10 @@ Optional properties:
-     A power domain consumer specifier as defined in
-     Documentation/devicetree/bindings/power/power_domain.txt
- 
-+  - switch-delay:
-+    This value is the number of Mali clock cycles it takes to
-+    enable the power gates and turn on the power mesh.
-+
- Vendor-specific bindings
- ------------------------
- 
--- 
-2.17.1
-

patch/kernel/sunxi-dev/fix-a64-timejump.patch

@@ -1,27 +1,34 @@
 diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
-index 9a5464c..6334b5a 100644
+index 9a5464c62..91142959c 100644
 --- a/drivers/clocksource/arm_arch_timer.c
 +++ b/drivers/clocksource/arm_arch_timer.c
-@@ -342,16 +342,17 @@ static u64 notrace arm64_858921_read_cntvct_el0(void)
+@@ -341,17 +341,18 @@ static u64 notrace arm64_858921_read_cntvct_el0(void)
+  * with all ones or all zeros in the low bits. Bound the loop by the maximum
   * number of CPU cycles in 3 consecutive 24 MHz counter periods.
   */
- #define __sun50i_a64_read_reg(reg) ({					\
+-#define __sun50i_a64_read_reg(reg) ({					\
 -	u64 _val;							\
 -	int _retries = 150;						\
-+	u64 _old, _new;                                                 \
-+	int _retries = 200;						\
- 									\ 									\
- 	do {								\
+-									\
+-	do {								\
 -		_val = read_sysreg(reg);				\
-+		_old = read_sysreg(reg);				\
-+		_new = read_sysreg(reg);				\
- 		_retries--;						\
+-		_retries--;						\
 -	} while (((_val + 1) & GENMASK(9, 0)) <= 1 && _retries);	\
-+	} while (unlikely(_old != _new) && _retries);			\
- 									\
- 	WARN_ON_ONCE(!_retries);					\
+-									\
+-	WARN_ON_ONCE(!_retries);					\
 -	_val;								\
-+	_new;								\
++#define __sun50i_a64_read_reg(reg) ({							\
++	u64 _old, _new;												\
++	int _retries = 200;											\
++																\
++	do {														\
++		_old = read_sysreg(reg);								\
++		_new = read_sysreg(reg);								\
++		_retries--;												\
++	} while (unlikely(_old != _new) && _retries);				\
++																\
++	WARN_ON_ONCE(!_retries);									\
++	_new;														\
  })
  
  static u64 notrace sun50i_a64_read_cntpct_el0(void)