From 52852469f18e4e312e12f80af1dcd5a7dfc6aba0 Mon Sep 17 00:00:00 2001 From: Martin Ayotte Date: Thu, 10 Jan 2019 18:27:23 -0500 Subject: [PATCH] delete more useless patches --- ...ass-drm_encoder-into-sun4i_tcon0_mod.patch | 66 --------- ...ename-Dithering-related-register-mac.patch | 59 -------- ...dd-dithering-support-for-RGB565-RGB6.patch | 132 ------------------ ...revent-tcon-panel-dereference-if-nul.patch | 34 ----- ...-a64-Add-minimal-rate-for-video-PLLs.patch | 84 ----------- ...-Add-max.-rate-constraint-to-video-P.patch | 90 ------------ ...lay-Add-compatible-for-A64-DE2-displ.patch | 52 ------- ...drm-sun4i-Add-support-for-A64-mixers.patch | 62 -------- ...i-Add-support-for-A64-display-engine.patch | 33 ----- ...i-drm-add-HDMI-VCC-supply-property-f.patch | 33 ----- 10 files changed, 645 deletions(-) delete mode 100644 patch/kernel/sunxi-dev/0087-drm-sun4i-tcon-Pass-drm_encoder-into-sun4i_tcon0_mod.patch delete mode 100644 patch/kernel/sunxi-dev/0088-drm-sun4i-tcon-Rename-Dithering-related-register-mac.patch delete mode 100644 patch/kernel/sunxi-dev/0089-drm-sun4i-tcon-Add-dithering-support-for-RGB565-RGB6.patch delete mode 100644 patch/kernel/sunxi-dev/0090-drm-sun4i-tcon-prevent-tcon-panel-dereference-if-nul.patch delete mode 100644 patch/kernel/sunxi-dev/0091-clk-sunxi-ng-a64-Add-minimal-rate-for-video-PLLs.patch delete mode 100644 patch/kernel/sunxi-dev/0092-clk-sunxi-ng-a64-Add-max.-rate-constraint-to-video-P.patch delete mode 100644 patch/kernel/sunxi-dev/0093-dt-bindings-display-Add-compatible-for-A64-DE2-displ.patch delete mode 100644 patch/kernel/sunxi-dev/0094-drm-sun4i-Add-support-for-A64-mixers.patch delete mode 100644 patch/kernel/sunxi-dev/0095-drm-sun4i-Add-support-for-A64-display-engine.patch delete mode 100644 patch/kernel/sunxi-dev/0099-dt-bindings-sun4i-drm-add-HDMI-VCC-supply-property-f.patch diff --git a/patch/kernel/sunxi-dev/0087-drm-sun4i-tcon-Pass-drm_encoder-into-sun4i_tcon0_mod.patch b/patch/kernel/sunxi-dev/0087-drm-sun4i-tcon-Pass-drm_encoder-into-sun4i_tcon0_mod.patch deleted file mode 100644 index 6e9d0fbf5..000000000 --- a/patch/kernel/sunxi-dev/0087-drm-sun4i-tcon-Pass-drm_encoder-into-sun4i_tcon0_mod.patch +++ /dev/null @@ -1,66 +0,0 @@ -From af6d185a66b416cb714fb3f1602e8e3f5ca46632 Mon Sep 17 00:00:00 2001 -From: Chen-Yu Tsai -Date: Fri, 7 Sep 2018 12:19:43 +0800 -Subject: [PATCH 087/146] drm/sun4i: tcon: Pass drm_encoder * into - sun4i_tcon0_mode_set_cpu - -sun4i_tcon0_mode_set_cpu() currently accepts struct mipi_dsi_device * -as its second parameter. This is derived from drm_encoder. - -The DSI encoder is tied to the CPU interface mode of the TCON as a -special case. In theory, if hardware were available, we could also -support normal CPU interface modes. It is better to pass the generic -encoder instead of the specialized mipi_dsi_device, and handle the -differences inside the function. - -Passing the encoder would also enable the function to pass it, or any -other data structures related to it, to other functions expecting it. -One such example would be dithering support that will be added in a -later patch, which looks at properties tied to the connector to -determine whether dithering should be enabled or not. - -Signed-off-by: Chen-Yu Tsai ---- - drivers/gpu/drm/sun4i/sun4i_tcon.c | 15 ++++++--------- - 1 file changed, 6 insertions(+), 9 deletions(-) - -diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c -index 3fb084f802e2..52e1150612ba 100644 ---- a/drivers/gpu/drm/sun4i/sun4i_tcon.c -+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c -@@ -276,9 +276,12 @@ static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon, - } - - static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon, -- struct mipi_dsi_device *device, -+ const struct drm_encoder *encoder, - const struct drm_display_mode *mode) - { -+ /* TODO support normal CPU interface modes */ -+ struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder); -+ struct mipi_dsi_device *device = dsi->device; - u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format); - u8 lanes = device->lanes; - u32 block_space, start_delay; -@@ -581,16 +584,10 @@ void sun4i_tcon_mode_set(struct sun4i_tcon *tcon, - const struct drm_encoder *encoder, - const struct drm_display_mode *mode) - { -- struct sun6i_dsi *dsi; -- - switch (encoder->encoder_type) { - case DRM_MODE_ENCODER_DSI: -- /* -- * This is not really elegant, but it's the "cleaner" -- * way I could think of... -- */ -- dsi = encoder_to_sun6i_dsi(encoder); -- sun4i_tcon0_mode_set_cpu(tcon, dsi->device, mode); -+ /* DSI is tied to special case of CPU interface */ -+ sun4i_tcon0_mode_set_cpu(tcon, encoder, mode); - break; - case DRM_MODE_ENCODER_LVDS: - sun4i_tcon0_mode_set_lvds(tcon, encoder, mode); --- -2.17.1 - diff --git a/patch/kernel/sunxi-dev/0088-drm-sun4i-tcon-Rename-Dithering-related-register-mac.patch b/patch/kernel/sunxi-dev/0088-drm-sun4i-tcon-Rename-Dithering-related-register-mac.patch deleted file mode 100644 index 3332362bc..000000000 --- a/patch/kernel/sunxi-dev/0088-drm-sun4i-tcon-Rename-Dithering-related-register-mac.patch +++ /dev/null @@ -1,59 +0,0 @@ -From cf81b437511bf56512273c773013c40b11a01520 Mon Sep 17 00:00:00 2001 -From: Chen-Yu Tsai -Date: Fri, 7 Sep 2018 12:19:44 +0800 -Subject: [PATCH 088/146] drm/sun4i: tcon: Rename Dithering related register - macros - -Dithering is only supported for TCON channel 0. Throughout the datasheet -all the names associated with these register are prefixed "TCON0", -instead of "TCON". The only exception is the control register -"TCON_FRM_CTL_REG". - -Rename the macros to reflect this. - -Signed-off-by: Chen-Yu Tsai ---- - drivers/gpu/drm/sun4i/sun4i_tcon.h | 27 +++++++++++++++------------ - 1 file changed, 15 insertions(+), 12 deletions(-) - -diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h -index f6a071cd5a6f..3d492c8be1fc 100644 ---- a/drivers/gpu/drm/sun4i/sun4i_tcon.h -+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h -@@ -37,18 +37,21 @@ - #define SUN4I_TCON_GINT1_REG 0x8 - - #define SUN4I_TCON_FRM_CTL_REG 0x10 --#define SUN4I_TCON_FRM_CTL_EN BIT(31) -- --#define SUN4I_TCON_FRM_SEED_PR_REG 0x14 --#define SUN4I_TCON_FRM_SEED_PG_REG 0x18 --#define SUN4I_TCON_FRM_SEED_PB_REG 0x1c --#define SUN4I_TCON_FRM_SEED_LR_REG 0x20 --#define SUN4I_TCON_FRM_SEED_LG_REG 0x24 --#define SUN4I_TCON_FRM_SEED_LB_REG 0x28 --#define SUN4I_TCON_FRM_TBL0_REG 0x2c --#define SUN4I_TCON_FRM_TBL1_REG 0x30 --#define SUN4I_TCON_FRM_TBL2_REG 0x34 --#define SUN4I_TCON_FRM_TBL3_REG 0x38 -+#define SUN4I_TCON0_FRM_CTL_EN BIT(31) -+#define SUN4I_TCON0_FRM_CTL_MODE_R BIT(6) -+#define SUN4I_TCON0_FRM_CTL_MODE_G BIT(5) -+#define SUN4I_TCON0_FRM_CTL_MODE_B BIT(4) -+ -+#define SUN4I_TCON0_FRM_SEED_PR_REG 0x14 -+#define SUN4I_TCON0_FRM_SEED_PG_REG 0x18 -+#define SUN4I_TCON0_FRM_SEED_PB_REG 0x1c -+#define SUN4I_TCON0_FRM_SEED_LR_REG 0x20 -+#define SUN4I_TCON0_FRM_SEED_LG_REG 0x24 -+#define SUN4I_TCON0_FRM_SEED_LB_REG 0x28 -+#define SUN4I_TCON0_FRM_TBL0_REG 0x2c -+#define SUN4I_TCON0_FRM_TBL1_REG 0x30 -+#define SUN4I_TCON0_FRM_TBL2_REG 0x34 -+#define SUN4I_TCON0_FRM_TBL3_REG 0x38 - - #define SUN4I_TCON0_CTL_REG 0x40 - #define SUN4I_TCON0_CTL_TCON_ENABLE BIT(31) --- -2.17.1 - diff --git a/patch/kernel/sunxi-dev/0089-drm-sun4i-tcon-Add-dithering-support-for-RGB565-RGB6.patch b/patch/kernel/sunxi-dev/0089-drm-sun4i-tcon-Add-dithering-support-for-RGB565-RGB6.patch deleted file mode 100644 index bff716f43..000000000 --- a/patch/kernel/sunxi-dev/0089-drm-sun4i-tcon-Add-dithering-support-for-RGB565-RGB6.patch +++ /dev/null @@ -1,132 +0,0 @@ -From 559d035001097a7ce6018117866e8f573fb15211 Mon Sep 17 00:00:00 2001 -From: Jonathan Liu -Date: Fri, 7 Sep 2018 12:19:45 +0800 -Subject: [PATCH 089/146] drm/sun4i: tcon: Add dithering support for - RGB565/RGB666 LCD panels - -The hardware supports dithering on TCON channel 0 which is used for LCD -panels. - -Dithering is a method of approximating a color from a mixture of other -colors when the required color isn't available. It reduces color -banding artifacts that can be observed when displaying gradients -(e.g. grayscale gradients). This may occur when the image that needs -to be displayed is 24-bit but the LCD panel is a lower bit depth and -does not perform dithering on its own. - -Signed-off-by: Jonathan Liu -[wens@csie.org: check display_info.bpc first; handle LVDS and MIPI DSI] -Signed-off-by: Chen-Yu Tsai ---- - drivers/gpu/drm/sun4i/sun4i_tcon.c | 62 ++++++++++++++++++++++++++++++ - 1 file changed, 62 insertions(+) - -diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c -index 52e1150612ba..0d438f633b5d 100644 ---- a/drivers/gpu/drm/sun4i/sun4i_tcon.c -+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c -@@ -12,11 +12,13 @@ - - #include - #include -+#include - #include - #include - #include - #include - #include -+#include - - #include - -@@ -275,6 +277,57 @@ static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon, - SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); - } - -+static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon, -+ const struct drm_connector *connector) -+{ -+ u32 bus_format = 0; -+ u32 val = 0; -+ -+ /* XXX Would this ever happen? */ -+ if (!connector) -+ return; -+ -+ /* -+ * FIXME: Undocumented bits -+ * -+ * The whole dithering process and these parameters are not -+ * explained in the vendor documents or BSP kernel code. -+ */ -+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111); -+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111); -+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111); -+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111); -+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111); -+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111); -+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000); -+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111); -+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555); -+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL3_REG, 0x7f7f7777); -+ -+ /* Do dithering if panel only supports 6 bits per color */ -+ if (connector->display_info.bpc == 6) -+ val |= SUN4I_TCON0_FRM_CTL_EN; -+ -+ if (connector->display_info.num_bus_formats == 1) -+ bus_format = connector->display_info.bus_formats[0]; -+ -+ /* Check the connection format */ -+ switch (bus_format) { -+ case MEDIA_BUS_FMT_RGB565_1X16: -+ /* R and B components are only 5 bits deep */ -+ val |= SUN4I_TCON0_FRM_CTL_MODE_R; -+ val |= SUN4I_TCON0_FRM_CTL_MODE_B; -+ case MEDIA_BUS_FMT_RGB666_1X18: -+ case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: -+ /* Fall through: enable dithering */ -+ val |= SUN4I_TCON0_FRM_CTL_EN; -+ break; -+ } -+ -+ /* Write dithering settings */ -+ regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val); -+} -+ - static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon, - const struct drm_encoder *encoder, - const struct drm_display_mode *mode) -@@ -292,6 +345,9 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon, - - sun4i_tcon0_mode_set_common(tcon, mode); - -+ /* Set dithering if needed */ -+ sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); -+ - regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, - SUN4I_TCON0_CTL_IF_MASK, - SUN4I_TCON0_CTL_IF_8080); -@@ -357,6 +413,9 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon, - tcon->dclk_max_div = 7; - sun4i_tcon0_mode_set_common(tcon, mode); - -+ /* Set dithering if needed */ -+ sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); -+ - /* Adjust clock delay */ - clk_delay = sun4i_tcon_get_clk_delay(mode, 0); - regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, -@@ -430,6 +489,9 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, - tcon->dclk_max_div = 127; - sun4i_tcon0_mode_set_common(tcon, mode); - -+ /* Set dithering if needed */ -+ sun4i_tcon0_mode_set_dithering(tcon, tcon->panel->connector); -+ - /* Adjust clock delay */ - clk_delay = sun4i_tcon_get_clk_delay(mode, 0); - regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, --- -2.17.1 - diff --git a/patch/kernel/sunxi-dev/0090-drm-sun4i-tcon-prevent-tcon-panel-dereference-if-nul.patch b/patch/kernel/sunxi-dev/0090-drm-sun4i-tcon-prevent-tcon-panel-dereference-if-nul.patch deleted file mode 100644 index a35a7f57b..000000000 --- a/patch/kernel/sunxi-dev/0090-drm-sun4i-tcon-prevent-tcon-panel-dereference-if-nul.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 99b4088bcefec2a055c1d7caa1f135168405ccf1 Mon Sep 17 00:00:00 2001 -From: Giulio Benetti -Date: Tue, 2 Oct 2018 23:59:17 +0200 -Subject: [PATCH 090/146] drm/sun4i: tcon: prevent tcon->panel dereference if - null - -If using tcon with VGA, tcon->panel will be null(0), this will cause -segmentation fault when trying to dereference tcon->panel->connector. - -Add tcon->panel null check before calling -sun4i_tcon0_mode_set_dithering(). - -Signed-off-by: Giulio Benetti ---- - drivers/gpu/drm/sun4i/sun4i_tcon.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c -index 0d438f633b5d..1b28fd9c2908 100644 ---- a/drivers/gpu/drm/sun4i/sun4i_tcon.c -+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c -@@ -490,7 +490,8 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, - sun4i_tcon0_mode_set_common(tcon, mode); - - /* Set dithering if needed */ -- sun4i_tcon0_mode_set_dithering(tcon, tcon->panel->connector); -+ if (tcon->panel) -+ sun4i_tcon0_mode_set_dithering(tcon, tcon->panel->connector); - - /* Adjust clock delay */ - clk_delay = sun4i_tcon_get_clk_delay(mode, 0); --- -2.17.1 - diff --git a/patch/kernel/sunxi-dev/0091-clk-sunxi-ng-a64-Add-minimal-rate-for-video-PLLs.patch b/patch/kernel/sunxi-dev/0091-clk-sunxi-ng-a64-Add-minimal-rate-for-video-PLLs.patch deleted file mode 100644 index b55b2b501..000000000 --- a/patch/kernel/sunxi-dev/0091-clk-sunxi-ng-a64-Add-minimal-rate-for-video-PLLs.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 8a348934a01914c7e6ada897d7ba121209961032 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Tue, 4 Sep 2018 12:40:43 +0800 -Subject: [PATCH 091/146] clk: sunxi-ng: a64: Add minimal rate for video PLLs - -According to documentation and experience with other similar SoCs, video -PLLs don't work stable if their output frequency is set below 192 MHz. - -Because of that, set minimal rate to both A64 video PLLs to 192 MHz. - -Signed-off-by: Jagan Teki -Signed-off-by: Icenowy Zheng -Reviewed-by: Jernej Skrabec ---- - drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 46 ++++++++++++++------------- - 1 file changed, 24 insertions(+), 22 deletions(-) - -diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c -index 7c645f2c017a..40a7b5fd091c 100644 ---- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c -+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c -@@ -64,17 +64,18 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", - BIT(28), /* lock */ - CLK_SET_RATE_UNGATE); - --static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", -- "osc24M", 0x010, -- 8, 7, /* N */ -- 0, 4, /* M */ -- BIT(24), /* frac enable */ -- BIT(25), /* frac select */ -- 270000000, /* frac rate 0 */ -- 297000000, /* frac rate 1 */ -- BIT(31), /* gate */ -- BIT(28), /* lock */ -- CLK_SET_RATE_UNGATE); -+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0", -+ "osc24M", 0x010, -+ 192000000, /* Minimum rate */ -+ 8, 7, /* N */ -+ 0, 4, /* M */ -+ BIT(24), /* frac enable */ -+ BIT(25), /* frac select */ -+ 270000000, /* frac rate 0 */ -+ 297000000, /* frac rate 1 */ -+ BIT(31), /* gate */ -+ BIT(28), /* lock */ -+ CLK_SET_RATE_UNGATE); - - static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", - "osc24M", 0x018, -@@ -125,17 +126,18 @@ static struct ccu_nk pll_periph1_clk = { - }, - }; - --static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1", -- "osc24M", 0x030, -- 8, 7, /* N */ -- 0, 4, /* M */ -- BIT(24), /* frac enable */ -- BIT(25), /* frac select */ -- 270000000, /* frac rate 0 */ -- 297000000, /* frac rate 1 */ -- BIT(31), /* gate */ -- BIT(28), /* lock */ -- CLK_SET_RATE_UNGATE); -+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1", -+ "osc24M", 0x030, -+ 192000000, /* Minimum rate */ -+ 8, 7, /* N */ -+ 0, 4, /* M */ -+ BIT(24), /* frac enable */ -+ BIT(25), /* frac select */ -+ 270000000, /* frac rate 0 */ -+ 297000000, /* frac rate 1 */ -+ BIT(31), /* gate */ -+ BIT(28), /* lock */ -+ CLK_SET_RATE_UNGATE); - - static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", - "osc24M", 0x038, --- -2.17.1 - diff --git a/patch/kernel/sunxi-dev/0092-clk-sunxi-ng-a64-Add-max.-rate-constraint-to-video-P.patch b/patch/kernel/sunxi-dev/0092-clk-sunxi-ng-a64-Add-max.-rate-constraint-to-video-P.patch deleted file mode 100644 index c15f791b6..000000000 --- a/patch/kernel/sunxi-dev/0092-clk-sunxi-ng-a64-Add-max.-rate-constraint-to-video-P.patch +++ /dev/null @@ -1,90 +0,0 @@ -From 99ce6e04231a5a185c1cc7d8d2bd9484c8eabc56 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Tue, 4 Sep 2018 12:40:44 +0800 -Subject: [PATCH 092/146] clk: sunxi-ng: a64: Add max. rate constraint to video - PLLs - -Video PLLs on A64 can be set to higher rate that it is actually -supported by HW. - -Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP -clock driver. Interestengly, user manual specifies maximum frequency to -be 600 MHz. Historically, this data was wrong in some user manuals for -other SoCs, so more faith is put in BSP clock driver. - -Signed-off-by: Icenowy Zheng ---- - drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 50 ++++++++++++++------------- - 1 file changed, 26 insertions(+), 24 deletions(-) - -diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c -index 40a7b5fd091c..90ffee824c33 100644 ---- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c -+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c -@@ -64,18 +64,19 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", - BIT(28), /* lock */ - CLK_SET_RATE_UNGATE); - --static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0", -- "osc24M", 0x010, -- 192000000, /* Minimum rate */ -- 8, 7, /* N */ -- 0, 4, /* M */ -- BIT(24), /* frac enable */ -- BIT(25), /* frac select */ -- 270000000, /* frac rate 0 */ -- 297000000, /* frac rate 1 */ -- BIT(31), /* gate */ -- BIT(28), /* lock */ -- CLK_SET_RATE_UNGATE); -+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0", -+ "osc24M", 0x010, -+ 192000000, /* Minimum rate */ -+ 1008000000, /* Maximum rate */ -+ 8, 7, /* N */ -+ 0, 4, /* M */ -+ BIT(24), /* frac enable */ -+ BIT(25), /* frac select */ -+ 270000000, /* frac rate 0 */ -+ 297000000, /* frac rate 1 */ -+ BIT(31), /* gate */ -+ BIT(28), /* lock */ -+ CLK_SET_RATE_UNGATE); - - static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", - "osc24M", 0x018, -@@ -126,18 +127,19 @@ static struct ccu_nk pll_periph1_clk = { - }, - }; - --static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1", -- "osc24M", 0x030, -- 192000000, /* Minimum rate */ -- 8, 7, /* N */ -- 0, 4, /* M */ -- BIT(24), /* frac enable */ -- BIT(25), /* frac select */ -- 270000000, /* frac rate 0 */ -- 297000000, /* frac rate 1 */ -- BIT(31), /* gate */ -- BIT(28), /* lock */ -- CLK_SET_RATE_UNGATE); -+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1", -+ "osc24M", 0x030, -+ 192000000, /* Minimum rate */ -+ 1008000000, /* Maximum rate */ -+ 8, 7, /* N */ -+ 0, 4, /* M */ -+ BIT(24), /* frac enable */ -+ BIT(25), /* frac select */ -+ 270000000, /* frac rate 0 */ -+ 297000000, /* frac rate 1 */ -+ BIT(31), /* gate */ -+ BIT(28), /* lock */ -+ CLK_SET_RATE_UNGATE); - - static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", - "osc24M", 0x038, --- -2.17.1 - diff --git a/patch/kernel/sunxi-dev/0093-dt-bindings-display-Add-compatible-for-A64-DE2-displ.patch b/patch/kernel/sunxi-dev/0093-dt-bindings-display-Add-compatible-for-A64-DE2-displ.patch deleted file mode 100644 index 5f607c3f5..000000000 --- a/patch/kernel/sunxi-dev/0093-dt-bindings-display-Add-compatible-for-A64-DE2-displ.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 3c133c6aa20eacb1b7f77e6b3136d483fdd80582 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Tue, 4 Sep 2018 12:40:45 +0800 -Subject: [PATCH 093/146] dt-bindings: display: Add compatible for A64 DE2 - display pipeline - -Allwinner A64 has a DE2 display pipeline. The TCONs are similar to the -ones in A83T, but the mixers are new (similar to the later R40 SoC). - -This patch adds dt-binding documentation for A64 DE2 display pipeline. - -Signed-off-by: Jagan Teki -Reviewed-by: Rob Herring -[Icenowy: Refactor and also cover TCON1] -Signed-off-by: Icenowy Zheng ---- - .../devicetree/bindings/display/sunxi/sun4i-drm.txt | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt -index f8773ecb7525..7b79c5e3dffc 100644 ---- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt -+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt -@@ -151,6 +151,8 @@ Required properties: - * allwinner,sun8i-v3s-tcon - * allwinner,sun9i-a80-tcon-lcd - * allwinner,sun9i-a80-tcon-tv -+ * "allwinner,sun50i-a64-tcon-lcd", "allwinner,sun8i-a83t-tcon-lcd" -+ * "allwinner,sun50i-a64-tcon-tv", "allwinner,sun8i-a83t-tcon-tv" - - reg: base address and size of memory-mapped region - - interrupts: interrupt associated to this IP - - clocks: phandles to the clocks feeding the TCON. -@@ -370,6 +372,8 @@ Required properties: - * allwinner,sun8i-a83t-de2-mixer-1 - * allwinner,sun8i-h3-de2-mixer-0 - * allwinner,sun8i-v3s-de2-mixer -+ * allwinner,sun50i-a64-de2-mixer-0 -+ * allwinner,sun50i-a64-de2-mixer-1 - - reg: base address and size of the memory-mapped region. - - clocks: phandles to the clocks feeding the mixer - * bus: the mixer interface clock -@@ -403,6 +407,7 @@ Required properties: - * allwinner,sun8i-r40-display-engine - * allwinner,sun8i-v3s-display-engine - * allwinner,sun9i-a80-display-engine -+ * allwinner,sun50i-a64-display-engine - - - allwinner,pipelines: list of phandle to the display engine - frontends (DE 1.0) or mixers (DE 2.0) available. --- -2.17.1 - diff --git a/patch/kernel/sunxi-dev/0094-drm-sun4i-Add-support-for-A64-mixers.patch b/patch/kernel/sunxi-dev/0094-drm-sun4i-Add-support-for-A64-mixers.patch deleted file mode 100644 index b13df124c..000000000 --- a/patch/kernel/sunxi-dev/0094-drm-sun4i-Add-support-for-A64-mixers.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 06cbcf31db7e0f3604f248e1731a0f316837cd64 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Tue, 4 Sep 2018 12:40:46 +0800 -Subject: [PATCH 094/146] drm/sun4i: Add support for A64 mixers - -Mixers in Allwinner have similar capabilities as others SoCs with DE2. - -Add support for them. - -Signed-off-by: Jagan Teki -[Icenowy: Add mixer1] -Signed-off-by: Icenowy Zheng -Reviewed-by: Jernej Skrabec ---- - drivers/gpu/drm/sun4i/sun8i_mixer.c | 24 ++++++++++++++++++++++++ - 1 file changed, 24 insertions(+) - -diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c -index cb65b0ed53fd..091f6cf40353 100644 ---- a/drivers/gpu/drm/sun4i/sun8i_mixer.c -+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c -@@ -553,6 +553,22 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = { - .mod_rate = 150000000, - }; - -+static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = { -+ .ccsc = 0, -+ .mod_rate = 297000000, -+ .scaler_mask = 0xf, -+ .ui_num = 3, -+ .vi_num = 1, -+}; -+ -+static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = { -+ .ccsc = 1, -+ .mod_rate = 297000000, -+ .scaler_mask = 0x3, -+ .ui_num = 1, -+ .vi_num = 1, -+}; -+ - static const struct of_device_id sun8i_mixer_of_table[] = { - { - .compatible = "allwinner,sun8i-a83t-de2-mixer-0", -@@ -570,6 +586,14 @@ static const struct of_device_id sun8i_mixer_of_table[] = { - .compatible = "allwinner,sun8i-v3s-de2-mixer", - .data = &sun8i_v3s_mixer_cfg, - }, -+ { -+ .compatible = "allwinner,sun50i-a64-de2-mixer-0", -+ .data = &sun50i_a64_mixer0_cfg, -+ }, -+ { -+ .compatible = "allwinner,sun50i-a64-de2-mixer-1", -+ .data = &sun50i_a64_mixer1_cfg, -+ }, - { } - }; - MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table); --- -2.17.1 - diff --git a/patch/kernel/sunxi-dev/0095-drm-sun4i-Add-support-for-A64-display-engine.patch b/patch/kernel/sunxi-dev/0095-drm-sun4i-Add-support-for-A64-display-engine.patch deleted file mode 100644 index 99e0b6238..000000000 --- a/patch/kernel/sunxi-dev/0095-drm-sun4i-Add-support-for-A64-display-engine.patch +++ /dev/null @@ -1,33 +0,0 @@ -From dd3d2cbe3b5312585fd0c525d0515ef0493192fa Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Tue, 4 Sep 2018 12:40:47 +0800 -Subject: [PATCH 095/146] drm/sun4i: Add support for A64 display engine - -Display Engine(DE2) in Allwinner A64 has two mixers and tcons. - -The routing for mixer0 is through tcon0 and connected to -LVDS/RGB/MIPI-DSI controller. - -The routing for mixer1 is through tcon1 and connected to HDMI. - -Signed-off-by: Jagan Teki -Signed-off-by: Icenowy Zheng ---- - drivers/gpu/drm/sun4i/sun4i_drv.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c -index 9f5de14fb2fe..486ae8507ae9 100644 ---- a/drivers/gpu/drm/sun4i/sun4i_drv.c -+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c -@@ -447,6 +447,7 @@ static const struct of_device_id sun4i_drv_of_table[] = { - { .compatible = "allwinner,sun8i-h3-display-engine" }, - { .compatible = "allwinner,sun8i-v3s-display-engine" }, - { .compatible = "allwinner,sun9i-a80-display-engine" }, -+ { .compatible = "allwinner,sun50i-a64-display-engine" }, - { } - }; - MODULE_DEVICE_TABLE(of, sun4i_drv_of_table); --- -2.17.1 - diff --git a/patch/kernel/sunxi-dev/0099-dt-bindings-sun4i-drm-add-HDMI-VCC-supply-property-f.patch b/patch/kernel/sunxi-dev/0099-dt-bindings-sun4i-drm-add-HDMI-VCC-supply-property-f.patch deleted file mode 100644 index a8e0639fd..000000000 --- a/patch/kernel/sunxi-dev/0099-dt-bindings-sun4i-drm-add-HDMI-VCC-supply-property-f.patch +++ /dev/null @@ -1,33 +0,0 @@ -From d2deb88ff41a528b4c35f1f6e344e6a097eabedd Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Tue, 4 Sep 2018 12:40:51 +0800 -Subject: [PATCH 099/146] dt-bindings: sun4i-drm: add HDMI VCC supply property - for sun8i-dw-hdmi - -Allwiner SoCs with DesignWare HDMI controller all come with a "HVCC" -pin, which is the VCC of HDMI part. - -Add a supply property to specify HVCC's regulator in the device tree. - -Signed-off-by: Icenowy Zheng ---- - Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt -index fdb8fb29033f..0bbb5d47f228 100644 ---- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt -+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt -@@ -97,6 +97,9 @@ Required properties: - first port should be the input endpoint. The second should be the - output, usually to an HDMI connector. - -+Optional properties: -+ - hvcc-supply: the VCC power supply of the controller -+ - DWC HDMI PHY - ------------ - --- -2.17.1 -