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Update u-boot DE2 HDMI patch
This commit is contained in:
zador-blood-stained
parent
24f611f133
commit
6926b4c204
1 changed files with 239 additions and 128 deletions
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@ -1,4 +1,4 @@
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commit 1c37c497a44fc5e3fe60319c88afc738b1fab3d7
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commit 6b19f528f7650c659806f0b100e155337d3b37b3
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Author: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Tue Nov 8 01:04:32 2016 +0100
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@ -7,14 +7,14 @@ Date: Tue Nov 8 01:04:32 2016 +0100
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
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index be9fcfd..a414f69 100644
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index be9fcfd..02d4a8c 100644
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--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
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+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
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@@ -67,12 +67,20 @@ struct sunxi_ccm_reg {
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u32 dram_pll_cfg; /* 0xf8 PLL_DDR cfg register, A33 only */
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u32 mbus_reset; /* 0xfc MBUS reset control, A33 only */
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u32 dram_clk_gate; /* 0x100 DRAM module gating */
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+#ifdef CONFIG_MACH_SUN8I
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+#ifdef CONFIG_SUNXI_DE2
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+ u32 de_clk_cfg; /* 0x104 DE module clock */
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+#else
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u32 be0_clk_cfg; /* 0x104 BE0 module clock */
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@ -23,7 +23,7 @@ index be9fcfd..a414f69 100644
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u32 fe0_clk_cfg; /* 0x10c FE0 module clock */
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u32 fe1_clk_cfg; /* 0x110 FE1 module clock */
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u32 mp_clk_cfg; /* 0x114 MP module clock */
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+#ifdef CONFIG_MACH_SUN8I
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+#ifdef CONFIG_SUNXI_DE2
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+ u32 tcon0_clk_cfg; /* 0x118 TCON0 module clock */
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+#else
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u32 lcd0_ch0_clk_cfg; /* 0x118 LCD0 CH0 module clock */
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@ -35,7 +35,7 @@ index be9fcfd..a414f69 100644
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u32 dmic_clk_cfg; /* 0x148 Digital Mic module clock*/
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u32 reserved15;
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u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */
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+#ifdef CONFIG_MACH_SUN8I
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+#ifdef CONFIG_SUNXI_DE2
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+ u32 hdmi_slow_clk_cfg; /* 0x154 HDMI slow module clock */
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+#else
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u32 ps_clk_cfg; /* 0x154 PS module clock */
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@ -117,7 +117,7 @@ index be9fcfd..a414f69 100644
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/* CCM bits common to all Display Engine (and IEP) clock ctrl regs */
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#define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
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+#ifndef CONFIG_MACH_SUN8I
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+#ifndef CONFIG_SUNXI_DE2
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#define CCM_DE_CTRL_PLL_MASK (0xf << 24)
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#define CCM_DE_CTRL_PLL3 (0 << 24)
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#define CCM_DE_CTRL_PLL7 (1 << 24)
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@ -144,24 +144,33 @@ index be9fcfd..a414f69 100644
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void clock_set_mipi_pll(unsigned int hz);
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unsigned int clock_get_pll3(void);
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diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
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index 5f93830..9758a14 100644
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index 5f93830..2cbc630 100644
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--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
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+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
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@@ -46,7 +46,9 @@
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@@ -18,6 +18,8 @@
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#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
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#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
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+#define SUNXI_DE2_BASE 0x01000000
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+
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#ifdef CONFIG_MACH_SUN8I_A83T
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#define SUNXI_CPUCFG_BASE 0x01700000
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#endif
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@@ -46,7 +48,9 @@
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#define SUNXI_USB1_BASE 0x01c14000
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#endif
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#define SUNXI_SS_BASE 0x01c15000
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+#ifndef CONFIG_MACH_SUN8I_H3
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+#ifndef CONFIG_SUNXI_DE2
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#define SUNXI_HDMI_BASE 0x01c16000
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+#endif
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#define SUNXI_SPI2_BASE 0x01c17000
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#define SUNXI_SATA_BASE 0x01c18000
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#ifdef CONFIG_SUNXI_GEN_SUN4I
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@@ -163,6 +165,10 @@ defined(CONFIG_MACH_SUN50I)
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@@ -163,6 +167,10 @@ defined(CONFIG_MACH_SUN50I)
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#define SUNXI_MP_BASE 0x01e80000
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#define SUNXI_AVG_BASE 0x01ea0000
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+#ifdef CONFIG_MACH_SUN8I_H3
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+#ifdef CONFIG_SUNXI_DE2
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+#define SUNXI_HDMI_BASE 0x01ee0000
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+#endif
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+
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@ -170,10 +179,10 @@ index 5f93830..9758a14 100644
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diff --git a/arch/arm/include/asm/arch-sunxi/display2.h b/arch/arm/include/asm/arch-sunxi/display2.h
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new file mode 100644
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index 0000000..e55e35a
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index 0000000..04790a8
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--- /dev/null
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+++ b/arch/arm/include/asm/arch-sunxi/display2.h
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@@ -0,0 +1,285 @@
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@@ -0,0 +1,282 @@
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+/*
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+ * Sunxi platform display controller register and constant defines
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+ *
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@ -232,7 +241,17 @@ index 0000000..e55e35a
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+ u32 tcon1_io_polarity; /* 0xf0 */
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+ u32 tcon1_io_tristate; /* 0xf4 */
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+ u8 res4[0x108]; /* 0xf8 */
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+ u32 mux_ctrl; /* 0x200 */};
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+ u32 mux_ctrl; /* 0x200 */
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+};
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+
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+/* internal clock settings */
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+struct de_clk {
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+ u32 gate_cfg;
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+ u32 bus_cfg;
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+ u32 rst_cfg;
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+ u32 div_cfg;
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+ u32 sel_cfg;
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+};
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+
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+/* global control */
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+struct de_glb {
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@ -273,22 +292,15 @@ index 0000000..e55e35a
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+struct de_vi {
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+ struct {
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+ u32 attr;
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+#define VI_CFG_ATTR_en BIT(0)
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+#define VI_CFG_ATTR_fcolor_en BIT(4)
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+#define VI_CFG_ATTR_fmt_SHIFT 8
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+#define VI_CFG_ATTR_fmt_MASK GENMASK(12, 8)
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+#define VI_CFG_ATTR_ui_sel BIT(15)
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+#define VI_CFG_ATTR_top_down BIT(23)
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+ u32 size;
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+ u32 coord;
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+#define VI_N_PLANES 3
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+ u32 pitch[VI_N_PLANES];
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+ u32 top_laddr[VI_N_PLANES];
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+ u32 bot_laddr[VI_N_PLANES];
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+ u32 pitch[3];
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+ u32 top_laddr[3];
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+ u32 bot_laddr[3];
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+ } cfg[4];
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+ u32 fcolor[4]; /* c0 */
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+ u32 top_haddr[VI_N_PLANES]; /* d0 */
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+ u32 bot_haddr[VI_N_PLANES]; /* dc */
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+ u32 top_haddr[3]; /* d0 */
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+ u32 bot_haddr[3]; /* dc */
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+ u32 ovl_size[2]; /* e8 */
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+ u32 hori[2]; /* f0 */
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+ u32 vert[2]; /* f8 */
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@ -303,7 +315,6 @@ index 0000000..e55e35a
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+#define UI_CFG_ATTR_fcolor_en BIT(4)
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+#define UI_CFG_ATTR_fmt_SHIFT 8
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+#define UI_CFG_ATTR_fmt_MASK GENMASK(12, 8)
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+#define UI_CFG_ATTR_top_down BIT(23)
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+#define UI_CFG_ATTR_alpha_SHIFT 24
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+#define UI_CFG_ATTR_alpha_MASK GENMASK(31, 24)
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+ u32 size;
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@ -339,38 +350,9 @@ index 0000000..e55e35a
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+#define SUNXI_HDMI_PHY_BASE (u32*)(SUNXI_HDMI_BASE + 0x10000)
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+
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+/* Naming is taken from Linux, drivers/gpu/drm/bridge/dw-hdmi.h */
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+#define SUNXI_HDMI_IH_I2CM_STAT0 (u8*)(SUNXI_HDMI_BASE + 0x0013)
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+#define SUNXI_HDMI_IH_MUTE (u8*)(SUNXI_HDMI_BASE + 0xF01F)
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+#define SUNXI_HDMI_I2CM_CTLINT (u8*)(SUNXI_HDMI_BASE + 0x8EE2)
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+#define SUNXI_HDMI_MC_CLKDIS (u8*)(SUNXI_HDMI_BASE + 0x0081)
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+
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+#define SUNXI_HDMI_MC_SWRSTZ (u8*)(SUNXI_HDMI_BASE + 0x8080)
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+#define SUNXI_HDMI_FC_INVIDCONF (u8*)(SUNXI_HDMI_BASE + 0x0040)
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+#define SUNXI_HDMI_FC_AVICONF0 (u8*)(SUNXI_HDMI_BASE + 0x4045)
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+#define SUNXI_HDMI_FC_AVICONF1 (u8*)(SUNXI_HDMI_BASE + 0xC044)
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+#define SUNXI_HDMI_FC_AVICONF2 (u8*)(SUNXI_HDMI_BASE + 0xC045)
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+#define SUNXI_HDMI_FC_INHACTV1 (u8*)(SUNXI_HDMI_BASE + 0x8040)
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+#define SUNXI_HDMI_FC_INHACTV0 (u8*)(SUNXI_HDMI_BASE + 0x0041)
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+#define SUNXI_HDMI_FC_INVACTV1 (u8*)(SUNXI_HDMI_BASE + 0x8042)
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+#define SUNXI_HDMI_FC_INVACTV0 (u8*)(SUNXI_HDMI_BASE + 0x0043)
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+#define SUNXI_HDMI_FC_VSYNCINWIDTH (u8*)(SUNXI_HDMI_BASE + 0x4043)
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+#define SUNXI_HDMI_FC_INHBLANK1 (u8*)(SUNXI_HDMI_BASE + 0x0042)
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+#define SUNXI_HDMI_FC_INHBLANK0 (u8*)(SUNXI_HDMI_BASE + 0x8041)
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+#define SUNXI_HDMI_FC_VSYNCINDELAY (u8*)(SUNXI_HDMI_BASE + 0x4042)
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+#define SUNXI_HDMI_FC_HSYNCINDELAY1 (u8*)(SUNXI_HDMI_BASE + 0x4041)
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+#define SUNXI_HDMI_FC_HSYNCINDELAY0 (u8*)(SUNXI_HDMI_BASE + 0x4040)
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+#define SUNXI_HDMI_FC_HSYNCINWIDTH1 (u8*)(SUNXI_HDMI_BASE + 0xC041)
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+#define SUNXI_HDMI_FC_HSYNCINWIDTH0 (u8*)(SUNXI_HDMI_BASE + 0xC040)
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+#define SUNXI_HDMI_FC_INVBLANK (u8*)(SUNXI_HDMI_BASE + 0x8043)
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+#define SUNXI_HDMI_FC_CTRLDUR (u8*)(SUNXI_HDMI_BASE + 0x0045)
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+#define SUNXI_HDMI_FC_EXCTRLDUR (u8*)(SUNXI_HDMI_BASE + 0x8044)
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+#define SUNXI_HDMI_FC_EXCTRLSPAC (u8*)(SUNXI_HDMI_BASE + 0x8045)
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+#define SUNXI_HDMI_FC_CH0PREAM (u8*)(SUNXI_HDMI_BASE + 0x0046)
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+#define SUNXI_HDMI_FC_CH1PREAM (u8*)(SUNXI_HDMI_BASE + 0x0047)
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+#define SUNXI_HDMI_FC_CH2PREAM (u8*)(SUNXI_HDMI_BASE + 0x8046)
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+#define SUNXI_HDMI_VP_PR_CD (u8*)(SUNXI_HDMI_BASE + 0x0401)
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+#define SUNXI_HDMI_VP_STUFF (u8*)(SUNXI_HDMI_BASE + 0x8400)
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+#define SUNXI_HDMI_VP_REMAP (u8*)(SUNXI_HDMI_BASE + 0x8401)
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+#define SUNXI_HDMI_VP_CONF (u8*)(SUNXI_HDMI_BASE + 0x0402)
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+#define SUNXI_HDMI_TX_INVID0 (u8*)(SUNXI_HDMI_BASE + 0x0800)
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+#define SUNXI_HDMI_TX_INSTUFFING (u8*)(SUNXI_HDMI_BASE + 0x0801)
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+#define SUNXI_HDMI_TX_GYDATA0 (u8*)(SUNXI_HDMI_BASE + 0x8800)
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@ -379,14 +361,46 @@ index 0000000..e55e35a
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+#define SUNXI_HDMI_TX_RCRDATA1 (u8*)(SUNXI_HDMI_BASE + 0x0803)
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+#define SUNXI_HDMI_TX_BCBDATA0 (u8*)(SUNXI_HDMI_BASE + 0x8802)
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+#define SUNXI_HDMI_TX_BCBDATA1 (u8*)(SUNXI_HDMI_BASE + 0x8803)
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+
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+#define SUNXI_HDMI_VP_PR_CD (u8*)(SUNXI_HDMI_BASE + 0x0401)
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+#define SUNXI_HDMI_VP_STUFF (u8*)(SUNXI_HDMI_BASE + 0x8400)
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+#define SUNXI_HDMI_VP_REMAP (u8*)(SUNXI_HDMI_BASE + 0x8401)
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+#define SUNXI_HDMI_VP_CONF (u8*)(SUNXI_HDMI_BASE + 0x0402)
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+
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+#define SUNXI_HDMI_FC_INVIDCONF (u8*)(SUNXI_HDMI_BASE + 0x0040)
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+#define SUNXI_HDMI_FC_INHACTV0 (u8*)(SUNXI_HDMI_BASE + 0x0041)
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+#define SUNXI_HDMI_FC_INHACTV1 (u8*)(SUNXI_HDMI_BASE + 0x8040)
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+#define SUNXI_HDMI_FC_INHBLANK0 (u8*)(SUNXI_HDMI_BASE + 0x8041)
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+#define SUNXI_HDMI_FC_INHBLANK1 (u8*)(SUNXI_HDMI_BASE + 0x0042)
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+#define SUNXI_HDMI_FC_INVACTV0 (u8*)(SUNXI_HDMI_BASE + 0x0043)
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+#define SUNXI_HDMI_FC_INVACTV1 (u8*)(SUNXI_HDMI_BASE + 0x8042)
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+#define SUNXI_HDMI_FC_INVBLANK (u8*)(SUNXI_HDMI_BASE + 0x8043)
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+#define SUNXI_HDMI_FC_HSYNCINDELAY0 (u8*)(SUNXI_HDMI_BASE + 0x4040)
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+#define SUNXI_HDMI_FC_HSYNCINDELAY1 (u8*)(SUNXI_HDMI_BASE + 0x4041)
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+#define SUNXI_HDMI_FC_HSYNCINWIDTH0 (u8*)(SUNXI_HDMI_BASE + 0xC040)
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+#define SUNXI_HDMI_FC_HSYNCINWIDTH1 (u8*)(SUNXI_HDMI_BASE + 0xC041)
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+#define SUNXI_HDMI_FC_VSYNCINDELAY (u8*)(SUNXI_HDMI_BASE + 0x4042)
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+#define SUNXI_HDMI_FC_VSYNCINWIDTH (u8*)(SUNXI_HDMI_BASE + 0x4043)
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+#define SUNXI_HDMI_FC_CTRLDUR (u8*)(SUNXI_HDMI_BASE + 0x0045)
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+#define SUNXI_HDMI_FC_EXCTRLDUR (u8*)(SUNXI_HDMI_BASE + 0x8044)
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+#define SUNXI_HDMI_FC_EXCTRLSPAC (u8*)(SUNXI_HDMI_BASE + 0x8045)
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+#define SUNXI_HDMI_FC_CH0PREAM (u8*)(SUNXI_HDMI_BASE + 0x0046)
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+#define SUNXI_HDMI_FC_CH1PREAM (u8*)(SUNXI_HDMI_BASE + 0x0047)
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+#define SUNXI_HDMI_FC_CH2PREAM (u8*)(SUNXI_HDMI_BASE + 0x8046)
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+#define SUNXI_HDMI_FC_AVICONF0 (u8*)(SUNXI_HDMI_BASE + 0x4045)
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+#define SUNXI_HDMI_FC_AVICONF1 (u8*)(SUNXI_HDMI_BASE + 0xC044)
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+#define SUNXI_HDMI_FC_AVICONF2 (u8*)(SUNXI_HDMI_BASE + 0xC045)
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+
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+#define SUNXI_HDMI_MC_CLKDIS (u8*)(SUNXI_HDMI_BASE + 0x0081)
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+#define SUNXI_HDMI_MC_SWRSTZ (u8*)(SUNXI_HDMI_BASE + 0x8080)
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+#define SUNXI_HDMI_MC_FLOWCTRL (u8*)(SUNXI_HDMI_BASE + 0x0082)
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+
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+#define SUNXI_HDMI_IH_I2CM_STAT0 (u8*)(SUNXI_HDMI_BASE + 0x0013)
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+#define SUNXI_HDMI_I2CM_SLAVE (u8*)(SUNXI_HDMI_BASE + 0x0EE0)
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+#define SUNXI_HDMI_I2CM_ADDRESS (u8*)(SUNXI_HDMI_BASE + 0x0EE1)
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+#define SUNXI_HDMI_I2CM_DATAI (u8*)(SUNXI_HDMI_BASE + 0x8EE1)
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+#define SUNXI_HDMI_I2CM_OPERATION (u8*)(SUNXI_HDMI_BASE + 0x0EE2)
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+#define SUNXI_HDMI_I2CM_INT (u8*)(SUNXI_HDMI_BASE + 0x0EE3)
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+#define SUNXI_HDMI_I2CM_CTLINT (u8*)(SUNXI_HDMI_BASE + 0x8EE2)
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+#define SUNXI_HDMI_I2CM_DIV (u8*)(SUNXI_HDMI_BASE + 0x8EE3)
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+#define SUNXI_HDMI_I2CM_SEGADDR (u8*)(SUNXI_HDMI_BASE + 0x4EE0)
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+#define SUNXI_HDMI_I2CM_SOFTRSTZ (u8*)(SUNXI_HDMI_BASE + 0x4EE1)
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@ -397,37 +411,29 @@ index 0000000..e55e35a
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+/*
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+ * DE register constants.
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+ */
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+/* TODO: move to appropriate place */
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+#define SUN8I_DE_BASE 0x01000000
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+#define SUN8I_DE_GATE_REG (u32*)(SUN8I_DE_BASE + 0x0004)
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+#define SUN8I_DE_MOD_REG (u32*)(SUN8I_DE_BASE + 0x0000)
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+#define SUN8I_DE_RESET_REG (u32*)(SUN8I_DE_BASE + 0x0008)
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+#define SUN8I_DE_DIV_REG (u32*)(SUN8I_DE_BASE + 0x000c)
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+#define SUN8I_DE_SEL_REG (u32*)(SUN8I_DE_BASE + 0x0010)
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+
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+#define DE_MUX0_BASE (u8*)(SUN8I_DE_BASE + 0x00100000)
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+#define SUNXI_DE2_MUX0_BASE (u8*)(SUNXI_DE2_BASE + 0x00100000)
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+/* MUX registers (addr / MUX base) */
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+#define DE_MUX_GLB_REGS 0x00000 /* global control */
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+#define DE_MUX_BLD_REGS 0x01000 /* alpha blending */
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+#define DE_MUX_CHAN_REGS 0x02000 /* VI/UI overlay channels */
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+#define DE_MUX_CHAN_SZ 0x1000 /* size of a channel */
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+#define DE_MUX_VSU_REGS 0x20000 /* VSU */
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+#define DE_MUX_GSU1_REGS 0x30000 /* GSUs */
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+#define DE_MUX_GSU2_REGS 0x40000
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+#define DE_MUX_GSU3_REGS 0x50000
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+#define DE_MUX_FCE_REGS 0xa0000 /* FCE */
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+#define DE_MUX_BWS_REGS 0xa2000 /* BWS */
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+#define DE_MUX_LTI_REGS 0xa4000 /* LTI */
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+#define DE_MUX_PEAK_REGS 0xa6000 /* PEAK */
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+#define DE_MUX_ASE_REGS 0xa8000 /* ASE */
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+#define DE_MUX_FCC_REGS 0xaa000 /* FCC */
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+#define DE_MUX_DCSC_REGS 0xb0000 /* DCSC/SMBL */
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+#define SUNXI_DE2_MUX_GLB_REGS 0x00000
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+#define SUNXI_DE2_MUX_BLD_REGS 0x01000
|
||||
+#define SUNXI_DE2_MUX_CHAN_REGS 0x02000
|
||||
+#define SUNXI_DE2_MUX_CHAN_SZ 0x1000
|
||||
+#define SUNXI_DE2_MUX_VSU_REGS 0x20000
|
||||
+#define SUNXI_DE2_MUX_GSU1_REGS 0x30000
|
||||
+#define SUNXI_DE2_MUX_GSU2_REGS 0x40000
|
||||
+#define SUNXI_DE2_MUX_GSU3_REGS 0x50000
|
||||
+#define SUNXI_DE2_MUX_FCE_REGS 0xa0000
|
||||
+#define SUNXI_DE2_MUX_BWS_REGS 0xa2000
|
||||
+#define SUNXI_DE2_MUX_LTI_REGS 0xa4000
|
||||
+#define SUNXI_DE2_MUX_PEAK_REGS 0xa6000
|
||||
+#define SUNXI_DE2_MUX_ASE_REGS 0xa8000
|
||||
+#define SUNXI_DE2_MUX_FCC_REGS 0xaa000
|
||||
+#define SUNXI_DE2_MUX_DCSC_REGS 0xb0000
|
||||
+
|
||||
+#define DE2_FORMAT_ARGB_8888 0
|
||||
+#define DE2_FORMAT_BGRA_8888 3
|
||||
+#define DE2_FORMAT_XRGB_8888 4
|
||||
+#define DE2_FORMAT_RGB_888 8
|
||||
+#define DE2_FORMAT_BGR_888 9
|
||||
+#define SUNXI_DE2_FORMAT_ARGB_8888 0
|
||||
+#define SUNXI_DE2_FORMAT_BGRA_8888 3
|
||||
+#define SUNXI_DE2_FORMAT_XRGB_8888 4
|
||||
+#define SUNXI_DE2_FORMAT_RGB_888 8
|
||||
+#define SUNXI_DE2_FORMAT_BGR_888 9
|
||||
+
|
||||
+/* coordinates and sizes */
|
||||
+#define XY(x, y) (((y) << 16) | (x))
|
||||
|
|
@ -460,7 +466,7 @@ index 0000000..e55e35a
|
|||
+
|
||||
+#endif /* _SUNXI_DISPLAY_H */
|
||||
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
|
||||
index ed8cd9b..bcf9aa1 100644
|
||||
index ed8cd9b..3a81e9d 100644
|
||||
--- a/arch/arm/mach-sunxi/clock_sun6i.c
|
||||
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
|
||||
@@ -141,6 +141,17 @@ void clock_set_pll3(unsigned int clk)
|
||||
|
|
@ -509,7 +515,7 @@ index ed8cd9b..bcf9aa1 100644
|
|||
return ((src / 1000) * n * k / m) * 1000;
|
||||
}
|
||||
|
||||
+#ifndef CONFIG_MACH_SUN8I
|
||||
+#ifndef CONFIG_SUNXI_DE2
|
||||
void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
|
||||
{
|
||||
int pll = clock_get_pll6() * 2;
|
||||
|
|
@ -519,7 +525,7 @@ index ed8cd9b..bcf9aa1 100644
|
|||
}
|
||||
+#endif
|
||||
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
|
||||
index c0ffeb3..77fdc8f 100644
|
||||
index c0ffeb3..4fed7e3 100644
|
||||
--- a/board/sunxi/Kconfig
|
||||
+++ b/board/sunxi/Kconfig
|
||||
@@ -458,7 +458,7 @@ config AXP_GPIO
|
||||
|
|
@ -536,7 +542,7 @@ index c0ffeb3..77fdc8f 100644
|
|||
config VIDEO_HDMI
|
||||
bool "HDMI output support"
|
||||
- depends on VIDEO && !MACH_SUN8I
|
||||
+ depends on VIDEO
|
||||
+ depends on VIDEO && !MACH_SUN8I_A23 && !MACH_SUN8I_A33
|
||||
default y
|
||||
---help---
|
||||
Say Y here to add support for outputting video over HDMI.
|
||||
|
|
@ -617,10 +623,10 @@ index db34904..3097b82 100644
|
|||
obj-$(CONFIG_VIDEO_VESA) += vesa.o
|
||||
diff --git a/drivers/video/sunxi_display2.c b/drivers/video/sunxi_display2.c
|
||||
new file mode 100644
|
||||
index 0000000..123017f
|
||||
index 0000000..bbe8e2b
|
||||
--- /dev/null
|
||||
+++ b/drivers/video/sunxi_display2.c
|
||||
@@ -0,0 +1,915 @@
|
||||
@@ -0,0 +1,982 @@
|
||||
+/*
|
||||
+ * Display driver for sunxi Allwinner SoCs with DE2.
|
||||
+ *
|
||||
|
|
@ -648,6 +654,7 @@ index 0000000..123017f
|
|||
+#include <asm/global_data.h>
|
||||
+#include <asm/io.h>
|
||||
+#include <errno.h>
|
||||
+#include <fdt_support.h>
|
||||
+#include <video_fb.h>
|
||||
+#include "videomodes.h"
|
||||
+
|
||||
|
|
@ -721,9 +728,12 @@ index 0000000..123017f
|
|||
+ writel(0x80639000, &phy->unk1);
|
||||
+ writel(0x0F81C405, &phy->unk2);
|
||||
+
|
||||
+ /* enable read access to HDMI controller*/
|
||||
+ /* enable read access to HDMI controller */
|
||||
+ writel(0x54524545, &phy->read_en);
|
||||
+}
|
||||
+
|
||||
+static void sunxi_hdmi_ctrl_init(void)
|
||||
+{
|
||||
+ /* soft reset HDMI controller */
|
||||
+ writeb(0x00, SUNXI_HDMI_MC_SWRSTZ);
|
||||
+ udelay(1);
|
||||
|
|
@ -758,6 +768,7 @@ index 0000000..123017f
|
|||
+ setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
|
||||
+
|
||||
+ sunxi_hdmi_phy_init();
|
||||
+ sunxi_hdmi_ctrl_init();
|
||||
+
|
||||
+ while (timer_get_us() < tmo) {
|
||||
+ if (readl(&phy->status) & SUNXI_HDMI_HPD_DETECT) {
|
||||
|
|
@ -959,23 +970,25 @@ index 0000000..123017f
|
|||
+static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
|
||||
+ unsigned int address)
|
||||
+{
|
||||
+ struct de_clk * const de_clk_regs =
|
||||
+ (struct de_clk *)(SUNXI_DE2_BASE);
|
||||
+ struct de_glb * const de_glb_regs =
|
||||
+ (struct de_glb *)(DE_MUX0_BASE + DE_MUX_GLB_REGS);
|
||||
+ (struct de_glb *)(SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_GLB_REGS);
|
||||
+ struct de_bld * const de_bld_regs =
|
||||
+ (struct de_bld *)(DE_MUX0_BASE + DE_MUX_BLD_REGS);
|
||||
+ (struct de_bld *)(SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_BLD_REGS);
|
||||
+ struct de_ui * const de_ui_regs =
|
||||
+ (struct de_ui *)(DE_MUX0_BASE + DE_MUX_CHAN_REGS +
|
||||
+ DE_MUX_CHAN_SZ * 1);
|
||||
+ (struct de_ui *)(SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_CHAN_REGS +
|
||||
+ SUNXI_DE2_MUX_CHAN_SZ * 1);
|
||||
+ u32 size = WH(mode->xres, mode->yres);
|
||||
+ int channel, i;
|
||||
+ u32 data;
|
||||
+
|
||||
+ /* enable clock */
|
||||
+ setbits_le32(SUN8I_DE_RESET_REG, 1);
|
||||
+ setbits_le32(SUN8I_DE_GATE_REG, 1);
|
||||
+ setbits_le32(SUN8I_DE_MOD_REG, 1);
|
||||
+ setbits_le32(&de_clk_regs->rst_cfg, 1);
|
||||
+ setbits_le32(&de_clk_regs->gate_cfg, 1);
|
||||
+ setbits_le32(&de_clk_regs->bus_cfg, 1);
|
||||
+
|
||||
+ clrbits_le32(SUN8I_DE_SEL_REG, 1);
|
||||
+ clrbits_le32(&de_clk_regs->sel_cfg, 1);
|
||||
+
|
||||
+ writel(DE_MUX_GLB_CTL_rt_en, &de_glb_regs->ctl);
|
||||
+ writel(0, &de_glb_regs->status);
|
||||
|
|
@ -983,8 +996,8 @@ index 0000000..123017f
|
|||
+ writel(size, &de_glb_regs->size);
|
||||
+
|
||||
+ for (channel = 0; channel < 4; channel++) {
|
||||
+ void *chan = DE_MUX0_BASE + DE_MUX_CHAN_REGS +
|
||||
+ DE_MUX_CHAN_SZ * channel;
|
||||
+ void *chan = SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_CHAN_REGS +
|
||||
+ SUNXI_DE2_MUX_CHAN_SZ * channel;
|
||||
+ memset(chan, 0, channel == 0 ?
|
||||
+ sizeof(struct de_vi) : sizeof(struct de_ui));
|
||||
+ }
|
||||
|
|
@ -1011,19 +1024,19 @@ index 0000000..123017f
|
|||
+ }
|
||||
+
|
||||
+ /* Disable all other units */
|
||||
+ writel(0, DE_MUX0_BASE + DE_MUX_VSU_REGS);
|
||||
+ writel(0, DE_MUX0_BASE + DE_MUX_GSU1_REGS);
|
||||
+ writel(0, DE_MUX0_BASE + DE_MUX_GSU2_REGS);
|
||||
+ writel(0, DE_MUX0_BASE + DE_MUX_GSU3_REGS);
|
||||
+ writel(0, DE_MUX0_BASE + DE_MUX_FCE_REGS);
|
||||
+ writel(0, DE_MUX0_BASE + DE_MUX_BWS_REGS);
|
||||
+ writel(0, DE_MUX0_BASE + DE_MUX_LTI_REGS);
|
||||
+ writel(0, DE_MUX0_BASE + DE_MUX_PEAK_REGS);
|
||||
+ writel(0, DE_MUX0_BASE + DE_MUX_ASE_REGS);
|
||||
+ writel(0, DE_MUX0_BASE + DE_MUX_FCC_REGS);
|
||||
+ writel(0, DE_MUX0_BASE + DE_MUX_DCSC_REGS);
|
||||
+ writel(0, SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_VSU_REGS);
|
||||
+ writel(0, SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_GSU1_REGS);
|
||||
+ writel(0, SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_GSU2_REGS);
|
||||
+ writel(0, SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_GSU3_REGS);
|
||||
+ writel(0, SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_FCE_REGS);
|
||||
+ writel(0, SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_BWS_REGS);
|
||||
+ writel(0, SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_LTI_REGS);
|
||||
+ writel(0, SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_PEAK_REGS);
|
||||
+ writel(0, SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_ASE_REGS);
|
||||
+ writel(0, SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_FCC_REGS);
|
||||
+ writel(0, SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_DCSC_REGS);
|
||||
+
|
||||
+ data = UI_CFG_ATTR_en | (DE2_FORMAT_XRGB_8888 << UI_CFG_ATTR_fmt_SHIFT) |
|
||||
+ data = UI_CFG_ATTR_en | (SUNXI_DE2_FORMAT_XRGB_8888 << UI_CFG_ATTR_fmt_SHIFT) |
|
||||
+ (1 << UI_CFG_ATTR_alpmod_SHIFT) | (0xff << UI_CFG_ATTR_alpha_SHIFT);
|
||||
+ writel(data, &de_ui_regs->cfg[0].attr);
|
||||
+ writel(size, &de_ui_regs->cfg[0].size);
|
||||
|
|
@ -1036,7 +1049,7 @@ index 0000000..123017f
|
|||
+static void sunxi_composer_enable(void)
|
||||
+{
|
||||
+ struct de_glb * const de_glb_regs =
|
||||
+ (struct de_glb *)(DE_MUX0_BASE + DE_MUX_GLB_REGS);
|
||||
+ (struct de_glb *)(SUNXI_DE2_MUX0_BASE + SUNXI_DE2_MUX_GLB_REGS);
|
||||
+
|
||||
+ writel(1, &de_glb_regs->dbuff);
|
||||
+}
|
||||
|
|
@ -1066,7 +1079,7 @@ index 0000000..123017f
|
|||
+ x = 1;
|
||||
+
|
||||
+ /*
|
||||
+ * Find the lowest divider resulting in a matching clock, if there
|
||||
+ * Find the lowest divider resulting in a matching clock. If there
|
||||
+ * is no match, pick the closest lower clock, as monitors tend to
|
||||
+ * not sync to higher frequencies.
|
||||
+ */
|
||||
|
|
@ -1536,29 +1549,127 @@ index 0000000..123017f
|
|||
+
|
||||
+ return graphic_device;
|
||||
+}
|
||||
+
|
||||
+/*
|
||||
+ * Simplefb support.
|
||||
+ */
|
||||
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
|
||||
+int sunxi_simplefb_setup(void *blob)
|
||||
+{
|
||||
+ static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
|
||||
+ int offset, ret;
|
||||
+ u64 start, size;
|
||||
+ const char *pipeline = NULL;
|
||||
+
|
||||
+ switch (sunxi_display.monitor) {
|
||||
+ case sunxi_monitor_none:
|
||||
+ return 0;
|
||||
+ case sunxi_monitor_dvi:
|
||||
+ case sunxi_monitor_hdmi:
|
||||
+ pipeline = "de0-lcd0-hdmi";
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ /* Find a prefilled simpefb node, matching out pipeline config */
|
||||
+ offset = fdt_node_offset_by_compatible(blob, -1,
|
||||
+ "allwinner,simple-framebuffer");
|
||||
+ while (offset >= 0) {
|
||||
+ ret = fdt_stringlist_search(blob, offset, "allwinner,pipeline",
|
||||
+ pipeline);
|
||||
+ if (ret == 0)
|
||||
+ break;
|
||||
+ offset = fdt_node_offset_by_compatible(blob, offset,
|
||||
+ "allwinner,simple-framebuffer");
|
||||
+ }
|
||||
+ if (offset < 0) {
|
||||
+ eprintf("Cannot setup simplefb: node not found\n");
|
||||
+ return 0; /* Keep older kernels working */
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
+ * Do not report the framebuffer as free RAM to the OS, note we cannot
|
||||
+ * use fdt_add_mem_rsv() here, because then it is still seen as RAM,
|
||||
+ * and e.g. Linux refuses to iomap RAM on ARM, see:
|
||||
+ * linux/arch/arm/mm/ioremap.c around line 301.
|
||||
+ */
|
||||
+ start = gd->bd->bi_dram[0].start;
|
||||
+ size = gd->bd->bi_dram[0].size - sunxi_display.fb_size;
|
||||
+ ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
|
||||
+ if (ret) {
|
||||
+ eprintf("Cannot setup simplefb: Error reserving memory\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ ret = fdt_setup_simplefb_node(blob, offset, sunxi_display.fb_addr,
|
||||
+ graphic_device->winSizeX, graphic_device->winSizeY,
|
||||
+ graphic_device->plnSizeX, "x8r8g8b8");
|
||||
+ if (ret)
|
||||
+ eprintf("Cannot setup simplefb: Error setting properties\n");
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+#endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */
|
||||
diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
|
||||
index 011d70f..c4eb3ba 100644
|
||||
--- a/include/configs/sun8i.h
|
||||
+++ b/include/configs/sun8i.h
|
||||
@@ -26,6 +26,10 @@
|
||||
#define CONFIG_SUNXI_USB_PHYS 2
|
||||
#endif
|
||||
|
||||
+#if defined(CONFIG_MACH_SUN8I_H3)
|
||||
+ #define CONFIG_SUNXI_DE2 1
|
||||
+#endif
|
||||
+
|
||||
/*
|
||||
* Include common sunxi configuration where most the settings are
|
||||
*/
|
||||
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
|
||||
index e0464df..c6032aa 100644
|
||||
index e0464df..211a37b 100644
|
||||
--- a/include/configs/sunxi-common.h
|
||||
+++ b/include/configs/sunxi-common.h
|
||||
@@ -284,9 +284,13 @@ extern int soft_i2c_gpio_scl;
|
||||
#define CONFIG_SUNXI_MAX_FB_SIZE (16 << 20)
|
||||
@@ -277,16 +277,23 @@ extern int soft_i2c_gpio_scl;
|
||||
#define CONFIG_SUNXI_GPIO
|
||||
|
||||
/* Do we want to initialize a simple FB? */
|
||||
#ifdef CONFIG_VIDEO
|
||||
+/* Do we want to initialize a simple FB? */
|
||||
+#define CONFIG_VIDEO_DT_SIMPLEFB
|
||||
+#ifndef CONFIG_MACH_SUN8I_H3
|
||||
#define CONFIG_VIDEO_DT_SIMPLEFB
|
||||
|
||||
#define CONFIG_VIDEO_SUNXI
|
||||
+#define CONFIG_VIDEO_SUNXI
|
||||
+#else
|
||||
+#define CONFIG_VIDEO_SUNXI2
|
||||
+#endif
|
||||
+
|
||||
/*
|
||||
* The amount of RAM to keep free at the top of RAM when relocating u-boot,
|
||||
* to use as framebuffer. This must be a multiple of 4096.
|
||||
*/
|
||||
+#ifndef CONFIG_VIDEO_SUNXI2
|
||||
#define CONFIG_SUNXI_MAX_FB_SIZE (16 << 20)
|
||||
-
|
||||
-/* Do we want to initialize a simple FB? */
|
||||
-#define CONFIG_VIDEO_DT_SIMPLEFB
|
||||
-
|
||||
-#define CONFIG_VIDEO_SUNXI
|
||||
+#else
|
||||
+#define CONFIG_SUNXI_MAX_FB_SIZE (32 << 20)
|
||||
+#endif
|
||||
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_VIDEO_STD_TIMINGS
|
||||
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
|
||||
index 11b5a22..be8850a 100644
|
||||
index 11b5a22..abb6d55 100644
|
||||
--- a/scripts/config_whitelist.txt
|
||||
+++ b/scripts/config_whitelist.txt
|
||||
@@ -8270,6 +8270,7 @@ CONFIG_VIDEO_SM501_8BPP
|
||||
@@ -4357,6 +4357,7 @@ CONFIG_ST_SMI
|
||||
CONFIG_SUN4
|
||||
CONFIG_SUNXI
|
||||
CONFIG_SUNXI_AHCI
|
||||
+CONFIG_SUNXI_DE2
|
||||
CONFIG_SUNXI_EMAC
|
||||
CONFIG_SUNXI_GMAC
|
||||
CONFIG_SUNXI_GPIO
|
||||
@@ -8270,6 +8271,7 @@ CONFIG_VIDEO_SM501_8BPP
|
||||
CONFIG_VIDEO_SM501_PCI
|
||||
CONFIG_VIDEO_STD_TIMINGS
|
||||
CONFIG_VIDEO_SUNXI
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue