mirror of
https://github.com/Fishwaldo/build.git
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Reverting mvebu64 to K4.19 (#1926)
It doesn't want to boot on 5.4.y. Adjusting kernel config, fix Docker dependency problem, move few other minor fixes from openwrt and closing https://github.com/armbian/build/issues/1453
This commit is contained in:
Igor Pečovnik
GitHub
parent
142f0506fe
commit
716bd3b9dc
29 changed files with 41601 additions and 987 deletions
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@ -7,6 +7,8 @@
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setenv rootdev "/dev/mmcblk0p1"
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setenv verbosity "1"
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setenv rootfstype "ext4"
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setenv fdt_name_a dtb/marvell/armada-3720-community.dtb
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setenv fdt_name_b dtb/marvell/armada-3720-espressobin.dtb
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# additional values
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setenv ethaddr "F0:AD:4E:03:64:7F"
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@ -16,13 +18,10 @@ env import -t ${scriptaddr} ${filesize}
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setenv bootargs "$console root=${rootdev} rootfstype=${rootfstype} rootwait loglevel=${verbosity} usb-storage.quirks=${usbstoragequirks} mtdparts=spi0.0:1536k(uboot),64k(uboot-environment),-(reserved) ${extraargs}"
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setenv fdt_name_a dtb/marvell/armada-3720-community.dtb
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setenv fdt_name_b dtb/marvell/armada-3720-espressobin.dtb
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ext4load $boot_interface 0:1 $kernel_addr ${prefix}$image_name
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ext4load $boot_interface 0:1 $initrd_addr ${prefix}$initrd_image
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ext4load $boot_interface 0:1 $fdt_addr ${prefix}$fdt_name_a
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ext4load $boot_interface 0:1 $fdt_addr ${prefix}$fdt_name_b
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booti $kernel_addr $initrd_addr $fdt_addr
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# mkimage -C none -A arm -T script -d /boot/boot.cmd /boot/boot.scr
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# mkimage -C none -A arm -T script -d /boot/boot.cmd /boot/boot.scr
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|
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File diff suppressed because it is too large
Load diff
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@ -38,7 +38,7 @@ case $BRANCH in
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current)
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KERNELBRANCH='branch:linux-5.4.y'
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KERNELBRANCH='branch:linux-4.19.y'
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;;
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|
|
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|
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@ -1,20 +0,0 @@
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diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
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index 2ce52ba..a759fd1 100644
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--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
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+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
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@@ -96,6 +96,15 @@
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status = "okay";
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};
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+&sdhci0 {
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+ non-removable;
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+ bus-width = <8>;
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+ mmc-ddr-1_8v;
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+ mmc-hs400-1_8v;
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+ marvell,pad-type = "fixed-1-8v";
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+ status = "okay";
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+};
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+
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/* Exported on the micro USB connector J5 through an FTDI */
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&uart0 {
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status = "okay";
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@ -0,0 +1,40 @@
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From 480d99fdc3eee31a23c317927a335e9a71c2904f Mon Sep 17 00:00:00 2001
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From: Gregory CLEMENT <gregory.clement@bootlin.com>
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Date: Wed, 10 Oct 2018 20:18:38 +0200
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Subject: clk: mvebu: armada-37xx-tbg: Switch to clk_get and balance it in
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probe
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The parent clock is get only to have its name, and then the clock is no
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more used, so we can safely free it using clk_put. Furthermore as between
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the successful devm_clk_get() and the devm_clk_put() call we don't exit
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the probe function in error so I can use non managed version of clk_get()
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and clk_put().
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Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/mvebu/armada-37xx-tbg.c | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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diff --git a/drivers/clk/mvebu/armada-37xx-tbg.c b/drivers/clk/mvebu/armada-37xx-tbg.c
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index 7ff041f73b55..4de15d44a0c1 100644
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--- a/drivers/clk/mvebu/armada-37xx-tbg.c
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+++ b/drivers/clk/mvebu/armada-37xx-tbg.c
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@@ -99,12 +99,13 @@ static int armada_3700_tbg_clock_probe(struct platform_device *pdev)
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hw_tbg_data->num = NUM_TBG;
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platform_set_drvdata(pdev, hw_tbg_data);
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- parent = devm_clk_get(dev, NULL);
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+ parent = clk_get(dev, NULL);
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if (IS_ERR(parent)) {
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dev_err(dev, "Could get the clock parent\n");
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return -EINVAL;
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}
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parent_name = __clk_get_name(parent);
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+ clk_put(parent);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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reg = devm_ioremap_resource(dev, res);
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--
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cgit 1.2-0.3.lf.el7
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@ -0,0 +1,70 @@
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From d9d95e78cff80c3fe43e757ba90644cd766302ac Mon Sep 17 00:00:00 2001
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From: Miquel Raynal <miquel.raynal@bootlin.com>
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Date: Fri, 13 Jul 2018 15:44:45 +0200
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Subject: clk: mvebu: armada-37xx-periph: save the IP base address in the
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driver data
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Prepare the introduction of suspend/resume hooks by having an easy way
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to access all the registers in one go just from a device: add the IP
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base address in the driver data.
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/mvebu/armada-37xx-periph.c | 15 +++++++--------
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1 file changed, 7 insertions(+), 8 deletions(-)
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diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c
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index 499f5962c8b0..78048c2e3774 100644
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--- a/drivers/clk/mvebu/armada-37xx-periph.c
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+++ b/drivers/clk/mvebu/armada-37xx-periph.c
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@@ -56,6 +56,7 @@
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struct clk_periph_driver_data {
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struct clk_hw_onecell_data *hw_data;
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spinlock_t lock;
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+ void __iomem *reg;
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};
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struct clk_double_div {
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@@ -680,7 +681,6 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev)
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struct device *dev = &pdev->dev;
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int num_periph = 0, i, ret;
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struct resource *res;
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- void __iomem *reg;
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data = of_device_get_match_data(dev);
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if (!data)
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@@ -689,11 +689,6 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev)
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while (data[num_periph].name)
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num_periph++;
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- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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- reg = devm_ioremap_resource(dev, res);
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- if (IS_ERR(reg))
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- return PTR_ERR(reg);
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-
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driver_data = devm_kzalloc(dev, sizeof(*driver_data), GFP_KERNEL);
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if (!driver_data)
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return -ENOMEM;
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@@ -706,12 +701,16 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev)
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return -ENOMEM;
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driver_data->hw_data->num = num_periph;
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ driver_data->reg = devm_ioremap_resource(dev, res);
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+ if (IS_ERR(driver_data->reg))
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+ return PTR_ERR(driver_data->reg);
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+
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spin_lock_init(&driver_data->lock);
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for (i = 0; i < num_periph; i++) {
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struct clk_hw **hw = &driver_data->hw_data->hws[i];
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-
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- if (armada_3700_add_composite_clk(&data[i], reg,
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+ if (armada_3700_add_composite_clk(&data[i], driver_data->reg,
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&driver_data->lock, dev, hw))
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dev_err(dev, "Can't register periph clock %s\n",
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data[i].name);
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--
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cgit 1.2-0.3.lf.el7
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@ -0,0 +1,92 @@
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From 5beb1e60dba973e0b9cfb54d9735d5d4385b9d90 Mon Sep 17 00:00:00 2001
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From: Miquel Raynal <miquel.raynal@bootlin.com>
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Date: Fri, 13 Jul 2018 15:44:46 +0200
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Subject: clk: mvebu: armada-37xx-periph: add suspend/resume support
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Add suspend/resume hooks in Armada 37xx peripheral clocks driver to
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handle S2RAM operations.
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One can think that these hooks are useless by comparing the register
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values before and after a suspend/resume cycle: they will look the same
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anyway. This is because of some scripts executed by the Cortex-M3 core
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during ATF operations to init both the clocks and the DDR. These values
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could be modified by the BL33 stage or by Linux itself and should be
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preserved.
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/mvebu/armada-37xx-periph.c | 43 ++++++++++++++++++++++++++++++++++
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1 file changed, 43 insertions(+)
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diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c
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index 78048c2e3774..1f1cff428d78 100644
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--- a/drivers/clk/mvebu/armada-37xx-periph.c
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+++ b/drivers/clk/mvebu/armada-37xx-periph.c
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@@ -57,6 +57,14 @@ struct clk_periph_driver_data {
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struct clk_hw_onecell_data *hw_data;
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spinlock_t lock;
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void __iomem *reg;
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+
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+ /* Storage registers for suspend/resume operations */
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+ u32 tbg_sel;
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+ u32 div_sel0;
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+ u32 div_sel1;
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+ u32 div_sel2;
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+ u32 clk_sel;
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+ u32 clk_dis;
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};
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struct clk_double_div {
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@@ -673,6 +681,40 @@ static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
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return PTR_ERR_OR_ZERO(*hw);
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}
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+static int __maybe_unused armada_3700_periph_clock_suspend(struct device *dev)
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+{
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+ struct clk_periph_driver_data *data = dev_get_drvdata(dev);
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+
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+ data->tbg_sel = readl(data->reg + TBG_SEL);
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+ data->div_sel0 = readl(data->reg + DIV_SEL0);
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+ data->div_sel1 = readl(data->reg + DIV_SEL1);
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+ data->div_sel2 = readl(data->reg + DIV_SEL2);
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+ data->clk_sel = readl(data->reg + CLK_SEL);
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+ data->clk_dis = readl(data->reg + CLK_DIS);
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+
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+ return 0;
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+}
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+
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+static int __maybe_unused armada_3700_periph_clock_resume(struct device *dev)
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+{
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+ struct clk_periph_driver_data *data = dev_get_drvdata(dev);
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+
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+ /* Follow the same order than what the Cortex-M3 does (ATF code) */
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+ writel(data->clk_dis, data->reg + CLK_DIS);
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+ writel(data->div_sel0, data->reg + DIV_SEL0);
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+ writel(data->div_sel1, data->reg + DIV_SEL1);
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+ writel(data->div_sel2, data->reg + DIV_SEL2);
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+ writel(data->tbg_sel, data->reg + TBG_SEL);
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+ writel(data->clk_sel, data->reg + CLK_SEL);
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+
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+ return 0;
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+}
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+
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+static const struct dev_pm_ops armada_3700_periph_clock_pm_ops = {
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+ SET_SYSTEM_SLEEP_PM_OPS(armada_3700_periph_clock_suspend,
|
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+ armada_3700_periph_clock_resume)
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+};
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+
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static int armada_3700_periph_clock_probe(struct platform_device *pdev)
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{
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struct clk_periph_driver_data *driver_data;
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@@ -748,6 +790,7 @@ static struct platform_driver armada_3700_periph_clock_driver = {
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.driver = {
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.name = "marvell-armada-3700-periph-clock",
|
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.of_match_table = armada_3700_periph_clock_of_match,
|
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+ .pm = &armada_3700_periph_clock_pm_ops,
|
||||
},
|
||||
};
|
||||
|
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--
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cgit 1.2-0.3.lf.el7
|
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|
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|
|
@ -0,0 +1,40 @@
|
|||
From eefe328439642101774f0f5c4ea0dc6ba1cfb687 Mon Sep 17 00:00:00 2001
|
||||
From: Ding Tao <miyatsu@qq.com>
|
||||
Date: Fri, 26 Oct 2018 11:50:27 +0000
|
||||
Subject: [PATCH] arm64: dts: marvell: armada37xx: Add emmc/sdio pinctrl
|
||||
definition
|
||||
|
||||
Add emmc/sdio pinctrl definition for marvell armada37xx SoCs.
|
||||
|
||||
Signed-off-by: Ding Tao <miyatsu@qq.com>
|
||||
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
|
||||
---
|
||||
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 10 ++++++++++
|
||||
1 file changed, 10 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
||||
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
||||
@@ -221,6 +221,11 @@
|
||||
groups = "uart2";
|
||||
function = "uart";
|
||||
};
|
||||
+
|
||||
+ mmc_pins: mmc-pins {
|
||||
+ groups = "emmc_nb";
|
||||
+ function = "emmc";
|
||||
+ };
|
||||
};
|
||||
|
||||
nb_pm: syscon@14000 {
|
||||
@@ -253,6 +258,11 @@
|
||||
function = "mii";
|
||||
};
|
||||
|
||||
+ sdio_pins: sdio-pins {
|
||||
+ groups = "sdio_sb";
|
||||
+ function = "sdio";
|
||||
+ };
|
||||
+
|
||||
};
|
||||
|
||||
eth0: ethernet@30000 {
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
From 43ebc7c1b3ed8198b9acf3019eca16e722f7331c Mon Sep 17 00:00:00 2001
|
||||
From: Ding Tao <miyatsu@qq.com>
|
||||
Date: Fri, 26 Oct 2018 11:50:28 +0000
|
||||
Subject: [PATCH] arm64: dts: marvell: armada-37xx: Enable emmc on espressobin
|
||||
|
||||
The ESPRESSObin board has a emmc interface available on U11: declare it
|
||||
and let the bootloader enable it if the emmc is present.
|
||||
|
||||
[gregory.clement@bootlin.com: disable the emmc by default]
|
||||
Signed-off-by: Ding Tao <miyatsu@qq.com>
|
||||
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
|
||||
---
|
||||
.../dts/marvell/armada-3720-espressobin.dts | 22 +++++++++++++++++++
|
||||
1 file changed, 22 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
||||
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
||||
@@ -60,9 +60,31 @@
|
||||
cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
|
||||
marvell,pad-type = "sd";
|
||||
vqmmc-supply = <&vcc_sd_reg1>;
|
||||
+
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdio_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+/* U11 */
|
||||
+&sdhci0 {
|
||||
+ non-removable;
|
||||
+ bus-width = <8>;
|
||||
+ mmc-ddr-1_8v;
|
||||
+ mmc-hs400-1_8v;
|
||||
+ marvell,xenon-emmc;
|
||||
+ marvell,xenon-tun-count = <9>;
|
||||
+ marvell,pad-type = "fixed-1-8v";
|
||||
+
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&mmc_pins>;
|
||||
+/*
|
||||
+ * This eMMC is not populated on all boards, so disable it by
|
||||
+ * default and let the bootloader enable it, if it is present
|
||||
+ */
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
From 6ea9a1ee9367fb35acff1c08a0dc4213ff4687a0 Mon Sep 17 00:00:00 2001
|
||||
From: Tomasz Maciej Nowak <tmn505@gmail.com>
|
||||
Date: Tue, 9 Apr 2019 15:53:42 +0200
|
||||
Subject: [PATCH] arm64: dts: marvell: armada-3720-espressobin: add ports
|
||||
phandle
|
||||
|
||||
Instead of referencing the whole mdio node, add ports phandle to adjust
|
||||
port labels in dts for different hardware iterations of ESPRESSObin
|
||||
boards.
|
||||
|
||||
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
||||
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
||||
@@ -132,7 +132,7 @@
|
||||
|
||||
dsa,member = <0 0>;
|
||||
|
||||
- ports {
|
||||
+ ports: ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
From 5e79c0c381eb085a2aa2da175eedea1950f07520 Mon Sep 17 00:00:00 2001
|
||||
From: Tomasz Maciej Nowak <tomek_n@o2.pl>
|
||||
Date: Tue, 30 Apr 2019 15:37:34 +0200
|
||||
Subject: [PATCH] Revert "PCI: aardvark: Convert to use pci_host_probe()"
|
||||
|
||||
This reverts commit c8e144f8ab00e6c4a070a932ef9c57db09aa41cf.
|
||||
---
|
||||
drivers/pci/controller/pci-aardvark.c | 12 +++++++++++-
|
||||
1 file changed, 11 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/pci/controller/pci-aardvark.c
|
||||
+++ b/drivers/pci/controller/pci-aardvark.c
|
||||
@@ -843,6 +843,7 @@ static int advk_pcie_probe(struct platfo
|
||||
struct device *dev = &pdev->dev;
|
||||
struct advk_pcie *pcie;
|
||||
struct resource *res;
|
||||
+ struct pci_bus *bus, *child;
|
||||
struct pci_host_bridge *bridge;
|
||||
int ret, irq;
|
||||
|
||||
@@ -896,13 +897,22 @@ static int advk_pcie_probe(struct platfo
|
||||
bridge->map_irq = of_irq_parse_and_map_pci;
|
||||
bridge->swizzle_irq = pci_common_swizzle;
|
||||
|
||||
- ret = pci_host_probe(bridge);
|
||||
+ ret = pci_scan_root_bus_bridge(bridge);
|
||||
if (ret < 0) {
|
||||
advk_pcie_remove_msi_irq_domain(pcie);
|
||||
advk_pcie_remove_irq_domain(pcie);
|
||||
return ret;
|
||||
}
|
||||
|
||||
+ bus = bridge->bus;
|
||||
+
|
||||
+ pci_bus_size_bridges(bus);
|
||||
+ pci_bus_assign_resources(bus);
|
||||
+
|
||||
+ list_for_each_entry(child, &bus->children, node)
|
||||
+ pcie_bus_configure_settings(child);
|
||||
+
|
||||
+ pci_bus_add_devices(bus);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,138 @@
|
|||
From patchwork Thu Sep 28 12:58:34 2017
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v2,
|
||||
3/7] PCI: aardvark: set host and device to the same MAX payload size
|
||||
X-Patchwork-Submitter: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
X-Patchwork-Id: 819587
|
||||
Message-Id: <20170928125838.11887-4-thomas.petazzoni@free-electrons.com>
|
||||
To: Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org
|
||||
Cc: Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
|
||||
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Gregory Clement
|
||||
<gregory.clement@free-electrons.com>,
|
||||
Nadav Haklai <nadavh@marvell.com>, Hanna Hawa <hannah@marvell.com>,
|
||||
Yehuda Yitschak <yehuday@marvell.com>,
|
||||
linux-arm-kernel@lists.infradead.org, Antoine Tenart
|
||||
<antoine.tenart@free-electrons.com>, =?utf-8?q?Miqu=C3=A8l_Raynal?=
|
||||
<miquel.raynal@free-electrons.com>, Victor Gu <xigu@marvell.com>,
|
||||
Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
Date: Thu, 28 Sep 2017 14:58:34 +0200
|
||||
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
List-Id: <linux-pci.vger.kernel.org>
|
||||
|
||||
From: Victor Gu <xigu@marvell.com>
|
||||
|
||||
Since the Aardvark does not implement a PCIe root bus, the Linux PCIe
|
||||
subsystem will not align the MAX payload size between the host and the
|
||||
device. This patch ensures that the host and device have the same MAX
|
||||
payload size, fixing a number of problems with various PCIe devices.
|
||||
|
||||
This is part of fixing bug
|
||||
https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
|
||||
reported as the user to be important to get a Intel 7260 mini-PCIe
|
||||
WiFi card working.
|
||||
|
||||
Fixes: Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
|
||||
Signed-off-by: Victor Gu <xigu@marvell.com>
|
||||
Reviewed-by: Evan Wang <xswang@marvell.com>
|
||||
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
|
||||
[Thomas: tweak commit log.]
|
||||
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
---
|
||||
drivers/pci/controller/pci-aardvark.c | 60 ++++++++++++++++++++++++++++++++++++++++-
|
||||
1 file changed, 59 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/pci/controller/pci-aardvark.c
|
||||
+++ b/drivers/pci/controller/pci-aardvark.c
|
||||
@@ -29,9 +29,11 @@
|
||||
#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
|
||||
#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
|
||||
#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
|
||||
+#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2
|
||||
#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
|
||||
#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
|
||||
#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2
|
||||
+#define PCIE_CORE_MPS_UNIT_BYTE 128
|
||||
#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
|
||||
#define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
|
||||
#define PCIE_CORE_LINK_TRAINING BIT(5)
|
||||
@@ -253,7 +255,8 @@ static void advk_pcie_setup_hw(struct ad
|
||||
|
||||
/* Set PCIe Device Control and Status 1 PF0 register */
|
||||
reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
|
||||
- (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
|
||||
+ (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ <<
|
||||
+ PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
|
||||
PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
|
||||
(PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
|
||||
PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
|
||||
@@ -838,6 +841,58 @@ out_release_res:
|
||||
return err;
|
||||
}
|
||||
|
||||
+static int advk_pcie_find_smpss(struct pci_dev *dev, void *data)
|
||||
+{
|
||||
+ u8 *smpss = data;
|
||||
+
|
||||
+ if (!dev)
|
||||
+ return 0;
|
||||
+
|
||||
+ if (!pci_is_pcie(dev))
|
||||
+ return 0;
|
||||
+
|
||||
+ if (*smpss > dev->pcie_mpss)
|
||||
+ *smpss = dev->pcie_mpss;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int advk_pcie_bus_configure_mps(struct pci_dev *dev, void *data)
|
||||
+{
|
||||
+ int mps;
|
||||
+
|
||||
+ if (!dev)
|
||||
+ return 0;
|
||||
+
|
||||
+ if (!pci_is_pcie(dev))
|
||||
+ return 0;
|
||||
+
|
||||
+ mps = PCIE_CORE_MPS_UNIT_BYTE << *(u8 *)data;
|
||||
+ pcie_set_mps(dev, mps);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void advk_pcie_configure_mps(struct pci_bus *bus, struct advk_pcie *pcie)
|
||||
+{
|
||||
+ u8 smpss = PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ;
|
||||
+ u32 reg;
|
||||
+
|
||||
+ /* Find the minimal supported MAX payload size */
|
||||
+ advk_pcie_find_smpss(bus->self, &smpss);
|
||||
+ pci_walk_bus(bus, advk_pcie_find_smpss, &smpss);
|
||||
+
|
||||
+ /* Configure RC MAX payload size */
|
||||
+ reg = advk_readl(pcie, PCIE_CORE_DEV_CTRL_STATS_REG);
|
||||
+ reg &= ~PCI_EXP_DEVCTL_PAYLOAD;
|
||||
+ reg |= smpss << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT;
|
||||
+ advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
|
||||
+
|
||||
+ /* Configure device MAX payload size */
|
||||
+ advk_pcie_bus_configure_mps(bus->self, &smpss);
|
||||
+ pci_walk_bus(bus, advk_pcie_bus_configure_mps, &smpss);
|
||||
+}
|
||||
+
|
||||
static int advk_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
@@ -912,6 +967,9 @@ static int advk_pcie_probe(struct platfo
|
||||
list_for_each_entry(child, &bus->children, node)
|
||||
pcie_bus_configure_settings(child);
|
||||
|
||||
+ /* Configure the MAX pay load size */
|
||||
+ advk_pcie_configure_mps(bus, pcie);
|
||||
+
|
||||
pci_bus_add_devices(bus);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
From patchwork Thu Sep 28 12:58:36 2017
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
Subject: [v2,5/7] PCI: aardvark: disable LOS state by default
|
||||
X-Patchwork-Submitter: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
X-Patchwork-Id: 819590
|
||||
Message-Id: <20170928125838.11887-6-thomas.petazzoni@free-electrons.com>
|
||||
To: Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org
|
||||
Cc: Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
|
||||
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Gregory Clement
|
||||
<gregory.clement@free-electrons.com>,
|
||||
Nadav Haklai <nadavh@marvell.com>, Hanna Hawa <hannah@marvell.com>,
|
||||
Yehuda Yitschak <yehuday@marvell.com>,
|
||||
linux-arm-kernel@lists.infradead.org, Antoine Tenart
|
||||
<antoine.tenart@free-electrons.com>, =?utf-8?q?Miqu=C3=A8l_Raynal?=
|
||||
<miquel.raynal@free-electrons.com>, Victor Gu <xigu@marvell.com>,
|
||||
Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
Date: Thu, 28 Sep 2017 14:58:36 +0200
|
||||
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
List-Id: <linux-pci.vger.kernel.org>
|
||||
|
||||
From: Victor Gu <xigu@marvell.com>
|
||||
|
||||
Some PCIe devices do not support LOS, and will cause timeouts if the
|
||||
root complex forces the LOS state. This patch disables the LOS state
|
||||
by default.
|
||||
|
||||
This is part of fixing bug
|
||||
https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
|
||||
reported as the user to be important to get a Intel 7260 mini-PCIe
|
||||
WiFi card working.
|
||||
|
||||
Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
|
||||
Signed-off-by: Victor Gu <xigu@marvell.com>
|
||||
Reviewed-by: Evan Wang <xswang@marvell.com>
|
||||
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
|
||||
[Thomas: tweak commit log.]
|
||||
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
---
|
||||
drivers/pci/controller/pci-aardvark.c | 3 +--
|
||||
1 file changed, 1 insertion(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/pci/controller/pci-aardvark.c
|
||||
+++ b/drivers/pci/controller/pci-aardvark.c
|
||||
@@ -324,8 +324,7 @@ static void advk_pcie_setup_hw(struct ad
|
||||
|
||||
advk_pcie_wait_for_link(pcie);
|
||||
|
||||
- reg = PCIE_CORE_LINK_L0S_ENTRY |
|
||||
- (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
|
||||
+ reg = (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
|
||||
advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
|
||||
|
||||
reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
From f70b629e488cc3f2a325ac35476f4f7ae502c5d0 Mon Sep 17 00:00:00 2001
|
||||
From: Tomasz Maciej Nowak <tmn505@gmail.com>
|
||||
Date: Thu, 14 Jun 2018 14:24:40 +0200
|
||||
Subject: [PATCH 1/2] PCI: aardvark: allow to specify link capability
|
||||
|
||||
Use DT of_pci_get_max_link_speed() facility to allow specifying link
|
||||
capability. If none or unspecified value is given it falls back to gen2,
|
||||
which is default for Armada 3700 SoC.
|
||||
|
||||
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
|
||||
---
|
||||
drivers/pci/controller/pci-aardvark.c | 11 +++++++++--
|
||||
1 file changed, 9 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/pci/controller/pci-aardvark.c
|
||||
+++ b/drivers/pci/controller/pci-aardvark.c
|
||||
@@ -233,6 +233,8 @@ static int advk_pcie_wait_for_link(struc
|
||||
|
||||
static void advk_pcie_setup_hw(struct advk_pcie *pcie)
|
||||
{
|
||||
+ struct device *dev = &pcie->pdev->dev;
|
||||
+ struct device_node *node = dev->of_node;
|
||||
u32 reg;
|
||||
|
||||
/* Set to Direct mode */
|
||||
@@ -267,10 +269,15 @@ static void advk_pcie_setup_hw(struct ad
|
||||
PCIE_CORE_CTRL2_TD_ENABLE;
|
||||
advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
|
||||
|
||||
- /* Set GEN2 */
|
||||
+ /* Set GEN */
|
||||
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
|
||||
reg &= ~PCIE_GEN_SEL_MSK;
|
||||
- reg |= SPEED_GEN_2;
|
||||
+ if (of_pci_get_max_link_speed(node) == 1)
|
||||
+ reg |= SPEED_GEN_1;
|
||||
+ else if (of_pci_get_max_link_speed(node) == 3)
|
||||
+ reg |= SPEED_GEN_3;
|
||||
+ else
|
||||
+ reg |= SPEED_GEN_2;
|
||||
advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
|
||||
|
||||
/* Set lane X1 */
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
From 33f8fdcedb01680427328d710594facef7a0092c Mon Sep 17 00:00:00 2001
|
||||
From: Tomasz Maciej Nowak <tmn505@gmail.com>
|
||||
Date: Thu, 14 Jun 2018 14:40:26 +0200
|
||||
Subject: [PATCH 2/2] arm64: dts: armada-3720-espressobin: set max link to gen1
|
||||
|
||||
Since the beginning there's been an issue with initializing the Atheros
|
||||
based MiniPCIe wireless cards. Here's an example of kerenel log:
|
||||
|
||||
OF: PCI: host bridge /soc/pcie@d0070000 ranges:
|
||||
OF: PCI: MEM 0xe8000000..0xe8ffffff -> 0xe8000000
|
||||
OF: PCI: IO 0xe9000000..0xe900ffff -> 0xe9000000
|
||||
advk-pcie d0070000.pcie: link up
|
||||
advk-pcie d0070000.pcie: PCI host bridge to bus 0000:00
|
||||
pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
pci_bus 0000:00: root bus resource [mem0xe8000000-0xe8ffffff]
|
||||
pci_bus 0000:00: root bus resource [io 0x0000-0xffff](bus address [0xe9000000-0xe900ffff])
|
||||
pci 0000:00:00.0: BAR 0: assigned [mem0xe8000000-0xe801ffff 64bit]
|
||||
pci 0000:00:00.0: BAR 6: assigned [mem0xe8020000-0xe802ffff pref]
|
||||
[...]
|
||||
advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x3c
|
||||
advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x44
|
||||
advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x4
|
||||
ath9k 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x3c
|
||||
advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0xc
|
||||
advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x4
|
||||
advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x40
|
||||
ath9k 0000:00:00.0: request_irq failed
|
||||
advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x4
|
||||
ath9k: probe of 0000:00:00.0 failed with error -22
|
||||
|
||||
The same happens for ath5k cards, while ath10k card didn't appear at
|
||||
all (not detected):
|
||||
|
||||
OF: PCI: host bridge /soc/pcie@d0070000 ranges:
|
||||
OF: PCI: MEM 0xe8000000..0xe8ffffff -> 0xe8000000
|
||||
OF: PCI: IO 0xe9000000..0xe900ffff -> 0xe9000000
|
||||
advk-pcie d0070000.pcie: link never came up
|
||||
advk-pcie d0070000.pcie: PCI host bridge to bus 0000:00
|
||||
pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
pci_bus 0000:00: root bus resource [mem0xe8000000-0xe8ffffff]
|
||||
pci_bus 0000:00: root bus resource [io 0x0000-0xffff](bus address [0xe9000000-0xe900ffff])
|
||||
advk-pcie d0070000.pcie: config read/write timed out
|
||||
|
||||
Following the issue on esppressobin.net forum [1] the workaround seems
|
||||
to be limiting the speed of PCIe bridge to 1st generation. This fixed
|
||||
the initialisation of all tested Atheros wireless cards.
|
||||
The patch in the forum thread swaped registers which would limit speed
|
||||
for all Armada 3700 based boards. The approach in this patch, in
|
||||
conjunction with "PCI: aardvark: allow to specify link capability" patch
|
||||
is less invasive, it only touches the affected board.
|
||||
|
||||
For the record, the iwlwifi and mt76 cards were not affected by this
|
||||
issue.
|
||||
|
||||
1. http://espressobin.net/forums/topic/which-pcie-wlan-cards-are-supported
|
||||
|
||||
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
||||
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
||||
@@ -46,6 +46,8 @@
|
||||
/* J9 */
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
+
|
||||
+ max-link-speed = <1>;
|
||||
};
|
||||
|
||||
/* J6 */
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
From c2a90025ad09d830c8d8ae69f485eac6aaaa2472 Mon Sep 17 00:00:00 2001
|
||||
From: Quentin Schulz <quentin.schulz@bootlin.com>
|
||||
Date: Thu, 4 Oct 2018 14:22:03 +0200
|
||||
Subject: [PATCH] phy: add QSGMII and PCIE modes
|
||||
|
||||
Prepare for upcoming phys that'll handle QSGMII or PCIe.
|
||||
|
||||
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
|
||||
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
|
||||
Signed-off-by: David S. Miller <davem@davemloft.net>
|
||||
---
|
||||
include/linux/phy/phy.h | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/include/linux/phy/phy.h
|
||||
+++ b/include/linux/phy/phy.h
|
||||
@@ -37,9 +37,11 @@ enum phy_mode {
|
||||
PHY_MODE_USB_OTG,
|
||||
PHY_MODE_SGMII,
|
||||
PHY_MODE_2500SGMII,
|
||||
+ PHY_MODE_QSGMII,
|
||||
PHY_MODE_10GKR,
|
||||
PHY_MODE_UFS_HS_A,
|
||||
PHY_MODE_UFS_HS_B,
|
||||
+ PHY_MODE_PCIE,
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
From 2af8caeee47846a84bc96abc3a72f7c991153040 Mon Sep 17 00:00:00 2001
|
||||
From: Grygorii Strashko <grygorii.strashko@ti.com>
|
||||
Date: Mon, 19 Nov 2018 19:24:21 -0600
|
||||
Subject: [PATCH] phy: core: add PHY_MODE_ETHERNET
|
||||
|
||||
Add new PHY's mode to be used by Ethernet PHY interface drivers or
|
||||
multipurpose PHYs like serdes. It will be reused in further changes.
|
||||
|
||||
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
|
||||
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
|
||||
---
|
||||
include/linux/phy/phy.h | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/include/linux/phy/phy.h
|
||||
+++ b/include/linux/phy/phy.h
|
||||
@@ -42,6 +42,7 @@ enum phy_mode {
|
||||
PHY_MODE_UFS_HS_A,
|
||||
PHY_MODE_UFS_HS_B,
|
||||
PHY_MODE_PCIE,
|
||||
+ PHY_MODE_ETHERNET,
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
From e1706720408e72fb883f6b151c2b3b23d8e7e5b2 Mon Sep 17 00:00:00 2001
|
||||
From: John Hubbard <jhubbard@nvidia.com>
|
||||
Date: Sat, 12 Jan 2019 17:29:09 -0800
|
||||
Subject: [PATCH] phy: fix build breakage: add PHY_MODE_SATA
|
||||
|
||||
Commit 49e54187ae0b ("ata: libahci_platform: comply to PHY framework") uses
|
||||
the PHY_MODE_SATA, but that enum had not yet been added. This caused a
|
||||
build failure for me, with today's linux.git.
|
||||
|
||||
Also, there is a potentially conflicting (mis-named) PHY_MODE_SATA, hiding
|
||||
in the Marvell Berlin SATA PHY driver.
|
||||
|
||||
Fix the build by:
|
||||
|
||||
1) Renaming Marvell's defined value to a more scoped name,
|
||||
in order to avoid any potential conflicts: PHY_BERLIN_MODE_SATA.
|
||||
|
||||
2) Adding the missing enum, which was going to be added anyway as part
|
||||
of [1].
|
||||
|
||||
[1] https://lkml.kernel.org/r/20190108163124.6409-3-miquel.raynal@bootlin.com
|
||||
|
||||
Fixes: 49e54187ae0b ("ata: libahci_platform: comply to PHY framework")
|
||||
|
||||
Signed-off-by: John Hubbard <jhubbard@nvidia.com>
|
||||
Acked-by: Jens Axboe <axboe@kernel.dk>
|
||||
Acked-by: Olof Johansson <olof@lixom.net>
|
||||
Cc: Grzegorz Jaszczyk <jaz@semihalf.com>
|
||||
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
|
||||
Cc: Hans de Goede <hdegoede@redhat.com>
|
||||
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
|
||||
---
|
||||
include/linux/phy/phy.h | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/include/linux/phy/phy.h
|
||||
+++ b/include/linux/phy/phy.h
|
||||
@@ -43,6 +43,7 @@ enum phy_mode {
|
||||
PHY_MODE_UFS_HS_B,
|
||||
PHY_MODE_PCIE,
|
||||
PHY_MODE_ETHERNET,
|
||||
+ PHY_MODE_SATA
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -0,0 +1,134 @@
|
|||
From 79a5a18aa9d1062205cdcfa183d4cd5241d1b8da Mon Sep 17 00:00:00 2001
|
||||
From: Grygorii Strashko <grygorii.strashko@ti.com>
|
||||
Date: Mon, 19 Nov 2018 19:24:20 -0600
|
||||
Subject: [PATCH] phy: core: rework phy_set_mode to accept phy mode and submode
|
||||
|
||||
Currently the attempt to add support for Ethernet interface mode PHY
|
||||
(MII/GMII/RGMII) will lead to the necessity of extending enum phy_mode and
|
||||
duplicate there values from phy_interface_t enum (or introduce more PHY
|
||||
callbacks) [1]. Both approaches are ineffective and would lead to fast
|
||||
bloating of enum phy_mode or struct phy_ops in the process of adding more
|
||||
PHYs for different subsystems which will make them unmaintainable.
|
||||
|
||||
As discussed in [1] the solution could be to introduce dual level PHYs mode
|
||||
configuration - PHY mode and PHY submode. The PHY mode will define generic
|
||||
PHY type (subsystem - PCIE/ETHERNET/USB_) while the PHY submode - subsystem
|
||||
specific interface mode. The last is usually already defined in
|
||||
corresponding subsystem headers (phy_interface_t for Ethernet, enum
|
||||
usb_device_speed for USB).
|
||||
|
||||
This patch is cumulative change which refactors PHY framework code to
|
||||
support dual level PHYs mode configuration - PHY mode and PHY submode. It
|
||||
extends .set_mode() callback to support additional parameter "int submode"
|
||||
and converts all corresponding PHY drivers to support new .set_mode()
|
||||
callback declaration.
|
||||
The new extended PHY API
|
||||
int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode)
|
||||
is introduced to support dual level PHYs mode configuration and existing
|
||||
phy_set_mode() API is converted to macros, so PHY framework consumers do
|
||||
not need to be changed (~21 matches).
|
||||
|
||||
[1] http://lkml.kernel.org/r/d63588f6-9ab0-848a-5ad4-8073143bd95d@ti.com
|
||||
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
|
||||
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
|
||||
---
|
||||
drivers/phy/allwinner/phy-sun4i-usb.c | 3 ++-
|
||||
drivers/phy/amlogic/phy-meson-gxl-usb2.c | 5 +++--
|
||||
drivers/phy/amlogic/phy-meson-gxl-usb3.c | 5 +++--
|
||||
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 3 ++-
|
||||
drivers/phy/mediatek/phy-mtk-tphy.c | 2 +-
|
||||
drivers/phy/mediatek/phy-mtk-xsphy.c | 2 +-
|
||||
drivers/phy/mscc/phy-ocelot-serdes.c | 2 +-
|
||||
drivers/phy/phy-core.c | 6 +++---
|
||||
drivers/phy/qualcomm/phy-qcom-qmp.c | 3 ++-
|
||||
drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 ++-
|
||||
drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.c | 3 ++-
|
||||
drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c | 3 ++-
|
||||
drivers/phy/qualcomm/phy-qcom-usb-hs.c | 3 ++-
|
||||
drivers/phy/ti/phy-da8xx-usb.c | 3 ++-
|
||||
drivers/phy/ti/phy-tusb1210.c | 2 +-
|
||||
include/linux/phy/phy.h | 13 ++++++++++---
|
||||
16 files changed, 39 insertions(+), 22 deletions(-)
|
||||
|
||||
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
|
||||
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
|
||||
@@ -512,7 +512,8 @@ static int mvebu_comphy_power_on(struct
|
||||
return ret;
|
||||
}
|
||||
|
||||
-static int mvebu_comphy_set_mode(struct phy *phy, enum phy_mode mode)
|
||||
+static int mvebu_comphy_set_mode(struct phy *phy,
|
||||
+ enum phy_mode mode, int submode)
|
||||
{
|
||||
struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
|
||||
|
||||
--- a/drivers/phy/phy-core.c
|
||||
+++ b/drivers/phy/phy-core.c
|
||||
@@ -360,7 +360,7 @@ int phy_power_off(struct phy *phy)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(phy_power_off);
|
||||
|
||||
-int phy_set_mode(struct phy *phy, enum phy_mode mode)
|
||||
+int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode)
|
||||
{
|
||||
int ret;
|
||||
|
||||
@@ -368,14 +368,14 @@ int phy_set_mode(struct phy *phy, enum p
|
||||
return 0;
|
||||
|
||||
mutex_lock(&phy->mutex);
|
||||
- ret = phy->ops->set_mode(phy, mode);
|
||||
+ ret = phy->ops->set_mode(phy, mode, submode);
|
||||
if (!ret)
|
||||
phy->attrs.mode = mode;
|
||||
mutex_unlock(&phy->mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
-EXPORT_SYMBOL_GPL(phy_set_mode);
|
||||
+EXPORT_SYMBOL_GPL(phy_set_mode_ext);
|
||||
|
||||
int phy_reset(struct phy *phy)
|
||||
{
|
||||
--- a/include/linux/phy/phy.h
|
||||
+++ b/include/linux/phy/phy.h
|
||||
@@ -62,7 +62,7 @@ struct phy_ops {
|
||||
int (*exit)(struct phy *phy);
|
||||
int (*power_on)(struct phy *phy);
|
||||
int (*power_off)(struct phy *phy);
|
||||
- int (*set_mode)(struct phy *phy, enum phy_mode mode);
|
||||
+ int (*set_mode)(struct phy *phy, enum phy_mode mode, int submode);
|
||||
int (*reset)(struct phy *phy);
|
||||
int (*calibrate)(struct phy *phy);
|
||||
struct module *owner;
|
||||
@@ -166,7 +166,10 @@ int phy_init(struct phy *phy);
|
||||
int phy_exit(struct phy *phy);
|
||||
int phy_power_on(struct phy *phy);
|
||||
int phy_power_off(struct phy *phy);
|
||||
-int phy_set_mode(struct phy *phy, enum phy_mode mode);
|
||||
+int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode);
|
||||
+#define phy_set_mode(phy, mode) \
|
||||
+ phy_set_mode_ext(phy, mode, 0)
|
||||
+
|
||||
static inline enum phy_mode phy_get_mode(struct phy *phy)
|
||||
{
|
||||
return phy->attrs.mode;
|
||||
@@ -280,13 +283,17 @@ static inline int phy_power_off(struct p
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
-static inline int phy_set_mode(struct phy *phy, enum phy_mode mode)
|
||||
+static inline int phy_set_mode_ext(struct phy *phy, enum phy_mode mode,
|
||||
+ int submode)
|
||||
{
|
||||
if (!phy)
|
||||
return 0;
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
+#define phy_set_mode(phy, mode) \
|
||||
+ phy_set_mode_ext(phy, mode, 0)
|
||||
+
|
||||
static inline enum phy_mode phy_get_mode(struct phy *phy)
|
||||
{
|
||||
return PHY_MODE_INVALID;
|
||||
|
|
@ -0,0 +1,381 @@
|
|||
From 9695375a3f4a604406f2e61f2b735eca1de931ed Mon Sep 17 00:00:00 2001
|
||||
From: Miquel Raynal <miquel.raynal@bootlin.com>
|
||||
Date: Tue, 8 Jan 2019 17:31:20 +0100
|
||||
Subject: [PATCH] phy: add A3700 COMPHY support
|
||||
|
||||
Add a driver to support COMPHY, a hardware block providing shared
|
||||
serdes PHYs on Marvell Armada 3700. This driver uses SMC calls and
|
||||
rely on having an up-to-date firmware.
|
||||
|
||||
SATA, PCie and USB3 host mode have been tested successfully with an
|
||||
ESPRESSObin. (HS)SGMII mode cannot be tested with this platform.
|
||||
|
||||
Evan worked on the original driver structure and Grzegorz on the SMC
|
||||
calls rework. The structure of this driver has been copied from
|
||||
Antoine Tenart work on CP110 COMPHY driver.
|
||||
|
||||
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
|
||||
Co-developed-by: Evan Wang <xswang@marvell.com>
|
||||
Signed-off-by: Evan Wang <xswang@marvell.com>
|
||||
Co-developed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
|
||||
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
|
||||
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
|
||||
---
|
||||
drivers/phy/marvell/Kconfig | 12 +
|
||||
drivers/phy/marvell/Makefile | 1 +
|
||||
drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 318 +++++++++++++++++++++++++++
|
||||
3 files changed, 331 insertions(+)
|
||||
create mode 100644 drivers/phy/marvell/phy-mvebu-a3700-comphy.c
|
||||
|
||||
--- a/drivers/phy/marvell/Kconfig
|
||||
+++ b/drivers/phy/marvell/Kconfig
|
||||
@@ -21,6 +21,18 @@ config PHY_BERLIN_USB
|
||||
help
|
||||
Enable this to support the USB PHY on Marvell Berlin SoCs.
|
||||
|
||||
+config PHY_MVEBU_A3700_COMPHY
|
||||
+ tristate "Marvell A3700 comphy driver"
|
||||
+ depends on ARCH_MVEBU || COMPILE_TEST
|
||||
+ depends on OF
|
||||
+ depends on HAVE_ARM_SMCCC
|
||||
+ default y
|
||||
+ select GENERIC_PHY
|
||||
+ help
|
||||
+ This driver allows to control the comphy, a hardware block providing
|
||||
+ shared serdes PHYs on Marvell Armada 3700. Its serdes lanes can be
|
||||
+ used by various controllers: Ethernet, SATA, USB3, PCIe.
|
||||
+
|
||||
config PHY_MVEBU_CP110_COMPHY
|
||||
tristate "Marvell CP110 comphy driver"
|
||||
depends on ARCH_MVEBU || COMPILE_TEST
|
||||
--- a/drivers/phy/marvell/Makefile
|
||||
+++ b/drivers/phy/marvell/Makefile
|
||||
@@ -2,6 +2,7 @@
|
||||
obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY) += phy-armada375-usb2.o
|
||||
obj-$(CONFIG_PHY_BERLIN_SATA) += phy-berlin-sata.o
|
||||
obj-$(CONFIG_PHY_BERLIN_USB) += phy-berlin-usb.o
|
||||
+obj-$(CONFIG_PHY_MVEBU_A3700_COMPHY) += phy-mvebu-a3700-comphy.o
|
||||
obj-$(CONFIG_PHY_MVEBU_CP110_COMPHY) += phy-mvebu-cp110-comphy.o
|
||||
obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
|
||||
obj-$(CONFIG_PHY_PXA_28NM_HSIC) += phy-pxa-28nm-hsic.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
|
||||
@@ -0,0 +1,318 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0
|
||||
+/*
|
||||
+ * Copyright (C) 2018 Marvell
|
||||
+ *
|
||||
+ * Authors:
|
||||
+ * Evan Wang <xswang@marvell.com>
|
||||
+ * Miquèl Raynal <miquel.raynal@bootlin.com>
|
||||
+ *
|
||||
+ * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
|
||||
+ * SMC call initial support done by Grzegorz Jaszczyk.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/arm-smccc.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/iopoll.h>
|
||||
+#include <linux/mfd/syscon.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/phy.h>
|
||||
+#include <linux/phy/phy.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+
|
||||
+#define MVEBU_A3700_COMPHY_LANES 3
|
||||
+#define MVEBU_A3700_COMPHY_PORTS 2
|
||||
+
|
||||
+/* COMPHY Fast SMC function identifiers */
|
||||
+#define COMPHY_SIP_POWER_ON 0x82000001
|
||||
+#define COMPHY_SIP_POWER_OFF 0x82000002
|
||||
+#define COMPHY_SIP_PLL_LOCK 0x82000003
|
||||
+
|
||||
+#define COMPHY_FW_MODE_SATA 0x1
|
||||
+#define COMPHY_FW_MODE_SGMII 0x2
|
||||
+#define COMPHY_FW_MODE_HS_SGMII 0x3
|
||||
+#define COMPHY_FW_MODE_USB3H 0x4
|
||||
+#define COMPHY_FW_MODE_USB3D 0x5
|
||||
+#define COMPHY_FW_MODE_PCIE 0x6
|
||||
+#define COMPHY_FW_MODE_RXAUI 0x7
|
||||
+#define COMPHY_FW_MODE_XFI 0x8
|
||||
+#define COMPHY_FW_MODE_SFI 0x9
|
||||
+#define COMPHY_FW_MODE_USB3 0xa
|
||||
+
|
||||
+#define COMPHY_FW_SPEED_1_25G 0 /* SGMII 1G */
|
||||
+#define COMPHY_FW_SPEED_2_5G 1
|
||||
+#define COMPHY_FW_SPEED_3_125G 2 /* SGMII 2.5G */
|
||||
+#define COMPHY_FW_SPEED_5G 3
|
||||
+#define COMPHY_FW_SPEED_5_15625G 4 /* XFI 5G */
|
||||
+#define COMPHY_FW_SPEED_6G 5
|
||||
+#define COMPHY_FW_SPEED_10_3125G 6 /* XFI 10G */
|
||||
+#define COMPHY_FW_SPEED_MAX 0x3F
|
||||
+
|
||||
+#define COMPHY_FW_MODE(mode) ((mode) << 12)
|
||||
+#define COMPHY_FW_NET(mode, idx, speed) (COMPHY_FW_MODE(mode) | \
|
||||
+ ((idx) << 8) | \
|
||||
+ ((speed) << 2))
|
||||
+#define COMPHY_FW_PCIE(mode, idx, speed, width) (COMPHY_FW_NET(mode, idx, speed) | \
|
||||
+ ((width) << 18))
|
||||
+
|
||||
+struct mvebu_a3700_comphy_conf {
|
||||
+ unsigned int lane;
|
||||
+ enum phy_mode mode;
|
||||
+ int submode;
|
||||
+ unsigned int port;
|
||||
+ u32 fw_mode;
|
||||
+};
|
||||
+
|
||||
+#define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode, _port, _fw) \
|
||||
+ { \
|
||||
+ .lane = _lane, \
|
||||
+ .mode = _mode, \
|
||||
+ .submode = _smode, \
|
||||
+ .port = _port, \
|
||||
+ .fw_mode = _fw, \
|
||||
+ }
|
||||
+
|
||||
+#define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode, _port, _fw) \
|
||||
+ MVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA, _port, _fw)
|
||||
+
|
||||
+#define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode, _port, _fw) \
|
||||
+ MVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode, _port, _fw)
|
||||
+
|
||||
+static const struct mvebu_a3700_comphy_conf mvebu_a3700_comphy_modes[] = {
|
||||
+ /* lane 0 */
|
||||
+ MVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS, 0,
|
||||
+ COMPHY_FW_MODE_USB3H),
|
||||
+ MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII, 1,
|
||||
+ COMPHY_FW_MODE_SGMII),
|
||||
+ MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX, 1,
|
||||
+ COMPHY_FW_MODE_HS_SGMII),
|
||||
+ /* lane 1 */
|
||||
+ MVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE, 0,
|
||||
+ COMPHY_FW_MODE_PCIE),
|
||||
+ MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII, 0,
|
||||
+ COMPHY_FW_MODE_SGMII),
|
||||
+ MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX, 0,
|
||||
+ COMPHY_FW_MODE_HS_SGMII),
|
||||
+ /* lane 2 */
|
||||
+ MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA, 0,
|
||||
+ COMPHY_FW_MODE_SATA),
|
||||
+ MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS, 0,
|
||||
+ COMPHY_FW_MODE_USB3H),
|
||||
+};
|
||||
+
|
||||
+struct mvebu_a3700_comphy_lane {
|
||||
+ struct device *dev;
|
||||
+ unsigned int id;
|
||||
+ enum phy_mode mode;
|
||||
+ int submode;
|
||||
+ int port;
|
||||
+};
|
||||
+
|
||||
+static int mvebu_a3700_comphy_smc(unsigned long function, unsigned long lane,
|
||||
+ unsigned long mode)
|
||||
+{
|
||||
+ struct arm_smccc_res res;
|
||||
+
|
||||
+ arm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res);
|
||||
+
|
||||
+ return res.a0;
|
||||
+}
|
||||
+
|
||||
+static int mvebu_a3700_comphy_get_fw_mode(int lane, int port,
|
||||
+ enum phy_mode mode,
|
||||
+ int submode)
|
||||
+{
|
||||
+ int i, n = ARRAY_SIZE(mvebu_a3700_comphy_modes);
|
||||
+
|
||||
+ /* Unused PHY mux value is 0x0 */
|
||||
+ if (mode == PHY_MODE_INVALID)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ for (i = 0; i < n; i++) {
|
||||
+ if (mvebu_a3700_comphy_modes[i].lane == lane &&
|
||||
+ mvebu_a3700_comphy_modes[i].port == port &&
|
||||
+ mvebu_a3700_comphy_modes[i].mode == mode &&
|
||||
+ mvebu_a3700_comphy_modes[i].submode == submode)
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ if (i == n)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ return mvebu_a3700_comphy_modes[i].fw_mode;
|
||||
+}
|
||||
+
|
||||
+static int mvebu_a3700_comphy_set_mode(struct phy *phy, enum phy_mode mode,
|
||||
+ int submode)
|
||||
+{
|
||||
+ struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
|
||||
+ int fw_mode;
|
||||
+
|
||||
+ if (submode == PHY_INTERFACE_MODE_1000BASEX)
|
||||
+ submode = PHY_INTERFACE_MODE_SGMII;
|
||||
+
|
||||
+ fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port, mode,
|
||||
+ submode);
|
||||
+ if (fw_mode < 0) {
|
||||
+ dev_err(lane->dev, "invalid COMPHY mode\n");
|
||||
+ return fw_mode;
|
||||
+ }
|
||||
+
|
||||
+ /* Just remember the mode, ->power_on() will do the real setup */
|
||||
+ lane->mode = mode;
|
||||
+ lane->submode = submode;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int mvebu_a3700_comphy_power_on(struct phy *phy)
|
||||
+{
|
||||
+ struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
|
||||
+ u32 fw_param;
|
||||
+ int fw_mode;
|
||||
+
|
||||
+ fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port,
|
||||
+ lane->mode, lane->submode);
|
||||
+ if (fw_mode < 0) {
|
||||
+ dev_err(lane->dev, "invalid COMPHY mode\n");
|
||||
+ return fw_mode;
|
||||
+ }
|
||||
+
|
||||
+ switch (lane->mode) {
|
||||
+ case PHY_MODE_USB_HOST_SS:
|
||||
+ dev_dbg(lane->dev, "set lane %d to USB3 host mode\n", lane->id);
|
||||
+ fw_param = COMPHY_FW_MODE(fw_mode);
|
||||
+ break;
|
||||
+ case PHY_MODE_SATA:
|
||||
+ dev_dbg(lane->dev, "set lane %d to SATA mode\n", lane->id);
|
||||
+ fw_param = COMPHY_FW_MODE(fw_mode);
|
||||
+ break;
|
||||
+ case PHY_MODE_ETHERNET:
|
||||
+ switch (lane->submode) {
|
||||
+ case PHY_INTERFACE_MODE_SGMII:
|
||||
+ dev_dbg(lane->dev, "set lane %d to SGMII mode\n",
|
||||
+ lane->id);
|
||||
+ fw_param = COMPHY_FW_NET(fw_mode, lane->port,
|
||||
+ COMPHY_FW_SPEED_1_25G);
|
||||
+ break;
|
||||
+ case PHY_INTERFACE_MODE_2500BASEX:
|
||||
+ dev_dbg(lane->dev, "set lane %d to HS SGMII mode\n",
|
||||
+ lane->id);
|
||||
+ fw_param = COMPHY_FW_NET(fw_mode, lane->port,
|
||||
+ COMPHY_FW_SPEED_3_125G);
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_err(lane->dev, "unsupported PHY submode (%d)\n",
|
||||
+ lane->submode);
|
||||
+ return -ENOTSUPP;
|
||||
+ }
|
||||
+ break;
|
||||
+ case PHY_MODE_PCIE:
|
||||
+ dev_dbg(lane->dev, "set lane %d to PCIe mode\n", lane->id);
|
||||
+ fw_param = COMPHY_FW_PCIE(fw_mode, lane->port,
|
||||
+ COMPHY_FW_SPEED_5G,
|
||||
+ phy->attrs.bus_width);
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_err(lane->dev, "unsupported PHY mode (%d)\n", lane->mode);
|
||||
+ return -ENOTSUPP;
|
||||
+ }
|
||||
+
|
||||
+ return mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_ON, lane->id, fw_param);
|
||||
+}
|
||||
+
|
||||
+static int mvebu_a3700_comphy_power_off(struct phy *phy)
|
||||
+{
|
||||
+ struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
|
||||
+
|
||||
+ return mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_OFF, lane->id, 0);
|
||||
+}
|
||||
+
|
||||
+static const struct phy_ops mvebu_a3700_comphy_ops = {
|
||||
+ .power_on = mvebu_a3700_comphy_power_on,
|
||||
+ .power_off = mvebu_a3700_comphy_power_off,
|
||||
+ .set_mode = mvebu_a3700_comphy_set_mode,
|
||||
+ .owner = THIS_MODULE,
|
||||
+};
|
||||
+
|
||||
+static struct phy *mvebu_a3700_comphy_xlate(struct device *dev,
|
||||
+ struct of_phandle_args *args)
|
||||
+{
|
||||
+ struct mvebu_a3700_comphy_lane *lane;
|
||||
+ struct phy *phy;
|
||||
+
|
||||
+ if (WARN_ON(args->args[0] >= MVEBU_A3700_COMPHY_PORTS))
|
||||
+ return ERR_PTR(-EINVAL);
|
||||
+
|
||||
+ phy = of_phy_simple_xlate(dev, args);
|
||||
+ if (IS_ERR(phy))
|
||||
+ return phy;
|
||||
+
|
||||
+ lane = phy_get_drvdata(phy);
|
||||
+ lane->port = args->args[0];
|
||||
+
|
||||
+ return phy;
|
||||
+}
|
||||
+
|
||||
+static int mvebu_a3700_comphy_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct phy_provider *provider;
|
||||
+ struct device_node *child;
|
||||
+
|
||||
+ for_each_available_child_of_node(pdev->dev.of_node, child) {
|
||||
+ struct mvebu_a3700_comphy_lane *lane;
|
||||
+ struct phy *phy;
|
||||
+ int ret;
|
||||
+ u32 lane_id;
|
||||
+
|
||||
+ ret = of_property_read_u32(child, "reg", &lane_id);
|
||||
+ if (ret < 0) {
|
||||
+ dev_err(&pdev->dev, "missing 'reg' property (%d)\n",
|
||||
+ ret);
|
||||
+ continue;
|
||||
+ }
|
||||
+
|
||||
+ if (lane_id >= MVEBU_A3700_COMPHY_LANES) {
|
||||
+ dev_err(&pdev->dev, "invalid 'reg' property\n");
|
||||
+ continue;
|
||||
+ }
|
||||
+
|
||||
+ lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL);
|
||||
+ if (!lane)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ phy = devm_phy_create(&pdev->dev, child,
|
||||
+ &mvebu_a3700_comphy_ops);
|
||||
+ if (IS_ERR(phy))
|
||||
+ return PTR_ERR(phy);
|
||||
+
|
||||
+ lane->dev = &pdev->dev;
|
||||
+ lane->mode = PHY_MODE_INVALID;
|
||||
+ lane->submode = PHY_INTERFACE_MODE_NA;
|
||||
+ lane->id = lane_id;
|
||||
+ lane->port = -1;
|
||||
+ phy_set_drvdata(phy, lane);
|
||||
+ }
|
||||
+
|
||||
+ provider = devm_of_phy_provider_register(&pdev->dev,
|
||||
+ mvebu_a3700_comphy_xlate);
|
||||
+ return PTR_ERR_OR_ZERO(provider);
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id mvebu_a3700_comphy_of_match_table[] = {
|
||||
+ { .compatible = "marvell,comphy-a3700" },
|
||||
+ { },
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, mvebu_a3700_comphy_of_match_table);
|
||||
+
|
||||
+static struct platform_driver mvebu_a3700_comphy_driver = {
|
||||
+ .probe = mvebu_a3700_comphy_probe,
|
||||
+ .driver = {
|
||||
+ .name = "mvebu-a3700-comphy",
|
||||
+ .of_match_table = mvebu_a3700_comphy_of_match_table,
|
||||
+ },
|
||||
+};
|
||||
+module_platform_driver(mvebu_a3700_comphy_driver);
|
||||
+
|
||||
+MODULE_AUTHOR("Miquèl Raynal <miquel.raynal@bootlin.com>");
|
||||
+MODULE_DESCRIPTION("Common PHY driver for A3700");
|
||||
+MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
From 2ef303f0fe44feee4a3ca8bd62fca86c105927d2 Mon Sep 17 00:00:00 2001
|
||||
From: Miquel Raynal <miquel.raynal@bootlin.com>
|
||||
Date: Tue, 8 Jan 2019 17:31:24 +0100
|
||||
Subject: [PATCH] arm64: dts: marvell: armada-37xx: declare the COMPHY
|
||||
node
|
||||
|
||||
Describe the A3700 COMPHY node. It has three PHYs that can be
|
||||
configured as follow:
|
||||
* PCIe or GbE
|
||||
* USB3 or GbE
|
||||
* SATA or USB3
|
||||
Each of them has its own memory area.
|
||||
|
||||
Suggested-by: Grzegorz Jaszczyk <jaz@semihalf.com>
|
||||
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
|
||||
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
|
||||
---
|
||||
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 29 ++++++++++++++++++++++++++++
|
||||
1 file changed, 29 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
||||
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
||||
@@ -235,6 +235,35 @@
|
||||
reg = <0x14000 0x60>;
|
||||
};
|
||||
|
||||
+ comphy: phy@18300 {
|
||||
+ compatible = "marvell,comphy-a3700";
|
||||
+ reg = <0x18300 0x300>,
|
||||
+ <0x1F000 0x400>,
|
||||
+ <0x5C000 0x400>,
|
||||
+ <0xe0178 0x8>;
|
||||
+ reg-names = "comphy",
|
||||
+ "lane1_pcie_gbe",
|
||||
+ "lane0_usb3_gbe",
|
||||
+ "lane2_sata_usb3";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ comphy0: phy@0 {
|
||||
+ reg = <0>;
|
||||
+ #phy-cells = <1>;
|
||||
+ };
|
||||
+
|
||||
+ comphy1: phy@1 {
|
||||
+ reg = <1>;
|
||||
+ #phy-cells = <1>;
|
||||
+ };
|
||||
+
|
||||
+ comphy2: phy@2 {
|
||||
+ reg = <2>;
|
||||
+ #phy-cells = <1>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
pinctrl_sb: pinctrl@18800 {
|
||||
compatible = "marvell,armada3710-sb-pinctrl",
|
||||
"syscon", "simple-mfd";
|
||||
|
|
@ -7,9 +7,9 @@ index ea9d49f2a911..d80da8f5d82d 100644
|
|||
dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb
|
||||
+dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobinv7.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-turris-mox.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-uDPU.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb
|
||||
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobinv7.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobinv7.dts
|
||||
new file mode 100644
|
||||
index 000000000000..6385b2488e45
|
||||
|
|
|
|||
|
|
@ -1,91 +0,0 @@
|
|||
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
||||
index cd5fbfa38..a81391164 100644
|
||||
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
||||
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
||||
@@ -41,6 +41,16 @@
|
||||
3300000 0x0>;
|
||||
enable-active-high;
|
||||
};
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+
|
||||
+ red {
|
||||
+ label = "espressobin:red:usr";
|
||||
+ gpios = <&gpionb 2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
};
|
||||
|
||||
/* J9 */
|
||||
@@ -95,19 +105,35 @@
|
||||
|
||||
flash@0 {
|
||||
reg = <0>;
|
||||
+ /*
|
||||
+ * Originally "winbond,w25q32dw", but since the manufacturer is known
|
||||
+ * to have replaced the part with "macronix,mx25u3235f" in some board
|
||||
+ * batches, just use the generic "jedec,spi-nor" and let the actual
|
||||
+ * chip type be probed. The partition table still depends on the chip
|
||||
+ * being 4 MiB in size.
|
||||
+ */
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <104000000>;
|
||||
m25p,fast-read;
|
||||
- };
|
||||
-};
|
||||
+ status = "okay";
|
||||
+
|
||||
+ partitions {
|
||||
+ compatible = "fixed-partitions";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
|
||||
-&sdhci0 {
|
||||
- non-removable;
|
||||
- bus-width = <8>;
|
||||
- mmc-ddr-1_8v;
|
||||
- mmc-hs400-1_8v;
|
||||
- marvell,pad-type = "fixed-1-8v";
|
||||
- status = "okay";
|
||||
+ partition@0 {
|
||||
+ label = "uboot";
|
||||
+ reg = <0 0x3f0000>;
|
||||
+ };
|
||||
+
|
||||
+ partition@180000 {
|
||||
+ label = "ubootenv";
|
||||
+ reg = <0x3f0000 0x10000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ };
|
||||
};
|
||||
|
||||
/* Exported on the micro USB connector J5 through an FTDI */
|
||||
@@ -137,11 +163,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
-/* J8 */
|
||||
-&usb2 {
|
||||
- status = "okay";
|
||||
-};
|
||||
-
|
||||
&mdio {
|
||||
switch0: switch0@1 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
@@ -199,12 +220,6 @@
|
||||
switch0phy2: switch0phy2@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
-
|
||||
- partition@190000 {
|
||||
- label = "Linux";
|
||||
- reg = <0x190000 0xDF0000>;
|
||||
- };
|
||||
-
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
diff --git linux-4.18.7/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
||||
index 3ab25ad40..0f99e751c 100644
|
||||
--- linux-4.18.7/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
||||
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
||||
@@ -41,6 +41,15 @@
|
||||
3300000 0x0>;
|
||||
enable-active-high;
|
||||
};
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+
|
||||
+ red {
|
||||
+ label = "espressobin:red:usr";
|
||||
+ gpios = <&gpionb 2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
/* J9 */
|
||||
@@ -68,9 +77,17 @@
|
||||
|
||||
flash@0 {
|
||||
reg = <0>;
|
||||
- compatible = "winbond,w25q32dw", "jedec,spi-flash";
|
||||
+ /*
|
||||
+ * Originally "winbond,w25q32dw", but since the manufacturer is known
|
||||
+ * to have replaced the part with "macronix,mx25u3235f" in some board
|
||||
+ * batches, just use the generic "jedec,spi-nor" and let the actual
|
||||
+ * chip type be probed. The partition table still depends on the chip
|
||||
+ * being 4 MiB in size.
|
||||
+ */
|
||||
+ compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <104000000>;
|
||||
m25p,fast-read;
|
||||
+ status = "okay";
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
@@ -79,12 +96,12 @@
|
||||
|
||||
partition@0 {
|
||||
label = "uboot";
|
||||
- reg = <0 0x180000>;
|
||||
+ reg = <0 0x3f0000>;
|
||||
};
|
||||
|
||||
- partition@180000 {
|
||||
+ partition@3f0000 {
|
||||
label = "ubootenv";
|
||||
- reg = <0x180000 0x10000>;
|
||||
+ reg = <0x3f0000 0x10000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
diff --git a/drivers/cpufreq/armada-37xx-cpufreq.c b/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
index 75491fc84..c2adf380b 100644
|
||||
--- a/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
+++ b/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
@@ -162,11 +162,25 @@ static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
|
||||
}
|
||||
|
||||
/*
|
||||
- * Set cpu clock source, for all the level we keep the same
|
||||
- * clock source that the one already configured. For this one
|
||||
- * we need to use the clock framework
|
||||
- */
|
||||
+ * Set CPU clock source, for all the level we keep the same
|
||||
+ * clock source that the one already configured with DVS
|
||||
+ * disabled. For this one we need to use the clock framewor
|
||||
+ */
|
||||
parent = clk_get_parent(clk);
|
||||
+
|
||||
+ /*
|
||||
+ * Unset parent clock to force the clock framework setting again
|
||||
+ * the clock parent
|
||||
+ */
|
||||
+ clk_set_parent(clk, NULL);
|
||||
+
|
||||
+ /*
|
||||
+ * For the Armada 37xx CPU clocks, setting the parent will
|
||||
+ * actually configure the parent when DVFS is enabled. At
|
||||
+ * hardware level it will be a different register from the one
|
||||
+ * read when doing clk_get_parent that will be set with
|
||||
+ * clk_set_parent.
|
||||
+ */
|
||||
clk_set_parent(clk, parent);
|
||||
}
|
||||
|
||||
@@ -359,11 +373,11 @@ static int __init armada37xx_cpufreq_driver_init(void)
|
||||
struct armada_37xx_dvfs *dvfs;
|
||||
struct platform_device *pdev;
|
||||
unsigned long freq;
|
||||
- unsigned int cur_frequency;
|
||||
+ unsigned int cur_frequency, base_frequency;
|
||||
struct regmap *nb_pm_base, *avs_base;
|
||||
struct device *cpu_dev;
|
||||
int load_lvl, ret;
|
||||
- struct clk *clk;
|
||||
+ struct clk *clk, *parent;
|
||||
|
||||
nb_pm_base =
|
||||
syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
|
||||
@@ -399,6 +413,22 @@ static int __init armada37xx_cpufreq_driver_init(void)
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
|
||||
+ parent = clk_get_parent(clk);
|
||||
+ if (IS_ERR(parent)) {
|
||||
+ dev_err(cpu_dev, "Cannot get parent clock for CPU0\n");
|
||||
+ clk_put(clk);
|
||||
+ return PTR_ERR(parent);
|
||||
+ }
|
||||
+
|
||||
+ /* Get parent CPU frequency */
|
||||
+ base_frequency = clk_get_rate(parent);
|
||||
+
|
||||
+ if (!base_frequency) {
|
||||
+ dev_err(cpu_dev, "Failed to get parent clock rate for CPU\n");
|
||||
+ clk_put(clk);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
/* Get nominal (current) CPU frequency */
|
||||
cur_frequency = clk_get_rate(clk);
|
||||
if (!cur_frequency) {
|
||||
@@ -431,7 +461,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
|
||||
for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
|
||||
load_lvl++) {
|
||||
unsigned long u_volt = avs_map[dvfs->avs[load_lvl]] * 1000;
|
||||
- freq = cur_frequency / dvfs->divider[load_lvl];
|
||||
+ freq = base_frequency / dvfs->divider[load_lvl];
|
||||
ret = dev_pm_opp_add(cpu_dev, freq, u_volt);
|
||||
if (ret)
|
||||
goto remove_opp;
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
|
||||
index a42a040..1754456
|
||||
--- a/drivers/pci/controller/pci-aardvark.c
|
||||
+++ b/drivers/pci/controller/pci-aardvark.c
|
||||
@@ -312,9 +312,10 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
|
||||
advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
|
||||
|
||||
/* Set GEN2 */
|
||||
+ /* Set GEN1 */
|
||||
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
|
||||
reg &= ~PCIE_GEN_SEL_MSK;
|
||||
- reg |= SPEED_GEN_2;
|
||||
+ reg |= SPEED_GEN_1;
|
||||
advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
|
||||
|
||||
/* Set lane X1 */
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
From 8fe9a4c4a024a6353e810a1dbb5e4bc78bff60a8 Mon Sep 17 00:00:00 2001
|
||||
From: FlashBurnGitHub <33546258+FlashBurnGitHub@users.noreply.github.com>
|
||||
Date: Wed, 6 Mar 2019 17:25:46 +0100
|
||||
Subject: [PATCH] Fix problem with cpu scaling not working
|
||||
|
||||
This fixes a problem that the cpu scaling is not working.
|
||||
|
||||
First one needs to first unset the parent clock, before setting the same old parent clock again. This solves the problem that the wrong TBG clock source was used for the cpu.
|
||||
|
||||
Also one needs to multiply the current cpu frequency with the used divider so that the right cpu frequency gets calculated when applying the dividers. This was need for a 600MHz final cpu frequency to work
|
||||
---
|
||||
drivers/cpufreq/armada-37xx-cpufreq.c | 11 ++++++++++-
|
||||
1 file changed, 10 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/cpufreq/armada-37xx-cpufreq.c b/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
index 75491fc841a6..5c744092f819 100644
|
||||
--- a/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
+++ b/drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
@@ -167,6 +167,11 @@ static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
|
||||
* we need to use the clock framework
|
||||
*/
|
||||
parent = clk_get_parent(clk);
|
||||
+
|
||||
+ /* Unset parent clock */
|
||||
+ clk_set_parent(clk, NULL);
|
||||
+
|
||||
+ /* set old parent; this triggers setting needed values for right CPU clock in hardware regs */
|
||||
clk_set_parent(clk, parent);
|
||||
}
|
||||
|
||||
@@ -360,6 +365,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
|
||||
struct platform_device *pdev;
|
||||
unsigned long freq;
|
||||
unsigned int cur_frequency;
|
||||
+ unsigned int base_frequency;
|
||||
struct regmap *nb_pm_base, *avs_base;
|
||||
struct device *cpu_dev;
|
||||
int load_lvl, ret;
|
||||
@@ -412,6 +418,9 @@ static int __init armada37xx_cpufreq_driver_init(void)
|
||||
clk_put(clk);
|
||||
return -EINVAL;
|
||||
}
|
||||
+
|
||||
+ /* Get base CPU frequency without divider */
|
||||
+ base_frequency = cur_frequency * dvfs->divider[ARMADA_37XX_DVFS_LOAD_0];
|
||||
|
||||
armada37xx_cpufreq_state = kmalloc(sizeof(*armada37xx_cpufreq_state),
|
||||
GFP_KERNEL);
|
||||
@@ -431,7 +440,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
|
||||
for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
|
||||
load_lvl++) {
|
||||
unsigned long u_volt = avs_map[dvfs->avs[load_lvl]] * 1000;
|
||||
- freq = cur_frequency / dvfs->divider[load_lvl];
|
||||
+ freq = base_frequency / dvfs->divider[load_lvl];
|
||||
ret = dev_pm_opp_add(cpu_dev, freq, u_volt);
|
||||
if (ret)
|
||||
goto remove_opp;
|
||||
39290
patch/kernel/mvebu64-current/general-aufs4.19-20181029.patch
Normal file
39290
patch/kernel/mvebu64-current/general-aufs4.19-20181029.patch
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,27 @@
|
|||
diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c
|
||||
index 3216e09..21bce28
|
||||
--- a/arch/arm64/mm/dma-mapping.c
|
||||
+++ b/arch/arm64/mm/dma-mapping.c
|
||||
@@ -44,7 +44,7 @@ static pgprot_t __get_dma_pgprot(unsigned long attrs, pgprot_t prot,
|
||||
|
||||
static struct gen_pool *atomic_pool;
|
||||
|
||||
-#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
|
||||
+#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_2M
|
||||
static size_t atomic_pool_size __initdata = DEFAULT_DMA_COHERENT_POOL_SIZE;
|
||||
|
||||
static int __init early_coherent_pool(char *p)
|
||||
|
||||
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
|
||||
index ada8eb2..8df220f
|
||||
--- a/arch/arm/mm/dma-mapping.c
|
||||
+++ b/arch/arm/mm/dma-mapping.c
|
||||
@@ -381,7 +381,7 @@ static void __dma_free_remap(void *cpu_addr, size_t size)
|
||||
VM_ARM_DMA_CONSISTENT | VM_USERMAP);
|
||||
}
|
||||
|
||||
-#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
|
||||
+#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_2M
|
||||
static struct gen_pool *atomic_pool __ro_after_init;
|
||||
|
||||
static size_t atomic_pool_size __initdata = DEFAULT_DMA_COHERENT_POOL_SIZE;
|
||||
Loading…
Add table
Reference in a new issue