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meson64: update patches and remove unused patches.

Browse source 
Signed-off-by: Zhang Ning <832666+zhangn1985@users.noreply.github.com>
This commit is contained in:
Zhang Ning 2019-11-27 10:37:05 +08:00
parent dac366f09f
commit 7243cadb72
8 changed files with 727 additions and 321 deletions
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455
patch/kernel/meson64-dev/1-0000-Revert-drm-meson-venc-use-proper-macros-instead-of-m.patch Normal file
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@ -0,0 +1,455 @@
From 2262dfd1cf2d47ed97c2276f6436f20f829cdd3a Mon Sep 17 00:00:00 2001
From: Zhang Ning <832666+zhangn1985@users.noreply.github.com>
Date: Tue, 26 Nov 2019 16:03:33 +0800
Subject: [PATCH] Revert "drm: meson: venc: use proper macros instead of magic
constants"
This reverts commit 7eef9e6104545e3aed75ac84129ab332e71b6557.
---
drivers/gpu/drm/meson/meson_registers.h | 51 --------
drivers/gpu/drm/meson/meson_venc.c | 155 +++++-------------------
drivers/gpu/drm/meson/meson_venc_cvbs.c | 3 +-
3 files changed, 32 insertions(+), 177 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h
index 05fce48ceee0..3c5ccfa755d9 100644
--- a/drivers/gpu/drm/meson/meson_registers.h
+++ b/drivers/gpu/drm/meson/meson_registers.h
@@ -735,25 +735,6 @@
#define VENC_UPSAMPLE_CTRL0 0x1b64
#define VENC_UPSAMPLE_CTRL1 0x1b65
#define VENC_UPSAMPLE_CTRL2 0x1b66
-#define VENC_UPSAMPLE_CTRL_F0_2_CLK_RATIO BIT(0)
-#define VENC_UPSAMPLE_CTRL_F1_EN BIT(5)
-#define VENC_UPSAMPLE_CTRL_F1_UPSAMPLE_EN BIT(6)
-#define VENC_UPSAMPLE_CTRL_INTERLACE_HIGH_LUMA (0x0 << 12)
-#define VENC_UPSAMPLE_CTRL_CVBS (0x1 << 12)
-#define VENC_UPSAMPLE_CTRL_S_VIDEO_LUMA (0x2 << 12)
-#define VENC_UPSAMPLE_CTRL_S_VIDEO_CHROMA (0x3 << 12)
-#define VENC_UPSAMPLE_CTRL_INTERLACE_PB (0x4 << 12)
-#define VENC_UPSAMPLE_CTRL_INTERLACE_PR (0x5 << 12)
-#define VENC_UPSAMPLE_CTRL_INTERLACE_R (0x6 << 12)
-#define VENC_UPSAMPLE_CTRL_INTERLACE_G (0x7 << 12)
-#define VENC_UPSAMPLE_CTRL_INTERLACE_B (0x8 << 12)
-#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_Y (0x9 << 12)
-#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_PB (0xa << 12)
-#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_PR (0xb << 12)
-#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_R (0xc << 12)
-#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_G (0xd << 12)
-#define VENC_UPSAMPLE_CTRL_PROGRESSIVE_B (0xe << 12)
-#define VENC_UPSAMPLE_CTRL_VDAC_TEST_VALUE (0xf << 12)
#define TCON_INVERT_CTL 0x1b67
#define VENC_VIDEO_PROG_MODE 0x1b68
#define VENC_ENCI_LINE 0x1b69
@@ -762,7 +743,6 @@
#define VENC_ENCP_PIXEL 0x1b6c
#define VENC_STATA 0x1b6d
#define VENC_INTCTRL 0x1b6e
-#define VENC_INTCTRL_ENCI_LNRST_INT_EN BIT(1)
#define VENC_INTFLAG 0x1b6f
#define VENC_VIDEO_TST_EN 0x1b70
#define VENC_VIDEO_TST_MDSEL 0x1b71
@@ -773,7 +753,6 @@
#define VENC_VIDEO_TST_CLRBAR_WIDTH 0x1b76
#define VENC_VIDEO_TST_VDCNT_STSET 0x1b77
#define VENC_VDAC_DACSEL0 0x1b78
-#define VENC_VDAC_SEL_ATV_DMD BIT(5)
#define VENC_VDAC_DACSEL1 0x1b79
#define VENC_VDAC_DACSEL2 0x1b7a
#define VENC_VDAC_DACSEL3 0x1b7b
@@ -794,7 +773,6 @@
#define VENC_VDAC_DAC5_GAINCTRL 0x1bfa
#define VENC_VDAC_DAC5_OFFSET 0x1bfb
#define VENC_VDAC_FIFO_CTRL 0x1bfc
-#define VENC_VDAC_FIFO_EN_ENCI_ENABLE BIT(13)
#define ENCL_TCON_INVERT_CTL 0x1bfd
#define ENCP_VIDEO_EN 0x1b80
#define ENCP_VIDEO_SYNC_MODE 0x1b81
@@ -810,7 +788,6 @@
#define ENCP_VIDEO_SYNC_OFFST 0x1b8b
#define ENCP_VIDEO_MACV_OFFST 0x1b8c
#define ENCP_VIDEO_MODE 0x1b8d
-#define ENCP_VIDEO_MODE_DE_V_HIGH BIT(14)
#define ENCP_VIDEO_MODE_ADV 0x1b8e
#define ENCP_DBG_PX_RST 0x1b90
#define ENCP_DBG_LN_RST 0x1b91
@@ -889,11 +866,6 @@
#define C656_FS_LNED 0x1be7
#define ENCI_VIDEO_MODE 0x1b00
#define ENCI_VIDEO_MODE_ADV 0x1b01
-#define ENCI_VIDEO_MODE_ADV_DMXMD(val) (val & 0x3)
-#define ENCI_VIDEO_MODE_ADV_VBICTL_LINE_17_22 BIT(2)
-#define ENCI_VIDEO_MODE_ADV_YBW_MEDIUM (0 << 4)
-#define ENCI_VIDEO_MODE_ADV_YBW_LOW (0x1 << 4)
-#define ENCI_VIDEO_MODE_ADV_YBW_HIGH (0x2 << 4)
#define ENCI_VIDEO_FSC_ADJ 0x1b02
#define ENCI_VIDEO_BRIGHT 0x1b03
#define ENCI_VIDEO_CONT 0x1b04
@@ -964,17 +936,13 @@
#define ENCI_DBG_MAXPX 0x1b4c
#define ENCI_DBG_MAXLN 0x1b4d
#define ENCI_MACV_MAX_AMP 0x1b50
-#define ENCI_MACV_MAX_AMP_ENABLE_CHANGE BIT(15)
-#define ENCI_MACV_MAX_AMP_VAL(val) (val & 0x83ff)
#define ENCI_MACV_PULSE_LO 0x1b51
#define ENCI_MACV_PULSE_HI 0x1b52
#define ENCI_MACV_BKP_MAX 0x1b53
#define ENCI_CFILT_CTRL 0x1b54
-#define ENCI_CFILT_CMPT_SEL_HIGH BIT(1)
#define ENCI_CFILT7 0x1b55
#define ENCI_YC_DELAY 0x1b56
#define ENCI_VIDEO_EN 0x1b57
-#define ENCI_VIDEO_EN_ENABLE BIT(0)
#define ENCI_DVI_HSO_BEGIN 0x1c00
#define ENCI_DVI_HSO_END 0x1c01
#define ENCI_DVI_VSO_BLINE_EVN 0x1c02
@@ -986,10 +954,6 @@
#define ENCI_DVI_VSO_END_EVN 0x1c08
#define ENCI_DVI_VSO_END_ODD 0x1c09
#define ENCI_CFILT_CTRL2 0x1c0a
-#define ENCI_CFILT_CMPT_CR_DLY(delay) (delay & 0xf)
-#define ENCI_CFILT_CMPT_CB_DLY(delay) ((delay & 0xf) << 4)
-#define ENCI_CFILT_CVBS_CR_DLY(delay) ((delay & 0xf) << 8)
-#define ENCI_CFILT_CVBS_CB_DLY(delay) ((delay & 0xf) << 12)
#define ENCI_DACSEL_0 0x1c0b
#define ENCI_DACSEL_1 0x1c0c
#define ENCP_DACSEL_0 0x1c0d
@@ -1004,8 +968,6 @@
#define ENCI_TST_CLRBAR_WIDTH 0x1c16
#define ENCI_TST_VDCNT_STSET 0x1c17
#define ENCI_VFIFO2VD_CTL 0x1c18
-#define ENCI_VFIFO2VD_CTL_ENABLE BIT(0)
-#define ENCI_VFIFO2VD_CTL_VD_SEL(val) ((val & 0xff) << 8)
#define ENCI_VFIFO2VD_PIXEL_START 0x1c19
#define ENCI_VFIFO2VD_PIXEL_END 0x1c1a
#define ENCI_VFIFO2VD_LINE_TOP_START 0x1c1b
@@ -1068,7 +1030,6 @@
#define VENC_VDAC_DAC5_FILT_CTRL0 0x1c56
#define VENC_VDAC_DAC5_FILT_CTRL1 0x1c57
#define VENC_VDAC_DAC0_FILT_CTRL0 0x1c58
-#define VENC_VDAC_DAC0_FILT_CTRL0_EN BIT(0)
#define VENC_VDAC_DAC0_FILT_CTRL1 0x1c59
#define VENC_VDAC_DAC1_FILT_CTRL0 0x1c5a
#define VENC_VDAC_DAC1_FILT_CTRL1 0x1c5b
@@ -1474,18 +1435,6 @@
#define VIU2_SEL_VENC_ENCP (2 << 2)
#define VIU2_SEL_VENC_ENCT (3 << 2)
#define VPU_HDMI_SETTING 0x271b
-#define VPU_HDMI_ENCI_DATA_TO_HDMI BIT(0)
-#define VPU_HDMI_ENCP_DATA_TO_HDMI BIT(1)
-#define VPU_HDMI_INV_HSYNC BIT(2)
-#define VPU_HDMI_INV_VSYNC BIT(3)
-#define VPU_HDMI_OUTPUT_CRYCB (0 << 5)
-#define VPU_HDMI_OUTPUT_YCBCR (1 << 5)
-#define VPU_HDMI_OUTPUT_YCRCB (2 << 5)
-#define VPU_HDMI_OUTPUT_CBCRY (3 << 5)
-#define VPU_HDMI_OUTPUT_CBYCR (4 << 5)
-#define VPU_HDMI_OUTPUT_CRCBY (5 << 5)
-#define VPU_HDMI_WR_RATE(rate) (((rate & 0x1f) - 1) << 8)
-#define VPU_HDMI_RD_RATE(rate) (((rate & 0x1f) - 1) << 12)
#define ENCI_INFO_READ 0x271c
#define ENCP_INFO_READ 0x271d
#define ENCT_INFO_READ 0x271e
diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c
index 4efd7864d5bf..5a4fab2221df 100644
--- a/drivers/gpu/drm/meson/meson_venc.c
+++ b/drivers/gpu/drm/meson/meson_venc.c
@@ -976,7 +976,6 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
unsigned int eof_lines;
unsigned int sof_lines;
unsigned int vsync_lines;
- u32 reg;
/* Use VENCI for 480i and 576i and double HDMI pixels */
if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
@@ -1049,11 +1048,8 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
unsigned int lines_f1;
/* CVBS Filter settings */
- writel_relaxed(ENCI_CFILT_CMPT_SEL_HIGH | 0x10,
- priv->io_base + _REG(ENCI_CFILT_CTRL));
- writel_relaxed(ENCI_CFILT_CMPT_CR_DLY(2) |
- ENCI_CFILT_CMPT_CB_DLY(1),
- priv->io_base + _REG(ENCI_CFILT_CTRL2));
+ writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL));
+ writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2));
/* Digital Video Select : Interlace, clk27 clk, external */
writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));
@@ -1075,9 +1071,8 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN));
/* Macrovision max amplitude change */
- writel_relaxed(ENCI_MACV_MAX_AMP_ENABLE_CHANGE |
- ENCI_MACV_MAX_AMP_VAL(vmode->enci.macv_max_amp),
- priv->io_base + _REG(ENCI_MACV_MAX_AMP));
+ writel_relaxed(vmode->enci.macv_max_amp,
+ priv->io_base + _REG(ENCI_MACV_MAX_AMP));
/* Video mode */
writel_relaxed(vmode->enci.video_prog_mode,
@@ -1094,10 +1089,7 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
* Bypass luma low pass filter
* No macrovision on CSYNC
*/
- writel_relaxed(ENCI_VIDEO_MODE_ADV_DMXMD(2) |
- ENCI_VIDEO_MODE_ADV_VBICTL_LINE_17_22 |
- ENCI_VIDEO_MODE_ADV_YBW_HIGH,
- priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
+ writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
writel(vmode->enci.sch_adjust,
priv->io_base + _REG(ENCI_VIDEO_SCH));
@@ -1113,17 +1105,8 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
/* UNreset Interlaced TV Encoder */
writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
- /*
- * Enable Vfifo2vd and set Y_Cb_Y_Cr:
- * Corresponding value:
- * Y => 00 or 10
- * Cb => 01
- * Cr => 11
- * Ex: 0x4e => 01001110 would mean Cb/Y/Cr/Y
- */
- writel_relaxed(ENCI_VFIFO2VD_CTL_ENABLE |
- ENCI_VFIFO2VD_CTL_VD_SEL(0x4e),
- priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
+ /* Enable Vfifo2vd, Y_Cb_Y_Cr select */
+ writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
/* Timings */
writel_relaxed(vmode->enci.pixel_start,
@@ -1145,8 +1128,7 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI);
/* Interlace video enable */
- writel_relaxed(ENCI_VIDEO_EN_ENABLE,
- priv->io_base + _REG(ENCI_VIDEO_EN));
+ writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
lines_f0 = mode->vtotal >> 1;
lines_f1 = lines_f0 + 1;
@@ -1393,8 +1375,7 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN));
/* Set DE signal’s polarity is active high */
- writel_bits_relaxed(ENCP_VIDEO_MODE_DE_V_HIGH,
- ENCP_VIDEO_MODE_DE_V_HIGH,
+ writel_bits_relaxed(BIT(14), BIT(14),
priv->io_base + _REG(ENCP_VIDEO_MODE));
/* Program DE timing */
@@ -1513,39 +1494,13 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCP);
}
- /* Set VPU HDMI setting */
- /* Select ENCP or ENCI data to HDMI */
- if (use_enci)
- reg = VPU_HDMI_ENCI_DATA_TO_HDMI;
- else
- reg = VPU_HDMI_ENCP_DATA_TO_HDMI;
-
- /* Invert polarity of HSYNC from VENC */
- if (mode->flags & DRM_MODE_FLAG_PHSYNC)
- reg |= VPU_HDMI_INV_HSYNC;
-
- /* Invert polarity of VSYNC from VENC */
- if (mode->flags & DRM_MODE_FLAG_PVSYNC)
- reg |= VPU_HDMI_INV_VSYNC;
-
- /* Output data format: CbYCr */
- reg |= VPU_HDMI_OUTPUT_CBYCR;
-
- /*
- * Write rate to the async FIFO between VENC and HDMI.
- * One write every 2 wr_clk.
- */
- if (venc_repeat)
- reg |= VPU_HDMI_WR_RATE(2);
-
- /*
- * Read rate to the async FIFO between VENC and HDMI.
- * One read every 2 wr_clk.
- */
- if (hdmi_repeat)
- reg |= VPU_HDMI_RD_RATE(2);
-
- writel_relaxed(reg, priv->io_base + _REG(VPU_HDMI_SETTING));
+ writel_relaxed((use_enci ? 1 : 2) |
+ (mode->flags & DRM_MODE_FLAG_PHSYNC ? 1 << 2 : 0) |
+ (mode->flags & DRM_MODE_FLAG_PVSYNC ? 1 << 3 : 0) |
+ 4 << 5 |
+ (venc_repeat ? 1 << 8 : 0) |
+ (hdmi_repeat ? 1 << 12 : 0),
+ priv->io_base + _REG(VPU_HDMI_SETTING));
priv->venc.hdmi_repeat = hdmi_repeat;
priv->venc.venc_repeat = venc_repeat;
@@ -1558,17 +1513,12 @@ EXPORT_SYMBOL_GPL(meson_venc_hdmi_mode_set);
void meson_venci_cvbs_mode_set(struct meson_drm *priv,
struct meson_cvbs_enci_mode *mode)
{
- u32 reg;
-
if (mode->mode_tag == priv->venc.current_mode)
return;
/* CVBS Filter settings */
- writel_relaxed(ENCI_CFILT_CMPT_SEL_HIGH | 0x10,
- priv->io_base + _REG(ENCI_CFILT_CTRL));
- writel_relaxed(ENCI_CFILT_CMPT_CR_DLY(2) |
- ENCI_CFILT_CMPT_CB_DLY(1),
- priv->io_base + _REG(ENCI_CFILT_CTRL2));
+ writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL));
+ writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2));
/* Digital Video Select : Interlace, clk27 clk, external */
writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));
@@ -1590,9 +1540,8 @@ void meson_venci_cvbs_mode_set(struct meson_drm *priv,
priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN));
/* Macrovision max amplitude change */
- writel_relaxed(ENCI_MACV_MAX_AMP_ENABLE_CHANGE |
- ENCI_MACV_MAX_AMP_VAL(mode->macv_max_amp),
- priv->io_base + _REG(ENCI_MACV_MAX_AMP));
+ writel_relaxed(0x8100 + mode->macv_max_amp,
+ priv->io_base + _REG(ENCI_MACV_MAX_AMP));
/* Video mode */
writel_relaxed(mode->video_prog_mode,
@@ -1609,10 +1558,7 @@ void meson_venci_cvbs_mode_set(struct meson_drm *priv,
* Bypass luma low pass filter
* No macrovision on CSYNC
*/
- writel_relaxed(ENCI_VIDEO_MODE_ADV_DMXMD(2) |
- ENCI_VIDEO_MODE_ADV_VBICTL_LINE_17_22 |
- ENCI_VIDEO_MODE_ADV_YBW_HIGH,
- priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
+ writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
writel(mode->sch_adjust, priv->io_base + _REG(ENCI_VIDEO_SCH));
@@ -1644,50 +1590,16 @@ void meson_venci_cvbs_mode_set(struct meson_drm *priv,
/* UNreset Interlaced TV Encoder */
writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
- /*
- * Enable Vfifo2vd and set Y_Cb_Y_Cr:
- * Corresponding value:
- * Y => 00 or 10
- * Cb => 01
- * Cr => 11
- * Ex: 0x4e => 01001110 would mean Cb/Y/Cr/Y
- */
- writel_relaxed(ENCI_VFIFO2VD_CTL_ENABLE |
- ENCI_VFIFO2VD_CTL_VD_SEL(0x4e),
- priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
+ /* Enable Vfifo2vd, Y_Cb_Y_Cr select */
+ writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
/* Power UP Dacs */
writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_SETTING));
/* Video Upsampling */
- /*
- * CTRL0, CTRL1 and CTRL2:
- * Filter0: input data sample every 2 cloks
- * Filter1: filtering and upsample enable
- */
- reg = VENC_UPSAMPLE_CTRL_F0_2_CLK_RATIO | VENC_UPSAMPLE_CTRL_F1_EN |
- VENC_UPSAMPLE_CTRL_F1_UPSAMPLE_EN;
-
- /*
- * Upsample CTRL0:
- * Interlace High Bandwidth Luma
- */
- writel_relaxed(VENC_UPSAMPLE_CTRL_INTERLACE_HIGH_LUMA | reg,
- priv->io_base + _REG(VENC_UPSAMPLE_CTRL0));
-
- /*
- * Upsample CTRL1:
- * Interlace Pb
- */
- writel_relaxed(VENC_UPSAMPLE_CTRL_INTERLACE_PB | reg,
- priv->io_base + _REG(VENC_UPSAMPLE_CTRL1));
-
- /*
- * Upsample CTRL2:
- * Interlace R
- */
- writel_relaxed(VENC_UPSAMPLE_CTRL_INTERLACE_PR | reg,
- priv->io_base + _REG(VENC_UPSAMPLE_CTRL2));
+ writel_relaxed(0x0061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL0));
+ writel_relaxed(0x4061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL1));
+ writel_relaxed(0x5061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL2));
/* Select Interlace Y DACs */
writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL0));
@@ -1701,16 +1613,14 @@ void meson_venci_cvbs_mode_set(struct meson_drm *priv,
meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI);
/* Enable ENCI FIFO */
- writel_relaxed(VENC_VDAC_FIFO_EN_ENCI_ENABLE,
- priv->io_base + _REG(VENC_VDAC_FIFO_CTRL));
+ writel_relaxed(0x2000, priv->io_base + _REG(VENC_VDAC_FIFO_CTRL));
/* Select ENCI DACs 0, 1, 4, and 5 */
writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_0));
writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_1));
/* Interlace video enable */
- writel_relaxed(ENCI_VIDEO_EN_ENABLE,
- priv->io_base + _REG(ENCI_VIDEO_EN));
+ writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
/* Configure Video Saturation / Contrast / Brightness / Hue */
writel_relaxed(mode->video_saturation,
@@ -1723,8 +1633,7 @@ void meson_venci_cvbs_mode_set(struct meson_drm *priv,
priv->io_base + _REG(ENCI_VIDEO_HUE));
/* Enable DAC0 Filter */
- writel_relaxed(VENC_VDAC_DAC0_FILT_CTRL0_EN,
- priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL0));
+ writel_relaxed(0x1, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL0));
writel_relaxed(0xfc48, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL1));
/* 0 in Macrovision register 0 */
@@ -1745,8 +1654,7 @@ unsigned int meson_venci_get_field(struct meson_drm *priv)
void meson_venc_enable_vsync(struct meson_drm *priv)
{
- writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN,
- priv->io_base + _REG(VENC_INTCTRL));
+ writel_relaxed(2, priv->io_base + _REG(VENC_INTCTRL));
regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25));
}
@@ -1774,8 +1682,7 @@ void meson_venc_init(struct meson_drm *priv)
regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);
/* Disable HDMI */
- writel_bits_relaxed(VPU_HDMI_ENCI_DATA_TO_HDMI |
- VPU_HDMI_ENCP_DATA_TO_HDMI, 0,
+ writel_bits_relaxed(0x3, 0,
priv->io_base + _REG(VPU_HDMI_SETTING));
/* Disable all encoders */
diff --git a/drivers/gpu/drm/meson/meson_venc_cvbs.c b/drivers/gpu/drm/meson/meson_venc_cvbs.c
index 9ab27aecfcf3..4d2ad852543e 100644
--- a/drivers/gpu/drm/meson/meson_venc_cvbs.c
+++ b/drivers/gpu/drm/meson/meson_venc_cvbs.c
@@ -171,8 +171,7 @@ static void meson_venc_cvbs_encoder_enable(struct drm_encoder *encoder)
struct meson_drm *priv = meson_venc_cvbs->priv;
/* VDAC0 source is not from ATV */
- writel_bits_relaxed(VENC_VDAC_SEL_ATV_DMD, 0,
- priv->io_base + _REG(VENC_VDAC_DACSEL0));
+ writel_bits_relaxed(BIT(5), 0, priv->io_base + _REG(VENC_VDAC_DACSEL0));
if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
regmap_write(priv->hhi, HHI_VDAC_CNTL0, 1);
--
2.20.1

11
patch/kernel/meson64-dev/1-0004-drm-meson-Add-YUV420-output-support.patch
View file

@ -511,6 +511,17 @@ index 7b7a0d8d737c..5710b5bcfe99 100644
struct drm_display_mode *mode)
{
union meson_hdmi_venc_mode *vmode = NULL;
@@ -1496,8 +1498,8 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
writel_relaxed((use_enci ? 1 : 2) |
(mode->flags & DRM_MODE_FLAG_PHSYNC ? 1 << 2 : 0) |
(mode->flags & DRM_MODE_FLAG_PVSYNC ? 1 << 3 : 0) |
- 4 << 5 |
- (venc_repeat ? 1 << 8 : 0) |
+ (ycrcb_map << 5) |
+ (venc_repeat || yuv420_mode ? 1 << 8 : 0) |
(hdmi_repeat ? 1 << 12 : 0),
priv->io_base + _REG(VPU_HDMI_SETTING));
diff --git a/drivers/gpu/drm/meson/meson_venc.h b/drivers/gpu/drm/meson/meson_venc.h
index 985642a1678e..2d0b71f99402 100644
--- a/drivers/gpu/drm/meson/meson_venc.h

40
patch/kernel/meson64-dev/5-0001-dt-bindings-crypto-Add-DT-bindings-documentation-for.patch
View file

@ -1,28 +1,29 @@
From 95dcad22559d65838826e0f635041037e2407076 Mon Sep 17 00:00:00 2001
From 59983d33bc5931c01ab119a97780f6bd1f00439a Mon Sep 17 00:00:00 2001
From: Corentin Labbe <clabbe@baylibre.com>
Date: Thu, 25 Jul 2019 19:42:53 +0000
Date: Thu, 17 Oct 2019 05:06:23 +0000
Subject: [PATCH 1/4] dt-bindings: crypto: Add DT bindings documentation for
amlogic-crypto
This patch adds documentation for Device-Tree bindings for the
Amlogic GXL cryptographic offloader driver.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
---
.../bindings/crypto/amlogic-gxl-crypto.yaml | 45 +++++++++++++++++++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/amlogic-gxl-crypto.yaml
.../bindings/crypto/amlogic,gxl-crypto.yaml | 52 +++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml
diff --git a/Documentation/devicetree/bindings/crypto/amlogic-gxl-crypto.yaml b/Documentation/devicetree/bindings/crypto/amlogic-gxl-crypto.yaml
diff --git a/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml b/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml
new file mode 100644
index 000000000000..41265e57c00b
index 000000000000..5becc60a0e28
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/amlogic-gxl-crypto.yaml
@@ -0,0 +1,45 @@
+++ b/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/amlogic-gxl-crypto.yaml#
+$id: http://devicetree.org/schemas/crypto/amlogic,gxl-crypto.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic GXL Cryptographic Offloader
@ -32,14 +33,16 @@ index 000000000000..41265e57c00b
+
+properties:
+ compatible:
+ oneOf:
+ - const: amlogic,gxl-crypto
+ items:
+ - const: amlogic,gxl-crypto
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+ items:
+ - description: "Interrupt for flow 0"
+ - description: "Interrupt for flow 1"
+
+ clocks:
+ maxItems: 1
@ -54,13 +57,18 @@ index 000000000000..41265e57c00b
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ crypto: crypto@c883e000 {
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/gxbb-clkc.h>
+
+ crypto: crypto-engine@c883e000 {
+ compatible = "amlogic,gxl-crypto";
+ reg = <0x0 0xc883e000 0x0 0x36>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc CLKID_BLKMV>;
+ clock-names = "blkmv";
+ };

13
patch/kernel/meson64-dev/5-0003-MAINTAINERS-Add-myself-as-maintainer-of-amlogic-cryp.patch → patch/kernel/meson64-dev/5-0002-MAINTAINERS-Add-myself-as-maintainer-of-amlogic-cryp.patch
View file

@ -1,21 +1,22 @@
From ea26c1dd64b66cd5917fdf4b416d7d04c4590c7a Mon Sep 17 00:00:00 2001
From 9ba653cf5d6db5be7e2ef54c3282bc04adf9ec35 Mon Sep 17 00:00:00 2001
From: Corentin Labbe <clabbe@baylibre.com>
Date: Thu, 25 Jul 2019 19:42:55 +0000
Subject: [PATCH 3/4] MAINTAINERS: Add myself as maintainer of amlogic crypto
Date: Thu, 17 Oct 2019 05:06:24 +0000
Subject: [PATCH 2/4] MAINTAINERS: Add myself as maintainer of amlogic crypto
I will maintain the amlogic crypto driver.
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index a2c343ee3b2c..277a3f020959 100644
index b4724c5a9adc..dbf9f16f9069 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1445,6 +1445,13 @@ F: drivers/mmc/host/meson*
F: drivers/soc/amlogic/
@@ -1470,6 +1470,13 @@ F: drivers/soc/amlogic/
F: drivers/rtc/rtc-meson*
N: meson
+ARM/Amlogic Meson SoC Crypto Drivers

419
patch/kernel/meson64-dev/5-0002-crypto-amlogic-Add-crypto-accelerator-for-amlogic-GX.patch → patch/kernel/meson64-dev/5-0003-crypto-amlogic-Add-crypto-accelerator-for-amlogic-GX.patch
View file

@ -1,7 +1,7 @@
From a79f8713e99873f1ac7c0e54d0ab9e8f1f5f982a Mon Sep 17 00:00:00 2001
From 40093b7713c77f0a49f4942f9f1fdf62abcc8adf Mon Sep 17 00:00:00 2001
From: Corentin Labbe <clabbe@baylibre.com>
Date: Thu, 25 Jul 2019 19:42:54 +0000
Subject: [PATCH 2/4] crypto: amlogic: Add crypto accelerator for amlogic GXL
Date: Thu, 17 Oct 2019 05:06:25 +0000
Subject: [PATCH 3/4] crypto: amlogic: Add crypto accelerator for amlogic GXL
This patch adds support for the amlogic GXL cryptographic offloader present
on GXL SoCs.
@ -9,26 +9,27 @@ on GXL SoCs.
This driver supports AES cipher in CBC/ECB mode.
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/crypto/Kconfig | 2 +
drivers/crypto/Makefile | 1 +
drivers/crypto/amlogic/Kconfig | 24 ++
drivers/crypto/amlogic/Makefile | 2 +
drivers/crypto/amlogic/amlogic-cipher.c | 358 ++++++++++++++++++++++++
drivers/crypto/amlogic/amlogic-core.c | 326 +++++++++++++++++++++
drivers/crypto/amlogic/amlogic.h | 172 ++++++++++++
7 files changed, 885 insertions(+)
drivers/crypto/Kconfig | 2 +
drivers/crypto/Makefile | 1 +
drivers/crypto/amlogic/Kconfig | 24 ++
drivers/crypto/amlogic/Makefile | 2 +
drivers/crypto/amlogic/amlogic-gxl-cipher.c | 381 ++++++++++++++++++++
drivers/crypto/amlogic/amlogic-gxl-core.c | 331 +++++++++++++++++
drivers/crypto/amlogic/amlogic-gxl.h | 170 +++++++++
7 files changed, 911 insertions(+)
create mode 100644 drivers/crypto/amlogic/Kconfig
create mode 100644 drivers/crypto/amlogic/Makefile
create mode 100644 drivers/crypto/amlogic/amlogic-cipher.c
create mode 100644 drivers/crypto/amlogic/amlogic-core.c
create mode 100644 drivers/crypto/amlogic/amlogic.h
create mode 100644 drivers/crypto/amlogic/amlogic-gxl-cipher.c
create mode 100644 drivers/crypto/amlogic/amlogic-gxl-core.c
create mode 100644 drivers/crypto/amlogic/amlogic-gxl.h
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 603413f28fa3..3b14afbcf092 100644
index 1fb622f2a87d..359a34ee7370 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -785,4 +785,6 @@ config CRYPTO_DEV_CCREE
@@ -805,4 +805,6 @@ config CRYPTO_DEV_CCREE
source "drivers/crypto/hisilicon/Kconfig"
@ -46,7 +47,7 @@ index afc4753b5d28..9919fbe0e1d4 100644
+obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) += amlogic/
diff --git a/drivers/crypto/amlogic/Kconfig b/drivers/crypto/amlogic/Kconfig
new file mode 100644
index 000000000000..9c4bf96afeb3
index 000000000000..5c81a4ad0fae
--- /dev/null
+++ b/drivers/crypto/amlogic/Kconfig
@@ -0,0 +1,24 @@
@ -59,35 +60,35 @@ index 000000000000..9c4bf96afeb3
+ select CRYPTO_CBC
+ select CRYPTO_AES
+ help
+ Select y here for having support for the cryptographic offloader
+ availlable on Amlogic GXL SoC.
+ This hardware handle AES ciphers in ECB/CBC mode.
+ Select y here to have support for the cryptographic offloader
+ available on Amlogic GXL SoC.
+ This hardware handles AES ciphers in ECB/CBC mode.
+
+ To compile this driver as a module, choose M here: the module
+ will be called amlogic-crypto.
+ will be called amlogic-gxl-crypto.
+
+config CRYPTO_DEV_AMLOGIC_GXL_DEBUG
+ bool "Enabled amlogic stats"
+ bool "Enable amlogic stats"
+ depends on CRYPTO_DEV_AMLOGIC_GXL
+ depends on DEBUG_FS
+ help
+ Say y to enabled amlogic-crypto debug stats.
+ Say y to enable amlogic-crypto debug stats.
+ This will create /sys/kernel/debug/gxl-crypto/stats for displaying
+ the number of requests per flow and per algorithm.
diff --git a/drivers/crypto/amlogic/Makefile b/drivers/crypto/amlogic/Makefile
new file mode 100644
index 000000000000..0ec472c5562e
index 000000000000..39057e62c13e
--- /dev/null
+++ b/drivers/crypto/amlogic/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) += amlogic-crypto.o
+amlogic-crypto-y := amlogic-core.o amlogic-cipher.o
diff --git a/drivers/crypto/amlogic/amlogic-cipher.c b/drivers/crypto/amlogic/amlogic-cipher.c
+obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) += amlogic-gxl-crypto.o
+amlogic-gxl-crypto-y := amlogic-gxl-core.o amlogic-gxl-cipher.o
diff --git a/drivers/crypto/amlogic/amlogic-gxl-cipher.c b/drivers/crypto/amlogic/amlogic-gxl-cipher.c
new file mode 100644
index 000000000000..84e65b4e9ba9
index 000000000000..e9283ffdbd23
--- /dev/null
+++ b/drivers/crypto/amlogic/amlogic-cipher.c
@@ -0,0 +1,358 @@
+++ b/drivers/crypto/amlogic/amlogic-gxl-cipher.c
@@ -0,0 +1,381 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * amlogic-cipher.c - hardware cryptographic offloader for Amlogic GXL SoC
@ -105,13 +106,74 @@ index 000000000000..84e65b4e9ba9
+#include <linux/scatterlist.h>
+#include <linux/dma-mapping.h>
+#include <crypto/internal/skcipher.h>
+#include "amlogic.h"
+#include "amlogic-gxl.h"
+
+static int get_engine_number(struct meson_dev *mc)
+{
+ return atomic_inc_return(&mc->flow) % MAXFLOW;
+}
+
+static bool meson_cipher_need_fallback(struct skcipher_request *areq)
+{
+ struct scatterlist *src_sg = areq->src;
+ struct scatterlist *dst_sg = areq->dst;
+
+ if (areq->cryptlen == 0)
+ return true;
+
+ if (sg_nents(src_sg) != sg_nents(dst_sg))
+ return true;
+
+ /* KEY/IV descriptors use 3 desc */
+ if (sg_nents(src_sg) > MAXDESC - 3 || sg_nents(dst_sg) > MAXDESC - 3)
+ return true;
+
+ while (src_sg && dst_sg) {
+ if ((src_sg->length % 16) != 0)
+ return true;
+ if ((dst_sg->length % 16) != 0)
+ return true;
+ if (src_sg->length != dst_sg->length)
+ return true;
+ if (!IS_ALIGNED(src_sg->offset, sizeof(u32)))
+ return true;
+ if (!IS_ALIGNED(dst_sg->offset, sizeof(u32)))
+ return true;
+ src_sg = sg_next(src_sg);
+ dst_sg = sg_next(dst_sg);
+ }
+
+ return false;
+}
+
+static int meson_cipher_do_fallback(struct skcipher_request *areq)
+{
+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq);
+ struct meson_cipher_tfm_ctx *op = crypto_skcipher_ctx(tfm);
+ struct meson_cipher_req_ctx *rctx = skcipher_request_ctx(areq);
+ int err;
+#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
+ struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
+ struct meson_alg_template *algt;
+#endif
+ SYNC_SKCIPHER_REQUEST_ON_STACK(req, op->fallback_tfm);
+
+#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
+ algt = container_of(alg, struct meson_alg_template, alg.skcipher);
+ algt->stat_fb++;
+#endif
+ skcipher_request_set_sync_tfm(req, op->fallback_tfm);
+ skcipher_request_set_callback(req, areq->base.flags, NULL, NULL);
+ skcipher_request_set_crypt(req, areq->src, areq->dst,
+ areq->cryptlen, areq->iv);
+ if (rctx->op_dir == MESON_DECRYPT)
+ err = crypto_skcipher_decrypt(req);
+ else
+ err = crypto_skcipher_encrypt(req);
+ skcipher_request_zero(req);
+ return err;
+}
+
+static int meson_cipher(struct skcipher_request *areq)
+{
+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq);
@ -125,7 +187,6 @@ index 000000000000..84e65b4e9ba9
+ struct scatterlist *src_sg = areq->src;
+ struct scatterlist *dst_sg = areq->dst;
+ struct meson_desc *desc;
+ bool need_fallback = false;
+ int nr_sgs, nr_sgd;
+ int i, err = 0;
+ unsigned int keyivlen, ivsize, offset, tloffset;
@ -140,53 +201,11 @@ index 000000000000..84e65b4e9ba9
+ rctx->op_dir, crypto_skcipher_ivsize(tfm),
+ op->keylen, flow);
+
+ if (areq->cryptlen == 0)
+ need_fallback = true;
+
+ if (sg_nents(src_sg) != sg_nents(dst_sg))
+ need_fallback = true;
+
+ /* KEY/IV descriptors use 3 desc */
+ if (sg_nents(src_sg) > MAXDESC - 3 || sg_nents(dst_sg) > MAXDESC - 3)
+ need_fallback = true;
+
+ while (src_sg && dst_sg && !need_fallback) {
+ if ((src_sg->length % 16) != 0)
+ need_fallback = true;
+ if ((dst_sg->length % 16) != 0)
+ need_fallback = true;
+ if (src_sg->length != dst_sg->length)
+ need_fallback = true;
+ if (!IS_ALIGNED(src_sg->offset, sizeof(u32)))
+ need_fallback = true;
+ if (!IS_ALIGNED(dst_sg->offset, sizeof(u32)))
+ need_fallback = true;
+ src_sg = sg_next(src_sg);
+ dst_sg = sg_next(dst_sg);
+ }
+
+#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
+ algt->stat_req++;
+ mc->chanlist[flow].stat_req++;
+#endif
+
+ if (need_fallback) {
+ SYNC_SKCIPHER_REQUEST_ON_STACK(req, op->fallback_tfm);
+#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
+ algt->stat_fb++;
+#endif
+ skcipher_request_set_sync_tfm(req, op->fallback_tfm);
+ skcipher_request_set_callback(req, areq->base.flags, NULL,
+ NULL);
+ skcipher_request_set_crypt(req, areq->src, areq->dst,
+ areq->cryptlen, areq->iv);
+ if (rctx->op_dir == MESON_DECRYPT)
+ err = crypto_skcipher_decrypt(req);
+ else
+ err = crypto_skcipher_encrypt(req);
+ skcipher_request_zero(req);
+ return err;
+ }
+
+ /*
+ * The hardware expect a list of meson_desc structures.
+ * The 2 first structures store key
@ -271,9 +290,6 @@ index 000000000000..84e65b4e9ba9
+ }
+ }
+
+#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
+ mc->chanlist[flow].stat_req++;
+#endif
+ src_sg = areq->src;
+ dst_sg = areq->dst;
+ len = areq->cryptlen;
@ -333,8 +349,8 @@ index 000000000000..84e65b4e9ba9
+ return err;
+}
+
+static int handle_cipher_request(struct crypto_engine *engine,
+ void *areq)
+static int meson_handle_cipher_request(struct crypto_engine *engine,
+ void *areq)
+{
+ int err;
+ struct skcipher_request *breq = container_of(areq, struct skcipher_request, base);
@ -350,10 +366,14 @@ index 000000000000..84e65b4e9ba9
+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq);
+ struct meson_cipher_tfm_ctx *op = crypto_skcipher_ctx(tfm);
+ struct meson_cipher_req_ctx *rctx = skcipher_request_ctx(areq);
+ int e = get_engine_number(op->mc);
+ struct crypto_engine *engine = op->mc->chanlist[e].engine;
+ struct crypto_engine *engine;
+ int e;
+
+ rctx->op_dir = MESON_DECRYPT;
+ if (meson_cipher_need_fallback(areq))
+ return meson_cipher_do_fallback(areq);
+ e = get_engine_number(op->mc);
+ engine = op->mc->chanlist[e].engine;
+ rctx->flow = e;
+
+ return crypto_transfer_skcipher_request_to_engine(engine, areq);
@ -364,10 +384,14 @@ index 000000000000..84e65b4e9ba9
+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq);
+ struct meson_cipher_tfm_ctx *op = crypto_skcipher_ctx(tfm);
+ struct meson_cipher_req_ctx *rctx = skcipher_request_ctx(areq);
+ int e = get_engine_number(op->mc);
+ struct crypto_engine *engine = op->mc->chanlist[e].engine;
+ struct crypto_engine *engine;
+ int e;
+
+ rctx->op_dir = MESON_ENCRYPT;
+ if (meson_cipher_need_fallback(areq))
+ return meson_cipher_do_fallback(areq);
+ e = get_engine_number(op->mc);
+ engine = op->mc->chanlist[e].engine;
+ rctx->flow = e;
+
+ return crypto_transfer_skcipher_request_to_engine(engine, areq);
@ -395,7 +419,7 @@ index 000000000000..84e65b4e9ba9
+ return PTR_ERR(op->fallback_tfm);
+ }
+
+ op->enginectx.op.do_one_request = handle_cipher_request;
+ op->enginectx.op.do_one_request = meson_handle_cipher_request;
+ op->enginectx.op.prepare_request = NULL;
+ op->enginectx.op.unprepare_request = NULL;
+
@ -446,12 +470,12 @@ index 000000000000..84e65b4e9ba9
+
+ return crypto_sync_skcipher_setkey(op->fallback_tfm, key, keylen);
+}
diff --git a/drivers/crypto/amlogic/amlogic-core.c b/drivers/crypto/amlogic/amlogic-core.c
diff --git a/drivers/crypto/amlogic/amlogic-gxl-core.c b/drivers/crypto/amlogic/amlogic-gxl-core.c
new file mode 100644
index 000000000000..94f6e5a520bb
index 000000000000..db5b421e88d8
--- /dev/null
+++ b/drivers/crypto/amlogic/amlogic-core.c
@@ -0,0 +1,326 @@
+++ b/drivers/crypto/amlogic/amlogic-gxl-core.c
@@ -0,0 +1,331 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * amlgoic-core.c - hardware cryptographic offloader for Amlogic GXL SoC
@ -469,11 +493,10 @@ index 000000000000..94f6e5a520bb
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <crypto/internal/skcipher.h>
+#include <linux/dma-mapping.h>
+
+#include "amlogic.h"
+#include "amlogic-gxl.h"
+
+static irqreturn_t meson_irq_handler(int irq, void *data)
+{
@ -505,7 +528,7 @@ index 000000000000..94f6e5a520bb
+ .alg.skcipher = {
+ .base = {
+ .cra_name = "cbc(aes)",
+ .cra_driver_name = "cbc-aes-meson",
+ .cra_driver_name = "cbc-aes-gxl",
+ .cra_priority = 400,
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
@ -530,7 +553,7 @@ index 000000000000..94f6e5a520bb
+ .alg.skcipher = {
+ .base = {
+ .cra_name = "ecb(aes)",
+ .cra_driver_name = "ecb-aes-meson",
+ .cra_driver_name = "ecb-aes-gxl",
+ .cra_priority = 400,
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
@ -557,7 +580,7 @@ index 000000000000..94f6e5a520bb
+ int i;
+
+ for (i = 0; i < MAXFLOW; i++)
+ seq_printf(seq, "Channel %d: req %lu\n", i, mc->chanlist[i].stat_req);
+ seq_printf(seq, "Channel %d: nreq %lu\n", i, mc->chanlist[i].stat_req);
+
+ for (i = 0; i < ARRAY_SIZE(mc_algs); i++) {
+ switch (mc_algs[i].type) {
@ -586,9 +609,98 @@ index 000000000000..94f6e5a520bb
+};
+#endif
+
+static void meson_free_chanlist(struct meson_dev *mc, int i)
+{
+ while (i >= 0) {
+ crypto_engine_exit(mc->chanlist[i].engine);
+ if (mc->chanlist[i].tl)
+ dma_free_coherent(mc->dev, sizeof(struct meson_desc) * MAXDESC,
+ mc->chanlist[i].tl,
+ mc->chanlist[i].t_phy);
+ i--;
+ }
+}
+
+/*
+ * Allocate the channel list structure
+ */
+static int meson_allocate_chanlist(struct meson_dev *mc)
+{
+ int i, err;
+
+ mc->chanlist = devm_kcalloc(mc->dev, MAXFLOW,
+ sizeof(struct meson_flow), GFP_KERNEL);
+ if (!mc->chanlist)
+ return -ENOMEM;
+
+ for (i = 0; i < MAXFLOW; i++) {
+ init_completion(&mc->chanlist[i].complete);
+
+ mc->chanlist[i].engine = crypto_engine_alloc_init(mc->dev, true);
+ if (!mc->chanlist[i].engine) {
+ dev_err(mc->dev, "Cannot allocate engine\n");
+ i--;
+ goto error_engine;
+ }
+ err = crypto_engine_start(mc->chanlist[i].engine);
+ if (err) {
+ dev_err(mc->dev, "Cannot start engine\n");
+ goto error_engine;
+ }
+ mc->chanlist[i].tl = dma_alloc_coherent(mc->dev,
+ sizeof(struct meson_desc) * MAXDESC,
+ &mc->chanlist[i].t_phy,
+ GFP_KERNEL);
+ if (!mc->chanlist[i].tl) {
+ err = -ENOMEM;
+ goto error_engine;
+ }
+ }
+ return 0;
+error_engine:
+ meson_free_chanlist(mc, i);
+ return err;
+}
+
+static int meson_register_algs(struct meson_dev *mc)
+{
+ int err, i;
+
+ for (i = 0; i < ARRAY_SIZE(mc_algs); i++) {
+ mc_algs[i].mc = mc;
+ switch (mc_algs[i].type) {
+ case CRYPTO_ALG_TYPE_SKCIPHER:
+ err = crypto_register_skcipher(&mc_algs[i].alg.skcipher);
+ if (err) {
+ dev_err(mc->dev, "Fail to register %s\n",
+ mc_algs[i].alg.skcipher.base.cra_name);
+ mc_algs[i].mc = NULL;
+ return err;
+ }
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static void meson_unregister_algs(struct meson_dev *mc)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(mc_algs); i++) {
+ if (!mc_algs[i].mc)
+ continue;
+ switch (mc_algs[i].type) {
+ case CRYPTO_ALG_TYPE_SKCIPHER:
+ crypto_unregister_skcipher(&mc_algs[i].alg.skcipher);
+ break;
+ }
+ }
+}
+
+static int meson_crypto_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ struct meson_dev *mc;
+ int err, i;
+
@ -602,10 +714,7 @@ index 000000000000..94f6e5a520bb
+ mc->dev = &pdev->dev;
+ platform_set_drvdata(pdev, mc);
+
+ dev_info(mc->dev, "GXL crypto driver v1.1\n");
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ mc->base = devm_ioremap_resource(&pdev->dev, res);
+ mc->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(mc->base)) {
+ err = PTR_ERR(mc->base);
+ dev_err(&pdev->dev, "Cannot request MMIO err=%d\n", err);
@ -634,126 +743,46 @@ index 000000000000..94f6e5a520bb
+ }
+ }
+
+ mc->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
+ if (IS_ERR(mc->reset)) {
+ if (PTR_ERR(mc->reset) == -EPROBE_DEFER)
+ return PTR_ERR(mc->reset);
+ dev_info(&pdev->dev, "No reset control found\n");
+ mc->reset = NULL;
+ }
+
+ err = clk_prepare_enable(mc->busclk);
+ if (err != 0) {
+ dev_err(&pdev->dev, "Cannot prepare_enable busclk\n");
+ return err;
+ }
+
+ err = reset_control_deassert(mc->reset);
+ if (err) {
+ dev_err(&pdev->dev, "Cannot deassert reset control\n");
+ goto error_clk;
+ }
+
+ mc->chanlist = devm_kcalloc(mc->dev, MAXFLOW,
+ sizeof(struct meson_flow), GFP_KERNEL);
+ if (!mc->chanlist) {
+ err = -ENOMEM;
+ err = meson_allocate_chanlist(mc);
+ if (err)
+ goto error_flow;
+ }
+
+ for (i = 0; i < MAXFLOW; i++) {
+ init_completion(&mc->chanlist[i].complete);
+
+ mc->chanlist[i].engine = crypto_engine_alloc_init(mc->dev, 1);
+ if (!mc->chanlist[i].engine) {
+ dev_err(mc->dev, "Cannot allocate engine\n");
+ i--;
+ goto error_engine;
+ }
+ err = crypto_engine_start(mc->chanlist[i].engine);
+ if (err) {
+ dev_err(mc->dev, "Cannot request engine\n");
+ goto error_engine;
+ }
+ mc->chanlist[i].tl = dma_alloc_coherent(mc->dev,
+ sizeof(struct meson_desc) * MAXDESC,
+ &mc->chanlist[i].t_phy,
+ GFP_KERNEL);
+ if (!mc->chanlist[i].tl) {
+ dev_err(mc->dev, "Cannot get DMA memory for task %d\n",
+ i);
+ err = -ENOMEM;
+ goto error_engine;
+ }
+ }
+ err = meson_register_algs(mc);
+ if (err)
+ goto error_alg;
+
+#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
+ mc->dbgfs_dir = debugfs_create_dir("gxl-crypto", NULL);
+ debugfs_create_file("stats", 0444, mc->dbgfs_dir, mc, &meson_debugfs_fops);
+#endif
+ for (i = 0; i < ARRAY_SIZE(mc_algs); i++) {
+ mc_algs[i].mc = mc;
+ switch (mc_algs[i].type) {
+ case CRYPTO_ALG_TYPE_SKCIPHER:
+ err = crypto_register_skcipher(&mc_algs[i].alg.skcipher);
+ if (err) {
+ dev_err(mc->dev, "Fail to register %s\n",
+ mc_algs[i].alg.skcipher.base.cra_name);
+ mc_algs[i].mc = NULL;
+ goto error_alg;
+ }
+ break;
+ }
+ }
+
+ return 0;
+error_alg:
+ i--;
+ for (; i >= 0; i--) {
+ switch (mc_algs[i].type) {
+ case CRYPTO_ALG_TYPE_SKCIPHER:
+ if (mc_algs[i].mc)
+ crypto_unregister_skcipher(&mc_algs[i].alg.skcipher);
+ break;
+ }
+ }
+#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
+ debugfs_remove_recursive(mc->dbgfs_dir);
+#endif
+ i = MAXFLOW;
+error_engine:
+ while (i >= 0) {
+ if (mc->chanlist[i].tl)
+ dma_free_coherent(mc->dev, sizeof(struct meson_desc) * MAXDESC,
+ mc->chanlist[i].tl, mc->chanlist[i].t_phy);
+ i--;
+ }
+ meson_unregister_algs(mc);
+error_flow:
+ reset_control_assert(mc->reset);
+error_clk:
+ meson_free_chanlist(mc, MAXFLOW);
+ clk_disable_unprepare(mc->busclk);
+ return err;
+}
+
+static int meson_crypto_remove(struct platform_device *pdev)
+{
+ int i;
+ struct meson_dev *mc = platform_get_drvdata(pdev);
+
+ for (i = 0; i < ARRAY_SIZE(mc_algs); i++) {
+ switch (mc_algs[i].type) {
+ case CRYPTO_ALG_TYPE_SKCIPHER:
+ if (mc_algs[i].mc)
+ crypto_unregister_skcipher(&mc_algs[i].alg.skcipher);
+ break;
+ }
+ }
+
+#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
+ debugfs_remove_recursive(mc->dbgfs_dir);
+#endif
+
+ reset_control_assert(mc->reset);
+ meson_unregister_algs(mc);
+
+ meson_free_chanlist(mc, MAXFLOW);
+
+ clk_disable_unprepare(mc->busclk);
+ return 0;
+}
@ -778,12 +807,12 @@ index 000000000000..94f6e5a520bb
+MODULE_DESCRIPTION("Amlogic GXL cryptographic offloader");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Corentin Labbe <clabbe@baylibre.com>");
diff --git a/drivers/crypto/amlogic/amlogic.h b/drivers/crypto/amlogic/amlogic.h
diff --git a/drivers/crypto/amlogic/amlogic-gxl.h b/drivers/crypto/amlogic/amlogic-gxl.h
new file mode 100644
index 000000000000..23891cc58d7f
index 000000000000..fd9192b4050b
--- /dev/null
+++ b/drivers/crypto/amlogic/amlogic.h
@@ -0,0 +1,172 @@
+++ b/drivers/crypto/amlogic/amlogic-gxl.h
@@ -0,0 +1,170 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * amlogic.h - hardware cryptographic offloader for Amlogic SoC
@ -877,7 +906,6 @@ index 000000000000..23891cc58d7f
+ * struct meson_dev - main container for all this driver information
+ * @base: base address of amlogic-crypto
+ * @busclk: bus clock for amlogic-crypto
+ * @reset: pointer to reset controller
+ * @dev: the platform device
+ * @chanlist: array of all flow
+ * @flow: flow to use in next request
@ -888,7 +916,6 @@ index 000000000000..23891cc58d7f
+struct meson_dev {
+ void __iomem *base;
+ struct clk *busclk;
+ struct reset_control *reset;
+ struct device *dev;
+ struct meson_flow *chanlist;
+ atomic_t flow;

14
patch/kernel/meson64-dev/5-0004-ARM64-dts-amlogic-adds-crypto-hardware-node.patch
View file

@ -1,20 +1,21 @@
From e71297718cc4a387e6f062ce44d9d187747cf129 Mon Sep 17 00:00:00 2001
From 17bafa64f603b316eed80a0c0fa8c1b66b2ca3c5 Mon Sep 17 00:00:00 2001
From: Corentin Labbe <clabbe@baylibre.com>
Date: Thu, 25 Jul 2019 19:42:56 +0000
Date: Thu, 17 Oct 2019 05:06:26 +0000
Subject: [PATCH 4/4] ARM64: dts: amlogic: adds crypto hardware node
This patch adds the GXL crypto hardware node for all GXL SoCs.
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index a09c53aaa0e8..905771a463f9 100644
index 49ff0a7d0210..ed33d8efaf62 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -36,6 +36,17 @@
@@ -36,6 +36,16 @@
phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>;
};
};
@ -28,7 +29,6 @@ index a09c53aaa0e8..905771a463f9 100644
+ clock-names = "blkmv";
+ status = "okay";
+ };
+
};
};

71
patch/kernel/meson64-dev/board-VIM1-0069-fix.patch
View file

@ -1,71 +0,0 @@
From 12c5dbdae16c4cd2d9914b7a4e31275f3d2070c6 Mon Sep 17 00:00:00 2001
From: balbes150 <balbes-150@yandex.ru>
Date: Mon, 18 Mar 2019 17:40:57 +0300
Subject: [PATCH 69/91] fix
---
drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c | 1 +
drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c | 1 +
drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c | 2 ++
include/linux/mmc/sdio_ids.h | 1 +
4 files changed, 5 insertions(+)
diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c
index d64bf23..0e80530 100644
--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c
+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c
@@ -982,6 +982,7 @@ static const struct sdio_device_id brcmf_sdmmc_ids[] = {
BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_43455),
BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_4354),
BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_4356),
+ BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_4359),
BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_CYPRESS_4373),
BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_CYPRESS_43012),
{ /* end: all zeroes */ }
diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
index 22534bf..1461794 100644
--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
@@ -1348,6 +1348,7 @@ bool brcmf_chip_sr_capable(struct brcmf_chip *pub)
switch (pub->chip) {
case BRCM_CC_4354_CHIP_ID:
case BRCM_CC_4356_CHIP_ID:
+ case BRCM_CC_4359_CHIP_ID:
case BRCM_CC_4345_CHIP_ID:
/* explicitly check SR engine enable bit */
pmu_cc3_mask = BIT(2);
diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
index 0cd5b8d..7809aa1 100644
--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
@@ -624,6 +624,7 @@ BRCMF_FW_DEF(43430A1, "brcmfmac43430-sdio");
BRCMF_FW_DEF(43455, "brcmfmac43455-sdio");
BRCMF_FW_DEF(4354, "brcmfmac4354-sdio");
BRCMF_FW_DEF(4356, "brcmfmac4356-sdio");
+BRCMF_FW_DEF(4359, "brcmfmac4359-sdio");
BRCMF_FW_DEF(4373, "brcmfmac4373-sdio");
BRCMF_FW_DEF(43012, "brcmfmac43012-sdio");
@@ -645,6 +646,7 @@ static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFFC0, 43455),
BRCMF_FW_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354),
BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356),
+ BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359),
BRCMF_FW_ENTRY(CY_CC_4373_CHIP_ID, 0xFFFFFFFF, 4373),
BRCMF_FW_ENTRY(CY_CC_43012_CHIP_ID, 0xFFFFFFFF, 43012)
};
diff --git a/include/linux/mmc/sdio_ids.h b/include/linux/mmc/sdio_ids.h
index 4332199..93a5ac7 100644
--- a/include/linux/mmc/sdio_ids.h
+++ b/include/linux/mmc/sdio_ids.h
@@ -41,6 +41,7 @@
#define SDIO_DEVICE_ID_BROADCOM_43455 0xa9bf
#define SDIO_DEVICE_ID_BROADCOM_4354 0x4354
#define SDIO_DEVICE_ID_BROADCOM_4356 0x4356
+#define SDIO_DEVICE_ID_BROADCOM_4359 0x4359
#define SDIO_DEVICE_ID_CYPRESS_4373 0x4373
#define SDIO_DEVICE_ID_CYPRESS_43012 43012
--
2.7.4

25
patch/kernel/meson64-dev/board-VIM1-fixup-btbcm.patch
View file

@ -1,25 +0,0 @@
From 198ba00ac6a46645a083baad7ddca790a3a1cb94 Mon Sep 17 00:00:00 2001
From: Nick <nick@khadas.com>
Date: Mon, 25 Mar 2019 10:58:49 +0800
Subject: [PATCH 78/91] VIM1: fixup btbcm
---
drivers/bluetooth/btbcm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/bluetooth/btbcm.c b/drivers/bluetooth/btbcm.c
index d5d6e6e..244ca4d 100644
--- a/drivers/bluetooth/btbcm.c
+++ b/drivers/bluetooth/btbcm.c
@@ -337,7 +337,7 @@ static const struct bcm_subver_table bcm_uart_subver_table[] = {
{ 0x6109, "BCM4335C0" }, /* 003.001.009 */
{ 0x610c, "BCM4354" }, /* 003.001.012 */
{ 0x2122, "BCM4343A0" }, /* 001.001.034 */
- { 0x2209, "BCM43430A1" }, /* 001.002.009 */
+ { 0x2209, "BCM43438A1" }, /* 001.002.009 */
{ 0x6119, "BCM4345C0" }, /* 003.001.025 */
{ 0x230f, "BCM4356A2" }, /* 001.003.015 */
{ 0x220e, "BCM20702A1" }, /* 001.002.014 */
--
2.7.4