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Add espressobinv7 dtb to swap wan and lan1 ports (#1244)
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patch/kernel/mvebu64-next/add-board-espressobinv7.patch
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patch/kernel/mvebu64-next/add-board-espressobinv7.patch
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@ -0,0 +1,219 @@
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diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
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index ea9d49f2a911..d80da8f5d82d 100644
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--- a/arch/arm64/boot/dts/marvell/Makefile
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+++ b/arch/arm64/boot/dts/marvell/Makefile
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@@ -2,6 +2,7 @@
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# Mvebu SoC Family
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dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb
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+dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobinv7.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb
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diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobinv7.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobinv7.dts
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new file mode 100644
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index 000000000000..6385b2488e45
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--- /dev/null
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+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobinv7.dts
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@@ -0,0 +1,201 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Device Tree file for Globalscale Marvell ESPRESSOBin Board
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+ * Copyright (C) 2016 Marvell
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+ *
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+ * Romain Perier <romain.perier@free-electrons.com>
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+ *
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+ */
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+/*
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+ * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
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+ */
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+
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+/dts-v1/;
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+
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+#include <dt-bindings/gpio/gpio.h>
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+#include "armada-372x.dtsi"
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+
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+/ {
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+ model = "Globalscale Marvell ESPRESSOBin Board";
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+ compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710";
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ memory@0 {
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+ device_type = "memory";
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+ reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
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+ };
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+
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+ vcc_sd_reg1: regulator {
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+ compatible = "regulator-gpio";
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+ regulator-name = "vcc_sd1";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-boot-on;
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+
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+ gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
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+ gpios-states = <0>;
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+ states = <1800000 0x1
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+ 3300000 0x0>;
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+ enable-active-high;
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+
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+ red {
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+ label = "espressobin:red:usr";
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+ gpios = <&gpionb 2 GPIO_ACTIVE_LOW>;
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+ };
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+ };
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+};
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+
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+/* J9 */
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+&pcie0 {
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+ status = "okay";
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+};
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+
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+/* J6 */
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+&sata {
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+ status = "okay";
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+};
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+
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+/* J1 */
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+&sdhci1 {
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+ wp-inverted;
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+ bus-width = <4>;
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+ cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
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+ marvell,pad-type = "sd";
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+ vqmmc-supply = <&vcc_sd_reg1>;
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+ status = "okay";
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+};
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+
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+&spi0 {
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+ status = "okay";
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+
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+ flash@0 {
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+ reg = <0>;
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+ /*
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+ * Originally "winbond,w25q32dw", but since the manufacturer is known
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+ * to have replaced the part with "macronix,mx25u3235f" in some board
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+ * batches, just use the generic "jedec,spi-nor" and let the actual
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+ * chip type be probed. The partition table still depends on the chip
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+ * being 4 MiB in size.
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+ */
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+ compatible = "jedec,spi-nor";
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+ spi-max-frequency = <104000000>;
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+ m25p,fast-read;
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+ status = "okay";
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+
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+ partitions {
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+ compatible = "fixed-partitions";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ partition@0 {
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+ label = "uboot";
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+ reg = <0 0x3f0000>;
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+ };
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+
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+ partition@3f0000 {
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+ label = "ubootenv";
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+ reg = <0x3f0000 0x10000>;
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+ };
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+ };
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+ };
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+};
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+
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+/* Exported on the micro USB connector J5 through an FTDI */
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+&uart0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart1_pins>;
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+ status = "okay";
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+};
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+
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+/*
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+ * Connector J17 and J18 expose a number of different features. Some pins are
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+ * multiplexed. This is the case for instance for the following features:
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+ * - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of
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+ * how to enable it. Beware that the signals are 1.8V TTL.
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+ * - I2C
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+ * - SPI
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+ * - MMC
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+ */
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+
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+/* J7 */
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+&usb3 {
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+ status = "okay";
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+};
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+
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+/* J8 */
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+&usb2 {
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+ status = "okay";
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+};
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+
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+&mdio {
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+ switch0: switch0@1 {
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+ compatible = "marvell,mv88e6085";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <1>;
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+
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+ dsa,member = <0 0>;
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port@0 {
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+ reg = <0>;
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+ label = "cpu";
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+ ethernet = <ð0>;
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+ };
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+
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+ port@1 {
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+ reg = <1>;
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+ label = "lan1";
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+ phy-handle = <&switch0phy0>;
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+ };
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+
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+ port@2 {
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+ reg = <2>;
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+ label = "lan0";
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+ phy-handle = <&switch0phy1>;
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+ };
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+
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+ port@3 {
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+ reg = <3>;
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+ label = "wan";
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+ phy-handle = <&switch0phy2>;
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+ };
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+
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+ };
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+
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+ mdio {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ switch0phy0: switch0phy0@11 {
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+ reg = <0x11>;
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+ };
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+ switch0phy1: switch0phy1@12 {
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+ reg = <0x12>;
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+ };
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+ switch0phy2: switch0phy2@13 {
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+ reg = <0x13>;
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+ };
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+ };
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+ };
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+};
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+
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+ð0 {
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+ phy-mode = "rgmii-id";
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+ status = "okay";
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+
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+};
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