Merge remote-tracking branch 'upstream/master' into xt-q8l-v10

compile.sh

@@ -54,7 +54,7 @@ for i in "$@"; do
 		parameter=${i%%=*}
 		value=${i##*=}
 		display_alert "Command line: setting $parameter to" "${value:-(empty)}" "info"
-		eval $parameter=$value
+		eval $parameter=\"$value\"
 	fi
 done
 

config/boards/helios4.conf

@@ -2,6 +2,7 @@
 BOARD_NAME="Helios4"
 BOARDFAMILY="mvebu"
 BOOTCONFIG="armada_38x_helios4_config"
+BOOTCONFIG_NEXT="helios4_defconfig"
 MODULES="mv_cesa"
 BUILD_DESKTOP="no"
 FORCE_BOOTSCRIPT_UPDATE="yes"

config/boards/orangepi-rk3399.wip

@@ -0,0 +1,14 @@
+# RK3399 hexa core 2G/4GB SoC GBe eMMC USB3 WiFi
+BOARD_NAME="OrangePiRK3399"
+BOARDFAMILY="rk3399"
+BOOTCONFIG="orangepi-rk3399_defconfig"
+#
+MODULES=""
+MODULES_NEXT=""
+#
+KERNEL_TARGET="default,dev"
+CLI_TARGET="stretch,bionic:default"
+DESKTOP_TARGET="stretch,bionic:default"
+
+CLI_BETA_TARGET=""
+DESKTOP_BETA_TARGET=""

config/boards/rockpi-4b.wip

@@ -0,0 +1,14 @@
+# RK3399 hexa core 2G/4GB SoC GBe eMMC USB3 WiFi
+BOARD_NAME="RockPi-4B"
+BOARDFAMILY="rockchip64"
+BOOTCONFIG="rockpi4b-rk3399_defconfig"
+#
+MODULES=""
+MODULES_NEXT=""
+#
+KERNEL_TARGET="default,dev"
+CLI_TARGET="stretch,bionic:default"
+DESKTOP_TARGET="stretch,bionic:default"
+
+CLI_BETA_TARGET=""
+DESKTOP_BETA_TARGET=""

config/boards/tinkerboard.conf

@@ -5,10 +5,10 @@ BOOTCONFIG="tinker-rk3288_defconfig"
 #
 MODULES="hci_uart rfcomm hidp 8723bs"
 MODULES_NEXT=""
-#
+DEFAULT_OVERLAYS="i2c1 i2c4 spi2 spidev2 uart1 uart2"
 KERNEL_TARGET="default,next,dev"
 CLI_TARGET="stretch,bionic:default,next"
 DESKTOP_TARGET="stretch,bionic:default,next"
 #
-CLI_BETA_TARGET=""
+CLI_BETA_TARGET="bionic:dev"
 DESKTOP_BETA_TARGET="stretch:dev"

config/kernel/linux-meson64-dev.config

@@ -703,9 +703,9 @@ CONFIG_CMA=y
 CONFIG_CMA_AREAS=7
 CONFIG_ZSWAP=y
 CONFIG_ZPOOL=y
-CONFIG_ZBUD=m
-# CONFIG_Z3FOLD is not set
-CONFIG_ZSMALLOC=m
+CONFIG_ZBUD=y
+CONFIG_Z3FOLD=y
+CONFIG_ZSMALLOC=y
 CONFIG_PGTABLE_MAPPING=y
 # CONFIG_ZSMALLOC_STAT is not set
 CONFIG_GENERIC_EARLY_IOREMAP=y

config/kernel/linux-mvebu64-next.config

@@ -1,6 +1,6 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Linux/arm64 4.19.2 Kernel Configuration
+# Linux/arm64 4.19.13 Kernel Configuration
 #
 
 #
@@ -2771,6 +2771,7 @@ CONFIG_RTL8814AU=m
 CONFIG_WLAN_VENDOR_MEDIATEK=y
 CONFIG_MT7601U=m
 CONFIG_MT76_CORE=m
+CONFIG_MT76_LEDS=y
 CONFIG_MT76_USB=m
 CONFIG_MT76x2_COMMON=m
 CONFIG_MT76x0U=m

config/kernel/linux-rk3399-default.config

@@ -1,6 +1,6 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Linux/arm64 4.4.162 Kernel Configuration
+# Linux/arm64 4.4.167 Kernel Configuration
 #
 CONFIG_ARM64=y
 CONFIG_64BIT=y

config/kernel/linux-rockchip-next.config

@@ -3821,7 +3821,13 @@ CONFIG_USB_UAS=m
 #
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_MICROTEK is not set
-# CONFIG_USBIP_CORE is not set
+CONFIG_USBIP_CORE=m
+CONFIG_USBIP_VHCI_HCD=m
+CONFIG_USBIP_HOST=m
+CONFIG_USBIP_VHCI_HC_PORTS=8
+CONFIG_USBIP_VHCI_NR_HCS=1
+CONFIG_USBIP_VUDC=m
+# CONFIG_USBIP_DEBUG is not set
 # CONFIG_USB_MUSB_HDRC is not set
 # CONFIG_USB_DWC3 is not set
 CONFIG_USB_DWC2=y

config/kernel/linux-rockchip64-default.config

@@ -1,6 +1,6 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Linux/arm64 4.4.166 Kernel Configuration
+# Linux/arm64 4.4.167 Kernel Configuration
 #
 CONFIG_ARM64=y
 CONFIG_64BIT=y
@@ -5665,7 +5665,7 @@ CONFIG_SQUASHFS_DECOMP_SINGLE=y
 CONFIG_SQUASHFS_ZLIB=y
 # CONFIG_SQUASHFS_LZ4 is not set
 CONFIG_SQUASHFS_LZO=y
-# CONFIG_SQUASHFS_XZ is not set
+CONFIG_SQUASHFS_XZ=y
 # CONFIG_SQUASHFS_ZSTD is not set
 # CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
 # CONFIG_SQUASHFS_EMBEDDED is not set

config/kernel/linux-sunxi-dev.config

@@ -1,6 +1,6 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Linux/arm 4.19.2 Kernel Configuration
+# Linux/arm 4.19.11 Kernel Configuration
 #
 
 #
@@ -1511,6 +1511,7 @@ CONFIG_BT_HCIUART_LL=y
 CONFIG_BT_HCIUART_3WIRE=y
 # CONFIG_BT_HCIUART_INTEL is not set
 # CONFIG_BT_HCIUART_BCM is not set
+CONFIG_BT_HCIUART_RTL=y
 # CONFIG_BT_HCIUART_QCA is not set
 # CONFIG_BT_HCIUART_AG6XX is not set
 # CONFIG_BT_HCIUART_MRVL is not set
@@ -2319,6 +2320,7 @@ CONFIG_RTL8814AU=m
 CONFIG_WLAN_VENDOR_MEDIATEK=y
 CONFIG_MT7601U=m
 CONFIG_MT76_CORE=m
+CONFIG_MT76_LEDS=y
 CONFIG_MT76_USB=m
 CONFIG_MT76x2_COMMON=m
 CONFIG_MT76x0U=m

config/kernel/linux-sunxi64-dev.config

@@ -1,6 +1,6 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Linux/arm64 4.19.6 Kernel Configuration
+# Linux/arm64 4.19.10 Kernel Configuration
 #
 
 #
@@ -1413,6 +1413,7 @@ CONFIG_BT_DEBUGFS=y
 CONFIG_BT_INTEL=m
 CONFIG_BT_BCM=m
 CONFIG_BT_RTL=m
+CONFIG_BT_QCA=m
 CONFIG_BT_HCIBTUSB=m
 # CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
 CONFIG_BT_HCIBTUSB_BCM=y
@@ -1421,10 +1422,15 @@ CONFIG_BT_HCIBTSDIO=m
 CONFIG_BT_HCIUART=m
 CONFIG_BT_HCIUART_SERDEV=y
 CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_NOKIA=m
 CONFIG_BT_HCIUART_BCSP=y
 CONFIG_BT_HCIUART_ATH3K=y
-CONFIG_BT_HCIUART_INTEL=y
+CONFIG_BT_HCIUART_LL=y
 CONFIG_BT_HCIUART_3WIRE=y
+CONFIG_BT_HCIUART_INTEL=y
+CONFIG_BT_HCIUART_BCM=y
+CONFIG_BT_HCIUART_RTL=y
+CONFIG_BT_HCIUART_QCA=y
 CONFIG_BT_HCIUART_AG6XX=y
 CONFIG_BT_HCIUART_MRVL=y
 CONFIG_BT_HCIBCM203X=m
@@ -1434,6 +1440,7 @@ CONFIG_BT_HCIVHCI=m
 CONFIG_BT_MRVL=m
 CONFIG_BT_MRVL_SDIO=m
 CONFIG_BT_ATH3K=m
+CONFIG_BT_MTKUART=m
 # CONFIG_AF_RXRPC is not set
 # CONFIG_AF_KCM is not set
 CONFIG_STREAM_PARSER=y
@@ -1550,6 +1557,9 @@ CONFIG_SUNXI_RSB=y
 # CONFIG_VEXPRESS_CONFIG is not set
 # CONFIG_CONNECTOR is not set
 CONFIG_GNSS=m
+CONFIG_GNSS_SERIAL=m
+CONFIG_GNSS_SIRF_SERIAL=m
+CONFIG_GNSS_UBX_SERIAL=m
 CONFIG_MTD=y
 # CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_REDBOOT_PARTS is not set
@@ -1931,7 +1941,9 @@ CONFIG_NET_VENDOR_NETRONOME=y
 CONFIG_NET_VENDOR_NI=y
 # CONFIG_ETHOC is not set
 CONFIG_NET_VENDOR_QUALCOMM=y
+CONFIG_QCA7000=m
 # CONFIG_QCA7000_SPI is not set
+CONFIG_QCA7000_UART=m
 # CONFIG_QCOM_EMAC is not set
 # CONFIG_RMNET is not set
 CONFIG_NET_VENDOR_RENESAS=y
@@ -2140,6 +2152,7 @@ CONFIG_RTL8814AU=m
 CONFIG_WLAN_VENDOR_MEDIATEK=y
 CONFIG_MT7601U=m
 CONFIG_MT76_CORE=m
+CONFIG_MT76_LEDS=y
 CONFIG_MT76_USB=m
 CONFIG_MT76x2_COMMON=m
 CONFIG_MT76x0U=m
@@ -2383,6 +2396,7 @@ CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
 # CONFIG_INPUT_DRV260X_HAPTICS is not set
 # CONFIG_INPUT_DRV2665_HAPTICS is not set
 # CONFIG_INPUT_DRV2667_HAPTICS is not set
+CONFIG_INPUT_RAVE_SP_PWRBUTTON=m
 CONFIG_RMI4_CORE=m
 CONFIG_RMI4_I2C=m
 CONFIG_RMI4_SPI=m
@@ -2940,6 +2954,7 @@ CONFIG_SOFT_WATCHDOG=m
 CONFIG_GPIO_WATCHDOG=m
 # CONFIG_XILINX_WATCHDOG is not set
 # CONFIG_ZIIRAVE_WATCHDOG is not set
+CONFIG_RAVE_SP_WATCHDOG=m
 CONFIG_ARM_SP805_WATCHDOG=m
 CONFIG_ARM_SBSA_WATCHDOG=m
 # CONFIG_CADENCE_WATCHDOG is not set
@@ -3074,6 +3089,7 @@ CONFIG_MFD_WL1273_CORE=m
 # CONFIG_MFD_WM8350_I2C is not set
 # CONFIG_MFD_WM8994 is not set
 CONFIG_MFD_ROHM_BD718XX=m
+CONFIG_RAVE_SP_CORE=m
 CONFIG_REGULATOR=y
 # CONFIG_REGULATOR_DEBUG is not set
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
@@ -3807,6 +3823,7 @@ CONFIG_BACKLIGHT_GPIO=m
 # CONFIG_BACKLIGHT_LV5207LP is not set
 # CONFIG_BACKLIGHT_BD6107 is not set
 # CONFIG_BACKLIGHT_ARCXCNN is not set
+CONFIG_BACKLIGHT_RAVE_SP=m
 CONFIG_VIDEOMODE_HELPERS=y
 CONFIG_HDMI=y
 
@@ -5505,6 +5522,7 @@ CONFIG_DAX=m
 # CONFIG_DEV_DAX is not set
 CONFIG_NVMEM=y
 CONFIG_NVMEM_SUNXI_SID=y
+CONFIG_RAVE_SP_EEPROM=m
 
 #
 # HW tracing support

config/sources/meson64.conf

@@ -150,19 +150,26 @@ uboot_custom_postprocess()
 	fi
 }
 
+
+if [[ $BOARD == odroidc2 ]]; then
+
 	write_uboot_platform()
 	{
-	. /etc/armbian-release 
-	if [[ $BOARD == odroidc2 ]]; then
 		dd if=$1/bl1.bin.hardkernel of=$2 bs=1 count=442 conv=fsync > /dev/null 2>&1
 		dd if=$1/bl1.bin.hardkernel of=$2 bs=512 skip=1 seek=1 conv=fsync > /dev/null 2>&1
 		dd if=$1/u-boot.bin of=$2 bs=512 seek=97 conv=fsync > /dev/null 2>&1
+	}
+
 	else
+
+	write_uboot_platform()
+	{
 		dd if=$1/u-boot.bin of=$2 bs=1 count=442 conv=fsync > /dev/null 2>&1
 		dd if=$1/u-boot.bin of=$2 bs=512 skip=1 seek=1 conv=fsync > /dev/null 2>&1
-	fi
 	}
 
+fi
+
 family_tweaks()
 {
 	echo "#Allow ttyAML0 root" >> $SDCARD/etc/securetty

config/sources/mvebu-helios4.inc

@@ -18,7 +18,6 @@ case $BRANCH in
 	BOOTBRANCH='branch:helios4'
 	BOOTDIR=$MAINLINE_UBOOT_DIR
 	BOOTSCRIPT='boot-marvell.cmd:boot.cmd'
-	BOOTCONFIG='helios4_defconfig'
 
 	UBOOT_TARGET_MAP=";;u-boot-spl.kwb:u-boot.mmc
 		;spi;u-boot-spl.kwb:u-boot.flash"

config/sources/mvebu64.conf

@@ -2,19 +2,19 @@ ARCH=arm64
 KERNEL_IMAGE_TYPE=Image
 
 BOOTSCRIPT="boot-espressobin.cmd:boot.cmd"
-UBOOT_TARGET_MAP=";;flash-image-*.bin"
+UBOOT_TARGET_MAP="DEVICE_TREE=armada-3720-espressobin ;;flash-image-*.bin"
 
 BOOTSOURCE='https://github.com/MarvellEmbeddedProcessors/u-boot-marvell.git'
 BOOTDIR=$MAINLINE_UBOOT_DIR
-BOOTBRANCH='branch:u-boot-2017.03-armada-18.09'
+BOOTBRANCH='branch:u-boot-2018.03-armada-18.12'
 
-UBOOT_USE_GCC='< 7.0'
+UBOOT_USE_GCC='> 7.2'
 
 BOOTENV_FILE='clearfog-default.txt'
 
 ATFSOURCE='https://github.com/MarvellEmbeddedProcessors/atf-marvell'
 ATFDIR='arm-trusted-firmware-espressobin'
-ATFBRANCH='branch:atf-v1.5-armada-18.09'
+ATFBRANCH='branch:atf-v1.5-armada-18.12'
 ATF_USE_GCC='> 7.2'
 ATF_COMPILER='aarch64-linux-gnu-'
 ATF_TARGET_MAP='DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 SECURE=0 CLOCKSPRESET=CPU_800_DDR_800 DDR_TOPOLOGY=2 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700;;build/a3700/debug/bl31.bin'
@@ -74,16 +74,19 @@ atf_custom_postprocess()
 
 uboot_custom_postprocess()
 {
+	# clean previous
+	rm $ubootdir/flash-image*
 	local atfdir="$SRC/cache/sources/$ATFDIR/${ATFBRANCH##*:}"
 	local ubootdir="$SRC/cache/sources/$BOOTDIR/${BOOTBRANCH##*:}"
 	cd $atfdir
 	clocks=( 600_600 800_800 1000_800 1200_750 )
-	topology=( 512m_1cs_0 512m_2cs_0 1g_2cs_2 1g_1cs_4 2g_2cs_2 )
+	topology=( 512m_1cs_0 512m_2cs_0 1g_2cs_2 1g_1cs_4 2g_2cs_2 1g_1cs_5 2g_2cs_6 )
 	for i in "${clocks[@]}"
 	do
         for j in "${topology[@]}"
         do
-			FILENAME="flash-image-$j-$i.bin"
+			if [[ $j = *cs_5 || $j = *cs_6 ]]; then local ddrname="DDR4"; else ddrname="DDR3"; fi
+			FILENAME="flash-image-$ddrname-$j-$i.bin"
 			DDR_TOPOLOGY="${j##*_}"
 			CLOCKSPRESET="CPU_${i%_*}_DDR_${i##*_}"
 			display_alert "Building $FILENAME" "" "info"

config/sources/odroidxu4.conf

@@ -116,8 +116,9 @@ family_tweaks()
 
 family_tweaks_bsp()
 {
-	if [[ $BRANCH != default ]]; then
 	mkdir -p $destination/etc/udev/rules.d
+	cp $SRC/packages/bsp/odroid/90-builtin-net-rps.rules $destination/etc/udev/rules.d
+	if [[ $BRANCH != default ]]; then
 		mkdir -p $destination/usr/local/bin
 		cp $SRC/packages/bsp/rockchip/hdmi.rules $destination/etc/udev/rules.d
 		install -m 755 $SRC/packages/bsp/rockchip/hdmi-hotplug $destination/usr/local/bin

config/sources/rk3399.conf

@@ -40,7 +40,7 @@ case $BRANCH in
 
 	dev)
 	KERNELSOURCE='https://github.com/ayufan-rock64/linux-mainline-kernel'
-	KERNELBRANCH='tag:tag:4.19.0-1073-ayufan'
+	KERNELBRANCH='tag:tag:4.20.0-1083-ayufan'
 	KERNELDIR='linux-rockchip64'
 	KERNELPATCHDIR='rockchip64-dev'
 	LINUXCONFIG='linux-rockchip64-dev'
@@ -89,5 +89,6 @@ family_tweaks()
 	[[ $BOARD == nanopct4 ]] && echo "fdtfile=rockchip/rk3399-nanopi4-rev00.dtb" >> $SDCARD/boot/armbianEnv.txt
 	[[ $BOARD == nanopim4 ]] && echo "fdtfile=rockchip/rk3399-nanopi4-rev01.dtb" >> $SDCARD/boot/armbianEnv.txt
 	[[ $BOARD == nanopineo4 ]] && echo "fdtfile=rockchip/rk3399-nanopi4-rev04.dtb" >> $SDCARD/boot/armbianEnv.txt
+	[[ $BOARD == orangepi-rk3399 ]] && echo "fdtfile=rockchip/rk3399-orangepi.dtb" >> $SDCARD/boot/armbianEnv.txt
 	[[ $BOARD == firefly-rk3399 ]] && echo "fdtfile=rockchip/rk3399-firefly.dtb" >> $SDCARD/boot/armbianEnv.txt
 }

config/sources/rockchip64.conf

@@ -24,7 +24,7 @@ ATFBRANCH='branch:rockchip'
 ATF_USE_GCC='> 6.3'
 GOVERNOR="ondemand"
 
-if [[ $BOARD == rockpro64 ]]; then
+if [[ $BOARD == rockpro64 ]] || [[ $BOARD == rockpi-4b ]]; then
 
 	ATF_TARGET_MAP='M0_CROSS_COMPILE=arm-linux-gnueabi- PLAT=rk3399 DEBUG=1 bl31;;trust.bin'
 	ATF_TOOLCHAIN2="arm-linux-gnueabi-:> 5.0"
@@ -43,14 +43,14 @@ fi
 case $BRANCH in
 	default)
 		KERNELSOURCE='https://github.com/ayufan-rock64/linux-kernel'
-		KERNELBRANCH='tag:4.4.154-1124-rockchip-ayufan'
+		KERNELBRANCH='tag:4.4.154-1128-rockchip-ayufan'
 		KERNELDIR='linux-rockchip64'
 		KERNEL_USE_GCC='> 7.0'
 	;;
 
 	dev)
 		KERNELSOURCE='https://github.com/ayufan-rock64/linux-mainline-kernel'
-		KERNELBRANCH='branch:mainline-master'
+		KERNELBRANCH='tag:4.20.0-1083-ayufan'
 		KERNELDIR='linux-rockchip64'
 		KERNEL_USE_GCC='> 7.0'
 	;;
@@ -82,7 +82,7 @@ setup_write_uboot_platform()
 uboot_custom_postprocess()
 {
 	# bootloader image
-	if [[ $BOARD == rockpro64 ]]; then
+	if [[ $BOARD == rockpro64 ]] || [[ $BOARD == rockpi-4b ]]; then
 		# 3399
 		tools/mkimage -n rk3399 -T rksd -d $SRC/cache/sources/rkbin-tools/rk33/rk3399_ddr_933MHz_v1.13.bin rksd_loader.img
 		cat spl/u-boot-spl.bin >> rksd_loader.img

config/sources/sun50iw1.conf

@@ -46,15 +46,19 @@ case $BRANCH in
 	;;
 
 	dev)
+	ATFSOURCE='https://github.com/apritzel/arm-trusted-firmware'
+	ATFBRANCH='branch:allwinner'
+	ATF_TARGET_MAP='PLAT=sun50iw1p1 DEBUG=1 bl31;;build/sun50iw1p1/debug/bl31.bin'
 	BOOTENV_FILE='sun50iw1-next.txt'
 	BOOTSOURCE='https://github.com/anarsoul/u-boot-pine64'
 	BOOTDIR=$MAINLINE_UBOOT_DIR
-	BOOTBRANCH='branch:pinebook-wip-20181104'
+	BOOTBRANCH='branch:pinebook-wip-20181109'
 	BOOTPATCHDIR='u-boot-sun50iw2'
 	UBOOT_USE_GCC='> 7.0'
 	UBOOT_TARGET_MAP=';;spl/sunxi-spl.bin u-boot.itb'
 	BOOTSCRIPT='boot-sun50i-next.cmd:boot.cmd'
 	GOVERNOR=ondemand
+	ASOUND_STATE='asound.state.pinebook-next'
 
 	;;
 esac
@@ -91,6 +95,14 @@ family_tweaks_s()
 	fi
 	# power manager
 	[[ $BUILD_DESKTOP == yes && $BOARD == pinebook-a64 || $BOARD == teres-a64 || $BOARD == lime-a64 ]] && chroot $SDCARD /bin/bash -c "apt-get -qq -y install xfce4-power-manager bluetooth >/dev/null 2>&1"
+
+	# add bluetooth firmware for 8723cs + sysrq fix
+	if [[ $BOARD == pinebook-a64 && $BRANCH == dev ]]; then
+		cp -R $SRC/packages/blobs/rtl8723bt_fw/* $SDCARD/lib/firmware/rtl_bt/
+		touch $SDCARD/etc/sysctl.d/sysrq.conf
+		echo "kernel.sysrq = 0" >> $SDCARD/etc/sysctl.d/sysrq.conf
+	fi
+
 }
 
 family_tweaks_bsp()

config/templates/config-example.conf

@@ -1,4 +1,4 @@
-# Read build script documentation http://www.armbian.com/using-armbian-tools/
+# Read build script documentation https://docs.armbian.com/Developer-Guide_Build-Options/
 # for detailed explanation of these options and for additional options not listed here
 
 KERNEL_ONLY=""				# leave empty to select each time, set to "yes" or "no" to skip dialog prompt

lib/build-all.sh

@@ -229,7 +229,7 @@ for line in "${buildlist[@]}"; do
 		MODULES_BLACKLIST_DEV MOUNT SDCARD BOOTPATCHDIR KERNELPATCHDIR buildtext RELEASE IMAGE_TYPE OVERLAY_PREFIX ASOUND_STATE \
 		ATF_COMPILER ATF_USE_GCC ATFSOURCE ATFDIR ATFBRANCH ATFSOURCEDIR PACKAGE_LIST_RM NM_IGNORE_DEVICES DISPLAY_MANAGER family_tweaks_bsp_s \
 		CRYPTROOT_ENABLE CRYPTROOT_PASSPHRASE CRYPTROOT_SSH_UNLOCK CRYPTROOT_SSH_UNLOCK_PORT CRYPTROOT_SSH_UNLOCK_KEY_NAME ROOT_MAPPER \
-		NETWORK HDMI USB WIRELESS ARMBIANMONITOR DEFAULT_CONSOLE
+		NETWORK HDMI USB WIRELESS ARMBIANMONITOR DEFAULT_CONSOLE FORCE_BOOTSCRIPT_UPDATE SERIALCON
 
 	read BOARD BRANCH RELEASE BUILD_DESKTOP <<< $line
 	n=$[$n+1]

lib/configuration.sh

@@ -10,7 +10,7 @@
 # common options
 # daily beta build contains date in subrevision
 if [[ $BETA == yes && -z $SUBREVISION ]]; then SUBREVISION="."$(date --date="tomorrow" +"%y%m%d"); fi
-REVISION="5.67$SUBREVISION" # all boards have same revision
+REVISION="5.68$SUBREVISION" # all boards have same revision
 ROOTPWD="1234" # Must be changed @first login
 [[ -z $MAINTAINER ]] && MAINTAINER="Igor Pecovnik" # deb signature
 [[ -z $MAINTAINERMAIL ]] && MAINTAINERMAIL="igor.pecovnik@****l.com" # deb signature

lib/distributions.sh

@@ -149,9 +149,11 @@ install_common()
 	ff02::2     ip6-allrouters
 	EOF
 
-	# install kernel and u-boot packages
+	# install kernel
 	install_deb_chroot "$DEST/debs/${CHOSEN_KERNEL}_${REVISION}_${ARCH}.deb"
-	install_deb_chroot "$DEST/debs/${CHOSEN_UBOOT}_${REVISION}_${ARCH}.deb"
+	# unpack u-boot
+	dpkg -x ${DEST}/debs/${CHOSEN_UBOOT}_${REVISION}_${ARCH}.deb $SDCARD
+
 
 	if [[ $BUILD_DESKTOP == yes ]]; then
 		install_deb_chroot "$DEST/debs/$RELEASE/armbian-${RELEASE}-desktop_${REVISION}_all.deb"

lib/general.sh

@@ -72,7 +72,7 @@ cleaning()
 		;;
 
 		oldcache)
-		if [[ -d $SRC/cache/rootfs && $(ls -1 $SRC/cache/rootfs/*.lz4 | wc -l) -gt ${ROOTFS_CACHE_MAX} ]]; then
+		if [[ -d $SRC/cache/rootfs && $(ls -1 $SRC/cache/rootfs/*.lz4 2> /dev/null | wc -l) -gt ${ROOTFS_CACHE_MAX} ]]; then
 			display_alert "Cleaning" "rootfs cache (old)" "info"
 			(cd $SRC/cache/rootfs; ls -t *.lz4 | sed -e "1,${ROOTFS_CACHE_MAX}d" | xargs -d '\n' rm -f)
 			# Remove signatures if they are present. We use them for internal purpose

lib/main.sh

@@ -245,8 +245,8 @@ if [[ $IGNORE_UPDATES != yes ]]; then
 	fi
 	fetch_from_repo "https://github.com/linux-sunxi/sunxi-tools" "sunxi-tools" "branch:master"
 	fetch_from_repo "https://github.com/armbian/rkbin" "rkbin-tools" "branch:master"
-	fetch_from_repo "https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell" "marvell-tools" "branch:A3700_utils-armada-18.09"
-	fetch_from_repo "https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git" "marvell-ddr" "branch:mv_ddr-armada-18.09"
+	fetch_from_repo "https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell" "marvell-tools" "branch:A3700_utils-armada-18.12"
+	fetch_from_repo "https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git" "marvell-ddr" "branch:mv_ddr-armada-18.12"
 	fetch_from_repo "https://github.com/armbian/odroidc2-blobs" "odroidc2-blobs" "branch:master"
 	fetch_from_repo "https://github.com/armbian/testings" "testing-reports" "branch:master"
 fi

lib/makeboarddeb.sh

@@ -200,9 +200,12 @@ create_board_package()
 		echo "Recreating boot script"
 		cp /usr/share/armbian/$bootscript_dst /boot  >/dev/null 2>&1
 		rootdev=\$(sed -e 's/^.*root=//' -e 's/ .*\$//' < /proc/cmdline)
+		rootfstype=\$(sed -e 's/^.*rootfstype=//' -e 's/ .*$//' < /proc/cmdline)
 		cp /usr/share/armbian/armbianEnv.txt /boot  >/dev/null 2>&1
 		echo "rootdev="\$rootdev >> /boot/armbianEnv.txt
+		echo "rootfstype="\$rootfstype >> /boot/armbianEnv.txt
 		sed -i "s/setenv rootdev.*/setenv rootdev \\"\$rootdev\\"/" /boot/boot.ini
+		sed -i "s/setenv rootfstype.*/setenv rootfstype \\"\$rootfstype\\"/" /boot/boot.ini
 		[ -f /boot/boot.cmd ] && mkimage -C none -A arm -T script -d /boot/boot.cmd /boot/boot.scr  >/dev/null 2>&1
 	EOF
 	if [[ $FORCE_BOOTSCRIPT_UPDATE == yes ]]; then
@@ -218,6 +221,8 @@ create_board_package()
 				mkimage -C none -A arm -T script -d /boot/boot.cmd /boot/boot.scr  >/dev/null 2>&1
 			elif [ -f /boot/boot.ini ]; then
 				rootdev=\$(sed -e 's/^.*root=//' -e 's/ .*\$//' < /proc/cmdline)
+				rootfstype=\$(sed -e 's/^.*rootfstype=//' -e 's/ .*$//' < /proc/cmdline)
+				sed -i "s/setenv rootfstype.*/setenv rootfstype \\"\$rootfstype\\"/" /boot/boot.ini
 				sed -i "s/setenv rootdev.*/setenv rootdev \\"\$rootdev\\"/" /boot/boot.ini
 			fi
 

packages/blobs/asound.state/asound.state.pinebook-next

@@ -0,0 +1,530 @@
+state.Card {
+  control.1 {
+    iface MIXER
+    name 'Headphone Playback Volume'
+    value 46
+    comment {
+      access 'read write'
+      type INTEGER
+      count 1
+      range '0 - 63'
+      dbmin -9999999
+      dbmax 0
+      dbvalue.0 -1700
+    }
+  }
+  control.2 {
+    iface MIXER
+    name 'Headphone Playback Switch'
+    value.0 true
+    value.1 true
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+  control.3 {
+    iface MIXER
+    name 'Line Out Playback Volume'
+    value 0
+    comment {
+      access 'read write'
+      type INTEGER
+      count 1
+      range '0 - 31'
+      dbmin -9999999
+      dbmax 0
+      dbvalue.0 -9999999
+    }
+  }
+  control.4 {
+    iface MIXER
+    name 'Line Out Playback Switch'
+    value.0 false
+    value.1 false
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+  control.5 {
+    iface MIXER
+    name 'Mic1 Playback Volume'
+    value 0
+    comment {
+      access 'read write'
+      type INTEGER
+      count 1
+      range '0 - 7'
+      dbmin -450
+      dbmax 600
+      dbvalue.0 -450
+    }
+  }
+  control.6 {
+    iface MIXER
+    name 'Mic1 Boost Volume'
+    value 0
+    comment {
+      access 'read write'
+      type INTEGER
+      count 1
+      range '0 - 7'
+      dbmin 0
+      dbmax 4200
+      dbvalue.0 0
+    }
+  }
+  control.7 {
+    iface MIXER
+    name 'ADC Gain Capture Volume'
+    value 6
+    comment {
+      access 'read write'
+      type INTEGER
+      count 1
+      range '0 - 7'
+      dbmin -450
+      dbmax 600
+      dbvalue.0 450
+    }
+  }
+  control.8 {
+    iface MIXER
+    name 'AIF1 Slot 0 Digital DAC Playback Switch'
+    value.0 true
+    value.1 true
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+  control.9 {
+    iface MIXER
+    name 'AIF1 Data Digital ADC Capture Switch'
+    value.0 false
+    value.1 false
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+  control.10 {
+    iface MIXER
+    name 'DAC Playback Switch'
+    value.0 false
+    value.1 false
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+  control.11 {
+    iface MIXER
+    name 'DAC Reversed Playback Switch'
+    value.0 false
+    value.1 false
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+  control.12 {
+    iface MIXER
+    name 'Mic1 Playback Switch'
+    value.0 false
+    value.1 false
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+  control.13 {
+    iface MIXER
+    name 'Mixer Capture Switch'
+    value.0 false
+    value.1 true
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+  control.14 {
+    iface MIXER
+    name 'Mixer Reversed Capture Switch'
+    value.0 false
+    value.1 true
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+  control.15 {
+    iface MIXER
+    name 'Mic1 Capture Switch'
+    value.0 false
+    value.1 false
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+  control.16 {
+    iface MIXER
+    name 'Headphone Source Playback Route'
+    value.0 DAC
+    value.1 DAC
+    comment {
+      access 'read write'
+      type ENUMERATED
+      count 2
+      item.0 DAC
+      item.1 Mixer
+    }
+  }
+  control.17 {
+    iface MIXER
+    name 'Line Out Source Playback Route'
+    value.0 Stereo
+    value.1 Stereo
+    comment {
+      access 'read write'
+      type ENUMERATED
+      count 2
+      item.0 Stereo
+      item.1 'Mono Differential'
+    }
+  }
+}
+state.allwinnerhdmi {
+  control.1 {
+    iface PCM
+    name 'Playback Channel Map'
+    value.0 0
+    value.1 0
+    value.2 0
+    value.3 0
+    value.4 0
+    value.5 0
+    comment {
+      access read
+      type INTEGER
+      count 6
+      range '0 - 36'
+    }
+  }
+  control.2 {
+    iface PCM
+    name ELD
+    value '0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
+    comment {
+      access 'read volatile'
+      type BYTES
+      count 128
+    }
+  }
+}
+state.sun50ia64audio {
+  control.1 {
+    iface MIXER
+    name 'Headphone Playback Volume'
+    value 0
+    comment {
+      access 'read write'
+      type INTEGER
+      count 1
+      range '0 - 63'
+      dbmin -9999999
+      dbmax 0
+      dbvalue.0 -9999999
+    }
+  }
+  control.2 {
+    iface MIXER
+    name 'Headphone Playback Switch'
+    value.0 false
+    value.1 false
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+  control.3 {
+    iface MIXER
+    name 'Mic1 Playback Volume'
+    value 3
+    comment {
+      access 'read write'
+      type INTEGER
+      count 1
+      range '0 - 7'
+      dbmin -450
+      dbmax 600
+      dbvalue.0 0
+    }
+  }
+  control.4 {
+    iface MIXER
+    name 'Mic1 Boost Volume'
+    value 4
+    comment {
+      access 'read write'
+      type INTEGER
+      count 1
+      range '0 - 7'
+      dbmin 0
+      dbmax 4200
+      dbvalue.0 3300
+    }
+  }
+  control.5 {
+    iface MIXER
+    name 'Mic2 Playback Volume'
+    value 3
+    comment {
+      access 'read write'
+      type INTEGER
+      count 1
+      range '0 - 7'
+      dbmin -450
+      dbmax 600
+      dbvalue.0 0
+    }
+  }
+  control.6 {
+    iface MIXER
+    name 'Mic2 Boost Volume'
+    value 4
+    comment {
+      access 'read write'
+      type INTEGER
+      count 1
+      range '0 - 7'
+      dbmin 0
+      dbmax 4200
+      dbvalue.0 3300
+    }
+  }
+  control.7 {
+    iface MIXER
+    name 'ADC Gain Capture Volume'
+    value 3
+    comment {
+      access 'read write'
+      type INTEGER
+      count 1
+      range '0 - 7'
+      dbmin -450
+      dbmax 600
+      dbvalue.0 0
+    }
+  }
+  control.8 {
+    iface MIXER
+    name 'Line In Playback Volume'
+    value 3
+    comment {
+      access 'read write'
+      type INTEGER
+      count 1
+      range '0 - 7'
+      dbmin -450
+      dbmax 600
+      dbvalue.0 0
+    }
+  }
+  control.9 {
+    iface MIXER
+    name 'Line Out Playback Volume'
+    value 28
+    comment {
+      access 'read write'
+      type INTEGER
+      count 1
+      range '0 - 31'
+      dbmin -9999999
+      dbmax 0
+      dbvalue.0 -450
+    }
+  }
+  control.10 {
+    iface MIXER
+    name 'Line Out Playback Switch'
+    value.0 true
+    value.1 true
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+  control.11 {
+    iface MIXER
+    name 'AIF1 Slot 0 Digital DAC Playback Switch'
+    value.0 true
+    value.1 true
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+  control.12 {
+    iface MIXER
+    name 'AIF1 Data Digital ADC Capture Switch'
+    value.0 true
+    value.1 true
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+  control.13 {
+    iface MIXER
+    name 'Headphone Source Playback Route'
+    value.0 DAC
+    value.1 DAC
+    comment {
+      access 'read write'
+      type ENUMERATED
+      count 2
+      item.0 DAC
+      item.1 Mixer
+    }
+  }
+  control.14 {
+    iface MIXER
+    name 'Line Out Source Playback Route'
+    value.0 Stereo
+    value.1 Stereo
+    comment {
+      access 'read write'
+      type ENUMERATED
+      count 2
+      item.0 Stereo
+      item.1 'Mono Differential'
+    }
+  }
+  control.15 {
+    iface MIXER
+    name 'DAC Playback Switch'
+    value.0 true
+    value.1 true
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+  control.16 {
+    iface MIXER
+    name 'DAC Reversed Playback Switch'
+    value.0 false
+    value.1 false
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+  control.17 {
+    iface MIXER
+    name 'Line In Playback Switch'
+    value.0 false
+    value.1 false
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+  control.18 {
+    iface MIXER
+    name 'Mic1 Playback Switch'
+    value.0 false
+    value.1 false
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+  control.19 {
+    iface MIXER
+    name 'Mic2 Playback Switch'
+    value.0 false
+    value.1 false
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+  control.20 {
+    iface MIXER
+    name 'Mixer Capture Switch'
+    value.0 false
+    value.1 false
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+  control.21 {
+    iface MIXER
+    name 'Mixer Reversed Capture Switch'
+    value.0 false
+    value.1 false
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+  control.22 {
+    iface MIXER
+    name 'Line In Capture Switch'
+    value.0 false
+    value.1 false
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+  control.23 {
+    iface MIXER
+    name 'Mic1 Capture Switch'
+    value.0 true
+    value.1 false
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+  control.24 {
+    iface MIXER
+    name 'Mic2 Capture Switch'
+    value.0 false
+    value.1 true
+    comment {
+      access 'read write'
+      type BOOLEAN
+      count 2
+    }
+  }
+}

packages/bsp/common/usr/lib/armbian/armbian-common

@@ -42,11 +42,11 @@ MACADDR=$(/sbin/ip link | grep -A1 ${DEVNAME} | awk -F" " '/ether / {print $2}')
 
 [[ -z $MACADDR ]] && get_random_mac
 
-if [[ -n $uuid ]]; then
-	nmcli connection modify $uuid ethernet.cloned-mac-address $MACADDR
-	nmcli connection modify $uuid -ethernet.mac-address ""
-	nmcli connection down $uuid >/dev/null 2>&1
-	nmcli connection up $uuid >/dev/null 2>&1
+if [[ -n $UUID ]]; then
+	nmcli connection modify $UUID ethernet.cloned-mac-address $MACADDR
+	nmcli connection modify $UUID -ethernet.mac-address ""
+	nmcli connection down $UUID >/dev/null 2>&1
+	nmcli connection up $UUID >/dev/null 2>&1
 	return 0
 fi
 } # set fixed mac to the 1st active network adapter

packages/bsp/common/usr/lib/armbian/armbian-hardware-optimization

@@ -123,9 +123,7 @@ prepare_board() {
 			for i in $(awk -F':' '/11800000.mali/{print $1}' </proc/interrupts | sed 's/\ //g'); do
 				echo 64 >/proc/irq/$i/smp_affinity
 			done
-			echo 7 >/sys/class/net/eth0/queues/rx-0/rps_cpus
 			echo 32768 >/proc/sys/net/core/rps_sock_flow_entries
-			echo 32768 >/sys/class/net/eth0/queues/rx-0/rps_flow_cnt
 			;;
 		rockchip) # RK3288: usb1 on cpu1, usb3 (EHCI) on cpu2, eth0 and GPU on cpu3
 			echo 2 >/proc/irq/$(awk -F":" "/usb1/ {print \$1}" </proc/interrupts | sed 's/\ //g')/smp_affinity

packages/bsp/helios4/mdadm-fault-led.sh

@@ -26,8 +26,8 @@ if [ $EVENT == "RebuildStarted" ]; then
     echo 1 > $BRIGHTNESS
 fi
 
-# A spare component device which was being rebuilt to replace a faulty device has been successfully rebuilt and has been made active
-if [ $EVENT == "SpareActive" ]; then
+# An md array that was rebuilding, isn't any more, either because it finished normally or was aborted. 
+if [ $EVENT == "RebuildFinished" ]; then
     echo none > $TRIGGER
     echo 0 > $BRIGHTNESS
 fi

packages/bsp/odroid/90-builtin-net-rps.rules

@@ -0,0 +1,5 @@
+# Set up receive packet steering for builtin ethernet
+ACTION=="add", SUBSYSTEMS=="usb", SUBSYSTEM=="net", \
+  ATTRS{idVendor}=="0bda", ATTRS{idProduct}=="8153", \
+  ATTR{queues/rx-0/rps_cpus}="7", ATTR{queues/rx-0/rps_flow_cnt}="32768"
+

patch/kernel/cubox-default/01-v2-05-16-ARM-dts-imx6qdl-sr-som-use-real-iomuxc-values-for-ethernet.patch

@@ -0,0 +1,18 @@
+diff --git a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
+index c1541f2ecf3a..2b332db6c20d 100644
+--- a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
+@@ -116,10 +116,10 @@
+ 				/* AR8035 reset */
+ 				MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x130b0
+ 				/* AR8035 interrupt */
+-				MX6QDL_PAD_DI0_PIN2__GPIO4_IO18		0x80000000
++				MX6QDL_PAD_DI0_PIN2__GPIO4_IO18		0x1b0b0
+ 				/* GPIO16 -> AR8035 25MHz */
+-				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0xc0000000
+-				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x80000000
++				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0b0
++				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x13030
+ 				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+ 				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+ 				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030

patch/kernel/cubox-default/01-v2-06-16-ARM-dts-imx6qdl-sr-som-split-out-Broadcom-Wi-Fi-support.patch

@@ -0,0 +1,338 @@
+diff --git a/arch/arm/boot/dts/imx6dl-cubox-i.dts b/arch/arm/boot/dts/imx6dl-cubox-i.dts
+index 045e59de5ffe..2b1b3e193f53 100644
+--- a/arch/arm/boot/dts/imx6dl-cubox-i.dts
++++ b/arch/arm/boot/dts/imx6dl-cubox-i.dts
+@@ -42,6 +42,7 @@
+ 
+ #include "imx6dl.dtsi"
+ #include "imx6qdl-sr-som.dtsi"
++#include "imx6qdl-sr-som-brcm.dtsi"
+ #include "imx6qdl-cubox-i.dtsi"
+ 
+ / {
+diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts
+index c3b826f4cab9..cbd02eb486e1 100644
+--- a/arch/arm/boot/dts/imx6dl-hummingboard.dts
++++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts
+@@ -43,6 +43,7 @@
+ 
+ #include "imx6dl.dtsi"
+ #include "imx6qdl-sr-som.dtsi"
++#include "imx6qdl-sr-som-brcm.dtsi"
+ #include "imx6qdl-hummingboard.dtsi"
+ 
+ / {
+diff --git a/arch/arm/boot/dts/imx6q-cubox-i.dts b/arch/arm/boot/dts/imx6q-cubox-i.dts
+index b9f581d0fa86..1c7b262e3709 100644
+--- a/arch/arm/boot/dts/imx6q-cubox-i.dts
++++ b/arch/arm/boot/dts/imx6q-cubox-i.dts
+@@ -42,6 +42,7 @@
+ 
+ #include "imx6q.dtsi"
+ #include "imx6qdl-sr-som.dtsi"
++#include "imx6qdl-sr-som-brcm.dtsi"
+ #include "imx6qdl-cubox-i.dtsi"
+ 
+ / {
+diff --git a/arch/arm/boot/dts/imx6q-h100.dts b/arch/arm/boot/dts/imx6q-h100.dts
+index 815e9437e3f0..743c11f1ad4e 100644
+--- a/arch/arm/boot/dts/imx6q-h100.dts
++++ b/arch/arm/boot/dts/imx6q-h100.dts
+@@ -43,6 +43,7 @@
+ 
+ #include "imx6q.dtsi"
+ #include "imx6qdl-sr-som.dtsi"
++#include "imx6qdl-sr-som-brcm.dtsi"
+ 
+ / {
+ 	model = "Auvidea H100";
+diff --git a/arch/arm/boot/dts/imx6q-hummingboard.dts b/arch/arm/boot/dts/imx6q-hummingboard.dts
+index 5f218856c3e5..8c9e94e648a7 100644
+--- a/arch/arm/boot/dts/imx6q-hummingboard.dts
++++ b/arch/arm/boot/dts/imx6q-hummingboard.dts
+@@ -43,6 +43,7 @@
+ 
+ #include "imx6q.dtsi"
+ #include "imx6qdl-sr-som.dtsi"
++#include "imx6qdl-sr-som-brcm.dtsi"
+ #include "imx6qdl-hummingboard.dtsi"
+ 
+ / {
+diff --git a/arch/arm/boot/dts/imx6qdl-sr-som-brcm.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som-brcm.dtsi
+new file mode 100644
+index 000000000000..809d7896775c
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6qdl-sr-som-brcm.dtsi
+@@ -0,0 +1,144 @@
++/*
++ * Copyright (C) 2013,2014 Russell King
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This file is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License
++ *     version 2 as published by the Free Software Foundation.
++ *
++ *     This file is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++#include <dt-bindings/gpio/gpio.h>
++/ {
++	clk_sdio: sdio-clock {
++		compatible = "gpio-gate-clock";
++		#clock-cells = <0>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pinctrl_microsom_brcm_osc>;
++		enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
++	};
++
++	reg_brcm: brcm-reg {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio3 19 0>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pinctrl_microsom_brcm_reg>;
++		regulator-name = "brcm_reg";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		startup-delay-us = <200000>;
++	};
++
++	usdhc1_pwrseq: usdhc1_pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>,
++			      <&gpio6 0 GPIO_ACTIVE_LOW>;
++		clocks = <&clk_sdio>;
++		clock-names = "ext_clock";
++	};
++};
++
++&iomuxc {
++	microsom {
++		pinctrl_microsom_brcm_bt: microsom-brcm-bt {
++			fsl,pins = <
++				MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00	0x40013070
++				MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01	0x40013070
++				MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04	0x40013070
++			>;
++		};
++
++		pinctrl_microsom_brcm_osc: microsom-brcm-osc {
++			fsl,pins = <
++				MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05	0x40013070
++			>;
++		};
++
++		pinctrl_microsom_brcm_reg: microsom-brcm-reg {
++			fsl,pins = <
++				MX6QDL_PAD_EIM_D19__GPIO3_IO19		0x40013070
++			>;
++		};
++
++		pinctrl_microsom_brcm_wifi: microsom-brcm-wifi {
++			fsl,pins = <
++				MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K	0x1b0b0
++				MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20	0x40013070
++				MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26	0x40013070
++				MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27	0x40013070
++			>;
++		};
++
++		pinctrl_microsom_uart4: microsom-uart4 {
++			fsl,pins = <
++				MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
++				MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
++				MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
++				MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
++			>;
++		};
++
++		pinctrl_microsom_usdhc1: microsom-usdhc1 {
++			fsl,pins = <
++				MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17059
++				MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10059
++				MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
++				MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
++				MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
++				MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
++			>;
++		};
++	};
++};
++
++/* UART4 - Connected to optional BRCM Wifi/BT/FM */
++&uart4 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_microsom_brcm_bt &pinctrl_microsom_uart4>;
++	uart-has-rtscts;
++	status = "okay";
++};
++
++/* USDHC1 - Connected to optional BRCM Wifi/BT/FM */
++&usdhc1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_microsom_brcm_wifi &pinctrl_microsom_usdhc1>;
++	bus-width = <4>;
++	mmc-pwrseq = <&usdhc1_pwrseq>;
++	keep-power-in-suspend;
++	no-1-8-v;
++	non-removable;
++	vmmc-supply = <&reg_brcm>;
++	status = "okay";
++};
+diff --git a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
+index 2b332db6c20d..449e241badfe 100644
+--- a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
+@@ -39,35 +39,6 @@
+  *     OTHER DEALINGS IN THE SOFTWARE.
+  */
+ #include <dt-bindings/gpio/gpio.h>
+-/ {
+-	clk_sdio: sdio-clock {
+-		compatible = "gpio-gate-clock";
+-		#clock-cells = <0>;
+-		pinctrl-names = "default";
+-		pinctrl-0 = <&pinctrl_microsom_brcm_osc>;
+-		enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
+-	};
+-
+-	reg_brcm: brcm-reg {
+-		compatible = "regulator-fixed";
+-		enable-active-high;
+-		gpio = <&gpio3 19 0>;
+-		pinctrl-names = "default";
+-		pinctrl-0 = <&pinctrl_microsom_brcm_reg>;
+-		regulator-name = "brcm_reg";
+-		regulator-min-microvolt = <3300000>;
+-		regulator-max-microvolt = <3300000>;
+-		startup-delay-us = <200000>;
+-	};
+-
+-	usdhc1_pwrseq: usdhc1_pwrseq {
+-		compatible = "mmc-pwrseq-simple";
+-		reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>,
+-			      <&gpio6 0 GPIO_ACTIVE_LOW>;
+-		clocks = <&clk_sdio>;
+-		clock-names = "ext_clock";
+-	};
+-};
+ 
+ &fec {
+ 	pinctrl-names = "default";
+@@ -80,35 +51,6 @@
+ 
+ &iomuxc {
+ 	microsom {
+-		pinctrl_microsom_brcm_bt: microsom-brcm-bt {
+-			fsl,pins = <
+-				MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00	0x40013070
+-				MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01	0x40013070
+-				MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04	0x40013070
+-			>;
+-		};
+-
+-		pinctrl_microsom_brcm_osc: microsom-brcm-osc {
+-			fsl,pins = <
+-				MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05	0x40013070
+-			>;
+-		};
+-
+-		pinctrl_microsom_brcm_reg: microsom-brcm-reg {
+-			fsl,pins = <
+-				MX6QDL_PAD_EIM_D19__GPIO3_IO19		0x40013070
+-			>;
+-		};
+-
+-		pinctrl_microsom_brcm_wifi: microsom-brcm-wifi {
+-			fsl,pins = <
+-				MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K	0x1b0b0
+-				MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20	0x40013070
+-				MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26	0x40013070
+-				MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27	0x40013070
+-			>;
+-		};
+-
+ 		pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 {
+ 			fsl,pins = <
+ 				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b8b0
+@@ -159,26 +101,6 @@
+ 				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
+ 			>;
+ 		};
+-
+-		pinctrl_microsom_uart4: microsom-uart4 {
+-			fsl,pins = <
+-				MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
+-				MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
+-				MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
+-				MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
+-			>;
+-		};
+-
+-		pinctrl_microsom_usdhc1: microsom-usdhc1 {
+-			fsl,pins = <
+-				MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17059
+-				MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10059
+-				MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+-				MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+-				MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+-				MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+-			>;
+-		};
+ 	};
+ };
+ 
+@@ -187,24 +109,3 @@
+ 	pinctrl-0 = <&pinctrl_microsom_uart1>;
+ 	status = "okay";
+ };
+-
+-/* UART4 - Connected to optional BRCM Wifi/BT/FM */
+-&uart4 {
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&pinctrl_microsom_brcm_bt &pinctrl_microsom_uart4>;
+-	uart-has-rtscts;
+-	status = "okay";
+-};
+-
+-/* USDHC1 - Connected to optional BRCM Wifi/BT/FM */
+-&usdhc1 {
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&pinctrl_microsom_brcm_wifi &pinctrl_microsom_usdhc1>;
+-	bus-width = <4>;
+-	mmc-pwrseq = <&usdhc1_pwrseq>;
+-	keep-power-in-suspend;
+-	no-1-8-v;
+-	non-removable;
+-	vmmc-supply = <&reg_brcm>;
+-	status = "okay";
+-};

patch/kernel/cubox-default/01-v2-08-16-ARM-dts-imx6qdl-sr-som-add-3.3V-vcc-regulator.patch

@@ -0,0 +1,21 @@
+diff --git a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
+index 449e241badfe..4ccb7afc4b35 100644
+--- a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
+@@ -40,6 +40,16 @@
+  */
+ #include <dt-bindings/gpio/gpio.h>
+ 
++/ {
++	vcc_3v3: regulator-vcc-3v3 {
++		compatible = "regulator-fixed";
++		regulator-always-on;
++		regulator-name = "vcc_3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++	};
++};
++
+ &fec {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;

patch/kernel/cubox-default/Linux4.14-001-ALSA:_usb-audio:_Add_native_DSD_support_for_Mytek_DACs.patch

@@ -0,0 +1,72 @@
+From 165a0d29ca8bae890e2f2767af83b09d61f33553 Mon Sep 17 00:00:00 2001
+From: Jussi Laako <jussi@sonarnerd.net>
+Date: Wed, 13 Jun 2018 01:43:01 +0300
+Subject: [PATCH] ALSA: usb-audio: Add native DSD support for Mytek DACs
+
+commit 3a572d94bcff98a14c94fe686881a169a26f3fca upstream.
+
+Add new mostly generic code with Mytek VID to support native DSD mode.
+
+This implementation should be easier to maintain when manufacturers
+release new products.
+
+Signed-off-by: Jussi Laako <jussi@sonarnerd.net>
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+---
+ sound/usb/card.h   |  1 +
+ sound/usb/format.c |  5 ++++-
+ sound/usb/quirks.c | 13 +++++++++++++
+ 3 files changed, 18 insertions(+), 1 deletion(-)
+
+diff --git a/sound/usb/card.h b/sound/usb/card.h
+index ed87cc83eb47d..2f4801cdc01d4 100644
+--- a/sound/usb/card.h
++++ b/sound/usb/card.h
+@@ -32,6 +32,7 @@ struct audioformat {
+ 	struct snd_pcm_chmap_elem *chmap; /* (optional) channel map */
+ 	bool dsd_dop;			/* add DOP headers in case of DSD samples */
+ 	bool dsd_bitrev;		/* reverse the bits of each DSD sample */
++	bool dsd_raw;			/* altsetting is raw DSD */
+ };
+ 
+ struct snd_usb_substream;
+diff --git a/sound/usb/format.c b/sound/usb/format.c
+index 2c44386e5569f..916ff842c4375 100644
+--- a/sound/usb/format.c
++++ b/sound/usb/format.c
+@@ -63,8 +63,11 @@ static u64 parse_audio_format_i_type(struct snd_usb_audio *chip,
+ 		sample_width = fmt->bBitResolution;
+ 		sample_bytes = fmt->bSubslotSize;
+ 
+-		if (format & UAC2_FORMAT_TYPE_I_RAW_DATA)
++		if (format & UAC2_FORMAT_TYPE_I_RAW_DATA) {
+ 			pcm_formats |= SNDRV_PCM_FMTBIT_SPECIAL;
++			/* flag potentially raw DSD capable altsettings */
++			fp->dsd_raw = true;
++		}
+ 
+ 		format <<= 1;
+ 		break;
+diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c
+index ad14d6b78bdcf..da6fd90360a8a 100644
+--- a/sound/usb/quirks.c
++++ b/sound/usb/quirks.c
+@@ -1411,5 +1411,18 @@ u64 snd_usb_interface_dsd_format_quirks(struct snd_usb_audio *chip,
+ 			return SNDRV_PCM_FMTBIT_DSD_U32_BE;
+ 	}
+ 
++	/* Mostly generic method to detect many DSD-capable implementations -
++	 * from XMOS/Thesycon
++	 */
++	switch (USB_ID_VENDOR(chip->usb_id)) {
++	case 0x25ce:  /* Mytek devices */
++		if (fp->dsd_raw)
++			return SNDRV_PCM_FMTBIT_DSD_U32_BE;
++		break;
++	default:
++		break;
++
++	}
++
+ 	return 0;
+ }

patch/kernel/cubox-default/Linux4.14-002-ALSA:_usb-audio:_generic_DSD_detection_for_XMOS-based_implementations.patch

@@ -0,0 +1,72 @@
+From: Gé Koerkamp <ge.koerkamp@gmail.com>
+Date: Thu, 27 Dec 2018 20:30:08 +0000
+Subject: [PATCH] ALSA: usb-audio: generic DSD detection for XMOS-based implementations
+
+This is the second half of the USB Audio patch for 4.14.90
+See the preceding back-port "ALSA:_usb-audio:_Add_native_DSD_support_for_Mytek_DACs"
+
+This patch adds support for a range of popular USB DAc's with DSD-direct (native DSD) capabilities.
+
+Signed-off-by: Gé Koerkamp <ge.koerkamp@gmail.com>
+---
+ sound/usb/quirks.c | 27 +++++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c
+index da6fd90360a8a..1c990a3e8fa9c 100644
+--- a/sound/usb/quirks.c
++++ b/sound/usb/quirks.c
+@@ -1356,19 +1356,44 @@ u64 snd_usb_interface_dsd_format_quirks(struct snd_usb_audio *chip,
+ 	/* XMOS based USB DACs */
+ 	switch (chip->usb_id) {
+ 	case USB_ID(0x20b1, 0x3008): /* iFi Audio micro/nano iDSD */
++	case USB_ID(0x1511, 0x0037): /* AURALiC VEGA */
++	case USB_ID(0x20b1, 0x0002): /* Wyred 4 Sound DAC-2 DSD */
++	case USB_ID(0x20b1, 0x2004): /* Matrix Audio X-SPDIF 2 */
+ 	case USB_ID(0x20b1, 0x2008): /* Matrix Audio X-Sabre */
+ 	case USB_ID(0x20b1, 0x300a): /* Matrix Audio Mini-i Pro */
+ 	case USB_ID(0x22d9, 0x0416): /* OPPO HA-1 */
++	case USB_ID(0x22d9, 0x0436): /* OPPO Sonica */
++	case USB_ID(0x22d9, 0x0461): /* OPPO UDP-205 */
++	case USB_ID(0x2522, 0x0012): /* LH Labs VI DAC Infinity */
+ 	case USB_ID(0x2772, 0x0230): /* Pro-Ject Pre Box S2 Digital */
+ 		if (fp->altsetting == 2)
+ 			return SNDRV_PCM_FMTBIT_DSD_U32_BE;
+ 		break;
+ 
++	case USB_ID(0x152a, 0x85de): /* SMSL D1 DAC */
++	case USB_ID(0x16d0, 0x09dd): /* Encore mDSD */
++	case USB_ID(0x0d8c, 0x0316): /* Hegel HD12 DSD */
++	case USB_ID(0x16b0, 0x06b2): /* NuPrime DAC-10 */
++	case USB_ID(0x16d0, 0x0733): /* Furutech ADL Stratos */
++	case USB_ID(0x16d0, 0x09db): /* NuPrime Audio DAC-9 */
++	case USB_ID(0x1db5, 0x0003): /* Bryston BDA3 */
+ 	case USB_ID(0x20b1, 0x000a): /* Gustard DAC-X20U */
++	case USB_ID(0x20b1, 0x2005): /* Denafrips Ares DAC */
+ 	case USB_ID(0x20b1, 0x2009): /* DIYINHK DSD DXD 384kHz USB to I2S/DSD */
+ 	case USB_ID(0x20b1, 0x2023): /* JLsounds I2SoverUSB */
++	case USB_ID(0x20b1, 0x3021): /* Eastern El. MiniMax Tube DAC Supreme */
+ 	case USB_ID(0x20b1, 0x3023): /* Aune X1S 32BIT/384 DSD DAC */
++	case USB_ID(0x20b1, 0x302d): /* Unison Research Unico CD Due */
++	case USB_ID(0x20b1, 0x307b): /* CH Precision C1 DAC */
++	case USB_ID(0x20b1, 0x3086): /* Singxer F-1 converter board */
++	case USB_ID(0x22d9, 0x0426): /* OPPO HA-2 */
++	case USB_ID(0x22e1, 0xca01): /* HDTA Serenade DSD */
++	case USB_ID(0x249c, 0x9326): /* M2Tech Young MkIII */
+ 	case USB_ID(0x2616, 0x0106): /* PS Audio NuWave DAC */
++	case USB_ID(0x2622, 0x0041): /* Audiolab M-DAC+ */
++	case USB_ID(0x27f7, 0x3002): /* W4S DAC-2v2SE */
++	case USB_ID(0x29a2, 0x0086): /* Mutec MC3+ USB */
++	case USB_ID(0x6b42, 0x0042): /* MSB Technology */
+ 		if (fp->altsetting == 3)
+ 			return SNDRV_PCM_FMTBIT_DSD_U32_BE;
+ 		break;
+@@ -1415,6 +1440,8 @@ u64 snd_usb_interface_dsd_format_quirks(struct snd_usb_audio *chip,
+ 	 * from XMOS/Thesycon
+ 	 */
+ 	switch (USB_ID_VENDOR(chip->usb_id)) {
++	case 0x20b1:  /* XMOS based devices */
++	case 0x152a:  /* Thesycon devices */
+ 	case 0x25ce:  /* Mytek devices */
+ 		if (fp->dsd_raw)
+ 			return SNDRV_PCM_FMTBIT_DSD_U32_BE;

patch/kernel/meson64-default/board-potato-add-i2c-ao.patch

@@ -0,0 +1,17 @@
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
+index c5c7f765b..3261cb10a 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
+@@ -200,6 +200,12 @@
+ 	};
+ };
+ 
++&i2c_AO {
++	status = "okay";
++	pinctrl-0 = <&i2c_ao_pins>;
++	pinctrl-names = "default";
++};
++
+ &pinctrl_aobus {
+ 	gpio-line-names = "UART TX",
+ 			  "UART RX",

patch/kernel/mvebu64-next/2001-clk_mvebu_armada-37xx-tbg_Switch_to_clk_get_and_balance_it_in_probe.patch

@@ -0,0 +1,40 @@
+From 480d99fdc3eee31a23c317927a335e9a71c2904f Mon Sep 17 00:00:00 2001
+From: Gregory CLEMENT <gregory.clement@bootlin.com>
+Date: Wed, 10 Oct 2018 20:18:38 +0200
+Subject: clk: mvebu: armada-37xx-tbg: Switch to clk_get and balance it in
+ probe
+
+The parent clock is get only to have its name, and then the clock is no
+more used, so we can safely free it using clk_put. Furthermore as between
+the successful devm_clk_get() and the devm_clk_put() call we don't exit
+the probe function in error so I can use non managed version of clk_get()
+and clk_put().
+
+Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/mvebu/armada-37xx-tbg.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/mvebu/armada-37xx-tbg.c b/drivers/clk/mvebu/armada-37xx-tbg.c
+index 7ff041f73b55..4de15d44a0c1 100644
+--- a/drivers/clk/mvebu/armada-37xx-tbg.c
++++ b/drivers/clk/mvebu/armada-37xx-tbg.c
+@@ -99,12 +99,13 @@ static int armada_3700_tbg_clock_probe(struct platform_device *pdev)
+ 	hw_tbg_data->num = NUM_TBG;
+ 	platform_set_drvdata(pdev, hw_tbg_data);
+ 
+-	parent = devm_clk_get(dev, NULL);
++	parent = clk_get(dev, NULL);
+ 	if (IS_ERR(parent)) {
+ 		dev_err(dev, "Could get the clock parent\n");
+ 		return -EINVAL;
+ 	}
+ 	parent_name = __clk_get_name(parent);
++	clk_put(parent);
+ 
+ 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ 	reg = devm_ioremap_resource(dev, res);
+-- 
+cgit 1.2-0.3.lf.el7
+

patch/kernel/mvebu64-next/2002-clk_mvebu_armada-37xx-periph_save_the_IP_base_address_in_the_driver_data.patch

@@ -0,0 +1,70 @@
+From d9d95e78cff80c3fe43e757ba90644cd766302ac Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal@bootlin.com>
+Date: Fri, 13 Jul 2018 15:44:45 +0200
+Subject: clk: mvebu: armada-37xx-periph: save the IP base address in the
+ driver data
+
+Prepare the introduction of suspend/resume hooks by having an easy way
+to access all the registers in one go just from a device: add the IP
+base address in the driver data.
+
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/mvebu/armada-37xx-periph.c | 15 +++++++--------
+ 1 file changed, 7 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c
+index 499f5962c8b0..78048c2e3774 100644
+--- a/drivers/clk/mvebu/armada-37xx-periph.c
++++ b/drivers/clk/mvebu/armada-37xx-periph.c
+@@ -56,6 +56,7 @@
+ struct clk_periph_driver_data {
+ 	struct clk_hw_onecell_data *hw_data;
+ 	spinlock_t lock;
++	void __iomem *reg;
+ };
+ 
+ struct clk_double_div {
+@@ -680,7 +681,6 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev)
+ 	struct device *dev = &pdev->dev;
+ 	int num_periph = 0, i, ret;
+ 	struct resource *res;
+-	void __iomem *reg;
+ 
+ 	data = of_device_get_match_data(dev);
+ 	if (!data)
+@@ -689,11 +689,6 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev)
+ 	while (data[num_periph].name)
+ 		num_periph++;
+ 
+-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+-	reg = devm_ioremap_resource(dev, res);
+-	if (IS_ERR(reg))
+-		return PTR_ERR(reg);
+-
+ 	driver_data = devm_kzalloc(dev, sizeof(*driver_data), GFP_KERNEL);
+ 	if (!driver_data)
+ 		return -ENOMEM;
+@@ -706,12 +701,16 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev)
+ 		return -ENOMEM;
+ 	driver_data->hw_data->num = num_periph;
+ 
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	driver_data->reg = devm_ioremap_resource(dev, res);
++	if (IS_ERR(driver_data->reg))
++		return PTR_ERR(driver_data->reg);
++
+ 	spin_lock_init(&driver_data->lock);
+ 
+ 	for (i = 0; i < num_periph; i++) {
+ 		struct clk_hw **hw = &driver_data->hw_data->hws[i];
+-
+-		if (armada_3700_add_composite_clk(&data[i], reg,
++		if (armada_3700_add_composite_clk(&data[i], driver_data->reg,
+ 						  &driver_data->lock, dev, hw))
+ 			dev_err(dev, "Can't register periph clock %s\n",
+ 				data[i].name);
+-- 
+cgit 1.2-0.3.lf.el7
+

patch/kernel/mvebu64-next/2003-clk_mvebu_armada-37xx-periph_add_suspend_resume_support.patch

@@ -0,0 +1,92 @@
+From 5beb1e60dba973e0b9cfb54d9735d5d4385b9d90 Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal@bootlin.com>
+Date: Fri, 13 Jul 2018 15:44:46 +0200
+Subject: clk: mvebu: armada-37xx-periph: add suspend/resume support
+
+Add suspend/resume hooks in Armada 37xx peripheral clocks driver to
+handle S2RAM operations.
+
+One can think that these hooks are useless by comparing the register
+values before and after a suspend/resume cycle: they will look the same
+anyway. This is because of some scripts executed by the Cortex-M3 core
+during ATF operations to init both the clocks and the DDR. These values
+could be modified by the BL33 stage or by Linux itself and should be
+preserved.
+
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/mvebu/armada-37xx-periph.c | 43 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 43 insertions(+)
+
+diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c
+index 78048c2e3774..1f1cff428d78 100644
+--- a/drivers/clk/mvebu/armada-37xx-periph.c
++++ b/drivers/clk/mvebu/armada-37xx-periph.c
+@@ -57,6 +57,14 @@ struct clk_periph_driver_data {
+ 	struct clk_hw_onecell_data *hw_data;
+ 	spinlock_t lock;
+ 	void __iomem *reg;
++
++	/* Storage registers for suspend/resume operations */
++	u32 tbg_sel;
++	u32 div_sel0;
++	u32 div_sel1;
++	u32 div_sel2;
++	u32 clk_sel;
++	u32 clk_dis;
+ };
+ 
+ struct clk_double_div {
+@@ -673,6 +681,40 @@ static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
+ 	return PTR_ERR_OR_ZERO(*hw);
+ }
+ 
++static int __maybe_unused armada_3700_periph_clock_suspend(struct device *dev)
++{
++	struct clk_periph_driver_data *data = dev_get_drvdata(dev);
++
++	data->tbg_sel = readl(data->reg + TBG_SEL);
++	data->div_sel0 = readl(data->reg + DIV_SEL0);
++	data->div_sel1 = readl(data->reg + DIV_SEL1);
++	data->div_sel2 = readl(data->reg + DIV_SEL2);
++	data->clk_sel = readl(data->reg + CLK_SEL);
++	data->clk_dis = readl(data->reg + CLK_DIS);
++
++	return 0;
++}
++
++static int __maybe_unused armada_3700_periph_clock_resume(struct device *dev)
++{
++	struct clk_periph_driver_data *data = dev_get_drvdata(dev);
++
++	/* Follow the same order than what the Cortex-M3 does (ATF code) */
++	writel(data->clk_dis, data->reg + CLK_DIS);
++	writel(data->div_sel0, data->reg + DIV_SEL0);
++	writel(data->div_sel1, data->reg + DIV_SEL1);
++	writel(data->div_sel2, data->reg + DIV_SEL2);
++	writel(data->tbg_sel, data->reg + TBG_SEL);
++	writel(data->clk_sel, data->reg + CLK_SEL);
++
++	return 0;
++}
++
++static const struct dev_pm_ops armada_3700_periph_clock_pm_ops = {
++	SET_SYSTEM_SLEEP_PM_OPS(armada_3700_periph_clock_suspend,
++				armada_3700_periph_clock_resume)
++};
++
+ static int armada_3700_periph_clock_probe(struct platform_device *pdev)
+ {
+ 	struct clk_periph_driver_data *driver_data;
+@@ -748,6 +790,7 @@ static struct platform_driver armada_3700_periph_clock_driver = {
+ 	.driver		= {
+ 		.name	= "marvell-armada-3700-periph-clock",
+ 		.of_match_table = armada_3700_periph_clock_of_match,
++		.pm	= &armada_3700_periph_clock_pm_ops,
+ 	},
+ };
+ 
+-- 
+cgit 1.2-0.3.lf.el7
+

patch/kernel/rockchip-dev/2018-ARM-DTS-rk3288-tinker-Defining-the-SPI-interface.patch

@@ -1,49 +0,0 @@
-From 14f951ca2d354ad8fd068d0f3d8648d5c0d1e60e Mon Sep 17 00:00:00 2001
-From: Myy Miouyouyou <myy@miouyouyou.fr>
-Date: Thu, 19 Oct 2017 22:40:26 +0200
-Subject: [PATCH 23/28] ARM: DTS: rk3288-tinker.dts: Defining the SPI interface
-
-Taken from, and tested by @TonyMac32 .
-
-Well, the original one was tested by him but I had to adapt the
-registers definitions to the new 64-bits LPAE-compliant syntax.
-
-Therefore that *might* break, along with a few other patches.
-
-Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
----
- arch/arm/boot/dts/rk3288-tinker.dts | 18 ++++++++++++++++++
- 1 file changed, 18 insertions(+)
-
-diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
-index 6f4c0843..f4b4525c 100644
---- a/arch/arm/boot/dts/rk3288-tinker.dts
-+++ b/arch/arm/boot/dts/rk3288-tinker.dts
-@@ -471,6 +471,24 @@
- 
- };
- 
-+&spi2 {
-+	status = "okay";
-+	max-freq = <50000000>;
-+	spidev@0 {
-+		compatible = "rockchip,spi_tinker";
-+		reg = <0>;
-+		spi-max-frequency = <50000000>;
-+		spi-cpha = <1>;
-+	};
-+	spidev@1 {
-+		compatible = "rockchip,spi_tinker";
-+		reg = <1>;
-+		spi-max-frequency = <50000000>;
-+		spi-cpha = <1>;
-+	};
-+};
-+
-+
- &pinctrl {
- 	pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
- 		drive-strength = <8>;
--- 
-2.11.0
-

patch/kernel/rockchip-dev/general-add-overlays.patch

@@ -12,15 +12,54 @@ index 6d4ff8cdf..2d0b2f4c4 100644
  dtb-$(CONFIG_ARCH_S3C24XX) += \
  	s3c2416-smdk2416.dtb
  dtb-$(CONFIG_ARCH_S3C64XX) += \
+diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
+index d0961c35d..994f60a55 100644
+--- a/arch/arm/boot/dts/rk3288-tinker.dts
++++ b/arch/arm/boot/dts/rk3288-tinker.dts
+@@ -579,19 +579,19 @@
+ };
+ 
+ &uart1 {
+-	status = "okay";
++	status = "disabled";
+ };
+ 
+ &uart2 {
+-	status = "okay";
++	status = "disabled";
+ };
+ 
+ &uart3 {
+-	status = "okay";
++	status = "disabled";
+ };
+ 
+ &uart4 {
+-	status = "okay";
++	status = "disabled";
+ };
+ 
+ &usbphy {
 diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile
 new file mode 100644
-index 000000000..b95172d18
+index 000000000..207eb4789
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/Makefile
-@@ -0,0 +1,15 @@
+@@ -0,0 +1,26 @@
 +# SPDX-License-Identifier: GPL-2.0
 +dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
-+	rockchip-ds1307.dtbo
++	rockchip-ds1307.dtbo	\
++	rockchip-i2c1.dtbo	\
++	rockchip-i2c4.dtbo	\
++	rockchip-spi0.dtbo	\
++	rockchip-spi2.dtbo	\
++	rockchip-spidev0.dtbo	\
++	rockchip-spidev2.dtbo	\
++	rockchip-uart1.dtbo	\
++	rockchip-uart2.dtbo	\
++	rockchip-uart3.dtbo	\
++	rockchip-uart4.dtbo	\
++	rockchip-w1-gpio.dtbo
 +
 +scr-$(CONFIG_ARCH_ROCKCHIP) += \
 +       rockchip-fixup.scr
@@ -35,10 +74,10 @@ index 000000000..b95172d18
 +
 diff --git a/arch/arm/boot/dts/overlay/README.rockchip-overlays b/arch/arm/boot/dts/overlay/README.rockchip-overlays
 new file mode 100644
-index 000000000..ca8d80af1
+index 000000000..c6f331542
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/README.rockchip-overlays
-@@ -0,0 +1,18 @@
+@@ -0,0 +1,78 @@
 +This document describes overlays provided in the kernel packages
 +For generic Armbian overlays documentation please see
 +https://docs.armbian.com/User-Guide_Allwinner_overlays/
@@ -50,6 +89,17 @@ index 000000000..ca8d80af1
 +### Provided overlays:
 +
 +- ds1307
++- i2c1
++- i2c4
++- spi0
++- spi2
++- spidev0
++- spidev2
++- uart1
++- uart2
++- uart3
++- uart4
++- w1-gpio
 +
 +### Overlay details:
 +
@@ -57,13 +107,65 @@ index 000000000..ca8d80af1
 +
 +Activates ds1307 rtc on i2c1
 +
++### i2c1
++
++Activate i2c1
++
++### i2c4
++
++Activate i2c4
++
++### spi0
++
++Activate spi0
++conflicts with uart4
++
++### spi2
++
++Activate spi2
++
++### spidev0
++
++Activate spidev on spi0
++Depends on spi0
++
++### spidev2
++
++Activate spidev on spi2
++depends on spi2
++
++### uart1
++
++Activate uart1
++
++### uart2
++
++Activate uart2
++
++### uart3
++
++Activate uart3
++
++### uart4
++
++Activate uart4
++Conflicts with spi0
++
++### w1-gpio
++
++Activates 1-wire gpio master on GPIO0 17
++
++
 diff --git a/arch/arm/boot/dts/overlay/rockchip-ds1307.dts b/arch/arm/boot/dts/overlay/rockchip-ds1307.dts
 new file mode 100644
-index 000000000..e60a37e0f
+index 000000000..af240e46b
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/rockchip-ds1307.dts
-@@ -0,0 +1,17 @@
-+// Definitions for ds1307
+@@ -0,0 +1,21 @@
++/* 	Definitions for ds1307
++*	From ASUS: https://github.com/TinkerBoard/debian_kernel/commits/develop/arch/arm/boot/dts/overlays/ds1307-overlay.dts
++*/
++
 +/dts-v1/;
 +/plugin/;
 +
@@ -75,6 +177,7 @@ index 000000000..e60a37e0f
 +		__overlay__ {
 +			rtc: ds1307@68 {
 +				compatible = "dallas,ds1307";
++				reg = <0x68>;
 +				status = "okay";
 +			};
 +		};
@@ -90,75 +193,218 @@ index 000000000..d4c39e20a
 +# implements (or rather substitutes) overlay arguments functionality
 +# using u-boot scripting, environment variables and "fdt" command
 +
-diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
-index db7399a49..6f14d9c7b 100644
---- a/scripts/Makefile.lib
-+++ b/scripts/Makefile.lib
-@@ -61,6 +61,9 @@ real-obj-m := $(foreach m, $(obj-m), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))
- extra-y				+= $(dtb-y)
- extra-$(CONFIG_OF_ALL_DTBS)	+= $(dtb-)
- 
-+# Overlay targets
-+extra-y				+= $(dtbo-y) $(scr-y) $(dtbotxt-y)
-+
- # Add subdir path
- 
- extra-y		:= $(addprefix $(obj)/,$(extra-y))
-diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile
-index b95172d18..f1c792059 100644
---- a/arch/arm/boot/dts/overlay/Makefile
-+++ b/arch/arm/boot/dts/overlay/Makefile
-@@ -1,6 +1,7 @@
- # SPDX-License-Identifier: GPL-2.0
- dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
--	rockchip-ds1307.dtbo
-+	rockchip-ds1307.dtbo	\
-+	rockchip-w1-gpio.dtbo
- 
- scr-$(CONFIG_ARCH_ROCKCHIP) += \
-        rockchip-fixup.scr
-diff --git a/arch/arm/boot/dts/overlay/README.rockchip-overlays b/arch/arm/boot/dts/overlay/README.rockchip-overlays
-index ca8d80af1..14b22cc0c 100644
---- a/arch/arm/boot/dts/overlay/README.rockchip-overlays
-+++ b/arch/arm/boot/dts/overlay/README.rockchip-overlays
-@@ -9,6 +9,7 @@ rockchip (Rockchip)
- ### Provided overlays:
- 
- - ds1307
-+- w1-gpio
- 
- ### Overlay details:
- 
-@@ -16,3 +17,8 @@ rockchip (Rockchip)
- 
- Activates ds1307 rtc on i2c1
- 
-+### w1-gpio
-+
-+Activates 1-wire gpio master on GPIO0 17
-+
-+
-diff --git a/arch/arm/boot/dts/overlay/rockchip-ds1307.dts b/arch/arm/boot/dts/overlay/rockchip-ds1307.dts
-index e60a37e0f..af240e46b 100644
---- a/arch/arm/boot/dts/overlay/rockchip-ds1307.dts
-+++ b/arch/arm/boot/dts/overlay/rockchip-ds1307.dts
-@@ -1,4 +1,7 @@
--// Definitions for ds1307
-+/* 	Definitions for ds1307
-+*	From ASUS: https://github.com/TinkerBoard/debian_kernel/commits/develop/arch/arm/boot/dts/overlays/ds1307-overlay.dts
+diff --git a/arch/arm/boot/dts/overlay/rockchip-spi0.dts b/arch/arm/boot/dts/overlay/rockchip-spi0.dts
+new file mode 100644
+index 000000000..cde22beb1
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rockchip-spi0.dts
+@@ -0,0 +1,17 @@
++/* 	Definitions for spi0
 +*/
 +
- /dts-v1/;
- /plugin/;
- 
-@@ -10,6 +13,7 @@
- 		__overlay__ {
- 			rtc: ds1307@68 {
- 				compatible = "dallas,ds1307";
-+				reg = <0x68>;
- 				status = "okay";
- 			};
- 		};
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "rockchip,rk3288-miniarm", "rockchip,rk3288";
++
++	fragment@0 {
++		target = <&spi0>;
++		__overlay__ {
++			status = "okay";
++			max-freq = <50000000>;
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/overlay/rockchip-spi2.dts b/arch/arm/boot/dts/overlay/rockchip-spi2.dts
+new file mode 100644
+index 000000000..dcbfd8ad6
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rockchip-spi2.dts
+@@ -0,0 +1,17 @@
++/* 	Definitions for spi2
++*/
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "rockchip,rk3288-miniarm", "rockchip,rk3288";
++
++	fragment@0 {
++		target = <&spi2>;
++		__overlay__ {
++			status = "okay";
++			max-freq = <50000000>;
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/overlay/rockchip-spidev0.dts b/arch/arm/boot/dts/overlay/rockchip-spidev0.dts
+new file mode 100644
+index 000000000..6f4565761
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rockchip-spidev0.dts
+@@ -0,0 +1,33 @@
++/* Definition for SPI0 Spidev
++ * spi port for Tinker Board
++ */
++
++/dts-v1/;
++/plugin/;
++
++/{
++	compatible = "rockchip,rk3288-miniarm", "rockchip,rk3288";
++
++	fragment@0 {
++		
++		target = <&spi0>;
++		__overlay__ {
++
++			spidev@0 {
++				compatible = "rockchip,spi_tinker";
++				reg = <0>;
++				spi-max-frequency = <50000000>;
++				spi-cpha = <1>;
++				status = "okay";
++			};
++	
++			spidev@1 {
++				compatible = "rockchip,spi_tinker";
++				reg = <1>;
++				spi-max-frequency = <50000000>;
++				spi-cpha = <1>;
++				status = "okay";
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/overlay/rockchip-spidev2.dts b/arch/arm/boot/dts/overlay/rockchip-spidev2.dts
+new file mode 100644
+index 000000000..bdaf0bd77
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rockchip-spidev2.dts
+@@ -0,0 +1,33 @@
++/* Definition for SPI2 Spidev
++ * spi port for Tinker Board
++ */
++
++/dts-v1/;
++/plugin/;
++
++/{
++	compatible = "rockchip,rk3288-miniarm", "rockchip,rk3288";
++
++	fragment@0 {
++		
++		target = <&spi2>;
++		__overlay__ {
++
++			spidev@0 {
++				compatible = "rockchip,spi_tinker";
++				reg = <0>;
++				spi-max-frequency = <50000000>;
++				spi-cpha = <1>;
++				status = "okay";
++			};
++	
++			spidev@1 {
++				compatible = "rockchip,spi_tinker";
++				reg = <1>;
++				spi-max-frequency = <50000000>;
++				spi-cpha = <1>;
++				status = "okay";
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/overlay/rockchip-uart1.dts b/arch/arm/boot/dts/overlay/rockchip-uart1.dts
+new file mode 100644
+index 000000000..8d6b28a9d
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rockchip-uart1.dts
+@@ -0,0 +1,16 @@
++/* 	Definitions for uart1
++*/
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "rockchip,rk3288-miniarm", "rockchip,rk3288";
++
++	fragment@0 {
++		target = <&uart1>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/overlay/rockchip-uart2.dts b/arch/arm/boot/dts/overlay/rockchip-uart2.dts
+new file mode 100644
+index 000000000..875de3c66
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rockchip-uart2.dts
+@@ -0,0 +1,16 @@
++/* 	Definitions for uart2
++*/
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "rockchip,rk3288-miniarm", "rockchip,rk3288";
++
++	fragment@0 {
++		target = <&uart2>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/overlay/rockchip-uart3.dts b/arch/arm/boot/dts/overlay/rockchip-uart3.dts
+new file mode 100644
+index 000000000..ccc51248a
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rockchip-uart3.dts
+@@ -0,0 +1,16 @@
++/* 	Definitions for uart3
++*/
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "rockchip,rk3288-miniarm", "rockchip,rk3288";
++
++	fragment@0 {
++		target = <&uart3>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/overlay/rockchip-uart4.dts b/arch/arm/boot/dts/overlay/rockchip-uart4.dts
+new file mode 100644
+index 000000000..cc9f84ae8
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rockchip-uart4.dts
+@@ -0,0 +1,16 @@
++/* 	Definitions for uart4
++*/
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "rockchip,rk3288-miniarm", "rockchip,rk3288";
++
++	fragment@0 {
++		target = <&uart4>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
 diff --git a/arch/arm/boot/dts/overlay/rockchip-w1-gpio.dts b/arch/arm/boot/dts/overlay/rockchip-w1-gpio.dts
 new file mode 100644
 index 000000000..02bb81a1e
@@ -198,3 +444,70 @@ index 000000000..02bb81a1e
 +        };
 +    };
 +};
+diff --git a/arch/arm/boot/dts/overlay/rockchip-i2c1.dts b/arch/arm/boot/dts/overlay/rockchip-i2c1.dts
+new file mode 100644
+index 000000000..12064d4d2
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rockchip-i2c1.dts
+@@ -0,0 +1,16 @@
++/* 	Definitions for i2c1
++*/
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "rockchip,rk3288-miniarm", "rockchip,rk3288";
++
++	fragment@0 {
++		target = <&i2c1>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/overlay/rockchip-i2c4.dts b/arch/arm/boot/dts/overlay/rockchip-i2c4.dts
+new file mode 100644
+index 000000000..b399ecbd8
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rockchip-i2c4.dts
+@@ -0,0 +1,16 @@
++/* 	Definitions for i2c4
++*/
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "rockchip,rk3288-miniarm", "rockchip,rk3288";
++
++	fragment@0 {
++		target = <&i2c4>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
+index 994f60a55..958c0f3bf 100644
+--- a/arch/arm/boot/dts/rk3288-tinker.dts
++++ b/arch/arm/boot/dts/rk3288-tinker.dts
+@@ -369,7 +369,7 @@
+ };
+ 
+ &i2c1 {
+-	status = "okay";
++	status = "disabled";
+ };
+ 
+ &i2c2 {
+@@ -392,7 +392,7 @@
+ };
+ 
+ &i2c4 {
+-	status = "okay";
++	status = "disabled";
+ };
+ 
+ &i2c5 {
+

patch/kernel/rockchip64-dev/add-board-rockpi4b.patch

@@ -0,0 +1,925 @@
+diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
+index 49042c4..191829b 100644
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -17,6 +17,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpi4b.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpi4b.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpi4b.dts
+new file mode 100644
+index 0000000..52f4731
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpi4b.dts
+@@ -0,0 +1,907 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
++ * Copyright (c) 2018 Akash Gajjar <Akash_Gajjar@mentor.com>
++ */
++
++/dts-v1/;
++#include <dt-bindings/input/linux-event-codes.h>
++#include <dt-bindings/pwm/pwm.h>
++#include "rk3399.dtsi"
++#include "rk3399-opp.dtsi"
++
++/ {
++	model = "RockPi-4B";
++	compatible = "radxa,rockpi-4b", "rockchip,rk3399";
++
++	chosen {
++		bootargs = "mmc_cmdqueue=0 earlycon=uart8250,mmio32,0xff1a0000";
++		stdout-path = "serial2:1500000n8";
++	};
++
++	clkin_gmac: external-gmac-clock {
++		compatible = "fixed-clock";
++		clock-frequency = <125000000>;
++		clock-output-names = "clkin_gmac";
++		#clock-cells = <0>;
++	};
++
++	dc_12v: dc-12v {
++		compatible = "regulator-fixed";
++		regulator-name = "dc_12v";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <12000000>;
++		regulator-max-microvolt = <12000000>;
++	};
++
++	gpio-keys {
++		compatible = "gpio-keys";
++		autorepeat;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pwrbtn>;
++
++		power {
++			debounce-interval = <100>;
++			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
++			label = "GPIO Key Power";
++			linux,code = <KEY_POWER>;
++			wakeup-source;
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++		pinctrl-names = "default";
++		pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>;
++
++		work-led {
++			label = "work";
++			default-state = "on";
++			gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
++		};
++
++		diy-led {
++			label = "diy";
++			default-state = "off";
++			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
++		};
++	};
++
++	es8316-sound {
++		status = "okay";
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "rockchip,es8316-codec";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,mclk-fs = <256>;
++		simple-audio-card,widgets =
++			"Microphone", "Mic Jack",
++			"Headphone", "Headphone Jack";
++		simple-audio-card,routing =
++			"Mic Jack", "MICBIAS1",
++			"IN1P", "Mic Jack",
++			"Headphone Jack", "HPOL",
++			"Headphone Jack", "HPOR";
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s1>;
++		};
++
++		simple-audio-card,codec {
++			sound-dai = <&es8316>;
++		};
++	};
++
++	sdio_pwrseq: sdio-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rk808 1>;
++		clock-names = "ext_clock";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_pwr>, <&wifi_enable_h>;
++
++		/*
++		 * On the module itself this is one of these (depending
++		 * on the actual card populated):
++		 * - SDIO_RESET_L_WL_REG_ON
++		 * - PDN (power down when low)
++		 */
++		reset-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>, <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
++	};
++
++	wireless-wlan {
++		compatible = "wlan-platdata";
++		rockchip,grf = <&grf>;
++		wifi_chip_type = "ap6256";
++		sdio_vref = <1800>;
++		WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_A3 */
++		status = "okay";
++	};
++
++	fan0: pwm-fan {
++		compatible = "pwm-fan";
++		pwms = <&pwm1 0 10000 0>;
++		cooling-min-state = <0>;
++		cooling-max-state = <3>;
++		#cooling-cells = <2>;
++		cooling-levels = <0 102 170 230>;
++	};
++
++	/* switched by pmic_sleep */
++	vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc1v8_s3";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&vcc_1v8>;
++	};
++
++	vcc3v3_pcie: vcc3v3-pcie-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pcie_pwr_en>;
++		regulator-name = "vcc3v3_pcie";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&dc_12v>;
++	};
++
++	vcc_phy: vcc-phy-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_phy";
++		regulator-always-on;
++		regulator-boot-on;
++	};
++
++	vcc3v3_sys: vcc3v3-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc_sys>;
++	};
++
++	/* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
++	vcc5v0_host: vcc5v0-host-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_host_en>;
++		regulator-name = "vcc5v0_host";
++		regulator-always-on;
++		vin-supply = <&vcc_sys>;
++	};
++
++	vcc5v0_typec: vcc5v0-typec-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_typec_en>;
++		regulator-name = "vcc5v0_typec";
++		regulator-always-on;
++		vin-supply = <&vcc_sys>;
++	};
++
++	vcc_sys: vcc-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&dc_12v>;
++	};
++
++	vdd_log: vdd-log {
++		compatible = "pwm-regulator";
++		pwms = <&pwm2 0 25000 1>;
++		pwm-supply = <&vcc_sys>;
++		regulator-name = "vdd_log";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <800000>;
++		regulator-max-microvolt = <1400000>;
++	};
++};
++
++&cpu_l0 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l1 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l2 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l3 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_b0 {
++	cpu-supply = <&vdd_cpu_b>;
++};
++
++&cpu_b1 {
++	cpu-supply = <&vdd_cpu_b>;
++};
++
++&cpu_alert0 {
++	temperature = <80000>;
++};
++
++&cpu_alert1 {
++	temperature = <95000>;
++};
++
++&cpu_crit {
++	temperature = <100000>;
++};
++
++&cooling_maps {
++	map2 {
++		trip = <&cpu_alert0>;
++		cooling-device = <&fan0 0 1>;
++	};
++	map3 {
++		trip = <&cpu_alert1>;
++		cooling-device = <&fan0 1 2>;
++	};
++	map4 {
++		trip = <&cpu_crit>;
++		cooling-device = <&fan0 2 3>;
++	};
++};
++
++&emmc_phy {
++	status = "okay";
++};
++
++&gmac {
++	assigned-clocks = <&cru SCLK_RMII_SRC>;
++	assigned-clock-parents = <&clkin_gmac>;
++	clock_in_out = "input";
++	phy-supply = <&vcc_phy>;
++	phy-mode = "rgmii";
++	pinctrl-names = "default";
++	pinctrl-0 = <&rgmii_pins>;
++	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	snps,reset-delays-us = <0 10000 50000>;
++	tx_delay = <0x28>;
++	rx_delay = <0x20>;
++	status = "okay";
++};
++
++&hdmi {
++	ddc-i2c-bus = <&i2c3>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&hdmi_cec>;
++	status = "okay";
++};
++
++&i2c0 {
++	clock-frequency = <400000>;
++	i2c-scl-rising-time-ns = <168>;
++	i2c-scl-falling-time-ns = <4>;
++	status = "okay";
++
++	rk808: pmic@1b {
++		compatible = "rockchip,rk808";
++		reg = <0x1b>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
++		#clock-cells = <1>;
++		clock-output-names = "xin32k", "rk808-clkout2";
++		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_int_l>;
++		rockchip,system-power-controller;
++		wakeup-source;
++
++		vcc1-supply = <&vcc_sys>;
++		vcc2-supply = <&vcc_sys>;
++		vcc3-supply = <&vcc_sys>;
++		vcc4-supply = <&vcc_sys>;
++		vcc6-supply = <&vcc_sys>;
++		vcc7-supply = <&vcc_sys>;
++		vcc8-supply = <&vcc3v3_sys>;
++		vcc9-supply = <&vcc_sys>;
++		vcc10-supply = <&vcc_sys>;
++		vcc11-supply = <&vcc_sys>;
++		vcc12-supply = <&vcc3v3_sys>;
++		vddio-supply = <&vcc1v8_pmu>;
++
++		regulators {
++			vdd_center: DCDC_REG1 {
++				regulator-name = "vdd_center";
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_cpu_l: DCDC_REG2 {
++				regulator-name = "vdd_cpu_l";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_ddr: DCDC_REG3 {
++				regulator-name = "vcc_ddr";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vcc_1v8: DCDC_REG4 {
++				regulator-name = "vcc_1v8";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc1v8_dvp: LDO_REG1 {
++				regulator-name = "vcc1v8_dvp";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc2v8_dvp: LDO_REG2 {
++				regulator-name = "vcc2v8_dvp";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <2800000>;
++				regulator-max-microvolt = <2800000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc1v8_pmu: LDO_REG3 {
++				regulator-name = "vcc1v8_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc_sdio: LDO_REG4 {
++				regulator-name = "vcc_sdio";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3000000>;
++				};
++			};
++
++			vcca3v0_codec: LDO_REG5 {
++				regulator-name = "vcca3v0_codec";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3000000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_1v5: LDO_REG6 {
++				regulator-name = "vcc_1v5";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1500000>;
++				regulator-max-microvolt = <1500000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1500000>;
++				};
++			};
++
++			vcca1v8_codec: LDO_REG7 {
++				regulator-name = "vcca1v8_codec";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_3v0: LDO_REG8 {
++				regulator-name = "vcc_3v0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3000000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3000000>;
++				};
++			};
++
++			vcc3v0_sd: vcc3v0-sd {
++				compatible = "regulator-fixed";
++				enable-active-high;
++				gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
++				pinctrl-names = "default";
++				pinctrl-0 = <&sdmmc0_pwr_h>;
++				regulator-always-on;
++				regulator-max-microvolt = <3000000>;
++				regulator-min-microvolt = <3000000>;
++				regulator-name = "vcc3v0_sd";
++				vin-supply = <&vcc3v3_sys>;
++			};
++
++			vcc3v3_s3: vcc_lan: SWITCH_REG1 {
++				regulator-name = "vcc3v3_s3";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v3_s0: SWITCH_REG2 {
++				regulator-name = "vcc3v3_s0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++		};
++	};
++
++	vdd_cpu_b: regulator@40 {
++		compatible = "silergy,syr827";
++		reg = <0x40>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-compatible = "fan53555-reg";
++		pinctrl-0 = <&vsel1_gpio>;
++		vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
++		regulator-name = "vdd_cpu_b";
++		regulator-min-microvolt = <712500>;
++		regulator-max-microvolt = <1500000>;
++		regulator-ramp-delay = <1000>;
++		regulator-always-on;
++		regulator-boot-on;
++		vin-supply = <&vcc_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	vdd_gpu: regulator@41 {
++		compatible = "silergy,syr828";
++		reg = <0x41>;
++		regulator-compatible = "fan53555-reg";
++		pinctrl-0 = <&vsel2_gpio>;
++		vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-name = "vdd_gpu";
++		regulator-min-microvolt = <712500>;
++		regulator-max-microvolt = <1500000>;
++		regulator-ramp-delay = <1000>;
++		regulator-always-on;
++		regulator-boot-on;
++		vin-supply = <&vcc_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++};
++
++&i2c1 {
++	i2c-scl-rising-time-ns = <300>;
++	i2c-scl-falling-time-ns = <15>;
++	status = "okay";
++
++	es8316: es8316@10 {
++		#sound-dai-cells = <0>;
++		compatible = "everest,es8316";
++		reg = <0x10>;
++		clocks = <&cru SCLK_I2S_8CH_OUT>;
++		clock-names = "mclk";
++		pinctrl-names = "default";
++		pinctrl-0 = <&i2s_8ch_mclk>;
++		hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
++	};
++};
++
++&i2c3 {
++	i2c-scl-rising-time-ns = <450>;
++	i2c-scl-falling-time-ns = <15>;
++	status = "okay";
++};
++
++&i2c4 {
++	i2c-scl-rising-time-ns = <600>;
++	i2c-scl-falling-time-ns = <20>;
++	status = "okay";
++};
++
++&i2s0 {
++	rockchip,playback-channels = <8>;
++	rockchip,capture-channels = <8>;
++	#sound-dai-cells = <0>;
++	status = "okay";
++};
++
++&i2s1 {
++	rockchip,playback-channels = <2>;
++	rockchip,capture-channels = <2>;
++	#sound-dai-cells = <0>;
++	status = "okay";
++};
++
++&i2s2 {
++	#sound-dai-cells = <0>;
++	status = "okay";
++};
++
++&io_domains {
++	status = "okay";
++
++	bt656-supply = <&vcc1v8_dvp>;
++	audio-supply = <&vcca1v8_codec>;
++	sdmmc-supply = <&vcc_sdio>;
++	gpio1830-supply = <&vcc_3v0>;
++};
++
++&pcie_phy {
++	status = "okay";
++};
++
++&pcie0 {
++	ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
++	num-lanes = <4>;
++	max-link-speed = <2>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&pcie_clkreqn_cpm>;
++	vpcie3v3-supply = <&vcc3v3_pcie>;
++	status = "okay";
++};
++
++&pmu_io_domains {
++	pmu1830-supply = <&vcc_3v0>;
++	status = "okay";
++};
++
++&pinctrl {
++	buttons {
++		pwrbtn: pwrbtn {
++			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	fusb302x {
++		fusb0_int: fusb0-int {
++			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	leds {
++		work_led_gpio: work_led-gpio {
++			rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		diy_led_gpio: diy_led-gpio {
++			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	lcd-panel {
++		lcd_panel_reset: lcd-panel-reset {
++			rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	pcie {
++		pcie_pwr_en: pcie-pwr-en {
++			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		pcie_3g_drv: pcie-3g-drv {
++			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	pmic {
++		pmic_int_l: pmic-int-l {
++			rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++
++		vsel1_gpio: vsel1-gpio {
++			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++
++		vsel2_gpio: vsel2-gpio {
++			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++	};
++
++	sd {
++		sdmmc0_pwr_h: sdmmc0-pwr-h {
++			rockchip,pins =
++				<RK_GPIO0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	sdio-pwrseq {
++		wifi_enable_h: wifi-enable-h {
++			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++		wifi_pwr: wifi-pwr {
++			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++		wifi_host_wake_l: wifi-host-wake-l {
++			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	usb-typec {
++		vcc5v0_typec_en: vcc5v0_typec_en {
++			rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	rt5640 {
++		rt5640_hpcon: rt5640-hpcon {
++			rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	usb2 {
++		vcc5v0_host_en: vcc5v0-host-en {
++			rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	i2s0 {
++		i2s_8ch_mclk: i2s-8ch-mclk {
++			rockchip,pins = <4 0 RK_FUNC_1 &pcfg_pull_none>;
++		};
++	};
++};
++
++&pwm0 {
++	status = "okay";
++};
++
++&pwm1 {
++	status = "okay";
++};
++
++&pwm2 {
++	status = "okay";
++};
++
++&saradc {
++	vref-supply = <&vcca1v8_s3>;
++	status = "okay";
++};
++
++&sdmmc {
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
++	disable-wp;
++	sd-uhs-sdr104;
++	max-frequency = <10000000>;
++	vqmmc-supply = <&vcc_sdio>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
++	status = "okay";
++};
++
++&sdio0 {
++//	clock-frequency = <50000000>;
++//	clock-freq-min-max = <200000 50000000>;
++	max-frequency = <20000000>;
++	bus-width = <4>;
++//	vmmc-supply = <&vcc3v0_sd>;
++//	vqmmc-supply = <&vcc_sdio>;
++	mmc-pwrseq = <&sdio_pwrseq>;
++	supports-sdio;
++	disable-wp;
++	cap-sd-highspeed;
++	cap-sdio-irq;
++	keep-power-in-suspend;
++	non-removable;
++	num-slots = <1>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
++	sd-uhs-sdr104;
++	status = "okay";
++};
++
++&sdhci {
++	bus-width = <8>;
++	//mmc-hs400-1_8v;
++	mmc-hs200-1_8v;
++	//mmc-hs400-enhanced-strobe;
++	keep-power-in-suspend;
++	supports-emmc;
++	non-removable;
++	status = "okay";
++};
++
++&tcphy0 {
++	status = "okay";
++};
++
++&tcphy1 {
++	status = "okay";
++};
++
++&tsadc {
++	/* tshut mode 0:CRU 1:GPIO */
++	rockchip,hw-tshut-mode = <1>;
++	/* tshut polarity 0:LOW 1:HIGH */
++	rockchip,hw-tshut-polarity = <1>;
++	status = "okay";
++};
++
++&u2phy0 {
++	status = "okay";
++
++	u2phy0_otg: otg-port {
++		status = "okay";
++	};
++
++	u2phy0_host: host-port {
++		phy-supply = <&vcc5v0_host>;
++		status = "okay";
++	};
++};
++
++&u2phy1 {
++	status = "okay";
++
++	u2phy1_otg: otg-port {
++		status = "okay";
++	};
++
++	u2phy1_host: host-port {
++		phy-supply = <&vcc5v0_host>;
++		status = "okay";
++	};
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_xfer &uart0_cts>;
++	status = "okay";
++};
++
++&uart2 {
++	status = "okay";
++};
++
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	status = "okay";
++};
++
++&usbdrd3_0 {
++	status = "disabled";
++};
++
++&usbdrd_dwc3_0 {
++	status = "disabled";
++	dr_mode = "otg";
++};
++
++&usbdrd3_1 {
++	status = "disabled";
++};
++
++&usbdrd_dwc3_1 {
++	status = "disabled";
++	dr_mode = "host";
++};
++
++&vopb {
++	status = "okay";
++};
++
++&vopb_mmu {
++	status = "okay";
++};
++
++&vopl {
++	status = "okay";
++};
++
++&vopl_mmu {
++	status = "okay";
++};
++
++&spi1 {
++	status = "okay";
++	max-freq = <10000000>;
++
++	spiflash: spi-flash@0 {
++		#address-cells = <0x1>;
++		#size-cells = <1>;
++		compatible = "jedec,spi-nor";
++		reg = <0x0>;
++		spi-max-frequency = <10000000>;
++		status = "okay";
++		m25p,fast-read;
++
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			loader@8000 {
++				label = "loader";
++				reg = <0x0 0x3F8000>;
++			};
++
++			env@3f8000 {
++				label = "env";
++				reg = <0x3F8000 0x8000>;
++			};
++
++			vendor@7c0000 {
++				label = "vendor";
++				reg = <0x7C0000 0x40000>;
++			};
++		};
++	};
++};

patch/kernel/rockchip64-dev/board-rockpi4-enable-usb3.patch

@@ -0,0 +1,30 @@
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpi4b.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpi4b.dts
+index 8b6314bda..415bf66ca 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpi4b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpi4b.dts
+@@ -837,20 +837,20 @@
+ };
+ 
+ &usbdrd3_0 {
+-	status = "disabled";
++	status = "okay";
+ };
+ 
+ &usbdrd_dwc3_0 {
+-	status = "disabled";
+-	dr_mode = "otg";
++	status = "okay";
++	dr_mode = "host";
+ };
+ 
+ &usbdrd3_1 {
+-	status = "disabled";
++	status = "okay";
+ };
+ 
+ &usbdrd_dwc3_1 {
+-	status = "disabled";
++	status = "okay";
+ 	dr_mode = "host";
+ };
+ 

patch/kernel/rockchip64-dev/board-rockpro64-reduce-sdcard-speed.patch

@@ -0,0 +1,13 @@
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
+index 4cbca4d..a0e2efb 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
+@@ -694,7 +729,7 @@
+ 	cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
+ 	disable-wp;
+ 	sd-uhs-sdr104;
+-	max-frequency = <150000000>;
++	max-frequency = <10000000>;
+ 	vqmmc-supply = <&vcc_sdio>;
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;

patch/kernel/rockchip64-dev/fix-rockpro64-emmc.patch

@@ -0,0 +1,24 @@
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
+index 4cbca4d..7421b71 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
+@@ -15,7 +15,7 @@
+ 	compatible = "pine64,rockpro64", "rockchip,rk3399";
+ 
+ 	chosen {
+-		bootargs = "earlycon=uart8250,mmio32,0xff1a0000";
++		bootargs = "mmc_cmdqueue=0 earlycon=uart8250,mmio32,0xff1a0000";
+ 		stdout-path = "serial2:1500000n8";
+ 	};
+ 
+@@ -721,8 +721,10 @@
+ 	//mmc-hs400-1_8v;
+ 	mmc-hs200-1_8v;
+ 	//mmc-hs400-enhanced-strobe;
++	keep-power-in-suspend;
++	supports-emmc;
+ 	non-removable;
+ 	status = "okay";
+ };
+ 
+ &tcphy0 {

patch/kernel/rockchip64-dev/fix-rockpro64-pmic-int-l.patch

@@ -1,13 +0,0 @@
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
-index 5b546fa..92ba1c0 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
-@@ -669,7 +689,7 @@
- 
- 	pmic {
- 		pmic_int_l: pmic-int-l {
--			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
-+			rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
- 		};
- 	};
- 

patch/kernel/rockchip64-dev/general-add-overlay-compilation-support.patch

@@ -1,20 +1,3 @@
-diff --git a/arch/arm/Makefile b/arch/arm/Makefile
-index 65f4e2a4..9eb2043c 100644
---- a/arch/arm/Makefile
-+++ b/arch/arm/Makefile
-@@ -339,6 +339,12 @@ $(INSTALL_TARGETS):
- %.dtb: | scripts
- 	$(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@
-
-+%.dtbo: | scripts
-+	$(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@
-+
-+%.scr: | scripts
-+	$(Q)$(MAKE) $(build)=$(boot)/dts ARCH=$(ARCH) $(boot)/dts/$@
-+
- PHONY += dtbs dtbs_install
-
- dtbs: prepare scripts
 diff --git a/arch/arm/boot/.gitignore b/arch/arm/boot/.gitignore
 index 3c79f859..4e5c1d59 100644
 --- a/arch/arm/boot/.gitignore
@@ -25,24 +8,6 @@ index 3c79f859..4e5c1d59 100644
  uImage
 +*.dtb*
 +*.scr
-\ No newline at end of file
-diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
-index f839ecd9..9788f16d 100644
---- a/arch/arm64/Makefile
-+++ b/arch/arm64/Makefile
-@@ -121,6 +121,12 @@ zinstall install:
- %.dtb: scripts
- 	$(Q)$(MAKE) $(build)=$(boot)/dts $(boot)/dts/$@
-
-+%.dtbo: | scripts
-+	$(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@
-+
-+%.scr: | scripts
-+	$(Q)$(MAKE) $(build)=$(boot)/dts ARCH=$(ARCH) $(boot)/dts/$@
-+
- PHONY += dtbs dtbs_install
-
- dtbs: prepare scripts
 diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst
 index 34614a48..8a8313d6 100644
 --- a/scripts/Makefile.dtbinst

patch/kernel/rockchip64-dev/orangepi-rk3399-dts.patch

@@ -0,0 +1,945 @@
+diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
+index 102a48a..dceef9d 100644
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile2
+@@ -16,6 +16,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi4-rev00.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi4-rev01.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi4-rev04.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts
+new file mode 100644
+index 000000000000..9a7887220551
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts
+@@ -0,0 +1,927 @@
++/*
++ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This file is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This file is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++#include "dt-bindings/pwm/pwm.h"
++#include "rk3399.dtsi"
++#include "rk3399-opp.dtsi"
++#include <dt-bindings/input/input.h>
++
++/ {
++	model = "OrangePi board based on Rockchip RK3399";
++	compatible = "xulung,orangepi-rk3399",
++		   "rockchip,rk3399";
++
++	cpuinfo {
++		compatible = "rockchip,cpuinfo";
++	};
++
++	mach: board {
++		compatible = "xulung,board";
++		machine = "ORANGEPI-RK3399";
++		hwrev = <255>;
++		model = "OrangePi Series";
++	};
++
++	clkin_gmac: external-gmac-clock {
++		compatible = "fixed-clock";
++		clock-frequency = <125000000>;
++		clock-output-names = "clkin_gmac";
++		#clock-cells = <0>;
++	};
++
++	vcc3v3_sys: vcc3v3-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++	};
++
++	vcc5v0_sys: vcc5v0-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
++	vccadc_ref: vccadc-ref {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc1v8_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++	};
++
++	vcc_phy: vcc-phy-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_phy";
++		regulator-always-on;
++		regulator-boot-on;
++	};
++
++	vcc_lcd: vcc-lcd {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_lcd";
++		gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
++		startup-delay-us = <20000>;
++		enable-active-high;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-boot-on;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vdd_log: vdd-log {
++		compatible = "pwm-regulator";
++		pwms = <&pwm2 0 25000 1>;
++		regulator-name = "vdd_log";
++		regulator-min-microvolt = <800000>;
++		regulator-max-microvolt = <1400000>;
++		regulator-always-on;
++		regulator-boot-on;
++
++		/* for rockchip boot on */
++		rockchip,pwm_id = <2>;
++		rockchip,pwm_voltage = <1000000>;
++	};
++
++	vcc5v0_host: vcc5v0-host-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_host_en>;
++		regulator-name = "vcc5v0_host";
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	dw_hdmi_audio: dw-hdmi-audio {
++		status = "disabled";
++		compatible = "rockchip,dw-hdmi-audio";
++		#sound-dai-cells = <0>;
++	};
++
++	hdmi_sound: hdmi-sound {
++		status = "okay";
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,mclk-fs = <256>;
++		simple-audio-card,name = "rockchip,hdmi";
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s2>;
++		};
++		simple-audio-card,codec {
++			sound-dai = <&hdmi>;
++		};
++	};
++
++	spdif-sound {
++		status = "okay";
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "ROCKCHIP,SPDIF";
++		simple-audio-card,cpu {
++			sound-dai = <&spdif>;
++		};
++		simple-audio-card,codec {
++			sound-dai = <&spdif_out>;
++		};
++	};
++
++	spdif_out: spdif-out {
++		status = "okay";
++		compatible = "linux,spdif-dit";
++		#sound-dai-cells = <0>;
++	};
++
++	pwm_bl: backlight {
++		status = "disabled";
++		compatible = "pwm-backlight";
++		pwms = <&pwm0 0 25000 0>;
++		brightness-levels = <
++			  0   1   2   3   4   5   6   7
++			  8   9  10  11  12  13  14  15
++			 16  17  18  19  20  21  22  23
++			 24  25  26  27  28  29  30  31
++			 32  33  34  35  36  37  38  39
++			 40  41  42  43  44  45  46  47
++			 48  49  50  51  52  53  54  55
++			 56  57  58  59  60  61  62  63
++			 64  65  66  67  68  69  70  71
++			 72  73  74  75  76  77  78  79
++			 80  81  82  83  84  85  86  87
++			 88  89  90  91  92  93  94  95
++			 96  97  98  99 100 101 102 103
++			104 105 106 107 108 109 110 111
++			112 113 114 115 116 117 118 119
++			120 121 122 123 124 125 126 127
++			128 129 130 131 132 133 134 135
++			136 137 138 139 140 141 142 143
++			144 145 146 147 148 149 150 151
++			152 153 154 155 156 157 158 159
++			160 161 162 163 164 165 166 167
++			168 169 170 171 172 173 174 175
++			176 177 178 179 180 181 182 183
++			184 185 186 187 188 189 190 191
++			192 193 194 195 196 197 198 199
++			200 201 202 203 204 205 206 207
++			208 209 210 211 212 213 214 215
++			216 217 218 219 220 221 222 223
++			224 225 226 227 228 229 230 231
++			232 233 234 235 236 237 238 239
++			240 241 242 243 244 245 246 247
++			248 249 250 251 252 253 254 255>;
++		default-brightness-level = <200>;
++	};
++
++	gpio-keys {
++		compatible = "gpio-keys";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		autorepeat;
++
++		pinctrl-names = "default";
++		pinctrl-0 = <&power_key>;
++
++		button@0 {
++			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
++			linux,code = <KEY_POWER>;
++			label = "GPIO Key Power";
++			linux,input-type = <1>;
++			gpio-key,wakeup = <1>;
++			debounce-interval = <100>;
++		};
++	};
++
++	adc-keys {
++		compatible = "adc-keys";
++		io-channels = <&saradc 1>;
++		io-channel-names = "buttons";
++		poll-interval = <100>;
++		keyup-threshold-microvolt = <1800000>;
++
++		button-up {
++			label = "Volume Up";
++			linux,code = <KEY_VOLUMEUP>;
++			press-threshold-microvolt = <100000>;
++		};
++
++		button-down {
++			label = "Volume Down";
++			linux,code = <KEY_VOLUMEDOWN>;
++			press-threshold-microvolt = <300000>;
++		};
++	};
++
++	leds: gpio-leds {
++		compatible = "gpio-leds";
++		pinctrl-names = "default";
++		pinctrl-0 =<&leds_gpio>;
++
++		led@1 {
++			gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
++			label = "status_led";
++			linux,default-trigger = "heartbeat";
++			linux,default-trigger-delay-ms = <0>;
++		};
++	};
++
++	sdio_pwrseq: sdio-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rk808 1>;
++		clock-names = "ext_clock";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_enable_h>;
++
++		/*
++		 * On the module itself this is one of these (depending
++		 * on the actual card populated):
++		 * - SDIO_RESET_L_WL_REG_ON
++		 * - PDN (power down when low)
++		 */
++		reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */
++	};
++
++	wireless-wlan {
++		compatible = "wlan-platdata";
++		rockchip,grf = <&grf>;
++		wifi_chip_type = "ap6354";
++		sdio_vref = <1800>;
++		WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */
++		status = "okay";
++	};
++
++	wireless-bluetooth {
++		compatible = "bluetooth-platdata";
++		clocks = <&rk808 1>;
++		clock-names = "ext_clock";
++		//wifi-bt-power-toggle;
++		uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */
++		pinctrl-names = "default", "rts_gpio";
++		pinctrl-0 = <&uart0_rts>;
++		pinctrl-1 = <&uart0_gpios>;
++		//BT,power_gpio  = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */
++		BT,reset_gpio    = <&gpio0 9 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */
++		BT,wake_gpio     = <&gpio2 26 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */
++		BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */
++		status = "okay";
++	};
++};
++
++&cpu_l0 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l1 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l2 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l3 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_b0 {
++	cpu-supply = <&vdd_cpu_b>;
++};
++
++&cpu_b1 {
++	cpu-supply = <&vdd_cpu_b>;
++};
++
++&gmac {
++	phy-supply = <&vcc_phy>;
++	phy-mode = "rgmii";
++	clock_in_out = "input";
++	snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	snps,reset-delays-us = <0 10000 50000>;
++	assigned-clocks = <&cru SCLK_RMII_SRC>;
++	assigned-clock-parents = <&clkin_gmac>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&rgmii_pins>;
++	tx_delay = <0x28>;
++	rx_delay = <0x11>;
++	status = "okay";
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_xfer &uart0_cts>;
++	status = "okay";
++};
++
++&uart2 {
++	status = "okay";
++};
++
++&vopb {
++	status = "okay";
++};
++
++&vopb_mmu {
++	status = "okay";
++};
++
++&vopl {
++	status = "okay";
++};
++
++&vopl_mmu {
++	status = "okay";
++};
++
++&hdmi {
++	/* remove the hdmi_cec, reused by edp_hpd */
++	pinctrl-0 = <&hdmi_i2c_xfer>;
++	#address-cells = <1>;
++	#size-cells = <0>;
++	#sound-dai-cells = <0>;
++	status = "okay";
++	ddc-i2c-bus = <&i2c7>;
++};
++
++&i2c0 {
++	status = "okay";
++	i2c-scl-rising-time-ns = <160>;
++	i2c-scl-falling-time-ns = <30>;
++	clock-frequency = <400000>;
++
++	vdd_cpu_b: syr827@40 {
++		compatible = "silergy,syr827";
++		reg = <0x40>;
++		vin-supply = <&vcc3v3_sys>;
++		regulator-compatible = "fan53555-reg";
++		pinctrl-names = "default";
++		pinctrl-0 = <&vsel1_gpio>;
++		vsel-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
++		regulator-name = "vdd_cpu_b";
++		regulator-min-microvolt = <712500>;
++		regulator-max-microvolt = <1500000>;
++		regulator-ramp-delay = <1000>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-initial-state = <3>;
++			regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	vdd_gpu: syr828@41 {
++		compatible = "silergy,syr828";
++		reg = <0x41>;
++		vin-supply = <&vcc3v3_sys>;
++		regulator-compatible = "fan53555-reg";
++		pinctrl-names = "default";
++		pinctrl-0 = <&vsel2_gpio>;
++		vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
++		regulator-name = "vdd_gpu";
++		regulator-min-microvolt = <712500>;
++		regulator-max-microvolt = <1500000>;
++		regulator-ramp-delay = <1000>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-initial-state = <3>;
++			regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	rk808: pmic@1b {
++		compatible = "rockchip,rk808";
++		reg = <0x1b>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_int_l>;
++		rockchip,system-power-controller;
++		wakeup-source;
++		#clock-cells = <1>;
++		clock-output-names = "xin32k", "rk808-clkout2";
++
++		vcc1-supply = <&vcc3v3_sys>;
++		vcc2-supply = <&vcc3v3_sys>;
++		vcc3-supply = <&vcc3v3_sys>;
++		vcc4-supply = <&vcc3v3_sys>;
++		vcc6-supply = <&vcc3v3_sys>;
++		vcc7-supply = <&vcc3v3_sys>;
++		vcc8-supply = <&vcc3v3_sys>;
++		vcc9-supply = <&vcc3v3_sys>;
++		vcc10-supply = <&vcc3v3_sys>;
++		vcc11-supply = <&vcc3v3_sys>;
++		vcc12-supply = <&vcc3v3_sys>;
++		vddio-supply = <&vcc_3v0>;
++
++		regulators {
++			vdd_center: DCDC_REG1 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++				regulator-name = "vdd_center";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_cpu_l: DCDC_REG2 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++				regulator-name = "vdd_cpu_l";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_ddr: DCDC_REG3 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-name = "vcc_ddr";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vcc_1v8: DCDC_REG4 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc_1v8";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc1v8_dvp: LDO_REG1 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc1v8_dvp";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v0_tp: LDO_REG2 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3000000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-name = "vcc3v0_tp";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc1v8_pmu: LDO_REG3 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc1v8_pmu";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc_sd: LDO_REG4 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc_sd";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcca3v0_codec: LDO_REG5 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3000000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-name = "vcca3v0_codec";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_1v5: LDO_REG6 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1500000>;
++				regulator-max-microvolt = <1500000>;
++				regulator-name = "vcc_1v5";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1500000>;
++				};
++			};
++
++			vcca1v8_codec: LDO_REG7 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcca1v8_codec";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_3v0: LDO_REG8 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3000000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-name = "vcc_3v0";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3000000>;
++				};
++			};
++
++			vcc3v3_s3: SWITCH_REG1 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-name = "vcc3v3_s3";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v3_s0: SWITCH_REG2 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-name = "vcc3v3_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++		};
++	};
++};
++
++&i2c1 {
++	status = "okay";
++	i2c-scl-rising-time-ns = <150>;
++	i2c-scl-falling-time-ns = <30>;
++	clock-frequency = <200000>;
++};
++
++&i2c2 {
++	status = "okay";
++};
++
++&i2c4 {
++	status = "okay";
++	i2c-scl-rising-time-ns = <160>;
++	i2c-scl-falling-time-ns = <30>;
++	clock-frequency = <400000>;
++
++	fusb0: fusb30x@22 {
++		compatible = "fairchild,fusb302";
++		reg = <0x22>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&fusb0_int>;
++		int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
++		vbus-5v-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
++		status = "okay";
++	};
++
++	gt9xx: goodix_ts@5d {
++		compatible = "goodix,gt9xx";
++		reg = <0x5d>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
++		goodix,irq-gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
++		goodix,rst-gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
++		status = "okay";
++	};
++
++	/*
++	onewire_ts@2f {
++		compatible = "onewire";
++		reg = <0x2f>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
++	}; */
++};
++
++&i2c7 {
++	status = "okay";
++};
++
++&spdif {
++	status = "okay";
++	pinctrl-0 = <&spdif_bus>;
++	i2c-scl-rising-time-ns = <450>;
++	i2c-scl-falling-time-ns = <15>;
++	#sound-dai-cells = <0>;
++};
++
++&i2s0 {
++	status = "okay";
++	rockchip,i2s-broken-burst-len;
++	rockchip,playback-channels = <8>;
++	rockchip,capture-channels = <8>;
++	#sound-dai-cells = <0>;
++};
++
++&i2s2 {
++	#sound-dai-cells = <0>;
++	status = "okay";
++};
++
++&io_domains {
++	status = "okay";
++
++	bt656-supply = <&vcc1v8_dvp>;		/* bt656_gpio2ab_ms */
++	audio-supply = <&vcca1v8_codec>;	/* audio_gpio3d4a_ms */
++	sdmmc-supply = <&vcc_sd>;		/* sdmmc_gpio4b_ms */
++	gpio1830-supply = <&vcc_3v0>;		/* gpio1833_gpio4cd_ms */
++};
++
++&pmu_io_domains {
++	status = "okay";
++	pmu1830-supply = <&vcc_3v0>;
++};
++
++&pcie_phy {
++	status = "okay";
++};
++
++&pcie0 {
++	status = "okay";
++	ep-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
++	num-lanes = <4>;
++};
++
++&pwm_bl {
++	status = "okay";
++	enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
++};
++
++&pwm0 {
++	status = "okay";
++};
++
++&pwm1 {
++	status = "okay";
++};
++
++&pwm2 {
++	status = "okay";
++};
++
++&saradc {
++	status = "okay";
++	vref-supply = <&vccadc_ref>; /* TBD */
++};
++
++&sdhci {
++	bus-width = <8>;
++	mmc-hs400-1_8v;
++	supports-emmc;
++	non-removable;
++	keep-power-in-suspend;
++	mmc-hs400-enhanced-strobe;
++	status = "okay";
++};
++
++&emmc_phy {
++	status = "okay";
++};
++
++&sdio0 {
++	clock-frequency = <50000000>;
++	clock-freq-min-max = <200000 50000000>;
++	supports-sdio;
++	bus-width = <4>;
++	disable-wp;
++	cap-sd-highspeed;
++	cap-sdio-irq;
++	keep-power-in-suspend;
++	mmc-pwrseq = <&sdio_pwrseq>;
++	non-removable;
++	num-slots = <1>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
++	sd-uhs-sdr104;
++	status = "okay";
++};
++
++&sdmmc {
++	clock-frequency = <150000000>;
++	clock-freq-min-max = <100000 150000000>;
++	supports-sd;
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	disable-wp;
++	num-slots = <1>;
++	//sd-uhs-sdr104;
++	vqmmc-supply = <&vcc_sd>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
++	status = "okay";
++};
++
++&tsadc {
++	/* tshut mode 0:CRU 1:GPIO */
++	rockchip,hw-tshut-mode = <1>;
++	/* tshut polarity 0:LOW 1:HIGH */
++	rockchip,hw-tshut-polarity = <1>;
++	status = "okay";
++};
++
++&tcphy0 {
++	extcon = <&fusb0>;
++	status = "okay";
++};
++
++&tcphy1 {
++	status = "okay";
++};
++
++&u2phy0 {
++	status = "okay";
++	extcon = <&fusb0>;
++
++	u2phy0_otg: otg-port {
++		status = "okay";
++	};
++
++	u2phy0_host: host-port {
++		phy-supply = <&vcc5v0_host>;
++		status = "okay";
++	};
++};
++
++&u2phy1 {
++	status = "okay";
++
++	u2phy1_otg: otg-port {
++		status = "okay";
++	};
++
++	u2phy1_host: host-port {
++		phy-supply = <&vcc5v0_host>;
++		status = "okay";
++	};
++};
++
++&usbdrd3_0 {
++	status = "okay";
++	extcon = <&fusb0>;
++};
++
++&usbdrd3_1 {
++	status = "okay";
++};
++
++&usbdrd_dwc3_0 {
++	status = "okay";
++};
++
++&usbdrd_dwc3_1 {
++	status = "okay";
++	dr_mode = "host";
++};
++
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	status = "okay";
++};
++
++&pinctrl {
++	pmic {
++		pmic_int_l: pmic-int-l {
++			rockchip,pins = <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++
++		vsel1_gpio: vsel1-gpio {
++			rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++		vsel2_gpio: vsel2-gpio {
++			rockchip,pins = <1 14 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++	};
++
++	usb2 {
++		vcc5v0_host_en: vcc5v0-host-en {
++			rockchip,pins = <4 25 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	fusb30x {
++		fusb0_int: fusb0-int {
++			rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	sdio-pwrseq {
++		wifi_enable_h: wifi-enable-h {
++			rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	wireless-bluetooth {
++		uart0_gpios: uart0-gpios {
++			rockchip,pins = <2 19 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	rockchip-key {
++		power_key: power-key {
++			rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	lcd-panel {
++		lcd_panel_reset: lcd-panel-reset {
++			rockchip,pins = <4 30 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	headphone {
++		hp_det: hp-det {
++			rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	gpio-leds {
++		leds_gpio: leds-gpio {
++			rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};

patch/kernel/rockchip64-dev/renegade-add-io_domains.patch

@@ -1,37 +0,0 @@
-From bbfbc438c11d595b24932273d2e956bce1e3280a Mon Sep 17 00:00:00 2001
-From: Levin Du <djw@t-chip.com.cn>
-Date: Tue, 31 Jul 2018 13:59:21 +0800
-Subject: [PATCH] arm64: dts: rockchip: add io-domain to roc-rk3328-cc
-
-It is necessary for the io domain setting of the SoC to match the voltage
-supplied by the regulators.
-
-Signed-off-by: Levin Du <djw@t-chip.com.cn>
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
-index 246c317f6a68..b983abd3d9c8 100644
---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
-@@ -208,6 +208,18 @@
- 	};
- };
- 
-+&io_domains {
-+	status = "okay";
-+
-+	vccio1-supply = <&vcc_io>;
-+	vccio2-supply = <&vcc18_emmc>;
-+	vccio3-supply = <&vcc_io>;
-+	vccio4-supply = <&vcc_18>;
-+	vccio5-supply = <&vcc_io>;
-+	vccio6-supply = <&vcc_io>;
-+	pmuio-supply = <&vcc_io>;
-+};
-+
- &pinctrl {
- 	pmic {
- 		pmic_int_l: pmic-int-l {

patch/kernel/rockchip64-dev/renegade-add-uhs.patch

@@ -1,73 +0,0 @@
-From 97c28fba89441a919376ff288efad9288c9937d1 Mon Sep 17 00:00:00 2001
-From: Levin Du <djw@t-chip.com.cn>
-Date: Tue, 31 Jul 2018 13:59:22 +0800
-Subject: [PATCH] arm64: dts: rockchip: add sdmmc UHS support for roc-rk3328-cc
-
-In roc-rk3328-cc board, the signal voltage of sdmmc is supplied by the
-vcc_sdio regulator, which is a mux between 1.8V and 3.3V, controlled by
-a special output only gpio pin labeled "gpiomut_pmuio_iout",
-corresponding bit 1 of the syscon GRF_SOC_CON10.
-
-This special pin can now be reference as <&grf_gpio 0>, thanks to the
-gpio-syscon driver, which makes writing regulator-gpio possible.
-
-If the signal voltage changes, the io domain needs to change
-correspondingly.
-
-To use this feature, the following options are required in kernel config:
- - CONFIG_GPIO_SYSCON=y
- - CONFIG_POWER_AVS=y
- - CONFIG_ROCKCHIP_IODOMAIN=y
-
-Signed-off-by: Levin Du <djw@t-chip.com.cn>
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 20 ++++++++++++++++++-
- 1 file changed, 19 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
-index b983abd3d9c8..99d0d9912950 100644
---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
-@@ -41,6 +41,19 @@
- 		vin-supply = <&vcc_io>;
- 	};
- 
-+	vcc_sdio: sdmmcio-regulator {
-+		compatible = "regulator-gpio";
-+		gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>;
-+		states = <1800000 0x1
-+			  3300000 0x0>;
-+		regulator-name = "vcc_sdio";
-+		regulator-type = "voltage";
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <3300000>;
-+		regulator-always-on;
-+		vin-supply = <&vcc_sys>;
-+	};
-+
- 	vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
- 		compatible = "regulator-fixed";
- 		enable-active-high;
-@@ -213,7 +226,7 @@
- 
- 	vccio1-supply = <&vcc_io>;
- 	vccio2-supply = <&vcc18_emmc>;
--	vccio3-supply = <&vcc_io>;
-+	vccio3-supply = <&vcc_sdio>;
- 	vccio4-supply = <&vcc_18>;
- 	vccio5-supply = <&vcc_io>;
- 	vccio6-supply = <&vcc_io>;
-@@ -242,7 +255,12 @@
- 	max-frequency = <150000000>;
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
-+	sd-uhs-sdr12;
-+	sd-uhs-sdr25;
-+	sd-uhs-sdr50;
-+	sd-uhs-sdr104;
- 	vmmc-supply = <&vcc_sd>;
-+	vqmmc-supply = <&vcc_sdio>;
- 	status = "okay";
- };
- 

patch/kernel/rockchip64-dev/rk3328-add-GRF-GPIO.patch

@@ -1,43 +0,0 @@
-From 47c0aa6d12f5fde27e9a673deabf814a4c6caf76 Mon Sep 17 00:00:00 2001
-From: Levin Du <djw@t-chip.com.cn>
-Date: Tue, 31 Jul 2018 13:59:20 +0800
-Subject: [PATCH] arm64: dts: rockchip: add GRF GPIO controller to rk3328
-
-Adding a GRF GPIO controller labled "grf_gpio" to rk3328, currently
-providing access to the GPIO_MUTE pin, which is manupulated by the
-GRF_SOC_CON10 register.
-
-The GPIO_MUTE pin is referred to as <&grf_gpio 0>.
-
-Signed-off-by: Levin Du <djw@t-chip.com.cn>
-[dropped default-status disabled]
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 7 ++++++-
- 1 file changed, 6 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-index 3f5a2944300f..d3ef6566325e 100644
---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-@@ -249,6 +249,12 @@
- 			status = "disabled";
- 		};
- 
-+		grf_gpio: grf-gpio {
-+			compatible = "rockchip,rk3328-grf-gpio";
-+			gpio-controller;
-+			#gpio-cells = <2>;
-+		};
-+
- 		power: power-controller {
- 			compatible = "rockchip,rk3328-power-controller";
- 			#power-domain-cells = <1>;
-@@ -274,7 +280,6 @@
- 			mode-bootloader = <BOOT_FASTBOOT>;
- 			mode-loader = <BOOT_BL_DOWNLOAD>;
- 		};
--
- 	};
- 
- 	uart0: serial@ff110000 {

patch/kernel/rockchip64-dev/rk3328-sd-drive-level-8ma.patch

@@ -0,0 +1,45 @@
+diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+index 6fa62cab2..d1ba2f5b9 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -1462,30 +1462,30 @@
+ 
+ 		sdmmc0 {
+ 			sdmmc0_clk: sdmmc0-clk {
+-				rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>;
++				rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
+ 			};
+ 
+ 			sdmmc0_cmd: sdmmc0-cmd {
+-				rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
++				rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
+ 			};
+ 
+ 			sdmmc0_dectn: sdmmc0-dectn {
+-				rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
++				rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_8ma>;
+ 			};
+ 
+ 			sdmmc0_wrprt: sdmmc0-wrprt {
+-				rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
++				rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_8ma>;
+ 			};
+ 
+ 			sdmmc0_bus1: sdmmc0-bus1 {
+-				rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>;
++				rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
+ 			};
+ 
+ 			sdmmc0_bus4: sdmmc0-bus4 {
+-				rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>,
+-						<1 RK_PA1 1 &pcfg_pull_up_4ma>,
+-						<1 RK_PA2 1 &pcfg_pull_up_4ma>,
+-						<1 RK_PA3 1 &pcfg_pull_up_4ma>;
++				rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
++						<1 RK_PA1 1 &pcfg_pull_up_8ma>,
++						<1 RK_PA2 1 &pcfg_pull_up_8ma>,
++						<1 RK_PA3 1 &pcfg_pull_up_8ma>;
+ 			};
+ 
+ 			sdmmc0_gpio: sdmmc0-gpio {
+ 

patch/kernel/sunxi-dev/0037-a64-dvfs-wip.patch

@@ -71,7 +71,7 @@ index 0eb482eb58b7..62b880f68d6a 100644
 
  / {
  	interrupt-parent = <&gic>;
-@@ -79,6 +80,47 @@
+@@ -79,6 +80,52 @@
  		};
  	};
 
@@ -114,6 +114,11 @@ index 0eb482eb58b7..62b880f68d6a 100644
 +			opp-microvolt = <1240000>;
 +			clock-latency-ns = <244144>; /* 8 32k periods */
 +		};
++		opp-1104000000 {
++			opp-hz = /bits/ 64 <1104000000>;
++			opp-microvolt = <1300000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
 +	};
 +
  	cpus {

patch/kernel/sunxi-dev/Revert_BT_HCIUART_RTL_ACPI_dependency.patch

@@ -0,0 +1,18 @@
+Reverts Bluetooth: Make BT_HCIUART_RTL configuration option depend on ACPI
+
+https://github.com/anarsoul/linux-2.6/commit/51474eff2bc2777061ab3658e014a37dc9d7a775
+
+otherwise it breaks the compilation
+
+diff --git a/drivers/bluetooth/Kconfig b/drivers/bluetooth/Kconfig
+index 845b0314c..2df11cc08 100644
+--- a/drivers/bluetooth/Kconfig
++++ b/drivers/bluetooth/Kconfig
+@@ -200,7 +200,6 @@ config BT_HCIUART_RTL
+ 	depends on BT_HCIUART
+ 	depends on BT_HCIUART_SERDEV
+ 	depends on GPIOLIB
+-	depends on ACPI
+ 	select BT_HCIUART_3WIRE
+ 	select BT_RTL
+ 	help

patch/kernel/sunxi-dev/xxx-0001-network-audio-orangepiwin-dts.patch

@@ -10,7 +10,7 @@ index eefe0a458..b5cb62beb 100644
  		serial0 = &uart0;
  	};
 
-@@ -59,6 +60,42 @@
+@@ -59,6 +60,43 @@
  		stdout-path = "serial0:115200n8";
  	};
 
@@ -28,6 +28,7 @@ index eefe0a458..b5cb62beb 100644
 +		regulator-name = "gmac-3v3";
 +		regulator-min-microvolt = <3300000>;
 +		regulator-max-microvolt = <3300000>;
++		startup-delay-us = <100000>;
 +		regulator-boot-on;
 +		enable-active-high;
 +		gpio = <&pio 3 14 GPIO_ACTIVE_HIGH>; /* PD14 */

patch/kernel/sunxi-dev/xxx-pinebook-revert-pwm-polairity-TEMP-WORKAROUND.patch

@@ -0,0 +1,13 @@
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+index c1e57597f..cf0a7b490 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+@@ -24,7 +24,7 @@
+ 
+ 	backlight: backlight {
+ 		compatible = "pwm-backlight";
+-		pwms = <&pwm 0 50000 0>;
++		pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+ 		brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>;
+ 		default-brightness-level = <2>;
+ 		enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */

patch/u-boot/u-boot-mvebu64/0001-drivers-spi-Add-support-for-Macronix-mx25u3235f-devi.patch

@@ -1,29 +0,0 @@
-From 7b0e72b4904b825d6f96d3a2a7c29a08c8b3968a Mon Sep 17 00:00:00 2001
-From: Konstantin Porotchkin <kostap@marvell.com>
-Date: Wed, 5 Sep 2018 16:56:02 +0300
-Subject: [PATCH] drivers: spi: Add support for Macronix mx25u3235f device
-
-Add support for Macronix SPI flash shipped on latest
-Espressobin boards
-
-Change-Id: Ia0798dfd4177c407c126e4f823d64d821b755433
-Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
----
- drivers/mtd/spi/spi_flash_ids.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
-index edca94e..1c50e0d 100644
---- a/drivers/mtd/spi/spi_flash_ids.c
-+++ b/drivers/mtd/spi/spi_flash_ids.c
-@@ -82,6 +82,7 @@ const struct spi_flash_info spi_flash_ids[] = {
- 	{"mx25l25635f",	   INFO(0xc22019, 0x0, 64 * 1024,   512, RD_FULL | WR_QPP) },
- 	{"mx25l51235f",	   INFO(0xc2201a, 0x0, 64 * 1024,  1024, RD_FULL | WR_QPP) },
- 	{"mx25l12855e",	   INFO(0xc22618, 0x0, 64 * 1024,   256, RD_FULL | WR_QPP) },
-+	{"mx25u3235f",     INFO(0xc22536, 0x0, 64 * 1024,    64, RD_FULL | WR_QPP) },
- 	{"mx66u51235f",    INFO(0xc2253a, 0x0, 64 * 1024,  1024, RD_FULL | WR_QPP) },
- 	{"mx66l1g45g",     INFO(0xc2201b, 0x0, 64 * 1024,  2048, RD_FULL | WR_QPP) },
- #endif
--- 
-2.7.4
-

patch/u-boot/u-boot-rk3399/nanopc-t4.patch

@@ -604,11 +604,11 @@ index 0000000..2b87c32
 +
 +&sdhci {
 +	bus-width = <8>;
-+	mmc-hs400-1_8v;
++	//mmc-hs400-1_8v;
 +	supports-emmc;
 +	non-removable;
 +	keep-power-in-suspend;
-+	mmc-hs400-enhanced-strobe;
++	//mmc-hs400-enhanced-strobe;
 +	status = "okay";
 +};
 +

patch/u-boot/u-boot-rk3399/orangepi-rk3399.patch

@@ -0,0 +1,825 @@
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index 31d9256..04be27e 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -48,6 +48,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+ 	rk3368-px5-evb.dtb \
+ 	rk3399-evb.dtb \
+ 	rk3399-firefly.dtb \
++	rk3399-orangepi.dtb \
+ 	rk3399-puma-ddr1333.dtb \
+ 	rk3399-puma-ddr1600.dtb \
+ 	rk3399-puma-ddr1866.dtb \
+diff --git a/arch/arm/dts/rk3399-orangepi.dts b/arch/arm/dts/rk3399-orangepi.dts
+new file mode 100644
+index 0000000..2b87c32
+--- /dev/null
++++ b/arch/arm/dts/rk3399-orangepi.dts
+@@ -0,0 +1,726 @@
++/*
++ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This file is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This file is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++#include <dt-bindings/pwm/pwm.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include "rk3399.dtsi"
++#include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
++
++/ {
++	model = "OrangePi boards based on Rockchip RK3399";
++	compatible = "xunlong,orangepi-rk3399",
++		   "rockchip,rk3399";
++
++	chosen {
++		stdout-path = &uart2;
++		u-boot,spl-boot-order = &sdhci, &sdmmc;	
++	};
++
++	mach: board {
++		compatible = "xunlong,board";
++		machine = "OrangePi-RK3399";
++		hwrev = <255>;
++		model = "OrangePi Series";
++	};
++
++	fiq_debugger: fiq-debugger {
++		compatible = "rockchip,fiq-debugger";
++		rockchip,serial-id = <2>;
++		rockchip,signal-irq = <182>;
++		rockchip,wake-irq = <0>;
++		rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
++		rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
++		pinctrl-names = "default";
++		pinctrl-0 = <&uart2c_xfer>;
++	};
++
++	clkin_gmac: external-gmac-clock {
++		compatible = "fixed-clock";
++		clock-frequency = <125000000>;
++		clock-output-names = "clkin_gmac";
++		#clock-cells = <0>;
++	};
++
++	vcc3v3_sys: vcc3v3-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++	};
++
++	vcc5v0_host: vcc5v0-host-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_host";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
++	vcc5v0_sys: vcc5v0-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
++	vccadc_ref: vccadc-ref {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc1v8_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++	};
++
++	vcc_phy: vcc-phy-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_phy";
++		regulator-always-on;
++		regulator-boot-on;
++	};
++
++	vcc_lcd: vcc-lcd {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_lcd";
++		gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
++		startup-delay-us = <20000>;
++		enable-active-high;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-boot-on;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vdd_log: vdd-log {
++		compatible = "pwm-regulator";
++		pwms = <&pwm2 0 25000 1>;
++		regulator-name = "vdd_log";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <800000>;
++		regulator-max-microvolt = <1400000>;
++		regulator-init-microvolt = <1000000>;
++	};
++
++	pwm_bl: backlight {
++		status = "disabled";
++		compatible = "pwm-backlight";
++		pwms = <&pwm0 0 25000 0>;
++		brightness-levels = <
++			  0   1   2   3   4   5   6   7
++			  8   9  10  11  12  13  14  15
++			 16  17  18  19  20  21  22  23
++			 24  25  26  27  28  29  30  31
++			 32  33  34  35  36  37  38  39
++			 40  41  42  43  44  45  46  47
++			 48  49  50  51  52  53  54  55
++			 56  57  58  59  60  61  62  63
++			 64  65  66  67  68  69  70  71
++			 72  73  74  75  76  77  78  79
++			 80  81  82  83  84  85  86  87
++			 88  89  90  91  92  93  94  95
++			 96  97  98  99 100 101 102 103
++			104 105 106 107 108 109 110 111
++			112 113 114 115 116 117 118 119
++			120 121 122 123 124 125 126 127
++			128 129 130 131 132 133 134 135
++			136 137 138 139 140 141 142 143
++			144 145 146 147 148 149 150 151
++			152 153 154 155 156 157 158 159
++			160 161 162 163 164 165 166 167
++			168 169 170 171 172 173 174 175
++			176 177 178 179 180 181 182 183
++			184 185 186 187 188 189 190 191
++			192 193 194 195 196 197 198 199
++			200 201 202 203 204 205 206 207
++			208 209 210 211 212 213 214 215
++			216 217 218 219 220 221 222 223
++			224 225 226 227 228 229 230 231
++			232 233 234 235 236 237 238 239
++			240 241 242 243 244 245 246 247
++			248 249 250 251 252 253 254 255>;
++		default-brightness-level = <200>;
++	};
++
++	sdio_pwrseq: sdio-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rk808 1>;
++		clock-names = "ext_clock";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_enable_h>;
++
++		/*
++		 * On the module itself this is one of these (depending
++		 * on the actual card populated):
++		 * - SDIO_RESET_L_WL_REG_ON
++		 * - PDN (power down when low)
++		 */
++		reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */
++	};
++};
++
++&cpu_l0 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l1 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l2 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l3 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_b0 {
++	cpu-supply = <&vdd_cpu_b>;
++};
++
++&cpu_b1 {
++	cpu-supply = <&vdd_cpu_b>;
++};
++
++&gmac {
++	phy-supply = <&vcc_phy>;
++	phy-mode = "rgmii";
++	clock_in_out = "input";
++	snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	snps,reset-delays-us = <0 10000 50000>;
++	assigned-clocks = <&cru SCLK_RMII_SRC>;
++	assigned-clock-parents = <&clkin_gmac>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&rgmii_pins>;
++	tx_delay = <0x28>;
++	rx_delay = <0x11>;
++	status = "okay";
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_xfer &uart0_cts>;
++	status = "okay";
++};
++
++&uart2 {
++	status = "okay";
++};
++
++&i2c0 {
++	status = "okay";
++	i2c-scl-rising-time-ns = <160>;
++	i2c-scl-falling-time-ns = <30>;
++	clock-frequency = <400000>;
++
++	vdd_cpu_b: syr827@40 {
++		compatible = "silergy,syr827";
++		reg = <0x40>;
++		vin-supply = <&vcc3v3_sys>;
++		regulator-compatible = "fan53555-reg";
++		pinctrl-names = "default";
++		pinctrl-0 = <&vsel1_gpio>;
++		vsel-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
++		regulator-name = "vdd_cpu_b";
++		regulator-min-microvolt = <712500>;
++		regulator-max-microvolt = <1500000>;
++		regulator-ramp-delay = <1000>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-initial-state = <3>;
++			regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	vdd_gpu: syr828@41 {
++		compatible = "silergy,syr828";
++		reg = <0x41>;
++		vin-supply = <&vcc3v3_sys>;
++		regulator-compatible = "fan53555-reg";
++		pinctrl-names = "default";
++		pinctrl-0 = <&vsel2_gpio>;
++		vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
++		regulator-name = "vdd_gpu";
++		regulator-min-microvolt = <712500>;
++		regulator-max-microvolt = <1500000>;
++		regulator-ramp-delay = <1000>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-initial-state = <3>;
++			regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	rk808: pmic@1b {
++		compatible = "rockchip,rk808";
++		reg = <0x1b>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_int_l>;
++		rockchip,system-power-controller;
++		wakeup-source;
++		#clock-cells = <1>;
++		clock-output-names = "xin32k", "rk808-clkout2";
++
++		vcc1-supply = <&vcc3v3_sys>;
++		vcc2-supply = <&vcc3v3_sys>;
++		vcc3-supply = <&vcc3v3_sys>;
++		vcc4-supply = <&vcc3v3_sys>;
++		vcc6-supply = <&vcc3v3_sys>;
++		vcc7-supply = <&vcc3v3_sys>;
++		vcc8-supply = <&vcc3v3_sys>;
++		vcc9-supply = <&vcc3v3_sys>;
++		vcc10-supply = <&vcc3v3_sys>;
++		vcc11-supply = <&vcc3v3_sys>;
++		vcc12-supply = <&vcc3v3_sys>;
++		vddio-supply = <&vcc_3v0>;
++
++		regulators {
++			vdd_center: DCDC_REG1 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++				regulator-name = "vdd_center";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_cpu_l: DCDC_REG2 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++				regulator-name = "vdd_cpu_l";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_ddr: DCDC_REG3 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-name = "vcc_ddr";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vcc_1v8: DCDC_REG4 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc_1v8";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc1v8_dvp: LDO_REG1 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc1v8_dvp";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v0_tp: LDO_REG2 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3000000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-name = "vcc3v0_tp";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc1v8_pmu: LDO_REG3 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc1v8_pmu";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc_sd: LDO_REG4 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc_sd";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcca3v0_codec: LDO_REG5 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3000000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-name = "vcca3v0_codec";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_1v5: LDO_REG6 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1500000>;
++				regulator-max-microvolt = <1500000>;
++				regulator-name = "vcc_1v5";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1500000>;
++				};
++			};
++
++			vcca1v8_codec: LDO_REG7 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcca1v8_codec";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_3v0: LDO_REG8 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3000000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-name = "vcc_3v0";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3000000>;
++				};
++			};
++
++			vcc3v3_s3: SWITCH_REG1 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-name = "vcc3v3_s3";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v3_s0: SWITCH_REG2 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-name = "vcc3v3_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++		};
++	};
++};
++
++&i2c1 {
++	status = "okay";
++	i2c-scl-rising-time-ns = <150>;
++	i2c-scl-falling-time-ns = <30>;
++	clock-frequency = <200000>;
++};
++
++&i2c2 {
++	status = "okay";
++};
++
++&i2c4 {
++	status = "okay";
++	i2c-scl-rising-time-ns = <160>;
++	i2c-scl-falling-time-ns = <30>;
++	clock-frequency = <400000>;
++
++	fusb0: fusb30x@22 {
++		compatible = "fairchild,fusb302";
++		reg = <0x22>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&fusb0_int>;
++		int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
++		vbus-5v-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
++		status = "okay";
++	};
++
++	gt9xx: goodix_ts@5d {
++		compatible = "goodix,gt9xx";
++		reg = <0x5d>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
++		goodix,irq-gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
++		goodix,rst-gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
++		status = "okay";
++	};
++
++	/*
++	onewire_ts@2f {
++		compatible = "onewire";
++		reg = <0x2f>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
++	}; */
++};
++
++&i2c7 {
++	status = "okay";
++};
++
++&i2s0 {
++	status = "okay";
++	rockchip,i2s-broken-burst-len;
++	rockchip,playback-channels = <8>;
++	rockchip,capture-channels = <8>;
++	#sound-dai-cells = <0>;
++};
++
++&i2s2 {
++	#sound-dai-cells = <0>;
++	status = "okay";
++};
++
++&io_domains {
++	status = "okay";
++
++	bt656-supply = <&vcc1v8_dvp>;		/* bt656_gpio2ab_ms */
++	audio-supply = <&vcca1v8_codec>;	/* audio_gpio3d4a_ms */
++	sdmmc-supply = <&vcc_sd>;		/* sdmmc_gpio4b_ms */
++	gpio1830-supply = <&vcc_3v0>;		/* gpio1833_gpio4cd_ms */
++};
++
++&pmu_io_domains {
++	status = "okay";
++	pmu1830-supply = <&vcc_3v0>;
++};
++
++&pcie_phy {
++	status = "okay";
++};
++
++&pcie0 {
++	status = "okay";
++	ep-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
++	num-lanes = <4>;
++};
++
++&pwm_bl {
++	status = "okay";
++	enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
++};
++
++&pwm0 {
++	status = "okay";
++};
++
++&pwm1 {
++	status = "okay";
++};
++
++&pwm2 {
++	status = "okay";
++};
++
++&saradc {
++	vref-supply = <&vccadc_ref>; /* TBD */
++};
++
++&sdhci {
++	bus-width = <8>;
++	//mmc-hs400-1_8v;
++	supports-emmc;
++	non-removable;
++	keep-power-in-suspend;
++	//mmc-hs400-enhanced-strobe;
++	status = "okay";
++};
++
++&emmc_phy {
++	status = "okay";
++};
++
++&sdio0 {
++	clock-frequency = <50000000>;
++	clock-freq-min-max = <200000 50000000>;
++	supports-sdio;
++	bus-width = <4>;
++	disable-wp;
++	cap-sd-highspeed;
++	cap-sdio-irq;
++	keep-power-in-suspend;
++	mmc-pwrseq = <&sdio_pwrseq>;
++	non-removable;
++	num-slots = <1>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
++	sd-uhs-sdr104;
++	status = "okay";
++};
++
++&sdmmc {
++	clock-frequency = <150000000>;
++	clock-freq-min-max = <100000 150000000>;
++	supports-sd;
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	disable-wp;
++	num-slots = <1>;
++	//sd-uhs-sdr104;
++	vqmmc-supply = <&vcc_sd>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
++	status = "okay";
++};
++
++&tsadc {
++	/* tshut mode 0:CRU 1:GPIO */
++	rockchip,hw-tshut-mode = <1>;
++	/* tshut polarity 0:LOW 1:HIGH */
++	rockchip,hw-tshut-polarity = <1>;
++	status = "okay";
++};
++
++&u2phy0 {
++	status = "okay";
++
++	u2phy0_otg: otg-port {
++		status = "okay";
++	};
++
++	u2phy0_host: host-port {
++		phy-supply = <&vcc5v0_host>;
++		status = "okay";
++	};
++};
++
++&u2phy1 {
++	status = "okay";
++
++	u2phy1_otg: otg-port {
++		status = "okay";
++	};
++
++	u2phy1_host: host-port {
++		phy-supply = <&vcc5v0_host>;
++		status = "okay";
++	};
++};
++
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	status = "okay";
++};
++
++&pinctrl {
++	pmic {
++		pmic_int_l: pmic-int-l {
++			rockchip,pins = <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++
++		vsel1_gpio: vsel1-gpio {
++			rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++		vsel2_gpio: vsel2-gpio {
++			rockchip,pins = <1 14 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++	};
++
++	fusb30x {
++		fusb0_int: fusb0-int {
++			rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	sdio-pwrseq {
++		wifi_enable_h: wifi-enable-h {
++			rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	rockchip-key {
++		power_key: power-key {
++			rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++};
+diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig
+new file mode 100644
+index 0000000..662c46e
+--- /dev/null
++++ b/configs/orangepi-rk3399_defconfig
+@@ -0,0 +1,75 @@
++CONFIG_ARM=y
++CONFIG_ARCH_ROCKCHIP=y
++CONFIG_SYS_TEXT_BASE=0x00200000
++CONFIG_SPL_LIBCOMMON_SUPPORT=y
++CONFIG_SPL_LIBGENERIC_SUPPORT=y
++CONFIG_SYS_MALLOC_F_LEN=0x4000
++CONFIG_ROCKCHIP_RK3399=y
++CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
++CONFIG_DEBUG_UART_BASE=0xFF1A0000
++CONFIG_DEBUG_UART_CLOCK=24000000
++CONFIG_SPL_STACK_R_ADDR=0x80000
++CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi"
++CONFIG_DEBUG_UART=y
++CONFIG_FIT=y
++CONFIG_SPL_LOAD_FIT=y
++CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
++# CONFIG_DISPLAY_CPUINFO is not set
++CONFIG_DISPLAY_BOARDINFO_LATE=y
++CONFIG_SPL_STACK_R=y
++CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
++CONFIG_SPL_ATF=y
++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
++CONFIG_CMD_BOOTZ=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_SF=y
++CONFIG_CMD_USB=y
++# CONFIG_CMD_SETEXPR is not set
++CONFIG_CMD_TIME=y
++CONFIG_SPL_OF_CONTROL=y
++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
++CONFIG_ENV_IS_IN_MMC=y
++CONFIG_REGMAP=y
++CONFIG_SPL_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_SPL_SYSCON=y
++CONFIG_CLK=y
++CONFIG_SPL_CLK=y
++CONFIG_ROCKCHIP_GPIO=y
++CONFIG_SYS_I2C_ROCKCHIP=y
++CONFIG_MMC_DW=y
++CONFIG_MMC_DW_ROCKCHIP=y
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_ROCKCHIP=y
++CONFIG_DM_ETH=y
++CONFIG_ETH_DESIGNWARE=y
++CONFIG_GMAC_ROCKCHIP=y
++CONFIG_PINCTRL=y
++CONFIG_SPL_PINCTRL=y
++CONFIG_PINCTRL_ROCKCHIP_RK3399=y
++CONFIG_DM_PMIC=y
++CONFIG_PMIC_RK8XX=y
++CONFIG_REGULATOR_PWM=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_REGULATOR_RK8XX=y
++CONFIG_PWM_ROCKCHIP=y
++CONFIG_RAM=y
++CONFIG_SPL_RAM=y
++CONFIG_BAUDRATE=1500000
++CONFIG_DEBUG_UART_SHIFT=2
++CONFIG_SYSRESET=y
++CONFIG_USB=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_DWC3=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_GENERIC=y
++CONFIG_USB_STORAGE=y
++CONFIG_USB_HOST_ETHER=y
++CONFIG_USB_ETHER_ASIX=y
++CONFIG_USB_ETHER_ASIX88179=y
++CONFIG_USB_ETHER_MCS7830=y
++CONFIG_USB_ETHER_RTL8152=y
++CONFIG_USB_ETHER_SMSC95XX=y
++CONFIG_USE_TINY_PRINTF=y
++CONFIG_ERRNO_STR=y

patch/u-boot/u-boot-rockchip64-dev/add-board-rockpi4b.patch

@@ -0,0 +1,774 @@
+diff --git a/configs/rockpi4b-rk3399_defconfig b/configs/rockpi4b-rk3399_defconfig
+new file mode 100644
+index 0000000..4a013c9
+--- /dev/null
++++ b/configs/rockpi4b-rk3399_defconfig
+@@ -0,0 +1,112 @@
++CONFIG_ARM=y
++CONFIG_ARCH_ROCKCHIP=y
++CONFIG_SPL_LIBCOMMON_SUPPORT=y
++CONFIG_SPL_LIBGENERIC_SUPPORT=y
++CONFIG_SYS_MALLOC_F_LEN=0x4000
++CONFIG_ROCKCHIP_RK3399=y
++CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
++CONFIG_TARGET_ROCKPRO64_RK3399=y
++CONFIG_SPL_SPI_FLASH_SUPPORT=y
++CONFIG_SPL_SPI_SUPPORT=y
++CONFIG_SPL_STACK_R_ADDR=0x600000
++CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpi4b"
++CONFIG_DEBUG_UART=y
++CONFIG_FIT=y
++CONFIG_SPL_LOAD_FIT=y
++CONFIG_SPL_FIT_GENERATOR="board/rockchip/rockpro64_rk3399/mk_fit_atf.sh"
++CONFIG_BOOTDELAY=2
++# CONFIG_DISPLAY_CPUINFO is not set
++CONFIG_ANDROID_BOOTLOADER=y
++CONFIG_SPL_BOOTROM_SUPPORT=y
++CONFIG_SPL_STACK_R=y
++CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
++CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
++CONFIG_SPL_MTD_SUPPORT=y
++CONFIG_SPL_ATF_SUPPORT=y
++CONFIG_FASTBOOT_BUF_ADDR=0x00800800
++CONFIG_FASTBOOT_BUF_SIZE=0x08000000
++CONFIG_FASTBOOT_FLASH=y
++CONFIG_FASTBOOT_FLASH_MMC_DEV=0
++CONFIG_CMD_BOOTZ=y
++# CONFIG_CMD_IMLS is not set
++CONFIG_CMD_MEMINFO=y
++CONFIG_CMD_SHA1SUM=y
++CONFIG_SHA1SUM_VERIFY=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_LOAD_ANDROID=y
++CONFIG_CMD_BOOT_ANDROID=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_SF=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_USB_MASS_STORAGE=y
++# CONFIG_CMD_SETEXPR is not set
++CONFIG_CMD_TIME=y
++CONFIG_CMD_REGULATOR=y
++CONFIG_CMD_MTDPARTS=y
++CONFIG_SPL_OF_CONTROL=y
++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
++CONFIG_ENV_IS_IN_SPI_FLASH=y
++CONFIG_SPL_DM_SEQ_ALIAS=y
++CONFIG_REGMAP=y
++CONFIG_SPL_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_SPL_SYSCON=y
++CONFIG_CLK=y
++CONFIG_SPL_CLK=y
++CONFIG_ROCKCHIP_GPIO=y
++CONFIG_SYS_I2C_ROCKCHIP=y
++CONFIG_LED=y
++CONFIG_LED_GPIO=y
++CONFIG_MISC=y
++CONFIG_ROCKCHIP_EFUSE=y
++CONFIG_MMC_DW=y
++CONFIG_MMC_DW_ROCKCHIP=y
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_ROCKCHIP=y
++CONFIG_SPI_FLASH=y
++CONFIG_SPI_FLASH_GIGADEVICE=y
++CONFIG_SPI_FLASH_WINBOND=y
++CONFIG_DM_ETH=y
++CONFIG_ETH_DESIGNWARE=y
++CONFIG_GMAC_ROCKCHIP=y
++CONFIG_PINCTRL=y
++CONFIG_SPL_PINCTRL=y
++CONFIG_PINCTRL_ROCKCHIP_RK3399=y
++CONFIG_DM_PMIC=y
++CONFIG_PMIC_RK8XX=y
++CONFIG_REGULATOR_PWM=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_REGULATOR_RK8XX=y
++CONFIG_PWM_ROCKCHIP=y
++CONFIG_RAM=y
++CONFIG_SPL_RAM=y
++CONFIG_DM_RESET=y
++CONFIG_BAUDRATE=1500000
++CONFIG_DEBUG_UART_BASE=0xFF1A0000
++CONFIG_DEBUG_UART_CLOCK=24000000
++CONFIG_DEBUG_UART_SHIFT=2
++CONFIG_SYS_NS16550=y
++CONFIG_ROCKCHIP_SPI=y
++CONFIG_SYSRESET=y
++CONFIG_USB=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_DWC3=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_GENERIC=y
++CONFIG_USB_DWC3=y
++CONFIG_USB_DWC3_GADGET=y
++CONFIG_USB_STORAGE=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_GADGET_DOWNLOAD=y
++CONFIG_G_DNL_MANUFACTURER="Rockchip"
++CONFIG_G_DNL_VENDOR_NUM=0x18d1
++CONFIG_G_DNL_PRODUCT_NUM=0xd00d
++CONFIG_USB_HOST_ETHER=y
++CONFIG_USB_ETHER_ASIX=y
++CONFIG_USB_ETHER_ASIX88179=y
++CONFIG_USB_ETHER_MCS7830=y
++CONFIG_USB_ETHER_RTL8152=y
++CONFIG_USB_ETHER_SMSC95XX=y
++CONFIG_USE_TINY_PRINTF=y
++CONFIG_ERRNO_STR=y
+diff --git a/arch/arm/dts/rk3399-rockpi4b.dts b/arch/arm/dts/rk3399-rockpi4b.dts
+new file mode 100644
+index 0000000..41dc902
+--- /dev/null
++++ b/arch/arm/dts/rk3399-rockpi4b.dts
+@@ -0,0 +1,638 @@
++/*
++ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
++ *
++ * SPDX-License-Identifier:     GPL-2.0+
++ */
++
++/dts-v1/;
++#include <dt-bindings/pwm/pwm.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include "rk3399.dtsi"
++
++/ {
++	model = "RockPi-4B";
++	compatible = "radxa,rockpi-4b", "rockchip,rk3399";
++
++	chosen {
++		stdout-path = &uart2;
++	};
++
++	aliases {
++		spi0 = &spi1;
++	};
++
++	backlight: backlight {
++		compatible = "pwm-backlight";
++		enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
++		pwms = <&pwm0 0 25000 0>;
++		brightness-levels = <
++			  0   1   2   3   4   5   6   7
++			  8   9  10  11  12  13  14  15
++			 16  17  18  19  20  21  22  23
++			 24  25  26  27  28  29  30  31
++			 32  33  34  35  36  37  38  39
++			 40  41  42  43  44  45  46  47
++			 48  49  50  51  52  53  54  55
++			 56  57  58  59  60  61  62  63
++			 64  65  66  67  68  69  70  71
++			 72  73  74  75  76  77  78  79
++			 80  81  82  83  84  85  86  87
++			 88  89  90  91  92  93  94  95
++			 96  97  98  99 100 101 102 103
++			104 105 106 107 108 109 110 111
++			112 113 114 115 116 117 118 119
++			120 121 122 123 124 125 126 127
++			128 129 130 131 132 133 134 135
++			136 137 138 139 140 141 142 143
++			144 145 146 147 148 149 150 151
++			152 153 154 155 156 157 158 159
++			160 161 162 163 164 165 166 167
++			168 169 170 171 172 173 174 175
++			176 177 178 179 180 181 182 183
++			184 185 186 187 188 189 190 191
++			192 193 194 195 196 197 198 199
++			200 201 202 203 204 205 206 207
++			208 209 210 211 212 213 214 215
++			216 217 218 219 220 221 222 223
++			224 225 226 227 228 229 230 231
++			232 233 234 235 236 237 238 239
++			240 241 242 243 244 245 246 247
++			248 249 250 251 252 253 254 255>;
++		default-brightness-level = <200>;
++	};
++
++	leds {
++		status = "okay";
++		compatible = "gpio-leds";
++
++		power-led {
++			label = "power";
++			gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
++		};
++
++		standby-led {
++			label = "standby";
++			gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
++		};
++	};
++
++	clkin_gmac: external-gmac-clock {
++		compatible = "fixed-clock";
++		clock-frequency = <125000000>;
++		clock-output-names = "clkin_gmac";
++		#clock-cells = <0>;
++	};
++
++	sdio_pwrseq: sdio-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rk808 1>;
++		clock-names = "ext_clock";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_enable_h>;
++
++		/*
++		 * On the module itself this is one of these (depending
++		 * on the actual card populated):
++		 * - SDIO_RESET_L_WL_REG_ON
++		 * - PDN (power down when low)
++		 */
++		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
++	};
++
++	vcc1v8_s0: vcc1v8-s0 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc1v8_s0";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++	};
++
++	dc_12v: dc-12v {
++		compatible = "regulator-fixed";
++		regulator-name = "dc_12v";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <12000000>;
++		regulator-max-microvolt = <12000000>;
++	};
++
++	vcc_sys: vcc-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_sys";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++		vin-supply = <&dc_12v>;
++	};
++
++	vcc3v3_sys: vcc3v3-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc_sys>;
++	};
++
++	vcc5v0_host: vcc5v0-host-regulator {
++		compatible = "regulator-fixed";
++		gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&host_vbus_drv>;
++		regulator-name = "vcc5v0_host";
++	};
++
++	vcc5v0_typec0: vcc5v0-typec0-en {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_typec0";
++		gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
++	};
++
++	vcc_phy: vcc-phy-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_phy";
++		regulator-always-on;
++		regulator-boot-on;
++	};
++
++	vdd_log: vdd-log {
++		compatible = "pwm-regulator";
++		pwms = <&pwm2 0 25000 1>;
++		regulator-name = "vdd_log";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-init-microvolt = <900000>;
++		regulator-min-microvolt = <800000>;
++		regulator-max-microvolt = <1400000>;
++	};
++};
++
++&cpu_l0 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l1 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l2 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&cpu_l3 {
++	cpu-supply = <&vdd_cpu_l>;
++};
++
++&emmc_phy {
++	status = "okay";
++};
++
++&gmac {
++	assigned-clocks = <&cru SCLK_RMII_SRC>;
++	assigned-clock-parents = <&clkin_gmac>;
++	clock_in_out = "input";
++	phy-supply = <&vcc_phy>;
++	phy-mode = "rgmii";
++	pinctrl-names = "default";
++	pinctrl-0 = <&rgmii_pins>;
++	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	snps,reset-delays-us = <0 10000 50000>;
++	tx_delay = <0x28>;
++	rx_delay = <0x20>;
++	status = "okay";
++};
++
++&i2c0 {
++	clock-frequency = <400000>;
++	i2c-scl-rising-time-ns = <168>;
++	i2c-scl-falling-time-ns = <4>;
++	status = "okay";
++
++	rk808: pmic@1b {
++		compatible = "rockchip,rk808";
++		reg = <0x1b>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
++		#clock-cells = <1>;
++		clock-output-names = "xin32k", "rk808-clkout2";
++		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_int_l>;
++		rockchip,system-power-controller;
++		wakeup-source;
++
++		vcc1-supply = <&vcc_sys>;
++		vcc2-supply = <&vcc_sys>;
++		vcc3-supply = <&vcc_sys>;
++		vcc4-supply = <&vcc_sys>;
++		vcc6-supply = <&vcc_sys>;
++		vcc7-supply = <&vcc_sys>;
++		vcc8-supply = <&vcc3v3_sys>;
++		vcc9-supply = <&vcc_sys>;
++		vcc10-supply = <&vcc_sys>;
++		vcc11-supply = <&vcc_sys>;
++		vcc12-supply = <&vcc3v3_sys>;
++		vddio-supply = <&vcc_1v8>;
++
++		regulators {
++			vdd_center: DCDC_REG1 {
++				regulator-name = "vdd_center";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_cpu_l: DCDC_REG2 {
++				regulator-name = "vdd_cpu_l";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_ddr: DCDC_REG3 {
++				regulator-name = "vcc_ddr";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vcc_1v8: DCDC_REG4 {
++				regulator-name = "vcc_1v8";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc1v8_dvp: LDO_REG1 {
++				regulator-name = "vcc1v8_dvp";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v0_touch: LDO_REG2 {
++				regulator-name = "vcc3v0_touch";
++				regulator-min-microvolt = <3000000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3000000>;
++				};
++			};
++
++			vcc1v8_pmu: LDO_REG3 {
++				regulator-name = "vcc1v8_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc_sd: LDO_REG4 {
++				regulator-name = "vcc_sd";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcca3v0_codec: LDO_REG5 {
++				regulator-name = "vcca3v0_codec";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3000000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_1v5: LDO_REG6 {
++				regulator-name = "vcc_1v5";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1500000>;
++				regulator-max-microvolt = <1500000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1500000>;
++				};
++			};
++
++			vcca1v8_codec: LDO_REG7 {
++				regulator-name = "vcca1v8_codec";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_3v0: LDO_REG8 {
++				regulator-name = "vcc_3v0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3000000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3000000>;
++				};
++			};
++
++			vcc3v0_sd: vcc3v0-sd {
++				compatible = "regulator-fixed";
++				enable-active-high;
++				gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
++				pinctrl-names = "default";
++				pinctrl-0 = <&sdmmc0_pwr_h>;
++				regulator-always-on;
++				regulator-max-microvolt = <3000000>;
++				regulator-min-microvolt = <3000000>;
++				regulator-name = "vcc3v0_sd";
++				vin-supply = <&vcc3v3_sys>;
++			};
++
++			vcc3v3_s3: SWITCH_REG1 {
++				regulator-name = "vcc3v3_s3";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v3_s0: SWITCH_REG2 {
++				regulator-name = "vcc3v3_s0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++		};
++	};
++};
++
++&i2c1 {
++	i2c-scl-rising-time-ns = <300>;
++	i2c-scl-falling-time-ns = <15>;
++	status = "okay";
++};
++
++&i2c3 {
++	i2c-scl-rising-time-ns = <450>;
++	i2c-scl-falling-time-ns = <15>;
++	status = "okay";
++};
++
++&i2c4 {
++	i2c-scl-rising-time-ns = <600>;
++	i2c-scl-falling-time-ns = <20>;
++	status = "okay";
++};
++
++&io_domains {
++	status = "okay";
++
++	bt656-supply = <&vcc1v8_s0>;
++	audio-supply = <&vcc1v8_s0>;
++	sdmmc-supply = <&vcc_sd>;
++	gpio1830-supply = <&vcc_3v0>;
++};
++
++&pmu_io_domains {
++	pmu1830-supply = <&vcc_3v0>;
++	status = "okay";
++};
++
++&pinctrl {
++	pmic {
++		vsel1_gpio: vsel1-gpio {
++			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++
++		vsel2_gpio: vsel2-gpio {
++			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++	};
++
++	sd {
++		sdmmc0_pwr_h: sdmmc0-pwr-h {
++			rockchip,pins =
++				<RK_GPIO0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	sdio-pwrseq {
++		wifi_enable_h: wifi-enable-h {
++			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	pmic {
++		pmic_int_l: pmic-int-l {
++			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	usb2 {
++		host_vbus_drv: host-vbus-drv {
++			rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
++
++&pwm0 {
++	status = "okay";
++};
++
++&pwm2 {
++	status = "okay";
++};
++
++&saradc {
++	status = "okay";
++};
++
++&sdmmc {
++	vmmc-supply = <&vcc3v0_sd>;
++	u-boot,dm-spl;
++	bus-width = <4>;
++	status = "okay";
++	max-frequency = <20000000>;
++};
++
++&sdhci {
++	u-boot,dm-spl;
++	bus-width = <8>;
++	max-frequency = <25000000>;
++	mmc-hs400-1_8v;
++	mmc-hs400-enhanced-strobe;
++	non-removable;
++	status = "okay";
++};
++
++&tsadc {
++	/* tshut mode 0:CRU 1:GPIO */
++	rockchip,hw-tshut-mode = <1>;
++	/* tshut polarity 0:LOW 1:HIGH */
++	rockchip,hw-tshut-polarity = <1>;
++	status = "okay";
++};
++
++&u2phy0 {
++	/delete-property/ clocks;
++	/delete-property/ clock-names;
++
++	status = "okay";
++
++	u2phy0_otg: otg-port {
++		status = "okay";
++	};
++
++	u2phy0_host: host-port {
++		phy-supply = <&vcc5v0_host>;
++		status = "okay";
++	};
++};
++
++&u2phy1 {
++	/delete-property/ clocks;
++	/delete-property/ clock-names;
++
++	status = "okay";
++
++	u2phy1_otg: otg-port {
++		status = "okay";
++	};
++
++	u2phy1_host: host-port {
++		phy-supply = <&vcc5v0_host>;
++		status = "okay";
++	};
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_xfer &uart0_cts>;
++	status = "okay";
++};
++
++&uart2 {
++	u-boot,dm-pre-reloc;
++	status = "okay";
++};
++
++&dwc3_typec0 {
++	status = "okay";
++	maximum-speed = "high-speed";
++};
++
++&usb_host0_ehci {
++	/delete-property/ clocks;
++	/delete-property/ clock-names;
++
++	vbus-supply = <&vcc5v0_host>;
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	/delete-property/ clocks;
++	/delete-property/ clock-names;
++
++	vbus-supply = <&vcc5v0_host>;
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	/delete-property/ clocks;
++	/delete-property/ clock-names;
++
++	vbus-supply = <&vcc5v0_host>;
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	/delete-property/ clocks;
++	/delete-property/ clock-names;
++
++	vbus-supply = <&vcc5v0_host>;
++	status = "okay";
++};
++
++&dwc3_typec1 {
++	vbus-supply = <&vcc5v0_host>;
++	status = "okay";
++	maximum-speed = "high-speed";
++};
++
++&spi1 {
++	u-boot,dm-spl;
++	status = "okay";
++
++	spiflash: spi-flash@0 {
++		u-boot,dm-spl;
++		#address-cells = <0x1>;
++		#size-cells = <1>;
++		compatible = "spi-flash";
++		reg = <0x0>;
++		spi-max-frequency = <25000000>;
++		status = "okay";
++
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			loader@8000 {
++				label = "loader";
++				reg = <0x0 0x3F8000>;
++			};
++
++			env@3f8000 {
++				label = "env";
++				reg = <0x3F8000 0x8000>;
++			};
++
++			vendor@7c0000 {
++				label = "vendor";
++				reg = <0x7C0000 0x40000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index af9d200..a6c7199 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -56,6 +57,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+ 	rk3399-puma-ddr1333.dtb \
+ 	rk3399-puma-ddr1600.dtb \
+ 	rk3399-puma-ddr1866.dtb \
++	rk3399-rockpi4b.dtb \
+ 	rk3399-rockpro64.dtb \
+ 	rv1108-evb.dtb
+ dtb-$(CONFIG_ARCH_MESON) += \

patch/u-boot/u-boot-sun50iw2/add-a64-olinuxino-emmc-support.patch.disabled

@@ -1,34 +0,0 @@
-diff --git a/arch/arm/dts/sun50i-a64-olinuxino.dts b/arch/arm/dts/sun50i-a64-olinuxino.dts
-index 7bd4730..cda5b3e 100644
---- a/arch/arm/dts/sun50i-a64-olinuxino.dts
-+++ b/arch/arm/dts/sun50i-a64-olinuxino.dts
-@@ -77,6 +77,16 @@
- 	status = "okay";
- };
- 
-+&mmc2 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&mmc2_pins>;
-+	vmmc-supply = <&reg_vcc3v3>;
-+	bus-width = <8>;
-+	non-removable;
-+	cap-mmc-hw-reset;
-+	status = "okay";
-+};
-+
- &uart0 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&uart0_pins_a>;
-diff --git a/configs/a64-olinuxino_defconfig b/configs/a64-olinuxino_defconfig
-index b32df99..4497dbe 100644
---- a/configs/a64-olinuxino_defconfig
-+++ b/configs/a64-olinuxino_defconfig
-@@ -9,6 +9,8 @@ CONFIG_NR_DRAM_BANKS=1
- # CONFIG_CMD_FLASH is not set
- # CONFIG_SPL_DOS_PARTITION is not set
- # CONFIG_SPL_EFI_PARTITION is not set
-+CONFIG_SPL_SPI_FLASH_SUPPORT=y
-+CONFIG_SPL_SPI_SUNXI=y
- CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-olinuxino"
- CONFIG_SUN8I_EMAC=y
- CONFIG_USB_EHCI_HCD=y

patch/u-boot/u-boot-sunxi/add-xx-nanopi-k1-plus-emmc.patch

@@ -15,7 +15,7 @@ new file mode 100644
 index 0000000..c08af78
 --- /dev/null
 +++ b/arch/arm/dts/sun50i-h5-nanopi-k1-plus.dts
-@@ -0,0 +1,96 @@
+@@ -0,0 +1,125 @@
 +/*
 + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
 + * Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
@@ -112,6 +112,35 @@ index 0000000..c08af78
 +	pinctrl-0 = <&uart0_pins_a>;
 +	status = "okay";
 +};
++
++&usbphy {
++	status = "okay";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&ohci2 {
++	status = "okay";
++};
++
++&ehci2 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
 diff --git a/configs/nanopi_k1_plus_defconfig b/configs/nanopi_k1_plus_defconfig
 new file mode 100644
 index 0000000..670c3c7