diff --git a/patch/kernel/meson64-dev/0022-drm-bridge-dw-hdmi-Add-SCDC-and-TMDS-Scrambling-supp.patch b/patch/kernel/meson64-dev/0022-drm-bridge-dw-hdmi-Add-SCDC-and-TMDS-Scrambling-supp.patch index f5f77f5c1..b738cfa25 100644 --- a/patch/kernel/meson64-dev/0022-drm-bridge-dw-hdmi-Add-SCDC-and-TMDS-Scrambling-supp.patch +++ b/patch/kernel/meson64-dev/0022-drm-bridge-dw-hdmi-Add-SCDC-and-TMDS-Scrambling-supp.patch @@ -29,70 +29,6 @@ diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/ index 1fc12708dbb5..2a30d8393477 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -28,6 +28,7 @@ - #include - #include - #include -+#include - #include - - #include -@@ -1026,6 +1027,20 @@ void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, - } - EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write); - -+/*void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi) -+{ -+ unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mpixelclock; -+ -+*/ /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ -+/* if (hdmi->connector.display_info.hdmi.scdc.supported) { -+ if (mtmdsclock > 340000000) -+ drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1); -+ else -+ drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0); -+ } -+} -+EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio); -+*/ - static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) - { - hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, -@@ -1351,11 +1366,12 @@ static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi) - - static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) - { -+ bool is_hdmi2_sink = hdmi->connector.display_info.hdmi.scdc.supported; - struct hdmi_avi_infoframe frame; - u8 val; - - /* Initialise info frame from DRM mode */ -- drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); -+ drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2_sink); - - if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) - frame.colorspace = HDMI_COLORSPACE_YUV444; -@@ -1514,7 +1530,8 @@ static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, - static void hdmi_av_composer(struct dw_hdmi *hdmi, - const struct drm_display_mode *mode) - { -- u8 inv_val; -+ u8 inv_val, bytes; -+ struct drm_hdmi_info *hdmi_info = &hdmi->connector.display_info.hdmi; - struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; - int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; - unsigned int vdisplay; -@@ -1524,7 +1541,9 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi, - dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); - - /* Set up HDMI_FC_INVIDCONF */ -- inv_val = (hdmi->hdmi_data.hdcp_enable ? -+ inv_val = (hdmi->hdmi_data.hdcp_enable || -+ vmode->mpixelclock > 340000000 || -+ hdmi_info->scdc.scrambling.low_rates ? - HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : - HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); - @@ -1573,6 +1592,26 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi, vsync_len /= 2; } @@ -120,27 +56,3 @@ index 1fc12708dbb5..2a30d8393477 100644 /* Set up horizontal active pixel width */ hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1); hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0); -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h -index 9d90eb9c46e5..3f3c616eba97 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h -@@ -255,6 +255,7 @@ - #define HDMI_FC_MASK2 0x10DA - #define HDMI_FC_POL2 0x10DB - #define HDMI_FC_PRCONF 0x10E0 -+#define HDMI_FC_SCRAMBLER_CTRL 0x10E1 - - #define HDMI_FC_GMD_STAT 0x1100 - #define HDMI_FC_GMD_EN 0x1101 -diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h -index ccb5aa8468e0..d7cc5d094270 100644 ---- a/include/drm/bridge/dw_hdmi.h -+++ b/include/drm/bridge/dw_hdmi.h -@@ -156,6 +156,7 @@ void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense); - void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate); - void dw_hdmi_audio_enable(struct dw_hdmi *hdmi); - void dw_hdmi_audio_disable(struct dw_hdmi *hdmi); -+void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi); - - /* PHY configuration */ - void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address); diff --git a/patch/kernel/meson64-dev/0028-drm-meson-Add-YUV420-output-support.patch b/patch/kernel/meson64-dev/0028-drm-meson-Add-YUV420-output-support.patch index 3534d8304..cfac9445e 100644 --- a/patch/kernel/meson64-dev/0028-drm-meson-Add-YUV420-output-support.patch +++ b/patch/kernel/meson64-dev/0028-drm-meson-Add-YUV420-output-support.patch @@ -118,20 +118,6 @@ index b8775102b100..83360f37d9ce 100644 unsigned int vclk_freq; unsigned int venc_freq; unsigned int hdmi_freq; -@@ -573,9 +589,11 @@ dw_hdmi_mode_valid(struct drm_connector *connector, - mode->vdisplay, mode->vsync_start, - mode->vsync_end, mode->vtotal, mode->type, mode->flags); - -- /* If sink max TMDS clock < 340MHz, we reject the HDMI2.0 modes */ -+ /* If sink does not support 540MHz, reject the non-420 HDMI2 modes */ - if (mode->clock > 340000 && -- connector->display_info.max_tmds_clock < 340000) -+ connector->display_info.max_tmds_clock < 340000 && -+ !drm_mode_is_420_only(&connector->display_info, mode) && -+ !drm_mode_is_420_also(&connector->display_info, mode)) - return MODE_BAD; - - /* Check against non-VIC supported modes */ @@ -591,6 +609,15 @@ dw_hdmi_mode_valid(struct drm_connector *connector, vclk_freq = mode->clock;