From 358b498d48abff02563a5a788def50b956829eb1 Mon Sep 17 00:00:00 2001 From: ThomasKaiser Date: Sat, 2 Apr 2016 19:30:55 +0200 Subject: [PATCH] Bumpt dev branch to 4.6.0-rc1, switch sun8i mainline to wens/h3-emac, adopt sun7i/sun8i led behaviour for mainline --- config/linux-sunxi-dev.config | 189 +- configuration.sh | 26 +- patch/kernel/sunxi-dev/0000-sun8i-h3.patch | 700 ------- ...sun8i-add-sun8i-emac-ethernet-driver.patch | 59 - ...M-dts-sun8i-Add-Orange-Pi-PC-support.patch | 146 -- ...nable-sun8i-emac-on-the-Orange-PI-PC.patch | 32 - .../0005-ethernet-add-sun8i-emac-driver.patch | 1671 ----------------- .../packaging-with-postinstall-scripts.patch | 8 +- .../u-boot-99-opi-change-build-settings.patch | 45 + scripts/armhwinfo | 13 +- scripts/firstrun | 6 +- 11 files changed, 191 insertions(+), 2704 deletions(-) delete mode 100644 patch/kernel/sunxi-dev/0000-sun8i-h3.patch delete mode 100644 patch/kernel/sunxi-dev/0001-ARM-dts-sun8i-add-sun8i-emac-ethernet-driver.patch delete mode 100644 patch/kernel/sunxi-dev/0002-ARM-dts-sun8i-Add-Orange-Pi-PC-support.patch delete mode 100644 patch/kernel/sunxi-dev/0003-ARM-dts-sun8i-Enable-sun8i-emac-on-the-Orange-PI-PC.patch delete mode 100644 patch/kernel/sunxi-dev/0005-ethernet-add-sun8i-emac-driver.patch create mode 100644 patch/u-boot/u-boot-dev/u-boot-99-opi-change-build-settings.patch diff --git a/config/linux-sunxi-dev.config b/config/linux-sunxi-dev.config index 05411a8c9..f8f91ec0a 100644 --- a/config/linux-sunxi-dev.config +++ b/config/linux-sunxi-dev.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 4.5.0 Kernel Configuration +# Linux/arm 4.6.0-rc1 Kernel Configuration # CONFIG_ARM=y CONFIG_ARM_HAS_SG_CHAIN=y @@ -167,6 +167,8 @@ CONFIG_SYSFS_SYSCALL=y # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y @@ -339,6 +341,7 @@ CONFIG_ARCH_MULTI_V6_V7=y # CONFIG_ARCH_VIRT is not set # CONFIG_ARCH_MVEBU is not set # CONFIG_ARCH_ALPINE is not set +# CONFIG_ARCH_ARTPEC is not set # CONFIG_ARCH_AT91 is not set # CONFIG_ARCH_BCM is not set # CONFIG_ARCH_BERLIN is not set @@ -387,10 +390,6 @@ CONFIG_ARCH_R8A7791=y CONFIG_ARCH_R8A7793=y CONFIG_ARCH_R8A7794=y CONFIG_ARCH_SH73A0=y - -# -# Renesas ARM SoCs System Configuration -# CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN4I=y CONFIG_MACH_SUN5I=y @@ -449,7 +448,8 @@ CONFIG_ARM_L1_CACHE_SHIFT_6=y CONFIG_ARM_L1_CACHE_SHIFT=6 CONFIG_ARM_DMA_MEM_BUFFERABLE=y CONFIG_ARM_HEAVY_MB=y -# CONFIG_ARM_KERNMEM_PERMS is not set +CONFIG_DEBUG_RODATA=y +CONFIG_DEBUG_ALIGN_RODATA=y CONFIG_MULTI_IRQ_HANDLER=y # CONFIG_ARM_ERRATA_430973 is not set CONFIG_ARM_ERRATA_643719=y @@ -721,7 +721,6 @@ CONFIG_INET_TUNNEL=m CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m CONFIG_INET_XFRM_MODE_BEET=m -CONFIG_INET_LRO=y CONFIG_INET_DIAG=m CONFIG_INET_TCP_DIAG=m CONFIG_INET_UDP_DIAG=m @@ -1255,6 +1254,7 @@ CONFIG_NET_ACT_CSUM=m CONFIG_NET_ACT_VLAN=m CONFIG_NET_ACT_BPF=m CONFIG_NET_ACT_CONNMARK=m +# CONFIG_NET_ACT_IFE is not set CONFIG_NET_CLS_IND=y CONFIG_NET_SCH_FIFO=y CONFIG_DCB=y @@ -1264,7 +1264,6 @@ CONFIG_OPENVSWITCH=m CONFIG_OPENVSWITCH_GRE=m CONFIG_OPENVSWITCH_VXLAN=m # CONFIG_VSOCKETS is not set -CONFIG_NETLINK_MMAP=y CONFIG_NETLINK_DIAG=m CONFIG_MPLS=y CONFIG_NET_MPLS_GSO=m @@ -1321,20 +1320,22 @@ CONFIG_CAN_SLCAN=m CONFIG_CAN_DEV=m CONFIG_CAN_CALC_BITTIMING=y # CONFIG_CAN_LEDS is not set -CONFIG_CAN_TI_HECC=m CONFIG_CAN_FLEXCAN=m CONFIG_CAN_GRCAN=m CONFIG_CAN_RCAR=m CONFIG_CAN_SUN4I=m -CONFIG_CAN_SJA1000=m -CONFIG_CAN_SJA1000_ISA=m -CONFIG_CAN_SJA1000_PLATFORM=m +CONFIG_CAN_TI_HECC=m CONFIG_CAN_C_CAN=m CONFIG_CAN_C_CAN_PLATFORM=m -CONFIG_CAN_M_CAN=m CONFIG_CAN_CC770=m CONFIG_CAN_CC770_ISA=m CONFIG_CAN_CC770_PLATFORM=m +# CONFIG_CAN_IFI_CANFD is not set +CONFIG_CAN_M_CAN=m +CONFIG_CAN_SJA1000=m +CONFIG_CAN_SJA1000_ISA=m +CONFIG_CAN_SJA1000_PLATFORM=m +CONFIG_CAN_SOFTING=m # # CAN SPI interfaces @@ -1350,7 +1351,6 @@ CONFIG_CAN_GS_USB=m CONFIG_CAN_KVASER_USB=m CONFIG_CAN_PEAK_USB=m CONFIG_CAN_8DEV_USB=m -CONFIG_CAN_SOFTING=m # CONFIG_CAN_DEBUG_DEVICES is not set CONFIG_IRDA=m @@ -1404,6 +1404,7 @@ CONFIG_BT_HIDP=m CONFIG_BT_HS=y CONFIG_BT_LE=y # CONFIG_BT_6LOWPAN is not set +# CONFIG_BT_LEDS is not set # CONFIG_BT_SELFTEST is not set CONFIG_BT_DEBUGFS=y @@ -1426,6 +1427,7 @@ CONFIG_BT_HCIUART_LL=y # CONFIG_BT_HCIUART_INTEL is not set # CONFIG_BT_HCIUART_BCM is not set # CONFIG_BT_HCIUART_QCA is not set +# CONFIG_BT_HCIUART_AG6XX is not set CONFIG_BT_HCIBCM203X=m CONFIG_BT_HCIBPA10X=m CONFIG_BT_HCIBFUSB=m @@ -1436,6 +1438,7 @@ CONFIG_BT_ATH3K=m CONFIG_AF_RXRPC=m # CONFIG_AF_RXRPC_DEBUG is not set CONFIG_RXKAD=m +# CONFIG_AF_KCM is not set CONFIG_FIB_RULES=y CONFIG_WIRELESS=y CONFIG_WIRELESS_EXT=y @@ -1445,7 +1448,6 @@ CONFIG_WEXT_PRIV=y CONFIG_CFG80211=m # CONFIG_NL80211_TESTMODE is not set CONFIG_CFG80211_DEVELOPER_WARNINGS=y -# CONFIG_CFG80211_REG_DEBUG is not set # CONFIG_CFG80211_CERTIFICATION_ONUS is not set CONFIG_CFG80211_DEFAULT_PS=y # CONFIG_CFG80211_DEBUGFS is not set @@ -1480,6 +1482,9 @@ CONFIG_CEPH_LIB=m # CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set # CONFIG_NFC is not set CONFIG_LWTUNNEL=y +CONFIG_DST_CACHE=y +# CONFIG_NET_DEVLINK is not set +CONFIG_MAY_USE_DEVLINK=y CONFIG_HAVE_BPF_JIT=y # @@ -1509,7 +1514,7 @@ CONFIG_DEV_COREDUMP=y # CONFIG_GENERIC_CPU_DEVICES is not set CONFIG_REGMAP=y CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_SPI=m +CONFIG_REGMAP_SPI=y CONFIG_REGMAP_MMIO=y CONFIG_REGMAP_IRQ=y CONFIG_DMA_SHARED_BUFFER=y @@ -1533,7 +1538,7 @@ CONFIG_ARM_CCI=y CONFIG_ARM_CCI_PMU=y CONFIG_ARM_CCI400_COMMON=y CONFIG_ARM_CCI400_PMU=y -CONFIG_ARM_CCI500_PMU=y +# CONFIG_ARM_CCI5xx_PMU is not set # CONFIG_ARM_CCN is not set # CONFIG_BRCMSTB_GISB_ARB is not set # CONFIG_SIMPLE_PM_BUS is not set @@ -1667,12 +1672,13 @@ CONFIG_SENSORS_TSL2550=m # CONFIG_HMC6352 is not set # CONFIG_DS1682 is not set # CONFIG_TI_DAC7512 is not set -CONFIG_BMP085=y +CONFIG_BMP085=m CONFIG_BMP085_I2C=m # CONFIG_BMP085_SPI is not set # CONFIG_USB_SWITCH_FSA9480 is not set # CONFIG_LATTICE_ECP3_CONFIG is not set # CONFIG_SRAM is not set +# CONFIG_PANEL is not set # CONFIG_C2PORT is not set # @@ -1705,6 +1711,10 @@ CONFIG_EEPROM_93CX6=m # SCIF Bus Driver # +# +# VOP Bus Driver +# + # # Intel MIC Host Driver # @@ -1720,6 +1730,10 @@ CONFIG_EEPROM_93CX6=m # # Intel MIC Coprocessor State Management (COSM) Drivers # + +# +# VOP Driver +# # CONFIG_ECHO is not set # CONFIG_CXL_BASE is not set # CONFIG_CXL_KERNEL_API is not set @@ -1829,7 +1843,6 @@ CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m CONFIG_DM_THIN_PROVISIONING=m CONFIG_DM_CACHE=m -CONFIG_DM_CACHE_MQ=m CONFIG_DM_CACHE_SMQ=m CONFIG_DM_CACHE_CLEANER=m # CONFIG_DM_ERA is not set @@ -1860,6 +1873,7 @@ CONFIG_MACVTAP=m CONFIG_IPVLAN=m CONFIG_VXLAN=m # CONFIG_GENEVE is not set +# CONFIG_MACSEC is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set @@ -1884,7 +1898,7 @@ CONFIG_ATM_DRIVERS=y # CONFIG_NET_DSA_MV88E6060 is not set # CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set # CONFIG_NET_DSA_MV88E6131 is not set -# CONFIG_NET_DSA_MV88E6123_61_65 is not set +# CONFIG_NET_DSA_MV88E6123 is not set # CONFIG_NET_DSA_MV88E6171 is not set # CONFIG_NET_DSA_MV88E6352 is not set # CONFIG_NET_DSA_BCM_SF2 is not set @@ -1980,6 +1994,7 @@ CONFIG_MDIO_SUN4I=y # CONFIG_MDIO_BUS_MUX_MMIOREG is not set # CONFIG_MDIO_BCM_UNIMAC is not set # CONFIG_MICREL_KS8995MA is not set +CONFIG_SUN8I_H3_EPHY=y # CONFIG_PLIP is not set CONFIG_PPP=m CONFIG_PPP_BSDCOMP=m @@ -2217,6 +2232,7 @@ CONFIG_KEYBOARD_BCM=m CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=y CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_CYPRESS=y @@ -2266,6 +2282,7 @@ CONFIG_TOUCHSCREEN_GOODIX=m # CONFIG_TOUCHSCREEN_MAX11801 is not set # CONFIG_TOUCHSCREEN_MCS5000 is not set # CONFIG_TOUCHSCREEN_MMS114 is not set +# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set # CONFIG_TOUCHSCREEN_MTOUCH is not set CONFIG_TOUCHSCREEN_IMX6UL_TSC=m # CONFIG_TOUCHSCREEN_INEXIO is not set @@ -2280,7 +2297,6 @@ CONFIG_TOUCHSCREEN_IMX6UL_TSC=m # CONFIG_TOUCHSCREEN_WM97XX is not set # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set -# CONFIG_TOUCHSCREEN_TS4800 is not set # CONFIG_TOUCHSCREEN_TSC_SERIO is not set # CONFIG_TOUCHSCREEN_TSC2004 is not set # CONFIG_TOUCHSCREEN_TSC2005 is not set @@ -2308,7 +2324,6 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_YEALINK is not set # CONFIG_INPUT_CM109 is not set # CONFIG_INPUT_REGULATOR_HAPTIC is not set -CONFIG_INPUT_AXP20X_PEK=y # CONFIG_INPUT_UINPUT is not set # CONFIG_INPUT_PCF8574 is not set # CONFIG_INPUT_PWM_BEEPER is not set @@ -2320,6 +2335,7 @@ CONFIG_INPUT_AXP20X_PEK=y # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set # CONFIG_INPUT_DRV2667_HAPTICS is not set +# CONFIG_RMI4_CORE is not set # # Hardware I/O ports @@ -2371,8 +2387,6 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=8 CONFIG_SERIAL_8250_FSL=y CONFIG_SERIAL_8250_DW=y # CONFIG_SERIAL_8250_EM is not set -# CONFIG_SERIAL_8250_RT288X is not set -# CONFIG_SERIAL_8250_INGENIC is not set CONFIG_SERIAL_OF_PLATFORM=y # @@ -2397,6 +2411,7 @@ CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_SERIAL_CONEXANT_DIGICOLOR=m # CONFIG_SERIAL_ST_ASC is not set CONFIG_SERIAL_STM32=m +# CONFIG_SERIAL_MVEBU_UART is not set # CONFIG_TTY_PRINTK is not set # CONFIG_PRINTER is not set # CONFIG_PPDEV is not set @@ -2427,6 +2442,7 @@ CONFIG_I2C_MUX_PCA9541=m CONFIG_I2C_MUX_PCA954x=m CONFIG_I2C_MUX_PINCTRL=m CONFIG_I2C_MUX_REG=m +# CONFIG_I2C_DEMUX_PINCTRL is not set CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_ALGOBIT=m @@ -2480,9 +2496,11 @@ CONFIG_SPI_MASTER=y # SPI Master Controller Drivers # # CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set # CONFIG_SPI_BITBANG is not set # CONFIG_SPI_BUTTERFLY is not set # CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DESIGNWARE is not set # CONFIG_SPI_GPIO is not set # CONFIG_SPI_LM70_LLP is not set # CONFIG_SPI_FSL_SPI is not set @@ -2498,7 +2516,6 @@ CONFIG_SPI_SUN6I=y # CONFIG_SPI_XCOMM is not set # CONFIG_SPI_XILINX is not set # CONFIG_SPI_ZYNQMP_GQSPI is not set -# CONFIG_SPI_DESIGNWARE is not set # # SPI Protocol Masters @@ -2544,7 +2561,7 @@ CONFIG_GENERIC_PINCONF=y # CONFIG_PINCTRL_AMD is not set # CONFIG_PINCTRL_SINGLE is not set CONFIG_PINCTRL_SH_PFC=y -CONFIG_GPIO_SH_PFC=y +CONFIG_PINCTRL_SH_PFC_GPIO=y CONFIG_PINCTRL_PFC_EMEV2=y CONFIG_PINCTRL_PFC_R8A73A4=y CONFIG_PINCTRL_PFC_R8A7740=y @@ -2555,7 +2572,7 @@ CONFIG_PINCTRL_PFC_R8A7791=y CONFIG_PINCTRL_PFC_R8A7793=y CONFIG_PINCTRL_PFC_R8A7794=y CONFIG_PINCTRL_PFC_SH73A0=y -CONFIG_PINCTRL_SUNXI_COMMON=y +CONFIG_PINCTRL_SUNXI=y CONFIG_PINCTRL_SUN4I_A10=y CONFIG_PINCTRL_SUN5I_A10S=y CONFIG_PINCTRL_SUN5I_A13=y @@ -2568,6 +2585,7 @@ CONFIG_PINCTRL_SUN8I_A33=y CONFIG_PINCTRL_SUN8I_A83T=y CONFIG_PINCTRL_SUN8I_A23_R=y CONFIG_PINCTRL_SUN8I_H3=y +CONFIG_PINCTRL_SUN8I_H3_R=y CONFIG_PINCTRL_SUN9I_A80=y CONFIG_PINCTRL_SUN9I_A80_R=y CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y @@ -2589,6 +2607,7 @@ CONFIG_GPIO_ALTERA=m # CONFIG_GPIO_EM is not set # CONFIG_GPIO_GENERIC_PLATFORM is not set # CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_MPC8XXX is not set # CONFIG_GPIO_RCAR is not set CONFIG_GPIO_SYSCON=m # CONFIG_GPIO_XILINX is not set @@ -2605,6 +2624,7 @@ CONFIG_GPIO_SYSCON=m # CONFIG_GPIO_PCA953X is not set CONFIG_GPIO_PCF857X=m # CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_TPIC2810 is not set # # MFD GPIO expanders @@ -2617,6 +2637,7 @@ CONFIG_GPIO_PCF857X=m # CONFIG_GPIO_74X164 is not set # CONFIG_GPIO_MAX7301 is not set # CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set # # SPI or I2C GPIO expanders @@ -2665,8 +2686,6 @@ CONFIG_POWER_SUPPLY=y # CONFIG_BATTERY_SBS is not set # CONFIG_BATTERY_BQ27XXX is not set # CONFIG_BATTERY_DA9150 is not set -CONFIG_AXP288_CHARGER=m -CONFIG_AXP288_FUEL_GAUGE=m # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set # CONFIG_CHARGER_ISP1704 is not set @@ -2683,7 +2702,6 @@ CONFIG_AXP288_FUEL_GAUGE=m CONFIG_BATTERY_GAUGE_LTC2941=m CONFIG_BATTERY_RT5033=m # CONFIG_CHARGER_RT9455 is not set -CONFIG_AXP20X_POWER=y CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_BRCMSTB is not set # CONFIG_POWER_RESET_GPIO is not set @@ -2737,6 +2755,7 @@ CONFIG_SENSORS_JC42=m CONFIG_SENSORS_POWR1220=m CONFIG_SENSORS_LINEAGE=m CONFIG_SENSORS_LTC2945=m +# CONFIG_SENSORS_LTC2990 is not set CONFIG_SENSORS_LTC4151=m CONFIG_SENSORS_LTC4215=m CONFIG_SENSORS_LTC4222=m @@ -2855,9 +2874,7 @@ CONFIG_GPIO_WATCHDOG=m # CONFIG_CADENCE_WATCHDOG is not set # CONFIG_DW_WATCHDOG is not set CONFIG_SUNXI_WATCHDOG=y -# CONFIG_TS4800_WATCHDOG is not set # CONFIG_MAX63XX_WATCHDOG is not set -# CONFIG_BCM7038_WDT is not set # CONFIG_MEN_A21_WDT is not set # @@ -2892,6 +2909,7 @@ CONFIG_BCMA_BLOCKIO=y # Multifunction device drivers # CONFIG_MFD_CORE=y +# CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_AS3711 is not set # CONFIG_MFD_AS3722 is not set # CONFIG_PMIC_ADP5520 is not set @@ -2899,7 +2917,8 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_ATMEL_FLEXCOM is not set # CONFIG_MFD_ATMEL_HLCDC is not set # CONFIG_MFD_BCM590XX is not set -CONFIG_MFD_AXP20X=y +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_AXP20X_RSB is not set # CONFIG_MFD_CROS_EC is not set # CONFIG_MFD_ASIC3 is not set # CONFIG_PMIC_DA903X is not set @@ -2958,12 +2977,12 @@ CONFIG_MFD_SYSCON=y # CONFIG_TPS6105X is not set # CONFIG_TPS65010 is not set # CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set # CONFIG_MFD_TPS65090 is not set # CONFIG_MFD_TPS65217 is not set # CONFIG_MFD_TPS65218 is not set # CONFIG_MFD_TPS6586X is not set # CONFIG_MFD_TPS65910 is not set -# CONFIG_MFD_TPS65912 is not set # CONFIG_MFD_TPS65912_I2C is not set # CONFIG_MFD_TPS65912_SPI is not set # CONFIG_MFD_TPS80031 is not set @@ -2991,7 +3010,6 @@ CONFIG_REGULATOR_VIRTUAL_CONSUMER=y # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set CONFIG_REGULATOR_ANATOP=m -CONFIG_REGULATOR_AXP20X=y CONFIG_REGULATOR_DA9062=m # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set @@ -3488,6 +3506,7 @@ CONFIG_DVB_M88DS3103=m CONFIG_DVB_DRXK=m CONFIG_DVB_TDA18271C2DD=m CONFIG_DVB_SI2165=m +CONFIG_DVB_MN88473=m # # DVB-S (satellite) frontends @@ -3629,6 +3648,11 @@ CONFIG_DVB_DUMMY_FE=m # CONFIG_IMX_IPUV3_CORE is not set # CONFIG_DRM is not set +# +# ACP Configuration +# +# CONFIG_DRM_AMD_ACP is not set + # # Frame buffer Devices # @@ -3718,6 +3742,7 @@ CONFIG_SND_DMAENGINE_PCM=m CONFIG_SND_HWDEP=m CONFIG_SND_RAWMIDI=m CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y # CONFIG_SND_SEQUENCER is not set # CONFIG_SND_MIXER_OSS is not set # CONFIG_SND_PCM_OSS is not set @@ -3754,6 +3779,7 @@ CONFIG_SND_ARM=y CONFIG_SND_SPI=y CONFIG_SND_USB=y CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y CONFIG_SND_USB_UA101=m CONFIG_SND_USB_CAIAQ=m # CONFIG_SND_USB_CAIAQ_INPUT is not set @@ -3797,6 +3823,7 @@ CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y # Allwinner SoC Audio support # CONFIG_SND_SUN4I_CODEC=m +# CONFIG_SND_SUN4I_SPDIF is not set # CONFIG_SND_SOC_XTFPGA_I2S is not set CONFIG_SND_SOC_I2C_AND_SPI=m @@ -3826,11 +3853,13 @@ CONFIG_SND_SOC_I2C_AND_SPI=m # CONFIG_SND_SOC_GTM601 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_PCM1681 is not set -# CONFIG_SND_SOC_PCM179X is not set +# CONFIG_SND_SOC_PCM179X_I2C is not set +# CONFIG_SND_SOC_PCM179X_SPI is not set # CONFIG_SND_SOC_PCM3168A_I2C is not set # CONFIG_SND_SOC_PCM3168A_SPI is not set # CONFIG_SND_SOC_PCM512x_I2C is not set # CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_RT5677_SPI is not set # CONFIG_SND_SOC_SGTL5000 is not set @@ -3898,6 +3927,7 @@ CONFIG_HID_CHERRY=m CONFIG_HID_CHICONY=m CONFIG_HID_CORSAIR=m CONFIG_HID_PRODIKEYS=m +# CONFIG_HID_CMEDIA is not set CONFIG_HID_CP2112=m CONFIG_HID_CYPRESS=m CONFIG_HID_DRAGONRISE=m @@ -4325,6 +4355,7 @@ CONFIG_LEDS_REGULATOR=m # CONFIG_LEDS_TLC591XX is not set # CONFIG_LEDS_LM355x is not set # CONFIG_LEDS_KTD2692 is not set +# CONFIG_LEDS_IS31FL32XX is not set # # LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) @@ -4375,9 +4406,9 @@ CONFIG_RTC_INTF_DEV=y CONFIG_RTC_DRV_ABB5ZES3=m CONFIG_RTC_DRV_ABX80X=m CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_DS1307_HWMON=y # CONFIG_RTC_DRV_DS1374 is not set # CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_DS3232 is not set # CONFIG_RTC_DRV_HYM8563 is not set # CONFIG_RTC_DRV_MAX6900 is not set # CONFIG_RTC_DRV_RS5C372 is not set @@ -4385,10 +4416,9 @@ CONFIG_RTC_DRV_DS1307=m # CONFIG_RTC_DRV_ISL12022 is not set # CONFIG_RTC_DRV_ISL12057 is not set # CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF2127 is not set # CONFIG_RTC_DRV_PCF8523 is not set -# CONFIG_RTC_DRV_PCF8563 is not set # CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF8563 is not set # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set # CONFIG_RTC_DRV_BQ32K is not set @@ -4410,13 +4440,20 @@ CONFIG_RTC_DRV_DS1307=m # CONFIG_RTC_DRV_DS1343 is not set # CONFIG_RTC_DRV_DS1347 is not set # CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6902 is not set # CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_DS3234 is not set -# CONFIG_RTC_DRV_PCF2123 is not set # CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX6110 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set # CONFIG_RTC_DRV_MCP795 is not set +CONFIG_RTC_I2C_AND_SPI=y + +# +# SPI and I2C RTC drivers +# +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_PCF2127 is not set # # Platform RTC drivers @@ -4472,6 +4509,8 @@ CONFIG_DMA_SUN6I=y # CONFIG_FSL_EDMA is not set # CONFIG_INTEL_IDMA64 is not set # CONFIG_NBPFAXI_DMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set # CONFIG_DW_DMAC is not set CONFIG_RENESAS_DMA=y CONFIG_SH_DMAE_BASE=y @@ -4504,7 +4543,6 @@ CONFIG_UIO_DMEM_GENIRQ=m CONFIG_STAGING=y # CONFIG_PRISM2_USB is not set # CONFIG_COMEDI is not set -# CONFIG_PANEL is not set # CONFIG_RTLLIB is not set CONFIG_R8712U=m CONFIG_R8188EU=m @@ -4572,12 +4610,6 @@ CONFIG_88EU_AP_MODE=y # CONFIG_TSL2583 is not set # CONFIG_TSL2x7x is not set -# -# Magnetometer sensors -# -# CONFIG_SENSORS_HMC5843_I2C is not set -# CONFIG_SENSORS_HMC5843_SPI is not set - # # Active energy metering IC # @@ -4603,21 +4635,17 @@ CONFIG_88EU_AP_MODE=y # Speakup console speech # # CONFIG_SPEAKUP is not set -# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set CONFIG_STAGING_MEDIA=y CONFIG_I2C_BCM2048=m CONFIG_DVB_MN88472=m -CONFIG_DVB_MN88473=m # CONFIG_LIRC_STAGING is not set # # Android # # CONFIG_STAGING_BOARD is not set -# CONFIG_WIMAX_GDM72XX is not set # CONFIG_LTE_GDM724X is not set -# CONFIG_LUSTRE_FS is not set -# CONFIG_DGAP is not set +# CONFIG_LNET is not set # CONFIG_GS_FPGABOOT is not set # CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set CONFIG_FB_TFT=m @@ -4639,7 +4667,9 @@ CONFIG_FB_TFT_RA8875=m CONFIG_FB_TFT_S6D02A1=m CONFIG_FB_TFT_S6D1121=m CONFIG_FB_TFT_SSD1289=m +# CONFIG_FB_TFT_SSD1305 is not set CONFIG_FB_TFT_SSD1306=m +# CONFIG_FB_TFT_SSD1325 is not set CONFIG_FB_TFT_SSD1331=m CONFIG_FB_TFT_SSD1351=m CONFIG_FB_TFT_ST7735R=m @@ -4663,6 +4693,7 @@ CONFIG_AIM_V4L2=m CONFIG_HDM_DIM2=m CONFIG_HDM_I2C=m CONFIG_HDM_USB=m +# CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y @@ -4674,13 +4705,13 @@ CONFIG_COMMON_CLK=y # CONFIG_COMMON_CLK_SI5351 is not set # CONFIG_COMMON_CLK_SI514 is not set # CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set CONFIG_CLK_QORIQ=y # CONFIG_COMMON_CLK_NXP is not set CONFIG_COMMON_CLK_PWM=m # CONFIG_COMMON_CLK_PXA is not set -# CONFIG_COMMON_CLK_CDCE706 is not set # # Hardware Spinlock drivers @@ -4717,6 +4748,7 @@ CONFIG_IOMMU_SUPPORT=y CONFIG_IOMMU_IO_PGTABLE=y CONFIG_IOMMU_IO_PGTABLE_LPAE=y # CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set CONFIG_OF_IOMMU=y CONFIG_ARM_SMMU=y @@ -4755,7 +4787,6 @@ CONFIG_EXTCON=y # Extcon Device Drivers # # CONFIG_EXTCON_ADC_JACK is not set -CONFIG_EXTCON_AXP288=y CONFIG_EXTCON_GPIO=m # CONFIG_EXTCON_MAX3355 is not set CONFIG_EXTCON_RT8973A=m @@ -4798,7 +4829,6 @@ CONFIG_IIO=m # CONFIG_AD7887 is not set # CONFIG_AD7923 is not set # CONFIG_AD799X is not set -CONFIG_AXP288_ADC=m # CONFIG_CC10001_ADC is not set # CONFIG_DA9150_GPADC is not set # CONFIG_HI8435 is not set @@ -4809,7 +4839,9 @@ CONFIG_AXP288_ADC=m # CONFIG_MCP3422 is not set # CONFIG_NAU7802 is not set # CONFIG_TI_ADC081C is not set +# CONFIG_TI_ADC0832 is not set # CONFIG_TI_ADC128S052 is not set +# CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS8688 is not set # CONFIG_VF610_ADC is not set @@ -4821,6 +4853,7 @@ CONFIG_AXP288_ADC=m # # Chemical Sensors # +# CONFIG_ATLAS_PH_SENSOR is not set # CONFIG_IAQCORE is not set # CONFIG_VZ89X is not set @@ -4847,6 +4880,7 @@ CONFIG_AXP288_ADC=m # CONFIG_AD5624R_SPI is not set # CONFIG_AD5686 is not set # CONFIG_AD5755 is not set +# CONFIG_AD5761 is not set # CONFIG_AD5764 is not set # CONFIG_AD5791 is not set # CONFIG_AD7303 is not set @@ -4855,6 +4889,7 @@ CONFIG_AXP288_ADC=m # CONFIG_MAX5821 is not set # CONFIG_MCP4725 is not set # CONFIG_MCP4922 is not set +# CONFIG_VF610_DAC is not set # # IIO dummy driver @@ -4889,8 +4924,14 @@ CONFIG_AXP288_ADC=m # CONFIG_ITG3200 is not set # -# Health sensors +# Health Sensors # + +# +# Heart Rate Monitors +# +# CONFIG_AFE4403 is not set +# CONFIG_AFE4404 is not set # CONFIG_MAX30100 is not set # @@ -4908,7 +4949,8 @@ CONFIG_AXP288_ADC=m # CONFIG_ADIS16400 is not set # CONFIG_ADIS16480 is not set # CONFIG_KMX61 is not set -# CONFIG_INV_MPU6050_IIO is not set +# CONFIG_INV_MPU6050_I2C is not set +# CONFIG_INV_MPU6050_SPI is not set # # Light sensors @@ -4949,6 +4991,8 @@ CONFIG_AXP288_ADC=m # CONFIG_HID_SENSOR_MAGNETOMETER_3D is not set # CONFIG_MMC35240 is not set # CONFIG_IIO_ST_MAGN_3AXIS is not set +# CONFIG_SENSORS_HMC5843_I2C is not set +# CONFIG_SENSORS_HMC5843_SPI is not set # # Inclinometer sensors @@ -4960,13 +5004,15 @@ CONFIG_AXP288_ADC=m # Digital potentiometers # # CONFIG_MCP4531 is not set +# CONFIG_TPL0102 is not set # # Pressure sensors # # CONFIG_BMP280 is not set # CONFIG_HID_SENSOR_PRESS is not set -# CONFIG_MPL115 is not set +# CONFIG_MPL115_I2C is not set +# CONFIG_MPL115_SPI is not set # CONFIG_MPL3115 is not set # CONFIG_MS5611 is not set # CONFIG_MS5637 is not set @@ -5003,7 +5049,7 @@ CONFIG_ARM_GIC=y CONFIG_ARM_GIC_MAX_NR=1 CONFIG_RENESAS_INTC_IRQPIN=y CONFIG_RENESAS_IRQC=y -# CONFIG_TS4800_IRQ is not set +CONFIG_TANGO_IRQ=y # CONFIG_IPACK_BUS is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y @@ -5038,7 +5084,8 @@ CONFIG_NVMEM=m CONFIG_NVMEM_SUNXI_SID=m CONFIG_STM=m CONFIG_STM_DUMMY=m -CONFIG_STM_SOURCE_CONSOLE=y +CONFIG_STM_SOURCE_CONSOLE=m +# CONFIG_STM_SOURCE_HEARTBEAT is not set # CONFIG_INTEL_TH is not set # @@ -5104,6 +5151,7 @@ CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y CONFIG_FILE_LOCKING=y CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y @@ -5143,6 +5191,7 @@ CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set CONFIG_NTFS_FS=m # CONFIG_NTFS_DEBUG is not set CONFIG_NTFS_RW=y @@ -5162,6 +5211,7 @@ CONFIG_TMPFS_XATTR=y # CONFIG_HUGETLB_PAGE is not set CONFIG_CONFIGFS_FS=m CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_ECRYPT_FS is not set @@ -5220,7 +5270,8 @@ CONFIG_NFSD_V2_ACL=y CONFIG_NFSD_V3=y CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y -# CONFIG_NFSD_PNFS is not set +# CONFIG_NFSD_BLOCKLAYOUT is not set +# CONFIG_NFSD_SCSILAYOUT is not set # CONFIG_NFSD_FAULT_INJECTION is not set CONFIG_GRACE_PERIOD=y CONFIG_LOCKD=y @@ -5340,6 +5391,7 @@ CONFIG_DEBUG_KERNEL=y # # CONFIG_PAGE_EXTENSION is not set # CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_PAGE_POISONING is not set # CONFIG_DEBUG_OBJECTS is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set @@ -5402,6 +5454,7 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=21 # CONFIG_RCU_EQS_DEBUG is not set # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set # CONFIG_NOTIFIER_ERROR_INJECTION is not set # CONFIG_FAULT_INJECTION is not set CONFIG_LATENCYTOP=y @@ -5429,6 +5482,7 @@ CONFIG_TEST_HEXDUMP=m # CONFIG_TEST_STRING_HELPERS is not set # CONFIG_TEST_KSTRTOX is not set # CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set # CONFIG_TEST_RHASHTABLE is not set # CONFIG_DMA_API_DEBUG is not set # CONFIG_TEST_LKM is not set @@ -5509,8 +5563,6 @@ CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_PCOMP=m -CONFIG_CRYPTO_PCOMP2=y CONFIG_CRYPTO_AKCIPHER2=y CONFIG_CRYPTO_AKCIPHER=m CONFIG_CRYPTO_RSA=m @@ -5562,7 +5614,7 @@ CONFIG_CRYPTO_VMAC=m # Digest # CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRC32=m +CONFIG_CRYPTO_CRC32=y CONFIG_CRYPTO_CRCT10DIF=m CONFIG_CRYPTO_GHASH=m CONFIG_CRYPTO_POLY1305=m @@ -5606,7 +5658,6 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # Compression # CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_ZLIB=m CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_842=m CONFIG_CRYPTO_LZ4=m @@ -5632,7 +5683,6 @@ CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_DEV_SUN4I_SS=m CONFIG_ASYMMETRIC_KEY_TYPE=m CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=m -CONFIG_PUBLIC_KEY_ALGO_RSA=m CONFIG_X509_CERTIFICATE_PARSER=m CONFIG_PKCS7_MESSAGE_PARSER=m CONFIG_PKCS7_TEST_KEY=m @@ -5642,6 +5692,7 @@ CONFIG_PKCS7_TEST_KEY=m # CONFIG_SYSTEM_TRUSTED_KEYRING=y CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set CONFIG_ARM_CRYPTO=y CONFIG_CRYPTO_SHA1_ARM=m CONFIG_CRYPTO_SHA1_ARM_NEON=m diff --git a/configuration.sh b/configuration.sh index 22706ae80..7ae244ccb 100644 --- a/configuration.sh +++ b/configuration.sh @@ -265,7 +265,7 @@ case $BOARD in CPUMAX="1200000" GOVERNOR="interactive" CLI_TARGET="%,%" - DESKTOP_TARGET="jessie,default" + DESKTOP_TARGET="jessie,default" ;; cubox-i)#enabled @@ -397,25 +397,28 @@ case $LINUXFAMILY in [[ -z $LINUXCONFIG && $BRANCH == "default" ]] && LINUXCONFIG="linux-"$LINUXFAMILY-"$BRANCH" [[ -z $LINUXCONFIG && $BRANCH != "default" ]] && LINUXCONFIG="linux-sunxi-"$BRANCH # Kernel - KERNEL_DEFAULT='https://github.com/linux-sunxi/linux-sunxi' - KERNEL_DEFAULT_BRANCH="sunxi-3.4" - KERNEL_DEFAULT_SOURCE="linux-sunxi" - # sun8i legacy + # sun8i switches if [[ $LINUXFAMILY == sun8i ]]; then - # KERNEL_DEFAULT="https://github.com/ssvb/linux-sunxi" - # KERNEL_DEFAULT_BRANCH="20151207-embedded-lima-memtester-h3" KERNEL_DEFAULT="https://github.com/O-Computers/linux-sunxi" KERNEL_DEFAULT_BRANCH="h3-wip" KERNEL_DEFAULT_SOURCE="linux-sun8i" + KERNEL_DEV=https://github.com/wens/linux + KERNEL_DEV_BRANCH=h3-emac + KERNEL_DEV_SOURCE="linux-sun8i-mainline" + else + KERNEL_DEFAULT='https://github.com/linux-sunxi/linux-sunxi' + KERNEL_DEFAULT_BRANCH="sunxi-3.4" + KERNEL_DEFAULT_SOURCE="linux-sunxi" + KERNEL_DEV='git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git' + [ "$USE_MAINLINE_GOOGLE_MIRROR" = "yes" ] && KERNEL_DEV='https://kernel.googlesource.com/pub/scm/linux/kernel/git/stable/linux-stable' + KERNEL_DEV_BRANCH="" + KERNEL_DEV_SOURCE="linux-vanilla" fi KERNEL_NEXT='git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git' [ "$USE_MAINLINE_GOOGLE_MIRROR" = "yes" ] && KERNEL_NEXT='https://kernel.googlesource.com/pub/scm/linux/kernel/git/stable/linux-stable' KERNEL_NEXT_BRANCH="v"`wget -qO- https://www.kernel.org/finger_banner | grep "The latest st" | awk '{print $NF}' | head -1` KERNEL_NEXT_SOURCE="linux-vanilla" - KERNEL_DEV='git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git' - [ "$USE_MAINLINE_GOOGLE_MIRROR" = "yes" ] && KERNEL_DEV='https://kernel.googlesource.com/pub/scm/linux/kernel/git/stable/linux-stable' - KERNEL_DEV_BRANCH="" - KERNEL_DEV_SOURCE="linux-vanilla" + # U-boot UBOOT_DEFAULT="git://git.denx.de/u-boot.git" UBOOT_DEFAULT_BRANCH="v"$(git ls-remote git://git.denx.de/u-boot.git | grep -v rc | grep -v "\^" | tail -1 | cut -d "v" -f 2) @@ -705,3 +708,4 @@ echo -e "Config: $LINUXCONFIG\nKernel source: $LINUXKERNEL\nBranch: $KERNELBRANC echo -e "linuxsource: $LINUXSOURCE\nOffset: $OFFSET\nbootsize: $BOOTSIZE" >> $DEST/debug/install.log echo -e "bootloader: $BOOTLOADER\nbootsource: $BOOTSOURCE\nbootbranch: $BOOTBRANCH" >> $DEST/debug/install.log echo -e "CPU $CPUMIN / $CPUMAX with $GOVERNOR" >> $DEST/debug/install.log + diff --git a/patch/kernel/sunxi-dev/0000-sun8i-h3.patch b/patch/kernel/sunxi-dev/0000-sun8i-h3.patch deleted file mode 100644 index add2f39bd..000000000 --- a/patch/kernel/sunxi-dev/0000-sun8i-h3.patch +++ /dev/null @@ -1,700 +0,0 @@ -diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi -index 1524130..58b5973 100644 ---- a/arch/arm/boot/dts/sun8i-h3.dtsi -+++ b/arch/arm/boot/dts/sun8i-h3.dtsi -@@ -51,29 +51,51 @@ - cpus { - #address-cells = <1>; - #size-cells = <0>; -+ enable-method = "allwinner,sun6i-a31"; - - cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; -+// enable-method = "psci"; - }; - - cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; -+// enable-method = "psci"; - }; - - cpu@2 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <2>; -+// enable-method = "psci"; - }; - - cpu@3 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <3>; -+// enable-method = "psci"; -+ }; -+ }; -+ -+//from A64 -+// psci { -+// compatible = "arm,psci-0.2", "arm,psci"; -+// method = "smc"; -+//// cpu_suspend = <0xc4000001>; -+//// cpu_off = <0x84000002>; -+//// cpu_on = <0xc4000003>; -+// }; -+ -+ thermal-zones { -+ cpu_thermal: cpu_thermal { -+ polling-delay-passive = <1000>; -+ polling-delay = <5000>; -+ thermal-sensors = <&ths 0>; - }; - }; - -@@ -83,6 +105,9 @@ - , - , - ; -+// from hdg and jens -+ clock-frequency = <24000000>; -+ arm,cpu-registers-not-fw-configured; - }; - - clocks { -@@ -104,7 +129,7 @@ - clock-output-names = "osc32k"; - }; - -- pll1: clk@01c20000 { -+ pll1: clk@01c20000 { /* PLL CPUX */ - #clock-cells = <0>; - compatible = "allwinner,sun8i-a23-pll1-clk"; - reg = <0x01c20000 0x4>; -@@ -112,6 +137,22 @@ - clock-output-names = "pll1"; - }; - -+ pll2: clk@01c20008 { /* PLL_AUDIO */ -+ #clock-cells = <1>; -+ compatible = "allwinner,sun8i-h3-pll2-clk"; -+ reg = <0x01c20008 0x4>; -+ clocks = <&osc24M>; -+ clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8"; -+ }; -+ -+ pll3: clk@01c20010 { /* PLL_VIDEO */ -+ #clock-cells = <0>; -+ compatible = "allwinner,sun6i-pll3-clk"; -+ reg = <0x01c20010 0x4>; -+ clocks = <&osc24M>; -+ clock-output-names = "pll3"; -+ }; -+ - /* dummy clock until actually implemented */ - pll5: pll5_clk { - #clock-cells = <0>; -@@ -120,29 +161,63 @@ - clock-output-names = "pll5"; - }; - -- pll6: clk@01c20028 { -- #clock-cells = <1>; -- compatible = "allwinner,sun6i-a31-pll6-clk"; -+ pll6x2: clk@01c20028 { -+ #clock-cells = <0>; -+ compatible = "allwinner,pll-periphx2-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; -- clock-output-names = "pll6", "pll6x2"; -+ clock-output-names = "pll6x2"; - }; -- -- pll6d2: pll6d2_clk { -+ pll6: pll6_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <2>; - clock-mult = <1>; -- clocks = <&pll6 0>; -+ clocks = <&pll6x2>; -+ clock-output-names = "pll6"; -+ assigned-clocks = <&pll6x2>; -+ assigned-clock-rates = <1200000000>; -+ }; -+ pll6d2: pll6d2_clk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clock-div = <4>; -+ clock-mult = <1>; -+ clocks = <&pll6x2>; - clock-output-names = "pll6d2"; - }; - -- /* dummy clock until pll6 can be reused */ -+ pll8x2: clk@01c20044 { /* PLL_PERIPH1 */ -+ #clock-cells = <0>; -+ compatible = "allwinner,pll-periphx2-clk"; -+ reg = <0x01c20044 0x4>; -+ clocks = <&osc24M>; -+ clock-output-names = "pll8x2"; -+ }; - pll8: pll8_clk { - #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clock-div = <2>; -+ clock-mult = <1>; -+ clocks = <&pll8x2>; -+ clock-output-names = "pll8"; -+ assigned-clocks = <&pll8x2>; -+ assigned-clock-rates = <1200000000>; -+ }; -+ -+ pll10: clk@01c20048 { /* PLL_DE */ -+ #clock-cells = <0>; -+ compatible = "allwinner,sun6i-pll3-clk"; -+ reg = <0x01c20048 0x4>; -+ clocks = <&osc24M>; -+ clock-output-names = "pll10"; -+ }; -+ -+ dum: dum_clk { /* (don't use) */ -+ #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1>; -- clock-output-names = "pll8"; -+ clock-output-names = "dum"; - }; - - cpu: cpu_clk@01c20050 { -@@ -165,8 +240,10 @@ - #clock-cells = <0>; - compatible = "allwinner,sun6i-a31-ahb1-clk"; - reg = <0x01c20054 0x4>; -- clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; -+ clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>; - clock-output-names = "ahb1"; -+ assigned-clocks = <&ahb1>; -+ assigned-clock-parents = <&pll6>; - }; - - ahb2: ahb2_clk@01c2005c { -@@ -175,6 +252,8 @@ - reg = <0x01c2005c 0x4>; - clocks = <&ahb1>, <&pll6d2>; - clock-output-names = "ahb2"; -+ assigned-clocks = <&ahb2>; -+ assigned-clock-parents = <&ahb1>; - }; - - apb1: apb1_clk@01c20054 { -@@ -189,8 +268,11 @@ - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; -- clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; -+ clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; - clock-output-names = "apb2"; -+//fixme: does not work -+// assigned-clocks = <&apb2>; -+// assigned-clock-parents = <&osc24M>; - }; - - bus_gates: clk@01c20060 { -@@ -239,41 +321,126 @@ - "bus_scr", "bus_ephy", "bus_dbg"; - }; - -+ ths_clk: clk@01c20074 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun8i-h3-ths-clk"; -+ reg = <0x01c20074 0x4>; -+ clocks = <&osc24M>; -+ clock-output-names = "ths"; -+ }; -+ - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; -- clocks = <&osc24M>, <&pll6 0>, <&pll8>; -+ clocks = <&osc24M>, <&pll6>, <&pll8>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; -+//fixme: does not work -+// assigned-clocks = <&mmc0_clk>; -+// assigned-clock-parents = <&pll8>; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; -- clocks = <&osc24M>, <&pll6 0>, <&pll8>; -+ clocks = <&osc24M>, <&pll6>, <&pll8>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; -+//fixme: does not work -+// assigned-clocks = <&mmc1_clk>; -+// assigned-clock-parents = <&pll8>; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; -- clocks = <&osc24M>, <&pll6 0>, <&pll8>; -+//fixme: test pll8 - pll8 problem... -+ clocks = <&osc24M>, <&pll6>, <&pll8>; -+// clocks = <&dum>, <&dum>, <&pll8>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; -+//fixme: does not work -+// assigned-clocks = <&mmc2_clk>; -+// assigned-clock-parents = <&pll8>; -+ }; -+ -+ i2s2_clk: clk@01c200b8 { /* I2S/PCM 2 (HDMI) */ -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-a10-mod1-clk"; -+ reg = <0x01c200b8 0x4>; -+//fixme: to check again... -+// clocks = <&pll2 3>, <&pll2 2>, <&pll2 1>, <&pll2 0>; -+ clocks = <&dum>, <&dum>, <&dum>, <&pll2 0>; -+ clock-output-names = "i2s2"; -+//fixme: test -+// assigned-clocks = <&pll2 0>; -+// assigned-clock-rates = <24576000>; -+ }; -+ -+ usb_clk: clk@01c200cc { -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ compatible = "allwinner,sun8i-h3-usb-clk"; -+ reg = <0x01c200cc 0x4>; -+ clocks = <&osc24M>; -+ clock-output-names = "usb_phy0", "usb_phy1", -+ "usb_phy2", "usb_phy3", -+ "usb_ohci0", "usb_ohci1", -+ "usb_ohci2", "usb_ohci3"; -+ }; -+ -+ de_clk: clk@01c20104 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun6i-display-clk"; -+ reg = <0x01c20104 0x4>; -+//change with assigned-clocks -+ clocks = <&pll6x2>, <&pll10>; /* PERIPH0 x2, DE */ -+// clocks = <&dum>, <&pll10>; /* force PLL DE only */ -+ clock-output-names = "de"; -+ assigned-clocks = <&de_clk>; -+ assigned-clock-parents = <&pll10>; -+ }; -+ -+ tcon0_clk: clk@1c20118 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun6i-display-clk"; -+ reg = <0x01c20118 0x4>; -+ clocks = <&pll3>; -+ clock-output-names = "tcon0"; -+ }; -+// tve_clk: clk@01c20120 { -+// #clock-cells = <0>; -+// compatible = "allwinner,sun6i-display-clk"; -+// reg = <0x01c20120 0x4>; -+// clocks = <&pll10>, <&pll8>; /* DE, PERIPH1 */ -+// clock-output-names = "tve"; -+// }; -+ hdmi_clk: clk@01c20150 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun6i-display-clk"; -+ reg = <0x01c20150 0x4>; -+ clocks = <&pll3>; -+ clock-output-names = "hdmi"; -+ }; -+ hdmi_slow_clk: clk@01c20154 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-a10-codec-clk"; -+ reg = <0x01c20154 0x4>; -+ clocks = <&osc24M>; -+ clock-output-names = "hdmi-slow"; - }; - - mbus_clk: clk@01c2015c { - #clock-cells = <0>; - compatible = "allwinner,sun8i-a23-mbus-clk"; - reg = <0x01c2015c 0x4>; -- clocks = <&osc24M>, <&pll6 1>, <&pll5>; -+ clocks = <&osc24M>, <&pll6x2>, <&pll5>; - clock-output-names = "mbus"; - }; - }; -@@ -284,6 +451,18 @@ - #size-cells = <1>; - ranges; - -+ de: de-controller@01000000 { -+ compatible = "allwinner,sun8i-h3-display-engine"; -+ reg = <0x01000000 0x400000>; -+ clocks = <&bus_gates 44>, <&de_clk>; -+ clock-names = "gate", "clock"; -+ resets = <&ahb_rst 44>; -+//fixme: tv to be added -+// ports = <&lcd0_p>, <&lcd1_p>; -+ ports = <&lcd0_p>; -+ status = "disabled"; -+ }; -+ - dma: dma-controller@01c02000 { - compatible = "allwinner,sun8i-h3-dma"; - reg = <0x01c02000 0x1000>; -@@ -293,6 +472,42 @@ - #dma-cells = <1>; - }; - -+ lcd0: lcd-controller@01c0c000 { -+ compatible = "allwinner,sun8i-h3-lcd"; -+// reg = <0x01c0c000 0x1000>; -+ reg = <0x01c0c000 0x400>; -+ clocks = <&bus_gates 35>, <&tcon0_clk>; -+ clock-names = "gate", "clock"; -+ resets = <&ahb_rst 35>; -+ interrupts = ; -+ status = "disabled"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ lcd0_p: port { -+ lcd0_ep: endpoint { -+ remote-endpoint = <&hdmi_ep>; -+ }; -+ }; -+ }; -+ -+// lcd1: lcd-controller@01c0d000 { -+// compatible = "allwinner,sun8i-h3-lcd"; -+//// reg = <0x01c0d000 0x1000>; -+// reg = <0x01c0d000 0x400>; -+// clocks = <&bus_gates 36>, <&??>; -+// clock-names = "gate", "clock"; -+// resets = <&ahb_rst 36>; -+// interrupts = ; -+// status = "disabled"; -+// #address-cells = <1>; -+// #size-cells = <0>; -+// lcd1_p: port { -+// lcd1_ep: endpoint { -+// remote-endpoint = <&tve_ep>; -+// }; -+// }; -+// }; -+ - mmc0: mmc@01c0f000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c0f000 0x1000>; -@@ -308,8 +523,8 @@ - reset-names = "ahb"; - interrupts = ; - status = "disabled"; -- #address-cells = <1>; -- #size-cells = <0>; -+// #address-cells = <1>; -+// #size-cells = <0>; - }; - - mmc1: mmc@01c10000 { -@@ -327,8 +542,8 @@ - reset-names = "ahb"; - interrupts = ; - status = "disabled"; -- #address-cells = <1>; -- #size-cells = <0>; -+// #address-cells = <1>; -+// #size-cells = <0>; - }; - - mmc2: mmc@01c11000 { -@@ -346,8 +561,136 @@ - reset-names = "ahb"; - interrupts = ; - status = "disabled"; -+// #address-cells = <1>; -+// #size-cells = <0>; -+ }; -+ -+ sid: eeprom@01c14000 { -+ compatible = "allwinner,sun4i-a10-sid"; -+ reg = <0x01c14000 0x400>; - #address-cells = <1>; -- #size-cells = <0>; -+ #size-cells = <1>; -+ -+ ths_calibration: calib@234 { -+ reg = <0x234 0x4>; -+ }; -+ }; -+ -+//fixme: to see later -+//?? otg not described -+// usb_otg: usb@01c19000 { -+// compatible = "allwinner,sun8i-a33-musb"; -+// reg = <0x01c19000 0x0458>; -+// clocks = <&bus_gates 23>; -+// resets = <&ahb_rst 23>; -+////?? -+// interrupts = ; -+// interrupt-names = "mc"; -+// phys = <&usbphy 0>; -+// phy-names = "usb"; -+// extcon = <&usbphy 0>; -+// status = "disabled"; -+// }; -+// -+ usbphy: phy@01c19400 { -+ compatible = "allwinner,sun8i-h3-usb-phy"; -+ reg = <0x01c19400 0x2c>, -+ <0x01c1a800 0x4>, -+ <0x01c1b800 0x4>, -+ <0x01c1c800 0x4>, -+ <0x01c1d800 0x4>; -+ reg-names = "phy_ctrl", -+ "pmu0", -+ "pmu1", -+ "pmu2", -+ "pmu3"; -+ clocks = <&usb_clk 8>, -+ <&usb_clk 9>, -+ <&usb_clk 10>, -+ <&usb_clk 11>; -+ clock-names = "usb0_phy", -+ "usb1_phy", -+ "usb2_phy", -+ "usb3_phy"; -+ resets = <&usb_clk 0>, -+ <&usb_clk 1>, -+ <&usb_clk 2>, -+ <&usb_clk 3>; -+ reset-names = "usb0_reset", -+ "usb1_reset", -+ "usb2_reset", -+ "usb3_reset"; -+ status = "disabled"; -+ #phy-cells = <1>; -+ }; -+ -+ ehci1: usb@01c1b000 { -+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; -+ reg = <0x01c1b000 0x100>; -+ interrupts = ; -+ clocks = <&bus_gates 25>, <&bus_gates 29>; -+ resets = <&ahb_rst 25>, <&ahb_rst 29>; -+ phys = <&usbphy 1>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ohci1: usb@01c1b400 { -+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; -+ reg = <0x01c1b400 0x100>; -+ interrupts = ; -+ clocks = <&bus_gates 29>, <&bus_gates 25>, -+ <&usb_clk 17>; -+ resets = <&ahb_rst 29>, <&ahb_rst 25>; -+ phys = <&usbphy 1>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ehci2: usb@01c1c000 { -+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; -+ reg = <0x01c1c000 0x100>; -+ interrupts = ; -+ clocks = <&bus_gates 26>, <&bus_gates 30>; -+ resets = <&ahb_rst 26>, <&ahb_rst 30>; -+ phys = <&usbphy 2>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ohci2: usb@01c1c400 { -+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; -+ reg = <0x01c1c400 0x100>; -+ interrupts = ; -+ clocks = <&bus_gates 30>, <&bus_gates 26>, -+ <&usb_clk 18>; -+ resets = <&ahb_rst 30>, <&ahb_rst 26>; -+ phys = <&usbphy 2>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ehci3: usb@01c1d000 { -+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; -+ reg = <0x01c1d000 0x100>; -+ interrupts = ; -+ clocks = <&bus_gates 27>, <&bus_gates 31>; -+ resets = <&ahb_rst 27>, <&ahb_rst 31>; -+ phys = <&usbphy 3>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ohci3: usb@01c1d400 { -+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; -+ reg = <0x01c1d400 0x100>; -+ interrupts = ; -+ clocks = <&bus_gates 31>, <&bus_gates 27>, -+ <&usb_clk 19>; -+ resets = <&ahb_rst 31>, <&ahb_rst 27>; -+ phys = <&usbphy 3>; -+ phy-names = "usb"; -+ status = "disabled"; - }; - - pio: pinctrl@01c20800 { -@@ -359,7 +702,7 @@ - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; -- #interrupt-cells = <2>; -+ #interrupt-cells = <3>; - - uart0_pins_a: uart0@0 { - allwinner,pins = "PA4", "PA5"; -@@ -424,6 +767,29 @@ - interrupts = ; - }; - -+ i2s2: i2s@1c22800 { -+ compatible = "allwinner,sun8i-h3-hdmi-audio"; -+ reg = <0x01c22800 0x60>; -+ resets = <&apb1_rst 14>; -+ clocks = <&bus_gates 78>, <&pll2 0>, <&i2s2_clk>; -+ clock-names = "gate", "clock", "i2s2"; -+ dmas = <&dma 27>; -+ dma-names = "tx"; -+ status = "disabled"; -+ }; -+ -+ ths: ths@01c25000 { -+ #thermal-sensor-cells = <0>; -+ compatible = "allwinner,sun8i-h3-ths"; -+ reg = <0x01c25000 0x88>; -+ interrupts = ; -+ resets = <&apb1_rst 8>; -+ clocks = <&bus_gates 72>, <&ths_clk>; -+ clock-names = "ahb", "ths"; -+ nvmem-cells = <&ths_calibration>; -+ nvmem-cell-names = "calibration"; -+ }; -+ - uart0: serial@01c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; -@@ -487,11 +853,101 @@ - interrupts = ; - }; - -+// tve { -+// compatible = "allwinner,sun8i-h3-tve"; -+// reg = <0x01e00000 0x10000>; -+// clocks = <&bus_gates 41>, <&tve_clk>; -+// clock-names = "gate", "clock"; -+// resets = <&ahb_rst 41> -+// status = "disabled"; -+// #address-cells = <1>; -+// #size-cells = <0>; -+// port { -+// tve_ep: endpoint { -+// remote-endpoint = <&lcd1_ep>; -+// }; -+// }; -+// }; -+ -+ hdmi: hdmi@01ee0000 { -+ compatible = "allwinner,sun8i-h3-hdmi"; -+ reg = <0x01ee0000 0x20000>; -+//fixme: hack - see hdmi_slow_clk -+ clocks = <&bus_gates 43>, <&hdmi_clk>, -+ <&hdmi_slow_clk 31>; -+ clock-names = "gate", "clock", "ddc-clock"; -+ resets = <&ahb_rst 42>, <&ahb_rst 43>; -+ reset-names = "hdmi0", "hdmi1"; -+ status = "disabled"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ port { -+ hdmi_ep: endpoint { -+ remote-endpoint = <&lcd0_ep>; -+ }; -+ }; -+ }; -+ - rtc: rtc@01f00000 { - compatible = "allwinner,sun6i-a31-rtc"; - reg = <0x01f00000 0x54>; - interrupts = , - ; - }; -+ -+ prcm@01f01400 { -+ compatible = "allwinner,sun6i-a31-prcm"; -+ reg = <0x01f01400 0x200>; -+ -+ ar100: ar100_clk { -+ compatible = "allwinner,sun6i-a31-ar100-clk"; -+ #clock-cells = <0>; -+ clocks = <&osc32k>, <&osc24M>, <&pll6>, -+ <&pll6>; -+ clock-output-names = "ar100"; -+ }; -+ ahb0: ahb0_clk { -+ compatible = "fixed-factor-clock"; -+ #clock-cells = <0>; -+ clock-div = <1>; -+ clock-mult = <1>; -+ clocks = <&ar100>; -+ clock-output-names = "ahb0"; -+ }; -+ -+ apb0: apb0_clk { -+ compatible = "allwinner,sun6i-a31-apb0-clk"; -+ #clock-cells = <0>; -+ clocks = <&ahb0>; -+ clock-output-names = "apb0"; -+ }; -+ -+ apb0_gates: apb0_gates_clk { -+ compatible = "allwinner,sun6i-a31-apb0-gates-clk"; -+ #clock-cells = <1>; -+ clocks = <&apb0>; -+ clock-output-names = "apb0_pio", "apb0_ir", -+ "apb0_timer", "apb0_p2wi", -+ "apb0_uart", "apb0_1wire", -+ "apb0_i2c"; -+ }; -+ -+// ir_clk: ir_clk { -+// #clock-cells = <0>; -+// compatible = "allwinner,sun4i-a10-mod0-clk"; -+// clocks = <&osc32k>, <&osc24M>; -+// clock-output-names = "ir"; -+// }; -+ -+ apb0_rst: apb0_rst { -+ compatible = "allwinner,sun6i-a31-clock-reset"; -+ #reset-cells = <1>; -+ }; -+ }; -+ -+ cpucfg@01f01c00 { -+ compatible = "allwinner,sun6i-a31-cpuconfig"; -+ reg = <0x01f01c00 0x300>; -+ }; - }; - }; - diff --git a/patch/kernel/sunxi-dev/0001-ARM-dts-sun8i-add-sun8i-emac-ethernet-driver.patch b/patch/kernel/sunxi-dev/0001-ARM-dts-sun8i-add-sun8i-emac-ethernet-driver.patch deleted file mode 100644 index 3d7b2bfff..000000000 --- a/patch/kernel/sunxi-dev/0001-ARM-dts-sun8i-add-sun8i-emac-ethernet-driver.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 3f82b8ac8519fae6e034140dcdb421ac9b2b1868 Mon Sep 17 00:00:00 2001 -From: LABBE Corentin -Date: Thu, 25 Feb 2016 14:43:41 +0100 -Subject: [PATCH 1/5] ARM: dts: sun8i: add sun8i-emac ethernet driver - -The sun8i-emac is an ethernet MAC hardware that support 10/100/1000 -speed. TODO - -This patch enable the sun8i-emac on the Allwinner H3 SoC Device-tree. - -Signed-off-by: LABBE Corentin ---- - arch/arm/boot/dts/sun8i-h3.dtsi | 23 +++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - -diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi -index 1524130e..7f119fc 100644 ---- a/arch/arm/boot/dts/sun8i-h3.dtsi -+++ b/arch/arm/boot/dts/sun8i-h3.dtsi -@@ -361,6 +361,17 @@ - interrupt-controller; - #interrupt-cells = <2>; - -+ emac_pins_a: emac0@0 { -+ allwinner,pins = "PD0", "PD1", "PD2", "PD3", -+ "PD4", "PD5", "PD6", "PD7", -+ "PD8", "PD9", "PD10", "PD11", -+ "PD12", "PD13", "PD14", "PD15", -+ "PD16", "PD17"; -+ allwinner,function = "emac"; -+ allwinner,drive = ; -+ allwinner,pull = ; -+ }; -+ - uart0_pins_a: uart0@0 { - allwinner,pins = "PA4", "PA5"; - allwinner,function = "uart0"; -@@ -476,6 +487,18 @@ - status = "disabled"; - }; - -+ emac: ethernet@1c30000 { -+ compatible = "allwinner,sun8i-h3-emac"; -+ reg = <0x01c30000 0x1054>; -+ interrupts = ; -+ resets = <&ahb_rst 17>, <&ahb_rst 66>; -+ reset-names = "ahb", "ephy"; -+ clocks = <&bus_gates 17>, <&bus_gates 128>; -+ clock-names = "bus_gmac", "bus_ephy"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ - gic: interrupt-controller@01c81000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; - reg = <0x01c81000 0x1000>, --- -2.4.10 - diff --git a/patch/kernel/sunxi-dev/0002-ARM-dts-sun8i-Add-Orange-Pi-PC-support.patch b/patch/kernel/sunxi-dev/0002-ARM-dts-sun8i-Add-Orange-Pi-PC-support.patch deleted file mode 100644 index 87a001fa1..000000000 --- a/patch/kernel/sunxi-dev/0002-ARM-dts-sun8i-Add-Orange-Pi-PC-support.patch +++ /dev/null @@ -1,146 +0,0 @@ -From cd9ca31e5522be5de6b9e70f99f79f8a37fbe76f Mon Sep 17 00:00:00 2001 -From: Chen-Yu Tsai -Date: Wed, 18 Nov 2015 13:40:33 +0800 -Subject: [PATCH 2/5] ARM: dts: sun8i: Add Orange Pi PC support - -The Orange Pi PC is an SBC based on the Allwinner H3 SoC with a uSD slot, -3 USB ports directly from the SoC, a 10/100M ethernet port using the -SoC's integrated PHY, USB OTG, HDMI, a TRRS headphone jack for stereo out -and composite out, a microphone, an IR receiver, a CSI connector, 2 LEDs, -a 3 pin UART header, and a 40-pin GPIO header. - -Signed-off-by: Chen-Yu Tsai -Signed-off-by: LABBE Corentin ---- - arch/arm/boot/dts/Makefile | 1 + - arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 106 +++++++++++++++++++++++++++++ - 2 files changed, 107 insertions(+) - create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts - -diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile -index a4a6d70..717cfbd 100644 ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -691,6 +691,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ - sun8i-a33-ippo-q8h-v1.2.dtb \ - sun8i-a33-q8-tablet.dtb \ - sun8i-a33-sinlinx-sina33.dtb \ -+ sun8i-h3-orangepi-pc.dtb \ - sun8i-h3-orangepi-plus.dtb - dtb-$(CONFIG_MACH_SUN9I) += \ - sun9i-a80-optimus.dtb \ -diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts -new file mode 100644 -index 0000000..4b25dcc ---- /dev/null -+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts -@@ -0,0 +1,106 @@ -+/* -+ * Copyright (C) 2015 Chen-Yu Tsai -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This file is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+/dts-v1/; -+#include "sun8i-h3.dtsi" -+#include "sunxi-common-regulators.dtsi" -+ -+#include -+#include -+ -+/ { -+ model = "Xunlong Orange Pi PC"; -+ compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; -+ -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+}; -+ -+&ehci1 { -+ status = "okay"; -+}; -+ -+&ehci2 { -+ status = "okay"; -+}; -+ -+&ehci3 { -+ status = "okay"; -+}; -+ -+&mmc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; -+ vmmc-supply = <®_vcc3v3>; -+ bus-width = <4>; -+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ -+ cd-inverted; -+ status = "okay"; -+}; -+ -+&ohci1 { -+ status = "okay"; -+}; -+ -+&ohci2 { -+ status = "okay"; -+}; -+ -+&ohci3 { -+ status = "okay"; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins_a>; -+ status = "okay"; -+}; -+ -+&usbphy { -+ /* USB VBUS is always on */ -+ status = "okay"; -+}; --- -2.4.10 - diff --git a/patch/kernel/sunxi-dev/0003-ARM-dts-sun8i-Enable-sun8i-emac-on-the-Orange-PI-PC.patch b/patch/kernel/sunxi-dev/0003-ARM-dts-sun8i-Enable-sun8i-emac-on-the-Orange-PI-PC.patch deleted file mode 100644 index ad19d380e..000000000 --- a/patch/kernel/sunxi-dev/0003-ARM-dts-sun8i-Enable-sun8i-emac-on-the-Orange-PI-PC.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 7fd516f0fc8051d4d5e8118ec08754937918e02b Mon Sep 17 00:00:00 2001 -From: LABBE Corentin -Date: Wed, 27 Jan 2016 10:19:51 +0100 -Subject: [PATCH 3/5] ARM: dts: sun8i: Enable sun8i-emac on the Orange PI PC - -Enable the sun8i-emac harware present on the Orange PI PC. - -Signed-off-by: LABBE Corentin ---- - arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts -index 4b25dcc..300ab14 100644 ---- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts -+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts -@@ -104,3 +104,12 @@ - /* USB VBUS is always on */ - status = "okay"; - }; -+ -+&emac { -+ phy = <&phy1>; -+ phy-mode = "mii"; -+ status = "okay"; -+ phy1: ethernet-phy@1 { -+ reg = <0>; -+ }; -+}; --- -2.4.10 - diff --git a/patch/kernel/sunxi-dev/0005-ethernet-add-sun8i-emac-driver.patch b/patch/kernel/sunxi-dev/0005-ethernet-add-sun8i-emac-driver.patch deleted file mode 100644 index 896d809a9..000000000 --- a/patch/kernel/sunxi-dev/0005-ethernet-add-sun8i-emac-driver.patch +++ /dev/null @@ -1,1671 +0,0 @@ -From 1b1fa6d2064332ea73ef1f8da97d966ea1b23f99 Mon Sep 17 00:00:00 2001 -From: LABBE Corentin -Date: Thu, 14 Jan 2016 11:40:23 +0100 -Subject: [PATCH] ethernet: add sun8i-emac driver - -This patch add support for sun8i-emac ethernet MAC hardware. -It could be found in Allwinner H3/A83T/A64 SoCs. - -Signed-off-by: LABBE Corentin ---- - drivers/net/ethernet/allwinner/Kconfig | 13 + - drivers/net/ethernet/allwinner/Makefile | 1 + - drivers/net/ethernet/allwinner/sun8i-emac.c | 1615 +++++++++++++++++++++++++++ - 3 files changed, 1629 insertions(+) - create mode 100644 drivers/net/ethernet/allwinner/sun8i-emac.c - -diff --git a/drivers/net/ethernet/allwinner/Kconfig b/drivers/net/ethernet/allwinner/Kconfig -index 47da7e7..31ed97e 100644 ---- a/drivers/net/ethernet/allwinner/Kconfig -+++ b/drivers/net/ethernet/allwinner/Kconfig -@@ -33,4 +33,17 @@ config SUN4I_EMAC - To compile this driver as a module, choose M here. The module - will be called sun4i-emac. - -+config SUN8I_EMAC -+ tristate "Allwinner H3 EMAC support" -+ depends on ARCH_SUNXI -+ depends on OF -+ select CRC32 -+ select MII -+ select PHYLIB -+ ---help--- -+ Support for Allwinner H3 EMAC ethernet driver. -+ -+ To compile this driver as a module, choose M here. The module -+ will be called sun8i-emac. -+ - endif # NET_VENDOR_ALLWINNER -diff --git a/drivers/net/ethernet/allwinner/Makefile b/drivers/net/ethernet/allwinner/Makefile -index 03129f7..8bd1693c 100644 ---- a/drivers/net/ethernet/allwinner/Makefile -+++ b/drivers/net/ethernet/allwinner/Makefile -@@ -3,3 +3,4 @@ - # - - obj-$(CONFIG_SUN4I_EMAC) += sun4i-emac.o -+obj-$(CONFIG_SUN8I_EMAC) += sun8i-emac.o -diff --git a/drivers/net/ethernet/allwinner/sun8i-emac.c b/drivers/net/ethernet/allwinner/sun8i-emac.c -new file mode 100644 -index 0000000..6b07f68 ---- /dev/null -+++ b/drivers/net/ethernet/allwinner/sun8i-emac.c -@@ -0,0 +1,1615 @@ -+/* -+ * sun8i-h3-emac driver -+ * -+ * Copyright (C) 2015-2016 Corentin LABBE -+ * -+ * This is the driver for Allwinner Ethernet MAC found in H3/A83T/A64 SoC -+ * -+ * This is a mono block driver that need to be splited: -+ * - A classic ethernet MAC driver -+ * - A PHY driver -+ * - A clk driver -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+/* for A83T */ -+#include -+ -+#define SUN8I_EMAC_BASIC_CTL0 0x00 -+#define SUN8I_EMAC_BASIC_CTL1 0x04 -+ -+#define SUN8I_EMAC_MDIO_CMD 0x48 -+#define SUN8I_EMAC_MDIO_DATA 0x4C -+ -+#define SUN8I_EMAC_RX_CTL0 0x24 -+#define SUN8I_EMAC_RX_CTL1 0x28 -+ -+#define SUN8I_EMAC_TX_CTL0 0x10 -+#define SUN8I_EMAC_TX_CTL1 0x14 -+ -+#define SUN8I_EMAC_TX_FLOW_CTL 0x1C -+ -+#define SUN8I_EMAC_RX_FRM_FLT 0x38 -+ -+#define SUN8I_EMAC_INT_STA 0x08 -+#define SUN8I_EMAC_INT_EN 0x0C -+#define SUN8I_EMAC_RGMII_STA 0xD0 -+ -+#define SUN8I_EMAC_TX_DMA_STA 0xB0 -+#define SUN8I_EMAC_TX_CUR_DDESC 0xB4 -+#define SUN8I_EMAC_RX_DMA_STA 0xC0 -+ -+#define MDIO_CMD_MII_BUSY BIT(0) -+#define MDIO_CMD_MII_WRITE BIT(1) -+#define MDIO_CMD_MII_PHY_REG_ADDR_MASK GENMASK(8, 4) -+#define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4 -+#define MDIO_CMD_MII_PHY_ADDR_MASK GENMASK(16, 12) -+#define MDIO_CMD_MII_PHY_ADDR_SHIFT 12 -+ -+#define SUN8I_EMAC_MACADDR_HI 0x50 -+#define SUN8I_EMAC_MACADDR_LO 0x54 -+ -+#define SUN8I_EMAC_RX_DESC_LIST 0x34 -+#define SUN8I_EMAC_TX_DESC_LIST 0x20 -+ -+#define SUN8I_COULD_BE_USED_BY_DMA BIT(31) -+ -+/*#define EMAC_DEBUG*/ -+ -+struct dma_desc { -+ u32 status; -+ u32 st; -+ u32 buf_addr; -+ u32 next; -+} __attribute__((packed, aligned(4))); -+ -+static int flow_ctrl; -+static int pause = 0x400; -+ -+static int nbdesc = 16; -+struct sun8i_emac_priv { -+ void __iomem *base; -+ int irq; -+ struct device *dev; -+ struct net_device *ndev; -+ struct mii_bus *mdio; -+ spinlock_t lock; -+ spinlock_t tx_lock; -+ int duplex; -+ int speed; -+ int link; -+ int phy_interface; -+ struct device_node *phy_node; -+ struct clk *ahb_clk; -+ struct clk *tx_clk; -+ u32 mdc; -+ -+ struct reset_control *rst_phy; -+ struct reset_control *rst; -+ -+ struct dma_desc *dd_rx ____cacheline_aligned; -+ dma_addr_t dd_rx_phy ____cacheline_aligned; -+ struct dma_desc *dd_tx; -+ dma_addr_t dd_tx_phy; -+ struct sk_buff **rx_sk; -+ struct sk_buff **tx_sk; -+ -+ int tx_slot; -+ int tx_dma_start; -+}; -+ -+void rb_inc(int *p) { -+ (*p)++; -+ if (*p >= nbdesc) -+ *p = 0; -+} -+ -+static int sun8i_ephy_hack(struct net_device *ndev); -+ -+/* allocate a sk in a dma descriptor -+ * -+ * @i index of slot to fill -+*/ -+static int sun8i_emac_rx_sk(struct net_device *ndev, int i) -+{ -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ struct dma_desc *ddesc; -+ struct sk_buff *sk; -+ -+ ddesc = priv->dd_rx + i; -+ -+ ddesc->st = 0; -+ -+ /* TODO need to recheck this value */ -+ sk = netdev_alloc_skb_ip_align(ndev, 2000); -+ if (!sk) -+ return -ENOMEM; -+ -+ if (priv->rx_sk[i]) { -+ dev_warn(priv->dev, "WARN: Leaking a skbuff\n"); -+ /* TODO should not happen */ -+ } -+ -+ priv->rx_sk[i] = sk; -+ -+ ddesc->buf_addr = dma_map_single(priv->dev, sk->data, -+ ndev->mtu, DMA_FROM_DEVICE); -+ if (dma_mapping_error(priv->dev, ddesc->buf_addr)) { -+ dev_err(priv->dev, "ERROR: Cannot dma_map RX\n"); -+ dev_kfree_skb(sk); -+ return -EINVAL; -+ } -+ ddesc->st |= 2000; -+ ddesc->status = BIT(31); -+ -+/* dev_info(priv->dev, "Init ddesc %02d at %pad buff=%p %x status=(%x %x) len=%d\n", -+ i, &ddesc, &sk->data, ddesc->buf_addr, ddesc->status, -+ ddesc->st, ndev->mtu);*/ -+ -+ return 0; -+} -+ -+/* Set MAC address for slot index -+ * */ -+static void sun8i_emac_set_macaddr(struct sun8i_emac_priv *priv, -+ unsigned char *addr, int index) -+{ -+ u32 v; -+ -+ if (!is_valid_ether_addr(addr)) { -+ random_ether_addr(priv->ndev->dev_addr); -+ addr = priv->ndev->dev_addr; -+ } -+ dev_info(priv->dev, "%s slot %d %x %x %x %x %x %x\n", __func__, index, -+ addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]), -+ -+ v = (addr[5] << 8) | addr[4]; -+ writel(v, priv->base + SUN8I_EMAC_MACADDR_HI + index * 8); -+ v = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; -+ writel(v, priv->base + SUN8I_EMAC_MACADDR_HI + index * 8); -+} -+ -+void sun8i_emac_set_link_mode(struct sun8i_emac_priv *priv) -+{ -+ u32 v; -+ -+ switch (priv->phy_interface) { -+ case PHY_INTERFACE_MODE_MII: -+ v = readl(priv->base + SUN8I_EMAC_BASIC_CTL0); -+ -+ if (!priv->duplex) -+ v &= ~BIT(0); -+ else -+ v |= BIT(0); -+ -+ v &= ~0x0C; -+ switch (priv->speed) { -+ case 1000: -+ break; -+ case 100: -+ v |= BIT(2); -+ v |= BIT(3); -+ break; -+ case 10: -+ v |= BIT(3); -+ break; -+ } -+ -+ writel(v, priv->base + SUN8I_EMAC_BASIC_CTL0); -+ break; -+ case PHY_INTERFACE_MODE_RGMII: -+ v = readl(priv->base + SUN8I_EMAC_RGMII_STA); -+ -+ if (!priv->duplex) -+ v &= ~BIT(0); -+ else -+ v |= BIT(0); -+ -+ v &= ~0x06; -+ switch (priv->speed) { -+ case 1000: -+ v |= BIT(2); -+ break; -+ case 100: -+ v |= BIT(1); -+ break; -+ case 10: -+ break; -+ } -+ -+ writel(v, priv->base + SUN8I_EMAC_RGMII_STA); -+ break; -+ default: -+ dev_err(priv->dev, "Unknown PHY type %d\n", priv->phy_interface); -+ return; -+ } -+} -+ -+static void sun8i_emac_flow_ctrl(struct sun8i_emac_priv *priv, int duplex, int fc, -+ int pause) -+{ -+ u32 flow = 0; -+ -+ dev_info(priv->dev, "%s %d %d %d\n", __func__, duplex, fc, pause); -+ -+ if (fc & BIT(0)) { -+ flow = readl(priv->base + SUN8I_EMAC_RX_CTL0); -+ flow |= 0x10000; -+ /*flow |= BIT(16);*/ -+ writel(flow, priv->base + SUN8I_EMAC_RX_CTL0); -+ } -+ -+ if (fc & BIT(1)) { -+ flow = readl(priv->base + SUN8I_EMAC_TX_FLOW_CTL); -+ flow |= BIT(0); -+ writel(flow, priv->base + SUN8I_EMAC_TX_FLOW_CTL); -+ } -+ -+ if (duplex) { -+ flow = readl(priv->base + SUN8I_EMAC_TX_FLOW_CTL); -+ flow |= (pause << 4); -+ /* pause & BIT(4)*/ -+ writel(flow, priv->base + SUN8I_EMAC_TX_FLOW_CTL); -+ } -+} -+ -+/* -+ * Grab a frame into a skb -+*/ -+static int sun8i_emac_rx_from_ddesc(struct net_device *ndev, int i) -+{ -+ struct sk_buff *skb; -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ struct dma_desc *ddesc; -+ int frame_len; -+ -+ ddesc = priv->dd_rx + i; -+ -+ /* possible erros */ -+ if ((ddesc->status & BIT(0)) > 0) { -+ /*dev_warn(priv->dev, "the checksum or length of received frame's payload is wrong.\n");*/ -+ } -+ if ((ddesc->status & BIT(7)) > 0) { -+ /*dev_warn(priv->dev, "RX_HEADER_ERR\n");*/ -+ } -+ -+ if ((ddesc->status & BIT(9)) == 0) { -+ /* begin of a frame */ -+ dev_warn(priv->dev, "This should not happen\n"); -+ } -+ frame_len = (ddesc->status >> 16) & 0x3FFF; -+ skb = priv->rx_sk[i]; -+ -+ #ifdef EMAC_DEBUG -+ dev_info(priv->dev, "%s from %02d %pad len=%d status=%x st=%x\n", -+ __func__, i, &ddesc, frame_len, ddesc->status, ddesc->st); -+ #endif -+ -+ skb_put(skb, frame_len); -+ -+ dma_unmap_single(priv->dev, ddesc->buf_addr, ndev->mtu, DMA_FROM_DEVICE); -+ skb->protocol = eth_type_trans(skb, priv->ndev); -+ skb->ip_summed = CHECKSUM_UNNECESSARY; -+ skb->dev = priv->ndev; -+ -+ priv->ndev->stats.rx_packets++; -+ priv->ndev->stats.rx_bytes += frame_len; -+ priv->rx_sk[i] = NULL; -+ -+ /* this frame is not the last */ -+ /* -+ if ((ddesc->status & BIT(8)) == 0) { -+ dev_warn(priv->dev, "Multi frame not implemented currlen=%d\n", frame_len); -+ rb_inc(&i); -+ ddesc = priv->dd_rx + i; -+ frame_len = (ddesc->status >> 16) & 0x3FFF; -+ dev_info(priv->dev, "Multi frame currlen=%d\n", frame_len); -+ } -+ */ -+ -+ sun8i_emac_rx_sk(ndev, i); -+ -+ netif_rx(skb); -+ -+ return 0; -+} -+ -+static int sun8i_emac_receive_all(struct net_device *ndev) -+{ -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ struct dma_desc *ddesc; -+ int i; -+ -+ for (i = 0; i < nbdesc; i++) { -+ ddesc = priv->dd_rx + i; -+ if (!(ddesc->status & BIT(31))) { -+ sun8i_emac_rx_from_ddesc(ndev, i); -+ } -+ } -+ return 0; -+} -+ -+/* iterate over dma desc for finding completed xmit */ -+static int sun8i_emac_complete_xmit(struct net_device *ndev) -+{ -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ struct dma_desc *ddesc; -+ int i, frame_len; -+ -+ #ifdef EMAC_DEBUG -+ dev_info(priv->dev, "%s\n", __func__); -+ #endif -+ -+ /*spin_lock(&priv->tx_lock);*/ -+ for (i = 0; i < nbdesc; i++) { -+ ddesc = priv->dd_tx + i; -+ if (ddesc->status & BIT(31)) -+ continue; -+ if (ddesc->status != 0 || ddesc->st) { -+ frame_len = ddesc->st & 0x3FFF; -+ #ifdef EMAC_DEBUG -+ dev_info(priv->dev, "%s found slot to clean %d at %pad %x %x (len=%d)\n", -+ __func__, i, &ddesc, ddesc->status, ddesc->st, -+ frame_len); -+ #endif -+ if (priv->tx_sk[i]) { -+ dev_kfree_skb_irq(priv->tx_sk[i]); -+ priv->tx_sk[i] = NULL; -+ priv->ndev->stats.tx_packets++; -+ dma_unmap_single(priv->dev, ddesc->buf_addr, -+ frame_len, DMA_TO_DEVICE); -+ } else { -+ dma_unmap_page(priv->dev, ddesc->buf_addr, frame_len, DMA_TO_DEVICE); -+ } -+ ddesc->status = 0; -+ ddesc->st = 0; -+ priv->ndev->stats.tx_bytes += frame_len; -+ } -+ } -+ /*spin_unlock(&priv->tx_lock);*/ -+ -+ return 0; -+} -+ -+static int debug_printall_desc(struct net_device *ndev) -+{ -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ struct dma_desc *ddesc; -+ int i; -+ int len; -+ /*TODO hex_dump_to_buffer*/ -+ -+ return 0; -+ ddesc = priv->dd_rx; -+ if (!ddesc) -+ return 0; -+ len = 0; -+ for (i = 0; i < nbdesc; i++) { -+ ddesc = priv->dd_rx + i; -+ dev_info(priv->dev, "rx%02d status=%x %x d=%x len=%d n=%x", i, ddesc->status, ddesc->st, ddesc->buf_addr, len, ddesc->next); -+ } -+ ddesc = priv->dd_tx; -+ if (!ddesc) -+ return 0; -+ for (i = 0; i < nbdesc; i++) { -+ ddesc = priv->dd_tx + i; -+ len = ddesc->st & 0x7FF; -+ dev_info(priv->dev, "tx%02d status=%x %x d=%x len=%d n=%x", i, ddesc->status, ddesc->st, ddesc->buf_addr, len, ddesc->next); -+ } -+ return 0; -+} -+ -+static int sun8i_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) -+{ -+ struct net_device *ndev = bus->priv; -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ int err; -+ u32 reg; -+ -+ err = readl_poll_timeout(priv->base + SUN8I_EMAC_MDIO_CMD, reg, -+ !(reg & MDIO_CMD_MII_BUSY), 100, 10000); -+ if (err) { -+ dev_err(priv->dev, "%s timeout %x\n", __func__, reg); -+ return err; -+ } -+ -+ /* TODO the MDC value is ... */ -+ reg &= ~MDIO_CMD_MII_WRITE; -+ reg &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK; -+ reg |= (phy_reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) & -+ MDIO_CMD_MII_PHY_REG_ADDR_MASK; -+ -+ reg &= ~MDIO_CMD_MII_PHY_ADDR_MASK; -+ -+ reg |= (phy_addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) & -+ MDIO_CMD_MII_PHY_ADDR_MASK; -+ -+ reg |= MDIO_CMD_MII_BUSY; -+ -+ writel(reg, priv->base + SUN8I_EMAC_MDIO_CMD); -+ -+ err = readl_poll_timeout(priv->base + SUN8I_EMAC_MDIO_CMD, reg, -+ !(reg & MDIO_CMD_MII_BUSY), 100, 10000); -+ -+ if (err) { -+ dev_err(priv->dev, "%s timeout %x\n", __func__, reg); -+ return err; -+ } -+ -+ return readl(priv->base + SUN8I_EMAC_MDIO_DATA); -+} -+ -+static int sun8i_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, -+ u16 data) -+{ -+ struct net_device *ndev = bus->priv; -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ u32 reg; -+ int err; -+ -+ err = readl_poll_timeout(priv->base + SUN8I_EMAC_MDIO_CMD, reg, -+ !(reg & MDIO_CMD_MII_BUSY), 100, 10000); -+ if (err) { -+ dev_err(priv->dev, "%s timeout %x\n", __func__, reg); -+ return err; -+ } -+ -+ reg &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK; -+ reg |= (phy_reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) & -+ MDIO_CMD_MII_PHY_REG_ADDR_MASK; -+ -+ reg &= ~MDIO_CMD_MII_PHY_ADDR_MASK; -+ reg |= (phy_addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) & -+ MDIO_CMD_MII_PHY_ADDR_MASK; -+ -+ reg |= MDIO_CMD_MII_WRITE; -+ reg |= MDIO_CMD_MII_BUSY; -+ -+ writel(reg, priv->base + SUN8I_EMAC_MDIO_CMD); -+ writel(data, priv->base + SUN8I_EMAC_MDIO_DATA); -+/* dev_info(priv->dev, "%s %d %d %x %x\n", __func__, phy_addr, phy_reg, reg, data);*/ -+ -+ err = readl_poll_timeout(priv->base + SUN8I_EMAC_MDIO_CMD, reg, -+ !(reg & MDIO_CMD_MII_BUSY), 100, 10000); -+ if (err) { -+ dev_err(priv->dev, "%s timeout %x\n", __func__, reg); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static int sun8i_emac_mdio_register(struct net_device *ndev) -+{ -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ struct mii_bus *bus; -+ int ret; -+ -+ dev_info(priv->dev, "%s\n", __func__); -+ -+ bus = devm_mdiobus_alloc(priv->dev); -+ if (!bus) { -+ netdev_err(ndev, "Failed to alloc new mdio bus\n"); -+ return -ENOMEM; -+ } -+ -+ bus->name = dev_name(priv->dev); -+ bus->read = &sun8i_mdio_read; -+ bus->write = &sun8i_mdio_write; -+ snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%x", bus->name, 0); -+ -+ bus->parent = priv->dev; -+ bus->priv = ndev; -+ -+ ret = of_mdiobus_register(bus, priv->dev->of_node); -+ if (ret) { -+ netdev_err(ndev, "Could not register as MDIO bus: %d\n", ret); -+ return ret; -+ } -+ -+ priv->mdio = bus; -+ -+ return 0; -+} -+ -+/* END of need to moved in phy/ */ -+ -+static void sun8i_emac_adjust_link(struct net_device *ndev) -+{ -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ struct phy_device *phydev = ndev->phydev; -+ unsigned long flags; -+ int new_state = 0; -+ /*int i;*/ -+ -+ dev_info(priv->dev, "%s link=%x duplex=%x speed=%x\n", __func__, phydev->link, -+ phydev->duplex, phydev->speed); -+ if (!phydev) -+ return; -+ -+ spin_lock_irqsave(&priv->lock, flags); -+ -+ if (phydev->link) { -+ if (phydev->duplex != priv->duplex) { -+ new_state = 1; -+ priv->duplex = phydev->duplex; -+ } -+ if (phydev->pause) -+ sun8i_emac_flow_ctrl(priv, phydev->duplex, -+ flow_ctrl, pause); -+ -+ if (phydev->speed != priv->speed) { -+ new_state = 1; -+ priv->speed = phydev->speed; -+ } -+ -+ if (priv->link == 0) { -+ new_state = 1; -+ priv->link = phydev->link; -+ } -+ -+ dev_info(priv->dev, "%s new=%d link=%d pause=%d\n", -+ __func__, new_state, priv->link, phydev->pause); -+ if (new_state) -+ sun8i_emac_set_link_mode(priv); -+ } else if (priv->link != phydev->link) { -+ new_state = 1; -+ priv->link = 0; -+ priv->speed = 0; -+ priv->duplex = -1; -+ } -+ if (new_state) -+ phy_print_status(phydev); -+ -+ spin_unlock_irqrestore(&priv->lock, flags); -+} -+ -+static int sun8i_emac_init(struct net_device *ndev) -+{ -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ struct device_node *node = priv->dev->of_node; -+ unsigned long rate; -+ u32 reg; -+ int ret; -+ -+ dev_info(priv->dev, "%s\n", __func__); -+ -+ priv->phy_interface = of_get_phy_mode(node); -+ if (priv->phy_interface < 0) { -+ netdev_err(ndev, "PHY interface mode node specified\n"); -+ return priv->phy_interface; -+ } -+ -+ priv->phy_node = of_parse_phandle(node, "phy", 0); -+ if (!priv->phy_node) { -+ netdev_err(ndev, "no associated PHY\n"); -+ return -ENODEV; -+ } -+ -+ ret = clk_prepare_enable(priv->ahb_clk); -+ if (ret) { -+ netdev_err(ndev, "Could not enable ahb clock"); -+ return ret; -+ } -+ -+ if (priv->rst) { -+ ret = reset_control_deassert(priv->rst); -+ if (ret) { -+ netdev_err(ndev, "Could not deassert reset\n"); -+ goto err_disable_ahb_clk; -+ } -+ } -+ -+ rate = clk_get_rate(priv->ahb_clk); -+ if (rate > 160000000) -+ reg = 0x3 << 20; /* AHB / 128 */ -+ else if (rate > 80000000) -+ reg = 0x2 << 20; /* AHB / 64 */ -+ else if (rate > 40000000) -+ reg = 0x1 << 20; /* AHB / 32 */ -+ else -+ reg = 0x0 << 20; /* AHB / 16 */ -+ dev_info(priv->dev, "MDC auto : %x\n", reg); -+ writel(reg, priv->base + SUN8I_EMAC_MDIO_CMD); -+ -+ sun8i_ephy_hack(ndev); -+ -+ ret = sun8i_emac_mdio_register(ndev); -+ if (ret) -+ goto err_assert_reset; -+ -+ return 0; -+err_assert_reset: -+ if (priv->rst) -+ reset_control_assert(priv->rst); -+err_disable_ahb_clk: -+ clk_disable_unprepare(priv->ahb_clk); -+ return ret; -+} -+ -+static void sun8i_emac_uninit(struct net_device *ndev) -+{ -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ -+ mdiobus_unregister(priv->mdio); -+ if (priv->rst) -+ reset_control_assert(priv->rst); -+ -+ clk_disable_unprepare(priv->ahb_clk); -+} -+ -+/* this function do lots of things that will be splited away (clk/phy) */ -+static int sun8i_ephy_hack(struct net_device *ndev) -+{ -+ -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ int err; -+ void __iomem *sc; -+ u32 v; -+ int do_ephy_clk = 1; -+ -+ dev_info(priv->dev, "%s\n", __func__); -+ -+ /* find type of PHY */ -+ priv->phy_interface = of_get_phy_mode(priv->dev->of_node); -+ dev_info(priv->dev, "%s phy_interface=%x\n", __func__, priv->phy_interface); -+ /*priv->phy_interface = PHY_INTERFACE_MODE_RGMII;*/ -+ -+ /* fallback to integrate MII */ -+ switch (priv->phy_interface) { -+ case PHY_INTERFACE_MODE_MII: -+ dev_info(priv->dev, "%s interface PHY_INTERFACE_MODE_MII\n", __func__); -+ break; -+ case PHY_INTERFACE_MODE_RGMII: -+ dev_info(priv->dev, "%s interface PHY_INTERFACE_MODE_RGMII\n", __func__); -+ break; -+ case PHY_INTERFACE_MODE_RMII: -+ dev_info(priv->dev, "%s interface PHY_INTERFACE_MODE_RMII\n", __func__); -+ break; -+ case PHY_INTERFACE_MODE_GMII: -+ dev_info(priv->dev, "%s interface PHY_INTERFACE_MODE_GMII\n", __func__); -+ break; -+ default: -+ dev_info(priv->dev, "Fallback to MII\n"); -+ priv->phy_interface = PHY_INTERFACE_MODE_MII; -+ } -+ -+ /* systemcontrol */ -+ /* TODO put that in phy clock */ -+ sc = ioremap(0x01C00030, 0x20); -+ if (sc) { -+ v = readl(sc); -+ dev_info(priv->dev, "SystemControl %x\n", v); -+ /* crappy switch to be moved */ -+ switch (v) { -+ case 0: /* A83T */ -+ do_ephy_clk = 0; -+ switch (priv->phy_interface) { -+ case PHY_INTERFACE_MODE_MII: -+ v &= ~BIT(2); -+ break; -+ case PHY_INTERFACE_MODE_RGMII: -+ v |= BIT(1); -+ v |= BIT(2); -+ v |= BIT(15); -+ break; -+ case PHY_INTERFACE_MODE_GMII: -+ v &= ~BIT(2); -+ break; -+ default: -+ dev_err(priv->dev, "Unknown PHY type %d\n", priv->phy_interface); -+ } -+ break; -+ case 0x58000: /* H3 */ -+ switch (priv->phy_interface) { -+ case PHY_INTERFACE_MODE_MII: -+ /* PHY_SELECT: Internal PHY */ -+ v |= BIT(15); -+ /* SHUTDOWN: Power up */ -+ v &= ~BIT(16); -+ /* 24 Mhz */ -+ /*v &= ~BIT(18);*/ -+ /* LED POL */ -+ v |= BIT(17); -+ break; -+ case PHY_INTERFACE_MODE_RGMII: -+ v |= BIT(1); -+ v |= BIT(2); -+ /* External PHY */ -+ v &= ~BIT(15); -+ /* SHUTDOWN: Shutdown */ -+ v |= BIT(16); -+ break; -+ /* TODO RMII */ -+ default: -+ dev_err(priv->dev, "Unknown PHY type %d\n", priv->phy_interface); -+ } -+ break; -+ default: -+ dev_err(priv->dev, "Unknown platform %x\n", v); -+ } -+ dev_info(priv->dev, "SystemControl %x\n", v); -+ writel(v, sc); -+ iounmap(sc); -+ } -+ /* end phy clock */ -+ -+ /* PWM */ -+ sc = ioremap(0x01C21400, 0x20); -+ if (sc) { -+ v = readl(sc); -+ dev_info(priv->dev, "PWM %x\n", v); -+ v = readl(sc + 0x04); -+ dev_info(priv->dev, "PWM %x\n", v); -+ iounmap(sc); -+ } -+ -+ if (do_ephy_clk == 1) { -+ priv->tx_clk = devm_clk_get(priv->dev, "bus_ephy"); -+ if (IS_ERR(priv->tx_clk)) { -+ err = PTR_ERR(priv->tx_clk); -+ dev_err(priv->dev, "Cannot get MII clock err=%d\n", err); -+ return err; -+ } -+ err = clk_prepare_enable(priv->tx_clk); -+ if (err != 0) { -+ dev_err(priv->dev, "Cannot prepare_enable PHY\n"); -+ return err; -+ } else { -+ dev_info(priv->dev, "PHY clk is enabled\n"); -+ } -+ -+ priv->rst_phy = devm_reset_control_get(priv->dev, "ephy"); -+ if (IS_ERR(priv->rst_phy)) { -+ err = PTR_ERR(priv->rst_phy); -+ dev_info(priv->dev, "no PHY reset control found %d\n", err); -+ priv->rst_phy = NULL; -+ } -+ if (priv->rst_phy) { -+ err = reset_control_deassert(priv->rst_phy); -+ if (err) -+ dev_err(priv->dev, "Cannot deassert PHY\n"); -+ else -+ dev_info(priv->dev, "PHY is de-asserted\n"); -+ } -+ } -+ return 0; -+} -+ -+static int sun8i_emac_mdio_probe(struct net_device *ndev) -+{ -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ struct phy_device *phydev = NULL; -+ int err; -+ int timeout, value; -+ -+ phydev = phy_find_first(priv->mdio); -+ if (!phydev) { -+ netdev_err(ndev, "No PHY found!\n"); -+ err = PTR_ERR(phydev); -+ return err; -+ } -+ -+ phydev->irq = PHY_POLL; -+ -+ /*priv->phy_interface = PHY_INTERFACE_MODE_MII;*/ -+ -+/* phydev = of_phy_connect(ndev, */ -+ phydev = phy_connect(ndev, phydev_name(phydev), -+ &sun8i_emac_adjust_link, priv->phy_interface); -+ -+ if (IS_ERR(phydev)) { -+ err = PTR_ERR(phydev); -+ netdev_err(ndev, "Could not attach to PHY: %d\n", err); -+ return err; -+ } -+ -+ netdev_info(ndev, "%s: PHY ID %08x at %d IRQ %s (%s)\n", -+ ndev->name, phydev->phy_id, phydev->mdio.addr, -+ "poll", phydev_name(phydev)); -+ -+ phy_write(phydev, MII_BMCR, BMCR_RESET); -+ timeout = 0; -+ while (BMCR_RESET & phy_read(phydev, MII_BMCR) && timeout++ < 15) -+ msleep(3); -+ if (timeout >= 15) -+ dev_warn(priv->dev, "PHY reset timeout\n"); -+ -+ value = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, (value & ~BMCR_PDOWN)); -+ -+ /* mask with MAC supported features */ -+ phydev->supported &= PHY_GBIT_FEATURES; -+ phydev->advertising = phydev->supported; -+ phy_print_status(phydev); -+ -+ ndev->phydev = phydev; /* unnecessary ? (done by a sub function of phy_connect */ -+ priv->link = 0; -+ priv->speed = 0; -+ priv->duplex = -1; -+ -+ return 0; -+} -+ -+static int sun8i_emac_set_mac_address(struct net_device *ndev, void *p) -+{ -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ -+ dev_info(priv->dev, "%s\n", __func__); -+ sun8i_emac_set_macaddr(priv, p, 0); -+ return 0; -+} -+ -+static int sun8i_emac_open(struct net_device *ndev) -+{ -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ int err; -+ u32 v, dr, dt, vtxphy; -+ struct dma_desc *ddesc; -+ int i; -+ int timeout = 0; -+ unsigned long rate; -+ -+ err = sun8i_emac_mdio_probe(ndev); -+ if (err) -+ return err; -+ -+ /* Do SOFT RST */ -+ v = readl(priv->base + SUN8I_EMAC_BASIC_CTL1); -+ writel(v | 0x01, priv->base + SUN8I_EMAC_BASIC_CTL1); -+ -+ /* wait for reset to be ended */ -+ do { -+ v = readl(priv->base + SUN8I_EMAC_BASIC_CTL1); -+ } while ((v & 0x01) != 0 && timeout++ < 50); -+ if (timeout >= 50) -+ dev_warn(priv->dev, "EMAC reset timeout\n"); -+ /*TODO continue or die ? */ -+ -+ rate = clk_get_rate(priv->ahb_clk); -+ if (rate > 160000000) -+ v = 0x3 << 20; /* AHB / 128 */ -+ else if (rate > 80000000) -+ v = 0x2 << 20; /* AHB / 64 */ -+ else if (rate > 40000000) -+ v = 0x1 << 20; /* AHB / 32 */ -+ else -+ v = 0x0 << 20; /* AHB / 16 */ -+ dev_info(priv->dev, "MDC auto : %x\n", v); -+ writel(v, priv->base + SUN8I_EMAC_MDIO_CMD); -+ -+ /* DMA */ -+ v = (8 << 24);/* burst len */ -+ writel(v, priv->base + SUN8I_EMAC_BASIC_CTL1); -+#define RX_INT BIT(8) -+#define TX_INT BIT(0) -+#define TX_UNF_INT BIT(4) -+ writel(RX_INT | TX_INT | TX_UNF_INT, priv->base + SUN8I_EMAC_INT_EN); -+ v = readl(priv->base + SUN8I_EMAC_INT_EN); -+ -+ v = readl(priv->base + SUN8I_EMAC_TX_CTL0); -+ /* TX_FRM_LEN_CL */ -+ /*v |= BIT(30);*/ -+ writel(v, priv->base + SUN8I_EMAC_TX_CTL0); -+ -+ v = readl(priv->base + SUN8I_EMAC_RX_CTL0); -+ /* CHECK_CRC */ -+ v |= BIT(27); -+ /* STRIP_FCS */ -+ v |= BIT(28); -+ /* JUMBO_FRM_EN */ -+ v |= BIT(29); -+ writel(v, priv->base + SUN8I_EMAC_RX_CTL0); -+ -+ v = readl(priv->base + SUN8I_EMAC_TX_CTL1); -+ /* TX_MD Transmission starts after a full frame located in TX DMA FIFO */ -+ v |= BIT(1); -+ writel(v, priv->base + SUN8I_EMAC_TX_CTL1); -+ -+ v = readl(priv->base + SUN8I_EMAC_RX_CTL1); -+ /* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a -+ * complete frame has been written to RX DMA FIFO -+ */ -+ v |= BIT(1); -+ writel(v, priv->base + SUN8I_EMAC_RX_CTL1); -+ -+ sun8i_emac_set_mac_address(ndev, ndev->dev_addr); -+ -+ priv->rx_sk = kcalloc(nbdesc, sizeof(struct sk_buff *), GFP_KERNEL); -+ if (!priv->rx_sk) { -+ err = -ENOMEM; -+ goto rx_sk_error; -+ } -+ priv->tx_sk = kcalloc(nbdesc, sizeof(struct sk_buff *), GFP_KERNEL); -+ if (!priv->tx_sk) { -+ err = -ENOMEM; -+ goto tx_sk_error; -+ } -+ -+ priv->dd_rx = dma_alloc_coherent(priv->dev, -+ nbdesc * sizeof(struct dma_desc), -+ &priv->dd_rx_phy, -+ GFP_KERNEL); -+ if (!priv->dd_rx) { -+ dev_err(priv->dev, "ERROR: cannot DMA RX"); -+ err = -ENOMEM; -+ goto dma_rx_error; -+ } -+ memset(priv->dd_rx, 0, nbdesc * sizeof(struct dma_desc)); -+ ddesc = priv->dd_rx; -+ for (i = 0; i < nbdesc; i++) { -+ sun8i_emac_rx_sk(ndev, i); -+ ddesc->next = (u32)priv->dd_rx_phy + (i + 1) * sizeof(struct dma_desc); -+ ddesc++; -+ } -+ /* last descriptor point back to first one */ -+ ddesc--; -+ ddesc->next = (u32)priv->dd_rx_phy; -+ -+ priv->dd_tx = dma_alloc_coherent(priv->dev, -+ nbdesc * sizeof(struct dma_desc), -+ &priv->dd_tx_phy, -+ GFP_KERNEL); -+ if (!priv->dd_tx) { -+ dev_err(priv->dev, "ERROR: cannot DMA TX"); -+ err = -ENOMEM; -+ goto dma_tx_error; -+ } -+ memset(priv->dd_tx, 0, nbdesc * sizeof(struct dma_desc)); -+ ddesc = priv->dd_tx; -+ for (i = 0; i < nbdesc; i++) { -+ ddesc->status = 0; -+ ddesc->st = 0; -+ ddesc->next = (u32)(priv->dd_tx_phy + (i + 1) * sizeof(struct dma_desc)); -+ ddesc++; -+ } -+ /* last descriptor point back to first one */ -+ ddesc--; -+ ddesc->next = (u32)priv->dd_tx_phy; -+ i--; -+ -+ if (ndev->phydev) { -+ phy_start(ndev->phydev); -+ } -+ -+ writel(priv->dd_rx_phy, priv->base + SUN8I_EMAC_RX_DESC_LIST); -+ v = readl(priv->base + SUN8I_EMAC_RX_CTL1); -+ v |= BIT(30); -+ /*v |= (1 << 31);*/ -+ /*dev_info(priv->dev, "%s %lx %lx\n", __func__, 0x40000000, BIT(30));*/ -+ writel(v, priv->base + SUN8I_EMAC_RX_CTL1); -+ -+ writel(priv->dd_tx_phy, priv->base + SUN8I_EMAC_TX_DESC_LIST); -+ v = readl(priv->base + SUN8I_EMAC_TX_CTL1); -+ v |= BIT(30); -+/* v |= (1 << 31);*/ -+ writel(v, priv->base + SUN8I_EMAC_TX_CTL1); -+ -+ /* activate TX */ -+ v = readl(priv->base + SUN8I_EMAC_TX_CTL0); -+ v |= (1 << 31); -+ writel(v, priv->base + SUN8I_EMAC_TX_CTL0); -+ -+ /* activate RX */ -+ v = readl(priv->base + SUN8I_EMAC_RX_CTL0); -+ v |= (1 << 31); -+ writel(v, priv->base + SUN8I_EMAC_RX_CTL0); -+ -+ writel(0x3FFF, priv->base + SUN8I_EMAC_INT_STA); -+ netif_start_queue(ndev); -+ -+ v = readl(priv->base + SUN8I_EMAC_RX_DESC_LIST); -+ vtxphy = readl(priv->base + SUN8I_EMAC_TX_DESC_LIST); -+ dt = readl(priv->base + SUN8I_EMAC_TX_DMA_STA); -+ dr = readl(priv->base + SUN8I_EMAC_RX_DMA_STA); -+ -+ return 0; -+dma_tx_error: -+ dma_free_coherent(priv->dev, nbdesc * sizeof(struct dma_desc), -+ priv->dd_rx, priv->dd_rx_phy); -+dma_rx_error: -+ kfree(priv->tx_sk); -+tx_sk_error: -+ kfree(priv->rx_sk); -+rx_sk_error: -+ return err; -+} -+ -+static int sun8i_emac_stop(struct net_device *ndev) -+{ -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ -+ dev_info(priv->dev, "%s\n", __func__); -+ -+ /* Stop receiver */ -+ writel(0, priv->base + SUN8I_EMAC_RX_CTL0); -+ -+ netif_stop_queue(ndev); -+ netif_carrier_off(ndev); -+ -+ phy_stop(ndev->phydev); -+ phy_disconnect(ndev->phydev); -+ -+ return 0; -+} -+ -+static netdev_tx_t sun8i_emac_xmit(struct sk_buff *skb, struct net_device *ndev) -+{ -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ struct dma_desc *ddesc; -+ int i = 0, rbd_i; -+ unsigned int len; -+ u32 v; -+ int n; -+ int nf; -+ const skb_frag_t *frag; -+ -+ len = skb_headlen(skb); -+ -+ #ifdef EMAC_DEBUG -+ dev_info(priv->dev, "%s xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx len=%u skblen=%u\n", __func__, len, skb->len); -+ #endif -+ /*hex_dump_to_buffer(*/ -+ -+ spin_lock(&priv->tx_lock); -+ /* find first empty descriptor not optimized */ -+ /* tx_slot is bad, better store address and follow ->next */ -+ ddesc = priv->dd_tx + priv->tx_slot; -+ if (ddesc->status == 0) { -+ i = priv->tx_slot; -+ rb_inc(&priv->tx_slot); -+ #ifdef EMAC_DEBUG -+ dev_info(priv->dev, "%s found txslot %d at %pad (txslot=%d)\n", -+ __func__, i, &ddesc, priv->tx_slot); -+ #endif -+ } else { -+ while (i < nbdesc) { -+ ddesc = priv->dd_tx + i; -+ /*if ((ddesc->status & BIT(31)) == 0) {*/ -+ if (ddesc->status == 0) -+ break; -+ i++; -+ } -+ #ifdef EMAC_DEBUG -+ dev_info(priv->dev, "%s found slot %d at %pad (txslot=%d)\n", -+ __func__, i, &ddesc, priv->tx_slot); -+ #endif -+ } -+ -+ if (i >= nbdesc) { -+ dev_err(priv->dev, "ERROR: TX is full\n"); -+ spin_unlock(&priv->tx_lock); -+ return NETDEV_TX_BUSY; -+ } -+ -+ priv->tx_sk[i] = skb; -+ ddesc->buf_addr = dma_map_single(priv->dev, skb->data, len, -+ DMA_TO_DEVICE); -+ -+ if (dma_mapping_error(priv->dev, ddesc->buf_addr)) { -+ dev_err(priv->dev, "ERROR: Cannot dmamap buf\n"); -+ return -EFAULT; -+ } -+ -+ ddesc->st = len; -+ /* undocumented bit that make it works TODO */ -+ ddesc->st |= BIT(24); -+ /* Checksum */ -+ /* TODO conditional CRC -+ * ndev->hw_features & NETIF_F_IP_CSUM/NETIF_F_IPV6_CSUM */ -+ ddesc->st |= BIT(27); -+ ddesc->st |= BIT(28); -+ /* frame begin */ -+ ddesc->st |= BIT(29); -+ rbd_i = i; -+ -+ /* handle fragmented skb */ -+ n = skb_shinfo(skb)->nr_frags; -+ if (n > 0) { -+ /*dev_info(priv->dev, "FRAGMENTS %d\n", n);*/ -+ for (nf = 0; nf < n; nf++) { -+ frag = &skb_shinfo(skb)->frags[nf]; -+ rb_inc(&i); -+ /*dev_info(priv->dev, "FRAG %02d %u on %d\n", nf, skb_frag_size(frag), i);*/ -+ ddesc = priv->dd_tx + i; -+ /* TODO check used*/ -+ if (ddesc->st & BIT(31)) -+ dev_err(priv->dev, "Already used\n"); -+ ddesc->st = skb_frag_size(frag); -+ ddesc->st |= BIT(24); -+ ddesc->buf_addr = skb_frag_dma_map(priv->dev, frag, 0, skb_frag_size(frag), DMA_TO_DEVICE); -+ if (dma_mapping_error(priv->dev, ddesc->buf_addr)) { -+ dev_err(priv->dev, "DMA MAP ERROR\n"); -+ /* TODO dma err*/ -+ } -+ /*ddesc->buf_addr = dma_map_single(priv->dev, skb->data, len,*/ -+ } -+ -+ } -+ -+ /* frame end */ -+ ddesc->st |= BIT(30); -+ /* We want an interrupt after transmission */ -+ ddesc->st |= BIT(31); -+ -+ rb_inc(&i); -+ do { -+ ddesc = priv->dd_tx + rbd_i; -+ ddesc->st |= BIT(27); -+ ddesc->st |= BIT(28); -+ /* DMA can work on it */ -+ ddesc->status = BIT(31); -+ #ifdef EMAC_DEBUG -+ dev_info(priv->dev, "xmit final %02d %x %x\n", rbd_i, ddesc->status, ddesc->st); -+ #endif -+ rb_inc(&rbd_i); -+ } while (rbd_i != i); -+ priv->tx_slot = i; -+ -+ v = readl(priv->base + SUN8I_EMAC_TX_CTL0); -+ v |= BIT(31);/* TODO do a define */ -+ writel(v, priv->base + SUN8I_EMAC_TX_CTL0); -+ -+ if (priv->tx_dma_start == 0) { -+ v = readl(priv->base + SUN8I_EMAC_TX_CTL1); -+ v |= BIT(31);/* mandatory */ -+ v |= BIT(30);/* TODO do a define */ -+ writel(v, priv->base + SUN8I_EMAC_TX_CTL1); -+ priv->tx_dma_start = 1; -+ } -+ -+ -+ spin_unlock(&priv->tx_lock); -+ -+ return NETDEV_TX_OK; -+} -+ -+static int sun8i_emac_change_mtu(struct net_device *ndev, int new_mtu) -+{ -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ int max_mtu; -+ -+ dev_info(priv->dev, "%s set MTU to %d\n", __func__, new_mtu); -+ -+ if (netif_running(ndev)) { -+ dev_err(priv->dev, "%s: must be stopped to change its MTU\n", -+ ndev->name); -+ return -EBUSY; -+ } -+ -+ max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); -+ -+ if ((new_mtu < 68) || (new_mtu > max_mtu)) { -+ dev_err(priv->dev, "%s: invalid MTU, max MTU is: %d\n", -+ ndev->name, max_mtu); -+ return -EINVAL; -+ } -+ -+ ndev->mtu = new_mtu; -+ netdev_update_features(ndev); -+ return 0; -+} -+ -+static netdev_features_t sun8i_emac_fix_features(struct net_device *ndev, -+ netdev_features_t features) -+{ -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ -+ dev_info(priv->dev, "%s %llx\n", __func__, features); -+ return features; -+} -+ -+static int sun8i_emac_set_features(struct net_device *ndev, netdev_features_t features) -+{ -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ u32 v; -+ -+ v = readl(priv->base + SUN8I_EMAC_BASIC_CTL0); -+ if (features & NETIF_F_LOOPBACK && netif_running(ndev)) { -+ dev_info(priv->dev, "Must set loopback\n"); -+ v |= BIT(1); -+ } else { -+ dev_info(priv->dev, "Must unset loopback\n"); -+ v &= ~BIT(1); -+ } -+ writel(v, priv->base + SUN8I_EMAC_BASIC_CTL0); -+ -+ dev_info(priv->dev, "%s %llx %x\n", __func__, features, v); -+ -+ return 0; -+} -+ -+static void sun8i_emac_set_rx_mode(struct net_device *ndev) -+{ -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ u32 v = 0; -+ int i = 0; -+ struct netdev_hw_addr *ha; -+ -+ /* Disable address filter */ -+ v |= BIT(31); -+ /* Receive all multicast frames */ -+ v |= BIT(16); -+ /* Receive all control frames */ -+ v |= BIT(13); -+ if (ndev->flags & IFF_PROMISC) -+ v |= BIT(1); -+ if (netdev_uc_count(ndev) > 7) { -+ v |= BIT(1); -+ } else { -+ netdev_for_each_uc_addr(ha, ndev) { -+ i++; -+ sun8i_emac_set_macaddr(priv, ha->addr, i); -+ } -+ } -+ writel(v, priv->base + SUN8I_EMAC_RX_FRM_FLT); -+} -+ -+static void sun8i_emac_tx_timeout(struct net_device *ndev) -+{ -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ -+ dev_info(priv->dev, "%s\n", __func__); -+ /* TODO reset/re-init all (see stmmac)*/ -+} -+ -+static int sun8i_emac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) -+{ -+ struct phy_device *phydev = ndev->phydev; -+ -+ if (!netif_running(ndev)) -+ return -EINVAL; -+ -+ if (!phydev) -+ return -ENODEV; -+ -+ return phy_mii_ioctl(phydev, rq, cmd); -+} -+ -+static int sun8i_emac_config(struct net_device *ndev, struct ifmap *map) -+{ -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ -+ dev_info(priv->dev, "%s\n", __func__); -+ return -EINVAL; -+} -+ -+static void sun8i_emac_poll_controller(struct net_device *ndev) -+{ -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ -+ dev_info(priv->dev, "%s\n", __func__); -+} -+ -+static int sun8i_emac_check_if_running(struct net_device *ndev) -+{ -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ -+ dev_info(priv->dev, "%s %d\n", __func__, netif_running(ndev)); -+ if (!netif_running(ndev)) -+ return -EBUSY; -+ return 0; -+} -+ -+static int sun8i_emac_get_sset_count(struct net_device *ndev, int sset) -+{ -+ int len; -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ -+ dev_info(priv->dev, "%s\n", __func__); -+ -+ switch (sset) { -+ case ETH_SS_STATS: -+ len = 0; -+ return len; -+ default: -+ return -EOPNOTSUPP; -+ } -+} -+ -+static int sun8i_emac_ethtool_get_settings(struct net_device *ndev, -+ struct ethtool_cmd *cmd) -+{ -+ struct phy_device *phy = ndev->phydev; -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ int rc; -+ -+ dev_info(priv->dev, "%s\n", __func__); -+ -+ if (!phy) { -+ netdev_err(ndev, "%s: %s: PHY is not registered\n", -+ __func__, ndev->name); -+ return -ENODEV; -+ } -+ -+ if (!netif_running(ndev)) { -+ dev_err(priv->dev, "interface disabled: we cannot track link speed / duplex setting\n"); -+ return -EBUSY; -+ } -+ -+ cmd->transceiver = XCVR_INTERNAL; -+ rc = phy_ethtool_gset(phy, cmd); -+ -+ return rc; -+} -+ -+static int sun8i_emac_ethtool_set_settings(struct net_device *ndev, -+ struct ethtool_cmd *cmd) -+{ -+ struct phy_device *phy = ndev->phydev; -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ int rc; -+ -+ dev_info(priv->dev, "%s\n", __func__); -+ -+ rc = phy_ethtool_sset(phy, cmd); -+ -+ return rc; -+} -+ -+static void sun8i_emac_ethtool_getdrvinfo(struct net_device *ndev, -+ struct ethtool_drvinfo *info) -+{ -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ -+ dev_info(priv->dev, "%s\n", __func__); -+ strlcpy(info->driver, "sun8i_emac", sizeof(info->driver)); -+ strcpy(info->version, "00"); -+ info->fw_version[0] = '\0'; -+} -+ -+static const struct ethtool_ops sun8i_emac_ethtool_ops = { -+ .begin = sun8i_emac_check_if_running, -+ .get_settings = sun8i_emac_ethtool_get_settings, -+ .set_settings = sun8i_emac_ethtool_set_settings, -+ .get_link = ethtool_op_get_link, -+ .get_pauseparam = NULL, -+ .set_pauseparam = NULL, -+ .get_ethtool_stats = NULL, -+ .get_strings = NULL, -+ .get_wol = NULL, -+ .set_wol = NULL, -+ .get_sset_count = sun8i_emac_get_sset_count, -+ .get_drvinfo = sun8i_emac_ethtool_getdrvinfo, -+}; -+ -+static const struct net_device_ops sun8i_emac_netdev_ops = { -+ .ndo_init = sun8i_emac_init, -+ .ndo_uninit = sun8i_emac_uninit, -+ .ndo_open = sun8i_emac_open, -+ .ndo_start_xmit = sun8i_emac_xmit, -+ .ndo_stop = sun8i_emac_stop, -+ .ndo_change_mtu = sun8i_emac_change_mtu, -+ .ndo_fix_features = sun8i_emac_fix_features, -+ .ndo_set_rx_mode = sun8i_emac_set_rx_mode, -+ .ndo_tx_timeout = sun8i_emac_tx_timeout, -+ .ndo_do_ioctl = sun8i_emac_ioctl, -+ .ndo_set_config = sun8i_emac_config, -+#ifdef CONFIG_NET_POLL_CONTROLLER -+ .ndo_poll_controller = sun8i_emac_poll_controller, -+#endif -+ .ndo_set_mac_address = sun8i_emac_set_mac_address, -+ .ndo_set_features = sun8i_emac_set_features, -+}; -+ -+static irqreturn_t sun8i_emac_dma_interrupt(int irq, void *dev_id) -+{ -+ struct net_device *ndev = (struct net_device *)dev_id; -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ u32 v, u; -+ -+ v = readl(priv->base + SUN8I_EMAC_INT_STA); -+ -+ #ifdef EMAC_DEBUG -+ dev_info(priv->dev, "%s %x\n", __func__, v); -+ #endif -+ -+ /* When this bit is asserted, a frame transmission is completed. */ -+ if (v & BIT(0)) -+ sun8i_emac_complete_xmit(ndev); -+ -+ /* When this bit is asserted, the TX DMA FSM is stopped. */ -+ if (v & BIT(1)) { -+ /* -+ u = readl(priv->base + SUN8I_EMAC_TX_CTL1); -+ #ifdef EMAC_DEBUG -+ dev_info(priv->dev, "Re-start TX DMA %x\n", u); -+ #endif -+ writel(u | BIT(31), priv->base + SUN8I_EMAC_TX_CTL1);*/ -+ priv->tx_dma_start = 0; -+ } -+ /* When this asserted, the TX DMA can not acquire next TX descriptor -+ * and TX DMA FSM is suspended. -+ */ -+ if (v & BIT(2)) { -+ /* -+ u = readl(priv->base + SUN8I_EMAC_TX_CTL1); -+ #ifdef EMAC_DEBUG -+ dev_info(priv->dev, "Re-run TX DMA %x\n", u); -+ #endif -+ writel(u | BIT(31), priv->base + SUN8I_EMAC_TX_CTL1);*/ -+ priv->tx_dma_start = 0; -+ } -+ -+ if (v & BIT(3)) -+ dev_info(priv->dev, "Unhandled interrupt TX TIMEOUT\n"); -+ if (v & BIT(4)) -+ dev_info(priv->dev, "Unhandled interrupt TX EARLY\n"); -+ -+ /* When this bit asserted , the frame is transmitted to FIFO totally. */ -+ #ifdef EMAC_DEBUG -+ if (v & BIT(5)) -+ dev_info(priv->dev, "Unhandled interrupt TX_EARLY_INT\n"); -+ #endif -+ -+ /* When this bit is asserted, a frame reception is completed */ -+ if (v & BIT(8)) -+ sun8i_emac_receive_all(ndev); -+ -+ /* When this asserted, the RX DMA can not acquire next TX descriptor -+ * and TX DMA FSM is suspended. -+ */ -+ if (v & BIT(9)) { -+ u = readl(priv->base + SUN8I_EMAC_RX_CTL1); -+ dev_info(priv->dev, "Re-run RX DMA %x\n", u); -+ writel(u | BIT(31), priv->base + SUN8I_EMAC_RX_CTL1); -+ } -+ -+ if (v & BIT(10)) -+ dev_info(priv->dev, "Unhandled interrupt RX_DMA_STOPPED_INT\n"); -+ if (v & BIT(11)) -+ dev_info(priv->dev, "Unhandled interrupt RX_TIMEOUT\n"); -+ if (v & BIT(12)) -+ dev_info(priv->dev, "Unhandled interrupt RX OVERFLOW\n"); -+ if (v & BIT(13)) -+ dev_info(priv->dev, "Unhandled interrupt RX EARLY\n"); -+ if (v & BIT(16)) -+ dev_info(priv->dev, "Unhandled interrupt RGMII\n"); -+ -+ writel(v & 0x3FFF, priv->base + SUN8I_EMAC_INT_STA); -+ -+ return IRQ_HANDLED; -+} -+ -+static int sun8i_emac_probe(struct platform_device *pdev) -+{ -+ struct resource *res; -+ struct sun8i_emac_priv *priv; -+ struct net_device *ndev; -+ int ret; -+ -+ ndev = alloc_etherdev(sizeof(*priv)); -+ if (!ndev) -+ return -ENOMEM; -+ -+ SET_NETDEV_DEV(ndev, &pdev->dev); -+ priv = netdev_priv(ndev); -+ platform_set_drvdata(pdev, ndev); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ priv->base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(priv->base)) { -+ ret = PTR_ERR(priv->base); -+ dev_err(&pdev->dev, "Cannot request MMIO: %d\n", ret); -+ goto probe_err; -+ } -+ -+ priv->irq = platform_get_irq(pdev, 0); -+ if (priv->irq < 0) { -+ ret = priv->irq; -+ dev_err(&pdev->dev, "Cannot claim IRQ: %d\n", ret); -+ goto probe_err; -+ } -+ -+ ret = devm_request_irq(&pdev->dev, priv->irq, sun8i_emac_dma_interrupt, -+ 0, dev_name(&pdev->dev), ndev); -+ if (ret) { -+ dev_err(&pdev->dev, "Cannot request IRQ: %d\n", ret); -+ goto probe_err; -+ } -+ -+ priv->ahb_clk = devm_clk_get(&pdev->dev, "bus_gmac"); -+ if (IS_ERR(priv->ahb_clk)) { -+ ret = PTR_ERR(priv->ahb_clk); -+ dev_err(&pdev->dev, "Cannot get AHB clock err=%d\n", ret); -+ goto probe_err; -+ } -+ -+ priv->rst = devm_reset_control_get_optional(&pdev->dev, "ahb"); -+ if (IS_ERR(priv->rst)) { -+ ret = PTR_ERR(priv->rst); -+ dev_info(&pdev->dev, "no mac reset control found %d\n", ret); -+ priv->rst = NULL; -+ } -+ -+ spin_lock_init(&priv->lock); -+ spin_lock_init(&priv->tx_lock); -+ -+ priv->tx_slot = 0; -+ -+ ndev->netdev_ops = &sun8i_emac_netdev_ops; -+ ndev->ethtool_ops = &sun8i_emac_ethtool_ops; -+ -+ priv->ndev = ndev; -+ priv->dev = &pdev->dev; -+ -+ ndev->base_addr = (unsigned long)priv->base; -+ ndev->irq = priv->irq; -+ -+ ndev->hw_features = NETIF_F_SG | NETIF_F_HIGHDMA; -+ ndev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM; -+ ndev->features |= ndev->hw_features; -+ ndev->hw_features |= NETIF_F_LOOPBACK; -+ ndev->priv_flags |= IFF_UNICAST_FLT; -+ -+ ndev->watchdog_timeo = msecs_to_jiffies(5000); -+ -+ ret = register_netdev(ndev); -+ if (ret) { -+ dev_err(&pdev->dev, "ERROR: Register %s failed\n", ndev->name); -+ goto probe_err; -+ } -+ -+ sun8i_emac_set_macaddr(priv, ndev->dev_addr, 0); -+ -+ return 0; -+probe_err: -+ free_netdev(ndev); -+ return ret; -+} -+ -+static int sun8i_emac_remove(struct platform_device *pdev) -+{ -+ struct net_device *ndev = platform_get_drvdata(pdev); -+ struct sun8i_emac_priv *priv = netdev_priv(ndev); -+ -+ clk_disable_unprepare(priv->tx_clk); -+ if (priv->rst_phy) -+ reset_control_assert(priv->rst_phy); -+ -+ unregister_netdev(ndev); -+ platform_set_drvdata(pdev, NULL); -+ free_netdev(ndev); -+ return 0; -+} -+ -+static const struct of_device_id sun8i_emac_of_match_table[] = { -+ { .compatible = "allwinner,sun8i-h3-emac" }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, sun8i_emac_of_match_table); -+ -+static struct platform_driver sun8i_emac_driver = { -+ .probe = sun8i_emac_probe, -+ .remove = sun8i_emac_remove, -+ .driver = { -+ .name = "sun8i-emac", -+ .of_match_table = sun8i_emac_of_match_table, -+ }, -+}; -+ -+module_platform_driver(sun8i_emac_driver); -+ -+MODULE_DESCRIPTION("SUN8I Ethernet driver"); -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("LABBE Corentin /sys/class/leds/green_led/trigger - echo 200 >/sys/class/leds/green_led/delay_off - echo 200 >/sys/class/leds/green_led/delay_on + if [ -f "X${SwapState}" != "X" ]; then + echo heartbeat >/sys/class/leds/*green*/trigger [ -f "/root/.not_logged_in_yet" ] && BlinkTime=120 || BlinkTime=10 - (sleep ${BlinkTime} && echo default-on >/sys/class/leds/green_led/trigger) & + (sleep ${BlinkTime} && echo default-on >/sys/class/leds/*green*/trigger) & fi # redistribute USB irqs to dedicated cores @@ -319,7 +318,7 @@ case $1 in collect_informations if [ $HARDWARE = "sun8i" ]; then # redefine green led to blink until shutdown - echo heartbeat >/sys/class/leds/green_led/trigger + echo heartbeat >/sys/class/leds/*green*/trigger fi ;; esac diff --git a/scripts/firstrun b/scripts/firstrun index 526bf5c2b..09af97323 100644 --- a/scripts/firstrun +++ b/scripts/firstrun @@ -114,11 +114,7 @@ autodetect_sunxi() { # kernel [[ -f /proc/device-tree/model ]] # trigger red or blue LED as user feedback - if [ -f /sys/class/leds/red_led/trigger ]; then - echo heartbeat >/sys/class/leds/red_led/trigger - elif [ -f /sys/class/leds/blue_led/trigger ]; then - echo heartbeat >/sys/class/leds/blue_led/trigger - fi + echo heartbeat >/sys/class/leds/*red*/trigger 2>/dev/null || echo heartbeat >/sys/class/leds/*blue*/trigger 2>/dev/null # wait for armhwinfo sleep 3