From 96fb5f51a443b2087dee6de92db05bd665233af0 Mon Sep 17 00:00:00 2001 From: Martin Ayotte Date: Tue, 24 Jan 2017 16:21:57 -0500 Subject: [PATCH] add mtd-spi-nor+large transfer to pine64-dev and sun50iw2-dev --- .../pine64-dev/add-mtd-spi-nor-dts.patch | 37 ++++ .../add_BergMicro_flashes_to_SPI-NOR.patch | 18 ++ .../spi-sun6i-allow-large-transfers.patch | 201 ++++++++++++++++++ .../add_BergMicro_flashes_to_SPI-NOR.patch | 18 ++ .../spi-sun6i-allow-large-transfers.patch | 201 ++++++++++++++++++ 5 files changed, 475 insertions(+) create mode 100644 patch/kernel/pine64-dev/add-mtd-spi-nor-dts.patch create mode 100644 patch/kernel/pine64-dev/add_BergMicro_flashes_to_SPI-NOR.patch create mode 100644 patch/kernel/pine64-dev/spi-sun6i-allow-large-transfers.patch create mode 100644 patch/kernel/sun50iw2-dev/add_BergMicro_flashes_to_SPI-NOR.patch create mode 100644 patch/kernel/sun50iw2-dev/spi-sun6i-allow-large-transfers.patch diff --git a/patch/kernel/pine64-dev/add-mtd-spi-nor-dts.patch b/patch/kernel/pine64-dev/add-mtd-spi-nor-dts.patch new file mode 100644 index 000000000..964255e7c --- /dev/null +++ b/patch/kernel/pine64-dev/add-mtd-spi-nor-dts.patch @@ -0,0 +1,37 @@ +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +index 7161b06..66b8fa7 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +@@ -124,3 +124,32 @@ + allwinner,leds-active-low; + status = "okay"; + }; ++ ++&spi0 { ++ status = "okay"; ++ spi-flash@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "jedec,spi-nor"; ++ reg = <0>; /* Chip select 0 */ ++ spi-max-frequency = <10000000>; ++ status = "okay"; ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ partition@0 { ++ label = "uboot"; ++ reg = <0x0 0x100000>; ++ }; ++ partition@100000 { ++ label = "env"; ++ reg = <0x100000 0x100000>; ++ }; ++ partition@200000 { ++ label = "data"; ++ reg = <0x200000 0x200000>; ++ }; ++ }; ++ }; ++}; diff --git a/patch/kernel/pine64-dev/add_BergMicro_flashes_to_SPI-NOR.patch b/patch/kernel/pine64-dev/add_BergMicro_flashes_to_SPI-NOR.patch new file mode 100644 index 000000000..87d97f508 --- /dev/null +++ b/patch/kernel/pine64-dev/add_BergMicro_flashes_to_SPI-NOR.patch @@ -0,0 +1,18 @@ +diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c +index d0fc165..4510c2d 100644 +--- a/drivers/mtd/spi-nor/spi-nor.c ++++ b/drivers/mtd/spi-nor/spi-nor.c +@@ -809,6 +809,13 @@ static const struct flash_info spi_nor_ids[] = { + + { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, + ++ /* BergMicro Flashes */ ++ { "bg25q80", INFO(0xe04014, 0, 64 * 1024, 16, SECT_4K) }, ++ { "bg25q16", INFO(0xe04015, 0, 64 * 1024, 32, SECT_4K) }, ++ { "bg25q32", INFO(0xe04016, 0, 64 * 1024, 64, SECT_4K) }, ++ { "bg25q64", INFO(0xe04017, 0, 64 * 1024, 128, SECT_4K) }, ++ { "bg25q128", INFO(0xe04018, 0, 64 * 1024, 256, SECT_4K) }, ++ + /* EON -- en25xxx */ + { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) }, + { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) }, diff --git a/patch/kernel/pine64-dev/spi-sun6i-allow-large-transfers.patch b/patch/kernel/pine64-dev/spi-sun6i-allow-large-transfers.patch new file mode 100644 index 000000000..7747b74c8 --- /dev/null +++ b/patch/kernel/pine64-dev/spi-sun6i-allow-large-transfers.patch @@ -0,0 +1,201 @@ +diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c +index 9918a57..64be5aa 100644 +--- a/drivers/spi/spi-sun6i.c ++++ b/drivers/spi/spi-sun6i.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -24,6 +25,7 @@ + #include + + #define SUN6I_FIFO_DEPTH 128 ++#define SUN8I_FIFO_DEPTH 64 + + #define SUN6I_GBL_CTL_REG 0x04 + #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0) +@@ -44,6 +46,8 @@ + #define SUN6I_TFR_CTL_XCH BIT(31) + + #define SUN6I_INT_CTL_REG 0x10 ++#define SUN6I_INT_CTL_RF_FUL BIT(2) ++#define SUN6I_INT_CTL_TF_EMP BIT(5) + #define SUN6I_INT_CTL_RF_OVF BIT(8) + #define SUN6I_INT_CTL_TC BIT(12) + +@@ -66,11 +70,13 @@ + #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8) + #define SUN6I_CLK_CTL_DRS BIT(12) + ++#define SUN6I_MAX_XFER_SIZE 0xffffff ++ + #define SUN6I_BURST_CNT_REG 0x30 +-#define SUN6I_BURST_CNT(cnt) ((cnt) & 0xffffff) ++#define SUN6I_BURST_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE) + + #define SUN6I_XMIT_CNT_REG 0x34 +-#define SUN6I_XMIT_CNT(cnt) ((cnt) & 0xffffff) ++#define SUN6I_XMIT_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE) + + #define SUN6I_BURST_CTL_CNT_REG 0x38 + #define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & 0xffffff) +@@ -90,6 +96,7 @@ struct sun6i_spi { + const u8 *tx_buf; + u8 *rx_buf; + int len; ++ unsigned long fifo_depth; + }; + + static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg) +@@ -102,6 +109,31 @@ static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value) + writel(value, sspi->base_addr + reg); + } + ++static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi) ++{ ++ u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); ++ ++ reg >>= SUN6I_FIFO_STA_TF_CNT_BITS; ++ ++ return reg & SUN6I_FIFO_STA_TF_CNT_MASK; ++} ++ ++static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask) ++{ ++ u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); ++ ++ reg |= mask; ++ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); ++} ++ ++static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask) ++{ ++ u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); ++ ++ reg &= ~mask; ++ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); ++} ++ + static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len) + { + u32 reg, cnt; +@@ -124,10 +156,13 @@ static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len) + + static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len) + { ++ u32 cnt; + u8 byte; + +- if (len > sspi->len) +- len = sspi->len; ++ /* See how much data we can fit */ ++ cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi); ++ ++ len = min3(len, (int)cnt, sspi->len); + + while (len--) { + byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; +@@ -155,7 +190,7 @@ static void sun6i_spi_set_cs(struct spi_device *spi, bool enable) + + static size_t sun6i_spi_max_transfer_size(struct spi_device *spi) + { +- return SUN6I_FIFO_DEPTH - 1; ++ return SUN6I_MAX_XFER_SIZE - 1; + } + + static int sun6i_spi_transfer_one(struct spi_master *master, +@@ -169,8 +204,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master, + int ret = 0; + u32 reg; + +- /* We don't support transfer larger than the FIFO */ +- if (tfr->len > SUN6I_FIFO_DEPTH) ++ if (tfr->len > SUN6I_MAX_XFER_SIZE) + return -EINVAL; + + reinit_completion(&sspi->done); +@@ -265,10 +299,16 @@ static int sun6i_spi_transfer_one(struct spi_master *master, + SUN6I_BURST_CTL_CNT_STC(tx_len)); + + /* Fill the TX FIFO */ +- sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH); ++ sun6i_spi_fill_fifo(sspi, sspi->fifo_depth); + + /* Enable the interrupts */ +- sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC); ++ /* Only enable Tx FIFO interrupt if we really need it */ ++ if (tx_len > sspi->fifo_depth) ++ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, ++ SUN6I_INT_CTL_TC | SUN6I_INT_CTL_RF_FUL | SUN6I_INT_CTL_TF_EMP); ++ else ++ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, ++ SUN6I_INT_CTL_TC | SUN6I_INT_CTL_RF_FUL); + + /* Start the transfer */ + reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); +@@ -288,8 +328,6 @@ static int sun6i_spi_transfer_one(struct spi_master *master, + goto out; + } + +- sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH); +- + out: + sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0); + +@@ -304,10 +342,33 @@ static irqreturn_t sun6i_spi_handler(int irq, void *dev_id) + /* Transfer complete */ + if (status & SUN6I_INT_CTL_TC) { + sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC); ++ sun6i_spi_drain_fifo(sspi, sspi->fifo_depth); + complete(&sspi->done); + return IRQ_HANDLED; + } + ++ /* Receive FIFO Full */ ++ if (status & SUN6I_INT_CTL_RF_FUL) { ++ sun6i_spi_drain_fifo(sspi, sspi->fifo_depth); ++ /* Only clear the interrupt _after_ draining the FIFO */ ++ sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_FUL); ++ return IRQ_HANDLED; ++ } ++ ++ /* Transmit FIFO Empty */ ++ if (status & SUN6I_INT_CTL_TF_EMP) { ++ sun6i_spi_fill_fifo(sspi, sspi->fifo_depth); ++ ++ if (!sspi->len) ++ /* nothing left to transmit */ ++ sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_EMP); ++ ++ /* Only clear the interrupt _after_ re-seeding the FIFO */ ++ sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_EMP); ++ ++ return IRQ_HANDLED; ++ } ++ + return IRQ_NONE; + } + +@@ -398,6 +459,8 @@ static int sun6i_spi_probe(struct platform_device *pdev) + } + + sspi->master = master; ++ sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev); ++ + master->max_speed_hz = 100 * 1000 * 1000; + master->min_speed_hz = 3 * 1000; + master->set_cs = sun6i_spi_set_cs; +@@ -470,7 +533,8 @@ static int sun6i_spi_remove(struct platform_device *pdev) + } + + static const struct of_device_id sun6i_spi_match[] = { +- { .compatible = "allwinner,sun6i-a31-spi", }, ++ { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH }, ++ { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH }, + {} + }; + MODULE_DEVICE_TABLE(of, sun6i_spi_match); diff --git a/patch/kernel/sun50iw2-dev/add_BergMicro_flashes_to_SPI-NOR.patch b/patch/kernel/sun50iw2-dev/add_BergMicro_flashes_to_SPI-NOR.patch new file mode 100644 index 000000000..87d97f508 --- /dev/null +++ b/patch/kernel/sun50iw2-dev/add_BergMicro_flashes_to_SPI-NOR.patch @@ -0,0 +1,18 @@ +diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c +index d0fc165..4510c2d 100644 +--- a/drivers/mtd/spi-nor/spi-nor.c ++++ b/drivers/mtd/spi-nor/spi-nor.c +@@ -809,6 +809,13 @@ static const struct flash_info spi_nor_ids[] = { + + { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, + ++ /* BergMicro Flashes */ ++ { "bg25q80", INFO(0xe04014, 0, 64 * 1024, 16, SECT_4K) }, ++ { "bg25q16", INFO(0xe04015, 0, 64 * 1024, 32, SECT_4K) }, ++ { "bg25q32", INFO(0xe04016, 0, 64 * 1024, 64, SECT_4K) }, ++ { "bg25q64", INFO(0xe04017, 0, 64 * 1024, 128, SECT_4K) }, ++ { "bg25q128", INFO(0xe04018, 0, 64 * 1024, 256, SECT_4K) }, ++ + /* EON -- en25xxx */ + { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) }, + { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) }, diff --git a/patch/kernel/sun50iw2-dev/spi-sun6i-allow-large-transfers.patch b/patch/kernel/sun50iw2-dev/spi-sun6i-allow-large-transfers.patch new file mode 100644 index 000000000..7747b74c8 --- /dev/null +++ b/patch/kernel/sun50iw2-dev/spi-sun6i-allow-large-transfers.patch @@ -0,0 +1,201 @@ +diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c +index 9918a57..64be5aa 100644 +--- a/drivers/spi/spi-sun6i.c ++++ b/drivers/spi/spi-sun6i.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -24,6 +25,7 @@ + #include + + #define SUN6I_FIFO_DEPTH 128 ++#define SUN8I_FIFO_DEPTH 64 + + #define SUN6I_GBL_CTL_REG 0x04 + #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0) +@@ -44,6 +46,8 @@ + #define SUN6I_TFR_CTL_XCH BIT(31) + + #define SUN6I_INT_CTL_REG 0x10 ++#define SUN6I_INT_CTL_RF_FUL BIT(2) ++#define SUN6I_INT_CTL_TF_EMP BIT(5) + #define SUN6I_INT_CTL_RF_OVF BIT(8) + #define SUN6I_INT_CTL_TC BIT(12) + +@@ -66,11 +70,13 @@ + #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8) + #define SUN6I_CLK_CTL_DRS BIT(12) + ++#define SUN6I_MAX_XFER_SIZE 0xffffff ++ + #define SUN6I_BURST_CNT_REG 0x30 +-#define SUN6I_BURST_CNT(cnt) ((cnt) & 0xffffff) ++#define SUN6I_BURST_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE) + + #define SUN6I_XMIT_CNT_REG 0x34 +-#define SUN6I_XMIT_CNT(cnt) ((cnt) & 0xffffff) ++#define SUN6I_XMIT_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE) + + #define SUN6I_BURST_CTL_CNT_REG 0x38 + #define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & 0xffffff) +@@ -90,6 +96,7 @@ struct sun6i_spi { + const u8 *tx_buf; + u8 *rx_buf; + int len; ++ unsigned long fifo_depth; + }; + + static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg) +@@ -102,6 +109,31 @@ static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value) + writel(value, sspi->base_addr + reg); + } + ++static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi) ++{ ++ u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); ++ ++ reg >>= SUN6I_FIFO_STA_TF_CNT_BITS; ++ ++ return reg & SUN6I_FIFO_STA_TF_CNT_MASK; ++} ++ ++static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask) ++{ ++ u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); ++ ++ reg |= mask; ++ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); ++} ++ ++static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask) ++{ ++ u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); ++ ++ reg &= ~mask; ++ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); ++} ++ + static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len) + { + u32 reg, cnt; +@@ -124,10 +156,13 @@ static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len) + + static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len) + { ++ u32 cnt; + u8 byte; + +- if (len > sspi->len) +- len = sspi->len; ++ /* See how much data we can fit */ ++ cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi); ++ ++ len = min3(len, (int)cnt, sspi->len); + + while (len--) { + byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; +@@ -155,7 +190,7 @@ static void sun6i_spi_set_cs(struct spi_device *spi, bool enable) + + static size_t sun6i_spi_max_transfer_size(struct spi_device *spi) + { +- return SUN6I_FIFO_DEPTH - 1; ++ return SUN6I_MAX_XFER_SIZE - 1; + } + + static int sun6i_spi_transfer_one(struct spi_master *master, +@@ -169,8 +204,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master, + int ret = 0; + u32 reg; + +- /* We don't support transfer larger than the FIFO */ +- if (tfr->len > SUN6I_FIFO_DEPTH) ++ if (tfr->len > SUN6I_MAX_XFER_SIZE) + return -EINVAL; + + reinit_completion(&sspi->done); +@@ -265,10 +299,16 @@ static int sun6i_spi_transfer_one(struct spi_master *master, + SUN6I_BURST_CTL_CNT_STC(tx_len)); + + /* Fill the TX FIFO */ +- sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH); ++ sun6i_spi_fill_fifo(sspi, sspi->fifo_depth); + + /* Enable the interrupts */ +- sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC); ++ /* Only enable Tx FIFO interrupt if we really need it */ ++ if (tx_len > sspi->fifo_depth) ++ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, ++ SUN6I_INT_CTL_TC | SUN6I_INT_CTL_RF_FUL | SUN6I_INT_CTL_TF_EMP); ++ else ++ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, ++ SUN6I_INT_CTL_TC | SUN6I_INT_CTL_RF_FUL); + + /* Start the transfer */ + reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); +@@ -288,8 +328,6 @@ static int sun6i_spi_transfer_one(struct spi_master *master, + goto out; + } + +- sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH); +- + out: + sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0); + +@@ -304,10 +342,33 @@ static irqreturn_t sun6i_spi_handler(int irq, void *dev_id) + /* Transfer complete */ + if (status & SUN6I_INT_CTL_TC) { + sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC); ++ sun6i_spi_drain_fifo(sspi, sspi->fifo_depth); + complete(&sspi->done); + return IRQ_HANDLED; + } + ++ /* Receive FIFO Full */ ++ if (status & SUN6I_INT_CTL_RF_FUL) { ++ sun6i_spi_drain_fifo(sspi, sspi->fifo_depth); ++ /* Only clear the interrupt _after_ draining the FIFO */ ++ sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_FUL); ++ return IRQ_HANDLED; ++ } ++ ++ /* Transmit FIFO Empty */ ++ if (status & SUN6I_INT_CTL_TF_EMP) { ++ sun6i_spi_fill_fifo(sspi, sspi->fifo_depth); ++ ++ if (!sspi->len) ++ /* nothing left to transmit */ ++ sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_EMP); ++ ++ /* Only clear the interrupt _after_ re-seeding the FIFO */ ++ sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_EMP); ++ ++ return IRQ_HANDLED; ++ } ++ + return IRQ_NONE; + } + +@@ -398,6 +459,8 @@ static int sun6i_spi_probe(struct platform_device *pdev) + } + + sspi->master = master; ++ sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev); ++ + master->max_speed_hz = 100 * 1000 * 1000; + master->min_speed_hz = 3 * 1000; + master->set_cs = sun6i_spi_set_cs; +@@ -470,7 +533,8 @@ static int sun6i_spi_remove(struct platform_device *pdev) + } + + static const struct of_device_id sun6i_spi_match[] = { +- { .compatible = "allwinner,sun6i-a31-spi", }, ++ { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH }, ++ { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH }, + {} + }; + MODULE_DEVICE_TABLE(of, sun6i_spi_match);