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Rockchip Next to 4.14.y

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This commit is contained in:
root 2017-11-28 23:17:20 -05:00
parent eab890e9c6
commit a50100eb1e
104 changed files with 5403 additions and 1042509 deletions
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631
config/kernel/linux-rockchip-next.config
View file

File diff suppressed because it is too large Load diff

2
config/sources/rockchip.conf
View file

@ -23,7 +23,7 @@ case $BRANCH in
next)
KERNELSOURCE=$MAINLINE_KERNEL_SOURCE
KERNELBRANCH='branch:linux-4.13.y'
KERNELBRANCH='branch:linux-4.14.y'
KERNELDIR=$MAINLINE_KERNEL_DIR
;;

122
patch/kernel/rockchip-dev/0001-Mali-midgard-r19p0-fixes-for-4.13-kernels.patch
View file

@ -1,122 +0,0 @@
From 7ba71967a2678e119bcd819ac92d08bd038e1879 Mon Sep 17 00:00:00 2001
From: Myy <myy@miouyouyou.fr>
Date: Mon, 17 Jul 2017 18:34:33 +0000
Subject: [PATCH 5/5] Mali midgard r19p0 fixes for 4.13 kernels
Mostly due to DMA structure members renamed, and some signatures
modifications done during the development of Linux 4.11.
* mm, fs: reduce fault, page_mkwrite, and pfn_mkwrite to take only vmf
11bac80004499ea59f361ef2a5516c84b6eab675
v4.11-rc1
* sched/headers: Move task->mm handling methods to <linux/sched/mm.h>
68e21be2916b359fd8afb536c1911dc014cfd03e
v4.11-rc1
* sched/headers: Move task-stack related APIs from <linux/sched.h> to
<linux/sched/task_stack.h>
f3ac60671954c8d413532627b1be13a76f394c49
v4.11-rc1
* dma-fence: Introduce drm_fence_set_error() helper
a009e975da5c7d42a7f5eaadc54946eb5f76c9af
v4.11-rc1
Signed-off-by: Myy <myy@miouyouyou.fr>
---
drivers/gpu/arm/midgard/mali_kbase.h | 4 ++++
drivers/gpu/arm/midgard/mali_kbase_fence.h | 4 ++++
drivers/gpu/arm/midgard/mali_kbase_mem_linux.c | 6 ++++++
drivers/gpu/arm/midgard/mali_kbase_sync_file.c | 12 ++++++++++++
4 files changed, 26 insertions(+)
diff --git a/drivers/gpu/arm/midgard/mali_kbase.h b/drivers/gpu/arm/midgard/mali_kbase.h
index d77f186..5ee47c4 100644
--- a/drivers/gpu/arm/midgard/mali_kbase.h
+++ b/drivers/gpu/arm/midgard/mali_kbase.h
@@ -35,6 +35,10 @@
#include <linux/mutex.h>
#include <linux/rwsem.h>
#include <linux/sched.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)
+#include <linux/sched/task_stack.h>
+#include <linux/sched/mm.h>
+#endif
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/vmalloc.h>
diff --git a/drivers/gpu/arm/midgard/mali_kbase_fence.h b/drivers/gpu/arm/midgard/mali_kbase_fence.h
index 8d39299..3c2e3a9 100644
--- a/drivers/gpu/arm/midgard/mali_kbase_fence.h
+++ b/drivers/gpu/arm/midgard/mali_kbase_fence.h
@@ -134,7 +134,11 @@ static inline bool kbase_fence_out_is_ours(struct kbase_jd_atom *katom)
static inline int kbase_fence_out_signal(struct kbase_jd_atom *katom,
int status)
{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 11, 0))
katom->dma_fence.fence->status = status;
+#else
+ katom->dma_fence.fence->error = status;
+#endif
return dma_fence_signal(katom->dma_fence.fence);
}
diff --git a/drivers/gpu/arm/midgard/mali_kbase_mem_linux.c b/drivers/gpu/arm/midgard/mali_kbase_mem_linux.c
index b1f2c46..896aa35 100644
--- a/drivers/gpu/arm/midgard/mali_kbase_mem_linux.c
+++ b/drivers/gpu/arm/midgard/mali_kbase_mem_linux.c
@@ -1788,8 +1788,14 @@ static void kbase_cpu_vm_close(struct vm_area_struct *vma)
KBASE_EXPORT_TEST_API(kbase_cpu_vm_close);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 11, 0))
static int kbase_cpu_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
{
+#else
+static int kbase_cpu_vm_fault(struct vm_fault *vmf)
+{
+ struct vm_area_struct *vma = vmf->vma;
+#endif
struct kbase_cpu_mapping *map = vma->vm_private_data;
pgoff_t rel_pgoff;
size_t i;
diff --git a/drivers/gpu/arm/midgard/mali_kbase_sync_file.c b/drivers/gpu/arm/midgard/mali_kbase_sync_file.c
index 4e1621c..d84a54e 100644
--- a/drivers/gpu/arm/midgard/mali_kbase_sync_file.c
+++ b/drivers/gpu/arm/midgard/mali_kbase_sync_file.c
@@ -161,8 +161,13 @@ static void kbase_fence_wait_callback(struct dma_fence *fence,
struct kbase_context *kctx = katom->kctx;
/* Cancel atom if fence is erroneous */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 11, 0))
if (dma_fence_is_signaled(kcb->fence) && kcb->fence->status < 0)
katom->event_code = BASE_JD_EVENT_JOB_CANCELLED;
+#else
+ if (dma_fence_is_signaled(kcb->fence) && kcb->fence->error < 0)
+ katom->event_code = BASE_JD_EVENT_JOB_CANCELLED;
+#endif
if (kbase_fence_dep_count_dec_and_test(katom)) {
/* We take responsibility of handling this */
@@ -273,10 +278,17 @@ static void kbase_sync_fence_info_get(struct dma_fence *fence,
* 1 : signaled
*/
if (dma_fence_is_signaled(fence)) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 11, 0))
if (fence->status < 0)
info->status = fence->status; /* signaled with error */
else
info->status = 1; /* signaled with success */
+#else
+ if (fence->error < 0)
+ info->status = fence->error; /* signaled with error */
+ else
+ info->status = 1; /* signaled with success */
+#endif
} else {
info->status = 0; /* still active (unsignaled) */
}
--
2.10.2

38
patch/kernel/rockchip-dev/0001-midgard-mali_kbase-include-linux-sched-task_stack.h.patch Normal file
View file

@ -0,0 +1,38 @@
From ac8315518f935e75692ac04b2f999d481db0a8e1 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@mioiuyouyou.fr>
Date: Thu, 19 Oct 2017 21:00:12 +0200
Subject: [PATCH 03/28] midgard: mali_kbase: include <linux/sched/task_stack.h>
It seems that most of the old patches are not required anymore.
Except this one :
* sched/headers: Move task-stack related APIs from <linux/sched.h> to
<linux/sched/task_stack.h>
f3ac60671954c8d413532627b1be13a76f394c49
v4.11-rc1
Since this include can be guarded with #if #endif clauses, I don't
know they were not included in the r20p0 version...
Well.
Signed-off-by: Myy Miouyouyou <myy@mioiuyouyou.fr>
---
drivers/gpu/arm/midgard/mali_kbase.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/arm/midgard/mali_kbase.h b/drivers/gpu/arm/midgard/mali_kbase.h
index 56b364e5..9dd547f2 100644
--- a/drivers/gpu/arm/midgard/mali_kbase.h
+++ b/drivers/gpu/arm/midgard/mali_kbase.h
@@ -36,6 +36,7 @@
#include <linux/rwsem.h>
#include <linux/sched.h>
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0))
+#include <linux/sched/task_stack.h>
#include <linux/sched/mm.h>
#endif
#include <linux/slab.h>
--
2.11.0

0
patch/kernel/rockchip-dev/1003-clk-rockchip-add-all-known-operating-points-to-the-a.patch → patch/kernel/rockchip-dev/1002-clk-rockchip-add-all-known-operating-points-to-the-a.patch
View file

167
patch/kernel/rockchip-dev/1002-fbdev-Mali-Add-the-FBIOGET_DMABUF-interface.patch
View file

@ -1,167 +0,0 @@
From 66c5bb20f8dd389496c40635625ae1132cdc686f Mon Sep 17 00:00:00 2001
From: Myy <myy@miouyouyou.fr>
Date: Sun, 30 Jul 2017 17:01:33 +0000
Subject: [PATCH 1/9] fbdev: Mali: Add the FBIOGET_DMABUF interface
I don't know if this interface is still useful. FBDEV will soon be
FBDEAD, since everyone is switching, for valid reasons, to the DRM
and Kernel Mode Setting interface.
This was added because the Mali FBDEV drivers need this interface.
Since the Mali FBDEV drivers are the only one that are Vulkan
compatible on RK3288 boards, I'm keeping it for the moment.
So this will stay until it can't be applied anymore. At the moment,
this patch will be removed.
Details about that interface can be found here :
https://www.community.arm.com/graphics/b/blog/posts/improving-arm-mali-drivers-on-fbdev
Signed-off-by: Myy <myy@miouyouyou.fr>
---
drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c | 21 ++++++++++++++++++
drivers/video/fbdev/core/fbmem.c | 31 +++++++++++++++++++++++++++
include/linux/fb.h | 2 ++
include/uapi/linux/fb.h | 6 ++++++
4 files changed, 60 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c
index ce946b9c..d63d0475 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c
@@ -35,6 +35,26 @@ static int rockchip_fbdev_mmap(struct fb_info *info,
return rockchip_gem_mmap_buf(private->fbdev_bo, vma);
}
+/* Mali driver specific API :
+ https://www.community.arm.com/graphics/b/blog/posts/improving-arm-mali-drivers-on-fbdev
+ I wonder if this problem isn't already solved in another way...
+ */
+static struct dma_buf *rockchip_fbdev_get_dma_buf(struct fb_info *info) {
+ struct dma_buf *buf = NULL;
+ struct drm_fb_helper *helper = info->par;
+ struct rockchip_drm_private *private = to_drm_private(helper);
+ struct drm_device *dev = helper->dev;
+
+ if (dev->driver->gem_prime_export) {
+ buf = dev->driver->gem_prime_export(dev, private->fbdev_bo, O_RDWR);
+ if (buf)
+ drm_gem_object_reference(private->fbdev_bo);
+ }
+
+ return buf;
+}
+
+
static struct fb_ops rockchip_drm_fbdev_ops = {
.owner = THIS_MODULE,
DRM_FB_HELPER_DEFAULT_OPS,
@@ -42,6 +62,7 @@ static struct fb_ops rockchip_drm_fbdev_ops = {
.fb_fillrect = drm_fb_helper_cfb_fillrect,
.fb_copyarea = drm_fb_helper_cfb_copyarea,
.fb_imageblit = drm_fb_helper_cfb_imageblit,
+ .fb_dmabuf_export = rockchip_fbdev_get_dma_buf
};
static int rockchip_drm_fbdev_create(struct drm_fb_helper *helper,
diff --git a/drivers/video/fbdev/core/fbmem.c b/drivers/video/fbdev/core/fbmem.c
index 7a42238d..61d1f3f8 100644
--- a/drivers/video/fbdev/core/fbmem.c
+++ b/drivers/video/fbdev/core/fbmem.c
@@ -31,6 +31,7 @@
#include <linux/err.h>
#include <linux/device.h>
#include <linux/efi.h>
+#include <linux/dma-buf.h> // Mali specific
#include <linux/fb.h>
#include <asm/fb.h>
@@ -1084,6 +1085,21 @@ fb_blank(struct fb_info *info, int blank)
}
EXPORT_SYMBOL(fb_blank);
+/* Mali specific */
+int fb_get_dmabuf(struct fb_info *info, int flags)
+{
+ struct dma_buf *dmabuf;
+
+ if (info->fbops->fb_dmabuf_export == NULL)
+ return -ENOTTY;
+
+ dmabuf = info->fbops->fb_dmabuf_export(info);
+ if (IS_ERR(dmabuf))
+ return PTR_ERR(dmabuf);
+
+ return dma_buf_fd(dmabuf, flags);
+}
+
static long do_fb_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
@@ -1094,6 +1110,7 @@ static long do_fb_ioctl(struct fb_info *info, unsigned int cmd,
struct fb_cmap cmap_from;
struct fb_cmap_user cmap;
struct fb_event event;
+ struct fb_dmabuf_export dmaexp;
void __user *argp = (void __user *)arg;
long ret = 0;
@@ -1199,6 +1216,20 @@ static long do_fb_ioctl(struct fb_info *info, unsigned int cmd,
unlock_fb_info(info);
console_unlock();
break;
+ case FBIOGET_DMABUF: /* Mali specific */
+ if (copy_from_user(&dmaexp, argp, sizeof(dmaexp)))
+ return -EFAULT;
+ if (!lock_fb_info(info))
+ return -ENODEV;
+ dmaexp.fd = fb_get_dmabuf(info, dmaexp.flags);
+ unlock_fb_info(info);
+
+ if (dmaexp.fd < 0)
+ return dmaexp.fd;
+
+ ret = copy_to_user(argp, &dmaexp, sizeof(dmaexp))
+ ? -EFAULT : 0;
+ break;
case FBIOBLANK:
console_lock();
if (!lock_fb_info(info)) {
diff --git a/include/linux/fb.h b/include/linux/fb.h
index a964d076..37a52dbb 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -320,6 +320,8 @@ struct fb_ops {
/* called at KDB enter and leave time to prepare the console */
int (*fb_debug_enter)(struct fb_info *info);
int (*fb_debug_leave)(struct fb_info *info);
+
+ struct dma_buf *(*fb_dmabuf_export)(struct fb_info *info);
};
#ifdef CONFIG_FB_TILEBLITTING
diff --git a/include/uapi/linux/fb.h b/include/uapi/linux/fb.h
index fb795c3b..c279b045 100644
--- a/include/uapi/linux/fb.h
+++ b/include/uapi/linux/fb.h
@@ -34,6 +34,8 @@
#define FBIOPUT_MODEINFO 0x4617
#define FBIOGET_DISPINFO 0x4618
#define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
+/* Mali specific */
+#define FBIOGET_DMABUF _IOR('F', 0x21, struct fb_dmabuf_export)
#define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */
#define FB_TYPE_PLANES 1 /* Non interleaved planes */
@@ -398,5 +400,9 @@ struct fb_cursor {
#define FB_BACKLIGHT_MAX 0xFF
#endif
+struct fb_dmabuf_export { /* Mali specific */
+ __u32 fd;
+ __u32 flags;
+};
#endif /* _UAPI_LINUX_FB_H */
--
2.13.0

0
patch/kernel/rockchip-dev/1004-clk-rockchip-rk3288-prefer-vdpu-for-vcodec-clock-sou.patch → patch/kernel/rockchip-dev/1003-clk-rockchip-rk3288-prefer-vdpu-for-vcodec-clock-sou.patch
View file

0
patch/kernel/rockchip-dev/1005-Remove-the-dependency-to-the-clk_mali-symbol.patch → patch/kernel/rockchip-dev/1004-Remove-the-dependency-to-the-clk_mali-symbol.patch
View file

82
patch/kernel/rockchip-next/9300_Tinker_Reboot_Hacks.patch → patch/kernel/rockchip-dev/1005-Reboot-patch-2-The-Return.patch
View file

@ -1,21 +1,36 @@
From 1aeeeeaf10ad5888c1a5b3ab9b780be91c7dada9 Mon Sep 17 00:00:00 2001
From: Myy <myy@miouyouyou.fr>
Date: Mon, 24 Jul 2017 23:09:31 +0000
Subject: [PATCH] Last try for the reboot hack
If this one does not work, get a refund for your CantRebootBoard.
Signed-off-by: Myy <myy@miouyouyou.fr>
---
drivers/mmc/host/dw_mmc-rockchip.c | 24 ++++++++++++++++++++++++
drivers/mmc/host/dw_mmc.c | 26 ++++++++++++++++++++++++++
include/linux/reboot.h | 3 +++
kernel/reboot.c | 1 +
4 files changed, 54 insertions(+)
diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c
index 372fb6e..a54c290 100644
index aaed6f9b..71131020 100644
--- a/drivers/mmc/host/dw_mmc-rockchip.c
+++ b/drivers/mmc/host/dw_mmc-rockchip.c
@@ -14,10 +14,12 @@
#include <linux/of_address.h>
#include <linux/mmc/slot-gpio.h>
#include <linux/pm_runtime.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/consumer.h> // Hack
#include <linux/slab.h>
#include "dw_mmc.h"
#include "dw_mmc-pltfm.h"
+#include "../core/core.h"
+#include "../core/core.h" // Hack
#define RK3288_CLKGEN_DIV 2
@@ -353,6 +355,27 @@ static int dw_mci_rockchip_probe(struct platform_device *pdev)
@@ -365,6 +367,27 @@ static int dw_mci_rockchip_probe(struct platform_device *pdev)
return 0;
}
@ -37,13 +52,13 @@ index 372fb6e..a54c290 100644
+ if (!IS_ERR(mmc->supply.vqmmc))
+ regulator_set_voltage(mmc->supply.vqmmc, 3000000, 3300000);
+ }
+
+}
+
+
static int dw_mci_rockchip_remove(struct platform_device *pdev)
{
pm_runtime_get_sync(&pdev->dev);
@@ -373,6 +396,7 @@ static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
@@ -385,6 +408,7 @@ static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
static struct platform_driver dw_mci_rockchip_pltfm_driver = {
.probe = dw_mci_rockchip_probe,
.remove = dw_mci_rockchip_remove,
@ -52,74 +67,80 @@ index 372fb6e..a54c290 100644
.name = "dwmmc_rockchip",
.of_match_table = dw_mci_rockchip_match,
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index e45129f..faad52d 100644
index a9dfb269..ee956a57 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -39,8 +39,10 @@
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/mmc/slot-gpio.h>
+#include <linux/reboot.h>
+#include <linux/reboot.h> // Hack
#include "dw_mmc.h"
+#include "../core/core.h"
+#include "../core/core.h" // Hack
/* Common flag combinations */
#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
@@ -2686,6 +2688,30 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
@@ -2687,6 +2689,28 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
return IRQ_HANDLED;
}
+struct dw_mci *mSdhost;
+
+void setmmcEmergency() {
+
+ struct mmc_host *mmc = mSdhost->slot->mmc;
+ struct mmc_host *mmc;
+ int ret;
+
+ if(of_machine_is_compatible("asus,rk3288-tinker")){
+ printk(KERN_ERR "Emergency route taken.\n");
+ if (of_machine_is_compatible("asus,rk3288-tinker")) {
+ mmc = mSdhost->slot->mmc;
+
+ mmc_power_off(mmc);
+
+ mdelay(20);
+
+ if (!IS_ERR(mmc->supply.vmmc)) {
+ if (!IS_ERR(mmc->supply.vmmc))
+ ret = regulator_enable(mmc->supply.vmmc);
+ }
+
+ if (!IS_ERR(mmc->supply.vqmmc))
+ regulator_set_voltage(mmc->supply.vqmmc, 3000000, 3300000);
+ }
+
+}
+
+EXPORT_SYMBOL(setmmcEmergency);
static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
+
static int dw_mci_init_slot(struct dw_mci *host)
{
@@ -2717,6 +2743,8 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
mmc->f_min = freq[0];
struct mmc_host *mmc;
@@ -2718,6 +2742,8 @@ static int dw_mci_init_slot(struct dw_mci *host)
mmc->f_max = freq[1];
}
+ if (of_find_property(host->dev->of_node, "supports-sd", NULL))
+ mSdhost = host;
+ if (of_find_property(host->dev->of_node, "supports-sd", NULL))
+ mSdhost = host;
/*if there are external regulators, get them*/
ret = mmc_regulator_get_supply(mmc);
if (ret == -EPROBE_DEFER)
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index a7ff409..e045bc2 100644
index a7ff409f..586e4504 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -73,6 +73,7 @@ extern char poweroff_cmd[POWEROFF_CMD_PATH_LEN];
@@ -72,12 +72,15 @@ extern char poweroff_cmd[POWEROFF_CMD_PATH_LEN];
extern void orderly_poweroff(bool force);
extern void orderly_reboot(void);
+// Wonderful ASUS hack
+extern void setmmcEmergency(void);
/*
* Emergency restart, callable from an interrupt handler.
*/
extern void emergency_restart(void);
+
#include <asm/emergency-restart.h>
#endif /* _LINUX_REBOOT_H */
diff --git a/kernel/reboot.c b/kernel/reboot.c
index bd30a97..9f99488 100644
index bd30a973..9f99488f 100644
--- a/kernel/reboot.c
+++ b/kernel/reboot.c
@@ -61,6 +61,7 @@ void (*pm_power_off_prepare)(void);
@ -130,3 +151,6 @@ index bd30a97..9f99488 100644
machine_emergency_restart();
}
EXPORT_SYMBOL_GPL(emergency_restart);
--
2.13.0

0
patch/kernel/rockchip-dev/1008-rockchip-rga-v4l2-m2m-support.patch → patch/kernel/rockchip-dev/1006-rockchip-rga-v4l2-m2m-support.patch
View file

92
patch/kernel/rockchip-dev/1006-soc-rockchip-power-domain-export-idle-request.patch
View file

@ -1,92 +0,0 @@
From f723bec5d7c860901ddae1634094d55bad2b8a4d Mon Sep 17 00:00:00 2001
From: Randy Li <ayaka@soulik.info>
Date: Tue, 9 May 2017 00:34:17 +0800
Subject: [PATCH 7/9] soc: rockchip: power-domain: export idle request
We need to put the power status of HEVC/RKVDEC IP into IDLE
unless we can't reset that IP or the SoC would crash down.
rockchip_pmu_idle_request(dev, true)---> enter idle
rockchip_pmu_idle_request(dev, false)---> exit idle
Only the video codec drivers of rockchip platform would
request this patch currently.
I am not sure whether it is necessary to add a new function
at generic power domain. I want someone give me some advises
here.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Randy Li <ayaka@soulik.info>
---
drivers/soc/rockchip/pm_domains.c | 24 ++++++++++++++++++++++++
include/linux/rockchip_pmu.h | 15 +++++++++++++++
2 files changed, 39 insertions(+)
create mode 100644 include/linux/rockchip_pmu.h
diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
index 796c46a6..c1bff1c8 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -18,6 +18,7 @@
#include <linux/clk.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
+#include <linux/rockchip_pmu.h>
#include <dt-bindings/power/rk3288-power.h>
#include <dt-bindings/power/rk3328-power.h>
#include <dt-bindings/power/rk3368-power.h>
@@ -179,6 +180,29 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
return 0;
}
+int rockchip_pmu_idle_request(struct device *dev, bool idle)
+{
+ struct generic_pm_domain *genpd;
+ struct rockchip_pm_domain *pd;
+ int ret;
+
+ if (IS_ERR_OR_NULL(dev))
+ return -EINVAL;
+
+ if (IS_ERR_OR_NULL(dev->pm_domain))
+ return -EINVAL;
+
+ genpd = pd_to_genpd(dev->pm_domain);
+ pd = to_rockchip_pd(genpd);
+
+ mutex_lock(&pd->pmu->mutex);
+ ret = rockchip_pmu_set_idle_request(pd, idle);
+ mutex_unlock(&pd->pmu->mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL(rockchip_pmu_idle_request);
+
static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
{
int i;
diff --git a/include/linux/rockchip_pmu.h b/include/linux/rockchip_pmu.h
new file mode 100644
index 00000000..720b3314
--- /dev/null
+++ b/include/linux/rockchip_pmu.h
@@ -0,0 +1,15 @@
+/*
+ * pm_domain.h - Definitions and headers related to device power domains.
+ *
+ * Copyright (C) 2017 Randy Li <ayaka@soulik.info>.
+ *
+ * This file is released under the GPLv2.
+ */
+
+#ifndef _LINUX_ROCKCHIP_PM_H
+#define _LINUX_ROCKCHIP_PM_H
+#include <linux/device.h>
+
+int rockchip_pmu_idle_request(struct device *dev, bool idle);
+
+#endif /* _LINUX_ROCKCHIP_PM_H */
--
2.13.0

0
patch/kernel/rockchip-dev/1009-dt-bindings-Document-the-Rockchip-RGA-bindings.patch → patch/kernel/rockchip-dev/1007-dt-bindings-Document-the-Rockchip-RGA-bindings.patch
View file

337
patch/kernel/rockchip-dev/1010-Rockchip-DRM-GEM-Prime-import-SG-Table-Support.patch
View file

@ -1,337 +0,0 @@
From e6e383f45f59fdd935a2b13b1e9b00968ac5a1aa Mon Sep 17 00:00:00 2001
From: Myy <myy@miouyouyou.fr>
Date: Sun, 30 Jul 2017 17:32:26 +0000
Subject: [PATCH 2/9] Rockchip DRM: GEM Prime import SG Table Support
A combination of an old patch provided by the ARM developers and the
patches provided by Rockchip and @wzyy2.
This patch provide a Rockchip specific implementation for the Rockchip
DRM driver gem_prime_import_sg_table call.
Signed-off-by: Myy <myy@miouyouyou.fr>
---
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 10 +++
drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 133 ++++++++++++++++++++++++++--
drivers/gpu/drm/rockchip/rockchip_drm_gem.h | 9 +-
include/uapi/drm/rockchip_drm.h | 57 ++++++++++++
4 files changed, 199 insertions(+), 10 deletions(-)
create mode 100644 include/uapi/drm/rockchip_drm.h
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
index c6b1b7f3..a261948f 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
@@ -19,6 +19,7 @@
#include <drm/drm_fb_helper.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_of.h>
+#include <drm/rockchip_drm.h>
#include <linux/dma-mapping.h>
#include <linux/dma-iommu.h>
#include <linux/pm_runtime.h>
@@ -217,6 +218,12 @@ static void rockchip_drm_lastclose(struct drm_device *dev)
drm_fb_helper_restore_fbdev_mode_unlocked(&priv->fbdev_helper);
}
+static const struct drm_ioctl_desc rockchip_ioctls[] = {
+ DRM_IOCTL_DEF_DRV(ROCKCHIP_GEM_CREATE, rockchip_gem_create_ioctl,
+ DRM_UNLOCKED | DRM_AUTH),
+};
+
+
static const struct file_operations rockchip_drm_driver_fops = {
.owner = THIS_MODULE,
.open = drm_open,
@@ -239,12 +246,15 @@ static struct drm_driver rockchip_drm_driver = {
.dumb_destroy = drm_gem_dumb_destroy,
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
+ .gem_prime_import_sg_table = rockchip_gem_prime_import_sg_table,
.gem_prime_import = drm_gem_prime_import,
.gem_prime_export = drm_gem_prime_export,
.gem_prime_get_sg_table = rockchip_gem_prime_get_sg_table,
.gem_prime_vmap = rockchip_gem_prime_vmap,
.gem_prime_vunmap = rockchip_gem_prime_vunmap,
.gem_prime_mmap = rockchip_gem_mmap_buf,
+ .ioctls = rockchip_ioctls,
+ .num_ioctls = ARRAY_SIZE(rockchip_ioctls),
.fops = &rockchip_drm_driver_fops,
.name = DRIVER_NAME,
.desc = DRIVER_DESC,
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
index b74ac717..05dfdbed 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
@@ -16,7 +16,12 @@
#include <drm/drmP.h>
#include <drm/drm_gem.h>
#include <drm/drm_vma_manager.h>
+#include <drm/rockchip_drm.h>
+
#include <linux/iommu.h>
+#include <linux/dma-mapping.h>
+#include <linux/dma-buf.h>
+
#include "rockchip_drm_drv.h"
#include "rockchip_drm_gem.h"
@@ -309,12 +314,10 @@ static void rockchip_gem_release_object(struct rockchip_gem_object *rk_obj)
}
struct rockchip_gem_object *
- rockchip_gem_create_object(struct drm_device *drm, unsigned int size,
- bool alloc_kmap)
+rockchip_gem_alloc_object(struct drm_device *drm, unsigned int size)
{
struct rockchip_gem_object *rk_obj;
struct drm_gem_object *obj;
- int ret;
size = round_up(size, PAGE_SIZE);
@@ -325,6 +328,19 @@ struct rockchip_gem_object *
obj = &rk_obj->base;
drm_gem_object_init(drm, obj, size);
+ return rk_obj;
+}
+
+struct rockchip_gem_object *
+rockchip_gem_create_object(struct drm_device *drm, unsigned int size,
+ bool alloc_kmap)
+{
+ struct rockchip_gem_object *rk_obj;
+ int ret;
+
+ rk_obj = rockchip_gem_alloc_object(drm, size);
+ if (IS_ERR(rk_obj))
+ return rk_obj;
ret = rockchip_gem_alloc_buf(rk_obj, alloc_kmap);
if (ret)
@@ -343,13 +359,24 @@ struct rockchip_gem_object *
*/
void rockchip_gem_free_object(struct drm_gem_object *obj)
{
- struct rockchip_gem_object *rk_obj;
-
- rk_obj = to_rockchip_obj(obj);
+ struct drm_device *drm = obj->dev;
+ struct rockchip_drm_private *private = drm->dev_private;
+ struct rockchip_gem_object *rk_obj = to_rockchip_obj(obj);
- rockchip_gem_free_buf(rk_obj);
+ if (obj->import_attach) {
+ if (private->domain) {
+ rockchip_gem_iommu_unmap(rk_obj);
+ } else {
+ dma_unmap_sg(
+ drm->dev, rk_obj->sgt->sgl,
+ rk_obj->sgt->nents, DMA_BIDIRECTIONAL
+ );
+ }
+ drm_prime_gem_destroy(obj, rk_obj->sgt);
+ } else {
+ rockchip_gem_free_buf(rk_obj);
+ }
- rockchip_gem_release_object(rk_obj);
}
/*
@@ -445,6 +472,16 @@ int rockchip_gem_dumb_create(struct drm_file *file_priv,
return PTR_ERR_OR_ZERO(rk_obj);
}
+int rockchip_gem_create_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv) {
+ struct drm_rockchip_gem_create *args = data;
+ struct rockchip_gem_object *rk_obj;
+
+ rk_obj = rockchip_gem_create_with_handle(file_priv, dev, args->size,
+ &args->handle);
+ return PTR_ERR_OR_ZERO(rk_obj);
+}
+
/*
* Allocate a sg_table for this GEM object.
* Note: Both the table's contents, and the sg_table itself must be freed by
@@ -477,6 +514,86 @@ struct sg_table *rockchip_gem_prime_get_sg_table(struct drm_gem_object *obj)
return sgt;
}
+static unsigned long rockchip_sg_get_contiguous_size(struct sg_table *sgt,
+ int count)
+{
+ struct scatterlist *s;
+ dma_addr_t expected = sg_dma_address(sgt->sgl);
+ unsigned int i;
+ unsigned long size = 0;
+
+ for_each_sg(sgt->sgl, s, count, i) {
+ if (sg_dma_address(s) != expected)
+ break;
+ expected = sg_dma_address(s) + sg_dma_len(s);
+ size += sg_dma_len(s);
+ }
+ return size;
+}
+
+static int
+rockchip_gem_iommu_map_sg(struct drm_device *drm,
+ struct dma_buf_attachment *attach,
+ struct sg_table *sg,
+ struct rockchip_gem_object *rk_obj)
+{
+ rk_obj->sgt = sg;
+ return rockchip_gem_iommu_map(rk_obj);
+}
+
+static int
+rockchip_gem_dma_map_sg(struct drm_device *drm,
+ struct dma_buf_attachment *attach,
+ struct sg_table *sg,
+ struct rockchip_gem_object *rk_obj)
+{
+ int count = dma_map_sg(drm->dev, sg->sgl, sg->nents,
+ DMA_BIDIRECTIONAL);
+ if (!count)
+ return -EINVAL;
+
+ if (rockchip_sg_get_contiguous_size(sg, count) < attach->dmabuf->size) {
+ DRM_ERROR("failed to map sg_table to contiguous linear address.\n");
+ dma_unmap_sg(drm->dev, sg->sgl, sg->nents,
+ DMA_BIDIRECTIONAL);
+ return -EINVAL;
+ }
+
+ rk_obj->dma_addr = sg_dma_address(sg->sgl);
+ rk_obj->sgt = sg;
+ return 0;
+}
+
+struct drm_gem_object *
+rockchip_gem_prime_import_sg_table(struct drm_device *drm,
+ struct dma_buf_attachment *attach,
+ struct sg_table *sg)
+{
+ struct rockchip_drm_private *private = drm->dev_private;
+ struct rockchip_gem_object *rk_obj;
+ int ret;
+
+ rk_obj = rockchip_gem_alloc_object(drm, attach->dmabuf->size);
+ if (IS_ERR(rk_obj))
+ return ERR_CAST(rk_obj);
+
+ if (private->domain)
+ ret = rockchip_gem_iommu_map_sg(drm, attach, sg, rk_obj);
+ else
+ ret = rockchip_gem_dma_map_sg(drm, attach, sg, rk_obj);
+
+ if (ret < 0) {
+ DRM_ERROR("failed to import sg table: %d\n", ret);
+ goto err_free_rk_obj;
+ }
+
+ return &rk_obj->base;
+
+err_free_rk_obj:
+ rockchip_gem_release_object(rk_obj);
+ return ERR_PTR(ret);
+}
+
void *rockchip_gem_prime_vmap(struct drm_gem_object *obj)
{
struct rockchip_gem_object *rk_obj = to_rockchip_obj(obj);
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h
index 3f6ea4d1..b8fed4df 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h
@@ -36,8 +36,9 @@ struct rockchip_gem_object {
struct sg_table *rockchip_gem_prime_get_sg_table(struct drm_gem_object *obj);
struct drm_gem_object *
-rockchip_gem_prime_import_sg_table(struct drm_device *dev, size_t size,
- struct sg_table *sgt);
+rockchip_gem_prime_import_sg_table(struct drm_device *dev,
+ struct dma_buf_attachment *attach,
+ struct sg_table *sgt);
void *rockchip_gem_prime_vmap(struct drm_gem_object *obj);
void rockchip_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
@@ -58,4 +58,8 @@ void rockchip_gem_free_object(struct drm_gem_object *obj);
int rockchip_gem_dumb_create(struct drm_file *file_priv,
struct drm_device *dev,
struct drm_mode_create_dumb *args);
+int rockchip_gem_create_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
+int rockchip_gem_map_offset_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
#endif /* _ROCKCHIP_DRM_GEM_H */
diff --git a/include/uapi/drm/rockchip_drm.h b/include/uapi/drm/rockchip_drm.h
new file mode 100644
index 00000000..c521e5a3
--- /dev/null
+++ b/include/uapi/drm/rockchip_drm.h
@@ -0,0 +1,57 @@
+/*
+ *
+ * Copyright (c) Fuzhou Rockchip Electronics Co.Ltd
+ * Authors:
+ * Mark Yao <yzq@rock-chips.com>
+ *
+ * base on exynos_drm.h
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef _UAPI_ROCKCHIP_DRM_H
+#define _UAPI_ROCKCHIP_DRM_H
+
+#include <drm/drm.h>
+
+/**
+ * User-desired buffer creation information structure.
+ *
+ * @size: user-desired memory allocation size.
+ * @flags: user request for setting memory type or cache attributes.
+ * @handle: returned a handle to created gem object.
+ * - this handle will be set by gem module of kernel side.
+ */
+struct drm_rockchip_gem_create {
+ uint64_t size;
+ uint32_t flags;
+ uint32_t handle;
+};
+
+/**
+ * A structure for getting buffer offset.
+ *
+ * @handle: a pointer to gem object created.
+ * @pad: just padding to be 64-bit aligned.
+ * @offset: relatived offset value of the memory region allocated.
+ * - this value should be set by user.
+ */
+struct drm_rockchip_gem_map_off {
+ uint32_t handle;
+ uint32_t pad;
+ uint64_t offset;
+};
+
+#define DRM_ROCKCHIP_GEM_CREATE 0x00
+#define DRM_ROCKCHIP_GEM_MAP_OFFSET 0x01
+
+#define DRM_IOCTL_ROCKCHIP_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
+ DRM_ROCKCHIP_GEM_CREATE, struct drm_rockchip_gem_create)
+
+#define DRM_IOCTL_ROCKCHIP_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \
+ DRM_ROCKCHIP_GEM_MAP_OFFSET, struct drm_rockchip_gem_map_off)
+
+#endif /* _UAPI_ROCKCHIP_DRM_H */
--
2.13.0

80
patch/kernel/rockchip-dev/1011-drm_fourcc-Add-new-P010-P016-video-format.patch
View file

@ -1,80 +0,0 @@
From 4e19e2a197570d60e188f7cf0e62d375eab68103 Mon Sep 17 00:00:00 2001
From: Randy Li <ayaka@soulik.info>
Date: Sun, 5 Mar 2017 18:00:31 +0800
Subject: [PATCH 8/9] drm_fourcc: Add new P010, P016 video format
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits
per channel video format.
P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits
per channel video format.
V3: Added P012 and fixed cpp for P010
V4: format definition refined per review
V5: Format comment block for each new pixel format
V6: reversed Cb/Cr order in comments
v7: reversed Cb/Cr order in comments of header files, remove
the wrong part of commit message.
Cc: Daniel Stone <daniel@fooishbar.org>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
include/uapi/drm/drm_fourcc.h | 21 +++++++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 9c0152df..61015204 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -173,6 +173,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+ { .format = DRM_FORMAT_P012, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+ { .format = DRM_FORMAT_P016, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 7586c46f..15a94c79 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -142,6 +142,27 @@ extern "C" {
#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y:x [10:6] little endian
+ * index 1 = Cb:Cr plane, [31:0] Cb:x:Cr:x [10:6:10:6] little endian
+ */
+#define DRM_FORMAT_P010 fourcc_code('N', 'A', '1', '2') /* 2x2 subsampled Cb:Cr plane 10 bits per channel */
+
+/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y:x [12:4] little endian
+ * index 1 = Cb:Cr plane, [31:0] Cb:x:Cr:x [12:4:12:4] little endian
+ */
+#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cb:Cr plane 12 bits per channel */
+
+/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y little endian
+ * index 1 = Cb:Cr plane, [31:0] Cb:Cr [16:16] little endian
+ */
+#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cb:Cr plane 16 bits per channel */
+
+/*
* 3 plane YCbCr
* index 0: Y plane, [7:0] Y
* index 1: Cb plane, [7:0] Cb
--
2.13.0

31
patch/kernel/rockchip-dev/1012-net-stmmac-Reverting-a-part-of-Use-the-right-logging.patch
View file

@ -1,31 +0,0 @@
From ead80e80c41a4c1275543c3c7c2d22ff1c19717a Mon Sep 17 00:00:00 2001
From: Myy <myy@miouyouyou.fr>
Date: Mon, 21 Aug 2017 06:22:15 +0000
Subject: [PATCH] net: stmmac: Reverting a part of "Use the right logging
function"
Turns out that the phy_attached_info call, added in commit
fbca164776e438b639af592c522b8b0506b54dcc provokes a crash on boot
with MiQi devices.
Signed-off-by: Myy <myy@miouyouyou.fr>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
index 72ec711f..889810f0 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
@@ -270,7 +270,7 @@ int stmmac_mdio_register(struct net_device *ndev)
if (priv->plat->phy_addr == -1)
priv->plat->phy_addr = addr;
- phy_attached_info(phydev);
+ //phy_attached_info(phydev);
found = 1;
}
--
2.13.0

34
patch/kernel/rockchip-dev/2001-Enabling-the-Mali-GPU-nodes-in-the-MiQi-and-Tinkerbo.patch
View file

@ -1,34 +0,0 @@
From 4b91f1b6cdd50bec47507704c127bbc913aeefe4 Mon Sep 17 00:00:00 2001
From: Myy <myy@miouyouyou.fr>
Date: Tue, 18 Jul 2017 02:25:27 +0000
Subject: [PATCH] Enabling the Mali GPU nodes in the MiQi and Tinkerboard DTS
files
These will be enabled in upcoming arm-soc patches. Meanwhile, they're
enabled through this patch.
Signed-off-by: Myy <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-miqi.dts | 5 +++++
arch/arm/boot/dts/rk3288-tinker.dts | 5 +++++
2 files changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index c165eec..29b94a0 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -150,6 +150,11 @@
status = "ok";
};
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
&hdmi {
ddc-i2c-bus = <&i2c5>;
status = "okay";
--
2.10.2

35
patch/kernel/rockchip-dev/2001-dts-rk3288-miqi-Enabling-the-Mali-GPU-node.patch Normal file
View file

@ -0,0 +1,35 @@
From 604ea7fc311af2b3a41e7fe3b4fbde0ee03dfb9c Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 21:09:50 +0200
Subject: [PATCH 04/28] dts: rk3288: miqi: Enabling the Mali GPU node
Why is the MiQi the only one left without a working mali GPU node ?
Seriously, is there a rk3288 chipset WITHOUT a mali GPU ? Couldn't
they enable it once in the DTSI, instead of defining it as "disabled"
and enabling it in every DTS file ?
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-miqi.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index 4d923aa6..3cd60674 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -149,6 +149,11 @@
status = "ok";
};
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
&hdmi {
ddc-i2c-bus = <&i2c5>;
status = "okay";
--
2.11.0

12
patch/kernel/rockchip-dev/2002-ARM-dts-rockchip-fix-the-regulator-s-voltage-range-o.patch
View file

@ -1,7 +1,7 @@
From 69515aeb405daf9b9767209d63a38f68a6e2521d Mon Sep 17 00:00:00 2001
From 89e5763110ca77d68a4be00cd97a638adc2401d5 Mon Sep 17 00:00:00 2001
From: Willy Tarreau <w@1wt.eu>
Date: Tue, 2 Aug 2016 08:31:00 +0200
Subject: [PATCH 05/12] ARM: dts: rockchip: fix the regulator's voltage range
Subject: [PATCH 05/28] ARM: dts: rockchip: fix the regulator's voltage range
on MiQi board
The board declared too narrow a voltage range for the CPU and GPU
@ -15,10 +15,10 @@ Signed-off-by: Willy Tarreau <w@1wt.eu>
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index cc42be5..43728c9 100644
index 3cd60674..a1c3cdaa 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -166,8 +166,8 @@
@@ -168,8 +168,8 @@
fcs,suspend-voltage-selector = <1>;
reg = <0x40>;
regulator-name = "vdd_cpu";
@ -29,7 +29,7 @@ index cc42be5..43728c9 100644
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <300>;
@@ -180,8 +180,8 @@
@@ -182,8 +182,8 @@
fcs,suspend-voltage-selector = <1>;
reg = <0x41>;
regulator-name = "vdd_gpu";
@ -41,5 +41,5 @@ index cc42be5..43728c9 100644
vin-supply = <&vcc_sys>;
};
--
2.10.2
2.11.0

9
patch/kernel/rockchip-next/2003-Adaptation-ARM-dts-rockchip-add-the-MiQi-board-s-fan.patch → patch/kernel/rockchip-dev/2003-ARM-dts-rockchip-add-the-MiQi-board-s-fan-definition.patch
View file

@ -1,8 +1,7 @@
From 112ef8de95b8b4287de14f7e5c9853cbbf3e69b0 Mon Sep 17 00:00:00 2001
From c27e445527e949f3ef46d5326066196969c17d23 Mon Sep 17 00:00:00 2001
From: Myy <myy@miouyouyou.fr>
Date: Sun, 12 Mar 2017 19:43:15 +0000
Subject: [PATCH 07/12] [Adaptation] ARM: dts: rockchip: add the MiQi board's
fan definition
Subject: [PATCH 06/28] ARM: dts: rockchip: add the MiQi board's fan definition
The MiQi board is sold with an enclosure in which a fan is connected
to the second LED output, and configured by default in "heartbeat"
@ -25,7 +24,7 @@ Signed-off-by: Myy <myy@miouyouyou.fr>
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index 7a42069..3132829 100644
index a1c3cdaa..0e383595 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -67,6 +67,13 @@
@ -43,5 +42,5 @@ index 7a42069..3132829 100644
gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
label = "miqi:green:user";
--
2.10.2
2.11.0

8
patch/kernel/rockchip-dev/2004-ARM-dts-rockchip-add-support-for-1800-MHz-operation-.patch
View file

@ -1,7 +1,7 @@
From 266b439288e86b26e4cc524b92f1e0683ae913f0 Mon Sep 17 00:00:00 2001
From e7e092be197c51b4d222a3b4e6638318067b7e6a Mon Sep 17 00:00:00 2001
From: Willy Tarreau <w@1wt.eu>
Date: Tue, 2 Aug 2016 08:20:53 +0200
Subject: [PATCH 08/12] ARM: dts: rockchip: add support for 1800 MHz operation
Subject: [PATCH 07/28] ARM: dts: rockchip: add support for 1800 MHz operation
on MiQi board
This board happily supports 1800 MHz operations (and even more), so
@ -14,7 +14,7 @@ Signed-off-by: Willy Tarreau <w@1wt.eu>
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index 3132829..db5fcd4 100644
index 0e383595..80603a3d 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -126,6 +126,18 @@
@ -37,5 +37,5 @@ index 3132829..db5fcd4 100644
&emmc {
--
2.10.2
2.11.0

8
patch/kernel/rockchip-dev/2005-Readapt-ARM-dts-rockchip-miqi-add-turbo-mode-operati.patch
View file

@ -1,7 +1,7 @@
From 7dfb0c2748133e40ae11d6f800550d3b00a8a22d Mon Sep 17 00:00:00 2001
From de9dcd5ecab0686022eee243464f35d2c7a34c97 Mon Sep 17 00:00:00 2001
From: Myy <myy@miouyouyou.fr>
Date: Mon, 16 Jan 2017 12:44:56 +0000
Subject: [PATCH 10/12] Readapt: ARM: dts: rockchip: miqi: add turbo-mode
Subject: [PATCH 08/28] Readapt: ARM: dts: rockchip: miqi: add turbo-mode
operating points
Readaptation of Willy Tarreau patch.
@ -32,7 +32,7 @@ Signed-off-by: Myy <myy@miouyouyou.fr>
1 file changed, 107 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index db5fcd4..bd27f91 100644
index 80603a3d..d7fde483 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -122,22 +122,116 @@
@ -166,5 +166,5 @@ index db5fcd4..bd27f91 100644
&emmc {
--
2.10.2
2.11.0

61
patch/kernel/rockchip-dev/2006-ARM-DTSI-rk3288-Missing-GRF-handles.patch Normal file
View file

@ -0,0 +1,61 @@
From 771bcfe1735e42650b763e52a042a9fd98b2fa5b Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 21:20:43 +0200
Subject: [PATCH 09/28] ARM: DTSI: rk3288.dtsi: Missing GRF handles
Add missing GRF handles.
This patch is taken from the patches provided by the ARMbian team.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 356ed1e6..5b789528 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -547,6 +547,7 @@
pinctrl-2 = <&otp_gpio>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
+ rockchip,grf = <&grf>;
status = "disabled";
};
@@ -655,6 +656,7 @@
pinctrl-0 = <&pwm0_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
+ rockchip,grf = <&grf>;
status = "disabled";
};
@@ -666,6 +668,7 @@
pinctrl-0 = <&pwm1_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
+ rockchip,grf = <&grf>;
status = "disabled";
};
@@ -677,6 +680,7 @@
pinctrl-0 = <&pwm2_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
+ rockchip,grf = <&grf>;
status = "disabled";
};
@@ -688,6 +692,7 @@
pinctrl-0 = <&pwm3_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
+ rockchip,grf = <&grf>;
status = "disabled";
};
--
2.11.0

31
patch/kernel/rockchip-dev/2007-RK3288-DTSI-rk3288-Add-missing-SPI2-pinctrl.patch Normal file
View file

@ -0,0 +1,31 @@
From 062488e4b8fd552c01e1104b3bc91a6f7ffe6c41 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 21:24:47 +0200
Subject: [PATCH 10/28] RK3288: DTSI: rk3288.dtsi: Add missing SPI2 pinctrl
The spi2_cs1 pin reference is missing in the spi2 first pin control
definition.
This patch is taken from the patches provided by the ARMbian team.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 5b789528..9ed532cc 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -334,7 +334,7 @@
dma-names = "tx", "rx";
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
+ pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0 &spi2_cs1>;
reg = <0x0 0xff130000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
--
2.11.0

27
patch/kernel/rockchip-dev/2008-Added-support-for-Tinkerboard-s-SPI-interface.patch Normal file
View file

@ -0,0 +1,27 @@
From af8d73ec0df1dde1e2fe1674c5708d4c30385ba9 Mon Sep 17 00:00:00 2001
From: Myy <myy@miouyouyou.fr>
Date: Mon, 5 Jun 2017 12:37:17 +0000
Subject: [PATCH 11/28] Added support for Tinkerboard's SPI interface
Imported from ARMbian
Signed-off-by: Myy <myy@miouyouyou.fr>
---
drivers/spi/spidev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
index cda10719..a6287475 100644
--- a/drivers/spi/spidev.c
+++ b/drivers/spi/spidev.c
@@ -669,6 +669,7 @@ static const struct of_device_id spidev_dt_ids[] = {
{ .compatible = "lineartechnology,ltc2488" },
{ .compatible = "ge,achc" },
{ .compatible = "semtech,sx1301" },
+ { .compatible = "rockchip,spi_tinker" },
{},
};
MODULE_DEVICE_TABLE(of, spidev_dt_ids);
--
2.11.0

69
patch/kernel/rockchip-dev/2009-Define-VPU-services-in-the-Rockchip-3288-DTS-files.patch
View file

@ -1,69 +0,0 @@
From 59b6f52c5290521ce2bd6209759e0d055c4bdc09 Mon Sep 17 00:00:00 2001
From: Myy <myy@miouyouyou.fr>
Date: Tue, 18 Jul 2017 02:21:44 +0000
Subject: [PATCH] Define VPU services in the Rockchip 3288 DTS files
And use them in the MiQi, Tinkerboard and Firefly board.
These will be used by the external Vcodec driver.
Signed-off-by: Myy <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-firefly.dtsi | 8 +++
arch/arm/boot/dts/rk3288-miqi.dts | 8 +++
arch/arm/boot/dts/rk3288-tinker.dts | 9 ++++
arch/arm/boot/dts/rk3288.dtsi | 97 +++++++++++++++++++++++++++++++++++
4 files changed, 122 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi
index 32dabae..13c8b42 100644
--- a/arch/arm/boot/dts/rk3288-firefly.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly.dtsi
@@ -612,3 +612,11 @@
&wdt {
status = "okay";
};
+
+&hevc_service {
+ status = "okay";
+};
+
+&vpu_service {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index 30e93f6..c165eec 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -462,3 +462,11 @@
&wdt {
status = "okay";
};
+
+&hevc_service {
+ status = "okay";
+};
+
+&vpu_service {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
index f601c78..6bbc8a3 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dts
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
@@ -534,3 +534,12 @@
&wdt {
status = "okay";
};
+
+&hevc_service {
+ status = "okay";
+};
+
+&vpu_service {
+ status = "okay";
+};
+
--
2.10.2

56
patch/kernel/rockchip-dev/2010-ARM-DTSI-rk3288-Adding-cells-addresses-and-size.patch Normal file
View file

@ -0,0 +1,56 @@
From 7af8d2bf732cb3baab7d926ed8a7e061e7a09ad9 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 21:39:00 +0200
Subject: [PATCH 13/28] ARM: DTSI: rk3288.dtsi: Adding cells addresses and
sizes of MMC nodes
Imported from the Rockchip 4.4 patches.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index be985f02..14ef8202 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -236,6 +236,8 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x0 0xff0c0000 0x0 0x4000>;
resets = <&cru SRST_MMC0>;
reset-names = "reset";
@@ -250,6 +252,8 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x0 0xff0d0000 0x0 0x4000>;
resets = <&cru SRST_SDIO0>;
reset-names = "reset";
@@ -264,6 +268,8 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x0 0xff0e0000 0x0 0x4000>;
resets = <&cru SRST_SDIO1>;
reset-names = "reset";
@@ -278,6 +284,8 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x0 0xff0f0000 0x0 0x4000>;
resets = <&cru SRST_EMMC>;
reset-names = "reset";
--
2.11.0

27
patch/kernel/rockchip-dev/2011-ARM-DTSI-rk3288-Adding-missing-EDP-power-domain.patch Normal file
View file

@ -0,0 +1,27 @@
From ac220d592aa38b9b717d36f7bb93f7be5a08f6b3 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 21:43:51 +0200
Subject: [PATCH 14/28] ARM: DTSI: rk3288.dtsi: Adding missing EDP power domain
Imported from Rockchip 4.4 kernel patches.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 14ef8202..10ecebb4 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -1105,6 +1105,7 @@
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
clock-names = "dp", "pclk";
+ power-domains = <&power RK3288_PD_VIO>;
phys = <&edp_phy>;
phy-names = "dp";
resets = <&cru SRST_EDP>;
--
2.11.0

40
patch/kernel/rockchip-dev/2012-ARM-DTSI-rk3288-Add-the-RGA-node.patch Normal file
View file

@ -0,0 +1,40 @@
From 3fe37d29b53e3d06c8f4314cfc113bfa679f67eb Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 21:48:05 +0200
Subject: [PATCH 15/28] ARM: DTSI: rk3288.dtsi: Add the RGA node
Imported from @wzyy2 patches.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 10ecebb4..455446f6 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -1159,6 +1159,20 @@
};
};
+ rga: rga@ff920000 {
+ compatible = "rockchip,rk3288-rga";
+ reg = <0x0 0xff920000 0x0 0x180>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rga";
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
+ clock-names = "aclk", "hclk", "sclk";
+ power-domains = <&power RK3288_PD_VIO>;
+ resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
+
+ reset-names = "core", "axi", "ahb";
+ status = "disabled";
+ };
+
vpu_mmu: iommu@ff9a0800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff9a0800 0x0 0x100>;
--
2.11.0

28
patch/kernel/rockchip-dev/2013-ARM-DTSI-rk3288-Adding-missing-VOPB-registers.patch Normal file
View file

@ -0,0 +1,28 @@
From c5af6798c9a411b3f550f463182a4b4904a21ec2 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 21:51:14 +0200
Subject: [PATCH 16/28] ARM: DTSI: rk3288.dtsi: Adding missing VOPB registers
Imported from @wzyy2 patches... I think...
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 455446f6..125f8835 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -987,7 +987,7 @@
vopb: vop@ff930000 {
compatible = "rockchip,rk3288-vop";
- reg = <0x0 0xff930000 0x0 0x19c>;
+ reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
--
2.11.0

31
patch/kernel/rockchip-dev/2014-ARM-DTSI-rk3288-Fixed-the-SPDIF-node-address.patch Normal file
View file

@ -0,0 +1,31 @@
From a0602b2724893de7ac9b4190a7a6bb66458da2d5 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 21:54:37 +0200
Subject: [PATCH 17/28] ARM: DTSI: rk3288.dtsi: Fixed the SPDIF node address
Now, the typo is only in the name of the node itself, not in the
actual registers addresses definition.
Still, this ought to be fixed one day !
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 125f8835..e5d3d3c9 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -922,7 +922,7 @@
status = "disabled";
};
- spdif: sound@ff88b0000 {
+ spdif: sound@ff8b0000 {
compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
reg = <0x0 0xff8b0000 0x0 0x10000>;
#sound-dai-cells = <0>;
--
2.11.0

165
patch/kernel/rockchip-dev/2015-ARM-DTS-rk3288-tinker-Enabling-SDIO-Wireless-and.patch Normal file
View file

@ -0,0 +1,165 @@
From 2715f4a9ab5c169c546029a61eebb0bde6619b0e Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 22:12:48 +0200
Subject: [PATCH 18/28] ARM: DTS: rk3288-tinker.dts: Enabling SDIO, Wireless
and Bluetooth
Adding the appropriate nodes in order to exploit the WiFi capabilities
of the board.
Since these capabilities are provided through SDIO, and the SDIO
nodes were not defined, these were added too.
These seems to depend on each other so they are added in one big
patch.
Split if necessary.
Bluetooth and uart0 (AKA Bluetooth UART) definitions were also added
in order to deal with all the wireless techs in one patch.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-tinker.dts | 82 ++++++++++++++++++++++++++++++++++++-
1 file changed, 81 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
index 346b0d8b..c552fd95 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dts
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
@@ -44,6 +44,7 @@
#include "rk3288.dtsi"
#include <dt-bindings/input/input.h>
+#include <dt-bindings/clock/rockchip,rk808.h>
/ {
model = "Rockchip RK3288 Tinker Board";
@@ -114,6 +115,24 @@
};
};
+ /* This is essential to get SDIO devices working.
+ The Wifi depends on SDIO ! */
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 RK808_CLKOUT1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&chip_enable_h>, <&wifi_enable_h>;
+
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>, <&gpio4 RK_PD3 GPIO_ACTIVE_LOW>;
+ };
+
vcc_sys: vsys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
@@ -134,6 +153,28 @@
startup-delay-us = <100000>;
vin-supply = <&vcc_io>;
};
+
+ wireless-wlan {
+ compatible = "wlan-platdata";
+ rockchip,grf = <&grf>;
+ wifi_chip_type = "8723bs";
+ sdio_vref = <1800>;
+ WIFI,host_wake_irq = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ wireless-bluetooth {
+ compatible = "bluetooth-platdata";
+ uart_rts_gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default","rts_gpio";
+ pinctrl-0 = <&uart0_rts>;
+ pinctrl-1 = <&uart0_gpios>;
+ BT,reset_gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+ BT,wake_gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
+ BT,wake_host_irq = <&gpio4 31 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
};
&cpu0 {
@@ -373,10 +414,30 @@
&io_domains {
status = "okay";
-
+ rockchip,grf = <&grf>;
+ wifi-supply = <&vcc_18>;
sdcard-supply = <&vccio_sd>;
};
+&sdio0 {
+ status = "okay";
+ clock-frequency = <50000000>;
+ clock-freq-min-max = <200000 50000000>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ supports-sdio;
+
+};
+
&pinctrl {
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
drive-strength = <8>;
@@ -422,6 +483,16 @@
};
};
+ sdio-pwrseq {
+ wifi_enable_h: wifienable-h {
+ rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ chip_enable_h: chip-enable-h {
+ rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
sdmmc {
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
@@ -453,6 +524,13 @@
rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ wireless-bluetooth {
+ uart0_gpios: uart0-gpios {
+ rockchip,pins = <4 19 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
};
&pwm0 {
@@ -485,6 +563,8 @@
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer>, <&uart0_cts>;
};
&uart1 {
--
2.11.0

29
patch/kernel/rockchip-dev/2016-ARM-DTS-rk3288-tinker-Improving-the-CPU-max-volt.patch Normal file
View file

@ -0,0 +1,29 @@
From d4775f623b25009039a8ef3f28332033c7766ecc Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 22:20:33 +0200
Subject: [PATCH 19/28] ARM: DTS: rk3288-tinker.dts: Improving the CPU max
voltage
Taken from the various patches provided by @TonyMac32 .
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-tinker.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
index c552fd95..4ce94698 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dts
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
@@ -243,7 +243,7 @@
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
+ regulator-max-microvolt = <1450000>;
regulator-name = "vdd_arm";
regulator-ramp-delay = <6000>;
regulator-state-mem {
--
2.11.0

40
patch/kernel/rockchip-dev/2017-ARM-DTS-rk3288-tinker-Setting-up-the-SD-regulato.patch Normal file
View file

@ -0,0 +1,40 @@
From 39e50ab508d8104a733771a8681908a66a300edd Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 22:25:03 +0200
Subject: [PATCH 20/28] ARM: DTS: rk3288-tinker.dts: Setting up the SD
regulators
Some are needed and some are not. Playing with these parameters is
required to get reboot working on these boards.
I still can't believe that these boards can't soft reset correctly.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-tinker.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
index 4ce94698..90c1a251 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dts
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
@@ -333,6 +333,8 @@
};
vccio_sd: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
@@ -379,7 +381,6 @@
};
vcc33_sd: SWITCH_REG1 {
- regulator-always-on;
regulator-boot-on;
regulator-name = "vcc33_sd";
regulator-state-mem {
--
2.11.0

53
patch/kernel/rockchip-dev/2018-ARM-DTS-rk3288-tinker-Defined-the-I2C-interfaces.patch Normal file
View file

@ -0,0 +1,53 @@
From b0a552add28bf4590b979abb3530b14b6811eec1 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 22:33:39 +0200
Subject: [PATCH 21/28] ARM: DTS: rk3288-tinker.dts: Defined the I2C interfaces
And all the hardware behind.
Taken from, and tested by @TonyMac32 .
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-tinker.dts | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
index 90c1a251..67a3ce6f 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dts
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
@@ -400,8 +400,31 @@
};
};
+&i2c1 {
+ status = "okay";
+};
+
&i2c2 {
status = "okay";
+
+ afc0:af-controller@0 {
+ status = "okay";
+ compatible = "silicon touch,vm149C-v4l2-i2c-subdev";
+ reg = <0x0 0x0c>;
+ };
+
+ eeprom:m24c08@50 {
+ compatible = "at,24c08";
+ reg = <0x0 0x50>;
+ };
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
};
&i2c5 {
--
2.11.0

35
patch/kernel/rockchip-dev/2019-ARM-DTS-rk3288-tinker-Add-the-MIPI-DSI-node.patch Normal file
View file

@ -0,0 +1,35 @@
From 8ca607f3fe77c80a3367d8363703d5dc1d6781d4 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 22:36:02 +0200
Subject: [PATCH 22/28] ARM: DTS: rk3288-tinker.dts: Add the MIPI DSI node
Taken from, and tested by @TonyMac32 .
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-tinker.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
index 67a3ce6f..6f4c0843 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dts
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
@@ -443,6 +443,15 @@
sdcard-supply = <&vccio_sd>;
};
+&mipi_dsi {
+ status = "okay";
+ mipi_panel: mipi-panel {
+ compatible ="asus,tc358762";
+ reg = <0x0 0>;
+ status = "okay";
+ };
+};
+
&sdio0 {
status = "okay";
clock-frequency = <50000000>;
--
2.11.0

49
patch/kernel/rockchip-dev/2020-ARM-DTS-rk3288-tinker-Defining-the-SPI-interface.patch Normal file
View file

@ -0,0 +1,49 @@
From 14f951ca2d354ad8fd068d0f3d8648d5c0d1e60e Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 22:40:26 +0200
Subject: [PATCH 23/28] ARM: DTS: rk3288-tinker.dts: Defining the SPI interface
Taken from, and tested by @TonyMac32 .
Well, the original one was tested by him but I had to adapt the
registers definitions to the new 64-bits LPAE-compliant syntax.
Therefore that *might* break, along with a few other patches.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-tinker.dts | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
index 6f4c0843..f4b4525c 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dts
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
@@ -471,6 +471,24 @@
};
+&spi2 {
+ status = "okay";
+ max-freq = <50000000>;
+ spidev@0 {
+ compatible = "rockchip,spi_tinker";
+ reg = <0x0 0>;
+ spi-max-frequency = <50000000>;
+ spi-cpha = <1>;
+ };
+ spidev@1 {
+ compatible = "rockchip,spi_tinker";
+ reg = <0x0 1>;
+ spi-max-frequency = <50000000>;
+ spi-cpha = <1>;
+ };
+};
+
+
&pinctrl {
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
drive-strength = <8>;
--
2.11.0

33
patch/kernel/rockchip-dev/2021-ARM-DTS-rk3288-tinker-Defining-SDMMC-properties.patch Normal file
View file

@ -0,0 +1,33 @@
From 58d72a1cc693c4c08391487476d0cd6d167a57cf Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 22:48:36 +0200
Subject: [PATCH 24/28] ARM: DTS: rk3288-tinker.dts: Defining SDMMC properties
I never knew if these properties were required to fix the dreaded
reboot issue...
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-tinker.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
index f4b4525c..a0663425 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dts
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
@@ -601,7 +601,12 @@
disable-wp; /* wp not hooked up */
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
status = "okay";
+ supports-sd;
vmmc-supply = <&vcc33_sd>;
vqmmc-supply = <&vccio_sd>;
};
--
2.11.0

107
patch/kernel/rockchip-dev/2022-ARM-DTSI-rk3288-Define-the-VPU-services.patch Normal file
View file

@ -0,0 +1,107 @@
From f4480cb8198085607c15e523b49aa21bc38cf62c Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Tue, 21 Nov 2017 21:47:33 +0100
Subject: [PATCH 1/5] ARM: DTSI: rk3288.dtsi: Define the VPU services
Still, you will need appropriate drivers to use them.
Contrary to the previous versions of this patch, these services are :
* NOT enabled by default;
* MUST be activated in each individual DTS;
I currently do not own enough RK3288 boards to ensure that the
VPU and HEVC MMU + services can be activated without issues.
Still this patch does not generate issues like the previous one AND
still enable these services on boot, when activated properly in
individual DTS files.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288.dtsi | 63 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 63 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 30b04257..bc3601ac 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -1182,6 +1182,27 @@
status = "disabled";
};
+ vpu_service: vpu-service@ff9a0000 {
+ compatible = "rockchip,vpu_service";
+ reg = <0x0 0xff9a0000 0x0 0x800>;
+ interrupts =
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_enc", "irq_dec";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ power-domains = <&power RK3288_PD_VIDEO>;
+ rockchip,grf = <&grf>;
+ resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
+ reset-names = "video_a", "video_h";
+ iommus = <&vpu_mmu>;
+ iommu_enabled = <1>;
+ dev_mode = <0>;
+ status = "disabled";
+ /* 0 means ion, 1 means drm */
+ allocator = <1>;
+ };
+
hevc_mmu: iommu@ff9c0440 {
compatible = "rockchip,iommu";
reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
@@ -1191,6 +1212,48 @@
status = "disabled";
};
+ hevc_service: hevc-service@ff9c0000 {
+ compatible = "rockchip,hevc_service";
+ reg = <0x0 0xff9c0000 0x0 0x400>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_dec";
+ clocks =
+ <&cru ACLK_HEVC>,
+ <&cru HCLK_HEVC>,
+ <&cru SCLK_HEVC_CORE>,
+ <&cru SCLK_HEVC_CABAC>;
+ clock-names =
+ "aclk_vcodec",
+ "hclk_vcodec",
+ "clk_core",
+ "clk_cabac";
+ /*
+ * The 4K hevc would also work well with 500/125/300/300,
+ * no more err irq and reset request.
+ */
+ assigned-clocks =
+ <&cru ACLK_HEVC>,
+ <&cru HCLK_HEVC>,
+ <&cru SCLK_HEVC_CORE>,
+ <&cru SCLK_HEVC_CABAC>;
+ assigned-clock-rates =
+ <400000000>,
+ <100000000>,
+ <300000000>,
+ <300000000>;
+
+ resets = <&cru SRST_HEVC>;
+ reset-names = "video";
+ power-domains = <&power RK3288_PD_HEVC>;
+ rockchip,grf = <&grf>;
+ dev_mode = <1>;
+ iommus = <&hevc_mmu>;
+ iommu_enabled = <1>;
+ status = "disabled";
+ /* 0 means ion, 1 means drm */
+ allocator = <1>;
+ };
+
gpu: gpu@ffa30000 {
compatible = "rockchip,rk3288-mali", "arm,mali-t760";
reg = <0x0 0xffa30000 0x0 0x10000>;
--
2.14.1

57
patch/kernel/rockchip-dev/2023-ARM-DTS-rk3288-miqi-Enable-the-Video-encoding-MM.patch Normal file
View file

@ -0,0 +1,57 @@
From 647d6012849191e9909a8acb0fc9ae5df1afc747 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Tue, 21 Nov 2017 21:51:31 +0100
Subject: [PATCH 2/5] ARM: DTS: rk3288-miqi.dts: Enable the Video encoding MMU
and services
Enable the :
* VPU MMU;
* VPU service;
* HEVC MMU;
* HEVC service;
on MiQi devices.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-miqi.dts | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index d7fde483..dd785c70 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -124,7 +124,7 @@
};
- cpu0_opp_table: opp_table0 {
+ cpu0_opp_table: opp_table {
compatible = "operating-points-v2";
opp-shared;
@@ -575,6 +575,22 @@
status = "okay";
};
+&vpu_mmu {
+ status = "okay";
+};
+
+&vpu_service {
+ status = "okay";
+};
+
+&hevc_mmu {
+ status = "okay";
+};
+
+&hevc_service {
+ status = "okay";
+};
+
&wdt {
status = "okay";
};
--
2.14.1

48
patch/kernel/rockchip-dev/2024-ARM-DTS-rk3288-tinker-Enable-the-Video-encoding-MMU-.patch Normal file
View file

@ -0,0 +1,48 @@
From 092c26ead2eb4035a57217f8705c9deed3bfb927 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Tue, 21 Nov 2017 21:54:22 +0100
Subject: [PATCH 3/5] ARM: DTS: rk3288-tinker: Enable the Video encoding MMU
and services
Enable the :
* VPU MMU;
* VPU Service;
* HEVC MMU;
* HEVC Service;
for ASUS Tinkerboard devices.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-tinker.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
index a0663425..07b4af4f 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dts
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
@@ -671,6 +671,22 @@
status = "okay";
};
+&vpu_mmu {
+ status = "okay";
+};
+
+&vpu_service {
+ status = "okay";
+};
+
+&hevc_mmu {
+ status = "okay";
+};
+
+&hevc_service {
+ status = "okay";
+};
+
&wdt {
status = "okay";
};
--
2.14.1

49
patch/kernel/rockchip-dev/2025-ARM-DTSI-rk3288-firefly-Enable-the-Video-encoding-MM.patch Normal file
View file

@ -0,0 +1,49 @@
From 2769b0e656d849c5d652c75db71ce0faff1c0551 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Tue, 21 Nov 2017 21:56:45 +0100
Subject: [PATCH 4/5] ARM: DTSI: rk3288-firefly: Enable the Video encoding MMU
and services
Enable the :
* VPU MMU;
* VPU Service;
* HEVC MMU;
* HEVC Service;
for RK3288 Firefly devices.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-firefly.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi
index b9e6f3a9..9961acce 100644
--- a/arch/arm/boot/dts/rk3288-firefly.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly.dtsi
@@ -606,6 +606,23 @@
status = "okay";
};
+&vpu_mmu {
+ status = "okay";
+};
+
+&vpu_service {
+ status = "okay";
+};
+
+&hevc_mmu {
+ status = "okay";
+};
+
+&hevc_service {
+ status = "okay";
+};
+
&wdt {
status = "okay";
};
+
--
2.14.1

48
patch/kernel/rockchip-dev/2026-ARM-DTSI-rk3288-veyron-Enable-the-Video-encoding-MMU.patch Normal file
View file

@ -0,0 +1,48 @@
From 4766516bcbf023813ad883c2d61c422316770d12 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Tue, 21 Nov 2017 21:58:22 +0100
Subject: [PATCH 5/5] ARM: DTSI: rk3288-veyron: Enable the Video encoding MMU
and services
Enable the :
* VPU MMU;
* VPU Service;
* HEVC MMU;
* HEVC Service;
for RK3288 Chromebook laptops.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-veyron.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
index 6e5bd897..517b9242 100644
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
@@ -450,6 +450,22 @@
status = "okay";
};
+&vpu_mmu {
+ status = "okay";
+};
+
+&vpu_service {
+ status = "okay";
+};
+
+&hevc_mmu {
+ status = "okay";
+};
+
+&hevc_service {
+ status = "okay";
+};
+
&wdt {
status = "okay";
};
--
2.14.1

36
patch/kernel/rockchip-dev/8000_VPU_driver_load.patch
View file

@ -1,36 +0,0 @@
From 3a4f9e972d9723594d020b2785e3ec3ac148d02e Mon Sep 17 00:00:00 2001
From: Myy <myy@miouyouyou.fr>
Date: Tue, 17 Jan 2017 19:55:25 +0000
Subject: [PATCH 12/12] Export rockchip_pmu_set_idle_request for out-of-tree
VPU code
In order to compile the Rockchip VPU modules "out-of-tree", it is
necessary to export rockchip_pmu_set_idle_request.
I do not know why the "out-of-tree" VPU code needs it, though. There
might be way to avoid calling this function, and avoid exporting this
function.
Or, in reverse, it might be extremely useful for external modules to
be able to use the Rockchip Power Management interface directly and,
therefore, export all the functions in rockchip/pw_domains.c
Signed-off-by: Myy <myy@miouyouyou.fr>
---
drivers/soc/rockchip/pm_domains.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
index 796c46a..63a186b 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -178,6 +178,7 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
return 0;
}
+EXPORT_SYMBOL(rockchip_pmu_set_idle_request);
static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
{
--
2.10.2

9483
patch/kernel/rockchip-dev/8001_rk_vcodec_driver.patch
View file

File diff suppressed because it is too large Load diff

12
patch/kernel/rockchip-dev/9000-Add-Tinkerboard-DTS.patch
View file

@ -1,12 +0,0 @@
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0118084..9b79466 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -691,6 +691,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-firefly-beta.dtb \
rk3288-firefly.dtb \
rk3288-firefly-reload.dtb \
+ rk3288-miniarm.dtb \
rk3288-miqi.dtb \
rk3288-popmetal.dtb \
rk3288-r89.dtb \

13
patch/kernel/rockchip-dev/9002_tinker_spidev.patch
View file

@ -1,13 +0,0 @@
diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
index 9e2e099..3a0f0a7 100644
--- a/drivers/spi/spidev.c
+++ b/drivers/spi/spidev.c
@@ -697,7 +697,8 @@ static const struct of_device_id spidev_dt_ids[] = {
{ .compatible = "rohm,dh2228fv" },
{ .compatible = "lineartechnology,ltc2488" },
{ .compatible = "ge,achc" },
{ .compatible = "semtech,sx1301" },
+ { .compatible = "rockchip,spi_tinker" },
{},
};
MODULE_DEVICE_TABLE(of, spidev_dt_ids);

46
patch/kernel/rockchip-dev/9003_Tinker_DTS_DSI.patch
View file

@ -1,46 +0,0 @@
diff --git a/arch/arm/boot/dts/rk3288-miniarm.dts b/arch/arm/boot/dts/rk3288-miniarm.dts
index 348e9be..3896506 100644
--- a/arch/arm/boot/dts/rk3288-miniarm.dts
+++ b/arch/arm/boot/dts/rk3288-miniarm.dts
@@ -194,6 +194,16 @@
status = "ok";
};
+&mipi_dsi {
+ status = "okay";
+ mipi_panel: mipi-panel {
+ compatible ="asus,tc358762";
+ reg = <0>;
+ status = "okay";
+ };
+};
+
+
&hdmi {
ddc-i2c-bus = <&i2c5>;
status = "okay";
@@ -400,9 +410,15 @@
&i2c2 {
status = "okay";
+ afc0:af-controller@0 {
+ status = "okay";
+ compatible = "silicon touch,vm149C-v4l2-i2c-subdev";
+ reg = < 0x0c >;
+ };
+
eeprom:m24c08@50 {
- compatible = "at,24c08";
- reg = <0x50>;
+ compatible = "at,24c08";
+ reg = <0x50>;
};
};
@@ -626,6 +642,7 @@
};
&usb_host0_ehci {
+ no-relinquish-port;
status = "okay";
};

78
patch/kernel/rockchip-dev/9004_dtsi_VPU_HEVC.patch
View file

@ -1,78 +0,0 @@
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index fc2d6be..624416f 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -1143,6 +1143,73 @@
};
};
+ vpu: video-codec@ff9a0000 {
+ compatible = "rockchip,rk3288-vpu";
+ reg = <0xff9a0000 0x800>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu", "vdpu";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3288_PD_VIDEO>;
+ iommus = <&vpu_mmu>;
+ assigned-clocks = <&cru ACLK_VCODEC>;
+ assigned-clock-rates = <400000000>;
+ status = "disabled";
+ };
+
+ vpu_service: vpu-service@ff9a0000 {
+ compatible = "rockchip,vpu_service";
+ reg = <0xff9a0000 0x800>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_enc", "irq_dec";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ power-domains = <&power RK3288_PD_VIDEO>;
+ rockchip,grf = <&grf>;
+ resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
+ reset-names = "video_a", "video_h";
+ iommus = <&vpu_mmu>;
+ iommu_enabled = <1>;
+ dev_mode = <0>;
+ status = "disabled";
+ /* 0 means ion, 1 means drm */
+ allocator = <1>;
+ };
+
+ hevc_service: hevc-service@ff9c0000 {
+ compatible = "rockchip,hevc_service";
+ reg = <0xff9c0000 0x400>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_dec";
+ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
+ <&cru SCLK_HEVC_CORE>,
+ <&cru SCLK_HEVC_CABAC>;
+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
+ "clk_cabac";
+ /*
+ * The 4K hevc would also work well with 500/125/300/300,
+ * no more err irq and reset request.
+ */
+ assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
+ <&cru SCLK_HEVC_CORE>,
+ <&cru SCLK_HEVC_CABAC>;
+ assigned-clock-rates = <400000000>, <100000000>,
+ <300000000>, <300000000>;
+
+ resets = <&cru SRST_HEVC>;
+ reset-names = "video";
+ power-domains = <&power RK3288_PD_HEVC>;
+ rockchip,grf = <&grf>;
+ dev_mode = <1>;
+ iommus = <&hevc_mmu>;
+ iommu_enabled = <1>;
+ status = "disabled";
+ /* 0 means ion, 1 means drm */
+ allocator = <1>;
+ };
+
gpu: gpu@ffa30000 {
compatible = "rockchip,rk3288-mali", "arm,mali-t760";
reg = <0xffa30000 0x10000>;

145
patch/kernel/rockchip-dev/9005_DTS_IOMMU_IEP_ISP.patch
View file

@ -1,145 +0,0 @@
diff --git a/arch/arm/boot/dts/rk3288-miniarm.dts b/arch/arm/boot/dts/rk3288-miniarm.dts
index 3896506..a6c0ec1 100644
--- a/arch/arm/boot/dts/rk3288-miniarm.dts
+++ b/arch/arm/boot/dts/rk3288-miniarm.dts
@@ -642,7 +642,6 @@
};
&usb_host0_ehci {
- no-relinquish-port;
status = "okay";
};
@@ -684,7 +683,22 @@
status = "okay";
};
+&hevc_mmu {
+ status = "okay";
+};
+
&vpu_service {
status = "okay";
};
+&vpu_mmu {
+ status = "okay";
+};
+
+&iep_mmu {
+ status = "okay";
+};
+
+&isp_mmu {
+ status = "okay";
+};
\ No newline at end of file
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index 83bb2a2..52ec00c 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -588,3 +588,20 @@
&vpu_service {
status = "okay";
};
+
+&hevc_mmu {
+ status = "okay";
+};
+
+&vpu_mmu {
+ status = "okay";
+};
+
+&iep_mmu {
+ status = "okay";
+};
+
+&isp_mmu {
+ status = "okay";
+};
+
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 624416f..cfa5178 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -999,6 +1014,11 @@
reg = <2>;
remote-endpoint = <&mipi_in_vopb>;
};
+
+ vopb_out_lvds: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&lvds_in_vopb>;
+ };
};
};
@@ -1042,6 +1062,11 @@
reg = <2>;
remote-endpoint = <&mipi_in_vopl>;
};
+
+ vopl_out_lvds: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&lvds_in_vopl>;
+ };
};
};
@@ -1083,6 +1108,39 @@
};
};
+ lvds: lvds@ff96c000 {
+ compatible = "rockchip,rk3288-lvds";
+ reg = <0xff96c000 0x4000>;
+ clocks = <&cru PCLK_LVDS_PHY>;
+ clock-names = "pclk_lvds";
+ pinctrl-names = "lcdc";
+ pinctrl-0 = <&lcdc_ctl>;
+ power-domains = <&power RK3288_PD_VIO>;
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lvds_in: port@0 {
+ reg = <0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lvds_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_lvds>;
+ };
+ lvds_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_lvds>;
+ };
+ };
+ };
+ };
+
edp: dp@ff970000 {
compatible = "rockchip,rk3288-dp";
reg = <0xff970000 0x4000>;
@@ -1926,5 +1984,15 @@
rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
};
};
+
+ lcdc {
+ lcdc_ctl: lcdc-ctl {
+ rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
+ <1 25 RK_FUNC_1 &pcfg_pull_none>,
+ <1 26 RK_FUNC_1 &pcfg_pull_none>,
+ <1 27 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
};
};

31
patch/kernel/rockchip-dev/9006_thermal_zone_fix.patch
View file

@ -1,31 +0,0 @@
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index cfa5178..08c96e7 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -546,6 +546,7 @@
pinctrl-0 = <&otp_gpio>;
pinctrl-1 = <&otp_out>;
pinctrl-2 = <&otp_gpio>;
+ rockchip,grf = <&grf>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
status = "disabled";
@@ -1297,7 +1298,18 @@
clocks = <&cru ACLK_GPU>;
operating-points-v2 = <&gpu_opp_table>;
power-domains = <&power RK3288_PD_GPU>;
+ #cooling-cells = <2>; /* min followed by max */
status = "disabled";
+
+ gpu_power_model: power_model {
+ compatible = "arm,mali-simple-power-model";
+ voltage = <950>;
+ frequency = <500>;
+ static-power = <300>;
+ dynamic-power = <396>;
+ ts = <32000 4700 (-80) 2>;
+ thermal-zone = "gpu_thermal";
+ };
};
gpu_opp_table: gpu-opp-table {

31
patch/kernel/rockchip-dev/9007_rk3288_dtsi_arrange_thermal_zones.patch
View file

@ -1,31 +0,0 @@
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 08c96e7..bfd41a3 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -460,12 +460,6 @@
};
thermal-zones {
- reserve_thermal: reserve_thermal {
- polling-delay-passive = <1000>; /* milliseconds */
- polling-delay = <5000>; /* milliseconds */
-
- thermal-sensors = <&tsadc 0>;
- };
cpu_thermal: cpu_thermal {
polling-delay-passive = <100>; /* milliseconds */
@@ -532,6 +526,13 @@
};
};
};
+
+ reserve_thermal: reserve_thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&tsadc 0>;
+ };
};
tsadc: tsadc@ff280000 {

58
patch/kernel/rockchip-dev/9008_vop_fix_64bit.patch
View file

@ -1,58 +0,0 @@
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 8f980d7..f3e0ff4 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -990,7 +990,7 @@
vopb: vop@ff930000 {
compatible = "rockchip,rk3288-vop";
- reg = <0xff930000 0x19c>, <0xff931000 0x1000>;
+ reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@@ -1038,7 +1038,7 @@
vopl: vop@ff940000 {
compatible = "rockchip,rk3288-vop";
- reg = <0xff940000 0x19c>, <0xff941000 0x1000>;
+ reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@@ -1114,7 +1114,7 @@
lvds: lvds@ff96c000 {
compatible = "rockchip,rk3288-lvds";
- reg = <0xff96c000 0x4000>;
+ reg = <0x0 0xff96c000 0x0 0x4000>;
clocks = <&cru PCLK_LVDS_PHY>;
clock-names = "pclk_lvds";
pinctrl-names = "lcdc";
@@ -1224,7 +1224,7 @@
vpu: video-codec@ff9a0000 {
compatible = "rockchip,rk3288-vpu";
- reg = <0xff9a0000 0x800>;
+ reg = <0x0 0xff9a0000 0x0 0x800>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vepu", "vdpu";
@@ -1239,7 +1239,7 @@
vpu_service: vpu-service@ff9a0000 {
compatible = "rockchip,vpu_service";
- reg = <0xff9a0000 0x800>;
+ reg = <0x0 0xff9a0000 0x0 0x800>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_enc", "irq_dec";
@@ -1259,7 +1259,7 @@
hevc_service: hevc-service@ff9c0000 {
compatible = "rockchip,hevc_service";
- reg = <0xff9c0000 0x400>;
+ reg = <0x0 0xff9c0000 0x0 0x400>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,

0
patch/kernel/rockchip-next/1003-clk-rockchip-add-all-known-operating-points-to-the-a.patch → patch/kernel/rockchip-next/1002-clk-rockchip-add-all-known-operating-points-to-the-a.patch
View file

167
patch/kernel/rockchip-next/1002-fbdev-Mali-Add-the-FBIOGET_DMABUF-interface.patch
View file

@ -1,167 +0,0 @@
From 66c5bb20f8dd389496c40635625ae1132cdc686f Mon Sep 17 00:00:00 2001
From: Myy <myy@miouyouyou.fr>
Date: Sun, 30 Jul 2017 17:01:33 +0000
Subject: [PATCH 1/9] fbdev: Mali: Add the FBIOGET_DMABUF interface
I don't know if this interface is still useful. FBDEV will soon be
FBDEAD, since everyone is switching, for valid reasons, to the DRM
and Kernel Mode Setting interface.
This was added because the Mali FBDEV drivers need this interface.
Since the Mali FBDEV drivers are the only one that are Vulkan
compatible on RK3288 boards, I'm keeping it for the moment.
So this will stay until it can't be applied anymore. At the moment,
this patch will be removed.
Details about that interface can be found here :
https://www.community.arm.com/graphics/b/blog/posts/improving-arm-mali-drivers-on-fbdev
Signed-off-by: Myy <myy@miouyouyou.fr>
---
drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c | 21 ++++++++++++++++++
drivers/video/fbdev/core/fbmem.c | 31 +++++++++++++++++++++++++++
include/linux/fb.h | 2 ++
include/uapi/linux/fb.h | 6 ++++++
4 files changed, 60 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c
index ce946b9c..d63d0475 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c
@@ -35,6 +35,26 @@ static int rockchip_fbdev_mmap(struct fb_info *info,
return rockchip_gem_mmap_buf(private->fbdev_bo, vma);
}
+/* Mali driver specific API :
+ https://www.community.arm.com/graphics/b/blog/posts/improving-arm-mali-drivers-on-fbdev
+ I wonder if this problem isn't already solved in another way...
+ */
+static struct dma_buf *rockchip_fbdev_get_dma_buf(struct fb_info *info) {
+ struct dma_buf *buf = NULL;
+ struct drm_fb_helper *helper = info->par;
+ struct rockchip_drm_private *private = to_drm_private(helper);
+ struct drm_device *dev = helper->dev;
+
+ if (dev->driver->gem_prime_export) {
+ buf = dev->driver->gem_prime_export(dev, private->fbdev_bo, O_RDWR);
+ if (buf)
+ drm_gem_object_reference(private->fbdev_bo);
+ }
+
+ return buf;
+}
+
+
static struct fb_ops rockchip_drm_fbdev_ops = {
.owner = THIS_MODULE,
DRM_FB_HELPER_DEFAULT_OPS,
@@ -42,6 +62,7 @@ static struct fb_ops rockchip_drm_fbdev_ops = {
.fb_fillrect = drm_fb_helper_cfb_fillrect,
.fb_copyarea = drm_fb_helper_cfb_copyarea,
.fb_imageblit = drm_fb_helper_cfb_imageblit,
+ .fb_dmabuf_export = rockchip_fbdev_get_dma_buf
};
static int rockchip_drm_fbdev_create(struct drm_fb_helper *helper,
diff --git a/drivers/video/fbdev/core/fbmem.c b/drivers/video/fbdev/core/fbmem.c
index 7a42238d..61d1f3f8 100644
--- a/drivers/video/fbdev/core/fbmem.c
+++ b/drivers/video/fbdev/core/fbmem.c
@@ -31,6 +31,7 @@
#include <linux/err.h>
#include <linux/device.h>
#include <linux/efi.h>
+#include <linux/dma-buf.h> // Mali specific
#include <linux/fb.h>
#include <asm/fb.h>
@@ -1084,6 +1085,21 @@ fb_blank(struct fb_info *info, int blank)
}
EXPORT_SYMBOL(fb_blank);
+/* Mali specific */
+int fb_get_dmabuf(struct fb_info *info, int flags)
+{
+ struct dma_buf *dmabuf;
+
+ if (info->fbops->fb_dmabuf_export == NULL)
+ return -ENOTTY;
+
+ dmabuf = info->fbops->fb_dmabuf_export(info);
+ if (IS_ERR(dmabuf))
+ return PTR_ERR(dmabuf);
+
+ return dma_buf_fd(dmabuf, flags);
+}
+
static long do_fb_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
@@ -1094,6 +1110,7 @@ static long do_fb_ioctl(struct fb_info *info, unsigned int cmd,
struct fb_cmap cmap_from;
struct fb_cmap_user cmap;
struct fb_event event;
+ struct fb_dmabuf_export dmaexp;
void __user *argp = (void __user *)arg;
long ret = 0;
@@ -1199,6 +1216,20 @@ static long do_fb_ioctl(struct fb_info *info, unsigned int cmd,
unlock_fb_info(info);
console_unlock();
break;
+ case FBIOGET_DMABUF: /* Mali specific */
+ if (copy_from_user(&dmaexp, argp, sizeof(dmaexp)))
+ return -EFAULT;
+ if (!lock_fb_info(info))
+ return -ENODEV;
+ dmaexp.fd = fb_get_dmabuf(info, dmaexp.flags);
+ unlock_fb_info(info);
+
+ if (dmaexp.fd < 0)
+ return dmaexp.fd;
+
+ ret = copy_to_user(argp, &dmaexp, sizeof(dmaexp))
+ ? -EFAULT : 0;
+ break;
case FBIOBLANK:
console_lock();
if (!lock_fb_info(info)) {
diff --git a/include/linux/fb.h b/include/linux/fb.h
index a964d076..37a52dbb 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -320,6 +320,8 @@ struct fb_ops {
/* called at KDB enter and leave time to prepare the console */
int (*fb_debug_enter)(struct fb_info *info);
int (*fb_debug_leave)(struct fb_info *info);
+
+ struct dma_buf *(*fb_dmabuf_export)(struct fb_info *info);
};
#ifdef CONFIG_FB_TILEBLITTING
diff --git a/include/uapi/linux/fb.h b/include/uapi/linux/fb.h
index fb795c3b..c279b045 100644
--- a/include/uapi/linux/fb.h
+++ b/include/uapi/linux/fb.h
@@ -34,6 +34,8 @@
#define FBIOPUT_MODEINFO 0x4617
#define FBIOGET_DISPINFO 0x4618
#define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
+/* Mali specific */
+#define FBIOGET_DMABUF _IOR('F', 0x21, struct fb_dmabuf_export)
#define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */
#define FB_TYPE_PLANES 1 /* Non interleaved planes */
@@ -398,5 +400,9 @@ struct fb_cursor {
#define FB_BACKLIGHT_MAX 0xFF
#endif
+struct fb_dmabuf_export { /* Mali specific */
+ __u32 fd;
+ __u32 flags;
+};
#endif /* _UAPI_LINUX_FB_H */
--
2.13.0

0
patch/kernel/rockchip-next/1004-clk-rockchip-rk3288-prefer-vdpu-for-vcodec-clock-sou.patch → patch/kernel/rockchip-next/1003-clk-rockchip-rk3288-prefer-vdpu-for-vcodec-clock-sou.patch
View file

0
patch/kernel/rockchip-next/1005-Remove-the-dependency-to-the-clk_mali-symbol.patch → patch/kernel/rockchip-next/1004-Remove-the-dependency-to-the-clk_mali-symbol.patch
View file

82
patch/kernel/rockchip-dev/9300_Tinker_Reboot_Hacks.patch → patch/kernel/rockchip-next/1005-Reboot-patch-2-The-Return.patch
View file

@ -1,21 +1,36 @@
From 1aeeeeaf10ad5888c1a5b3ab9b780be91c7dada9 Mon Sep 17 00:00:00 2001
From: Myy <myy@miouyouyou.fr>
Date: Mon, 24 Jul 2017 23:09:31 +0000
Subject: [PATCH] Last try for the reboot hack
If this one does not work, get a refund for your CantRebootBoard.
Signed-off-by: Myy <myy@miouyouyou.fr>
---
drivers/mmc/host/dw_mmc-rockchip.c | 24 ++++++++++++++++++++++++
drivers/mmc/host/dw_mmc.c | 26 ++++++++++++++++++++++++++
include/linux/reboot.h | 3 +++
kernel/reboot.c | 1 +
4 files changed, 54 insertions(+)
diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c
index 372fb6e..a54c290 100644
index aaed6f9b..71131020 100644
--- a/drivers/mmc/host/dw_mmc-rockchip.c
+++ b/drivers/mmc/host/dw_mmc-rockchip.c
@@ -14,10 +14,12 @@
#include <linux/of_address.h>
#include <linux/mmc/slot-gpio.h>
#include <linux/pm_runtime.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/consumer.h> // Hack
#include <linux/slab.h>
#include "dw_mmc.h"
#include "dw_mmc-pltfm.h"
+#include "../core/core.h"
+#include "../core/core.h" // Hack
#define RK3288_CLKGEN_DIV 2
@@ -353,6 +355,27 @@ static int dw_mci_rockchip_probe(struct platform_device *pdev)
@@ -365,6 +367,27 @@ static int dw_mci_rockchip_probe(struct platform_device *pdev)
return 0;
}
@ -37,13 +52,13 @@ index 372fb6e..a54c290 100644
+ if (!IS_ERR(mmc->supply.vqmmc))
+ regulator_set_voltage(mmc->supply.vqmmc, 3000000, 3300000);
+ }
+
+}
+
+
static int dw_mci_rockchip_remove(struct platform_device *pdev)
{
pm_runtime_get_sync(&pdev->dev);
@@ -373,6 +396,7 @@ static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
@@ -385,6 +408,7 @@ static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
static struct platform_driver dw_mci_rockchip_pltfm_driver = {
.probe = dw_mci_rockchip_probe,
.remove = dw_mci_rockchip_remove,
@ -52,74 +67,80 @@ index 372fb6e..a54c290 100644
.name = "dwmmc_rockchip",
.of_match_table = dw_mci_rockchip_match,
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index e45129f..faad52d 100644
index a9dfb269..ee956a57 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -39,8 +39,10 @@
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/mmc/slot-gpio.h>
+#include <linux/reboot.h>
+#include <linux/reboot.h> // Hack
#include "dw_mmc.h"
+#include "../core/core.h"
+#include "../core/core.h" // Hack
/* Common flag combinations */
#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
@@ -2686,6 +2688,30 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
@@ -2687,6 +2689,28 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
return IRQ_HANDLED;
}
+struct dw_mci *mSdhost;
+
+void setmmcEmergency() {
+
+ struct mmc_host *mmc = mSdhost->slot->mmc;
+ struct mmc_host *mmc;
+ int ret;
+
+ if(of_machine_is_compatible("asus,rk3288-tinker")){
+ printk(KERN_ERR "Emergency route taken.\n");
+ if (of_machine_is_compatible("asus,rk3288-tinker")) {
+ mmc = mSdhost->slot->mmc;
+
+ mmc_power_off(mmc);
+
+ mdelay(20);
+
+ if (!IS_ERR(mmc->supply.vmmc)) {
+ if (!IS_ERR(mmc->supply.vmmc))
+ ret = regulator_enable(mmc->supply.vmmc);
+ }
+
+ if (!IS_ERR(mmc->supply.vqmmc))
+ regulator_set_voltage(mmc->supply.vqmmc, 3000000, 3300000);
+ }
+
+}
+
+EXPORT_SYMBOL(setmmcEmergency);
static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
+
static int dw_mci_init_slot(struct dw_mci *host)
{
@@ -2717,6 +2743,8 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
mmc->f_min = freq[0];
struct mmc_host *mmc;
@@ -2718,6 +2742,8 @@ static int dw_mci_init_slot(struct dw_mci *host)
mmc->f_max = freq[1];
}
+ if (of_find_property(host->dev->of_node, "supports-sd", NULL))
+ mSdhost = host;
+ if (of_find_property(host->dev->of_node, "supports-sd", NULL))
+ mSdhost = host;
/*if there are external regulators, get them*/
ret = mmc_regulator_get_supply(mmc);
if (ret == -EPROBE_DEFER)
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index a7ff409..e045bc2 100644
index a7ff409f..586e4504 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -73,6 +73,7 @@ extern char poweroff_cmd[POWEROFF_CMD_PATH_LEN];
@@ -72,12 +72,15 @@ extern char poweroff_cmd[POWEROFF_CMD_PATH_LEN];
extern void orderly_poweroff(bool force);
extern void orderly_reboot(void);
+// Wonderful ASUS hack
+extern void setmmcEmergency(void);
/*
* Emergency restart, callable from an interrupt handler.
*/
extern void emergency_restart(void);
+
#include <asm/emergency-restart.h>
#endif /* _LINUX_REBOOT_H */
diff --git a/kernel/reboot.c b/kernel/reboot.c
index bd30a97..9f99488 100644
index bd30a973..9f99488f 100644
--- a/kernel/reboot.c
+++ b/kernel/reboot.c
@@ -61,6 +61,7 @@ void (*pm_power_off_prepare)(void);
@ -130,3 +151,6 @@ index bd30a97..9f99488 100644
machine_emergency_restart();
}
EXPORT_SYMBOL_GPL(emergency_restart);
--
2.13.0

0
patch/kernel/rockchip-next/1008-rockchip-rga-v4l2-m2m-support.patch → patch/kernel/rockchip-next/1006-rockchip-rga-v4l2-m2m-support.patch
View file

92
patch/kernel/rockchip-next/1006-soc-rockchip-power-domain-export-idle-request.patch
View file

@ -1,92 +0,0 @@
From f723bec5d7c860901ddae1634094d55bad2b8a4d Mon Sep 17 00:00:00 2001
From: Randy Li <ayaka@soulik.info>
Date: Tue, 9 May 2017 00:34:17 +0800
Subject: [PATCH 7/9] soc: rockchip: power-domain: export idle request
We need to put the power status of HEVC/RKVDEC IP into IDLE
unless we can't reset that IP or the SoC would crash down.
rockchip_pmu_idle_request(dev, true)---> enter idle
rockchip_pmu_idle_request(dev, false)---> exit idle
Only the video codec drivers of rockchip platform would
request this patch currently.
I am not sure whether it is necessary to add a new function
at generic power domain. I want someone give me some advises
here.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Randy Li <ayaka@soulik.info>
---
drivers/soc/rockchip/pm_domains.c | 24 ++++++++++++++++++++++++
include/linux/rockchip_pmu.h | 15 +++++++++++++++
2 files changed, 39 insertions(+)
create mode 100644 include/linux/rockchip_pmu.h
diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
index 796c46a6..c1bff1c8 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -18,6 +18,7 @@
#include <linux/clk.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
+#include <linux/rockchip_pmu.h>
#include <dt-bindings/power/rk3288-power.h>
#include <dt-bindings/power/rk3328-power.h>
#include <dt-bindings/power/rk3368-power.h>
@@ -179,6 +180,29 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
return 0;
}
+int rockchip_pmu_idle_request(struct device *dev, bool idle)
+{
+ struct generic_pm_domain *genpd;
+ struct rockchip_pm_domain *pd;
+ int ret;
+
+ if (IS_ERR_OR_NULL(dev))
+ return -EINVAL;
+
+ if (IS_ERR_OR_NULL(dev->pm_domain))
+ return -EINVAL;
+
+ genpd = pd_to_genpd(dev->pm_domain);
+ pd = to_rockchip_pd(genpd);
+
+ mutex_lock(&pd->pmu->mutex);
+ ret = rockchip_pmu_set_idle_request(pd, idle);
+ mutex_unlock(&pd->pmu->mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL(rockchip_pmu_idle_request);
+
static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
{
int i;
diff --git a/include/linux/rockchip_pmu.h b/include/linux/rockchip_pmu.h
new file mode 100644
index 00000000..720b3314
--- /dev/null
+++ b/include/linux/rockchip_pmu.h
@@ -0,0 +1,15 @@
+/*
+ * pm_domain.h - Definitions and headers related to device power domains.
+ *
+ * Copyright (C) 2017 Randy Li <ayaka@soulik.info>.
+ *
+ * This file is released under the GPLv2.
+ */
+
+#ifndef _LINUX_ROCKCHIP_PM_H
+#define _LINUX_ROCKCHIP_PM_H
+#include <linux/device.h>
+
+int rockchip_pmu_idle_request(struct device *dev, bool idle);
+
+#endif /* _LINUX_ROCKCHIP_PM_H */
--
2.13.0

0
patch/kernel/rockchip-next/1009-dt-bindings-Document-the-Rockchip-RGA-bindings.patch → patch/kernel/rockchip-next/1007-dt-bindings-Document-the-Rockchip-RGA-bindings.patch
View file

339
patch/kernel/rockchip-next/1010-Rockchip-DRM-GEM-Prime-import-SG-Table-Support.patch
View file

@ -1,339 +0,0 @@
From e6e383f45f59fdd935a2b13b1e9b00968ac5a1aa Mon Sep 17 00:00:00 2001
From: Myy <myy@miouyouyou.fr>
Date: Sun, 30 Jul 2017 17:32:26 +0000
Subject: [PATCH 2/9] Rockchip DRM: GEM Prime import SG Table Support
A combination of an old patch provided by the ARM developers and the
patches provided by Rockchip and @wzyy2.
This patch provide a Rockchip specific implementation for the Rockchip
DRM driver gem_prime_import_sg_table call.
Signed-off-by: Myy <myy@miouyouyou.fr>
---
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 10 +++
drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 133 ++++++++++++++++++++++++++--
drivers/gpu/drm/rockchip/rockchip_drm_gem.h | 9 +-
include/uapi/drm/rockchip_drm.h | 57 ++++++++++++
4 files changed, 199 insertions(+), 10 deletions(-)
create mode 100644 include/uapi/drm/rockchip_drm.h
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
index c6b1b7f3..a261948f 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
@@ -19,6 +19,7 @@
#include <drm/drm_fb_helper.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_of.h>
+#include <drm/rockchip_drm.h>
#include <linux/dma-mapping.h>
#include <linux/dma-iommu.h>
#include <linux/pm_runtime.h>
@@ -217,6 +218,12 @@ static void rockchip_drm_lastclose(struct drm_device *dev)
drm_fb_helper_restore_fbdev_mode_unlocked(&priv->fbdev_helper);
}
+static const struct drm_ioctl_desc rockchip_ioctls[] = {
+ DRM_IOCTL_DEF_DRV(ROCKCHIP_GEM_CREATE, rockchip_gem_create_ioctl,
+ DRM_UNLOCKED | DRM_AUTH),
+};
+
+
static const struct file_operations rockchip_drm_driver_fops = {
.owner = THIS_MODULE,
.open = drm_open,
@@ -239,12 +246,15 @@ static struct drm_driver rockchip_drm_driver = {
.dumb_destroy = drm_gem_dumb_destroy,
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
+ .gem_prime_import_sg_table = rockchip_gem_prime_import_sg_table,
.gem_prime_import = drm_gem_prime_import,
.gem_prime_export = drm_gem_prime_export,
.gem_prime_get_sg_table = rockchip_gem_prime_get_sg_table,
.gem_prime_vmap = rockchip_gem_prime_vmap,
.gem_prime_vunmap = rockchip_gem_prime_vunmap,
.gem_prime_mmap = rockchip_gem_mmap_buf,
+ .ioctls = rockchip_ioctls,
+ .num_ioctls = ARRAY_SIZE(rockchip_ioctls),
.fops = &rockchip_drm_driver_fops,
.name = DRIVER_NAME,
.desc = DRIVER_DESC,
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
index b74ac717..05dfdbed 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
@@ -16,7 +16,12 @@
#include <drm/drmP.h>
#include <drm/drm_gem.h>
#include <drm/drm_vma_manager.h>
+#include <drm/rockchip_drm.h>
+
#include <linux/iommu.h>
+#include <linux/dma-mapping.h>
+#include <linux/dma-buf.h>
+
#include "rockchip_drm_drv.h"
#include "rockchip_drm_gem.h"
@@ -309,12 +314,10 @@ static void rockchip_gem_release_object(struct rockchip_gem_object *rk_obj)
}
struct rockchip_gem_object *
- rockchip_gem_create_object(struct drm_device *drm, unsigned int size,
- bool alloc_kmap)
+rockchip_gem_alloc_object(struct drm_device *drm, unsigned int size)
{
struct rockchip_gem_object *rk_obj;
struct drm_gem_object *obj;
- int ret;
size = round_up(size, PAGE_SIZE);
@@ -325,6 +328,19 @@ struct rockchip_gem_object *
obj = &rk_obj->base;
drm_gem_object_init(drm, obj, size);
+ return rk_obj;
+}
+
+struct rockchip_gem_object *
+rockchip_gem_create_object(struct drm_device *drm, unsigned int size,
+ bool alloc_kmap)
+{
+ struct rockchip_gem_object *rk_obj;
+ int ret;
+
+ rk_obj = rockchip_gem_alloc_object(drm, size);
+ if (IS_ERR(rk_obj))
+ return rk_obj;
ret = rockchip_gem_alloc_buf(rk_obj, alloc_kmap);
if (ret)
@@ -343,13 +359,24 @@ struct rockchip_gem_object *
*/
void rockchip_gem_free_object(struct drm_gem_object *obj)
{
- struct rockchip_gem_object *rk_obj;
-
- rk_obj = to_rockchip_obj(obj);
+ struct drm_device *drm = obj->dev;
+ struct rockchip_drm_private *private = drm->dev_private;
+ struct rockchip_gem_object *rk_obj = to_rockchip_obj(obj);
- rockchip_gem_free_buf(rk_obj);
+ if (obj->import_attach) {
+ if (private->domain) {
+ rockchip_gem_iommu_unmap(rk_obj);
+ } else {
+ dma_unmap_sg(
+ drm->dev, rk_obj->sgt->sgl,
+ rk_obj->sgt->nents, DMA_BIDIRECTIONAL
+ );
+ }
+ drm_prime_gem_destroy(obj, rk_obj->sgt);
+ } else {
+ rockchip_gem_free_buf(rk_obj);
+ }
- rockchip_gem_release_object(rk_obj);
}
/*
@@ -445,6 +472,16 @@ int rockchip_gem_dumb_create(struct drm_file *file_priv,
return PTR_ERR_OR_ZERO(rk_obj);
}
+int rockchip_gem_create_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv) {
+ struct drm_rockchip_gem_create *args = data;
+ struct rockchip_gem_object *rk_obj;
+
+ rk_obj = rockchip_gem_create_with_handle(file_priv, dev, args->size,
+ &args->handle);
+ return PTR_ERR_OR_ZERO(rk_obj);
+}
+
/*
* Allocate a sg_table for this GEM object.
* Note: Both the table's contents, and the sg_table itself must be freed by
@@ -477,6 +514,86 @@ struct sg_table *rockchip_gem_prime_get_sg_table(struct drm_gem_object *obj)
return sgt;
}
+static unsigned long rockchip_sg_get_contiguous_size(struct sg_table *sgt,
+ int count)
+{
+ struct scatterlist *s;
+ dma_addr_t expected = sg_dma_address(sgt->sgl);
+ unsigned int i;
+ unsigned long size = 0;
+
+ for_each_sg(sgt->sgl, s, count, i) {
+ if (sg_dma_address(s) != expected)
+ break;
+ expected = sg_dma_address(s) + sg_dma_len(s);
+ size += sg_dma_len(s);
+ }
+ return size;
+}
+
+static int
+rockchip_gem_iommu_map_sg(struct drm_device *drm,
+ struct dma_buf_attachment *attach,
+ struct sg_table *sg,
+ struct rockchip_gem_object *rk_obj)
+{
+ rk_obj->sgt = sg;
+ return rockchip_gem_iommu_map(rk_obj);
+}
+
+static int
+rockchip_gem_dma_map_sg(struct drm_device *drm,
+ struct dma_buf_attachment *attach,
+ struct sg_table *sg,
+ struct rockchip_gem_object *rk_obj)
+{
+ int count = dma_map_sg(drm->dev, sg->sgl, sg->nents,
+ DMA_BIDIRECTIONAL);
+ if (!count)
+ return -EINVAL;
+
+ if (rockchip_sg_get_contiguous_size(sg, count) < attach->dmabuf->size) {
+ DRM_ERROR("failed to map sg_table to contiguous linear address.\n");
+ dma_unmap_sg(drm->dev, sg->sgl, sg->nents,
+ DMA_BIDIRECTIONAL);
+ return -EINVAL;
+ }
+
+ rk_obj->dma_addr = sg_dma_address(sg->sgl);
+ rk_obj->sgt = sg;
+ return 0;
+}
+
+struct drm_gem_object *
+rockchip_gem_prime_import_sg_table(struct drm_device *drm,
+ struct dma_buf_attachment *attach,
+ struct sg_table *sg)
+{
+ struct rockchip_drm_private *private = drm->dev_private;
+ struct rockchip_gem_object *rk_obj;
+ int ret;
+
+ rk_obj = rockchip_gem_alloc_object(drm, attach->dmabuf->size);
+ if (IS_ERR(rk_obj))
+ return ERR_CAST(rk_obj);
+
+ if (private->domain)
+ ret = rockchip_gem_iommu_map_sg(drm, attach, sg, rk_obj);
+ else
+ ret = rockchip_gem_dma_map_sg(drm, attach, sg, rk_obj);
+
+ if (ret < 0) {
+ DRM_ERROR("failed to import sg table: %d\n", ret);
+ goto err_free_rk_obj;
+ }
+
+ return &rk_obj->base;
+
+err_free_rk_obj:
+ rockchip_gem_release_object(rk_obj);
+ return ERR_PTR(ret);
+}
+
void *rockchip_gem_prime_vmap(struct drm_gem_object *obj)
{
struct rockchip_gem_object *rk_obj = to_rockchip_obj(obj);
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h
index 3f6ea4d1..b8fed4df 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h
@@ -36,8 +36,9 @@ struct rockchip_gem_object {
struct sg_table *rockchip_gem_prime_get_sg_table(struct drm_gem_object *obj);
struct drm_gem_object *
-rockchip_gem_prime_import_sg_table(struct drm_device *dev, size_t size,
- struct sg_table *sgt);
+rockchip_gem_prime_import_sg_table(struct drm_device *dev,
+ struct dma_buf_attachment *attach,
+ struct sg_table *sgt);
void *rockchip_gem_prime_vmap(struct drm_gem_object *obj);
void rockchip_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
@@ -57,6 +58,10 @@ void rockchip_gem_free_object(struct drm_gem_object *obj);
int rockchip_gem_dumb_create(struct drm_file *file_priv,
struct drm_device *dev,
struct drm_mode_create_dumb *args);
+int rockchip_gem_create_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
+int rockchip_gem_map_offset_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
int rockchip_gem_dumb_map_offset(struct drm_file *file_priv,
struct drm_device *dev, uint32_t handle,
uint64_t *offset);
diff --git a/include/uapi/drm/rockchip_drm.h b/include/uapi/drm/rockchip_drm.h
new file mode 100644
index 00000000..c521e5a3
--- /dev/null
+++ b/include/uapi/drm/rockchip_drm.h
@@ -0,0 +1,57 @@
+/*
+ *
+ * Copyright (c) Fuzhou Rockchip Electronics Co.Ltd
+ * Authors:
+ * Mark Yao <yzq@rock-chips.com>
+ *
+ * base on exynos_drm.h
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef _UAPI_ROCKCHIP_DRM_H
+#define _UAPI_ROCKCHIP_DRM_H
+
+#include <drm/drm.h>
+
+/**
+ * User-desired buffer creation information structure.
+ *
+ * @size: user-desired memory allocation size.
+ * @flags: user request for setting memory type or cache attributes.
+ * @handle: returned a handle to created gem object.
+ * - this handle will be set by gem module of kernel side.
+ */
+struct drm_rockchip_gem_create {
+ uint64_t size;
+ uint32_t flags;
+ uint32_t handle;
+};
+
+/**
+ * A structure for getting buffer offset.
+ *
+ * @handle: a pointer to gem object created.
+ * @pad: just padding to be 64-bit aligned.
+ * @offset: relatived offset value of the memory region allocated.
+ * - this value should be set by user.
+ */
+struct drm_rockchip_gem_map_off {
+ uint32_t handle;
+ uint32_t pad;
+ uint64_t offset;
+};
+
+#define DRM_ROCKCHIP_GEM_CREATE 0x00
+#define DRM_ROCKCHIP_GEM_MAP_OFFSET 0x01
+
+#define DRM_IOCTL_ROCKCHIP_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
+ DRM_ROCKCHIP_GEM_CREATE, struct drm_rockchip_gem_create)
+
+#define DRM_IOCTL_ROCKCHIP_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \
+ DRM_ROCKCHIP_GEM_MAP_OFFSET, struct drm_rockchip_gem_map_off)
+
+#endif /* _UAPI_ROCKCHIP_DRM_H */
--
2.13.0

80
patch/kernel/rockchip-next/1011-drm_fourcc-Add-new-P010-P016-video-format.patch
View file

@ -1,80 +0,0 @@
From 4e19e2a197570d60e188f7cf0e62d375eab68103 Mon Sep 17 00:00:00 2001
From: Randy Li <ayaka@soulik.info>
Date: Sun, 5 Mar 2017 18:00:31 +0800
Subject: [PATCH 8/9] drm_fourcc: Add new P010, P016 video format
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits
per channel video format.
P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits
per channel video format.
V3: Added P012 and fixed cpp for P010
V4: format definition refined per review
V5: Format comment block for each new pixel format
V6: reversed Cb/Cr order in comments
v7: reversed Cb/Cr order in comments of header files, remove
the wrong part of commit message.
Cc: Daniel Stone <daniel@fooishbar.org>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
include/uapi/drm/drm_fourcc.h | 21 +++++++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 9c0152df..61015204 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -173,6 +173,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+ { .format = DRM_FORMAT_P012, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+ { .format = DRM_FORMAT_P016, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 7586c46f..15a94c79 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -142,6 +142,27 @@ extern "C" {
#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y:x [10:6] little endian
+ * index 1 = Cb:Cr plane, [31:0] Cb:x:Cr:x [10:6:10:6] little endian
+ */
+#define DRM_FORMAT_P010 fourcc_code('N', 'A', '1', '2') /* 2x2 subsampled Cb:Cr plane 10 bits per channel */
+
+/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y:x [12:4] little endian
+ * index 1 = Cb:Cr plane, [31:0] Cb:x:Cr:x [12:4:12:4] little endian
+ */
+#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cb:Cr plane 12 bits per channel */
+
+/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y little endian
+ * index 1 = Cb:Cr plane, [31:0] Cb:Cr [16:16] little endian
+ */
+#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cb:Cr plane 16 bits per channel */
+
+/*
* 3 plane YCbCr
* index 0: Y plane, [7:0] Y
* index 1: Cb plane, [7:0] Cb
--
2.13.0

31
patch/kernel/rockchip-next/1012-net-stmmac-Reverting-a-part-of-Use-the-right-logging.patch
View file

@ -1,31 +0,0 @@
From ead80e80c41a4c1275543c3c7c2d22ff1c19717a Mon Sep 17 00:00:00 2001
From: Myy <myy@miouyouyou.fr>
Date: Mon, 21 Aug 2017 06:22:15 +0000
Subject: [PATCH] net: stmmac: Reverting a part of "Use the right logging
function"
Turns out that the phy_attached_info call, added in commit
fbca164776e438b639af592c522b8b0506b54dcc provokes a crash on boot
with MiQi devices.
Signed-off-by: Myy <myy@miouyouyou.fr>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
index 72ec711f..889810f0 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
@@ -286,7 +286,7 @@ int stmmac_mdio_register(struct net_device *ndev)
irq_str = irq_num;
break;
}
- phy_attached_info(phydev);
+ //phy_attached_info(phydev);
found = 1;
}
--
2.13.0

34
patch/kernel/rockchip-next/2001-Enabling-the-Mali-GPU-nodes-in-the-MiQi-and-Tinkerbo.patch
View file

@ -1,34 +0,0 @@
From 4b91f1b6cdd50bec47507704c127bbc913aeefe4 Mon Sep 17 00:00:00 2001
From: Myy <myy@miouyouyou.fr>
Date: Tue, 18 Jul 2017 02:25:27 +0000
Subject: [PATCH] Enabling the Mali GPU nodes in the MiQi and Tinkerboard DTS
files
These will be enabled in upcoming arm-soc patches. Meanwhile, they're
enabled through this patch.
Signed-off-by: Myy <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-miqi.dts | 5 +++++
arch/arm/boot/dts/rk3288-tinker.dts | 5 +++++
2 files changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index c165eec..29b94a0 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -150,6 +150,11 @@
status = "ok";
};
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
&hdmi {
ddc-i2c-bus = <&i2c5>;
status = "okay";
--
2.10.2

35
patch/kernel/rockchip-next/2001-dts-rk3288-miqi-Enabling-the-Mali-GPU-node.patch Normal file
View file

@ -0,0 +1,35 @@
From 604ea7fc311af2b3a41e7fe3b4fbde0ee03dfb9c Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 21:09:50 +0200
Subject: [PATCH 04/28] dts: rk3288: miqi: Enabling the Mali GPU node
Why is the MiQi the only one left without a working mali GPU node ?
Seriously, is there a rk3288 chipset WITHOUT a mali GPU ? Couldn't
they enable it once in the DTSI, instead of defining it as "disabled"
and enabling it in every DTS file ?
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-miqi.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index 4d923aa6..3cd60674 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -149,6 +149,11 @@
status = "ok";
};
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
&hdmi {
ddc-i2c-bus = <&i2c5>;
status = "okay";
--
2.11.0

12
patch/kernel/rockchip-next/2002-ARM-dts-rockchip-fix-the-regulator-s-voltage-range-o.patch
View file

@ -1,7 +1,7 @@
From 69515aeb405daf9b9767209d63a38f68a6e2521d Mon Sep 17 00:00:00 2001
From 89e5763110ca77d68a4be00cd97a638adc2401d5 Mon Sep 17 00:00:00 2001
From: Willy Tarreau <w@1wt.eu>
Date: Tue, 2 Aug 2016 08:31:00 +0200
Subject: [PATCH 05/12] ARM: dts: rockchip: fix the regulator's voltage range
Subject: [PATCH 05/28] ARM: dts: rockchip: fix the regulator's voltage range
on MiQi board
The board declared too narrow a voltage range for the CPU and GPU
@ -15,10 +15,10 @@ Signed-off-by: Willy Tarreau <w@1wt.eu>
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index cc42be5..43728c9 100644
index 3cd60674..a1c3cdaa 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -166,8 +166,8 @@
@@ -168,8 +168,8 @@
fcs,suspend-voltage-selector = <1>;
reg = <0x40>;
regulator-name = "vdd_cpu";
@ -29,7 +29,7 @@ index cc42be5..43728c9 100644
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <300>;
@@ -180,8 +180,8 @@
@@ -182,8 +182,8 @@
fcs,suspend-voltage-selector = <1>;
reg = <0x41>;
regulator-name = "vdd_gpu";
@ -41,5 +41,5 @@ index cc42be5..43728c9 100644
vin-supply = <&vcc_sys>;
};
--
2.10.2
2.11.0

9
patch/kernel/rockchip-dev/2003-Adaptation-ARM-dts-rockchip-add-the-MiQi-board-s-fan.patch → patch/kernel/rockchip-next/2003-ARM-dts-rockchip-add-the-MiQi-board-s-fan-definition.patch
View file

@ -1,8 +1,7 @@
From 112ef8de95b8b4287de14f7e5c9853cbbf3e69b0 Mon Sep 17 00:00:00 2001
From c27e445527e949f3ef46d5326066196969c17d23 Mon Sep 17 00:00:00 2001
From: Myy <myy@miouyouyou.fr>
Date: Sun, 12 Mar 2017 19:43:15 +0000
Subject: [PATCH 07/12] [Adaptation] ARM: dts: rockchip: add the MiQi board's
fan definition
Subject: [PATCH 06/28] ARM: dts: rockchip: add the MiQi board's fan definition
The MiQi board is sold with an enclosure in which a fan is connected
to the second LED output, and configured by default in "heartbeat"
@ -25,7 +24,7 @@ Signed-off-by: Myy <myy@miouyouyou.fr>
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index 7a42069..3132829 100644
index a1c3cdaa..0e383595 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -67,6 +67,13 @@
@ -43,5 +42,5 @@ index 7a42069..3132829 100644
gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
label = "miqi:green:user";
--
2.10.2
2.11.0

8
patch/kernel/rockchip-next/2004-ARM-dts-rockchip-add-support-for-1800-MHz-operation-.patch
View file

@ -1,7 +1,7 @@
From 266b439288e86b26e4cc524b92f1e0683ae913f0 Mon Sep 17 00:00:00 2001
From e7e092be197c51b4d222a3b4e6638318067b7e6a Mon Sep 17 00:00:00 2001
From: Willy Tarreau <w@1wt.eu>
Date: Tue, 2 Aug 2016 08:20:53 +0200
Subject: [PATCH 08/12] ARM: dts: rockchip: add support for 1800 MHz operation
Subject: [PATCH 07/28] ARM: dts: rockchip: add support for 1800 MHz operation
on MiQi board
This board happily supports 1800 MHz operations (and even more), so
@ -14,7 +14,7 @@ Signed-off-by: Willy Tarreau <w@1wt.eu>
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index 3132829..db5fcd4 100644
index 0e383595..80603a3d 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -126,6 +126,18 @@
@ -37,5 +37,5 @@ index 3132829..db5fcd4 100644
&emmc {
--
2.10.2
2.11.0

8
patch/kernel/rockchip-next/2005-Readapt-ARM-dts-rockchip-miqi-add-turbo-mode-operati.patch
View file

@ -1,7 +1,7 @@
From 7dfb0c2748133e40ae11d6f800550d3b00a8a22d Mon Sep 17 00:00:00 2001
From de9dcd5ecab0686022eee243464f35d2c7a34c97 Mon Sep 17 00:00:00 2001
From: Myy <myy@miouyouyou.fr>
Date: Mon, 16 Jan 2017 12:44:56 +0000
Subject: [PATCH 10/12] Readapt: ARM: dts: rockchip: miqi: add turbo-mode
Subject: [PATCH 08/28] Readapt: ARM: dts: rockchip: miqi: add turbo-mode
operating points
Readaptation of Willy Tarreau patch.
@ -32,7 +32,7 @@ Signed-off-by: Myy <myy@miouyouyou.fr>
1 file changed, 107 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index db5fcd4..bd27f91 100644
index 80603a3d..d7fde483 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -122,22 +122,116 @@
@ -166,5 +166,5 @@ index db5fcd4..bd27f91 100644
&emmc {
--
2.10.2
2.11.0

61
patch/kernel/rockchip-next/2006-ARM-DTSI-rk3288-Missing-GRF-handles.patch Normal file
View file

@ -0,0 +1,61 @@
From 771bcfe1735e42650b763e52a042a9fd98b2fa5b Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 21:20:43 +0200
Subject: [PATCH 09/28] ARM: DTSI: rk3288.dtsi: Missing GRF handles
Add missing GRF handles.
This patch is taken from the patches provided by the ARMbian team.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 356ed1e6..5b789528 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -547,6 +547,7 @@
pinctrl-2 = <&otp_gpio>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
+ rockchip,grf = <&grf>;
status = "disabled";
};
@@ -655,6 +656,7 @@
pinctrl-0 = <&pwm0_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
+ rockchip,grf = <&grf>;
status = "disabled";
};
@@ -666,6 +668,7 @@
pinctrl-0 = <&pwm1_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
+ rockchip,grf = <&grf>;
status = "disabled";
};
@@ -677,6 +680,7 @@
pinctrl-0 = <&pwm2_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
+ rockchip,grf = <&grf>;
status = "disabled";
};
@@ -688,6 +692,7 @@
pinctrl-0 = <&pwm3_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
+ rockchip,grf = <&grf>;
status = "disabled";
};
--
2.11.0

31
patch/kernel/rockchip-next/2007-RK3288-DTSI-rk3288-Add-missing-SPI2-pinctrl.patch Normal file
View file

@ -0,0 +1,31 @@
From 062488e4b8fd552c01e1104b3bc91a6f7ffe6c41 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 21:24:47 +0200
Subject: [PATCH 10/28] RK3288: DTSI: rk3288.dtsi: Add missing SPI2 pinctrl
The spi2_cs1 pin reference is missing in the spi2 first pin control
definition.
This patch is taken from the patches provided by the ARMbian team.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 5b789528..9ed532cc 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -334,7 +334,7 @@
dma-names = "tx", "rx";
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
+ pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0 &spi2_cs1>;
reg = <0x0 0xff130000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
--
2.11.0

27
patch/kernel/rockchip-next/2008-Added-support-for-Tinkerboard-s-SPI-interface.patch Normal file
View file

@ -0,0 +1,27 @@
From af8d73ec0df1dde1e2fe1674c5708d4c30385ba9 Mon Sep 17 00:00:00 2001
From: Myy <myy@miouyouyou.fr>
Date: Mon, 5 Jun 2017 12:37:17 +0000
Subject: [PATCH 11/28] Added support for Tinkerboard's SPI interface
Imported from ARMbian
Signed-off-by: Myy <myy@miouyouyou.fr>
---
drivers/spi/spidev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
index cda10719..a6287475 100644
--- a/drivers/spi/spidev.c
+++ b/drivers/spi/spidev.c
@@ -669,6 +669,7 @@ static const struct of_device_id spidev_dt_ids[] = {
{ .compatible = "lineartechnology,ltc2488" },
{ .compatible = "ge,achc" },
{ .compatible = "semtech,sx1301" },
+ { .compatible = "rockchip,spi_tinker" },
{},
};
MODULE_DEVICE_TABLE(of, spidev_dt_ids);
--
2.11.0

69
patch/kernel/rockchip-next/2009-Define-VPU-services-in-the-Rockchip-3288-DTS-files.patch
View file

@ -1,69 +0,0 @@
From 59b6f52c5290521ce2bd6209759e0d055c4bdc09 Mon Sep 17 00:00:00 2001
From: Myy <myy@miouyouyou.fr>
Date: Tue, 18 Jul 2017 02:21:44 +0000
Subject: [PATCH] Define VPU services in the Rockchip 3288 DTS files
And use them in the MiQi, Tinkerboard and Firefly board.
These will be used by the external Vcodec driver.
Signed-off-by: Myy <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-firefly.dtsi | 8 +++
arch/arm/boot/dts/rk3288-miqi.dts | 8 +++
arch/arm/boot/dts/rk3288-tinker.dts | 9 ++++
arch/arm/boot/dts/rk3288.dtsi | 97 +++++++++++++++++++++++++++++++++++
4 files changed, 122 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi
index 32dabae..13c8b42 100644
--- a/arch/arm/boot/dts/rk3288-firefly.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly.dtsi
@@ -612,3 +612,11 @@
&wdt {
status = "okay";
};
+
+&hevc_service {
+ status = "okay";
+};
+
+&vpu_service {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index 30e93f6..c165eec 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -462,3 +462,11 @@
&wdt {
status = "okay";
};
+
+&hevc_service {
+ status = "okay";
+};
+
+&vpu_service {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
index f601c78..6bbc8a3 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dts
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
@@ -534,3 +534,12 @@
&wdt {
status = "okay";
};
+
+&hevc_service {
+ status = "okay";
+};
+
+&vpu_service {
+ status = "okay";
+};
+
--
2.10.2

56
patch/kernel/rockchip-next/2010-ARM-DTSI-rk3288-Adding-cells-addresses-and-size.patch Normal file
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@ -0,0 +1,56 @@
From 7af8d2bf732cb3baab7d926ed8a7e061e7a09ad9 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 21:39:00 +0200
Subject: [PATCH 13/28] ARM: DTSI: rk3288.dtsi: Adding cells addresses and
sizes of MMC nodes
Imported from the Rockchip 4.4 patches.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index be985f02..14ef8202 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -236,6 +236,8 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x0 0xff0c0000 0x0 0x4000>;
resets = <&cru SRST_MMC0>;
reset-names = "reset";
@@ -250,6 +252,8 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x0 0xff0d0000 0x0 0x4000>;
resets = <&cru SRST_SDIO0>;
reset-names = "reset";
@@ -264,6 +268,8 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x0 0xff0e0000 0x0 0x4000>;
resets = <&cru SRST_SDIO1>;
reset-names = "reset";
@@ -278,6 +284,8 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x0 0xff0f0000 0x0 0x4000>;
resets = <&cru SRST_EMMC>;
reset-names = "reset";
--
2.11.0

27
patch/kernel/rockchip-next/2011-ARM-DTSI-rk3288-Adding-missing-EDP-power-domain.patch Normal file
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@ -0,0 +1,27 @@
From ac220d592aa38b9b717d36f7bb93f7be5a08f6b3 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 21:43:51 +0200
Subject: [PATCH 14/28] ARM: DTSI: rk3288.dtsi: Adding missing EDP power domain
Imported from Rockchip 4.4 kernel patches.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 14ef8202..10ecebb4 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -1105,6 +1105,7 @@
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
clock-names = "dp", "pclk";
+ power-domains = <&power RK3288_PD_VIO>;
phys = <&edp_phy>;
phy-names = "dp";
resets = <&cru SRST_EDP>;
--
2.11.0

40
patch/kernel/rockchip-next/2012-ARM-DTSI-rk3288-Add-the-RGA-node.patch Normal file
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@ -0,0 +1,40 @@
From 3fe37d29b53e3d06c8f4314cfc113bfa679f67eb Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 21:48:05 +0200
Subject: [PATCH 15/28] ARM: DTSI: rk3288.dtsi: Add the RGA node
Imported from @wzyy2 patches.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 10ecebb4..455446f6 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -1159,6 +1159,20 @@
};
};
+ rga: rga@ff920000 {
+ compatible = "rockchip,rk3288-rga";
+ reg = <0x0 0xff920000 0x0 0x180>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rga";
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
+ clock-names = "aclk", "hclk", "sclk";
+ power-domains = <&power RK3288_PD_VIO>;
+ resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
+
+ reset-names = "core", "axi", "ahb";
+ status = "disabled";
+ };
+
vpu_mmu: iommu@ff9a0800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff9a0800 0x0 0x100>;
--
2.11.0

28
patch/kernel/rockchip-next/2013-ARM-DTSI-rk3288-Adding-missing-VOPB-registers.patch Normal file
View file

@ -0,0 +1,28 @@
From c5af6798c9a411b3f550f463182a4b4904a21ec2 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 21:51:14 +0200
Subject: [PATCH 16/28] ARM: DTSI: rk3288.dtsi: Adding missing VOPB registers
Imported from @wzyy2 patches... I think...
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 455446f6..125f8835 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -987,7 +987,7 @@
vopb: vop@ff930000 {
compatible = "rockchip,rk3288-vop";
- reg = <0x0 0xff930000 0x0 0x19c>;
+ reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
--
2.11.0

31
patch/kernel/rockchip-next/2014-ARM-DTSI-rk3288-Fixed-the-SPDIF-node-address.patch Normal file
View file

@ -0,0 +1,31 @@
From a0602b2724893de7ac9b4190a7a6bb66458da2d5 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 21:54:37 +0200
Subject: [PATCH 17/28] ARM: DTSI: rk3288.dtsi: Fixed the SPDIF node address
Now, the typo is only in the name of the node itself, not in the
actual registers addresses definition.
Still, this ought to be fixed one day !
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 125f8835..e5d3d3c9 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -922,7 +922,7 @@
status = "disabled";
};
- spdif: sound@ff88b0000 {
+ spdif: sound@ff8b0000 {
compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
reg = <0x0 0xff8b0000 0x0 0x10000>;
#sound-dai-cells = <0>;
--
2.11.0

165
patch/kernel/rockchip-next/2015-ARM-DTS-rk3288-tinker-Enabling-SDIO-Wireless-and.patch Normal file
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@ -0,0 +1,165 @@
From 2715f4a9ab5c169c546029a61eebb0bde6619b0e Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 22:12:48 +0200
Subject: [PATCH 18/28] ARM: DTS: rk3288-tinker.dts: Enabling SDIO, Wireless
and Bluetooth
Adding the appropriate nodes in order to exploit the WiFi capabilities
of the board.
Since these capabilities are provided through SDIO, and the SDIO
nodes were not defined, these were added too.
These seems to depend on each other so they are added in one big
patch.
Split if necessary.
Bluetooth and uart0 (AKA Bluetooth UART) definitions were also added
in order to deal with all the wireless techs in one patch.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-tinker.dts | 82 ++++++++++++++++++++++++++++++++++++-
1 file changed, 81 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
index 346b0d8b..c552fd95 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dts
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
@@ -44,6 +44,7 @@
#include "rk3288.dtsi"
#include <dt-bindings/input/input.h>
+#include <dt-bindings/clock/rockchip,rk808.h>
/ {
model = "Rockchip RK3288 Tinker Board";
@@ -114,6 +115,24 @@
};
};
+ /* This is essential to get SDIO devices working.
+ The Wifi depends on SDIO ! */
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 RK808_CLKOUT1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&chip_enable_h>, <&wifi_enable_h>;
+
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>, <&gpio4 RK_PD3 GPIO_ACTIVE_LOW>;
+ };
+
vcc_sys: vsys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
@@ -134,6 +153,28 @@
startup-delay-us = <100000>;
vin-supply = <&vcc_io>;
};
+
+ wireless-wlan {
+ compatible = "wlan-platdata";
+ rockchip,grf = <&grf>;
+ wifi_chip_type = "8723bs";
+ sdio_vref = <1800>;
+ WIFI,host_wake_irq = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ wireless-bluetooth {
+ compatible = "bluetooth-platdata";
+ uart_rts_gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default","rts_gpio";
+ pinctrl-0 = <&uart0_rts>;
+ pinctrl-1 = <&uart0_gpios>;
+ BT,reset_gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+ BT,wake_gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
+ BT,wake_host_irq = <&gpio4 31 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
};
&cpu0 {
@@ -373,10 +414,30 @@
&io_domains {
status = "okay";
-
+ rockchip,grf = <&grf>;
+ wifi-supply = <&vcc_18>;
sdcard-supply = <&vccio_sd>;
};
+&sdio0 {
+ status = "okay";
+ clock-frequency = <50000000>;
+ clock-freq-min-max = <200000 50000000>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ supports-sdio;
+
+};
+
&pinctrl {
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
drive-strength = <8>;
@@ -422,6 +483,16 @@
};
};
+ sdio-pwrseq {
+ wifi_enable_h: wifienable-h {
+ rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ chip_enable_h: chip-enable-h {
+ rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
sdmmc {
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
@@ -453,6 +524,13 @@
rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ wireless-bluetooth {
+ uart0_gpios: uart0-gpios {
+ rockchip,pins = <4 19 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
};
&pwm0 {
@@ -485,6 +563,8 @@
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer>, <&uart0_cts>;
};
&uart1 {
--
2.11.0

29
patch/kernel/rockchip-next/2016-ARM-DTS-rk3288-tinker-Improving-the-CPU-max-volt.patch Normal file
View file

@ -0,0 +1,29 @@
From d4775f623b25009039a8ef3f28332033c7766ecc Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 22:20:33 +0200
Subject: [PATCH 19/28] ARM: DTS: rk3288-tinker.dts: Improving the CPU max
voltage
Taken from the various patches provided by @TonyMac32 .
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-tinker.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
index c552fd95..4ce94698 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dts
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
@@ -243,7 +243,7 @@
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
+ regulator-max-microvolt = <1450000>;
regulator-name = "vdd_arm";
regulator-ramp-delay = <6000>;
regulator-state-mem {
--
2.11.0

40
patch/kernel/rockchip-next/2017-ARM-DTS-rk3288-tinker-Setting-up-the-SD-regulato.patch Normal file
View file

@ -0,0 +1,40 @@
From 39e50ab508d8104a733771a8681908a66a300edd Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 22:25:03 +0200
Subject: [PATCH 20/28] ARM: DTS: rk3288-tinker.dts: Setting up the SD
regulators
Some are needed and some are not. Playing with these parameters is
required to get reboot working on these boards.
I still can't believe that these boards can't soft reset correctly.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-tinker.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
index 4ce94698..90c1a251 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dts
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
@@ -333,6 +333,8 @@
};
vccio_sd: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
@@ -379,7 +381,6 @@
};
vcc33_sd: SWITCH_REG1 {
- regulator-always-on;
regulator-boot-on;
regulator-name = "vcc33_sd";
regulator-state-mem {
--
2.11.0

53
patch/kernel/rockchip-next/2018-ARM-DTS-rk3288-tinker-Defined-the-I2C-interfaces.patch Normal file
View file

@ -0,0 +1,53 @@
From b0a552add28bf4590b979abb3530b14b6811eec1 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 22:33:39 +0200
Subject: [PATCH 21/28] ARM: DTS: rk3288-tinker.dts: Defined the I2C interfaces
And all the hardware behind.
Taken from, and tested by @TonyMac32 .
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-tinker.dts | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
index 90c1a251..67a3ce6f 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dts
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
@@ -400,8 +400,31 @@
};
};
+&i2c1 {
+ status = "okay";
+};
+
&i2c2 {
status = "okay";
+
+ afc0:af-controller@0 {
+ status = "okay";
+ compatible = "silicon touch,vm149C-v4l2-i2c-subdev";
+ reg = <0x0 0x0c>;
+ };
+
+ eeprom:m24c08@50 {
+ compatible = "at,24c08";
+ reg = <0x0 0x50>;
+ };
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
};
&i2c5 {
--
2.11.0

35
patch/kernel/rockchip-next/2019-ARM-DTS-rk3288-tinker-Add-the-MIPI-DSI-node.patch Normal file
View file

@ -0,0 +1,35 @@
From 8ca607f3fe77c80a3367d8363703d5dc1d6781d4 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 22:36:02 +0200
Subject: [PATCH 22/28] ARM: DTS: rk3288-tinker.dts: Add the MIPI DSI node
Taken from, and tested by @TonyMac32 .
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-tinker.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
index 67a3ce6f..6f4c0843 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dts
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
@@ -443,6 +443,15 @@
sdcard-supply = <&vccio_sd>;
};
+&mipi_dsi {
+ status = "okay";
+ mipi_panel: mipi-panel {
+ compatible ="asus,tc358762";
+ reg = <0x0 0>;
+ status = "okay";
+ };
+};
+
&sdio0 {
status = "okay";
clock-frequency = <50000000>;
--
2.11.0

49
patch/kernel/rockchip-next/2020-ARM-DTS-rk3288-tinker-Defining-the-SPI-interface.patch Normal file
View file

@ -0,0 +1,49 @@
From 14f951ca2d354ad8fd068d0f3d8648d5c0d1e60e Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 22:40:26 +0200
Subject: [PATCH 23/28] ARM: DTS: rk3288-tinker.dts: Defining the SPI interface
Taken from, and tested by @TonyMac32 .
Well, the original one was tested by him but I had to adapt the
registers definitions to the new 64-bits LPAE-compliant syntax.
Therefore that *might* break, along with a few other patches.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-tinker.dts | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
index 6f4c0843..f4b4525c 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dts
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
@@ -471,6 +471,24 @@
};
+&spi2 {
+ status = "okay";
+ max-freq = <50000000>;
+ spidev@0 {
+ compatible = "rockchip,spi_tinker";
+ reg = <0x0 0>;
+ spi-max-frequency = <50000000>;
+ spi-cpha = <1>;
+ };
+ spidev@1 {
+ compatible = "rockchip,spi_tinker";
+ reg = <0x0 1>;
+ spi-max-frequency = <50000000>;
+ spi-cpha = <1>;
+ };
+};
+
+
&pinctrl {
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
drive-strength = <8>;
--
2.11.0

33
patch/kernel/rockchip-next/2021-ARM-DTS-rk3288-tinker-Defining-SDMMC-properties.patch Normal file
View file

@ -0,0 +1,33 @@
From 58d72a1cc693c4c08391487476d0cd6d167a57cf Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 22:48:36 +0200
Subject: [PATCH 24/28] ARM: DTS: rk3288-tinker.dts: Defining SDMMC properties
I never knew if these properties were required to fix the dreaded
reboot issue...
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-tinker.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
index f4b4525c..a0663425 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dts
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
@@ -601,7 +601,12 @@
disable-wp; /* wp not hooked up */
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
status = "okay";
+ supports-sd;
vmmc-supply = <&vcc33_sd>;
vqmmc-supply = <&vccio_sd>;
};
--
2.11.0

107
patch/kernel/rockchip-next/2022-ARM-DTSI-rk3288-Define-the-VPU-services.patch Normal file
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@ -0,0 +1,107 @@
From f4480cb8198085607c15e523b49aa21bc38cf62c Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Tue, 21 Nov 2017 21:47:33 +0100
Subject: [PATCH 1/5] ARM: DTSI: rk3288.dtsi: Define the VPU services
Still, you will need appropriate drivers to use them.
Contrary to the previous versions of this patch, these services are :
* NOT enabled by default;
* MUST be activated in each individual DTS;
I currently do not own enough RK3288 boards to ensure that the
VPU and HEVC MMU + services can be activated without issues.
Still this patch does not generate issues like the previous one AND
still enable these services on boot, when activated properly in
individual DTS files.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288.dtsi | 63 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 63 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 30b04257..bc3601ac 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -1182,6 +1182,27 @@
status = "disabled";
};
+ vpu_service: vpu-service@ff9a0000 {
+ compatible = "rockchip,vpu_service";
+ reg = <0x0 0xff9a0000 0x0 0x800>;
+ interrupts =
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_enc", "irq_dec";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ power-domains = <&power RK3288_PD_VIDEO>;
+ rockchip,grf = <&grf>;
+ resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
+ reset-names = "video_a", "video_h";
+ iommus = <&vpu_mmu>;
+ iommu_enabled = <1>;
+ dev_mode = <0>;
+ status = "disabled";
+ /* 0 means ion, 1 means drm */
+ allocator = <1>;
+ };
+
hevc_mmu: iommu@ff9c0440 {
compatible = "rockchip,iommu";
reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
@@ -1191,6 +1212,48 @@
status = "disabled";
};
+ hevc_service: hevc-service@ff9c0000 {
+ compatible = "rockchip,hevc_service";
+ reg = <0x0 0xff9c0000 0x0 0x400>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_dec";
+ clocks =
+ <&cru ACLK_HEVC>,
+ <&cru HCLK_HEVC>,
+ <&cru SCLK_HEVC_CORE>,
+ <&cru SCLK_HEVC_CABAC>;
+ clock-names =
+ "aclk_vcodec",
+ "hclk_vcodec",
+ "clk_core",
+ "clk_cabac";
+ /*
+ * The 4K hevc would also work well with 500/125/300/300,
+ * no more err irq and reset request.
+ */
+ assigned-clocks =
+ <&cru ACLK_HEVC>,
+ <&cru HCLK_HEVC>,
+ <&cru SCLK_HEVC_CORE>,
+ <&cru SCLK_HEVC_CABAC>;
+ assigned-clock-rates =
+ <400000000>,
+ <100000000>,
+ <300000000>,
+ <300000000>;
+
+ resets = <&cru SRST_HEVC>;
+ reset-names = "video";
+ power-domains = <&power RK3288_PD_HEVC>;
+ rockchip,grf = <&grf>;
+ dev_mode = <1>;
+ iommus = <&hevc_mmu>;
+ iommu_enabled = <1>;
+ status = "disabled";
+ /* 0 means ion, 1 means drm */
+ allocator = <1>;
+ };
+
gpu: gpu@ffa30000 {
compatible = "rockchip,rk3288-mali", "arm,mali-t760";
reg = <0x0 0xffa30000 0x0 0x10000>;
--
2.14.1

57
patch/kernel/rockchip-next/2023-ARM-DTS-rk3288-miqi-Enable-the-Video-encoding-MM.patch Normal file
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@ -0,0 +1,57 @@
From 647d6012849191e9909a8acb0fc9ae5df1afc747 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Tue, 21 Nov 2017 21:51:31 +0100
Subject: [PATCH 2/5] ARM: DTS: rk3288-miqi.dts: Enable the Video encoding MMU
and services
Enable the :
* VPU MMU;
* VPU service;
* HEVC MMU;
* HEVC service;
on MiQi devices.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-miqi.dts | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index d7fde483..dd785c70 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -124,7 +124,7 @@
};
- cpu0_opp_table: opp_table0 {
+ cpu0_opp_table: opp_table {
compatible = "operating-points-v2";
opp-shared;
@@ -575,6 +575,22 @@
status = "okay";
};
+&vpu_mmu {
+ status = "okay";
+};
+
+&vpu_service {
+ status = "okay";
+};
+
+&hevc_mmu {
+ status = "okay";
+};
+
+&hevc_service {
+ status = "okay";
+};
+
&wdt {
status = "okay";
};
--
2.14.1

48
patch/kernel/rockchip-next/2024-ARM-DTS-rk3288-tinker-Enable-the-Video-encoding-MMU-.patch Normal file
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@ -0,0 +1,48 @@
From 092c26ead2eb4035a57217f8705c9deed3bfb927 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Tue, 21 Nov 2017 21:54:22 +0100
Subject: [PATCH 3/5] ARM: DTS: rk3288-tinker: Enable the Video encoding MMU
and services
Enable the :
* VPU MMU;
* VPU Service;
* HEVC MMU;
* HEVC Service;
for ASUS Tinkerboard devices.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-tinker.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
index a0663425..07b4af4f 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dts
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
@@ -671,6 +671,22 @@
status = "okay";
};
+&vpu_mmu {
+ status = "okay";
+};
+
+&vpu_service {
+ status = "okay";
+};
+
+&hevc_mmu {
+ status = "okay";
+};
+
+&hevc_service {
+ status = "okay";
+};
+
&wdt {
status = "okay";
};
--
2.14.1

49
patch/kernel/rockchip-next/2025-ARM-DTSI-rk3288-firefly-Enable-the-Video-encoding-MM.patch Normal file
View file

@ -0,0 +1,49 @@
From 2769b0e656d849c5d652c75db71ce0faff1c0551 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Tue, 21 Nov 2017 21:56:45 +0100
Subject: [PATCH 4/5] ARM: DTSI: rk3288-firefly: Enable the Video encoding MMU
and services
Enable the :
* VPU MMU;
* VPU Service;
* HEVC MMU;
* HEVC Service;
for RK3288 Firefly devices.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-firefly.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi
index b9e6f3a9..9961acce 100644
--- a/arch/arm/boot/dts/rk3288-firefly.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly.dtsi
@@ -606,6 +606,23 @@
status = "okay";
};
+&vpu_mmu {
+ status = "okay";
+};
+
+&vpu_service {
+ status = "okay";
+};
+
+&hevc_mmu {
+ status = "okay";
+};
+
+&hevc_service {
+ status = "okay";
+};
+
&wdt {
status = "okay";
};
+
--
2.14.1

48
patch/kernel/rockchip-next/2026-ARM-DTSI-rk3288-veyron-Enable-the-Video-encoding-MMU.patch Normal file
View file

@ -0,0 +1,48 @@
From 4766516bcbf023813ad883c2d61c422316770d12 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Tue, 21 Nov 2017 21:58:22 +0100
Subject: [PATCH 5/5] ARM: DTSI: rk3288-veyron: Enable the Video encoding MMU
and services
Enable the :
* VPU MMU;
* VPU Service;
* HEVC MMU;
* HEVC Service;
for RK3288 Chromebook laptops.
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-veyron.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
index 6e5bd897..517b9242 100644
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
@@ -450,6 +450,22 @@
status = "okay";
};
+&vpu_mmu {
+ status = "okay";
+};
+
+&vpu_service {
+ status = "okay";
+};
+
+&hevc_mmu {
+ status = "okay";
+};
+
+&hevc_service {
+ status = "okay";
+};
+
&wdt {
status = "okay";
};
--
2.14.1

12
patch/kernel/rockchip-next/9000-Add-Tinkerboard-DTS.patch
View file

@ -1,12 +0,0 @@
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0118084..9b79466 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -691,6 +691,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-firefly-beta.dtb \
rk3288-firefly.dtb \
rk3288-firefly-reload.dtb \
+ rk3288-miniarm.dtb \
rk3288-miqi.dtb \
rk3288-popmetal.dtb \
rk3288-r89.dtb \

773
patch/kernel/rockchip-next/9001_miniarm_dts.patch
View file

@ -1,773 +0,0 @@
diff --git a/arch/arm/boot/dts/rk3288-miniarm.dts b/arch/arm/boot/dts/rk3288-miniarm.dts
new file mode 100644
index 0000000..348e9be
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-miniarm.dts
@@ -0,0 +1,673 @@
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk3288.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/clock/rockchip,rk808.h>
+
+/ {
+ model = "Rockchip RK3288 Tinker Board";
+ compatible = "asus,rk3288-tinker", "rockchip,rk3288";
+
+ memory@0 {
+ reg = <0x0 0x80000000>;
+ device_type = "memory";
+ };
+
+ wireless-bluetooth {
+ compatible = "bluetooth-platdata";
+ uart_rts_gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default","rts_gpio";
+ pinctrl-0 = <&uart0_rts>;
+ pinctrl-1 = <&uart0_gpios>;
+ BT,reset_gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+ BT,wake_gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
+ BT,wake_host_irq = <&gpio4 31 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ wireless-wlan {
+ compatible = "wlan-platdata";
+ rockchip,grf = <&grf>;
+ wifi_chip_type = "8723bs";
+ sdio_vref = <1800>;
+ WIFI,host_wake_irq = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ ext_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ clock-output-names = "ext_gmac";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwrbtn>;
+
+ button@0 {
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ label = "GPIO Key Power";
+ linux,input-type = <1>;
+ gpio-key,wakeup = <1>;
+ debounce-interval = <100>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ pwr-led {
+ gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+
+ act-led {
+ gpios=<&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger="mmc0";
+ };
+
+
+ heartbeat-led {
+ gpios=<&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger="heartbeat";
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "rockchip,tinker-codec";
+ simple-audio-card,mclk-fs = <512>;
+ simple-audio-card,cpu {
+ sound-dai = <&i2s>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&hdmi>;
+ };
+ };
+
+ vcc_sys: vsys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_pwr>;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 RK808_CLKOUT1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&chip_enable_h>, <&wifi_enable_h>;
+
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>, <&gpio4 RK_PD3 GPIO_ACTIVE_LOW>;
+ };
+
+};
+
+&cpu0 {
+ cpu0-supply = <&vdd_cpu>;
+};
+
+&gmac {
+ phy-supply = <&vcc33_lan>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = <&gpio4 7 0>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ status = "ok";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c5>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int &global_pwroff &dvs_1 &dvs_2>;
+ dvs-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>,
+ <&gpio0 12 GPIO_ACTIVE_HIGH>;
+
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc_io>;
+ vcc9-supply = <&vcc_io>;
+ vcc10-supply = <&vcc_io>;
+ vcc11-supply = <&vcc_sys>;
+ vcc12-supply = <&vcc_io>;
+ vddio-supply = <&vcc_io>;
+
+ regulators {
+ vdd_cpu: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-name = "vdd_arm";
+ regulator-ramp-delay = <6000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd_gpu";
+ regulator-ramp-delay = <6000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_ddr";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_io";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc18_ldo1: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18_ldo1";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc33_mipi: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc33_mipi";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd_10";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc18_codec: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18_codec";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vdd10_lcd: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd10_lcd";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc_18: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_18";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc18_lcd: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18_lcd";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc33_sd: SWITCH_REG1 {
+ regulator-boot-on;
+ regulator-name = "vcc33_sd";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc33_lan: SWITCH_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc33_lan";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+
+ eeprom:m24c08@50 {
+ compatible = "at,24c08";
+ reg = <0x50>;
+ };
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+ &spi2 {
+ status = "okay";
+ max-freq = <50000000>;
+ spidev@0 {
+ compatible = "rockchip,spi_tinker";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-cpha = <1>;
+ //spi-cpol = <1>;
+ };
+ spidev@1 {
+ compatible = "rockchip,spi_tinker";
+ reg = <1>;
+ spi-max-frequency = <50000000>;
+ spi-cpha = <1>;
+ //spi-cpol = <1>;
+ };
+ };
+
+&i2s {
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
+&sdio0 {
+ status = "okay";
+ clock-frequency = <50000000>;
+ clock-freq-min-max = <200000 50000000>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ supports-sdio;
+
+};
+
+
+&io_domains {
+ status = "okay";
+ rockchip,grf = <&grf>;
+ wifi-supply = <&vcc_18>;
+ sdcard-supply = <&vccio_sd>;
+};
+
+&pinctrl {
+ pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
+ drive-strength = <8>;
+ };
+
+ pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ backlight {
+ bl_en: bl-en {
+ rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ buttons {
+ pwrbtn: pwrbtn {
+ rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ eth_phy {
+ eth_phy_pwr: eth-phy-pwr {
+ rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic-int {
+ rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO \
+ &pcfg_pull_up>;
+ };
+
+ dvs_1: dvs-1 {
+ rockchip,pins = <RK_GPIO0 11 RK_FUNC_GPIO \
+ &pcfg_pull_down>;
+ };
+
+ dvs_2: dvs-2 {
+ rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO \
+ &pcfg_pull_down>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifienable-h {
+ rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ chip_enable_h: chip-enable-h {
+ rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+
+ sdmmc {
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
+ <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
+ <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
+ <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
+ };
+
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins = <6 20 RK_FUNC_1 \
+ &pcfg_pull_none_drv_8ma>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
+ };
+
+ sdmmc_pwr: sdmmc-pwr {
+ rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pwr_3g: pwr-3g {
+ rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wireless-bluetooth {
+ uart0_gpios: uart0-gpios {
+ rockchip,pins = <4 19 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc18_ldo1>;
+ status ="okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ card-detect-delay = <200>;
+ disable-wp; /* wp not hooked up */
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ status = "okay";
+ supports-sd;
+ vmmc-supply = <&vcc33_sd>;
+ vqmmc-supply = <&vccio_sd>;
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer>, <&uart0_cts>;
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host1 {
+ status = "okay";
+};
+
+&usb_otg {
+ status= "okay";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
+
+/* Support for Mali and Video codecs services */
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hevc_service {
+ status = "okay";
+};
+
+&vpu_service {
+ status = "okay";
+};
+
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 5d63ee0..458d545 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -43,7 +43,6 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3288-cru.h>
-#include <dt-bindings/power/rk3288-power.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/power/rk3288-power.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
@@ -100,6 +99,8 @@
resets = <&cru SRST_CORE0>;
operating-points = <
/* KHz uV */
+ 1800000 1350000
+ 1704000 1350000
1608000 1350000
1512000 1300000
1416000 1200000
@@ -334,9 +466,9 @@
dma-names = "tx", "rx";
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
+ pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0 &spi2_cs1>;
reg = <0xff130000 0x1000>;
- #address-cells = <1>;
+ #address-cells = <2>;
#size-cells = <0>;
status = "disabled";
};
@@ -527,7 +659,7 @@
map0 {
trip = <&gpu_alert0>;
cooling-device =
- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -914,7 +1046,7 @@
status = "disabled";
};
- spdif: sound@ff88b0000 {
+ spdif: sound@ff8b0000 {
compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
reg = <0xff8b0000 0x10000>;
#sound-dai-cells = <0>;
@@ -958,9 +1090,24 @@
status = "okay";
};
+ rga: rga@ff920000 {
+ compatible = "rockchip,rk3288-rga";
+ reg = <0xff920000 0x180>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rga";
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
+ clock-names = "aclk", "hclk", "sclk";
+ power-domains = <&power RK3288_PD_VIO>;
+ resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
+
+ reset-names = "core", "axi", "ahb";
+ status = "disabled";
+ };
+
+
vopb: vop@ff930000 {
compatible = "rockchip,rk3288-vop";
- reg = <0xff930000 0x19c>;
+ reg = <0xff930000 0x19c>, <0xff931000 0x1000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@@ -1003,7 +1150,7 @@
vopl: vop@ff940000 {
compatible = "rockchip,rk3288-vop";
- reg = <0xff940000 0x19c>;
+ reg = <0xff940000 0x19c>, <0xff941000 0x1000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@@ -1078,6 +1225,7 @@
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
clock-names = "dp", "pclk";
+ power-domains = <&power RK3288_PD_VIO>;
phys = <&edp_phy>;
phy-names = "dp";
resets = <&cru SRST_EDP>;

13
patch/kernel/rockchip-next/9002_tinker_spidev.patch
View file

@ -1,13 +0,0 @@
diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
index 9e2e099..3a0f0a7 100644
--- a/drivers/spi/spidev.c
+++ b/drivers/spi/spidev.c
@@ -697,7 +697,8 @@ static const struct of_device_id spidev_dt_ids[] = {
{ .compatible = "rohm,dh2228fv" },
{ .compatible = "lineartechnology,ltc2488" },
{ .compatible = "ge,achc" },
{ .compatible = "semtech,sx1301" },
+ { .compatible = "rockchip,spi_tinker" },
{},
};
MODULE_DEVICE_TABLE(of, spidev_dt_ids);

46
patch/kernel/rockchip-next/9003_Tinker_DTS_DSI.patch
View file

@ -1,46 +0,0 @@
diff --git a/arch/arm/boot/dts/rk3288-miniarm.dts b/arch/arm/boot/dts/rk3288-miniarm.dts
index 348e9be..3896506 100644
--- a/arch/arm/boot/dts/rk3288-miniarm.dts
+++ b/arch/arm/boot/dts/rk3288-miniarm.dts
@@ -194,6 +194,16 @@
status = "ok";
};
+&mipi_dsi {
+ status = "okay";
+ mipi_panel: mipi-panel {
+ compatible ="asus,tc358762";
+ reg = <0>;
+ status = "okay";
+ };
+};
+
+
&hdmi {
ddc-i2c-bus = <&i2c5>;
status = "okay";
@@ -400,9 +410,15 @@
&i2c2 {
status = "okay";
+ afc0:af-controller@0 {
+ status = "okay";
+ compatible = "silicon touch,vm149C-v4l2-i2c-subdev";
+ reg = < 0x0c >;
+ };
+
eeprom:m24c08@50 {
- compatible = "at,24c08";
- reg = <0x50>;
+ compatible = "at,24c08";
+ reg = <0x50>;
};
};
@@ -626,6 +642,7 @@
};
&usb_host0_ehci {
+ no-relinquish-port;
status = "okay";
};

97
patch/kernel/rockchip-next/9004_dtsi_VPU_HEVC.patch
View file

@ -1,97 +0,0 @@
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index fc2d6be..624416f 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -1143,6 +1143,92 @@
};
};
+ vpu: video-codec@ff9a0000 {
+ compatible = "rockchip,rk3288-vpu";
+ reg = <0xff9a0000 0x800>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu", "vdpu";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3288_PD_VIDEO>;
+ iommus = <&vpu_mmu>;
+ assigned-clocks = <&cru ACLK_VCODEC>;
+ assigned-clock-rates = <400000000>;
+ status = "disabled";
+ };
+
+ vpu_service: vpu-service@ff9a0000 {
+ compatible = "rockchip,vpu_service";
+ reg = <0xff9a0000 0x800>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_enc", "irq_dec";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ power-domains = <&power RK3288_PD_VIDEO>;
+ rockchip,grf = <&grf>;
+ resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
+ reset-names = "video_a", "video_h";
+ iommus = <&vpu_mmu>;
+ iommu_enabled = <1>;
+ dev_mode = <0>;
+ status = "disabled";
+ /* 0 means ion, 1 means drm */
+ allocator = <1>;
+ };
+
+ vpu_mmu: iommu@ff9a0800 {
+ compatible = "rockchip,iommu";
+ reg = <0xff9a0800 0x100>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vpu_mmu";
+ power-domains = <&power RK3288_PD_VIDEO>;
+ #iommu-cells = <0>;
+ };
+
+ hevc_service: hevc-service@ff9c0000 {
+ compatible = "rockchip,hevc_service";
+ reg = <0xff9c0000 0x400>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_dec";
+ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
+ <&cru SCLK_HEVC_CORE>,
+ <&cru SCLK_HEVC_CABAC>;
+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
+ "clk_cabac";
+ /*
+ * The 4K hevc would also work well with 500/125/300/300,
+ * no more err irq and reset request.
+ */
+ assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
+ <&cru SCLK_HEVC_CORE>,
+ <&cru SCLK_HEVC_CABAC>;
+ assigned-clock-rates = <400000000>, <100000000>,
+ <300000000>, <300000000>;
+
+ resets = <&cru SRST_HEVC>;
+ reset-names = "video";
+ power-domains = <&power RK3288_PD_HEVC>;
+ rockchip,grf = <&grf>;
+ dev_mode = <1>;
+ iommus = <&hevc_mmu>;
+ iommu_enabled = <1>;
+ status = "disabled";
+ /* 0 means ion, 1 means drm */
+ allocator = <1>;
+ };
+
+ hevc_mmu: iommu@ff9c0440 {
+ compatible = "rockchip,iommu";
+ reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hevc_mmu";
+ power-domains = <&power RK3288_PD_HEVC>;
+ #iommu-cells = <0>;
+ };
+
+
gpu: gpu@ffa30000 {
compatible = "rockchip,rk3288-mali", "arm,mali-t760";
reg = <0xffa30000 0x10000>;

199
patch/kernel/rockchip-next/9005_DTS_IOMMU_IEP_ISP.patch
View file

@ -1,199 +0,0 @@
diff --git a/arch/arm/boot/dts/rk3288-miniarm.dts b/arch/arm/boot/dts/rk3288-miniarm.dts
index 3896506..a6c0ec1 100644
--- a/arch/arm/boot/dts/rk3288-miniarm.dts
+++ b/arch/arm/boot/dts/rk3288-miniarm.dts
@@ -642,7 +642,6 @@
};
&usb_host0_ehci {
- no-relinquish-port;
status = "okay";
};
@@ -684,7 +683,22 @@
status = "okay";
};
+&hevc_mmu {
+ status = "okay";
+};
+
&vpu_service {
status = "okay";
};
+&vpu_mmu {
+ status = "okay";
+};
+
+&iep_mmu {
+ status = "okay";
+};
+
+&isp_mmu {
+ status = "okay";
+};
\ No newline at end of file
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index 83bb2a2..52ec00c 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -588,3 +588,20 @@
&vpu_service {
status = "okay";
};
+
+&hevc_mmu {
+ status = "okay";
+};
+
+&vpu_mmu {
+ status = "okay";
+};
+
+&iep_mmu {
+ status = "okay";
+};
+
+&isp_mmu {
+ status = "okay";
+};
+
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 624416f..cfa5178 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -958,16 +958,31 @@
compatible = "rockchip,rk3288-rga";
reg = <0xff920000 0x180>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "rga";
clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
clock-names = "aclk", "hclk", "sclk";
power-domains = <&power RK3288_PD_VIO>;
resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
-
reset-names = "core", "axi", "ahb";
+ };
+
+ iep_mmu: iommu@ff900800 {
+ compatible = "rockchip,iommu";
+ reg = <0xff900800 0x40>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "iep_mmu";
+ #iommu-cells = <0>;
status = "disabled";
};
+ isp_mmu: iommu@ff914000 {
+ compatible = "rockchip,iommu";
+ reg = <0xff914000 0x100>, <0xff915000 0x100>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "isp_mmu";
+ #iommu-cells = <0>;
+ rockchip,disable-mmu-reset;
+ status = "disabled";
+ };
vopb: vop@ff930000 {
compatible = "rockchip,rk3288-vop";
@@ -999,6 +1014,11 @@
reg = <2>;
remote-endpoint = <&mipi_in_vopb>;
};
+
+ vopb_out_lvds: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&lvds_in_vopb>;
+ };
};
};
@@ -1042,6 +1062,11 @@
reg = <2>;
remote-endpoint = <&mipi_in_vopl>;
};
+
+ vopl_out_lvds: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&lvds_in_vopl>;
+ };
};
};
@@ -1083,6 +1108,39 @@
};
};
+ lvds: lvds@ff96c000 {
+ compatible = "rockchip,rk3288-lvds";
+ reg = <0xff96c000 0x4000>;
+ clocks = <&cru PCLK_LVDS_PHY>;
+ clock-names = "pclk_lvds";
+ pinctrl-names = "lcdc";
+ pinctrl-0 = <&lcdc_ctl>;
+ power-domains = <&power RK3288_PD_VIO>;
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lvds_in: port@0 {
+ reg = <0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lvds_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_lvds>;
+ };
+ lvds_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_lvds>;
+ };
+ };
+ };
+ };
+
edp: dp@ff970000 {
compatible = "rockchip,rk3288-dp";
reg = <0xff970000 0x4000>;
@@ -1183,8 +1241,8 @@
reg = <0xff9a0800 0x100>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_mmu";
- power-domains = <&power RK3288_PD_VIDEO>;
#iommu-cells = <0>;
+ status = "disabled";
};
hevc_service: hevc-service@ff9c0000 {
@@ -1224,8 +1282,8 @@
reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hevc_mmu";
- power-domains = <&power RK3288_PD_HEVC>;
#iommu-cells = <0>;
+ status = "disabled";
};
@@ -1926,5 +1984,15 @@
rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
};
};
+
+ lcdc {
+ lcdc_ctl: lcdc-ctl {
+ rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
+ <1 25 RK_FUNC_1 &pcfg_pull_none>,
+ <1 26 RK_FUNC_1 &pcfg_pull_none>,
+ <1 27 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
};
};

31
patch/kernel/rockchip-next/9006_thermal_zone_fix.patch
View file

@ -1,31 +0,0 @@
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index cfa5178..08c96e7 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -546,6 +546,7 @@
pinctrl-0 = <&otp_gpio>;
pinctrl-1 = <&otp_out>;
pinctrl-2 = <&otp_gpio>;
+ rockchip,grf = <&grf>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
status = "disabled";
@@ -1297,7 +1298,18 @@
clocks = <&cru ACLK_GPU>;
operating-points-v2 = <&gpu_opp_table>;
power-domains = <&power RK3288_PD_GPU>;
+ #cooling-cells = <2>; /* min followed by max */
status = "disabled";
+
+ gpu_power_model: power_model {
+ compatible = "arm,mali-simple-power-model";
+ voltage = <950>;
+ frequency = <500>;
+ static-power = <300>;
+ dynamic-power = <396>;
+ ts = <32000 4700 (-80) 2>;
+ thermal-zone = "gpu_thermal";
+ };
};
gpu_opp_table: gpu-opp-table {

31
patch/kernel/rockchip-next/9007_rk3288_dtsi_arrange_thermal_zones.patch
View file

@ -1,31 +0,0 @@
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 08c96e7..bfd41a3 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -460,12 +460,6 @@
};
thermal-zones {
- reserve_thermal: reserve_thermal {
- polling-delay-passive = <1000>; /* milliseconds */
- polling-delay = <5000>; /* milliseconds */
-
- thermal-sensors = <&tsadc 0>;
- };
cpu_thermal: cpu_thermal {
polling-delay-passive = <100>; /* milliseconds */
@@ -532,6 +526,13 @@
};
};
};
+
+ reserve_thermal: reserve_thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&tsadc 0>;
+ };
};
tsadc: tsadc@ff280000 {

342
patch/kernel/rockchip-dev/9001_miniarm_dts.patch → patch/kernel/rockchip-next/9999_tinker_miniarm_dts.patch
View file

@ -1,9 +1,21 @@
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index eff87a3..1661eda 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -756,6 +756,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-firefly-beta.dtb \
rk3288-firefly.dtb \
rk3288-firefly-reload.dtb \
+ rk3288-miniarm.dtb\
rk3288-miqi.dtb \
rk3288-phycore-rdk.dtb \
rk3288-popmetal.dtb \
diff --git a/arch/arm/boot/dts/rk3288-miniarm.dts b/arch/arm/boot/dts/rk3288-miniarm.dts
new file mode 100644
index 0000000..348e9be
index 0000000..07b4af4
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-miniarm.dts
@@ -0,0 +1,673 @@
@@ -0,0 +1,692 @@
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ *
@ -56,32 +68,11 @@ index 0000000..348e9be
+ model = "Rockchip RK3288 Tinker Board";
+ compatible = "asus,rk3288-tinker", "rockchip,rk3288";
+
+ memory@0 {
+ reg = <0x0 0x80000000>;
+ memory {
+ reg = <0x0 0x0 0x0 0x80000000>;
+ device_type = "memory";
+ };
+
+ wireless-bluetooth {
+ compatible = "bluetooth-platdata";
+ uart_rts_gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default","rts_gpio";
+ pinctrl-0 = <&uart0_rts>;
+ pinctrl-1 = <&uart0_gpios>;
+ BT,reset_gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+ BT,wake_gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
+ BT,wake_host_irq = <&gpio4 31 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ wireless-wlan {
+ compatible = "wlan-platdata";
+ rockchip,grf = <&grf>;
+ wifi_chip_type = "8723bs";
+ sdio_vref = <1800>;
+ WIFI,host_wake_irq = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ ext_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
@ -103,7 +94,7 @@ index 0000000..348e9be
+ linux,code = <KEY_POWER>;
+ label = "GPIO Key Power";
+ linux,input-type = <1>;
+ gpio-key,wakeup = <1>;
+ wakeup-source;
+ debounce-interval = <100>;
+ };
+ };
@ -111,21 +102,20 @@ index 0000000..348e9be
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ pwr-led {
+ gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+
+ act-led {
+ gpios=<&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger="mmc0";
+ };
+
+
+ heartbeat-led {
+ gpios=<&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger="heartbeat";
+ };
+
+ pwr-led {
+ gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+ };
+
+ sound {
@ -133,12 +123,32 @@ index 0000000..348e9be
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "rockchip,tinker-codec";
+ simple-audio-card,mclk-fs = <512>;
+ simple-audio-card,cpu {
+ sound-dai = <&i2s>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&hdmi>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s>;
+ };
+ };
+
+ /* This is essential to get SDIO devices working.
+ The Wifi depends on SDIO ! */
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 RK808_CLKOUT1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&chip_enable_h>, <&wifi_enable_h>;
+
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>, <&gpio4 RK_PD3 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc_sys: vsys-regulator {
@ -162,20 +172,25 @@ index 0000000..348e9be
+ vin-supply = <&vcc_io>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 RK808_CLKOUT1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&chip_enable_h>, <&wifi_enable_h>;
+ wireless-wlan {
+ compatible = "wlan-platdata";
+ rockchip,grf = <&grf>;
+ wifi_chip_type = "8723bs";
+ sdio_vref = <1800>;
+ WIFI,host_wake_irq = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>, <&gpio4 RK_PD3 GPIO_ACTIVE_LOW>;
+ wireless-bluetooth {
+ compatible = "bluetooth-platdata";
+ uart_rts_gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default","rts_gpio";
+ pinctrl-0 = <&uart0_rts>;
+ pinctrl-1 = <&uart0_gpios>;
+ BT,reset_gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+ BT,wake_gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
+ BT,wake_host_irq = <&gpio4 31 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+};
@ -185,44 +200,48 @@ index 0000000..348e9be
+};
+
+&gmac {
+ phy-supply = <&vcc33_lan>;
+ phy-mode = "rgmii";
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>;
+ clock_in_out = "input";
+ phy-mode = "rgmii";
+ phy-supply = <&vcc33_lan>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ snps,reset-gpio = <&gpio4 7 0>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ status = "ok";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c5>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+ status = "okay";
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int &global_pwroff &dvs_1 &dvs_2>;
+ dvs-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>,
+ <&gpio0 12 GPIO_ACTIVE_HIGH>;
+
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+ dvs-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>,
+ <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int &global_pwroff &dvs_1 &dvs_2>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
@ -400,54 +419,57 @@ index 0000000..348e9be
+};
+
+&i2c1 {
+ status = "okay";
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+
+ afc0:af-controller@0 {
+ status = "okay";
+ compatible = "silicon touch,vm149C-v4l2-i2c-subdev";
+ reg = <0x0 0x0c>;
+ };
+
+ eeprom:m24c08@50 {
+ compatible = "at,24c08";
+ reg = <0x50>;
+ };
+ compatible = "at,24c08";
+ reg = <0x0 0x50>;
+ };
+};
+
+&i2c3 {
+ status = "okay";
+ status = "okay";
+};
+
+
+&i2c4 {
+ status = "okay";
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+ &spi2 {
+ status = "okay";
+ max-freq = <50000000>;
+ spidev@0 {
+ compatible = "rockchip,spi_tinker";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-cpha = <1>;
+ //spi-cpol = <1>;
+ };
+ spidev@1 {
+ compatible = "rockchip,spi_tinker";
+ reg = <1>;
+ spi-max-frequency = <50000000>;
+ spi-cpha = <1>;
+ //spi-cpol = <1>;
+ };
+ };
+
+&i2s {
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
+&io_domains {
+ status = "okay";
+ rockchip,grf = <&grf>;
+ wifi-supply = <&vcc_18>;
+ sdcard-supply = <&vccio_sd>;
+};
+
+&mipi_dsi {
+ status = "okay";
+ mipi_panel: mipi-panel {
+ compatible ="asus,tc358762";
+ reg = <0x0 0>;
+ status = "okay";
+ };
+};
+
+&sdio0 {
+ status = "okay";
+ clock-frequency = <50000000>;
@ -467,14 +489,24 @@ index 0000000..348e9be
+
+};
+
+
+&io_domains {
+&spi2 {
+ status = "okay";
+ rockchip,grf = <&grf>;
+ wifi-supply = <&vcc_18>;
+ sdcard-supply = <&vccio_sd>;
+ max-freq = <50000000>;
+ spidev@0 {
+ compatible = "rockchip,spi_tinker";
+ reg = <0x0 0>;
+ spi-max-frequency = <50000000>;
+ spi-cpha = <1>;
+ };
+ spidev@1 {
+ compatible = "rockchip,spi_tinker";
+ reg = <0x0 1>;
+ spi-max-frequency = <50000000>;
+ spi-cpha = <1>;
+ };
+};
+
+
+&pinctrl {
+ pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
+ drive-strength = <8>;
@ -529,7 +561,6 @@ index 0000000..348e9be
+ rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+
+ sdmmc {
+ sdmmc_bus4: sdmmc-bus4 {
@ -584,15 +615,14 @@ index 0000000..348e9be
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ disable-wp; /* wp not hooked up */
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ card-detect-delay = <200>;
+ disable-wp; /* wp not hooked up */
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ status = "okay";
+ supports-sd;
+ vmmc-supply = <&vcc33_sd>;
@ -606,9 +636,9 @@ index 0000000..348e9be
+};
+
+&uart0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer>, <&uart0_cts>;
+ status = "okay";
+};
+
+&uart1 {
@ -659,17 +689,7 @@ index 0000000..348e9be
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
+
+/* Support for Mali and Video codecs services */
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hevc_service {
+&vpu_mmu {
+ status = "okay";
+};
+
@ -677,96 +697,14 @@ index 0000000..348e9be
+ status = "okay";
+};
+
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 5d63ee0..458d545 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -43,7 +43,6 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3288-cru.h>
-#include <dt-bindings/power/rk3288-power.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/power/rk3288-power.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
@@ -100,6 +99,8 @@
resets = <&cru SRST_CORE0>;
operating-points = <
/* KHz uV */
+ 1800000 1350000
+ 1704000 1350000
1608000 1350000
1512000 1300000
1416000 1200000
@@ -335,9 +335,9 @@
dma-names = "tx", "rx";
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
+ pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0 &spi2_cs1>;
reg = <0x0 0xff130000 0x0 0x1000>;
- #address-cells = <1>;
+ #address-cells = <2>;
#size-cells = <0>;
status = "disabled";
};
@@ -527,7 +659,7 @@
map0 {
trip = <&gpu_alert0>;
cooling-device =
- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -914,7 +1046,7 @@
status = "disabled";
};
- spdif: sound@ff88b0000 {
+ spdif: sound@ff8b0000 {
compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
reg = <0xff8b0000 0x10000>;
#sound-dai-cells = <0>;
@@ -975,9 +975,22 @@
status = "disabled";
};
+ rga: rga@ff920000 {
+ compatible = "rockchip,rk3288-rga";
+ reg = <0xff920000 0x180>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
+ clock-names = "aclk", "hclk", "sclk";
+ power-domains = <&power RK3288_PD_VIO>;
+ resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
+&hevc_mmu {
+ status = "okay";
+};
+
+ reset-names = "core", "axi", "ahb";
+ status = "disabled";
+ };
+&hevc_service {
+ status = "okay";
+};
+
vopb: vop@ff930000 {
compatible = "rockchip,rk3288-vop";
- reg = <0x0 0xff930000 0x0 0x19c>;
+ reg = <0xff930000 0x19c>, <0xff931000 0x1000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@@ -1020,7 +1034,7 @@
vopl: vop@ff940000 {
compatible = "rockchip,rk3288-vop";
- reg = <0x0 0xff940000 0x0 0x19c>;
+ reg = <0xff940000 0x19c>, <0xff941000 0x1000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@@ -1078,6 +1225,7 @@
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
clock-names = "dp", "pclk";
+ power-domains = <&power RK3288_PD_VIO>;
phys = <&edp_phy>;
phy-names = "dp";
resets = <&cru SRST_EDP>;
+&wdt {
+ status = "okay";
+};

497539
patch/kernel/rockchip-next/add_8812au_8821au_with_monitor_mode_and_frame_injection.patch
View file

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