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Add MVEBU64 NEXT target, mainline + patches for Espressobin

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This commit is contained in:
Igor Pecovnik 2017-08-20 17:30:21 +02:00
parent dc9b761ae7
commit b4e3760b69
17 changed files with 5787 additions and 62 deletions
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2
config/boards/espressobin.wip
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@ -6,7 +6,7 @@ MODULES=""
MODULES_NEXT=""
BUILD_DESKTOP="no"
#
KERNEL_TARGET="default,dev"
KERNEL_TARGET="default,next,dev"
CLI_TARGET="jessie,xenial:default,dev"
#
RECOMMENDED="Ubuntu_xenial_default_nightly:60"

5077
config/kernel/linux-mvebu64-next.config Normal file
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File diff suppressed because it is too large Load diff

8
config/sources/mvebu64.conf
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@ -18,7 +18,13 @@ case $BRANCH in
KERNELSOURCE='https://github.com/MarvellEmbeddedProcessors/linux-marvell.git'
KERNELBRANCH='branch:linux-4.4.52-armada-17.08'
KERNELDIR='linux-marvell'
KERNEL_IMAGE_TYPE='Image'
KERNEL_IMAGE_TYPE='Image'
;;
next)
KERNELSOURCE=$MAINLINE_KERNEL_SOURCE
KERNELBRANCH=$MAINLINE_KERNEL_BRANCH
KERNELDIR=$MAINLINE_KERNEL_DIR
;;
dev)

33
patch/kernel/mvebu64-next/0001-ARM64-dts-marvell-armada37xx-Fix-GIC-maintenance-int.patch Normal file
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@ -0,0 +1,33 @@
From b5470764c194b8930cf0fb65f48e2f2cea6246c5 Mon Sep 17 00:00:00 2001
From: Marc Zyngier <Marc.Zyngier@arm.com>
Date: Sat, 1 Jul 2017 15:16:34 +0100
Subject: [PATCH 01/11] ARM64: dts: marvell: armada37xx: Fix GIC maintenance
interrupt
The GIC-500 integrated in the Armada-37xx SoCs is compliant with
the GICv3 architecture, and thus provides a maintenance interrupt
that is required for hypervisors to function correctly.
With the interrupt provided in the DT, KVM now works as it should.
Tested on an Espressobin system.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index bc179efb10ef..592e95e5f633 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -312,6 +312,7 @@
interrupt-controller;
reg = <0x1d00000 0x10000>, /* GICD */
<0x1d40000 0x40000>; /* GICR */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
};
--
2.13.3

38
patch/kernel/mvebu64-next/0002-ARM64-dts-marvell-armada37xx-Enable-memory-mapped-GI.patch Normal file
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@ -0,0 +1,38 @@
From a6e0e494f7213d914963b2aea8e3ff0e9a0e978a Mon Sep 17 00:00:00 2001
From: Marc Zyngier <Marc.Zyngier@arm.com>
Date: Sat, 1 Jul 2017 15:16:35 +0100
Subject: [PATCH 02/11] ARM64: dts: marvell: armada37xx: Enable memory-mapped
GIC CPU interface
The Cortex-A53s that power the Armada-37xx SoCs are equipped with
a GIC CPU interface that gets enabled when coupled with a GICv3
interrupt controller, such as the GIC-500 on the this SoC.
Advertise the MMIO ranges provided by the CPUs, which enables
(among other things) GICv2 guests to run under a hypervisor such
as KVM.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index 592e95e5f633..fd26d31d2846 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -311,7 +311,10 @@
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x1d00000 0x10000>, /* GICD */
- <0x1d40000 0x40000>; /* GICR */
+ <0x1d40000 0x40000>, /* GICR */
+ <0x1d80000 0x2000>, /* GICC */
+ <0x1d90000 0x2000>, /* GICH */
+ <0x1da0000 0x20000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
};
--
2.13.3

35
patch/kernel/mvebu64-next/0003-ARM64-dts-marvell-armada37xx-Wire-PMUv3.patch Normal file
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@ -0,0 +1,35 @@
From b61fe18e003c4a37b91092cf4abaee9592bb5a87 Mon Sep 17 00:00:00 2001
From: Marc Zyngier <Marc.Zyngier@arm.com>
Date: Sat, 1 Jul 2017 15:16:36 +0100
Subject: [PATCH 03/11] ARM64: dts: marvell: armada37xx: Wire PMUv3
The Cortex-A53s that power the Armada-37xx SoCs are equipped with
a PMUv3, just like most ARMv8 cores.
Advertise the PMUv3 presence in the device tree, and wire its
interrupt. This allows the perf subsystem to work correctly.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index fd26d31d2846..f4deb8cd11c6 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -81,6 +81,11 @@
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
};
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
--
2.13.3

33
patch/kernel/mvebu64-next/0004-ARM64-dts-marvell-armada37xx-Enable-USB2-on-espresso.patch Normal file
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@ -0,0 +1,33 @@
From d71549275ca1e2bee8e7914501526b625e9f8a53 Mon Sep 17 00:00:00 2001
From: Marc Zyngier <Marc.Zyngier@arm.com>
Date: Sat, 1 Jul 2017 15:16:37 +0100
Subject: [PATCH 04/11] ARM64: dts: marvell: armada37xx: Enable USB2 on
espressobin
The Espressobin SBC has a USB2 interface available on J8. Let's
enable it.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
index e3a136ed77b0..b1af3f988b29 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
@@ -81,6 +81,11 @@
status = "okay";
};
+/* J8 */
+&usb2 {
+ status = "okay";
+};
+
&mdio {
switch0: switch0@1 {
compatible = "marvell,mv88e6085";
--
2.13.3

72
patch/kernel/mvebu64-next/0005-arm64-dts-marvell-Enable-second-SDHCI-controller-in-.patch Normal file
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@ -0,0 +1,72 @@
From aff7d41d285c04f5990247660c860e30029f72b2 Mon Sep 17 00:00:00 2001
From: Konstantin Porotchkin <kostap@marvell.com>
Date: Tue, 23 May 2017 16:11:40 +0300
Subject: [PATCH 05/11] arm64: dts: marvell: Enable second SDHCI controller in
Armada 37xx
The Armada 37xx SoCs has 2 SDHCI interfaces. This patch adds the second
one.
Moreover, the Armada 37xx DB v2 board populates the 2 SDHCI interfaces.
The second interface is using pluggable module that can either
have an SD connector or eMMC on it.
This patch adds support for SD module in the device DT.
[ gregory.clement@free-electrons.com:
- Add more detail in commit log
- Sort the dt node in address order
- Document the SD slot in the dts ]
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 9 +++++++++
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 11 +++++++++++
2 files changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index a89855f57091..6a0abd7a5349 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -113,6 +113,15 @@
status = "okay";
};
+/* SD slot module on CON14(V2.0)/CON15(V1.4) */
+&sdhci1 {
+ wp-inverted;
+ cd-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ marvell,pad-type = "sd";
+ status = "okay";
+};
+
&spi0 {
status = "okay";
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index f4deb8cd11c6..a78195b4ef7a 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -293,6 +293,17 @@
};
};
+ sdhci1: sdhci@d0000 {
+ compatible = "marvell,armada-3700-sdhci",
+ "marvell,sdhci-xenon";
+ reg = <0xd0000 0x300>,
+ <0x1e808 0x4>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&nb_periph_clk 0>;
+ clock-names = "core";
+ status = "disabled";
+ };
+
sdhci0: sdhci@d8000 {
compatible = "marvell,armada-3700-sdhci",
"marvell,sdhci-xenon";
--
2.13.3

71
patch/kernel/mvebu64-next/0006-ARM64-dts-marvell-armada-37xx-Enable-uSD-on-ESPRESSO.patch Normal file
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@ -0,0 +1,71 @@
From 1d0dd1ab378af298bf4040edb8ee58d340f48518 Mon Sep 17 00:00:00 2001
From: Marcin Wojtas <mw@semihalf.com>
Date: Fri, 21 Jul 2017 01:50:36 +0200
Subject: [PATCH 06/11] ARM64: dts: marvell: armada-37xx: Enable uSD on
ESPRESSObin
The ESPRESSObin board exposes one of the SDHCI interfaces
via J1 uSD slot. This patch enables it.
Tested-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Zbigniew Bodek <zbodek@gmail.com>
[gregory.clement@free-electrons.com: removed "no-1-8-v"]
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
.../boot/dts/marvell/armada-3720-espressobin.dts | 25 ++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
index b1af3f988b29..2ce52ba74f73 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
@@ -45,6 +45,7 @@
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
#include "armada-372x.dtsi"
/ {
@@ -59,6 +60,20 @@
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
+
+ vcc_sd_reg1: regulator {
+ compatible = "regulator-gpio";
+ regulator-name = "vcc_sd1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+
+ gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ enable-active-high;
+ };
};
/* J9 */
@@ -71,6 +86,16 @@
status = "okay";
};
+/* J1 */
+&sdhci1 {
+ wp-inverted;
+ bus-width = <4>;
+ cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
+ marvell,pad-type = "sd";
+ vqmmc-supply = <&vcc_sd_reg1>;
+ status = "okay";
+};
+
/* Exported on the micro USB connector J5 through an FTDI */
&uart0 {
status = "okay";
--
2.13.3

25
patch/kernel/mvebu64-next/0007-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch Normal file
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@ -0,0 +1,25 @@
From 8440f9edeb29c10cc0ec29c55c07d4e5e5b67c5b Mon Sep 17 00:00:00 2001
From: Kevin Mihelich <kevin@archlinuxarm.org>
Date: Tue, 4 Jul 2017 19:25:28 -0600
Subject: [PATCH 07/11] arm64: dts: marvell: armada37xx: Add eth0 alias
Signed-off-by: Kevin Mihelich <kevin@archlinuxarm.org>
---
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index a78195b4ef7a..14248957b2dd 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -54,6 +54,7 @@
#size-cells = <2>;
aliases {
+ ethernet0 = &eth0;
serial0 = &uart0;
};
--
2.13.3

35
patch/kernel/mvebu64-next/0008-fix-pci-aardvark-disable-LOS-state-by-default.patch Normal file
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@ -0,0 +1,35 @@
From c1d0aadc4440c07d2e940c83c1b6e5d9d694a3a5 Mon Sep 17 00:00:00 2001
From: Victor Gu <xigu@marvell.com>
Date: Wed, 29 Mar 2017 15:17:03 +0800
Subject: [PATCH 08/11] fix: pci: aardvark: disable LOS state by default
Some PCIe devices do not support LOS, there will be time out issue
if the RC forces the LOS state.
This patch disables the LOS state by default.
Change-Id: I88a6a5cf58ea5f2df234c99050ce041987cdabc6
Signed-off-by: Victor Gu <xigu@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38119
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Evan Wang <xswang@marvell.com>
---
drivers/pci/host/pci-aardvark.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 37d0bcd31f8a..072bc70e900c 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -365,8 +365,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
advk_pcie_wait_for_link(pcie);
- reg = PCIE_CORE_LINK_L0S_ENTRY |
- (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
+ reg = (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
--
2.13.3

104
patch/kernel/mvebu64-next/0009-fix-pci-aardvark-use-isr1-interrupt-in-legacy-irq-mo.patch Normal file
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@ -0,0 +1,104 @@
From 364d845b2fd8c083f32a95377f5b3cd3f0cf2323 Mon Sep 17 00:00:00 2001
From: Victor Gu <xigu@marvell.com>
Date: Mon, 27 Mar 2017 18:28:25 +0800
Subject: [PATCH 09/11] fix: pci: aardvark: use isr1 interrupt in legacy irq
mode
The Aardvark has two interrupts sets, first set is bit[23:16] of
PCIe ISR 0 register(RD0074840h), second set is bit[11:8] of PCIe
ISR 1 register(RD0074848h). Only one set should be used, while
another set should be masked.
The second set is more advanced, the Legacy INT_X status bit is
asserted once Assert_INTX message is received, and de-asserted after
Deassert_INTX message is received, which provides alternate way
besides of the assert/deassert interrupt pairs in PCIe ISR 0 register.
Change-Id: Idef2eb474a094754195a031ad580caa8a88f046d
Signed-off-by: Victor Gu <xigu@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38024
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Evan Wang <xswang@marvell.com>
---
drivers/pci/host/pci-aardvark.c | 29 ++++++++++++++++++-----------
1 file changed, 18 insertions(+), 11 deletions(-)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 072bc70e900c..10154dcf219b 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -103,7 +103,8 @@
#define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
#define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
#define PCIE_ISR1_FLUSH BIT(5)
-#define PCIE_ISR1_ALL_MASK GENMASK(5, 4)
+#define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val))
+#define PCIE_ISR1_ALL_MASK GENMASK(11, 4)
#define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
#define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
#define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
@@ -612,9 +613,9 @@ static void advk_pcie_irq_mask(struct irq_data *d)
irq_hw_number_t hwirq = irqd_to_hwirq(d);
u32 mask;
- mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
- mask |= PCIE_ISR0_INTX_ASSERT(hwirq);
- advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
+ mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
+ mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
+ advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
}
static void advk_pcie_irq_unmask(struct irq_data *d)
@@ -623,9 +624,9 @@ static void advk_pcie_irq_unmask(struct irq_data *d)
irq_hw_number_t hwirq = irqd_to_hwirq(d);
u32 mask;
- mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
- mask &= ~PCIE_ISR0_INTX_ASSERT(hwirq);
- advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
+ mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
+ mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
+ advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
}
static int advk_pcie_irq_map(struct irq_domain *h,
@@ -769,14 +770,20 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie)
static void advk_pcie_handle_int(struct advk_pcie *pcie)
{
u32 val, mask, status;
+ u32 val2, mask2, status2;
int i, virq;
val = advk_readl(pcie, PCIE_ISR0_REG);
mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
status = val & ((~mask) & PCIE_ISR0_ALL_MASK);
- if (!status) {
+ val2 = advk_readl(pcie, PCIE_ISR1_REG);
+ mask2 = advk_readl(pcie, PCIE_ISR1_MASK_REG);
+ status2 = val2 & ((~mask2) & PCIE_ISR1_ALL_MASK);
+
+ if (!status && !status2) {
advk_writel(pcie, val, PCIE_ISR0_REG);
+ advk_writel(pcie, val2, PCIE_ISR1_REG);
return;
}
@@ -786,11 +793,11 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie)
/* Process legacy interrupts */
for (i = 0; i < LEGACY_IRQ_NUM; i++) {
- if (!(status & PCIE_ISR0_INTX_ASSERT(i)))
+ if (!(status2 & PCIE_ISR1_INTX_ASSERT(i)))
continue;
- advk_writel(pcie, PCIE_ISR0_INTX_ASSERT(i),
- PCIE_ISR0_REG);
+ advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
+ PCIE_ISR1_REG);
virq = irq_find_mapping(pcie->irq_domain, i);
generic_handle_irq(virq);
--
2.13.3

105
patch/kernel/mvebu64-next/0010-pci-aardvard-set-host-and-device-to-the-same-MAX-pay.patch Normal file
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@ -0,0 +1,105 @@
From dda187271721fbc30329d56fd68034c54e304a44 Mon Sep 17 00:00:00 2001
From: Victor Gu <xigu@marvell.com>
Date: Fri, 24 Mar 2017 20:52:30 +0800
Subject: [PATCH 10/11] pci: aardvard: set host and device to the same MAX
payload size
Since the Aardvard does not implement PCIe root bus, the Linux PCIe
framework will not align the MAX payload size between host and device
for it.
This patch sets host and device to the same MAX payload size in Aardvard
PCIe driver.
Change-Id: I3979397b3af98911c067f7ad384922aa3f05497f
Signed-off-by: Victor Gu <xigu@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/37927
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Evan Wang <xswang@marvell.com>
---
drivers/pci/host/pci-aardvark.c | 56 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 10154dcf219b..0407c8cb89fb 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -32,6 +32,7 @@
#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
+#define PCIE_CORE_MPS_UNIT_BYTE 128
#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
#define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
#define PCIE_CORE_LINK_TRAINING BIT(5)
@@ -886,6 +887,58 @@ static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
return err;
}
+static int advk_pcie_find_smpss(struct pci_dev *dev, void *data)
+{
+ u8 *smpss = data;
+
+ if (!dev)
+ return 0;
+
+ if (!pci_is_pcie(dev))
+ return 0;
+
+ if (*smpss > dev->pcie_mpss)
+ *smpss = dev->pcie_mpss;
+
+ return 0;
+}
+
+static int advk_pcie_bus_configure_mps(struct pci_dev *dev, void *data)
+{
+ int mps;
+
+ if (!dev)
+ return 0;
+
+ if (!pci_is_pcie(dev))
+ return 0;
+
+ mps = PCIE_CORE_MPS_UNIT_BYTE << *(u8 *)data;
+ pcie_set_mps(dev, mps);
+
+ return 0;
+}
+
+static void advk_pcie_configure_mps(struct pci_bus *bus, struct advk_pcie *pcie)
+{
+ u8 smpss = PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ;
+ u32 reg;
+
+ /* Find the minimal supported MAX payload size */
+ advk_pcie_find_smpss(bus->self, &smpss);
+ pci_walk_bus(bus, advk_pcie_find_smpss, &smpss);
+
+ /* Configure RC MAX payload size */
+ reg = advk_readl(pcie, PCIE_CORE_DEV_CTRL_STATS_REG);
+ reg &= ~PCI_EXP_DEVCTL_PAYLOAD;
+ reg |= smpss << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT;
+ advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
+
+ /* Configure device MAX payload size */
+ advk_pcie_bus_configure_mps(bus->self, &smpss);
+ pci_walk_bus(bus, advk_pcie_bus_configure_mps, &smpss);
+}
+
static int advk_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -948,6 +1001,9 @@ static int advk_pcie_probe(struct platform_device *pdev)
list_for_each_entry(child, &bus->children, node)
pcie_bus_configure_settings(child);
+ /* Configure the MAX pay load size */
+ advk_pcie_configure_mps(bus, pcie);
+
pci_bus_add_devices(bus);
return 0;
}
--
2.13.3

44
patch/kernel/mvebu64-next/0011-fix-pcie-aardvark-correct-the-default-MAX-payload-si.patch Normal file
View file

@ -0,0 +1,44 @@
From 100881d53b53c3c6691a3f3b4ddfc88d738c753b Mon Sep 17 00:00:00 2001
From: Victor Gu <xigu@marvell.com>
Date: Fri, 24 Mar 2017 20:41:55 +0800
Subject: [PATCH 11/11] fix: pcie: aardvark: correct the default MAX payload
size
The previous PCIe MAX payload field is set to 7 which is undefined
value according to functional specification.
The default PICe host controller MAX payload size should be
set to 512 bytes according to specification.
Change-Id: I8fa4868ad251f2582d58ed588e570c43aa8b24b9
Signed-off-by: Victor Gu <xigu@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/37926
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Evan Wang <xswang@marvell.com>
---
drivers/pci/host/pci-aardvark.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 0407c8cb89fb..cac1558b8d3b 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -30,6 +30,7 @@
#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
+#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2
#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
#define PCIE_CORE_MPS_UNIT_BYTE 128
@@ -300,7 +301,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
/* Set PCIe Device Control and Status 1 PF0 register */
reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
- (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
+ (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
--
2.13.3

11
patch/kernel/mvebu64-next/bash_to_afterinstall.patch Normal file
View file

@ -0,0 +1,11 @@
--- a/scripts/package/builddeb
+++ b/scripts/package/builddeb
@@ -218,7 +218,7 @@
for script in postinst postrm preinst prerm ; do
mkdir -p "$tmpdir$debhookdir/$script.d"
cat <<EOF > "$tmpdir/DEBIAN/$script"
-#!/bin/sh
+#!/bin/bash
set -e

84
patch/kernel/mvebu64-next/packaging-4.x-with-postinstall-scripts-espressobin.patch → patch/kernel/mvebu64-next/packaging-4.x-NEXT-with-postinstall-scripts.patch
View file

@ -1,5 +1,5 @@
diff --git a/scripts/package/builddeb b/scripts/package/builddeb
index 3c575cd..fafbd4a 100755
index aad67000..b4f574e7 100755
--- a/scripts/package/builddeb
+++ b/scripts/package/builddeb
@@ -29,6 +29,28 @@ create_package() {
@ -60,20 +60,7 @@ index 3c575cd..fafbd4a 100755
mkdir -m 755 -p "$tmpdir/DEBIAN"
mkdir -p "$tmpdir/lib" "$tmpdir/boot"
mkdir -p "$fwdir/lib/firmware/$version/"
@@ -145,9 +171,10 @@ else
fi
# Not all arches include the boot path in KBUILD_IMAGE
if [ -e $KBUILD_IMAGE ]; then
- cp $KBUILD_IMAGE "$tmpdir/$installed_image_path"
+ #Forcing KBUILD_MAGE reference to Image instead of zImage.. Armbian LINUX_KERNEL_TYPE=Image not being honored
+ cp Image "$tmpdir/$installed_image_path"
else
- cp arch/$ARCH/boot/$KBUILD_IMAGE "$tmpdir/$installed_image_path"
+ cp arch/$ARCH/boot/Image "$tmpdir/$installed_image_path"
fi
if grep -q "^CONFIG_OF=y" $KCONFIG_CONFIG ; then
@@ -185,6 +212,11 @@ if grep -q '^CONFIG_MODULES=y' $KCONFIG_CONFIG ; then
@@ -180,6 +206,11 @@ if grep -q '^CONFIG_MODULES=y' $KCONFIG_CONFIG ; then
fi
fi
@ -85,25 +72,7 @@ index 3c575cd..fafbd4a 100755
if [ "$ARCH" != "um" ]; then
$MAKE headers_check KBUILD_SRC=
$MAKE headers_install KBUILD_SRC= INSTALL_HDR_PATH="$libc_headers_dir/usr"
@@ -204,14 +236,16 @@ fi
for script in postinst postrm preinst prerm ; do
mkdir -p "$tmpdir$debhookdir/$script.d"
cat <<EOF > "$tmpdir/DEBIAN/$script"
-#!/bin/sh
+#!/bin/bash
set -e
# Pass maintainer script parameters to hook scripts
+
export DEB_MAINT_PARAMS="\$*"
# Tell initramfs builder whether it's wanted
+
export INITRD=$want_initrd
test -d $debhookdir/$script.d && run-parts --arg="$version" --arg="/$installed_image_path" $debhookdir/$script.d
@@ -220,6 +254,58 @@ EOF
@@ -215,6 +246,55 @@ EOF
chmod 755 "$tmpdir/DEBIAN/$script"
done
@ -112,19 +81,16 @@ index 3c575cd..fafbd4a 100755
+##
+sed -e "s/set -e//g" -i $tmpdir/DEBIAN/postinst
+sed -e "s/exit 0//g" -i $tmpdir/DEBIAN/postinst
+cat >> $tmpdir/DEBIAN/postinst <<EOT
+cat >> $tmpdir/DEBIAN/postinst <<EOT
+if [ "\$(grep nand /proc/partitions)" != "" ] && [ "\$(grep mmc /proc/partitions)" = "" ]; then
+mkimage -A arm -O linux -T kernel -C gzip -a "0x40008000" -e "0x40008000" -n "Linux kernel" -d /$installed_image_path /boot/uImage > /dev/null 2>&1
+mkimage -A arm -O linux -T kernel -C none -a "0x40008000" -e "0x40008000" -n "Linux kernel" -d /$installed_image_path /boot/uImage > /dev/null 2>&1
+cp /boot/uImage /tmp/uImage
+##copy uncompressed Kernel Image w/o Uboot for espressobin--gzip compressed forced above for mkimage
+cp $installed_image_path /tmp/Image
+sync
+mountpoint -q /boot || mount /boot
+cp /tmp/uImage /boot/uImage
+cp /tmp/Image /boot/Image
+rm -f /$installed_image_path
+else
+ln -sf $(basename $installed_image_path) /boot/Image > /dev/null 2>&1 || mv /$installed_image_path /boot/Image
+ln -sf $(basename $installed_image_path) /boot/zImage > /dev/null 2>&1 || mv /$installed_image_path /boot/zImage
+fi
+touch /boot/.next
+exit 0
@ -134,7 +100,7 @@ index 3c575cd..fafbd4a 100755
+##
+sed -e "s/set -e//g" -i $tmpdir/DEBIAN/preinst
+sed -e "s/exit 0//g" -i $tmpdir/DEBIAN/preinst
+cat >> $tmpdir/DEBIAN/preinst <<EOT
+cat >> $tmpdir/DEBIAN/preinst <<EOT
+# exit if we are running chroot
+if [ "\$(stat -c %d:%i /)" != "\$(stat -c %d:%i /proc/1/root/.)" ]; then exit 0; fi
+
@ -150,45 +116,43 @@ index 3c575cd..fafbd4a 100755
+done
+
+bootfstype=\$(blkid -s TYPE -o value \$boot_partition)
+if [ "\$bootfstype" = "vfat" ]; then
+umount /boot;
+rm -f /boot/System.map* /boot/config* /boot/vmlinuz* /boot/zImage /boot/uImage /boot/Image
+if [ "\$bootfstype" = "vfat" ]; then
+umount /boot;
+rm -f /boot/System.map* /boot/config* /boot/vmlinuz* /boot/zImage /boot/uImage
+fi
+}
+mountpoint -q /boot && check_and_unmount
+EOT
+echo "exit 0" >> $tmpdir/DEBIAN/preinst
+echo "exit 0" >> $tmpdir/DEBIAN/preinst
+
# Try to determine maintainer and email values
if [ -n "$DEBEMAIL" ]; then
email=$DEBEMAIL
@@ -337,16 +423,24 @@ if grep -q '^CONFIG_GCC_PLUGINS=y' $KCONFIG_CONFIG ; then
@@ -318,6 +398,7 @@ fi
# Build kernel header package
(cd $srctree; find . -name Makefile\* -o -name Kconfig\* -o -name \*.pl) > "$objtree/debian/hdrsrcfiles"
(cd $srctree; find arch/*/include include scripts -type f) >> "$objtree/debian/hdrsrcfiles"
+(cd $srctree; find security/*/include -type f) >> "$objtree/debian/hdrsrcfiles"
(cd $srctree; find arch/$SRCARCH -name module.lds -o -name Kbuild.platforms -o -name Platform) >> "$objtree/debian/hdrsrcfiles"
(cd $srctree; find $(find arch/$SRCARCH -name include -o -name scripts -type d) -type f) >> "$objtree/debian/hdrsrcfiles"
if grep -q '^CONFIG_STACK_VALIDATION=y' $KCONFIG_CONFIG ; then
@@ -329,12 +410,15 @@ if grep -q '^CONFIG_GCC_PLUGINS=y' $KCONFIG_CONFIG ; then
fi
destdir=$kernel_headers_dir/usr/src/linux-headers-$version
mkdir -p "$destdir"
+######################## headers patch
+ZACNI=$(pwd)
+cd $destdir
+patch -p1 < /tmp/headers-debian-byteshift.patch
+cd $ZACNI
+######################## headers patch
+(cd $destdir; patch -p1 < /tmp/headers-debian-byteshift.patch)
(cd $srctree; tar -c -f - -T -) < "$objtree/debian/hdrsrcfiles" | (cd $destdir; tar -xf -)
(cd $objtree; tar -c -f - -T -) < "$objtree/debian/hdrobjfiles" | (cd $destdir; tar -xf -)
(cd $objtree; cp $KCONFIG_CONFIG $destdir/.config) # copy .config manually to be where it's expected to be
ln -sf "/usr/src/linux-headers-$version" "$kernel_headers_dir/lib/modules/$version/build"
rm -f "$objtree/debian/hdrsrcfiles" "$objtree/debian/hdrobjfiles"
+(cd "$destdir"; make M=scripts clean)
+(cd $destdir; make M=scripts clean)
+
cat <<EOF >> debian/control
Package: $kernel_headers_packagename
-Provides: linux-headers, linux-headers-2.6
+Provides: linux-headers
Architecture: any
Description: Linux kernel headers for $KERNELRELEASE on \${kernel:debarch}
This package provides kernel header files for $KERNELRELEASE on \${kernel:debarch}
@@ -372,6 +466,16 @@ fi
@@ -363,6 +447,16 @@ fi
cat <<EOF >> debian/control
@ -205,7 +169,7 @@ index 3c575cd..fafbd4a 100755
Package: $libc_headers_packagename
Section: devel
Provides: linux-kernel-headers
@@ -383,7 +487,7 @@ EOF
@@ -374,7 +468,7 @@ EOF
if [ "$ARCH" != "um" ]; then
create_package "$kernel_headers_packagename" "$kernel_headers_dir"

72
patch/kernel/mvebu64-next/unlock_atheros_regulatory_restrictions.patch Normal file
View file

@ -0,0 +1,72 @@
diff --git a/drivers/net/wireless/ath/regd.c b/drivers/net/wireless/ath/regd.c
index ccc4c71..71a4d00 100644
--- a/drivers/net/wireless/ath/regd.c
+++ b/drivers/net/wireless/ath/regd.c
@@ -49,12 +49,9 @@ static int __ath_regd_init(struct ath_regulatory *reg);
#define ATH9K_5GHZ_5725_5850 REG_RULE(5725-10, 5850+10, 40, 0, 30,\
NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
-#define ATH9K_2GHZ_ALL ATH9K_2GHZ_CH01_11, \
- ATH9K_2GHZ_CH12_13, \
- ATH9K_2GHZ_CH14
+#define ATH9K_2GHZ_ALL REG_RULE(2400, 2483, 40, 0, 30, 0)
-#define ATH9K_5GHZ_ALL ATH9K_5GHZ_5150_5350, \
- ATH9K_5GHZ_5470_5850
+#define ATH9K_5GHZ_ALL REG_RULE(5140, 5860, 40, 0, 30, 0)
/* This one skips what we call "mid band" */
#define ATH9K_5GHZ_NO_MIDBAND ATH9K_5GHZ_5150_5350, \
@@ -76,9 +73,8 @@ static const struct ieee80211_regdomain ath_world_regdom_63_65 = {
.n_reg_rules = 4,
.alpha2 = "99",
.reg_rules = {
- ATH9K_2GHZ_CH01_11,
- ATH9K_2GHZ_CH12_13,
- ATH9K_5GHZ_NO_MIDBAND,
+ ATH9K_2GHZ_ALL,
+ ATH9K_5GHZ_ALL,
}
};
@@ -87,8 +83,8 @@ static const struct ieee80211_regdomain ath_world_regdom_64 = {
.n_reg_rules = 3,
.alpha2 = "99",
.reg_rules = {
- ATH9K_2GHZ_CH01_11,
- ATH9K_5GHZ_NO_MIDBAND,
+ ATH9K_2GHZ_ALL,
+ ATH9K_5GHZ_ALL,
}
};
@@ -97,7 +93,7 @@ static const struct ieee80211_regdomain ath_world_regdom_66_69 = {
.n_reg_rules = 3,
.alpha2 = "99",
.reg_rules = {
- ATH9K_2GHZ_CH01_11,
+ ATH9K_2GHZ_ALL,
ATH9K_5GHZ_ALL,
}
};
@@ -107,8 +103,7 @@ static const struct ieee80211_regdomain ath_world_regdom_67_68_6A_6C = {
.n_reg_rules = 4,
.alpha2 = "99",
.reg_rules = {
- ATH9K_2GHZ_CH01_11,
- ATH9K_2GHZ_CH12_13,
+ ATH9K_2GHZ_ALL,
ATH9K_5GHZ_ALL,
}
};
@@ -253,9 +253,7 @@ static bool ath_is_radar_freq(u16 center_freq,
struct ath_regulatory *reg)
{
- if (reg->country_code == CTRY_INDIA)
- return (center_freq >= 5500 && center_freq <= 5700);
- return (center_freq >= 5260 && center_freq <= 5700);
+ return false;
}
static void ath_force_clear_no_ir_chan(struct wiphy *wiphy,