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H3 Rev A impedance calibration fix
This commit is contained in:
ThomasKaiser
parent
3baf7fc2aa
commit
b62ed03b96
3 changed files with 213 additions and 1 deletions
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@ -19,7 +19,7 @@ case $BRANCH in
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KERNELSOURCE='https://github.com/apritzel/linux.git'
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KERNELBRANCH='branch:a64-v5'
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KERNELDIR='linux-pine64-dev'
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GOVERNOR=ondemand
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GOVERNOR=schedutil
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UBOOT_FILES="u-boot-with-spl.bin"
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;;
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esac
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106
patch/u-boot/u-boot-default/fix-h3-rev3-dram-calibration.patch
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106
patch/u-boot/u-boot-default/fix-h3-rev3-dram-calibration.patch
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@ -0,0 +1,106 @@
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From f0b3ecefb7241c565b6400d2da11fc5c49b570ff Mon Sep 17 00:00:00 2001
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From: Jens Kuske <jenskuske@gmail.com>
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Date: Wed, 21 Sep 2016 16:08:43 +0200
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Subject: [PATCH] sunxi: Fix H3 DRAM impedance calibration on rev. A chips
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H3 seems to have a silicon bug breaking the impedance calibration.
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This is currently worked around in software by multiple steps
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combining the results to replace the wrong values.
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Revision A chips need a different workaround, which is present in
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the vendor bootloader too, but got overlooked in lack of
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information and affected boards till now.
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This commit adds a simplified version without correction factor,
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which would be 1.00 for all known boards anyway.
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Signed-off-by: Jens Kuske <jenskuske@gmail.com>
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---
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arch/arm/mach-sunxi/dram_sun8i_h3.c | 67 +++++++++++++++++++++++++------------
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1 file changed, 46 insertions(+), 21 deletions(-)
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diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c b/arch/arm/mach-sunxi/dram_sun8i_h3.c
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index 2020d75..b23a46c 100644
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--- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
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+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
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@@ -217,35 +217,60 @@ static void mctl_zq_calibration(struct dram_para *para)
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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- int i;
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- u16 zq_val[6];
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- u8 val;
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+ if ((readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) == 0 &&
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+ (readl(SUNXI_SRAMC_BASE + 0xf0) & 0x1) == 0)
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+ {
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+ u32 reg_val;
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- writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
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-
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- for (i = 0; i < 6; i++) {
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- u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
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-
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- writel((zq << 20) | (zq << 16) | (zq << 12) |
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- (zq << 8) | (zq << 4) | (zq << 0),
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- &mctl_ctl->zqcr);
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+ clrsetbits_le32(&mctl_ctl->zqcr, 0xffff,
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+ CONFIG_DRAM_ZQ & 0xffff);
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writel(PIR_CLRSR, &mctl_ctl->pir);
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mctl_phy_init(PIR_ZCAL);
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- zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
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- writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
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-
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- writel(PIR_CLRSR, &mctl_ctl->pir);
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- mctl_phy_init(PIR_ZCAL);
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+ reg_val = readl(&mctl_ctl->zqdr[0]);
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+ reg_val &= (0x1f << 16) | (0x1f << 0);
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+ reg_val |= reg_val << 8;
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+ writel(reg_val, &mctl_ctl->zqdr[0]);
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- val = readl(&mctl_ctl->zqdr[0]) >> 24;
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- zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
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+ reg_val = readl(&mctl_ctl->zqdr[1]);
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+ reg_val &= (0x1f << 16) | (0x1f << 0);
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+ reg_val |= reg_val << 8;
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+ writel(reg_val, &mctl_ctl->zqdr[1]);
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+ writel(reg_val, &mctl_ctl->zqdr[2]);
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}
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+ else
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+ {
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+ int i;
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+ u16 zq_val[6];
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+ u8 val;
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+
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+ writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
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+
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+ for (i = 0; i < 6; i++) {
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+ u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
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- writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
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- writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
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- writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
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+ writel((zq << 20) | (zq << 16) | (zq << 12) |
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+ (zq << 8) | (zq << 4) | (zq << 0),
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+ &mctl_ctl->zqcr);
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+
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+ writel(PIR_CLRSR, &mctl_ctl->pir);
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+ mctl_phy_init(PIR_ZCAL);
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+
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+ zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
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+ writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
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+
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+ writel(PIR_CLRSR, &mctl_ctl->pir);
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+ mctl_phy_init(PIR_ZCAL);
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+
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+ val = readl(&mctl_ctl->zqdr[0]) >> 24;
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+ zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
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+ }
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+
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+ writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
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+ writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
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+ writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
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+ }
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}
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static void mctl_set_cr(struct dram_para *para)
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106
patch/u-boot/u-boot-dev/fix-h3-rev3-dram-calibration.patch
Normal file
106
patch/u-boot/u-boot-dev/fix-h3-rev3-dram-calibration.patch
Normal file
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@ -0,0 +1,106 @@
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From f0b3ecefb7241c565b6400d2da11fc5c49b570ff Mon Sep 17 00:00:00 2001
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From: Jens Kuske <jenskuske@gmail.com>
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Date: Wed, 21 Sep 2016 16:08:43 +0200
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Subject: [PATCH] sunxi: Fix H3 DRAM impedance calibration on rev. A chips
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H3 seems to have a silicon bug breaking the impedance calibration.
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This is currently worked around in software by multiple steps
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combining the results to replace the wrong values.
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Revision A chips need a different workaround, which is present in
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the vendor bootloader too, but got overlooked in lack of
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information and affected boards till now.
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This commit adds a simplified version without correction factor,
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which would be 1.00 for all known boards anyway.
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Signed-off-by: Jens Kuske <jenskuske@gmail.com>
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---
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arch/arm/mach-sunxi/dram_sun8i_h3.c | 67 +++++++++++++++++++++++++------------
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1 file changed, 46 insertions(+), 21 deletions(-)
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diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c b/arch/arm/mach-sunxi/dram_sun8i_h3.c
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index 2020d75..b23a46c 100644
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--- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
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+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
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@@ -217,35 +217,60 @@ static void mctl_zq_calibration(struct dram_para *para)
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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- int i;
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- u16 zq_val[6];
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- u8 val;
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+ if ((readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) == 0 &&
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+ (readl(SUNXI_SRAMC_BASE + 0xf0) & 0x1) == 0)
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+ {
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+ u32 reg_val;
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- writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
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-
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- for (i = 0; i < 6; i++) {
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- u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
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-
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- writel((zq << 20) | (zq << 16) | (zq << 12) |
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- (zq << 8) | (zq << 4) | (zq << 0),
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- &mctl_ctl->zqcr);
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+ clrsetbits_le32(&mctl_ctl->zqcr, 0xffff,
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+ CONFIG_DRAM_ZQ & 0xffff);
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writel(PIR_CLRSR, &mctl_ctl->pir);
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mctl_phy_init(PIR_ZCAL);
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- zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
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- writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
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-
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- writel(PIR_CLRSR, &mctl_ctl->pir);
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- mctl_phy_init(PIR_ZCAL);
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+ reg_val = readl(&mctl_ctl->zqdr[0]);
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+ reg_val &= (0x1f << 16) | (0x1f << 0);
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+ reg_val |= reg_val << 8;
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+ writel(reg_val, &mctl_ctl->zqdr[0]);
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- val = readl(&mctl_ctl->zqdr[0]) >> 24;
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- zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
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+ reg_val = readl(&mctl_ctl->zqdr[1]);
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+ reg_val &= (0x1f << 16) | (0x1f << 0);
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+ reg_val |= reg_val << 8;
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+ writel(reg_val, &mctl_ctl->zqdr[1]);
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+ writel(reg_val, &mctl_ctl->zqdr[2]);
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}
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+ else
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+ {
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+ int i;
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+ u16 zq_val[6];
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+ u8 val;
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+
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+ writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
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+
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+ for (i = 0; i < 6; i++) {
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+ u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
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- writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
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- writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
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- writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
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+ writel((zq << 20) | (zq << 16) | (zq << 12) |
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+ (zq << 8) | (zq << 4) | (zq << 0),
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+ &mctl_ctl->zqcr);
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+
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+ writel(PIR_CLRSR, &mctl_ctl->pir);
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+ mctl_phy_init(PIR_ZCAL);
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+
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+ zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
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+ writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
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+
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+ writel(PIR_CLRSR, &mctl_ctl->pir);
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+ mctl_phy_init(PIR_ZCAL);
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+
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+ val = readl(&mctl_ctl->zqdr[0]) >> 24;
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+ zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
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+ }
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+
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+ writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
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+ writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
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+ writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
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+ }
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}
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static void mctl_set_cr(struct dram_para *para)
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